opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define EdqwS { OP_E, dqw_swap_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, stack_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   dqw_swap_mode,
 560   bnd_mode,
 561   /* 4- or 6-byte pointer operand */
 562   f_mode,
 563   const_1_mode,
 564   /* v_mode for stack-related opcodes.  */
 565   stack_v_mode,
 566   /* non-quad operand size depends on prefixes */
 567   z_mode,
 568   /* 16-byte operand */
 569   o_mode,
 570   /* registers like dq_mode, memory like b_mode.  */
 571   dqb_mode,
 572   /* registers like d_mode, memory like b_mode.  */
 573   db_mode,
 574   /* registers like d_mode, memory like w_mode.  */
 575   dw_mode,
 576   /* registers like dq_mode, memory like d_mode.  */
 577   dqd_mode,
 578   /* normal vex mode */
 579   vex_mode,
 580   /* 128bit vex mode */
 581   vex128_mode,
 582   /* 256bit vex mode */
 583   vex256_mode,
 584   /* operand size depends on the VEX.W bit.  */
 585   vex_w_dq_mode,
 586
 587   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 588   vex_vsib_d_w_dq_mode,
 589   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 590   vex_vsib_d_w_d_mode,
 591   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 592   vex_vsib_q_w_dq_mode,
 593   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 594   vex_vsib_q_w_d_mode,
 595
 596   /* scalar, ignore vector length.  */
 597   scalar_mode,
 598   /* like d_mode, ignore vector length.  */
 599   d_scalar_mode,
 600   /* like d_swap_mode, ignore vector length.  */
 601   d_scalar_swap_mode,
 602   /* like q_mode, ignore vector length.  */
 603   q_scalar_mode,
 604   /* like q_swap_mode, ignore vector length.  */
 605   q_scalar_swap_mode,
 606   /* like vex_mode, ignore vector length.  */
 607   vex_scalar_mode,
 608   /* like vex_w_dq_mode, ignore vector length.  */
 609   vex_scalar_w_dq_mode,
 610
 611   /* Static rounding.  */
 612   evex_rounding_mode,
 613   /* Supress all exceptions.  */
 614   evex_sae_mode,
 615
 616   /* Mask register operand.  */
 617   mask_mode,
 618   /* Mask register operand.  */
 619   mask_bd_mode,
 620
 621   es_reg,
 622   cs_reg,
 623   ss_reg,
 624   ds_reg,
 625   fs_reg,
 626   gs_reg,
 627
 628   eAX_reg,
 629   eCX_reg,
 630   eDX_reg,
 631   eBX_reg,
 632   eSP_reg,
 633   eBP_reg,
 634   eSI_reg,
 635   eDI_reg,
 636
 637   al_reg,
 638   cl_reg,
 639   dl_reg,
 640   bl_reg,
 641   ah_reg,
 642   ch_reg,
 643   dh_reg,
 644   bh_reg,
 645
 646   ax_reg,
 647   cx_reg,
 648   dx_reg,
 649   bx_reg,
 650   sp_reg,
 651   bp_reg,
 652   si_reg,
 653   di_reg,
 654
 655   rAX_reg,
 656   rCX_reg,
 657   rDX_reg,
 658   rBX_reg,
 659   rSP_reg,
 660   rBP_reg,
 661   rSI_reg,
 662   rDI_reg,
 663
 664   z_mode_ax_reg,
 665   indir_dx_reg
 666 };
 667
 668 enum
 669 {
 670   FLOATCODE = 1,
 671   USE_REG_TABLE,
 672   USE_MOD_TABLE,
 673   USE_RM_TABLE,
 674   USE_PREFIX_TABLE,
 675   USE_X86_64_TABLE,
 676   USE_3BYTE_TABLE,
 677   USE_XOP_8F_TABLE,
 678   USE_VEX_C4_TABLE,
 679   USE_VEX_C5_TABLE,
 680   USE_VEX_LEN_TABLE,
 681   USE_VEX_W_TABLE,
 682   USE_EVEX_TABLE
 683 };
 684
 685 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 686
 687 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 688 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 689 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 690 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 691 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 692 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 693 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 694 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 695 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 696 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 697 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 698 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 699 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 700 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 701 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 702
 703 enum
 704 {
 705   REG_80 = 0,
 706   REG_81,
 707   REG_82,
 708   REG_8F,
 709   REG_C0,
 710   REG_C1,
 711   REG_C6,
 712   REG_C7,
 713   REG_D0,
 714   REG_D1,
 715   REG_D2,
 716   REG_D3,
 717   REG_F6,
 718   REG_F7,
 719   REG_FE,
 720   REG_FF,
 721   REG_0F00,
 722   REG_0F01,
 723   REG_0F0D,
 724   REG_0F18,
 725   REG_0F71,
 726   REG_0F72,
 727   REG_0F73,
 728   REG_0FA6,
 729   REG_0FA7,
 730   REG_0FAE,
 731   REG_0FBA,
 732   REG_0FC7,
 733   REG_VEX_0F71,
 734   REG_VEX_0F72,
 735   REG_VEX_0F73,
 736   REG_VEX_0FAE,
 737   REG_VEX_0F38F3,
 738   REG_XOP_LWPCB,
 739   REG_XOP_LWP,
 740   REG_XOP_TBM_01,
 741   REG_XOP_TBM_02,
 742
 743   REG_EVEX_0F71,
 744   REG_EVEX_0F72,
 745   REG_EVEX_0F73,
 746   REG_EVEX_0F38C6,
 747   REG_EVEX_0F38C7
 748 };
 749
 750 enum
 751 {
 752   MOD_8D = 0,
 753   MOD_C6_REG_7,
 754   MOD_C7_REG_7,
 755   MOD_FF_REG_3,
 756   MOD_FF_REG_5,
 757   MOD_0F01_REG_0,
 758   MOD_0F01_REG_1,
 759   MOD_0F01_REG_2,
 760   MOD_0F01_REG_3,
 761   MOD_0F01_REG_7,
 762   MOD_0F12_PREFIX_0,
 763   MOD_0F13,
 764   MOD_0F16_PREFIX_0,
 765   MOD_0F17,
 766   MOD_0F18_REG_0,
 767   MOD_0F18_REG_1,
 768   MOD_0F18_REG_2,
 769   MOD_0F18_REG_3,
 770   MOD_0F18_REG_4,
 771   MOD_0F18_REG_5,
 772   MOD_0F18_REG_6,
 773   MOD_0F18_REG_7,
 774   MOD_0F1A_PREFIX_0,
 775   MOD_0F1B_PREFIX_0,
 776   MOD_0F1B_PREFIX_1,
 777   MOD_0F24,
 778   MOD_0F26,
 779   MOD_0F2B_PREFIX_0,
 780   MOD_0F2B_PREFIX_1,
 781   MOD_0F2B_PREFIX_2,
 782   MOD_0F2B_PREFIX_3,
 783   MOD_0F51,
 784   MOD_0F71_REG_2,
 785   MOD_0F71_REG_4,
 786   MOD_0F71_REG_6,
 787   MOD_0F72_REG_2,
 788   MOD_0F72_REG_4,
 789   MOD_0F72_REG_6,
 790   MOD_0F73_REG_2,
 791   MOD_0F73_REG_3,
 792   MOD_0F73_REG_6,
 793   MOD_0F73_REG_7,
 794   MOD_0FAE_REG_0,
 795   MOD_0FAE_REG_1,
 796   MOD_0FAE_REG_2,
 797   MOD_0FAE_REG_3,
 798   MOD_0FAE_REG_4,
 799   MOD_0FAE_REG_5,
 800   MOD_0FAE_REG_6,
 801   MOD_0FAE_REG_7,
 802   MOD_0FB2,
 803   MOD_0FB4,
 804   MOD_0FB5,
 805   MOD_0FC3,
 806   MOD_0FC7_REG_3,
 807   MOD_0FC7_REG_4,
 808   MOD_0FC7_REG_5,
 809   MOD_0FC7_REG_6,
 810   MOD_0FC7_REG_7,
 811   MOD_0FD7,
 812   MOD_0FE7_PREFIX_2,
 813   MOD_0FF0_PREFIX_3,
 814   MOD_0F382A_PREFIX_2,
 815   MOD_62_32BIT,
 816   MOD_C4_32BIT,
 817   MOD_C5_32BIT,
 818   MOD_VEX_0F12_PREFIX_0,
 819   MOD_VEX_0F13,
 820   MOD_VEX_0F16_PREFIX_0,
 821   MOD_VEX_0F17,
 822   MOD_VEX_0F2B,
 823   MOD_VEX_0F50,
 824   MOD_VEX_0F71_REG_2,
 825   MOD_VEX_0F71_REG_4,
 826   MOD_VEX_0F71_REG_6,
 827   MOD_VEX_0F72_REG_2,
 828   MOD_VEX_0F72_REG_4,
 829   MOD_VEX_0F72_REG_6,
 830   MOD_VEX_0F73_REG_2,
 831   MOD_VEX_0F73_REG_3,
 832   MOD_VEX_0F73_REG_6,
 833   MOD_VEX_0F73_REG_7,
 834   MOD_VEX_0FAE_REG_2,
 835   MOD_VEX_0FAE_REG_3,
 836   MOD_VEX_0FD7_PREFIX_2,
 837   MOD_VEX_0FE7_PREFIX_2,
 838   MOD_VEX_0FF0_PREFIX_3,
 839   MOD_VEX_0F381A_PREFIX_2,
 840   MOD_VEX_0F382A_PREFIX_2,
 841   MOD_VEX_0F382C_PREFIX_2,
 842   MOD_VEX_0F382D_PREFIX_2,
 843   MOD_VEX_0F382E_PREFIX_2,
 844   MOD_VEX_0F382F_PREFIX_2,
 845   MOD_VEX_0F385A_PREFIX_2,
 846   MOD_VEX_0F388C_PREFIX_2,
 847   MOD_VEX_0F388E_PREFIX_2,
 848
 849   MOD_EVEX_0F10_PREFIX_1,
 850   MOD_EVEX_0F10_PREFIX_3,
 851   MOD_EVEX_0F11_PREFIX_1,
 852   MOD_EVEX_0F11_PREFIX_3,
 853   MOD_EVEX_0F12_PREFIX_0,
 854   MOD_EVEX_0F16_PREFIX_0,
 855   MOD_EVEX_0F38C6_REG_1,
 856   MOD_EVEX_0F38C6_REG_2,
 857   MOD_EVEX_0F38C6_REG_5,
 858   MOD_EVEX_0F38C6_REG_6,
 859   MOD_EVEX_0F38C7_REG_1,
 860   MOD_EVEX_0F38C7_REG_2,
 861   MOD_EVEX_0F38C7_REG_5,
 862   MOD_EVEX_0F38C7_REG_6
 863 };
 864
 865 enum
 866 {
 867   RM_C6_REG_7 = 0,
 868   RM_C7_REG_7,
 869   RM_0F01_REG_0,
 870   RM_0F01_REG_1,
 871   RM_0F01_REG_2,
 872   RM_0F01_REG_3,
 873   RM_0F01_REG_7,
 874   RM_0FAE_REG_5,
 875   RM_0FAE_REG_6,
 876   RM_0FAE_REG_7
 877 };
 878
 879 enum
 880 {
 881   PREFIX_90 = 0,
 882   PREFIX_0F10,
 883   PREFIX_0F11,
 884   PREFIX_0F12,
 885   PREFIX_0F16,
 886   PREFIX_0F1A,
 887   PREFIX_0F1B,
 888   PREFIX_0F2A,
 889   PREFIX_0F2B,
 890   PREFIX_0F2C,
 891   PREFIX_0F2D,
 892   PREFIX_0F2E,
 893   PREFIX_0F2F,
 894   PREFIX_0F51,
 895   PREFIX_0F52,
 896   PREFIX_0F53,
 897   PREFIX_0F58,
 898   PREFIX_0F59,
 899   PREFIX_0F5A,
 900   PREFIX_0F5B,
 901   PREFIX_0F5C,
 902   PREFIX_0F5D,
 903   PREFIX_0F5E,
 904   PREFIX_0F5F,
 905   PREFIX_0F60,
 906   PREFIX_0F61,
 907   PREFIX_0F62,
 908   PREFIX_0F6C,
 909   PREFIX_0F6D,
 910   PREFIX_0F6F,
 911   PREFIX_0F70,
 912   PREFIX_0F73_REG_3,
 913   PREFIX_0F73_REG_7,
 914   PREFIX_0F78,
 915   PREFIX_0F79,
 916   PREFIX_0F7C,
 917   PREFIX_0F7D,
 918   PREFIX_0F7E,
 919   PREFIX_0F7F,
 920   PREFIX_0FAE_REG_0,
 921   PREFIX_0FAE_REG_1,
 922   PREFIX_0FAE_REG_2,
 923   PREFIX_0FAE_REG_3,
 924   PREFIX_0FAE_REG_6,
 925   PREFIX_0FAE_REG_7,
 926   PREFIX_RM_0_0FAE_REG_7,
 927   PREFIX_0FB8,
 928   PREFIX_0FBC,
 929   PREFIX_0FBD,
 930   PREFIX_0FC2,
 931   PREFIX_MOD_0_0FC3,
 932   PREFIX_MOD_0_0FC7_REG_6,
 933   PREFIX_MOD_3_0FC7_REG_6,
 934   PREFIX_MOD_3_0FC7_REG_7,
 935   PREFIX_0FD0,
 936   PREFIX_0FD6,
 937   PREFIX_0FE6,
 938   PREFIX_0FE7,
 939   PREFIX_0FF0,
 940   PREFIX_0FF7,
 941   PREFIX_0F3810,
 942   PREFIX_0F3814,
 943   PREFIX_0F3815,
 944   PREFIX_0F3817,
 945   PREFIX_0F3820,
 946   PREFIX_0F3821,
 947   PREFIX_0F3822,
 948   PREFIX_0F3823,
 949   PREFIX_0F3824,
 950   PREFIX_0F3825,
 951   PREFIX_0F3828,
 952   PREFIX_0F3829,
 953   PREFIX_0F382A,
 954   PREFIX_0F382B,
 955   PREFIX_0F3830,
 956   PREFIX_0F3831,
 957   PREFIX_0F3832,
 958   PREFIX_0F3833,
 959   PREFIX_0F3834,
 960   PREFIX_0F3835,
 961   PREFIX_0F3837,
 962   PREFIX_0F3838,
 963   PREFIX_0F3839,
 964   PREFIX_0F383A,
 965   PREFIX_0F383B,
 966   PREFIX_0F383C,
 967   PREFIX_0F383D,
 968   PREFIX_0F383E,
 969   PREFIX_0F383F,
 970   PREFIX_0F3840,
 971   PREFIX_0F3841,
 972   PREFIX_0F3880,
 973   PREFIX_0F3881,
 974   PREFIX_0F3882,
 975   PREFIX_0F38C8,
 976   PREFIX_0F38C9,
 977   PREFIX_0F38CA,
 978   PREFIX_0F38CB,
 979   PREFIX_0F38CC,
 980   PREFIX_0F38CD,
 981   PREFIX_0F38DB,
 982   PREFIX_0F38DC,
 983   PREFIX_0F38DD,
 984   PREFIX_0F38DE,
 985   PREFIX_0F38DF,
 986   PREFIX_0F38F0,
 987   PREFIX_0F38F1,
 988   PREFIX_0F38F6,
 989   PREFIX_0F3A08,
 990   PREFIX_0F3A09,
 991   PREFIX_0F3A0A,
 992   PREFIX_0F3A0B,
 993   PREFIX_0F3A0C,
 994   PREFIX_0F3A0D,
 995   PREFIX_0F3A0E,
 996   PREFIX_0F3A14,
 997   PREFIX_0F3A15,
 998   PREFIX_0F3A16,
 999   PREFIX_0F3A17,
1000   PREFIX_0F3A20,
1001   PREFIX_0F3A21,
1002   PREFIX_0F3A22,
1003   PREFIX_0F3A40,
1004   PREFIX_0F3A41,
1005   PREFIX_0F3A42,
1006   PREFIX_0F3A44,
1007   PREFIX_0F3A60,
1008   PREFIX_0F3A61,
1009   PREFIX_0F3A62,
1010   PREFIX_0F3A63,
1011   PREFIX_0F3ACC,
1012   PREFIX_0F3ADF,
1013   PREFIX_VEX_0F10,
1014   PREFIX_VEX_0F11,
1015   PREFIX_VEX_0F12,
1016   PREFIX_VEX_0F16,
1017   PREFIX_VEX_0F2A,
1018   PREFIX_VEX_0F2C,
1019   PREFIX_VEX_0F2D,
1020   PREFIX_VEX_0F2E,
1021   PREFIX_VEX_0F2F,
1022   PREFIX_VEX_0F41,
1023   PREFIX_VEX_0F42,
1024   PREFIX_VEX_0F44,
1025   PREFIX_VEX_0F45,
1026   PREFIX_VEX_0F46,
1027   PREFIX_VEX_0F47,
1028   PREFIX_VEX_0F4A,
1029   PREFIX_VEX_0F4B,
1030   PREFIX_VEX_0F51,
1031   PREFIX_VEX_0F52,
1032   PREFIX_VEX_0F53,
1033   PREFIX_VEX_0F58,
1034   PREFIX_VEX_0F59,
1035   PREFIX_VEX_0F5A,
1036   PREFIX_VEX_0F5B,
1037   PREFIX_VEX_0F5C,
1038   PREFIX_VEX_0F5D,
1039   PREFIX_VEX_0F5E,
1040   PREFIX_VEX_0F5F,
1041   PREFIX_VEX_0F60,
1042   PREFIX_VEX_0F61,
1043   PREFIX_VEX_0F62,
1044   PREFIX_VEX_0F63,
1045   PREFIX_VEX_0F64,
1046   PREFIX_VEX_0F65,
1047   PREFIX_VEX_0F66,
1048   PREFIX_VEX_0F67,
1049   PREFIX_VEX_0F68,
1050   PREFIX_VEX_0F69,
1051   PREFIX_VEX_0F6A,
1052   PREFIX_VEX_0F6B,
1053   PREFIX_VEX_0F6C,
1054   PREFIX_VEX_0F6D,
1055   PREFIX_VEX_0F6E,
1056   PREFIX_VEX_0F6F,
1057   PREFIX_VEX_0F70,
1058   PREFIX_VEX_0F71_REG_2,
1059   PREFIX_VEX_0F71_REG_4,
1060   PREFIX_VEX_0F71_REG_6,
1061   PREFIX_VEX_0F72_REG_2,
1062   PREFIX_VEX_0F72_REG_4,
1063   PREFIX_VEX_0F72_REG_6,
1064   PREFIX_VEX_0F73_REG_2,
1065   PREFIX_VEX_0F73_REG_3,
1066   PREFIX_VEX_0F73_REG_6,
1067   PREFIX_VEX_0F73_REG_7,
1068   PREFIX_VEX_0F74,
1069   PREFIX_VEX_0F75,
1070   PREFIX_VEX_0F76,
1071   PREFIX_VEX_0F77,
1072   PREFIX_VEX_0F7C,
1073   PREFIX_VEX_0F7D,
1074   PREFIX_VEX_0F7E,
1075   PREFIX_VEX_0F7F,
1076   PREFIX_VEX_0F90,
1077   PREFIX_VEX_0F91,
1078   PREFIX_VEX_0F92,
1079   PREFIX_VEX_0F93,
1080   PREFIX_VEX_0F98,
1081   PREFIX_VEX_0F99,
1082   PREFIX_VEX_0FC2,
1083   PREFIX_VEX_0FC4,
1084   PREFIX_VEX_0FC5,
1085   PREFIX_VEX_0FD0,
1086   PREFIX_VEX_0FD1,
1087   PREFIX_VEX_0FD2,
1088   PREFIX_VEX_0FD3,
1089   PREFIX_VEX_0FD4,
1090   PREFIX_VEX_0FD5,
1091   PREFIX_VEX_0FD6,
1092   PREFIX_VEX_0FD7,
1093   PREFIX_VEX_0FD8,
1094   PREFIX_VEX_0FD9,
1095   PREFIX_VEX_0FDA,
1096   PREFIX_VEX_0FDB,
1097   PREFIX_VEX_0FDC,
1098   PREFIX_VEX_0FDD,
1099   PREFIX_VEX_0FDE,
1100   PREFIX_VEX_0FDF,
1101   PREFIX_VEX_0FE0,
1102   PREFIX_VEX_0FE1,
1103   PREFIX_VEX_0FE2,
1104   PREFIX_VEX_0FE3,
1105   PREFIX_VEX_0FE4,
1106   PREFIX_VEX_0FE5,
1107   PREFIX_VEX_0FE6,
1108   PREFIX_VEX_0FE7,
1109   PREFIX_VEX_0FE8,
1110   PREFIX_VEX_0FE9,
1111   PREFIX_VEX_0FEA,
1112   PREFIX_VEX_0FEB,
1113   PREFIX_VEX_0FEC,
1114   PREFIX_VEX_0FED,
1115   PREFIX_VEX_0FEE,
1116   PREFIX_VEX_0FEF,
1117   PREFIX_VEX_0FF0,
1118   PREFIX_VEX_0FF1,
1119   PREFIX_VEX_0FF2,
1120   PREFIX_VEX_0FF3,
1121   PREFIX_VEX_0FF4,
1122   PREFIX_VEX_0FF5,
1123   PREFIX_VEX_0FF6,
1124   PREFIX_VEX_0FF7,
1125   PREFIX_VEX_0FF8,
1126   PREFIX_VEX_0FF9,
1127   PREFIX_VEX_0FFA,
1128   PREFIX_VEX_0FFB,
1129   PREFIX_VEX_0FFC,
1130   PREFIX_VEX_0FFD,
1131   PREFIX_VEX_0FFE,
1132   PREFIX_VEX_0F3800,
1133   PREFIX_VEX_0F3801,
1134   PREFIX_VEX_0F3802,
1135   PREFIX_VEX_0F3803,
1136   PREFIX_VEX_0F3804,
1137   PREFIX_VEX_0F3805,
1138   PREFIX_VEX_0F3806,
1139   PREFIX_VEX_0F3807,
1140   PREFIX_VEX_0F3808,
1141   PREFIX_VEX_0F3809,
1142   PREFIX_VEX_0F380A,
1143   PREFIX_VEX_0F380B,
1144   PREFIX_VEX_0F380C,
1145   PREFIX_VEX_0F380D,
1146   PREFIX_VEX_0F380E,
1147   PREFIX_VEX_0F380F,
1148   PREFIX_VEX_0F3813,
1149   PREFIX_VEX_0F3816,
1150   PREFIX_VEX_0F3817,
1151   PREFIX_VEX_0F3818,
1152   PREFIX_VEX_0F3819,
1153   PREFIX_VEX_0F381A,
1154   PREFIX_VEX_0F381C,
1155   PREFIX_VEX_0F381D,
1156   PREFIX_VEX_0F381E,
1157   PREFIX_VEX_0F3820,
1158   PREFIX_VEX_0F3821,
1159   PREFIX_VEX_0F3822,
1160   PREFIX_VEX_0F3823,
1161   PREFIX_VEX_0F3824,
1162   PREFIX_VEX_0F3825,
1163   PREFIX_VEX_0F3828,
1164   PREFIX_VEX_0F3829,
1165   PREFIX_VEX_0F382A,
1166   PREFIX_VEX_0F382B,
1167   PREFIX_VEX_0F382C,
1168   PREFIX_VEX_0F382D,
1169   PREFIX_VEX_0F382E,
1170   PREFIX_VEX_0F382F,
1171   PREFIX_VEX_0F3830,
1172   PREFIX_VEX_0F3831,
1173   PREFIX_VEX_0F3832,
1174   PREFIX_VEX_0F3833,
1175   PREFIX_VEX_0F3834,
1176   PREFIX_VEX_0F3835,
1177   PREFIX_VEX_0F3836,
1178   PREFIX_VEX_0F3837,
1179   PREFIX_VEX_0F3838,
1180   PREFIX_VEX_0F3839,
1181   PREFIX_VEX_0F383A,
1182   PREFIX_VEX_0F383B,
1183   PREFIX_VEX_0F383C,
1184   PREFIX_VEX_0F383D,
1185   PREFIX_VEX_0F383E,
1186   PREFIX_VEX_0F383F,
1187   PREFIX_VEX_0F3840,
1188   PREFIX_VEX_0F3841,
1189   PREFIX_VEX_0F3845,
1190   PREFIX_VEX_0F3846,
1191   PREFIX_VEX_0F3847,
1192   PREFIX_VEX_0F3858,
1193   PREFIX_VEX_0F3859,
1194   PREFIX_VEX_0F385A,
1195   PREFIX_VEX_0F3878,
1196   PREFIX_VEX_0F3879,
1197   PREFIX_VEX_0F388C,
1198   PREFIX_VEX_0F388E,
1199   PREFIX_VEX_0F3890,
1200   PREFIX_VEX_0F3891,
1201   PREFIX_VEX_0F3892,
1202   PREFIX_VEX_0F3893,
1203   PREFIX_VEX_0F3896,
1204   PREFIX_VEX_0F3897,
1205   PREFIX_VEX_0F3898,
1206   PREFIX_VEX_0F3899,
1207   PREFIX_VEX_0F389A,
1208   PREFIX_VEX_0F389B,
1209   PREFIX_VEX_0F389C,
1210   PREFIX_VEX_0F389D,
1211   PREFIX_VEX_0F389E,
1212   PREFIX_VEX_0F389F,
1213   PREFIX_VEX_0F38A6,
1214   PREFIX_VEX_0F38A7,
1215   PREFIX_VEX_0F38A8,
1216   PREFIX_VEX_0F38A9,
1217   PREFIX_VEX_0F38AA,
1218   PREFIX_VEX_0F38AB,
1219   PREFIX_VEX_0F38AC,
1220   PREFIX_VEX_0F38AD,
1221   PREFIX_VEX_0F38AE,
1222   PREFIX_VEX_0F38AF,
1223   PREFIX_VEX_0F38B6,
1224   PREFIX_VEX_0F38B7,
1225   PREFIX_VEX_0F38B8,
1226   PREFIX_VEX_0F38B9,
1227   PREFIX_VEX_0F38BA,
1228   PREFIX_VEX_0F38BB,
1229   PREFIX_VEX_0F38BC,
1230   PREFIX_VEX_0F38BD,
1231   PREFIX_VEX_0F38BE,
1232   PREFIX_VEX_0F38BF,
1233   PREFIX_VEX_0F38DB,
1234   PREFIX_VEX_0F38DC,
1235   PREFIX_VEX_0F38DD,
1236   PREFIX_VEX_0F38DE,
1237   PREFIX_VEX_0F38DF,
1238   PREFIX_VEX_0F38F2,
1239   PREFIX_VEX_0F38F3_REG_1,
1240   PREFIX_VEX_0F38F3_REG_2,
1241   PREFIX_VEX_0F38F3_REG_3,
1242   PREFIX_VEX_0F38F5,
1243   PREFIX_VEX_0F38F6,
1244   PREFIX_VEX_0F38F7,
1245   PREFIX_VEX_0F3A00,
1246   PREFIX_VEX_0F3A01,
1247   PREFIX_VEX_0F3A02,
1248   PREFIX_VEX_0F3A04,
1249   PREFIX_VEX_0F3A05,
1250   PREFIX_VEX_0F3A06,
1251   PREFIX_VEX_0F3A08,
1252   PREFIX_VEX_0F3A09,
1253   PREFIX_VEX_0F3A0A,
1254   PREFIX_VEX_0F3A0B,
1255   PREFIX_VEX_0F3A0C,
1256   PREFIX_VEX_0F3A0D,
1257   PREFIX_VEX_0F3A0E,
1258   PREFIX_VEX_0F3A0F,
1259   PREFIX_VEX_0F3A14,
1260   PREFIX_VEX_0F3A15,
1261   PREFIX_VEX_0F3A16,
1262   PREFIX_VEX_0F3A17,
1263   PREFIX_VEX_0F3A18,
1264   PREFIX_VEX_0F3A19,
1265   PREFIX_VEX_0F3A1D,
1266   PREFIX_VEX_0F3A20,
1267   PREFIX_VEX_0F3A21,
1268   PREFIX_VEX_0F3A22,
1269   PREFIX_VEX_0F3A30,
1270   PREFIX_VEX_0F3A31,
1271   PREFIX_VEX_0F3A32,
1272   PREFIX_VEX_0F3A33,
1273   PREFIX_VEX_0F3A38,
1274   PREFIX_VEX_0F3A39,
1275   PREFIX_VEX_0F3A40,
1276   PREFIX_VEX_0F3A41,
1277   PREFIX_VEX_0F3A42,
1278   PREFIX_VEX_0F3A44,
1279   PREFIX_VEX_0F3A46,
1280   PREFIX_VEX_0F3A48,
1281   PREFIX_VEX_0F3A49,
1282   PREFIX_VEX_0F3A4A,
1283   PREFIX_VEX_0F3A4B,
1284   PREFIX_VEX_0F3A4C,
1285   PREFIX_VEX_0F3A5C,
1286   PREFIX_VEX_0F3A5D,
1287   PREFIX_VEX_0F3A5E,
1288   PREFIX_VEX_0F3A5F,
1289   PREFIX_VEX_0F3A60,
1290   PREFIX_VEX_0F3A61,
1291   PREFIX_VEX_0F3A62,
1292   PREFIX_VEX_0F3A63,
1293   PREFIX_VEX_0F3A68,
1294   PREFIX_VEX_0F3A69,
1295   PREFIX_VEX_0F3A6A,
1296   PREFIX_VEX_0F3A6B,
1297   PREFIX_VEX_0F3A6C,
1298   PREFIX_VEX_0F3A6D,
1299   PREFIX_VEX_0F3A6E,
1300   PREFIX_VEX_0F3A6F,
1301   PREFIX_VEX_0F3A78,
1302   PREFIX_VEX_0F3A79,
1303   PREFIX_VEX_0F3A7A,
1304   PREFIX_VEX_0F3A7B,
1305   PREFIX_VEX_0F3A7C,
1306   PREFIX_VEX_0F3A7D,
1307   PREFIX_VEX_0F3A7E,
1308   PREFIX_VEX_0F3A7F,
1309   PREFIX_VEX_0F3ADF,
1310   PREFIX_VEX_0F3AF0,
1311
1312   PREFIX_EVEX_0F10,
1313   PREFIX_EVEX_0F11,
1314   PREFIX_EVEX_0F12,
1315   PREFIX_EVEX_0F13,
1316   PREFIX_EVEX_0F14,
1317   PREFIX_EVEX_0F15,
1318   PREFIX_EVEX_0F16,
1319   PREFIX_EVEX_0F17,
1320   PREFIX_EVEX_0F28,
1321   PREFIX_EVEX_0F29,
1322   PREFIX_EVEX_0F2A,
1323   PREFIX_EVEX_0F2B,
1324   PREFIX_EVEX_0F2C,
1325   PREFIX_EVEX_0F2D,
1326   PREFIX_EVEX_0F2E,
1327   PREFIX_EVEX_0F2F,
1328   PREFIX_EVEX_0F51,
1329   PREFIX_EVEX_0F54,
1330   PREFIX_EVEX_0F55,
1331   PREFIX_EVEX_0F56,
1332   PREFIX_EVEX_0F57,
1333   PREFIX_EVEX_0F58,
1334   PREFIX_EVEX_0F59,
1335   PREFIX_EVEX_0F5A,
1336   PREFIX_EVEX_0F5B,
1337   PREFIX_EVEX_0F5C,
1338   PREFIX_EVEX_0F5D,
1339   PREFIX_EVEX_0F5E,
1340   PREFIX_EVEX_0F5F,
1341   PREFIX_EVEX_0F60,
1342   PREFIX_EVEX_0F61,
1343   PREFIX_EVEX_0F62,
1344   PREFIX_EVEX_0F63,
1345   PREFIX_EVEX_0F64,
1346   PREFIX_EVEX_0F65,
1347   PREFIX_EVEX_0F66,
1348   PREFIX_EVEX_0F67,
1349   PREFIX_EVEX_0F68,
1350   PREFIX_EVEX_0F69,
1351   PREFIX_EVEX_0F6A,
1352   PREFIX_EVEX_0F6B,
1353   PREFIX_EVEX_0F6C,
1354   PREFIX_EVEX_0F6D,
1355   PREFIX_EVEX_0F6E,
1356   PREFIX_EVEX_0F6F,
1357   PREFIX_EVEX_0F70,
1358   PREFIX_EVEX_0F71_REG_2,
1359   PREFIX_EVEX_0F71_REG_4,
1360   PREFIX_EVEX_0F71_REG_6,
1361   PREFIX_EVEX_0F72_REG_0,
1362   PREFIX_EVEX_0F72_REG_1,
1363   PREFIX_EVEX_0F72_REG_2,
1364   PREFIX_EVEX_0F72_REG_4,
1365   PREFIX_EVEX_0F72_REG_6,
1366   PREFIX_EVEX_0F73_REG_2,
1367   PREFIX_EVEX_0F73_REG_3,
1368   PREFIX_EVEX_0F73_REG_6,
1369   PREFIX_EVEX_0F73_REG_7,
1370   PREFIX_EVEX_0F74,
1371   PREFIX_EVEX_0F75,
1372   PREFIX_EVEX_0F76,
1373   PREFIX_EVEX_0F78,
1374   PREFIX_EVEX_0F79,
1375   PREFIX_EVEX_0F7A,
1376   PREFIX_EVEX_0F7B,
1377   PREFIX_EVEX_0F7E,
1378   PREFIX_EVEX_0F7F,
1379   PREFIX_EVEX_0FC2,
1380   PREFIX_EVEX_0FC4,
1381   PREFIX_EVEX_0FC5,
1382   PREFIX_EVEX_0FC6,
1383   PREFIX_EVEX_0FD1,
1384   PREFIX_EVEX_0FD2,
1385   PREFIX_EVEX_0FD3,
1386   PREFIX_EVEX_0FD4,
1387   PREFIX_EVEX_0FD5,
1388   PREFIX_EVEX_0FD6,
1389   PREFIX_EVEX_0FD8,
1390   PREFIX_EVEX_0FD9,
1391   PREFIX_EVEX_0FDA,
1392   PREFIX_EVEX_0FDB,
1393   PREFIX_EVEX_0FDC,
1394   PREFIX_EVEX_0FDD,
1395   PREFIX_EVEX_0FDE,
1396   PREFIX_EVEX_0FDF,
1397   PREFIX_EVEX_0FE0,
1398   PREFIX_EVEX_0FE1,
1399   PREFIX_EVEX_0FE2,
1400   PREFIX_EVEX_0FE3,
1401   PREFIX_EVEX_0FE4,
1402   PREFIX_EVEX_0FE5,
1403   PREFIX_EVEX_0FE6,
1404   PREFIX_EVEX_0FE7,
1405   PREFIX_EVEX_0FE8,
1406   PREFIX_EVEX_0FE9,
1407   PREFIX_EVEX_0FEA,
1408   PREFIX_EVEX_0FEB,
1409   PREFIX_EVEX_0FEC,
1410   PREFIX_EVEX_0FED,
1411   PREFIX_EVEX_0FEE,
1412   PREFIX_EVEX_0FEF,
1413   PREFIX_EVEX_0FF1,
1414   PREFIX_EVEX_0FF2,
1415   PREFIX_EVEX_0FF3,
1416   PREFIX_EVEX_0FF4,
1417   PREFIX_EVEX_0FF5,
1418   PREFIX_EVEX_0FF6,
1419   PREFIX_EVEX_0FF8,
1420   PREFIX_EVEX_0FF9,
1421   PREFIX_EVEX_0FFA,
1422   PREFIX_EVEX_0FFB,
1423   PREFIX_EVEX_0FFC,
1424   PREFIX_EVEX_0FFD,
1425   PREFIX_EVEX_0FFE,
1426   PREFIX_EVEX_0F3800,
1427   PREFIX_EVEX_0F3804,
1428   PREFIX_EVEX_0F380B,
1429   PREFIX_EVEX_0F380C,
1430   PREFIX_EVEX_0F380D,
1431   PREFIX_EVEX_0F3810,
1432   PREFIX_EVEX_0F3811,
1433   PREFIX_EVEX_0F3812,
1434   PREFIX_EVEX_0F3813,
1435   PREFIX_EVEX_0F3814,
1436   PREFIX_EVEX_0F3815,
1437   PREFIX_EVEX_0F3816,
1438   PREFIX_EVEX_0F3818,
1439   PREFIX_EVEX_0F3819,
1440   PREFIX_EVEX_0F381A,
1441   PREFIX_EVEX_0F381B,
1442   PREFIX_EVEX_0F381C,
1443   PREFIX_EVEX_0F381D,
1444   PREFIX_EVEX_0F381E,
1445   PREFIX_EVEX_0F381F,
1446   PREFIX_EVEX_0F3820,
1447   PREFIX_EVEX_0F3821,
1448   PREFIX_EVEX_0F3822,
1449   PREFIX_EVEX_0F3823,
1450   PREFIX_EVEX_0F3824,
1451   PREFIX_EVEX_0F3825,
1452   PREFIX_EVEX_0F3826,
1453   PREFIX_EVEX_0F3827,
1454   PREFIX_EVEX_0F3828,
1455   PREFIX_EVEX_0F3829,
1456   PREFIX_EVEX_0F382A,
1457   PREFIX_EVEX_0F382B,
1458   PREFIX_EVEX_0F382C,
1459   PREFIX_EVEX_0F382D,
1460   PREFIX_EVEX_0F3830,
1461   PREFIX_EVEX_0F3831,
1462   PREFIX_EVEX_0F3832,
1463   PREFIX_EVEX_0F3833,
1464   PREFIX_EVEX_0F3834,
1465   PREFIX_EVEX_0F3835,
1466   PREFIX_EVEX_0F3836,
1467   PREFIX_EVEX_0F3837,
1468   PREFIX_EVEX_0F3838,
1469   PREFIX_EVEX_0F3839,
1470   PREFIX_EVEX_0F383A,
1471   PREFIX_EVEX_0F383B,
1472   PREFIX_EVEX_0F383C,
1473   PREFIX_EVEX_0F383D,
1474   PREFIX_EVEX_0F383E,
1475   PREFIX_EVEX_0F383F,
1476   PREFIX_EVEX_0F3840,
1477   PREFIX_EVEX_0F3842,
1478   PREFIX_EVEX_0F3843,
1479   PREFIX_EVEX_0F3844,
1480   PREFIX_EVEX_0F3845,
1481   PREFIX_EVEX_0F3846,
1482   PREFIX_EVEX_0F3847,
1483   PREFIX_EVEX_0F384C,
1484   PREFIX_EVEX_0F384D,
1485   PREFIX_EVEX_0F384E,
1486   PREFIX_EVEX_0F384F,
1487   PREFIX_EVEX_0F3858,
1488   PREFIX_EVEX_0F3859,
1489   PREFIX_EVEX_0F385A,
1490   PREFIX_EVEX_0F385B,
1491   PREFIX_EVEX_0F3864,
1492   PREFIX_EVEX_0F3865,
1493   PREFIX_EVEX_0F3866,
1494   PREFIX_EVEX_0F3875,
1495   PREFIX_EVEX_0F3876,
1496   PREFIX_EVEX_0F3877,
1497   PREFIX_EVEX_0F3878,
1498   PREFIX_EVEX_0F3879,
1499   PREFIX_EVEX_0F387A,
1500   PREFIX_EVEX_0F387B,
1501   PREFIX_EVEX_0F387C,
1502   PREFIX_EVEX_0F387D,
1503   PREFIX_EVEX_0F387E,
1504   PREFIX_EVEX_0F387F,
1505   PREFIX_EVEX_0F3883,
1506   PREFIX_EVEX_0F3888,
1507   PREFIX_EVEX_0F3889,
1508   PREFIX_EVEX_0F388A,
1509   PREFIX_EVEX_0F388B,
1510   PREFIX_EVEX_0F388D,
1511   PREFIX_EVEX_0F3890,
1512   PREFIX_EVEX_0F3891,
1513   PREFIX_EVEX_0F3892,
1514   PREFIX_EVEX_0F3893,
1515   PREFIX_EVEX_0F3896,
1516   PREFIX_EVEX_0F3897,
1517   PREFIX_EVEX_0F3898,
1518   PREFIX_EVEX_0F3899,
1519   PREFIX_EVEX_0F389A,
1520   PREFIX_EVEX_0F389B,
1521   PREFIX_EVEX_0F389C,
1522   PREFIX_EVEX_0F389D,
1523   PREFIX_EVEX_0F389E,
1524   PREFIX_EVEX_0F389F,
1525   PREFIX_EVEX_0F38A0,
1526   PREFIX_EVEX_0F38A1,
1527   PREFIX_EVEX_0F38A2,
1528   PREFIX_EVEX_0F38A3,
1529   PREFIX_EVEX_0F38A6,
1530   PREFIX_EVEX_0F38A7,
1531   PREFIX_EVEX_0F38A8,
1532   PREFIX_EVEX_0F38A9,
1533   PREFIX_EVEX_0F38AA,
1534   PREFIX_EVEX_0F38AB,
1535   PREFIX_EVEX_0F38AC,
1536   PREFIX_EVEX_0F38AD,
1537   PREFIX_EVEX_0F38AE,
1538   PREFIX_EVEX_0F38AF,
1539   PREFIX_EVEX_0F38B4,
1540   PREFIX_EVEX_0F38B5,
1541   PREFIX_EVEX_0F38B6,
1542   PREFIX_EVEX_0F38B7,
1543   PREFIX_EVEX_0F38B8,
1544   PREFIX_EVEX_0F38B9,
1545   PREFIX_EVEX_0F38BA,
1546   PREFIX_EVEX_0F38BB,
1547   PREFIX_EVEX_0F38BC,
1548   PREFIX_EVEX_0F38BD,
1549   PREFIX_EVEX_0F38BE,
1550   PREFIX_EVEX_0F38BF,
1551   PREFIX_EVEX_0F38C4,
1552   PREFIX_EVEX_0F38C6_REG_1,
1553   PREFIX_EVEX_0F38C6_REG_2,
1554   PREFIX_EVEX_0F38C6_REG_5,
1555   PREFIX_EVEX_0F38C6_REG_6,
1556   PREFIX_EVEX_0F38C7_REG_1,
1557   PREFIX_EVEX_0F38C7_REG_2,
1558   PREFIX_EVEX_0F38C7_REG_5,
1559   PREFIX_EVEX_0F38C7_REG_6,
1560   PREFIX_EVEX_0F38C8,
1561   PREFIX_EVEX_0F38CA,
1562   PREFIX_EVEX_0F38CB,
1563   PREFIX_EVEX_0F38CC,
1564   PREFIX_EVEX_0F38CD,
1565
1566   PREFIX_EVEX_0F3A00,
1567   PREFIX_EVEX_0F3A01,
1568   PREFIX_EVEX_0F3A03,
1569   PREFIX_EVEX_0F3A04,
1570   PREFIX_EVEX_0F3A05,
1571   PREFIX_EVEX_0F3A08,
1572   PREFIX_EVEX_0F3A09,
1573   PREFIX_EVEX_0F3A0A,
1574   PREFIX_EVEX_0F3A0B,
1575   PREFIX_EVEX_0F3A0F,
1576   PREFIX_EVEX_0F3A14,
1577   PREFIX_EVEX_0F3A15,
1578   PREFIX_EVEX_0F3A16,
1579   PREFIX_EVEX_0F3A17,
1580   PREFIX_EVEX_0F3A18,
1581   PREFIX_EVEX_0F3A19,
1582   PREFIX_EVEX_0F3A1A,
1583   PREFIX_EVEX_0F3A1B,
1584   PREFIX_EVEX_0F3A1D,
1585   PREFIX_EVEX_0F3A1E,
1586   PREFIX_EVEX_0F3A1F,
1587   PREFIX_EVEX_0F3A20,
1588   PREFIX_EVEX_0F3A21,
1589   PREFIX_EVEX_0F3A22,
1590   PREFIX_EVEX_0F3A23,
1591   PREFIX_EVEX_0F3A25,
1592   PREFIX_EVEX_0F3A26,
1593   PREFIX_EVEX_0F3A27,
1594   PREFIX_EVEX_0F3A38,
1595   PREFIX_EVEX_0F3A39,
1596   PREFIX_EVEX_0F3A3A,
1597   PREFIX_EVEX_0F3A3B,
1598   PREFIX_EVEX_0F3A3E,
1599   PREFIX_EVEX_0F3A3F,
1600   PREFIX_EVEX_0F3A42,
1601   PREFIX_EVEX_0F3A43,
1602   PREFIX_EVEX_0F3A50,
1603   PREFIX_EVEX_0F3A51,
1604   PREFIX_EVEX_0F3A54,
1605   PREFIX_EVEX_0F3A55,
1606   PREFIX_EVEX_0F3A56,
1607   PREFIX_EVEX_0F3A57,
1608   PREFIX_EVEX_0F3A66,
1609   PREFIX_EVEX_0F3A67
1610 };
1611
1612 enum
1613 {
1614   X86_64_06 = 0,
1615   X86_64_07,
1616   X86_64_0D,
1617   X86_64_16,
1618   X86_64_17,
1619   X86_64_1E,
1620   X86_64_1F,
1621   X86_64_27,
1622   X86_64_2F,
1623   X86_64_37,
1624   X86_64_3F,
1625   X86_64_60,
1626   X86_64_61,
1627   X86_64_62,
1628   X86_64_63,
1629   X86_64_6D,
1630   X86_64_6F,
1631   X86_64_9A,
1632   X86_64_C4,
1633   X86_64_C5,
1634   X86_64_CE,
1635   X86_64_D4,
1636   X86_64_D5,
1637   X86_64_E8,
1638   X86_64_E9,
1639   X86_64_EA,
1640   X86_64_0F01_REG_0,
1641   X86_64_0F01_REG_1,
1642   X86_64_0F01_REG_2,
1643   X86_64_0F01_REG_3
1644 };
1645
1646 enum
1647 {
1648   THREE_BYTE_0F38 = 0,
1649   THREE_BYTE_0F3A,
1650   THREE_BYTE_0F7A
1651 };
1652
1653 enum
1654 {
1655   XOP_08 = 0,
1656   XOP_09,
1657   XOP_0A
1658 };
1659
1660 enum
1661 {
1662   VEX_0F = 0,
1663   VEX_0F38,
1664   VEX_0F3A
1665 };
1666
1667 enum
1668 {
1669   EVEX_0F = 0,
1670   EVEX_0F38,
1671   EVEX_0F3A
1672 };
1673
1674 enum
1675 {
1676   VEX_LEN_0F10_P_1 = 0,
1677   VEX_LEN_0F10_P_3,
1678   VEX_LEN_0F11_P_1,
1679   VEX_LEN_0F11_P_3,
1680   VEX_LEN_0F12_P_0_M_0,
1681   VEX_LEN_0F12_P_0_M_1,
1682   VEX_LEN_0F12_P_2,
1683   VEX_LEN_0F13_M_0,
1684   VEX_LEN_0F16_P_0_M_0,
1685   VEX_LEN_0F16_P_0_M_1,
1686   VEX_LEN_0F16_P_2,
1687   VEX_LEN_0F17_M_0,
1688   VEX_LEN_0F2A_P_1,
1689   VEX_LEN_0F2A_P_3,
1690   VEX_LEN_0F2C_P_1,
1691   VEX_LEN_0F2C_P_3,
1692   VEX_LEN_0F2D_P_1,
1693   VEX_LEN_0F2D_P_3,
1694   VEX_LEN_0F2E_P_0,
1695   VEX_LEN_0F2E_P_2,
1696   VEX_LEN_0F2F_P_0,
1697   VEX_LEN_0F2F_P_2,
1698   VEX_LEN_0F41_P_0,
1699   VEX_LEN_0F41_P_2,
1700   VEX_LEN_0F42_P_0,
1701   VEX_LEN_0F42_P_2,
1702   VEX_LEN_0F44_P_0,
1703   VEX_LEN_0F44_P_2,
1704   VEX_LEN_0F45_P_0,
1705   VEX_LEN_0F45_P_2,
1706   VEX_LEN_0F46_P_0,
1707   VEX_LEN_0F46_P_2,
1708   VEX_LEN_0F47_P_0,
1709   VEX_LEN_0F47_P_2,
1710   VEX_LEN_0F4A_P_0,
1711   VEX_LEN_0F4A_P_2,
1712   VEX_LEN_0F4B_P_0,
1713   VEX_LEN_0F4B_P_2,
1714   VEX_LEN_0F51_P_1,
1715   VEX_LEN_0F51_P_3,
1716   VEX_LEN_0F52_P_1,
1717   VEX_LEN_0F53_P_1,
1718   VEX_LEN_0F58_P_1,
1719   VEX_LEN_0F58_P_3,
1720   VEX_LEN_0F59_P_1,
1721   VEX_LEN_0F59_P_3,
1722   VEX_LEN_0F5A_P_1,
1723   VEX_LEN_0F5A_P_3,
1724   VEX_LEN_0F5C_P_1,
1725   VEX_LEN_0F5C_P_3,
1726   VEX_LEN_0F5D_P_1,
1727   VEX_LEN_0F5D_P_3,
1728   VEX_LEN_0F5E_P_1,
1729   VEX_LEN_0F5E_P_3,
1730   VEX_LEN_0F5F_P_1,
1731   VEX_LEN_0F5F_P_3,
1732   VEX_LEN_0F6E_P_2,
1733   VEX_LEN_0F7E_P_1,
1734   VEX_LEN_0F7E_P_2,
1735   VEX_LEN_0F90_P_0,
1736   VEX_LEN_0F90_P_2,
1737   VEX_LEN_0F91_P_0,
1738   VEX_LEN_0F91_P_2,
1739   VEX_LEN_0F92_P_0,
1740   VEX_LEN_0F92_P_2,
1741   VEX_LEN_0F92_P_3,
1742   VEX_LEN_0F93_P_0,
1743   VEX_LEN_0F93_P_2,
1744   VEX_LEN_0F93_P_3,
1745   VEX_LEN_0F98_P_0,
1746   VEX_LEN_0F98_P_2,
1747   VEX_LEN_0F99_P_0,
1748   VEX_LEN_0F99_P_2,
1749   VEX_LEN_0FAE_R_2_M_0,
1750   VEX_LEN_0FAE_R_3_M_0,
1751   VEX_LEN_0FC2_P_1,
1752   VEX_LEN_0FC2_P_3,
1753   VEX_LEN_0FC4_P_2,
1754   VEX_LEN_0FC5_P_2,
1755   VEX_LEN_0FD6_P_2,
1756   VEX_LEN_0FF7_P_2,
1757   VEX_LEN_0F3816_P_2,
1758   VEX_LEN_0F3819_P_2,
1759   VEX_LEN_0F381A_P_2_M_0,
1760   VEX_LEN_0F3836_P_2,
1761   VEX_LEN_0F3841_P_2,
1762   VEX_LEN_0F385A_P_2_M_0,
1763   VEX_LEN_0F38DB_P_2,
1764   VEX_LEN_0F38DC_P_2,
1765   VEX_LEN_0F38DD_P_2,
1766   VEX_LEN_0F38DE_P_2,
1767   VEX_LEN_0F38DF_P_2,
1768   VEX_LEN_0F38F2_P_0,
1769   VEX_LEN_0F38F3_R_1_P_0,
1770   VEX_LEN_0F38F3_R_2_P_0,
1771   VEX_LEN_0F38F3_R_3_P_0,
1772   VEX_LEN_0F38F5_P_0,
1773   VEX_LEN_0F38F5_P_1,
1774   VEX_LEN_0F38F5_P_3,
1775   VEX_LEN_0F38F6_P_3,
1776   VEX_LEN_0F38F7_P_0,
1777   VEX_LEN_0F38F7_P_1,
1778   VEX_LEN_0F38F7_P_2,
1779   VEX_LEN_0F38F7_P_3,
1780   VEX_LEN_0F3A00_P_2,
1781   VEX_LEN_0F3A01_P_2,
1782   VEX_LEN_0F3A06_P_2,
1783   VEX_LEN_0F3A0A_P_2,
1784   VEX_LEN_0F3A0B_P_2,
1785   VEX_LEN_0F3A14_P_2,
1786   VEX_LEN_0F3A15_P_2,
1787   VEX_LEN_0F3A16_P_2,
1788   VEX_LEN_0F3A17_P_2,
1789   VEX_LEN_0F3A18_P_2,
1790   VEX_LEN_0F3A19_P_2,
1791   VEX_LEN_0F3A20_P_2,
1792   VEX_LEN_0F3A21_P_2,
1793   VEX_LEN_0F3A22_P_2,
1794   VEX_LEN_0F3A30_P_2,
1795   VEX_LEN_0F3A31_P_2,
1796   VEX_LEN_0F3A32_P_2,
1797   VEX_LEN_0F3A33_P_2,
1798   VEX_LEN_0F3A38_P_2,
1799   VEX_LEN_0F3A39_P_2,
1800   VEX_LEN_0F3A41_P_2,
1801   VEX_LEN_0F3A44_P_2,
1802   VEX_LEN_0F3A46_P_2,
1803   VEX_LEN_0F3A60_P_2,
1804   VEX_LEN_0F3A61_P_2,
1805   VEX_LEN_0F3A62_P_2,
1806   VEX_LEN_0F3A63_P_2,
1807   VEX_LEN_0F3A6A_P_2,
1808   VEX_LEN_0F3A6B_P_2,
1809   VEX_LEN_0F3A6E_P_2,
1810   VEX_LEN_0F3A6F_P_2,
1811   VEX_LEN_0F3A7A_P_2,
1812   VEX_LEN_0F3A7B_P_2,
1813   VEX_LEN_0F3A7E_P_2,
1814   VEX_LEN_0F3A7F_P_2,
1815   VEX_LEN_0F3ADF_P_2,
1816   VEX_LEN_0F3AF0_P_3,
1817   VEX_LEN_0FXOP_08_CC,
1818   VEX_LEN_0FXOP_08_CD,
1819   VEX_LEN_0FXOP_08_CE,
1820   VEX_LEN_0FXOP_08_CF,
1821   VEX_LEN_0FXOP_08_EC,
1822   VEX_LEN_0FXOP_08_ED,
1823   VEX_LEN_0FXOP_08_EE,
1824   VEX_LEN_0FXOP_08_EF,
1825   VEX_LEN_0FXOP_09_80,
1826   VEX_LEN_0FXOP_09_81
1827 };
1828
1829 enum
1830 {
1831   VEX_W_0F10_P_0 = 0,
1832   VEX_W_0F10_P_1,
1833   VEX_W_0F10_P_2,
1834   VEX_W_0F10_P_3,
1835   VEX_W_0F11_P_0,
1836   VEX_W_0F11_P_1,
1837   VEX_W_0F11_P_2,
1838   VEX_W_0F11_P_3,
1839   VEX_W_0F12_P_0_M_0,
1840   VEX_W_0F12_P_0_M_1,
1841   VEX_W_0F12_P_1,
1842   VEX_W_0F12_P_2,
1843   VEX_W_0F12_P_3,
1844   VEX_W_0F13_M_0,
1845   VEX_W_0F14,
1846   VEX_W_0F15,
1847   VEX_W_0F16_P_0_M_0,
1848   VEX_W_0F16_P_0_M_1,
1849   VEX_W_0F16_P_1,
1850   VEX_W_0F16_P_2,
1851   VEX_W_0F17_M_0,
1852   VEX_W_0F28,
1853   VEX_W_0F29,
1854   VEX_W_0F2B_M_0,
1855   VEX_W_0F2E_P_0,
1856   VEX_W_0F2E_P_2,
1857   VEX_W_0F2F_P_0,
1858   VEX_W_0F2F_P_2,
1859   VEX_W_0F41_P_0_LEN_1,
1860   VEX_W_0F41_P_2_LEN_1,
1861   VEX_W_0F42_P_0_LEN_1,
1862   VEX_W_0F42_P_2_LEN_1,
1863   VEX_W_0F44_P_0_LEN_0,
1864   VEX_W_0F44_P_2_LEN_0,
1865   VEX_W_0F45_P_0_LEN_1,
1866   VEX_W_0F45_P_2_LEN_1,
1867   VEX_W_0F46_P_0_LEN_1,
1868   VEX_W_0F46_P_2_LEN_1,
1869   VEX_W_0F47_P_0_LEN_1,
1870   VEX_W_0F47_P_2_LEN_1,
1871   VEX_W_0F4A_P_0_LEN_1,
1872   VEX_W_0F4A_P_2_LEN_1,
1873   VEX_W_0F4B_P_0_LEN_1,
1874   VEX_W_0F4B_P_2_LEN_1,
1875   VEX_W_0F50_M_0,
1876   VEX_W_0F51_P_0,
1877   VEX_W_0F51_P_1,
1878   VEX_W_0F51_P_2,
1879   VEX_W_0F51_P_3,
1880   VEX_W_0F52_P_0,
1881   VEX_W_0F52_P_1,
1882   VEX_W_0F53_P_0,
1883   VEX_W_0F53_P_1,
1884   VEX_W_0F58_P_0,
1885   VEX_W_0F58_P_1,
1886   VEX_W_0F58_P_2,
1887   VEX_W_0F58_P_3,
1888   VEX_W_0F59_P_0,
1889   VEX_W_0F59_P_1,
1890   VEX_W_0F59_P_2,
1891   VEX_W_0F59_P_3,
1892   VEX_W_0F5A_P_0,
1893   VEX_W_0F5A_P_1,
1894   VEX_W_0F5A_P_3,
1895   VEX_W_0F5B_P_0,
1896   VEX_W_0F5B_P_1,
1897   VEX_W_0F5B_P_2,
1898   VEX_W_0F5C_P_0,
1899   VEX_W_0F5C_P_1,
1900   VEX_W_0F5C_P_2,
1901   VEX_W_0F5C_P_3,
1902   VEX_W_0F5D_P_0,
1903   VEX_W_0F5D_P_1,
1904   VEX_W_0F5D_P_2,
1905   VEX_W_0F5D_P_3,
1906   VEX_W_0F5E_P_0,
1907   VEX_W_0F5E_P_1,
1908   VEX_W_0F5E_P_2,
1909   VEX_W_0F5E_P_3,
1910   VEX_W_0F5F_P_0,
1911   VEX_W_0F5F_P_1,
1912   VEX_W_0F5F_P_2,
1913   VEX_W_0F5F_P_3,
1914   VEX_W_0F60_P_2,
1915   VEX_W_0F61_P_2,
1916   VEX_W_0F62_P_2,
1917   VEX_W_0F63_P_2,
1918   VEX_W_0F64_P_2,
1919   VEX_W_0F65_P_2,
1920   VEX_W_0F66_P_2,
1921   VEX_W_0F67_P_2,
1922   VEX_W_0F68_P_2,
1923   VEX_W_0F69_P_2,
1924   VEX_W_0F6A_P_2,
1925   VEX_W_0F6B_P_2,
1926   VEX_W_0F6C_P_2,
1927   VEX_W_0F6D_P_2,
1928   VEX_W_0F6F_P_1,
1929   VEX_W_0F6F_P_2,
1930   VEX_W_0F70_P_1,
1931   VEX_W_0F70_P_2,
1932   VEX_W_0F70_P_3,
1933   VEX_W_0F71_R_2_P_2,
1934   VEX_W_0F71_R_4_P_2,
1935   VEX_W_0F71_R_6_P_2,
1936   VEX_W_0F72_R_2_P_2,
1937   VEX_W_0F72_R_4_P_2,
1938   VEX_W_0F72_R_6_P_2,
1939   VEX_W_0F73_R_2_P_2,
1940   VEX_W_0F73_R_3_P_2,
1941   VEX_W_0F73_R_6_P_2,
1942   VEX_W_0F73_R_7_P_2,
1943   VEX_W_0F74_P_2,
1944   VEX_W_0F75_P_2,
1945   VEX_W_0F76_P_2,
1946   VEX_W_0F77_P_0,
1947   VEX_W_0F7C_P_2,
1948   VEX_W_0F7C_P_3,
1949   VEX_W_0F7D_P_2,
1950   VEX_W_0F7D_P_3,
1951   VEX_W_0F7E_P_1,
1952   VEX_W_0F7F_P_1,
1953   VEX_W_0F7F_P_2,
1954   VEX_W_0F90_P_0_LEN_0,
1955   VEX_W_0F90_P_2_LEN_0,
1956   VEX_W_0F91_P_0_LEN_0,
1957   VEX_W_0F91_P_2_LEN_0,
1958   VEX_W_0F92_P_0_LEN_0,
1959   VEX_W_0F92_P_2_LEN_0,
1960   VEX_W_0F92_P_3_LEN_0,
1961   VEX_W_0F93_P_0_LEN_0,
1962   VEX_W_0F93_P_2_LEN_0,
1963   VEX_W_0F93_P_3_LEN_0,
1964   VEX_W_0F98_P_0_LEN_0,
1965   VEX_W_0F98_P_2_LEN_0,
1966   VEX_W_0F99_P_0_LEN_0,
1967   VEX_W_0F99_P_2_LEN_0,
1968   VEX_W_0FAE_R_2_M_0,
1969   VEX_W_0FAE_R_3_M_0,
1970   VEX_W_0FC2_P_0,
1971   VEX_W_0FC2_P_1,
1972   VEX_W_0FC2_P_2,
1973   VEX_W_0FC2_P_3,
1974   VEX_W_0FC4_P_2,
1975   VEX_W_0FC5_P_2,
1976   VEX_W_0FD0_P_2,
1977   VEX_W_0FD0_P_3,
1978   VEX_W_0FD1_P_2,
1979   VEX_W_0FD2_P_2,
1980   VEX_W_0FD3_P_2,
1981   VEX_W_0FD4_P_2,
1982   VEX_W_0FD5_P_2,
1983   VEX_W_0FD6_P_2,
1984   VEX_W_0FD7_P_2_M_1,
1985   VEX_W_0FD8_P_2,
1986   VEX_W_0FD9_P_2,
1987   VEX_W_0FDA_P_2,
1988   VEX_W_0FDB_P_2,
1989   VEX_W_0FDC_P_2,
1990   VEX_W_0FDD_P_2,
1991   VEX_W_0FDE_P_2,
1992   VEX_W_0FDF_P_2,
1993   VEX_W_0FE0_P_2,
1994   VEX_W_0FE1_P_2,
1995   VEX_W_0FE2_P_2,
1996   VEX_W_0FE3_P_2,
1997   VEX_W_0FE4_P_2,
1998   VEX_W_0FE5_P_2,
1999   VEX_W_0FE6_P_1,
2000   VEX_W_0FE6_P_2,
2001   VEX_W_0FE6_P_3,
2002   VEX_W_0FE7_P_2_M_0,
2003   VEX_W_0FE8_P_2,
2004   VEX_W_0FE9_P_2,
2005   VEX_W_0FEA_P_2,
2006   VEX_W_0FEB_P_2,
2007   VEX_W_0FEC_P_2,
2008   VEX_W_0FED_P_2,
2009   VEX_W_0FEE_P_2,
2010   VEX_W_0FEF_P_2,
2011   VEX_W_0FF0_P_3_M_0,
2012   VEX_W_0FF1_P_2,
2013   VEX_W_0FF2_P_2,
2014   VEX_W_0FF3_P_2,
2015   VEX_W_0FF4_P_2,
2016   VEX_W_0FF5_P_2,
2017   VEX_W_0FF6_P_2,
2018   VEX_W_0FF7_P_2,
2019   VEX_W_0FF8_P_2,
2020   VEX_W_0FF9_P_2,
2021   VEX_W_0FFA_P_2,
2022   VEX_W_0FFB_P_2,
2023   VEX_W_0FFC_P_2,
2024   VEX_W_0FFD_P_2,
2025   VEX_W_0FFE_P_2,
2026   VEX_W_0F3800_P_2,
2027   VEX_W_0F3801_P_2,
2028   VEX_W_0F3802_P_2,
2029   VEX_W_0F3803_P_2,
2030   VEX_W_0F3804_P_2,
2031   VEX_W_0F3805_P_2,
2032   VEX_W_0F3806_P_2,
2033   VEX_W_0F3807_P_2,
2034   VEX_W_0F3808_P_2,
2035   VEX_W_0F3809_P_2,
2036   VEX_W_0F380A_P_2,
2037   VEX_W_0F380B_P_2,
2038   VEX_W_0F380C_P_2,
2039   VEX_W_0F380D_P_2,
2040   VEX_W_0F380E_P_2,
2041   VEX_W_0F380F_P_2,
2042   VEX_W_0F3816_P_2,
2043   VEX_W_0F3817_P_2,
2044   VEX_W_0F3818_P_2,
2045   VEX_W_0F3819_P_2,
2046   VEX_W_0F381A_P_2_M_0,
2047   VEX_W_0F381C_P_2,
2048   VEX_W_0F381D_P_2,
2049   VEX_W_0F381E_P_2,
2050   VEX_W_0F3820_P_2,
2051   VEX_W_0F3821_P_2,
2052   VEX_W_0F3822_P_2,
2053   VEX_W_0F3823_P_2,
2054   VEX_W_0F3824_P_2,
2055   VEX_W_0F3825_P_2,
2056   VEX_W_0F3828_P_2,
2057   VEX_W_0F3829_P_2,
2058   VEX_W_0F382A_P_2_M_0,
2059   VEX_W_0F382B_P_2,
2060   VEX_W_0F382C_P_2_M_0,
2061   VEX_W_0F382D_P_2_M_0,
2062   VEX_W_0F382E_P_2_M_0,
2063   VEX_W_0F382F_P_2_M_0,
2064   VEX_W_0F3830_P_2,
2065   VEX_W_0F3831_P_2,
2066   VEX_W_0F3832_P_2,
2067   VEX_W_0F3833_P_2,
2068   VEX_W_0F3834_P_2,
2069   VEX_W_0F3835_P_2,
2070   VEX_W_0F3836_P_2,
2071   VEX_W_0F3837_P_2,
2072   VEX_W_0F3838_P_2,
2073   VEX_W_0F3839_P_2,
2074   VEX_W_0F383A_P_2,
2075   VEX_W_0F383B_P_2,
2076   VEX_W_0F383C_P_2,
2077   VEX_W_0F383D_P_2,
2078   VEX_W_0F383E_P_2,
2079   VEX_W_0F383F_P_2,
2080   VEX_W_0F3840_P_2,
2081   VEX_W_0F3841_P_2,
2082   VEX_W_0F3846_P_2,
2083   VEX_W_0F3858_P_2,
2084   VEX_W_0F3859_P_2,
2085   VEX_W_0F385A_P_2_M_0,
2086   VEX_W_0F3878_P_2,
2087   VEX_W_0F3879_P_2,
2088   VEX_W_0F38DB_P_2,
2089   VEX_W_0F38DC_P_2,
2090   VEX_W_0F38DD_P_2,
2091   VEX_W_0F38DE_P_2,
2092   VEX_W_0F38DF_P_2,
2093   VEX_W_0F3A00_P_2,
2094   VEX_W_0F3A01_P_2,
2095   VEX_W_0F3A02_P_2,
2096   VEX_W_0F3A04_P_2,
2097   VEX_W_0F3A05_P_2,
2098   VEX_W_0F3A06_P_2,
2099   VEX_W_0F3A08_P_2,
2100   VEX_W_0F3A09_P_2,
2101   VEX_W_0F3A0A_P_2,
2102   VEX_W_0F3A0B_P_2,
2103   VEX_W_0F3A0C_P_2,
2104   VEX_W_0F3A0D_P_2,
2105   VEX_W_0F3A0E_P_2,
2106   VEX_W_0F3A0F_P_2,
2107   VEX_W_0F3A14_P_2,
2108   VEX_W_0F3A15_P_2,
2109   VEX_W_0F3A18_P_2,
2110   VEX_W_0F3A19_P_2,
2111   VEX_W_0F3A20_P_2,
2112   VEX_W_0F3A21_P_2,
2113   VEX_W_0F3A30_P_2_LEN_0,
2114   VEX_W_0F3A31_P_2_LEN_0,
2115   VEX_W_0F3A32_P_2_LEN_0,
2116   VEX_W_0F3A33_P_2_LEN_0,
2117   VEX_W_0F3A38_P_2,
2118   VEX_W_0F3A39_P_2,
2119   VEX_W_0F3A40_P_2,
2120   VEX_W_0F3A41_P_2,
2121   VEX_W_0F3A42_P_2,
2122   VEX_W_0F3A44_P_2,
2123   VEX_W_0F3A46_P_2,
2124   VEX_W_0F3A48_P_2,
2125   VEX_W_0F3A49_P_2,
2126   VEX_W_0F3A4A_P_2,
2127   VEX_W_0F3A4B_P_2,
2128   VEX_W_0F3A4C_P_2,
2129   VEX_W_0F3A60_P_2,
2130   VEX_W_0F3A61_P_2,
2131   VEX_W_0F3A62_P_2,
2132   VEX_W_0F3A63_P_2,
2133   VEX_W_0F3ADF_P_2,
2134
2135   EVEX_W_0F10_P_0,
2136   EVEX_W_0F10_P_1_M_0,
2137   EVEX_W_0F10_P_1_M_1,
2138   EVEX_W_0F10_P_2,
2139   EVEX_W_0F10_P_3_M_0,
2140   EVEX_W_0F10_P_3_M_1,
2141   EVEX_W_0F11_P_0,
2142   EVEX_W_0F11_P_1_M_0,
2143   EVEX_W_0F11_P_1_M_1,
2144   EVEX_W_0F11_P_2,
2145   EVEX_W_0F11_P_3_M_0,
2146   EVEX_W_0F11_P_3_M_1,
2147   EVEX_W_0F12_P_0_M_0,
2148   EVEX_W_0F12_P_0_M_1,
2149   EVEX_W_0F12_P_1,
2150   EVEX_W_0F12_P_2,
2151   EVEX_W_0F12_P_3,
2152   EVEX_W_0F13_P_0,
2153   EVEX_W_0F13_P_2,
2154   EVEX_W_0F14_P_0,
2155   EVEX_W_0F14_P_2,
2156   EVEX_W_0F15_P_0,
2157   EVEX_W_0F15_P_2,
2158   EVEX_W_0F16_P_0_M_0,
2159   EVEX_W_0F16_P_0_M_1,
2160   EVEX_W_0F16_P_1,
2161   EVEX_W_0F16_P_2,
2162   EVEX_W_0F17_P_0,
2163   EVEX_W_0F17_P_2,
2164   EVEX_W_0F28_P_0,
2165   EVEX_W_0F28_P_2,
2166   EVEX_W_0F29_P_0,
2167   EVEX_W_0F29_P_2,
2168   EVEX_W_0F2A_P_1,
2169   EVEX_W_0F2A_P_3,
2170   EVEX_W_0F2B_P_0,
2171   EVEX_W_0F2B_P_2,
2172   EVEX_W_0F2E_P_0,
2173   EVEX_W_0F2E_P_2,
2174   EVEX_W_0F2F_P_0,
2175   EVEX_W_0F2F_P_2,
2176   EVEX_W_0F51_P_0,
2177   EVEX_W_0F51_P_1,
2178   EVEX_W_0F51_P_2,
2179   EVEX_W_0F51_P_3,
2180   EVEX_W_0F54_P_0,
2181   EVEX_W_0F54_P_2,
2182   EVEX_W_0F55_P_0,
2183   EVEX_W_0F55_P_2,
2184   EVEX_W_0F56_P_0,
2185   EVEX_W_0F56_P_2,
2186   EVEX_W_0F57_P_0,
2187   EVEX_W_0F57_P_2,
2188   EVEX_W_0F58_P_0,
2189   EVEX_W_0F58_P_1,
2190   EVEX_W_0F58_P_2,
2191   EVEX_W_0F58_P_3,
2192   EVEX_W_0F59_P_0,
2193   EVEX_W_0F59_P_1,
2194   EVEX_W_0F59_P_2,
2195   EVEX_W_0F59_P_3,
2196   EVEX_W_0F5A_P_0,
2197   EVEX_W_0F5A_P_1,
2198   EVEX_W_0F5A_P_2,
2199   EVEX_W_0F5A_P_3,
2200   EVEX_W_0F5B_P_0,
2201   EVEX_W_0F5B_P_1,
2202   EVEX_W_0F5B_P_2,
2203   EVEX_W_0F5C_P_0,
2204   EVEX_W_0F5C_P_1,
2205   EVEX_W_0F5C_P_2,
2206   EVEX_W_0F5C_P_3,
2207   EVEX_W_0F5D_P_0,
2208   EVEX_W_0F5D_P_1,
2209   EVEX_W_0F5D_P_2,
2210   EVEX_W_0F5D_P_3,
2211   EVEX_W_0F5E_P_0,
2212   EVEX_W_0F5E_P_1,
2213   EVEX_W_0F5E_P_2,
2214   EVEX_W_0F5E_P_3,
2215   EVEX_W_0F5F_P_0,
2216   EVEX_W_0F5F_P_1,
2217   EVEX_W_0F5F_P_2,
2218   EVEX_W_0F5F_P_3,
2219   EVEX_W_0F62_P_2,
2220   EVEX_W_0F66_P_2,
2221   EVEX_W_0F6A_P_2,
2222   EVEX_W_0F6B_P_2,
2223   EVEX_W_0F6C_P_2,
2224   EVEX_W_0F6D_P_2,
2225   EVEX_W_0F6E_P_2,
2226   EVEX_W_0F6F_P_1,
2227   EVEX_W_0F6F_P_2,
2228   EVEX_W_0F6F_P_3,
2229   EVEX_W_0F70_P_2,
2230   EVEX_W_0F72_R_2_P_2,
2231   EVEX_W_0F72_R_6_P_2,
2232   EVEX_W_0F73_R_2_P_2,
2233   EVEX_W_0F73_R_6_P_2,
2234   EVEX_W_0F76_P_2,
2235   EVEX_W_0F78_P_0,
2236   EVEX_W_0F78_P_2,
2237   EVEX_W_0F79_P_0,
2238   EVEX_W_0F79_P_2,
2239   EVEX_W_0F7A_P_1,
2240   EVEX_W_0F7A_P_2,
2241   EVEX_W_0F7A_P_3,
2242   EVEX_W_0F7B_P_1,
2243   EVEX_W_0F7B_P_2,
2244   EVEX_W_0F7B_P_3,
2245   EVEX_W_0F7E_P_1,
2246   EVEX_W_0F7E_P_2,
2247   EVEX_W_0F7F_P_1,
2248   EVEX_W_0F7F_P_2,
2249   EVEX_W_0F7F_P_3,
2250   EVEX_W_0FC2_P_0,
2251   EVEX_W_0FC2_P_1,
2252   EVEX_W_0FC2_P_2,
2253   EVEX_W_0FC2_P_3,
2254   EVEX_W_0FC6_P_0,
2255   EVEX_W_0FC6_P_2,
2256   EVEX_W_0FD2_P_2,
2257   EVEX_W_0FD3_P_2,
2258   EVEX_W_0FD4_P_2,
2259   EVEX_W_0FD6_P_2,
2260   EVEX_W_0FE6_P_1,
2261   EVEX_W_0FE6_P_2,
2262   EVEX_W_0FE6_P_3,
2263   EVEX_W_0FE7_P_2,
2264   EVEX_W_0FF2_P_2,
2265   EVEX_W_0FF3_P_2,
2266   EVEX_W_0FF4_P_2,
2267   EVEX_W_0FFA_P_2,
2268   EVEX_W_0FFB_P_2,
2269   EVEX_W_0FFE_P_2,
2270   EVEX_W_0F380C_P_2,
2271   EVEX_W_0F380D_P_2,
2272   EVEX_W_0F3810_P_1,
2273   EVEX_W_0F3810_P_2,
2274   EVEX_W_0F3811_P_1,
2275   EVEX_W_0F3811_P_2,
2276   EVEX_W_0F3812_P_1,
2277   EVEX_W_0F3812_P_2,
2278   EVEX_W_0F3813_P_1,
2279   EVEX_W_0F3813_P_2,
2280   EVEX_W_0F3814_P_1,
2281   EVEX_W_0F3815_P_1,
2282   EVEX_W_0F3818_P_2,
2283   EVEX_W_0F3819_P_2,
2284   EVEX_W_0F381A_P_2,
2285   EVEX_W_0F381B_P_2,
2286   EVEX_W_0F381E_P_2,
2287   EVEX_W_0F381F_P_2,
2288   EVEX_W_0F3820_P_1,
2289   EVEX_W_0F3821_P_1,
2290   EVEX_W_0F3822_P_1,
2291   EVEX_W_0F3823_P_1,
2292   EVEX_W_0F3824_P_1,
2293   EVEX_W_0F3825_P_1,
2294   EVEX_W_0F3825_P_2,
2295   EVEX_W_0F3826_P_1,
2296   EVEX_W_0F3826_P_2,
2297   EVEX_W_0F3828_P_1,
2298   EVEX_W_0F3828_P_2,
2299   EVEX_W_0F3829_P_1,
2300   EVEX_W_0F3829_P_2,
2301   EVEX_W_0F382A_P_1,
2302   EVEX_W_0F382A_P_2,
2303   EVEX_W_0F382B_P_2,
2304   EVEX_W_0F3830_P_1,
2305   EVEX_W_0F3831_P_1,
2306   EVEX_W_0F3832_P_1,
2307   EVEX_W_0F3833_P_1,
2308   EVEX_W_0F3834_P_1,
2309   EVEX_W_0F3835_P_1,
2310   EVEX_W_0F3835_P_2,
2311   EVEX_W_0F3837_P_2,
2312   EVEX_W_0F3838_P_1,
2313   EVEX_W_0F3839_P_1,
2314   EVEX_W_0F383A_P_1,
2315   EVEX_W_0F3840_P_2,
2316   EVEX_W_0F3858_P_2,
2317   EVEX_W_0F3859_P_2,
2318   EVEX_W_0F385A_P_2,
2319   EVEX_W_0F385B_P_2,
2320   EVEX_W_0F3866_P_2,
2321   EVEX_W_0F3875_P_2,
2322   EVEX_W_0F3878_P_2,
2323   EVEX_W_0F3879_P_2,
2324   EVEX_W_0F387A_P_2,
2325   EVEX_W_0F387B_P_2,
2326   EVEX_W_0F387D_P_2,
2327   EVEX_W_0F3883_P_2,
2328   EVEX_W_0F388D_P_2,
2329   EVEX_W_0F3891_P_2,
2330   EVEX_W_0F3893_P_2,
2331   EVEX_W_0F38A1_P_2,
2332   EVEX_W_0F38A3_P_2,
2333   EVEX_W_0F38C7_R_1_P_2,
2334   EVEX_W_0F38C7_R_2_P_2,
2335   EVEX_W_0F38C7_R_5_P_2,
2336   EVEX_W_0F38C7_R_6_P_2,
2337
2338   EVEX_W_0F3A00_P_2,
2339   EVEX_W_0F3A01_P_2,
2340   EVEX_W_0F3A04_P_2,
2341   EVEX_W_0F3A05_P_2,
2342   EVEX_W_0F3A08_P_2,
2343   EVEX_W_0F3A09_P_2,
2344   EVEX_W_0F3A0A_P_2,
2345   EVEX_W_0F3A0B_P_2,
2346   EVEX_W_0F3A16_P_2,
2347   EVEX_W_0F3A18_P_2,
2348   EVEX_W_0F3A19_P_2,
2349   EVEX_W_0F3A1A_P_2,
2350   EVEX_W_0F3A1B_P_2,
2351   EVEX_W_0F3A1D_P_2,
2352   EVEX_W_0F3A21_P_2,
2353   EVEX_W_0F3A22_P_2,
2354   EVEX_W_0F3A23_P_2,
2355   EVEX_W_0F3A38_P_2,
2356   EVEX_W_0F3A39_P_2,
2357   EVEX_W_0F3A3A_P_2,
2358   EVEX_W_0F3A3B_P_2,
2359   EVEX_W_0F3A3E_P_2,
2360   EVEX_W_0F3A3F_P_2,
2361   EVEX_W_0F3A42_P_2,
2362   EVEX_W_0F3A43_P_2,
2363   EVEX_W_0F3A50_P_2,
2364   EVEX_W_0F3A51_P_2,
2365   EVEX_W_0F3A56_P_2,
2366   EVEX_W_0F3A57_P_2,
2367   EVEX_W_0F3A66_P_2,
2368   EVEX_W_0F3A67_P_2
2369 };
2370
2371 typedef void (*op_rtn) (int bytemode, int sizeflag);
2372
2373 struct dis386 {
2374   const char *name;
2375   struct
2376     {
2377       op_rtn rtn;
2378       int bytemode;
2379     } op[MAX_OPERANDS];
2380   unsigned int prefix_requirement;
2381 };
2382
2383 /* Upper case letters in the instruction names here are macros.
2384    'A' => print 'b' if no register operands or suffix_always is true
2385    'B' => print 'b' if suffix_always is true
2386    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2387           size prefix
2388    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2389           suffix_always is true
2390    'E' => print 'e' if 32-bit form of jcxz
2391    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2392    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2393    'H' => print ",pt" or ",pn" branch hint
2394    'I' => honor following macro letter even in Intel mode (implemented only
2395           for some of the macro letters)
2396    'J' => print 'l'
2397    'K' => print 'd' or 'q' if rex prefix is present.
2398    'L' => print 'l' if suffix_always is true
2399    'M' => print 'r' if intel_mnemonic is false.
2400    'N' => print 'n' if instruction has no wait "prefix"
2401    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2402    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2403           or suffix_always is true.  print 'q' if rex prefix is present.
2404    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2405           is true
2406    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2407    'S' => print 'w', 'l' or 'q' if suffix_always is true
2408    'T' => print 'q' in 64bit mode if instruction has no operand size
2409           prefix and behave as 'P' otherwise
2410    'U' => print 'q' in 64bit mode if instruction has no operand size
2411           prefix and behave as 'Q' otherwise
2412    'V' => print 'q' in 64bit mode if instruction has no operand size
2413           prefix and behave as 'S' otherwise
2414    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2415    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2416    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2417           suffix_always is true.
2418    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2419    '!' => change condition from true to false or from false to true.
2420    '%' => add 1 upper case letter to the macro.
2421    '^' => print 'w' or 'l' depending on operand size prefix or
2422           suffix_always is true (lcall/ljmp).
2423    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2424           on operand size prefix.
2425
2426    2 upper case letter macros:
2427    "XY" => print 'x' or 'y' if suffix_always is true or no register
2428            operands and no broadcast.
2429    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2430            register operands and no broadcast.
2431    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2432    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2433            or suffix_always is true
2434    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2435    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2436    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2437    "LW" => print 'd', 'q' depending on the VEX.W bit
2438    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2439            an operand size prefix, or suffix_always is true.  print
2440            'q' if rex prefix is present.
2441
2442    Many of the above letters print nothing in Intel mode.  See "putop"
2443    for the details.
2444
2445    Braces '{' and '}', and vertical bars '|', indicate alternative
2446    mnemonic strings for AT&T and Intel.  */
2447
2448 static const struct dis386 dis386[] = {
2449   /* 00 */
2450   { "addB",             { Ebh1, Gb }, 0 },
2451   { "addS",             { Evh1, Gv }, 0 },
2452   { "addB",             { Gb, EbS }, 0 },
2453   { "addS",             { Gv, EvS }, 0 },
2454   { "addB",             { AL, Ib }, 0 },
2455   { "addS",             { eAX, Iv }, 0 },
2456   { X86_64_TABLE (X86_64_06) },
2457   { X86_64_TABLE (X86_64_07) },
2458   /* 08 */
2459   { "orB",              { Ebh1, Gb }, 0 },
2460   { "orS",              { Evh1, Gv }, 0 },
2461   { "orB",              { Gb, EbS }, 0 },
2462   { "orS",              { Gv, EvS }, 0 },
2463   { "orB",              { AL, Ib }, 0 },
2464   { "orS",              { eAX, Iv }, 0 },
2465   { X86_64_TABLE (X86_64_0D) },
2466   { Bad_Opcode },       /* 0x0f extended opcode escape */
2467   /* 10 */
2468   { "adcB",             { Ebh1, Gb }, 0 },
2469   { "adcS",             { Evh1, Gv }, 0 },
2470   { "adcB",             { Gb, EbS }, 0 },
2471   { "adcS",             { Gv, EvS }, 0 },
2472   { "adcB",             { AL, Ib }, 0 },
2473   { "adcS",             { eAX, Iv }, 0 },
2474   { X86_64_TABLE (X86_64_16) },
2475   { X86_64_TABLE (X86_64_17) },
2476   /* 18 */
2477   { "sbbB",             { Ebh1, Gb }, 0 },
2478   { "sbbS",             { Evh1, Gv }, 0 },
2479   { "sbbB",             { Gb, EbS }, 0 },
2480   { "sbbS",             { Gv, EvS }, 0 },
2481   { "sbbB",             { AL, Ib }, 0 },
2482   { "sbbS",             { eAX, Iv }, 0 },
2483   { X86_64_TABLE (X86_64_1E) },
2484   { X86_64_TABLE (X86_64_1F) },
2485   /* 20 */
2486   { "andB",             { Ebh1, Gb }, 0 },
2487   { "andS",             { Evh1, Gv }, 0 },
2488   { "andB",             { Gb, EbS }, 0 },
2489   { "andS",             { Gv, EvS }, 0 },
2490   { "andB",             { AL, Ib }, 0 },
2491   { "andS",             { eAX, Iv }, 0 },
2492   { Bad_Opcode },       /* SEG ES prefix */
2493   { X86_64_TABLE (X86_64_27) },
2494   /* 28 */
2495   { "subB",             { Ebh1, Gb }, 0 },
2496   { "subS",             { Evh1, Gv }, 0 },
2497   { "subB",             { Gb, EbS }, 0 },
2498   { "subS",             { Gv, EvS }, 0 },
2499   { "subB",             { AL, Ib }, 0 },
2500   { "subS",             { eAX, Iv }, 0 },
2501   { Bad_Opcode },       /* SEG CS prefix */
2502   { X86_64_TABLE (X86_64_2F) },
2503   /* 30 */
2504   { "xorB",             { Ebh1, Gb }, 0 },
2505   { "xorS",             { Evh1, Gv }, 0 },
2506   { "xorB",             { Gb, EbS }, 0 },
2507   { "xorS",             { Gv, EvS }, 0 },
2508   { "xorB",             { AL, Ib }, 0 },
2509   { "xorS",             { eAX, Iv }, 0 },
2510   { Bad_Opcode },       /* SEG SS prefix */
2511   { X86_64_TABLE (X86_64_37) },
2512   /* 38 */
2513   { "cmpB",             { Eb, Gb }, 0 },
2514   { "cmpS",             { Ev, Gv }, 0 },
2515   { "cmpB",             { Gb, EbS }, 0 },
2516   { "cmpS",             { Gv, EvS }, 0 },
2517   { "cmpB",             { AL, Ib }, 0 },
2518   { "cmpS",             { eAX, Iv }, 0 },
2519   { Bad_Opcode },       /* SEG DS prefix */
2520   { X86_64_TABLE (X86_64_3F) },
2521   /* 40 */
2522   { "inc{S|}",          { RMeAX }, 0 },
2523   { "inc{S|}",          { RMeCX }, 0 },
2524   { "inc{S|}",          { RMeDX }, 0 },
2525   { "inc{S|}",          { RMeBX }, 0 },
2526   { "inc{S|}",          { RMeSP }, 0 },
2527   { "inc{S|}",          { RMeBP }, 0 },
2528   { "inc{S|}",          { RMeSI }, 0 },
2529   { "inc{S|}",          { RMeDI }, 0 },
2530   /* 48 */
2531   { "dec{S|}",          { RMeAX }, 0 },
2532   { "dec{S|}",          { RMeCX }, 0 },
2533   { "dec{S|}",          { RMeDX }, 0 },
2534   { "dec{S|}",          { RMeBX }, 0 },
2535   { "dec{S|}",          { RMeSP }, 0 },
2536   { "dec{S|}",          { RMeBP }, 0 },
2537   { "dec{S|}",          { RMeSI }, 0 },
2538   { "dec{S|}",          { RMeDI }, 0 },
2539   /* 50 */
2540   { "pushV",            { RMrAX }, 0 },
2541   { "pushV",            { RMrCX }, 0 },
2542   { "pushV",            { RMrDX }, 0 },
2543   { "pushV",            { RMrBX }, 0 },
2544   { "pushV",            { RMrSP }, 0 },
2545   { "pushV",            { RMrBP }, 0 },
2546   { "pushV",            { RMrSI }, 0 },
2547   { "pushV",            { RMrDI }, 0 },
2548   /* 58 */
2549   { "popV",             { RMrAX }, 0 },
2550   { "popV",             { RMrCX }, 0 },
2551   { "popV",             { RMrDX }, 0 },
2552   { "popV",             { RMrBX }, 0 },
2553   { "popV",             { RMrSP }, 0 },
2554   { "popV",             { RMrBP }, 0 },
2555   { "popV",             { RMrSI }, 0 },
2556   { "popV",             { RMrDI }, 0 },
2557   /* 60 */
2558   { X86_64_TABLE (X86_64_60) },
2559   { X86_64_TABLE (X86_64_61) },
2560   { X86_64_TABLE (X86_64_62) },
2561   { X86_64_TABLE (X86_64_63) },
2562   { Bad_Opcode },       /* seg fs */
2563   { Bad_Opcode },       /* seg gs */
2564   { Bad_Opcode },       /* op size prefix */
2565   { Bad_Opcode },       /* adr size prefix */
2566   /* 68 */
2567   { "pushT",            { sIv }, 0 },
2568   { "imulS",            { Gv, Ev, Iv }, 0 },
2569   { "pushT",            { sIbT }, 0 },
2570   { "imulS",            { Gv, Ev, sIb }, 0 },
2571   { "ins{b|}",          { Ybr, indirDX }, 0 },
2572   { X86_64_TABLE (X86_64_6D) },
2573   { "outs{b|}",         { indirDXr, Xb }, 0 },
2574   { X86_64_TABLE (X86_64_6F) },
2575   /* 70 */
2576   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2577   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2578   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2579   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2580   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2581   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2582   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2583   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2584   /* 78 */
2585   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2586   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2587   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2588   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2589   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2590   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2591   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2592   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2593   /* 80 */
2594   { REG_TABLE (REG_80) },
2595   { REG_TABLE (REG_81) },
2596   { Bad_Opcode },
2597   { REG_TABLE (REG_82) },
2598   { "testB",            { Eb, Gb }, 0 },
2599   { "testS",            { Ev, Gv }, 0 },
2600   { "xchgB",            { Ebh2, Gb }, 0 },
2601   { "xchgS",            { Evh2, Gv }, 0 },
2602   /* 88 */
2603   { "movB",             { Ebh3, Gb }, 0 },
2604   { "movS",             { Evh3, Gv }, 0 },
2605   { "movB",             { Gb, EbS }, 0 },
2606   { "movS",             { Gv, EvS }, 0 },
2607   { "movD",             { Sv, Sw }, 0 },
2608   { MOD_TABLE (MOD_8D) },
2609   { "movD",             { Sw, Sv }, 0 },
2610   { REG_TABLE (REG_8F) },
2611   /* 90 */
2612   { PREFIX_TABLE (PREFIX_90) },
2613   { "xchgS",            { RMeCX, eAX }, 0 },
2614   { "xchgS",            { RMeDX, eAX }, 0 },
2615   { "xchgS",            { RMeBX, eAX }, 0 },
2616   { "xchgS",            { RMeSP, eAX }, 0 },
2617   { "xchgS",            { RMeBP, eAX }, 0 },
2618   { "xchgS",            { RMeSI, eAX }, 0 },
2619   { "xchgS",            { RMeDI, eAX }, 0 },
2620   /* 98 */
2621   { "cW{t|}R",          { XX }, 0 },
2622   { "cR{t|}O",          { XX }, 0 },
2623   { X86_64_TABLE (X86_64_9A) },
2624   { Bad_Opcode },       /* fwait */
2625   { "pushfT",           { XX }, 0 },
2626   { "popfT",            { XX }, 0 },
2627   { "sahf",             { XX }, 0 },
2628   { "lahf",             { XX }, 0 },
2629   /* a0 */
2630   { "mov%LB",           { AL, Ob }, 0 },
2631   { "mov%LS",           { eAX, Ov }, 0 },
2632   { "mov%LB",           { Ob, AL }, 0 },
2633   { "mov%LS",           { Ov, eAX }, 0 },
2634   { "movs{b|}",         { Ybr, Xb }, 0 },
2635   { "movs{R|}",         { Yvr, Xv }, 0 },
2636   { "cmps{b|}",         { Xb, Yb }, 0 },
2637   { "cmps{R|}",         { Xv, Yv }, 0 },
2638   /* a8 */
2639   { "testB",            { AL, Ib }, 0 },
2640   { "testS",            { eAX, Iv }, 0 },
2641   { "stosB",            { Ybr, AL }, 0 },
2642   { "stosS",            { Yvr, eAX }, 0 },
2643   { "lodsB",            { ALr, Xb }, 0 },
2644   { "lodsS",            { eAXr, Xv }, 0 },
2645   { "scasB",            { AL, Yb }, 0 },
2646   { "scasS",            { eAX, Yv }, 0 },
2647   /* b0 */
2648   { "movB",             { RMAL, Ib }, 0 },
2649   { "movB",             { RMCL, Ib }, 0 },
2650   { "movB",             { RMDL, Ib }, 0 },
2651   { "movB",             { RMBL, Ib }, 0 },
2652   { "movB",             { RMAH, Ib }, 0 },
2653   { "movB",             { RMCH, Ib }, 0 },
2654   { "movB",             { RMDH, Ib }, 0 },
2655   { "movB",             { RMBH, Ib }, 0 },
2656   /* b8 */
2657   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2658   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2659   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2660   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2661   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2662   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2663   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2664   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2665   /* c0 */
2666   { REG_TABLE (REG_C0) },
2667   { REG_TABLE (REG_C1) },
2668   { "retT",             { Iw, BND }, 0 },
2669   { "retT",             { BND }, 0 },
2670   { X86_64_TABLE (X86_64_C4) },
2671   { X86_64_TABLE (X86_64_C5) },
2672   { REG_TABLE (REG_C6) },
2673   { REG_TABLE (REG_C7) },
2674   /* c8 */
2675   { "enterT",           { Iw, Ib }, 0 },
2676   { "leaveT",           { XX }, 0 },
2677   { "Jret{|f}P",        { Iw }, 0 },
2678   { "Jret{|f}P",        { XX }, 0 },
2679   { "int3",             { XX }, 0 },
2680   { "int",              { Ib }, 0 },
2681   { X86_64_TABLE (X86_64_CE) },
2682   { "iret%LP",          { XX }, 0 },
2683   /* d0 */
2684   { REG_TABLE (REG_D0) },
2685   { REG_TABLE (REG_D1) },
2686   { REG_TABLE (REG_D2) },
2687   { REG_TABLE (REG_D3) },
2688   { X86_64_TABLE (X86_64_D4) },
2689   { X86_64_TABLE (X86_64_D5) },
2690   { Bad_Opcode },
2691   { "xlat",             { DSBX }, 0 },
2692   /* d8 */
2693   { FLOAT },
2694   { FLOAT },
2695   { FLOAT },
2696   { FLOAT },
2697   { FLOAT },
2698   { FLOAT },
2699   { FLOAT },
2700   { FLOAT },
2701   /* e0 */
2702   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2703   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2704   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2705   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2706   { "inB",              { AL, Ib }, 0 },
2707   { "inG",              { zAX, Ib }, 0 },
2708   { "outB",             { Ib, AL }, 0 },
2709   { "outG",             { Ib, zAX }, 0 },
2710   /* e8 */
2711   { X86_64_TABLE (X86_64_E8) },
2712   { X86_64_TABLE (X86_64_E9) },
2713   { X86_64_TABLE (X86_64_EA) },
2714   { "jmp",              { Jb, BND }, 0 },
2715   { "inB",              { AL, indirDX }, 0 },
2716   { "inG",              { zAX, indirDX }, 0 },
2717   { "outB",             { indirDX, AL }, 0 },
2718   { "outG",             { indirDX, zAX }, 0 },
2719   /* f0 */
2720   { Bad_Opcode },       /* lock prefix */
2721   { "icebp",            { XX }, 0 },
2722   { Bad_Opcode },       /* repne */
2723   { Bad_Opcode },       /* repz */
2724   { "hlt",              { XX }, 0 },
2725   { "cmc",              { XX }, 0 },
2726   { REG_TABLE (REG_F6) },
2727   { REG_TABLE (REG_F7) },
2728   /* f8 */
2729   { "clc",              { XX }, 0 },
2730   { "stc",              { XX }, 0 },
2731   { "cli",              { XX }, 0 },
2732   { "sti",              { XX }, 0 },
2733   { "cld",              { XX }, 0 },
2734   { "std",              { XX }, 0 },
2735   { REG_TABLE (REG_FE) },
2736   { REG_TABLE (REG_FF) },
2737 };
2738
2739 static const struct dis386 dis386_twobyte[] = {
2740   /* 00 */
2741   { REG_TABLE (REG_0F00 ) },
2742   { REG_TABLE (REG_0F01 ) },
2743   { "larS",             { Gv, Ew }, 0 },
2744   { "lslS",             { Gv, Ew }, 0 },
2745   { Bad_Opcode },
2746   { "syscall",          { XX }, 0 },
2747   { "clts",             { XX }, 0 },
2748   { "sysret%LP",                { XX }, 0 },
2749   /* 08 */
2750   { "invd",             { XX }, 0 },
2751   { "wbinvd",           { XX }, 0 },
2752   { Bad_Opcode },
2753   { "ud2",              { XX }, 0 },
2754   { Bad_Opcode },
2755   { REG_TABLE (REG_0F0D) },
2756   { "femms",            { XX }, 0 },
2757   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2758   /* 10 */
2759   { PREFIX_TABLE (PREFIX_0F10) },
2760   { PREFIX_TABLE (PREFIX_0F11) },
2761   { PREFIX_TABLE (PREFIX_0F12) },
2762   { MOD_TABLE (MOD_0F13) },
2763   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2764   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2765   { PREFIX_TABLE (PREFIX_0F16) },
2766   { MOD_TABLE (MOD_0F17) },
2767   /* 18 */
2768   { REG_TABLE (REG_0F18) },
2769   { "nopQ",             { Ev }, 0 },
2770   { PREFIX_TABLE (PREFIX_0F1A) },
2771   { PREFIX_TABLE (PREFIX_0F1B) },
2772   { "nopQ",             { Ev }, 0 },
2773   { "nopQ",             { Ev }, 0 },
2774   { "nopQ",             { Ev }, 0 },
2775   { "nopQ",             { Ev }, 0 },
2776   /* 20 */
2777   { "movZ",             { Rm, Cm }, 0 },
2778   { "movZ",             { Rm, Dm }, 0 },
2779   { "movZ",             { Cm, Rm }, 0 },
2780   { "movZ",             { Dm, Rm }, 0 },
2781   { MOD_TABLE (MOD_0F24) },
2782   { Bad_Opcode },
2783   { MOD_TABLE (MOD_0F26) },
2784   { Bad_Opcode },
2785   /* 28 */
2786   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2787   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2788   { PREFIX_TABLE (PREFIX_0F2A) },
2789   { PREFIX_TABLE (PREFIX_0F2B) },
2790   { PREFIX_TABLE (PREFIX_0F2C) },
2791   { PREFIX_TABLE (PREFIX_0F2D) },
2792   { PREFIX_TABLE (PREFIX_0F2E) },
2793   { PREFIX_TABLE (PREFIX_0F2F) },
2794   /* 30 */
2795   { "wrmsr",            { XX }, 0 },
2796   { "rdtsc",            { XX }, 0 },
2797   { "rdmsr",            { XX }, 0 },
2798   { "rdpmc",            { XX }, 0 },
2799   { "sysenter",         { XX }, 0 },
2800   { "sysexit",          { XX }, 0 },
2801   { Bad_Opcode },
2802   { "getsec",           { XX }, 0 },
2803   /* 38 */
2804   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2805   { Bad_Opcode },
2806   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2807   { Bad_Opcode },
2808   { Bad_Opcode },
2809   { Bad_Opcode },
2810   { Bad_Opcode },
2811   { Bad_Opcode },
2812   /* 40 */
2813   { "cmovoS",           { Gv, Ev }, 0 },
2814   { "cmovnoS",          { Gv, Ev }, 0 },
2815   { "cmovbS",           { Gv, Ev }, 0 },
2816   { "cmovaeS",          { Gv, Ev }, 0 },
2817   { "cmoveS",           { Gv, Ev }, 0 },
2818   { "cmovneS",          { Gv, Ev }, 0 },
2819   { "cmovbeS",          { Gv, Ev }, 0 },
2820   { "cmovaS",           { Gv, Ev }, 0 },
2821   /* 48 */
2822   { "cmovsS",           { Gv, Ev }, 0 },
2823   { "cmovnsS",          { Gv, Ev }, 0 },
2824   { "cmovpS",           { Gv, Ev }, 0 },
2825   { "cmovnpS",          { Gv, Ev }, 0 },
2826   { "cmovlS",           { Gv, Ev }, 0 },
2827   { "cmovgeS",          { Gv, Ev }, 0 },
2828   { "cmovleS",          { Gv, Ev }, 0 },
2829   { "cmovgS",           { Gv, Ev }, 0 },
2830   /* 50 */
2831   { MOD_TABLE (MOD_0F51) },
2832   { PREFIX_TABLE (PREFIX_0F51) },
2833   { PREFIX_TABLE (PREFIX_0F52) },
2834   { PREFIX_TABLE (PREFIX_0F53) },
2835   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2836   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2837   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2838   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2839   /* 58 */
2840   { PREFIX_TABLE (PREFIX_0F58) },
2841   { PREFIX_TABLE (PREFIX_0F59) },
2842   { PREFIX_TABLE (PREFIX_0F5A) },
2843   { PREFIX_TABLE (PREFIX_0F5B) },
2844   { PREFIX_TABLE (PREFIX_0F5C) },
2845   { PREFIX_TABLE (PREFIX_0F5D) },
2846   { PREFIX_TABLE (PREFIX_0F5E) },
2847   { PREFIX_TABLE (PREFIX_0F5F) },
2848   /* 60 */
2849   { PREFIX_TABLE (PREFIX_0F60) },
2850   { PREFIX_TABLE (PREFIX_0F61) },
2851   { PREFIX_TABLE (PREFIX_0F62) },
2852   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2853   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2854   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2855   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2856   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2857   /* 68 */
2858   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2859   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2860   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2861   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2862   { PREFIX_TABLE (PREFIX_0F6C) },
2863   { PREFIX_TABLE (PREFIX_0F6D) },
2864   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2865   { PREFIX_TABLE (PREFIX_0F6F) },
2866   /* 70 */
2867   { PREFIX_TABLE (PREFIX_0F70) },
2868   { REG_TABLE (REG_0F71) },
2869   { REG_TABLE (REG_0F72) },
2870   { REG_TABLE (REG_0F73) },
2871   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2872   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2873   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2874   { "emms",             { XX }, PREFIX_OPCODE },
2875   /* 78 */
2876   { PREFIX_TABLE (PREFIX_0F78) },
2877   { PREFIX_TABLE (PREFIX_0F79) },
2878   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2879   { Bad_Opcode },
2880   { PREFIX_TABLE (PREFIX_0F7C) },
2881   { PREFIX_TABLE (PREFIX_0F7D) },
2882   { PREFIX_TABLE (PREFIX_0F7E) },
2883   { PREFIX_TABLE (PREFIX_0F7F) },
2884   /* 80 */
2885   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2886   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2887   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2888   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2889   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2890   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2891   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2892   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2893   /* 88 */
2894   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2895   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2896   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2897   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2898   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2899   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2900   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2901   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2902   /* 90 */
2903   { "seto",             { Eb }, 0 },
2904   { "setno",            { Eb }, 0 },
2905   { "setb",             { Eb }, 0 },
2906   { "setae",            { Eb }, 0 },
2907   { "sete",             { Eb }, 0 },
2908   { "setne",            { Eb }, 0 },
2909   { "setbe",            { Eb }, 0 },
2910   { "seta",             { Eb }, 0 },
2911   /* 98 */
2912   { "sets",             { Eb }, 0 },
2913   { "setns",            { Eb }, 0 },
2914   { "setp",             { Eb }, 0 },
2915   { "setnp",            { Eb }, 0 },
2916   { "setl",             { Eb }, 0 },
2917   { "setge",            { Eb }, 0 },
2918   { "setle",            { Eb }, 0 },
2919   { "setg",             { Eb }, 0 },
2920   /* a0 */
2921   { "pushT",            { fs }, 0 },
2922   { "popT",             { fs }, 0 },
2923   { "cpuid",            { XX }, 0 },
2924   { "btS",              { Ev, Gv }, 0 },
2925   { "shldS",            { Ev, Gv, Ib }, 0 },
2926   { "shldS",            { Ev, Gv, CL }, 0 },
2927   { REG_TABLE (REG_0FA6) },
2928   { REG_TABLE (REG_0FA7) },
2929   /* a8 */
2930   { "pushT",            { gs }, 0 },
2931   { "popT",             { gs }, 0 },
2932   { "rsm",              { XX }, 0 },
2933   { "btsS",             { Evh1, Gv }, 0 },
2934   { "shrdS",            { Ev, Gv, Ib }, 0 },
2935   { "shrdS",            { Ev, Gv, CL }, 0 },
2936   { REG_TABLE (REG_0FAE) },
2937   { "imulS",            { Gv, Ev }, 0 },
2938   /* b0 */
2939   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2940   { "cmpxchgS",         { Evh1, Gv }, 0 },
2941   { MOD_TABLE (MOD_0FB2) },
2942   { "btrS",             { Evh1, Gv }, 0 },
2943   { MOD_TABLE (MOD_0FB4) },
2944   { MOD_TABLE (MOD_0FB5) },
2945   { "movz{bR|x}",       { Gv, Eb }, 0 },
2946   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2947   /* b8 */
2948   { PREFIX_TABLE (PREFIX_0FB8) },
2949   { "ud1",              { XX }, 0 },
2950   { REG_TABLE (REG_0FBA) },
2951   { "btcS",             { Evh1, Gv }, 0 },
2952   { PREFIX_TABLE (PREFIX_0FBC) },
2953   { PREFIX_TABLE (PREFIX_0FBD) },
2954   { "movs{bR|x}",       { Gv, Eb }, 0 },
2955   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2956   /* c0 */
2957   { "xaddB",            { Ebh1, Gb }, 0 },
2958   { "xaddS",            { Evh1, Gv }, 0 },
2959   { PREFIX_TABLE (PREFIX_0FC2) },
2960   { MOD_TABLE (MOD_0FC3) },
2961   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2962   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2963   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2964   { REG_TABLE (REG_0FC7) },
2965   /* c8 */
2966   { "bswap",            { RMeAX }, 0 },
2967   { "bswap",            { RMeCX }, 0 },
2968   { "bswap",            { RMeDX }, 0 },
2969   { "bswap",            { RMeBX }, 0 },
2970   { "bswap",            { RMeSP }, 0 },
2971   { "bswap",            { RMeBP }, 0 },
2972   { "bswap",            { RMeSI }, 0 },
2973   { "bswap",            { RMeDI }, 0 },
2974   /* d0 */
2975   { PREFIX_TABLE (PREFIX_0FD0) },
2976   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2977   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2978   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2979   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2980   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2981   { PREFIX_TABLE (PREFIX_0FD6) },
2982   { MOD_TABLE (MOD_0FD7) },
2983   /* d8 */
2984   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2985   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2986   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2987   { "pand",             { MX, EM }, PREFIX_OPCODE },
2988   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2989   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2990   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2991   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2992   /* e0 */
2993   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2994   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2995   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2996   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2997   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2998   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2999   { PREFIX_TABLE (PREFIX_0FE6) },
3000   { PREFIX_TABLE (PREFIX_0FE7) },
3001   /* e8 */
3002   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3003   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3004   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3005   { "por",              { MX, EM }, PREFIX_OPCODE },
3006   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3007   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3008   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3009   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3010   /* f0 */
3011   { PREFIX_TABLE (PREFIX_0FF0) },
3012   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3013   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3014   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3015   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3016   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3017   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3018   { PREFIX_TABLE (PREFIX_0FF7) },
3019   /* f8 */
3020   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3021   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3022   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3023   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3024   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3025   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3026   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3027   { Bad_Opcode },
3028 };
3029
3030 static const unsigned char onebyte_has_modrm[256] = {
3031   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3032   /*       -------------------------------        */
3033   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3034   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3035   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3036   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3037   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3038   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3039   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3040   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3041   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3042   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3043   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3044   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3045   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3046   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3047   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3048   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3049   /*       -------------------------------        */
3050   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3051 };
3052
3053 static const unsigned char twobyte_has_modrm[256] = {
3054   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3055   /*       -------------------------------        */
3056   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3057   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3058   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3059   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3060   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3061   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3062   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3063   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3064   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3065   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3066   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3067   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3068   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3069   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3070   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3071   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3072   /*       -------------------------------        */
3073   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3074 };
3075
3076 static char obuf[100];
3077 static char *obufp;
3078 static char *mnemonicendp;
3079 static char scratchbuf[100];
3080 static unsigned char *start_codep;
3081 static unsigned char *insn_codep;
3082 static unsigned char *codep;
3083 static unsigned char *end_codep;
3084 static int last_lock_prefix;
3085 static int last_repz_prefix;
3086 static int last_repnz_prefix;
3087 static int last_data_prefix;
3088 static int last_addr_prefix;
3089 static int last_rex_prefix;
3090 static int last_seg_prefix;
3091 static int fwait_prefix;
3092 /* The active segment register prefix.  */
3093 static int active_seg_prefix;
3094 #define MAX_CODE_LENGTH 15
3095 /* We can up to 14 prefixes since the maximum instruction length is
3096    15bytes.  */
3097 static int all_prefixes[MAX_CODE_LENGTH - 1];
3098 static disassemble_info *the_info;
3099 static struct
3100   {
3101     int mod;
3102     int reg;
3103     int rm;
3104   }
3105 modrm;
3106 static unsigned char need_modrm;
3107 static struct
3108   {
3109     int scale;
3110     int index;
3111     int base;
3112   }
3113 sib;
3114 static struct
3115   {
3116     int register_specifier;
3117     int length;
3118     int prefix;
3119     int w;
3120     int evex;
3121     int r;
3122     int v;
3123     int mask_register_specifier;
3124     int zeroing;
3125     int ll;
3126     int b;
3127   }
3128 vex;
3129 static unsigned char need_vex;
3130 static unsigned char need_vex_reg;
3131 static unsigned char vex_w_done;
3132
3133 struct op
3134   {
3135     const char *name;
3136     unsigned int len;
3137   };
3138
3139 /* If we are accessing mod/rm/reg without need_modrm set, then the
3140    values are stale.  Hitting this abort likely indicates that you
3141    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3142 #define MODRM_CHECK  if (!need_modrm) abort ()
3143
3144 static const char **names64;
3145 static const char **names32;
3146 static const char **names16;
3147 static const char **names8;
3148 static const char **names8rex;
3149 static const char **names_seg;
3150 static const char *index64;
3151 static const char *index32;
3152 static const char **index16;
3153 static const char **names_bnd;
3154
3155 static const char *intel_names64[] = {
3156   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3157   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3158 };
3159 static const char *intel_names32[] = {
3160   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3161   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3162 };
3163 static const char *intel_names16[] = {
3164   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3165   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3166 };
3167 static const char *intel_names8[] = {
3168   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3169 };
3170 static const char *intel_names8rex[] = {
3171   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3172   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3173 };
3174 static const char *intel_names_seg[] = {
3175   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3176 };
3177 static const char *intel_index64 = "riz";
3178 static const char *intel_index32 = "eiz";
3179 static const char *intel_index16[] = {
3180   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3181 };
3182
3183 static const char *att_names64[] = {
3184   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3185   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3186 };
3187 static const char *att_names32[] = {
3188   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3189   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3190 };
3191 static const char *att_names16[] = {
3192   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3193   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3194 };
3195 static const char *att_names8[] = {
3196   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3197 };
3198 static const char *att_names8rex[] = {
3199   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3200   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3201 };
3202 static const char *att_names_seg[] = {
3203   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3204 };
3205 static const char *att_index64 = "%riz";
3206 static const char *att_index32 = "%eiz";
3207 static const char *att_index16[] = {
3208   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3209 };
3210
3211 static const char **names_mm;
3212 static const char *intel_names_mm[] = {
3213   "mm0", "mm1", "mm2", "mm3",
3214   "mm4", "mm5", "mm6", "mm7"
3215 };
3216 static const char *att_names_mm[] = {
3217   "%mm0", "%mm1", "%mm2", "%mm3",
3218   "%mm4", "%mm5", "%mm6", "%mm7"
3219 };
3220
3221 static const char *intel_names_bnd[] = {
3222   "bnd0", "bnd1", "bnd2", "bnd3"
3223 };
3224
3225 static const char *att_names_bnd[] = {
3226   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3227 };
3228
3229 static const char **names_xmm;
3230 static const char *intel_names_xmm[] = {
3231   "xmm0", "xmm1", "xmm2", "xmm3",
3232   "xmm4", "xmm5", "xmm6", "xmm7",
3233   "xmm8", "xmm9", "xmm10", "xmm11",
3234   "xmm12", "xmm13", "xmm14", "xmm15",
3235   "xmm16", "xmm17", "xmm18", "xmm19",
3236   "xmm20", "xmm21", "xmm22", "xmm23",
3237   "xmm24", "xmm25", "xmm26", "xmm27",
3238   "xmm28", "xmm29", "xmm30", "xmm31"
3239 };
3240 static const char *att_names_xmm[] = {
3241   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3242   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3243   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3244   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3245   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3246   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3247   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3248   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3249 };
3250
3251 static const char **names_ymm;
3252 static const char *intel_names_ymm[] = {
3253   "ymm0", "ymm1", "ymm2", "ymm3",
3254   "ymm4", "ymm5", "ymm6", "ymm7",
3255   "ymm8", "ymm9", "ymm10", "ymm11",
3256   "ymm12", "ymm13", "ymm14", "ymm15",
3257   "ymm16", "ymm17", "ymm18", "ymm19",
3258   "ymm20", "ymm21", "ymm22", "ymm23",
3259   "ymm24", "ymm25", "ymm26", "ymm27",
3260   "ymm28", "ymm29", "ymm30", "ymm31"
3261 };
3262 static const char *att_names_ymm[] = {
3263   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3264   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3265   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3266   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3267   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3268   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3269   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3270   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3271 };
3272
3273 static const char **names_zmm;
3274 static const char *intel_names_zmm[] = {
3275   "zmm0", "zmm1", "zmm2", "zmm3",
3276   "zmm4", "zmm5", "zmm6", "zmm7",
3277   "zmm8", "zmm9", "zmm10", "zmm11",
3278   "zmm12", "zmm13", "zmm14", "zmm15",
3279   "zmm16", "zmm17", "zmm18", "zmm19",
3280   "zmm20", "zmm21", "zmm22", "zmm23",
3281   "zmm24", "zmm25", "zmm26", "zmm27",
3282   "zmm28", "zmm29", "zmm30", "zmm31"
3283 };
3284 static const char *att_names_zmm[] = {
3285   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3286   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3287   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3288   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3289   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3290   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3291   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3292   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3293 };
3294
3295 static const char **names_mask;
3296 static const char *intel_names_mask[] = {
3297   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3298 };
3299 static const char *att_names_mask[] = {
3300   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3301 };
3302
3303 static const char *names_rounding[] =
3304 {
3305   "{rn-sae}",
3306   "{rd-sae}",
3307   "{ru-sae}",
3308   "{rz-sae}"
3309 };
3310
3311 static const struct dis386 reg_table[][8] = {
3312   /* REG_80 */
3313   {
3314     { "addA",   { Ebh1, Ib }, 0 },
3315     { "orA",    { Ebh1, Ib }, 0 },
3316     { "adcA",   { Ebh1, Ib }, 0 },
3317     { "sbbA",   { Ebh1, Ib }, 0 },
3318     { "andA",   { Ebh1, Ib }, 0 },
3319     { "subA",   { Ebh1, Ib }, 0 },
3320     { "xorA",   { Ebh1, Ib }, 0 },
3321     { "cmpA",   { Eb, Ib }, 0 },
3322   },
3323   /* REG_81 */
3324   {
3325     { "addQ",   { Evh1, Iv }, 0 },
3326     { "orQ",    { Evh1, Iv }, 0 },
3327     { "adcQ",   { Evh1, Iv }, 0 },
3328     { "sbbQ",   { Evh1, Iv }, 0 },
3329     { "andQ",   { Evh1, Iv }, 0 },
3330     { "subQ",   { Evh1, Iv }, 0 },
3331     { "xorQ",   { Evh1, Iv }, 0 },
3332     { "cmpQ",   { Ev, Iv }, 0 },
3333   },
3334   /* REG_82 */
3335   {
3336     { "addQ",   { Evh1, sIb }, 0 },
3337     { "orQ",    { Evh1, sIb }, 0 },
3338     { "adcQ",   { Evh1, sIb }, 0 },
3339     { "sbbQ",   { Evh1, sIb }, 0 },
3340     { "andQ",   { Evh1, sIb }, 0 },
3341     { "subQ",   { Evh1, sIb }, 0 },
3342     { "xorQ",   { Evh1, sIb }, 0 },
3343     { "cmpQ",   { Ev, sIb }, 0 },
3344   },
3345   /* REG_8F */
3346   {
3347     { "popU",   { stackEv }, 0 },
3348     { XOP_8F_TABLE (XOP_09) },
3349     { Bad_Opcode },
3350     { Bad_Opcode },
3351     { Bad_Opcode },
3352     { XOP_8F_TABLE (XOP_09) },
3353   },
3354   /* REG_C0 */
3355   {
3356     { "rolA",   { Eb, Ib }, 0 },
3357     { "rorA",   { Eb, Ib }, 0 },
3358     { "rclA",   { Eb, Ib }, 0 },
3359     { "rcrA",   { Eb, Ib }, 0 },
3360     { "shlA",   { Eb, Ib }, 0 },
3361     { "shrA",   { Eb, Ib }, 0 },
3362     { Bad_Opcode },
3363     { "sarA",   { Eb, Ib }, 0 },
3364   },
3365   /* REG_C1 */
3366   {
3367     { "rolQ",   { Ev, Ib }, 0 },
3368     { "rorQ",   { Ev, Ib }, 0 },
3369     { "rclQ",   { Ev, Ib }, 0 },
3370     { "rcrQ",   { Ev, Ib }, 0 },
3371     { "shlQ",   { Ev, Ib }, 0 },
3372     { "shrQ",   { Ev, Ib }, 0 },
3373     { Bad_Opcode },
3374     { "sarQ",   { Ev, Ib }, 0 },
3375   },
3376   /* REG_C6 */
3377   {
3378     { "movA",   { Ebh3, Ib }, 0 },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { Bad_Opcode },
3384     { Bad_Opcode },
3385     { MOD_TABLE (MOD_C6_REG_7) },
3386   },
3387   /* REG_C7 */
3388   {
3389     { "movQ",   { Evh3, Iv }, 0 },
3390     { Bad_Opcode },
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { Bad_Opcode },
3396     { MOD_TABLE (MOD_C7_REG_7) },
3397   },
3398   /* REG_D0 */
3399   {
3400     { "rolA",   { Eb, I1 }, 0 },
3401     { "rorA",   { Eb, I1 }, 0 },
3402     { "rclA",   { Eb, I1 }, 0 },
3403     { "rcrA",   { Eb, I1 }, 0 },
3404     { "shlA",   { Eb, I1 }, 0 },
3405     { "shrA",   { Eb, I1 }, 0 },
3406     { Bad_Opcode },
3407     { "sarA",   { Eb, I1 }, 0 },
3408   },
3409   /* REG_D1 */
3410   {
3411     { "rolQ",   { Ev, I1 }, 0 },
3412     { "rorQ",   { Ev, I1 }, 0 },
3413     { "rclQ",   { Ev, I1 }, 0 },
3414     { "rcrQ",   { Ev, I1 }, 0 },
3415     { "shlQ",   { Ev, I1 }, 0 },
3416     { "shrQ",   { Ev, I1 }, 0 },
3417     { Bad_Opcode },
3418     { "sarQ",   { Ev, I1 }, 0 },
3419   },
3420   /* REG_D2 */
3421   {
3422     { "rolA",   { Eb, CL }, 0 },
3423     { "rorA",   { Eb, CL }, 0 },
3424     { "rclA",   { Eb, CL }, 0 },
3425     { "rcrA",   { Eb, CL }, 0 },
3426     { "shlA",   { Eb, CL }, 0 },
3427     { "shrA",   { Eb, CL }, 0 },
3428     { Bad_Opcode },
3429     { "sarA",   { Eb, CL }, 0 },
3430   },
3431   /* REG_D3 */
3432   {
3433     { "rolQ",   { Ev, CL }, 0 },
3434     { "rorQ",   { Ev, CL }, 0 },
3435     { "rclQ",   { Ev, CL }, 0 },
3436     { "rcrQ",   { Ev, CL }, 0 },
3437     { "shlQ",   { Ev, CL }, 0 },
3438     { "shrQ",   { Ev, CL }, 0 },
3439     { Bad_Opcode },
3440     { "sarQ",   { Ev, CL }, 0 },
3441   },
3442   /* REG_F6 */
3443   {
3444     { "testA",  { Eb, Ib }, 0 },
3445     { Bad_Opcode },
3446     { "notA",   { Ebh1 }, 0 },
3447     { "negA",   { Ebh1 }, 0 },
3448     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3449     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3450     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3451     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3452   },
3453   /* REG_F7 */
3454   {
3455     { "testQ",  { Ev, Iv }, 0 },
3456     { Bad_Opcode },
3457     { "notQ",   { Evh1 }, 0 },
3458     { "negQ",   { Evh1 }, 0 },
3459     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3460     { "imulQ",  { Ev }, 0 },
3461     { "divQ",   { Ev }, 0 },
3462     { "idivQ",  { Ev }, 0 },
3463   },
3464   /* REG_FE */
3465   {
3466     { "incA",   { Ebh1 }, 0 },
3467     { "decA",   { Ebh1 }, 0 },
3468   },
3469   /* REG_FF */
3470   {
3471     { "incQ",   { Evh1 }, 0 },
3472     { "decQ",   { Evh1 }, 0 },
3473     { "call{T|}", { indirEv, BND }, 0 },
3474     { MOD_TABLE (MOD_FF_REG_3) },
3475     { "jmp{T|}", { indirEv, BND }, 0 },
3476     { MOD_TABLE (MOD_FF_REG_5) },
3477     { "pushU",  { stackEv }, 0 },
3478     { Bad_Opcode },
3479   },
3480   /* REG_0F00 */
3481   {
3482     { "sldtD",  { Sv }, 0 },
3483     { "strD",   { Sv }, 0 },
3484     { "lldt",   { Ew }, 0 },
3485     { "ltr",    { Ew }, 0 },
3486     { "verr",   { Ew }, 0 },
3487     { "verw",   { Ew }, 0 },
3488     { Bad_Opcode },
3489     { Bad_Opcode },
3490   },
3491   /* REG_0F01 */
3492   {
3493     { MOD_TABLE (MOD_0F01_REG_0) },
3494     { MOD_TABLE (MOD_0F01_REG_1) },
3495     { MOD_TABLE (MOD_0F01_REG_2) },
3496     { MOD_TABLE (MOD_0F01_REG_3) },
3497     { "smswD",  { Sv }, 0 },
3498     { Bad_Opcode },
3499     { "lmsw",   { Ew }, 0 },
3500     { MOD_TABLE (MOD_0F01_REG_7) },
3501   },
3502   /* REG_0F0D */
3503   {
3504     { "prefetch",       { Mb }, 0 },
3505     { "prefetchw",      { Mb }, 0 },
3506     { "prefetchwt1",    { Mb }, 0 },
3507     { "prefetch",       { Mb }, 0 },
3508     { "prefetch",       { Mb }, 0 },
3509     { "prefetch",       { Mb }, 0 },
3510     { "prefetch",       { Mb }, 0 },
3511     { "prefetch",       { Mb }, 0 },
3512   },
3513   /* REG_0F18 */
3514   {
3515     { MOD_TABLE (MOD_0F18_REG_0) },
3516     { MOD_TABLE (MOD_0F18_REG_1) },
3517     { MOD_TABLE (MOD_0F18_REG_2) },
3518     { MOD_TABLE (MOD_0F18_REG_3) },
3519     { MOD_TABLE (MOD_0F18_REG_4) },
3520     { MOD_TABLE (MOD_0F18_REG_5) },
3521     { MOD_TABLE (MOD_0F18_REG_6) },
3522     { MOD_TABLE (MOD_0F18_REG_7) },
3523   },
3524   /* REG_0F71 */
3525   {
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_0F71_REG_2) },
3529     { Bad_Opcode },
3530     { MOD_TABLE (MOD_0F71_REG_4) },
3531     { Bad_Opcode },
3532     { MOD_TABLE (MOD_0F71_REG_6) },
3533   },
3534   /* REG_0F72 */
3535   {
3536     { Bad_Opcode },
3537     { Bad_Opcode },
3538     { MOD_TABLE (MOD_0F72_REG_2) },
3539     { Bad_Opcode },
3540     { MOD_TABLE (MOD_0F72_REG_4) },
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_0F72_REG_6) },
3543   },
3544   /* REG_0F73 */
3545   {
3546     { Bad_Opcode },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_0F73_REG_2) },
3549     { MOD_TABLE (MOD_0F73_REG_3) },
3550     { Bad_Opcode },
3551     { Bad_Opcode },
3552     { MOD_TABLE (MOD_0F73_REG_6) },
3553     { MOD_TABLE (MOD_0F73_REG_7) },
3554   },
3555   /* REG_0FA6 */
3556   {
3557     { "montmul",        { { OP_0f07, 0 } }, 0 },
3558     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3559     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3560   },
3561   /* REG_0FA7 */
3562   {
3563     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3564     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3565     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3566     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3567     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3568     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3569   },
3570   /* REG_0FAE */
3571   {
3572     { MOD_TABLE (MOD_0FAE_REG_0) },
3573     { MOD_TABLE (MOD_0FAE_REG_1) },
3574     { MOD_TABLE (MOD_0FAE_REG_2) },
3575     { MOD_TABLE (MOD_0FAE_REG_3) },
3576     { MOD_TABLE (MOD_0FAE_REG_4) },
3577     { MOD_TABLE (MOD_0FAE_REG_5) },
3578     { MOD_TABLE (MOD_0FAE_REG_6) },
3579     { MOD_TABLE (MOD_0FAE_REG_7) },
3580   },
3581   /* REG_0FBA */
3582   {
3583     { Bad_Opcode },
3584     { Bad_Opcode },
3585     { Bad_Opcode },
3586     { Bad_Opcode },
3587     { "btQ",    { Ev, Ib }, 0 },
3588     { "btsQ",   { Evh1, Ib }, 0 },
3589     { "btrQ",   { Evh1, Ib }, 0 },
3590     { "btcQ",   { Evh1, Ib }, 0 },
3591   },
3592   /* REG_0FC7 */
3593   {
3594     { Bad_Opcode },
3595     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_0FC7_REG_3) },
3598     { MOD_TABLE (MOD_0FC7_REG_4) },
3599     { MOD_TABLE (MOD_0FC7_REG_5) },
3600     { MOD_TABLE (MOD_0FC7_REG_6) },
3601     { MOD_TABLE (MOD_0FC7_REG_7) },
3602   },
3603   /* REG_VEX_0F71 */
3604   {
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3608     { Bad_Opcode },
3609     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3610     { Bad_Opcode },
3611     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3612   },
3613   /* REG_VEX_0F72 */
3614   {
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3618     { Bad_Opcode },
3619     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3620     { Bad_Opcode },
3621     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3622   },
3623   /* REG_VEX_0F73 */
3624   {
3625     { Bad_Opcode },
3626     { Bad_Opcode },
3627     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3628     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3629     { Bad_Opcode },
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3632     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3633   },
3634   /* REG_VEX_0FAE */
3635   {
3636     { Bad_Opcode },
3637     { Bad_Opcode },
3638     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3639     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3640   },
3641   /* REG_VEX_0F38F3 */
3642   {
3643     { Bad_Opcode },
3644     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3645     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3646     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3647   },
3648   /* REG_XOP_LWPCB */
3649   {
3650     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3651     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3652   },
3653   /* REG_XOP_LWP */
3654   {
3655     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3656     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3657   },
3658   /* REG_XOP_TBM_01 */
3659   {
3660     { Bad_Opcode },
3661     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3662     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3663     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3664     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3665     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3666     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3667     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3668   },
3669   /* REG_XOP_TBM_02 */
3670   {
3671     { Bad_Opcode },
3672     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3673     { Bad_Opcode },
3674     { Bad_Opcode },
3675     { Bad_Opcode },
3676     { Bad_Opcode },
3677     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3678   },
3679 #define NEED_REG_TABLE
3680 #include "i386-dis-evex.h"
3681 #undef NEED_REG_TABLE
3682 };
3683
3684 static const struct dis386 prefix_table[][4] = {
3685   /* PREFIX_90 */
3686   {
3687     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3688     { "pause", { XX }, 0 },
3689     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3690     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3691   },
3692
3693   /* PREFIX_0F10 */
3694   {
3695     { "movups", { XM, EXx }, PREFIX_OPCODE },
3696     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3697     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3698     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3699   },
3700
3701   /* PREFIX_0F11 */
3702   {
3703     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3704     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3705     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3706     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3707   },
3708
3709   /* PREFIX_0F12 */
3710   {
3711     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3712     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3713     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3714     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3715   },
3716
3717   /* PREFIX_0F16 */
3718   {
3719     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3720     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3721     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3722   },
3723
3724   /* PREFIX_0F1A */
3725   {
3726     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3727     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3728     { "bndmov", { Gbnd, Ebnd }, 0 },
3729     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3730   },
3731
3732   /* PREFIX_0F1B */
3733   {
3734     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3735     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3736     { "bndmov", { Ebnd, Gbnd }, 0 },
3737     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3738   },
3739
3740   /* PREFIX_0F2A */
3741   {
3742     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3743     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3744     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3745     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3746   },
3747
3748   /* PREFIX_0F2B */
3749   {
3750     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3751     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3752     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3753     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3754   },
3755
3756   /* PREFIX_0F2C */
3757   {
3758     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3759     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3760     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3761     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3762   },
3763
3764   /* PREFIX_0F2D */
3765   {
3766     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3767     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3768     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3769     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3770   },
3771
3772   /* PREFIX_0F2E */
3773   {
3774     { "ucomiss",{ XM, EXd }, 0 },
3775     { Bad_Opcode },
3776     { "ucomisd",{ XM, EXq }, 0 },
3777   },
3778
3779   /* PREFIX_0F2F */
3780   {
3781     { "comiss", { XM, EXd }, 0 },
3782     { Bad_Opcode },
3783     { "comisd", { XM, EXq }, 0 },
3784   },
3785
3786   /* PREFIX_0F51 */
3787   {
3788     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3789     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3790     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3791     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3792   },
3793
3794   /* PREFIX_0F52 */
3795   {
3796     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3797     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3798   },
3799
3800   /* PREFIX_0F53 */
3801   {
3802     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3803     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3804   },
3805
3806   /* PREFIX_0F58 */
3807   {
3808     { "addps", { XM, EXx }, PREFIX_OPCODE },
3809     { "addss", { XM, EXd }, PREFIX_OPCODE },
3810     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3811     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F59 */
3815   {
3816     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3817     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3818     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3819     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F5A */
3823   {
3824     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3825     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3826     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3827     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3828   },
3829
3830   /* PREFIX_0F5B */
3831   {
3832     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3833     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3834     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3835   },
3836
3837   /* PREFIX_0F5C */
3838   {
3839     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3840     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3841     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3842     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0F5D */
3846   {
3847     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3848     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3849     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3850     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F5E */
3854   {
3855     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3856     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3857     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3858     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F5F */
3862   {
3863     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3864     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3865     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3866     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F60 */
3870   {
3871     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3872     { Bad_Opcode },
3873     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F61 */
3877   {
3878     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3879     { Bad_Opcode },
3880     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F62 */
3884   {
3885     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3886     { Bad_Opcode },
3887     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0F6C */
3891   {
3892     { Bad_Opcode },
3893     { Bad_Opcode },
3894     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3895   },
3896
3897   /* PREFIX_0F6D */
3898   {
3899     { Bad_Opcode },
3900     { Bad_Opcode },
3901     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3902   },
3903
3904   /* PREFIX_0F6F */
3905   {
3906     { "movq",   { MX, EM }, PREFIX_OPCODE },
3907     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3908     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3909   },
3910
3911   /* PREFIX_0F70 */
3912   {
3913     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3914     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3915     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3916     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3917   },
3918
3919   /* PREFIX_0F73_REG_3 */
3920   {
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { "psrldq", { XS, Ib }, 0 },
3924   },
3925
3926   /* PREFIX_0F73_REG_7 */
3927   {
3928     { Bad_Opcode },
3929     { Bad_Opcode },
3930     { "pslldq", { XS, Ib }, 0 },
3931   },
3932
3933   /* PREFIX_0F78 */
3934   {
3935     {"vmread",  { Em, Gm }, 0 },
3936     { Bad_Opcode },
3937     {"extrq",   { XS, Ib, Ib }, 0 },
3938     {"insertq", { XM, XS, Ib, Ib }, 0 },
3939   },
3940
3941   /* PREFIX_0F79 */
3942   {
3943     {"vmwrite", { Gm, Em }, 0 },
3944     { Bad_Opcode },
3945     {"extrq",   { XM, XS }, 0 },
3946     {"insertq", { XM, XS }, 0 },
3947   },
3948
3949   /* PREFIX_0F7C */
3950   {
3951     { Bad_Opcode },
3952     { Bad_Opcode },
3953     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3954     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3955   },
3956
3957   /* PREFIX_0F7D */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3962     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F7E */
3966   {
3967     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3968     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3969     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F7F */
3973   {
3974     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3975     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3976     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0FAE_REG_0 */
3980   {
3981     { Bad_Opcode },
3982     { "rdfsbase", { Ev }, 0 },
3983   },
3984
3985   /* PREFIX_0FAE_REG_1 */
3986   {
3987     { Bad_Opcode },
3988     { "rdgsbase", { Ev }, 0 },
3989   },
3990
3991   /* PREFIX_0FAE_REG_2 */
3992   {
3993     { Bad_Opcode },
3994     { "wrfsbase", { Ev }, 0 },
3995   },
3996
3997   /* PREFIX_0FAE_REG_3 */
3998   {
3999     { Bad_Opcode },
4000     { "wrgsbase", { Ev }, 0 },
4001   },
4002
4003   /* PREFIX_0FAE_REG_6 */
4004   {
4005     { "xsaveopt",      { FXSAVE }, 0 },
4006     { Bad_Opcode },
4007     { "clwb",   { Mb }, 0 },
4008   },
4009
4010   /* PREFIX_0FAE_REG_7 */
4011   {
4012     { "clflush",        { Mb }, 0 },
4013     { Bad_Opcode },
4014     { "clflushopt",     { Mb }, 0 },
4015   },
4016
4017   /* PREFIX_RM_0_0FAE_REG_7 */
4018   {
4019     { "sfence",         { Skip_MODRM }, 0 },
4020     { Bad_Opcode },
4021     { "pcommit",                { Skip_MODRM }, 0 },
4022   },
4023
4024   /* PREFIX_0FB8 */
4025   {
4026     { Bad_Opcode },
4027     { "popcntS", { Gv, Ev }, 0 },
4028   },
4029
4030   /* PREFIX_0FBC */
4031   {
4032     { "bsfS",   { Gv, Ev }, 0 },
4033     { "tzcntS", { Gv, Ev }, 0 },
4034     { "bsfS",   { Gv, Ev }, 0 },
4035   },
4036
4037   /* PREFIX_0FBD */
4038   {
4039     { "bsrS",   { Gv, Ev }, 0 },
4040     { "lzcntS", { Gv, Ev }, 0 },
4041     { "bsrS",   { Gv, Ev }, 0 },
4042   },
4043
4044   /* PREFIX_0FC2 */
4045   {
4046     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4047     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4048     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4049     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4050   },
4051
4052   /* PREFIX_MOD_0_0FC3 */
4053   {
4054     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4055   },
4056
4057   /* PREFIX_MOD_0_0FC7_REG_6 */
4058   {
4059     { "vmptrld",{ Mq }, 0 },
4060     { "vmxon",  { Mq }, 0 },
4061     { "vmclear",{ Mq }, 0 },
4062   },
4063
4064   /* PREFIX_MOD_3_0FC7_REG_6 */
4065   {
4066     { "rdrand", { Ev }, 0 },
4067     { Bad_Opcode },
4068     { "rdrand", { Ev }, 0 }
4069   },
4070
4071   /* PREFIX_MOD_3_0FC7_REG_7 */
4072   {
4073     { "rdseed", { Ev }, 0 },
4074     { Bad_Opcode },
4075     { "rdseed", { Ev }, 0 },
4076   },
4077
4078   /* PREFIX_0FD0 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { "addsubpd", { XM, EXx }, 0 },
4083     { "addsubps", { XM, EXx }, 0 },
4084   },
4085
4086   /* PREFIX_0FD6 */
4087   {
4088     { Bad_Opcode },
4089     { "movq2dq",{ XM, MS }, 0 },
4090     { "movq",   { EXqS, XM }, 0 },
4091     { "movdq2q",{ MX, XS }, 0 },
4092   },
4093
4094   /* PREFIX_0FE6 */
4095   {
4096     { Bad_Opcode },
4097     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4098     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4099     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4100   },
4101
4102   /* PREFIX_0FE7 */
4103   {
4104     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4105     { Bad_Opcode },
4106     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4107   },
4108
4109   /* PREFIX_0FF0 */
4110   {
4111     { Bad_Opcode },
4112     { Bad_Opcode },
4113     { Bad_Opcode },
4114     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4115   },
4116
4117   /* PREFIX_0FF7 */
4118   {
4119     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4120     { Bad_Opcode },
4121     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_0F3810 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4129   },
4130
4131   /* PREFIX_0F3814 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4136   },
4137
4138   /* PREFIX_0F3815 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0F3817 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0F3820 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F3821 */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F3822 */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F3823 */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F3824 */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0F3825 */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4192   },
4193
4194   /* PREFIX_0F3828 */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0F3829 */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4206   },
4207
4208   /* PREFIX_0F382A */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4213   },
4214
4215   /* PREFIX_0F382B */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_0F3830 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0F3831 */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_0F3832 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0F3833 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4248   },
4249
4250   /* PREFIX_0F3834 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4255   },
4256
4257   /* PREFIX_0F3835 */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F3837 */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F3838 */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0F3839 */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4283   },
4284
4285   /* PREFIX_0F383A */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4290   },
4291
4292   /* PREFIX_0F383B */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4297   },
4298
4299   /* PREFIX_0F383C */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4304   },
4305
4306   /* PREFIX_0F383D */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4311   },
4312
4313   /* PREFIX_0F383E */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4318   },
4319
4320   /* PREFIX_0F383F */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4325   },
4326
4327   /* PREFIX_0F3840 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0F3841 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F3880 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F3881 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F3882 */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F38C8 */
4363   {
4364     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F38C9 */
4368   {
4369     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F38CA */
4373   {
4374     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F38CB */
4378   {
4379     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38CC */
4383   {
4384     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F38CD */
4388   {
4389     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F38DB */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F38DC */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F38DD */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F38DE */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F38DF */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F38F0 */
4428   {
4429     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4430     { Bad_Opcode },
4431     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4432     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F38F1 */
4436   {
4437     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4438     { Bad_Opcode },
4439     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4440     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4441   },
4442
4443   /* PREFIX_0F38F6 */
4444   {
4445     { Bad_Opcode },
4446     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4447     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4448     { Bad_Opcode },
4449   },
4450
4451   /* PREFIX_0F3A08 */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4456   },
4457
4458   /* PREFIX_0F3A09 */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4463   },
4464
4465   /* PREFIX_0F3A0A */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4470   },
4471
4472   /* PREFIX_0F3A0B */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4477   },
4478
4479   /* PREFIX_0F3A0C */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F3A0D */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3A0E */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3A14 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3A15 */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F3A16 */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F3A17 */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F3A20 */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_0F3A21 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F3A22 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4547   },
4548
4549   /* PREFIX_0F3A40 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F3A41 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F3A42 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F3A44 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F3A60 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4582   },
4583
4584   /* PREFIX_0F3A61 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4589   },
4590
4591   /* PREFIX_0F3A62 */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4596   },
4597
4598   /* PREFIX_0F3A63 */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4603   },
4604
4605   /* PREFIX_0F3ACC */
4606   {
4607     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3ADF */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_VEX_0F10 */
4618   {
4619     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4620     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4621     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4622     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4623   },
4624
4625   /* PREFIX_VEX_0F11 */
4626   {
4627     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4628     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4629     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4630     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4631   },
4632
4633   /* PREFIX_VEX_0F12 */
4634   {
4635     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4636     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4637     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4638     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4639   },
4640
4641   /* PREFIX_VEX_0F16 */
4642   {
4643     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4644     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4645     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4646   },
4647
4648   /* PREFIX_VEX_0F2A */
4649   {
4650     { Bad_Opcode },
4651     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4652     { Bad_Opcode },
4653     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4654   },
4655
4656   /* PREFIX_VEX_0F2C */
4657   {
4658     { Bad_Opcode },
4659     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4660     { Bad_Opcode },
4661     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4662   },
4663
4664   /* PREFIX_VEX_0F2D */
4665   {
4666     { Bad_Opcode },
4667     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4668     { Bad_Opcode },
4669     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4670   },
4671
4672   /* PREFIX_VEX_0F2E */
4673   {
4674     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4675     { Bad_Opcode },
4676     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4677   },
4678
4679   /* PREFIX_VEX_0F2F */
4680   {
4681     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4684   },
4685
4686   /* PREFIX_VEX_0F41 */
4687   {
4688     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4689     { Bad_Opcode },
4690     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4691   },
4692
4693   /* PREFIX_VEX_0F42 */
4694   {
4695     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4696     { Bad_Opcode },
4697     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F44 */
4701   {
4702     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4703     { Bad_Opcode },
4704     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4705   },
4706
4707   /* PREFIX_VEX_0F45 */
4708   {
4709     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4710     { Bad_Opcode },
4711     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4712   },
4713
4714   /* PREFIX_VEX_0F46 */
4715   {
4716     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4717     { Bad_Opcode },
4718     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4719   },
4720
4721   /* PREFIX_VEX_0F47 */
4722   {
4723     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4724     { Bad_Opcode },
4725     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4726   },
4727
4728   /* PREFIX_VEX_0F4A */
4729   {
4730     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4731     { Bad_Opcode },
4732     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4733   },
4734
4735   /* PREFIX_VEX_0F4B */
4736   {
4737     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4738     { Bad_Opcode },
4739     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4740   },
4741
4742   /* PREFIX_VEX_0F51 */
4743   {
4744     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4745     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4746     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4747     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4748   },
4749
4750   /* PREFIX_VEX_0F52 */
4751   {
4752     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4753     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4754   },
4755
4756   /* PREFIX_VEX_0F53 */
4757   {
4758     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4759     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4760   },
4761
4762   /* PREFIX_VEX_0F58 */
4763   {
4764     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4765     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4766     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4767     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4768   },
4769
4770   /* PREFIX_VEX_0F59 */
4771   {
4772     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4773     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4774     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4775     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4776   },
4777
4778   /* PREFIX_VEX_0F5A */
4779   {
4780     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4781     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4782     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4783     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4784   },
4785
4786   /* PREFIX_VEX_0F5B */
4787   {
4788     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4789     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4790     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4791   },
4792
4793   /* PREFIX_VEX_0F5C */
4794   {
4795     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4796     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4797     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4798     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4799   },
4800
4801   /* PREFIX_VEX_0F5D */
4802   {
4803     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4804     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4805     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4806     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4807   },
4808
4809   /* PREFIX_VEX_0F5E */
4810   {
4811     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4812     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4813     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4814     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4815   },
4816
4817   /* PREFIX_VEX_0F5F */
4818   {
4819     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4820     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4821     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4822     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4823   },
4824
4825   /* PREFIX_VEX_0F60 */
4826   {
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4830   },
4831
4832   /* PREFIX_VEX_0F61 */
4833   {
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4837   },
4838
4839   /* PREFIX_VEX_0F62 */
4840   {
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4844   },
4845
4846   /* PREFIX_VEX_0F63 */
4847   {
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4851   },
4852
4853   /* PREFIX_VEX_0F64 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4858   },
4859
4860   /* PREFIX_VEX_0F65 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4865   },
4866
4867   /* PREFIX_VEX_0F66 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4872   },
4873
4874   /* PREFIX_VEX_0F67 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4879   },
4880
4881   /* PREFIX_VEX_0F68 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0F69 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0F6A */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0F6B */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F6C */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4914   },
4915
4916   /* PREFIX_VEX_0F6D */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4921   },
4922
4923   /* PREFIX_VEX_0F6E */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0F6F */
4931   {
4932     { Bad_Opcode },
4933     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4934     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4935   },
4936
4937   /* PREFIX_VEX_0F70 */
4938   {
4939     { Bad_Opcode },
4940     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4941     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4942     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4943   },
4944
4945   /* PREFIX_VEX_0F71_REG_2 */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0F71_REG_4 */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4957   },
4958
4959   /* PREFIX_VEX_0F71_REG_6 */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4964   },
4965
4966   /* PREFIX_VEX_0F72_REG_2 */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0F72_REG_4 */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0F72_REG_6 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0F73_REG_2 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4992   },
4993
4994   /* PREFIX_VEX_0F73_REG_3 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4999   },
5000
5001   /* PREFIX_VEX_0F73_REG_6 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5006   },
5007
5008   /* PREFIX_VEX_0F73_REG_7 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5013   },
5014
5015   /* PREFIX_VEX_0F74 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5020   },
5021
5022   /* PREFIX_VEX_0F75 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5027   },
5028
5029   /* PREFIX_VEX_0F76 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5034   },
5035
5036   /* PREFIX_VEX_0F77 */
5037   {
5038     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5039   },
5040
5041   /* PREFIX_VEX_0F7C */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5046     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5047   },
5048
5049   /* PREFIX_VEX_0F7D */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5054     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5055   },
5056
5057   /* PREFIX_VEX_0F7E */
5058   {
5059     { Bad_Opcode },
5060     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5061     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0F7F */
5065   {
5066     { Bad_Opcode },
5067     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5068     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0F90 */
5072   {
5073     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5074     { Bad_Opcode },
5075     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0F91 */
5079   {
5080     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5081     { Bad_Opcode },
5082     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0F92 */
5086   {
5087     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5088     { Bad_Opcode },
5089     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5090     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5091   },
5092
5093   /* PREFIX_VEX_0F93 */
5094   {
5095     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5096     { Bad_Opcode },
5097     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5098     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5099   },
5100
5101   /* PREFIX_VEX_0F98 */
5102   {
5103     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F99 */
5109   {
5110     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5111     { Bad_Opcode },
5112     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0FC2 */
5116   {
5117     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5118     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5119     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5120     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5121   },
5122
5123   /* PREFIX_VEX_0FC4 */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0FC5 */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0FD0 */
5138   {
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5142     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5143   },
5144
5145   /* PREFIX_VEX_0FD1 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0FD2 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0FD3 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0FD4 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_0FD5 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_0FD6 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_0FD7 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5192   },
5193
5194   /* PREFIX_VEX_0FD8 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_0FD9 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5206   },
5207
5208   /* PREFIX_VEX_0FDA */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_0FDB */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_0FDC */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_0FDD */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5234   },
5235
5236   /* PREFIX_VEX_0FDE */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_0FDF */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5248   },
5249
5250   /* PREFIX_VEX_0FE0 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5255   },
5256
5257   /* PREFIX_VEX_0FE1 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_0FE2 */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_0FE3 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_0FE4 */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5283   },
5284
5285   /* PREFIX_VEX_0FE5 */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5290   },
5291
5292   /* PREFIX_VEX_0FE6 */
5293   {
5294     { Bad_Opcode },
5295     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5296     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5297     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5298   },
5299
5300   /* PREFIX_VEX_0FE7 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5305   },
5306
5307   /* PREFIX_VEX_0FE8 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5312   },
5313
5314   /* PREFIX_VEX_0FE9 */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5319   },
5320
5321   /* PREFIX_VEX_0FEA */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FEB */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5333   },
5334
5335   /* PREFIX_VEX_0FEC */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5340   },
5341
5342   /* PREFIX_VEX_0FED */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5347   },
5348
5349   /* PREFIX_VEX_0FEE */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5354   },
5355
5356   /* PREFIX_VEX_0FEF */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5361   },
5362
5363   /* PREFIX_VEX_0FF0 */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5369   },
5370
5371   /* PREFIX_VEX_0FF1 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5376   },
5377
5378   /* PREFIX_VEX_0FF2 */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5383   },
5384
5385   /* PREFIX_VEX_0FF3 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5390   },
5391
5392   /* PREFIX_VEX_0FF4 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FF5 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5404   },
5405
5406   /* PREFIX_VEX_0FF6 */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5411   },
5412
5413   /* PREFIX_VEX_0FF7 */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5418   },
5419
5420   /* PREFIX_VEX_0FF8 */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5425   },
5426
5427   /* PREFIX_VEX_0FF9 */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5432   },
5433
5434   /* PREFIX_VEX_0FFA */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5439   },
5440
5441   /* PREFIX_VEX_0FFB */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5446   },
5447
5448   /* PREFIX_VEX_0FFC */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5453   },
5454
5455   /* PREFIX_VEX_0FFD */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0FFE */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0F3800 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0F3801 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5481   },
5482
5483   /* PREFIX_VEX_0F3802 */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5488   },
5489
5490   /* PREFIX_VEX_0F3803 */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5495   },
5496
5497   /* PREFIX_VEX_0F3804 */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5502   },
5503
5504   /* PREFIX_VEX_0F3805 */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5509   },
5510
5511   /* PREFIX_VEX_0F3806 */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5516   },
5517
5518   /* PREFIX_VEX_0F3807 */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5523   },
5524
5525   /* PREFIX_VEX_0F3808 */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5530   },
5531
5532   /* PREFIX_VEX_0F3809 */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5537   },
5538
5539   /* PREFIX_VEX_0F380A */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5544   },
5545
5546   /* PREFIX_VEX_0F380B */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5551   },
5552
5553   /* PREFIX_VEX_0F380C */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5558   },
5559
5560   /* PREFIX_VEX_0F380D */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5565   },
5566
5567   /* PREFIX_VEX_0F380E */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5572   },
5573
5574   /* PREFIX_VEX_0F380F */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5579   },
5580
5581   /* PREFIX_VEX_0F3813 */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5586   },
5587
5588   /* PREFIX_VEX_0F3816 */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5593   },
5594
5595   /* PREFIX_VEX_0F3817 */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5600   },
5601
5602   /* PREFIX_VEX_0F3818 */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5607   },
5608
5609   /* PREFIX_VEX_0F3819 */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5614   },
5615
5616   /* PREFIX_VEX_0F381A */
5617   {
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5621   },
5622
5623   /* PREFIX_VEX_0F381C */
5624   {
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5628   },
5629
5630   /* PREFIX_VEX_0F381D */
5631   {
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5635   },
5636
5637   /* PREFIX_VEX_0F381E */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5642   },
5643
5644   /* PREFIX_VEX_0F3820 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5649   },
5650
5651   /* PREFIX_VEX_0F3821 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5656   },
5657
5658   /* PREFIX_VEX_0F3822 */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5663   },
5664
5665   /* PREFIX_VEX_0F3823 */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5670   },
5671
5672   /* PREFIX_VEX_0F3824 */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5677   },
5678
5679   /* PREFIX_VEX_0F3825 */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5684   },
5685
5686   /* PREFIX_VEX_0F3828 */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5691   },
5692
5693   /* PREFIX_VEX_0F3829 */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5698   },
5699
5700   /* PREFIX_VEX_0F382A */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5705   },
5706
5707   /* PREFIX_VEX_0F382B */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5712   },
5713
5714   /* PREFIX_VEX_0F382C */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5719   },
5720
5721   /* PREFIX_VEX_0F382D */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5726   },
5727
5728   /* PREFIX_VEX_0F382E */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5733   },
5734
5735   /* PREFIX_VEX_0F382F */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5740   },
5741
5742   /* PREFIX_VEX_0F3830 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5747   },
5748
5749   /* PREFIX_VEX_0F3831 */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5754   },
5755
5756   /* PREFIX_VEX_0F3832 */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5761   },
5762
5763   /* PREFIX_VEX_0F3833 */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5768   },
5769
5770   /* PREFIX_VEX_0F3834 */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5775   },
5776
5777   /* PREFIX_VEX_0F3835 */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5782   },
5783
5784   /* PREFIX_VEX_0F3836 */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5789   },
5790
5791   /* PREFIX_VEX_0F3837 */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5796   },
5797
5798   /* PREFIX_VEX_0F3838 */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5803   },
5804
5805   /* PREFIX_VEX_0F3839 */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5810   },
5811
5812   /* PREFIX_VEX_0F383A */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5817   },
5818
5819   /* PREFIX_VEX_0F383B */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5824   },
5825
5826   /* PREFIX_VEX_0F383C */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5831   },
5832
5833   /* PREFIX_VEX_0F383D */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5838   },
5839
5840   /* PREFIX_VEX_0F383E */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5845   },
5846
5847   /* PREFIX_VEX_0F383F */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5852   },
5853
5854   /* PREFIX_VEX_0F3840 */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5859   },
5860
5861   /* PREFIX_VEX_0F3841 */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5866   },
5867
5868   /* PREFIX_VEX_0F3845 */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5873   },
5874
5875   /* PREFIX_VEX_0F3846 */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5880   },
5881
5882   /* PREFIX_VEX_0F3847 */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5887   },
5888
5889   /* PREFIX_VEX_0F3858 */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5894   },
5895
5896   /* PREFIX_VEX_0F3859 */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5901   },
5902
5903   /* PREFIX_VEX_0F385A */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5908   },
5909
5910   /* PREFIX_VEX_0F3878 */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5915   },
5916
5917   /* PREFIX_VEX_0F3879 */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5922   },
5923
5924   /* PREFIX_VEX_0F388C */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5929   },
5930
5931   /* PREFIX_VEX_0F388E */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5936   },
5937
5938   /* PREFIX_VEX_0F3890 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5943   },
5944
5945   /* PREFIX_VEX_0F3891 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5950   },
5951
5952   /* PREFIX_VEX_0F3892 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5957   },
5958
5959   /* PREFIX_VEX_0F3893 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5964   },
5965
5966   /* PREFIX_VEX_0F3896 */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5971   },
5972
5973   /* PREFIX_VEX_0F3897 */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5978   },
5979
5980   /* PREFIX_VEX_0F3898 */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5985   },
5986
5987   /* PREFIX_VEX_0F3899 */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F389A */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F389B */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F389C */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F389D */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F389E */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F389F */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F38A6 */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6041     { Bad_Opcode },
6042   },
6043
6044   /* PREFIX_VEX_0F38A7 */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6049   },
6050
6051   /* PREFIX_VEX_0F38A8 */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6056   },
6057
6058   /* PREFIX_VEX_0F38A9 */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6063   },
6064
6065   /* PREFIX_VEX_0F38AA */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6070   },
6071
6072   /* PREFIX_VEX_0F38AB */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6077   },
6078
6079   /* PREFIX_VEX_0F38AC */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6084   },
6085
6086   /* PREFIX_VEX_0F38AD */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F38AE */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F38AF */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F38B6 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F38B7 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F38B8 */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F38B9 */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F38BA */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F38BB */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F38BC */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F38BD */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F38BE */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F38BF */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F38DB */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6182   },
6183
6184   /* PREFIX_VEX_0F38DC */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6189   },
6190
6191   /* PREFIX_VEX_0F38DD */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6196   },
6197
6198   /* PREFIX_VEX_0F38DE */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6203   },
6204
6205   /* PREFIX_VEX_0F38DF */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6210   },
6211
6212   /* PREFIX_VEX_0F38F2 */
6213   {
6214     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6215   },
6216
6217   /* PREFIX_VEX_0F38F3_REG_1 */
6218   {
6219     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6220   },
6221
6222   /* PREFIX_VEX_0F38F3_REG_2 */
6223   {
6224     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6225   },
6226
6227   /* PREFIX_VEX_0F38F3_REG_3 */
6228   {
6229     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6230   },
6231
6232   /* PREFIX_VEX_0F38F5 */
6233   {
6234     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6235     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6236     { Bad_Opcode },
6237     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6238   },
6239
6240   /* PREFIX_VEX_0F38F6 */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6246   },
6247
6248   /* PREFIX_VEX_0F38F7 */
6249   {
6250     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6251     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6252     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6253     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6254   },
6255
6256   /* PREFIX_VEX_0F3A00 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6261   },
6262
6263   /* PREFIX_VEX_0F3A01 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6268   },
6269
6270   /* PREFIX_VEX_0F3A02 */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6275   },
6276
6277   /* PREFIX_VEX_0F3A04 */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6282   },
6283
6284   /* PREFIX_VEX_0F3A05 */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6289   },
6290
6291   /* PREFIX_VEX_0F3A06 */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6296   },
6297
6298   /* PREFIX_VEX_0F3A08 */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6303   },
6304
6305   /* PREFIX_VEX_0F3A09 */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6310   },
6311
6312   /* PREFIX_VEX_0F3A0A */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A0B */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F3A0C */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F3A0D */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A0E */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A0F */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6352   },
6353
6354   /* PREFIX_VEX_0F3A14 */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6359   },
6360
6361   /* PREFIX_VEX_0F3A15 */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6366   },
6367
6368   /* PREFIX_VEX_0F3A16 */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6373   },
6374
6375   /* PREFIX_VEX_0F3A17 */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6380   },
6381
6382   /* PREFIX_VEX_0F3A18 */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6387   },
6388
6389   /* PREFIX_VEX_0F3A19 */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6394   },
6395
6396   /* PREFIX_VEX_0F3A1D */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6401   },
6402
6403   /* PREFIX_VEX_0F3A20 */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6408   },
6409
6410   /* PREFIX_VEX_0F3A21 */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6415   },
6416
6417   /* PREFIX_VEX_0F3A22 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A30 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A31 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A32 */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A33 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6450   },
6451
6452   /* PREFIX_VEX_0F3A38 */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6457   },
6458
6459   /* PREFIX_VEX_0F3A39 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6464   },
6465
6466   /* PREFIX_VEX_0F3A40 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6471   },
6472
6473   /* PREFIX_VEX_0F3A41 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6478   },
6479
6480   /* PREFIX_VEX_0F3A42 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A44 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A46 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A48 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A49 */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6513   },
6514
6515   /* PREFIX_VEX_0F3A4A */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6520   },
6521
6522   /* PREFIX_VEX_0F3A4B */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6527   },
6528
6529   /* PREFIX_VEX_0F3A4C */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6534   },
6535
6536   /* PREFIX_VEX_0F3A5C */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6541   },
6542
6543   /* PREFIX_VEX_0F3A5D */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6548   },
6549
6550   /* PREFIX_VEX_0F3A5E */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6555   },
6556
6557   /* PREFIX_VEX_0F3A5F */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6562   },
6563
6564   /* PREFIX_VEX_0F3A60 */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6569     { Bad_Opcode },
6570   },
6571
6572   /* PREFIX_VEX_0F3A61 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A62 */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A63 */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6591   },
6592
6593   /* PREFIX_VEX_0F3A68 */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6598   },
6599
6600   /* PREFIX_VEX_0F3A69 */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6605   },
6606
6607   /* PREFIX_VEX_0F3A6A */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6612   },
6613
6614   /* PREFIX_VEX_0F3A6B */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3A6C */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6626   },
6627
6628   /* PREFIX_VEX_0F3A6D */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6633   },
6634
6635   /* PREFIX_VEX_0F3A6E */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A6F */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A78 */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6654   },
6655
6656   /* PREFIX_VEX_0F3A79 */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6661   },
6662
6663   /* PREFIX_VEX_0F3A7A */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A7B */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6675   },
6676
6677   /* PREFIX_VEX_0F3A7C */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6682     { Bad_Opcode },
6683   },
6684
6685   /* PREFIX_VEX_0F3A7D */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6690   },
6691
6692   /* PREFIX_VEX_0F3A7E */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6697   },
6698
6699   /* PREFIX_VEX_0F3A7F */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3ADF */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6711   },
6712
6713   /* PREFIX_VEX_0F3AF0 */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6719   },
6720
6721 #define NEED_PREFIX_TABLE
6722 #include "i386-dis-evex.h"
6723 #undef NEED_PREFIX_TABLE
6724 };
6725
6726 static const struct dis386 x86_64_table[][2] = {
6727   /* X86_64_06 */
6728   {
6729     { "pushP", { es }, 0 },
6730   },
6731
6732   /* X86_64_07 */
6733   {
6734     { "popP", { es }, 0 },
6735   },
6736
6737   /* X86_64_0D */
6738   {
6739     { "pushP", { cs }, 0 },
6740   },
6741
6742   /* X86_64_16 */
6743   {
6744     { "pushP", { ss }, 0 },
6745   },
6746
6747   /* X86_64_17 */
6748   {
6749     { "popP", { ss }, 0 },
6750   },
6751
6752   /* X86_64_1E */
6753   {
6754     { "pushP", { ds }, 0 },
6755   },
6756
6757   /* X86_64_1F */
6758   {
6759     { "popP", { ds }, 0 },
6760   },
6761
6762   /* X86_64_27 */
6763   {
6764     { "daa", { XX }, 0 },
6765   },
6766
6767   /* X86_64_2F */
6768   {
6769     { "das", { XX }, 0 },
6770   },
6771
6772   /* X86_64_37 */
6773   {
6774     { "aaa", { XX }, 0 },
6775   },
6776
6777   /* X86_64_3F */
6778   {
6779     { "aas", { XX }, 0 },
6780   },
6781
6782   /* X86_64_60 */
6783   {
6784     { "pushaP", { XX }, 0 },
6785   },
6786
6787   /* X86_64_61 */
6788   {
6789     { "popaP", { XX }, 0 },
6790   },
6791
6792   /* X86_64_62 */
6793   {
6794     { MOD_TABLE (MOD_62_32BIT) },
6795     { EVEX_TABLE (EVEX_0F) },
6796   },
6797
6798   /* X86_64_63 */
6799   {
6800     { "arpl", { Ew, Gw }, 0 },
6801     { "movs{lq|xd}", { Gv, Ed }, 0 },
6802   },
6803
6804   /* X86_64_6D */
6805   {
6806     { "ins{R|}", { Yzr, indirDX }, 0 },
6807     { "ins{G|}", { Yzr, indirDX }, 0 },
6808   },
6809
6810   /* X86_64_6F */
6811   {
6812     { "outs{R|}", { indirDXr, Xz }, 0 },
6813     { "outs{G|}", { indirDXr, Xz }, 0 },
6814   },
6815
6816   /* X86_64_9A */
6817   {
6818     { "Jcall{T|}", { Ap }, 0 },
6819   },
6820
6821   /* X86_64_C4 */
6822   {
6823     { MOD_TABLE (MOD_C4_32BIT) },
6824     { VEX_C4_TABLE (VEX_0F) },
6825   },
6826
6827   /* X86_64_C5 */
6828   {
6829     { MOD_TABLE (MOD_C5_32BIT) },
6830     { VEX_C5_TABLE (VEX_0F) },
6831   },
6832
6833   /* X86_64_CE */
6834   {
6835     { "into", { XX }, 0 },
6836   },
6837
6838   /* X86_64_D4 */
6839   {
6840     { "aam", { Ib }, 0 },
6841   },
6842
6843   /* X86_64_D5 */
6844   {
6845     { "aad", { Ib }, 0 },
6846   },
6847
6848   /* X86_64_E8 */
6849   {
6850     { "callP",          { Jv, BND }, 0 },
6851     { "call@",          { Jv, BND }, 0 }
6852   },
6853
6854   /* X86_64_E9 */
6855   {
6856     { "jmpP",           { Jv, BND }, 0 },
6857     { "jmp@",           { Jv, BND }, 0 }
6858   },
6859
6860   /* X86_64_EA */
6861   {
6862     { "Jjmp{T|}", { Ap }, 0 },
6863   },
6864
6865   /* X86_64_0F01_REG_0 */
6866   {
6867     { "sgdt{Q|IQ}", { M }, 0 },
6868     { "sgdt", { M }, 0 },
6869   },
6870
6871   /* X86_64_0F01_REG_1 */
6872   {
6873     { "sidt{Q|IQ}", { M }, 0 },
6874     { "sidt", { M }, 0 },
6875   },
6876
6877   /* X86_64_0F01_REG_2 */
6878   {
6879     { "lgdt{Q|Q}", { M }, 0 },
6880     { "lgdt", { M }, 0 },
6881   },
6882
6883   /* X86_64_0F01_REG_3 */
6884   {
6885     { "lidt{Q|Q}", { M }, 0 },
6886     { "lidt", { M }, 0 },
6887   },
6888 };
6889
6890 static const struct dis386 three_byte_table[][256] = {
6891
6892   /* THREE_BYTE_0F38 */
6893   {
6894     /* 00 */
6895     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6896     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6897     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6898     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6899     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6900     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6901     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6902     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6903     /* 08 */
6904     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6905     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6906     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6907     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     /* 10 */
6913     { PREFIX_TABLE (PREFIX_0F3810) },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { PREFIX_TABLE (PREFIX_0F3814) },
6918     { PREFIX_TABLE (PREFIX_0F3815) },
6919     { Bad_Opcode },
6920     { PREFIX_TABLE (PREFIX_0F3817) },
6921     /* 18 */
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6927     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6928     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6929     { Bad_Opcode },
6930     /* 20 */
6931     { PREFIX_TABLE (PREFIX_0F3820) },
6932     { PREFIX_TABLE (PREFIX_0F3821) },
6933     { PREFIX_TABLE (PREFIX_0F3822) },
6934     { PREFIX_TABLE (PREFIX_0F3823) },
6935     { PREFIX_TABLE (PREFIX_0F3824) },
6936     { PREFIX_TABLE (PREFIX_0F3825) },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     /* 28 */
6940     { PREFIX_TABLE (PREFIX_0F3828) },
6941     { PREFIX_TABLE (PREFIX_0F3829) },
6942     { PREFIX_TABLE (PREFIX_0F382A) },
6943     { PREFIX_TABLE (PREFIX_0F382B) },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     /* 30 */
6949     { PREFIX_TABLE (PREFIX_0F3830) },
6950     { PREFIX_TABLE (PREFIX_0F3831) },
6951     { PREFIX_TABLE (PREFIX_0F3832) },
6952     { PREFIX_TABLE (PREFIX_0F3833) },
6953     { PREFIX_TABLE (PREFIX_0F3834) },
6954     { PREFIX_TABLE (PREFIX_0F3835) },
6955     { Bad_Opcode },
6956     { PREFIX_TABLE (PREFIX_0F3837) },
6957     /* 38 */
6958     { PREFIX_TABLE (PREFIX_0F3838) },
6959     { PREFIX_TABLE (PREFIX_0F3839) },
6960     { PREFIX_TABLE (PREFIX_0F383A) },
6961     { PREFIX_TABLE (PREFIX_0F383B) },
6962     { PREFIX_TABLE (PREFIX_0F383C) },
6963     { PREFIX_TABLE (PREFIX_0F383D) },
6964     { PREFIX_TABLE (PREFIX_0F383E) },
6965     { PREFIX_TABLE (PREFIX_0F383F) },
6966     /* 40 */
6967     { PREFIX_TABLE (PREFIX_0F3840) },
6968     { PREFIX_TABLE (PREFIX_0F3841) },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     /* 48 */
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     /* 50 */
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 58 */
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     /* 60 */
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     /* 68 */
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 70 */
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 78 */
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     /* 80 */
7039     { PREFIX_TABLE (PREFIX_0F3880) },
7040     { PREFIX_TABLE (PREFIX_0F3881) },
7041     { PREFIX_TABLE (PREFIX_0F3882) },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* 88 */
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 90 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 98 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* a0 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* a8 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* b0 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* b8 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* c0 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* c8 */
7120     { PREFIX_TABLE (PREFIX_0F38C8) },
7121     { PREFIX_TABLE (PREFIX_0F38C9) },
7122     { PREFIX_TABLE (PREFIX_0F38CA) },
7123     { PREFIX_TABLE (PREFIX_0F38CB) },
7124     { PREFIX_TABLE (PREFIX_0F38CC) },
7125     { PREFIX_TABLE (PREFIX_0F38CD) },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* d0 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* d8 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { PREFIX_TABLE (PREFIX_0F38DB) },
7142     { PREFIX_TABLE (PREFIX_0F38DC) },
7143     { PREFIX_TABLE (PREFIX_0F38DD) },
7144     { PREFIX_TABLE (PREFIX_0F38DE) },
7145     { PREFIX_TABLE (PREFIX_0F38DF) },
7146     /* e0 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* e8 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* f0 */
7165     { PREFIX_TABLE (PREFIX_0F38F0) },
7166     { PREFIX_TABLE (PREFIX_0F38F1) },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { PREFIX_TABLE (PREFIX_0F38F6) },
7172     { Bad_Opcode },
7173     /* f8 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182   },
7183   /* THREE_BYTE_0F3A */
7184   {
7185     /* 00 */
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     /* 08 */
7195     { PREFIX_TABLE (PREFIX_0F3A08) },
7196     { PREFIX_TABLE (PREFIX_0F3A09) },
7197     { PREFIX_TABLE (PREFIX_0F3A0A) },
7198     { PREFIX_TABLE (PREFIX_0F3A0B) },
7199     { PREFIX_TABLE (PREFIX_0F3A0C) },
7200     { PREFIX_TABLE (PREFIX_0F3A0D) },
7201     { PREFIX_TABLE (PREFIX_0F3A0E) },
7202     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7203     /* 10 */
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { PREFIX_TABLE (PREFIX_0F3A14) },
7209     { PREFIX_TABLE (PREFIX_0F3A15) },
7210     { PREFIX_TABLE (PREFIX_0F3A16) },
7211     { PREFIX_TABLE (PREFIX_0F3A17) },
7212     /* 18 */
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     /* 20 */
7222     { PREFIX_TABLE (PREFIX_0F3A20) },
7223     { PREFIX_TABLE (PREFIX_0F3A21) },
7224     { PREFIX_TABLE (PREFIX_0F3A22) },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     /* 28 */
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     /* 30 */
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     /* 38 */
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     /* 40 */
7258     { PREFIX_TABLE (PREFIX_0F3A40) },
7259     { PREFIX_TABLE (PREFIX_0F3A41) },
7260     { PREFIX_TABLE (PREFIX_0F3A42) },
7261     { Bad_Opcode },
7262     { PREFIX_TABLE (PREFIX_0F3A44) },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* 48 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 50 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 58 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 60 */
7294     { PREFIX_TABLE (PREFIX_0F3A60) },
7295     { PREFIX_TABLE (PREFIX_0F3A61) },
7296     { PREFIX_TABLE (PREFIX_0F3A62) },
7297     { PREFIX_TABLE (PREFIX_0F3A63) },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 68 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 70 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 78 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 80 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 88 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 90 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 98 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* a0 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* a8 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* b0 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* b8 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* c0 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* c8 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { PREFIX_TABLE (PREFIX_0F3ACC) },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* d0 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* d8 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { PREFIX_TABLE (PREFIX_0F3ADF) },
7437     /* e0 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* e8 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* f0 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* f8 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473   },
7474
7475   /* THREE_BYTE_0F7A */
7476   {
7477     /* 00 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     /* 08 */
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     /* 10 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* 18 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     /* 20 */
7514     { "ptest",          { XX }, PREFIX_OPCODE },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* 28 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* 30 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     /* 38 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     /* 40 */
7550     { Bad_Opcode },
7551     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7552     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7553     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7557     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7558     /* 48 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 50 */
7568     { Bad_Opcode },
7569     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7570     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7571     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7575     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7576     /* 58 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 60 */
7586     { Bad_Opcode },
7587     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7588     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7589     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 68 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 70 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 78 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 80 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 88 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 90 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 98 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* a0 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* a8 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* b0 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* b8 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* c0 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     /* c8 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     /* d0 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     /* d8 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     /* e0 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* e8 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* f0 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* f8 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765   },
7766 };
7767
7768 static const struct dis386 xop_table[][256] = {
7769   /* XOP_08 */
7770   {
7771     /* 00 */
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     /* 08 */
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     /* 10 */
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     /* 18 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     /* 20 */
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     /* 28 */
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     /* 30 */
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     /* 38 */
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     /* 40 */
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* 48 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     /* 50 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* 58 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 60 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 68 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 70 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* 78 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 80 */
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7922     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7923     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7924     /* 88 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7932     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7933     /* 90 */
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7940     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7941     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7942     /* 98 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7950     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7951     /* a0 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7955     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7959     { Bad_Opcode },
7960     /* a8 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* b0 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7977     { Bad_Opcode },
7978     /* b8 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* c0 */
7988     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7989     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7990     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7991     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     /* c8 */
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8002     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8003     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8004     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8005     /* d0 */
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     /* d8 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* e0 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     /* e8 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8038     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8039     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8040     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8041     /* f0 */
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     /* f8 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059   },
8060   /* XOP_09 */
8061   {
8062     /* 00 */
8063     { Bad_Opcode },
8064     { REG_TABLE (REG_XOP_TBM_01) },
8065     { REG_TABLE (REG_XOP_TBM_02) },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     /* 08 */
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     /* 10 */
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { REG_TABLE (REG_XOP_LWPCB) },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     /* 18 */
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     /* 20 */
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     /* 28 */
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     /* 30 */
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     /* 38 */
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     /* 40 */
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     /* 48 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* 50 */
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     /* 58 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* 60 */
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* 68 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* 70 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* 78 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     /* 80 */
8207     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8208     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8209     { "vfrczss",        { XM, EXd }, 0 },
8210     { "vfrczsd",        { XM, EXq }, 0 },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     /* 88 */
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     /* 90 */
8225     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8226     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8227     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8228     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8229     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8230     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8231     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8232     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233     /* 98 */
8234     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8235     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8237     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     /* a0 */
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     /* a8 */
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     /* b0 */
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     /* b8 */
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     /* c0 */
8279     { Bad_Opcode },
8280     { "vphaddbw",       { XM, EXxmm }, 0 },
8281     { "vphaddbd",       { XM, EXxmm }, 0 },
8282     { "vphaddbq",       { XM, EXxmm }, 0 },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { "vphaddwd",       { XM, EXxmm }, 0 },
8286     { "vphaddwq",       { XM, EXxmm }, 0 },
8287     /* c8 */
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { "vphadddq",       { XM, EXxmm }, 0 },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     /* d0 */
8297     { Bad_Opcode },
8298     { "vphaddubw",      { XM, EXxmm }, 0 },
8299     { "vphaddubd",      { XM, EXxmm }, 0 },
8300     { "vphaddubq",      { XM, EXxmm }, 0 },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { "vphadduwd",      { XM, EXxmm }, 0 },
8304     { "vphadduwq",      { XM, EXxmm }, 0 },
8305     /* d8 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { "vphaddudq",      { XM, EXxmm }, 0 },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* e0 */
8315     { Bad_Opcode },
8316     { "vphsubbw",       { XM, EXxmm }, 0 },
8317     { "vphsubwd",       { XM, EXxmm }, 0 },
8318     { "vphsubdq",       { XM, EXxmm }, 0 },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* e8 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* f0 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* f8 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350   },
8351   /* XOP_0A */
8352   {
8353     /* 00 */
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     /* 08 */
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     /* 10 */
8372     { "bextr",  { Gv, Ev, Iq }, 0 },
8373     { Bad_Opcode },
8374     { REG_TABLE (REG_XOP_LWP) },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* 18 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* 20 */
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     /* 28 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* 30 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     /* 38 */
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     /* 40 */
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     /* 48 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 50 */
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* 58 */
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* 60 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 68 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* 70 */
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     /* 78 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* 80 */
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     /* 88 */
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     /* 90 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 98 */
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     /* a0 */
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     /* a8 */
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     /* b0 */
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     /* b8 */
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     /* c0 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     /* c8 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* d0 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     /* d8 */
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* e0 */
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* e8 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* f0 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     /* f8 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641   },
8642 };
8643
8644 static const struct dis386 vex_table[][256] = {
8645   /* VEX_0F */
8646   {
8647     /* 00 */
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     /* 08 */
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     /* 10 */
8666     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8669     { MOD_TABLE (MOD_VEX_0F13) },
8670     { VEX_W_TABLE (VEX_W_0F14) },
8671     { VEX_W_TABLE (VEX_W_0F15) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8673     { MOD_TABLE (MOD_VEX_0F17) },
8674     /* 18 */
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     /* 20 */
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     /* 28 */
8693     { VEX_W_TABLE (VEX_W_0F28) },
8694     { VEX_W_TABLE (VEX_W_0F29) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8696     { MOD_TABLE (MOD_VEX_0F2B) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8701     /* 30 */
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     /* 38 */
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     /* 40 */
8720     { Bad_Opcode },
8721     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8723     { Bad_Opcode },
8724     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8728     /* 48 */
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     /* 50 */
8738     { MOD_TABLE (MOD_VEX_0F50) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8742     { "vandpX",         { XM, Vex, EXx }, 0 },
8743     { "vandnpX",        { XM, Vex, EXx }, 0 },
8744     { "vorpX",          { XM, Vex, EXx }, 0 },
8745     { "vxorpX",         { XM, Vex, EXx }, 0 },
8746     /* 58 */
8747     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8755     /* 60 */
8756     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8764     /* 68 */
8765     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8773     /* 70 */
8774     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8775     { REG_TABLE (REG_VEX_0F71) },
8776     { REG_TABLE (REG_VEX_0F72) },
8777     { REG_TABLE (REG_VEX_0F73) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8782     /* 78 */
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8791     /* 80 */
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     /* 88 */
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     /* 90 */
8810     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     /* 98 */
8819     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     /* a0 */
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     /* a8 */
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { REG_TABLE (REG_VEX_0FAE) },
8844     { Bad_Opcode },
8845     /* b0 */
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     /* b8 */
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     /* c0 */
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8867     { Bad_Opcode },
8868     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8870     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8871     { Bad_Opcode },
8872     /* c8 */
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     /* d0 */
8882     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8890     /* d8 */
8891     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8898     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8899     /* e0 */
8900     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8907     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8908     /* e8 */
8909     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8913     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8915     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8916     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8917     /* f0 */
8918     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8919     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8920     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8921     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8922     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8923     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8924     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8925     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8926     /* f8 */
8927     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8928     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8929     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8930     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8931     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8932     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8933     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8934     { Bad_Opcode },
8935   },
8936   /* VEX_0F38 */
8937   {
8938     /* 00 */
8939     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8947     /* 08 */
8948     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8956     /* 10 */
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8965     /* 18 */
8966     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8969     { Bad_Opcode },
8970     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8973     { Bad_Opcode },
8974     /* 20 */
8975     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     /* 28 */
8984     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8992     /* 30 */
8993     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9001     /* 38 */
9002     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9010     /* 40 */
9011     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9019     /* 48 */
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     /* 50 */
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     /* 58 */
9038     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     /* 60 */
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     /* 68 */
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     /* 70 */
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     /* 78 */
9074     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     /* 80 */
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     /* 88 */
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9097     { Bad_Opcode },
9098     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9099     { Bad_Opcode },
9100     /* 90 */
9101     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9109     /* 98 */
9110     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9118     /* a0 */
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9127     /* a8 */
9128     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9136     /* b0 */
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9145     /* b8 */
9146     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9154     /* c0 */
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     /* c8 */
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     /* d0 */
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     /* d8 */
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9190     /* e0 */
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     /* e8 */
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     /* f0 */
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9212     { REG_TABLE (REG_VEX_0F38F3) },
9213     { Bad_Opcode },
9214     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9217     /* f8 */
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226   },
9227   /* VEX_0F3A */
9228   {
9229     /* 00 */
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9233     { Bad_Opcode },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9237     { Bad_Opcode },
9238     /* 08 */
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9247     /* 10 */
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9256     /* 18 */
9257     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     /* 20 */
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     /* 28 */
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     /* 30 */
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     /* 38 */
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     /* 40 */
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9305     { Bad_Opcode },
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9307     { Bad_Opcode },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9309     { Bad_Opcode },
9310     /* 48 */
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     /* 50 */
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     /* 58 */
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9336     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9337     /* 60 */
9338     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9339     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9340     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9341     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     /* 68 */
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9351     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9353     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9354     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9355     /* 70 */
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     /* 78 */
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9368     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9369     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9370     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9371     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9372     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9373     /* 80 */
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     /* 88 */
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     /* 90 */
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     /* 98 */
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     /* a0 */
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     /* a8 */
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     /* b0 */
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     /* b8 */
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     /* c0 */
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     /* c8 */
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     /* d0 */
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     /* d8 */
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9481     /* e0 */
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     /* e8 */
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     /* f0 */
9500     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     { Bad_Opcode },
9508     /* f8 */
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     { Bad_Opcode },
9517   },
9518 };
9519
9520 #define NEED_OPCODE_TABLE
9521 #include "i386-dis-evex.h"
9522 #undef NEED_OPCODE_TABLE
9523 static const struct dis386 vex_len_table[][2] = {
9524   /* VEX_LEN_0F10_P_1 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9527     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9528   },
9529
9530   /* VEX_LEN_0F10_P_3 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9533     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9534   },
9535
9536   /* VEX_LEN_0F11_P_1 */
9537   {
9538     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9539     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9540   },
9541
9542   /* VEX_LEN_0F11_P_3 */
9543   {
9544     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9545     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9546   },
9547
9548   /* VEX_LEN_0F12_P_0_M_0 */
9549   {
9550     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9551   },
9552
9553   /* VEX_LEN_0F12_P_0_M_1 */
9554   {
9555     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9556   },
9557
9558   /* VEX_LEN_0F12_P_2 */
9559   {
9560     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9561   },
9562
9563   /* VEX_LEN_0F13_M_0 */
9564   {
9565     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9566   },
9567
9568   /* VEX_LEN_0F16_P_0_M_0 */
9569   {
9570     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9571   },
9572
9573   /* VEX_LEN_0F16_P_0_M_1 */
9574   {
9575     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9576   },
9577
9578   /* VEX_LEN_0F16_P_2 */
9579   {
9580     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9581   },
9582
9583   /* VEX_LEN_0F17_M_0 */
9584   {
9585     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9586   },
9587
9588   /* VEX_LEN_0F2A_P_1 */
9589   {
9590     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9591     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9592   },
9593
9594   /* VEX_LEN_0F2A_P_3 */
9595   {
9596     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9597     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9598   },
9599
9600   /* VEX_LEN_0F2C_P_1 */
9601   {
9602     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9603     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9604   },
9605
9606   /* VEX_LEN_0F2C_P_3 */
9607   {
9608     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9609     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9610   },
9611
9612   /* VEX_LEN_0F2D_P_1 */
9613   {
9614     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9615     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F2D_P_3 */
9619   {
9620     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9621     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F2E_P_0 */
9625   {
9626     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9627     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9628   },
9629
9630   /* VEX_LEN_0F2E_P_2 */
9631   {
9632     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9633     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9634   },
9635
9636   /* VEX_LEN_0F2F_P_0 */
9637   {
9638     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9639     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9640   },
9641
9642   /* VEX_LEN_0F2F_P_2 */
9643   {
9644     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9645     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9646   },
9647
9648   /* VEX_LEN_0F41_P_0 */
9649   {
9650     { Bad_Opcode },
9651     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9652   },
9653   /* VEX_LEN_0F41_P_2 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9657   },
9658   /* VEX_LEN_0F42_P_0 */
9659   {
9660     { Bad_Opcode },
9661     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9662   },
9663   /* VEX_LEN_0F42_P_2 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9667   },
9668   /* VEX_LEN_0F44_P_0 */
9669   {
9670     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9671   },
9672   /* VEX_LEN_0F44_P_2 */
9673   {
9674     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9675   },
9676   /* VEX_LEN_0F45_P_0 */
9677   {
9678     { Bad_Opcode },
9679     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9680   },
9681   /* VEX_LEN_0F45_P_2 */
9682   {
9683     { Bad_Opcode },
9684     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9685   },
9686   /* VEX_LEN_0F46_P_0 */
9687   {
9688     { Bad_Opcode },
9689     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9690   },
9691   /* VEX_LEN_0F46_P_2 */
9692   {
9693     { Bad_Opcode },
9694     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9695   },
9696   /* VEX_LEN_0F47_P_0 */
9697   {
9698     { Bad_Opcode },
9699     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9700   },
9701   /* VEX_LEN_0F47_P_2 */
9702   {
9703     { Bad_Opcode },
9704     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9705   },
9706   /* VEX_LEN_0F4A_P_0 */
9707   {
9708     { Bad_Opcode },
9709     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9710   },
9711   /* VEX_LEN_0F4A_P_2 */
9712   {
9713     { Bad_Opcode },
9714     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9715   },
9716   /* VEX_LEN_0F4B_P_0 */
9717   {
9718     { Bad_Opcode },
9719     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9720   },
9721   /* VEX_LEN_0F4B_P_2 */
9722   {
9723     { Bad_Opcode },
9724     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9725   },
9726
9727   /* VEX_LEN_0F51_P_1 */
9728   {
9729     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9730     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9731   },
9732
9733   /* VEX_LEN_0F51_P_3 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9736     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9737   },
9738
9739   /* VEX_LEN_0F52_P_1 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9742     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9743   },
9744
9745   /* VEX_LEN_0F53_P_1 */
9746   {
9747     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9748     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9749   },
9750
9751   /* VEX_LEN_0F58_P_1 */
9752   {
9753     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9754     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9755   },
9756
9757   /* VEX_LEN_0F58_P_3 */
9758   {
9759     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9760     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9761   },
9762
9763   /* VEX_LEN_0F59_P_1 */
9764   {
9765     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9766     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9767   },
9768
9769   /* VEX_LEN_0F59_P_3 */
9770   {
9771     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9772     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9773   },
9774
9775   /* VEX_LEN_0F5A_P_1 */
9776   {
9777     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9778     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9779   },
9780
9781   /* VEX_LEN_0F5A_P_3 */
9782   {
9783     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9784     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9785   },
9786
9787   /* VEX_LEN_0F5C_P_1 */
9788   {
9789     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9790     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9791   },
9792
9793   /* VEX_LEN_0F5C_P_3 */
9794   {
9795     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9796     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9797   },
9798
9799   /* VEX_LEN_0F5D_P_1 */
9800   {
9801     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9802     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9803   },
9804
9805   /* VEX_LEN_0F5D_P_3 */
9806   {
9807     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9808     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9809   },
9810
9811   /* VEX_LEN_0F5E_P_1 */
9812   {
9813     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9814     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9815   },
9816
9817   /* VEX_LEN_0F5E_P_3 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9820     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9821   },
9822
9823   /* VEX_LEN_0F5F_P_1 */
9824   {
9825     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9826     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9827   },
9828
9829   /* VEX_LEN_0F5F_P_3 */
9830   {
9831     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9832     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9833   },
9834
9835   /* VEX_LEN_0F6E_P_2 */
9836   {
9837     { "vmovK",          { XMScalar, Edq }, 0 },
9838     { "vmovK",          { XMScalar, Edq }, 0 },
9839   },
9840
9841   /* VEX_LEN_0F7E_P_1 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9844     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9845   },
9846
9847   /* VEX_LEN_0F7E_P_2 */
9848   {
9849     { "vmovK",          { Edq, XMScalar }, 0 },
9850     { "vmovK",          { Edq, XMScalar }, 0 },
9851   },
9852
9853   /* VEX_LEN_0F90_P_0 */
9854   {
9855     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9856   },
9857
9858   /* VEX_LEN_0F90_P_2 */
9859   {
9860     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9861   },
9862
9863   /* VEX_LEN_0F91_P_0 */
9864   {
9865     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9866   },
9867
9868   /* VEX_LEN_0F91_P_2 */
9869   {
9870     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9871   },
9872
9873   /* VEX_LEN_0F92_P_0 */
9874   {
9875     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9876   },
9877
9878   /* VEX_LEN_0F92_P_2 */
9879   {
9880     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9881   },
9882
9883   /* VEX_LEN_0F92_P_3 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9886   },
9887
9888   /* VEX_LEN_0F93_P_0 */
9889   {
9890     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9891   },
9892
9893   /* VEX_LEN_0F93_P_2 */
9894   {
9895     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9896   },
9897
9898   /* VEX_LEN_0F93_P_3 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9901   },
9902
9903   /* VEX_LEN_0F98_P_0 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9906   },
9907
9908   /* VEX_LEN_0F98_P_2 */
9909   {
9910     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9911   },
9912
9913   /* VEX_LEN_0F99_P_0 */
9914   {
9915     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9916   },
9917
9918   /* VEX_LEN_0F99_P_2 */
9919   {
9920     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9921   },
9922
9923   /* VEX_LEN_0FAE_R_2_M_0 */
9924   {
9925     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9926   },
9927
9928   /* VEX_LEN_0FAE_R_3_M_0 */
9929   {
9930     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9931   },
9932
9933   /* VEX_LEN_0FC2_P_1 */
9934   {
9935     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9936     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9937   },
9938
9939   /* VEX_LEN_0FC2_P_3 */
9940   {
9941     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9942     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9943   },
9944
9945   /* VEX_LEN_0FC4_P_2 */
9946   {
9947     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9948   },
9949
9950   /* VEX_LEN_0FC5_P_2 */
9951   {
9952     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9953   },
9954
9955   /* VEX_LEN_0FD6_P_2 */
9956   {
9957     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9958     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9959   },
9960
9961   /* VEX_LEN_0FF7_P_2 */
9962   {
9963     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9964   },
9965
9966   /* VEX_LEN_0F3816_P_2 */
9967   {
9968     { Bad_Opcode },
9969     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9970   },
9971
9972   /* VEX_LEN_0F3819_P_2 */
9973   {
9974     { Bad_Opcode },
9975     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9976   },
9977
9978   /* VEX_LEN_0F381A_P_2_M_0 */
9979   {
9980     { Bad_Opcode },
9981     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9982   },
9983
9984   /* VEX_LEN_0F3836_P_2 */
9985   {
9986     { Bad_Opcode },
9987     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9988   },
9989
9990   /* VEX_LEN_0F3841_P_2 */
9991   {
9992     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9993   },
9994
9995   /* VEX_LEN_0F385A_P_2_M_0 */
9996   {
9997     { Bad_Opcode },
9998     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9999   },
10000
10001   /* VEX_LEN_0F38DB_P_2 */
10002   {
10003     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10004   },
10005
10006   /* VEX_LEN_0F38DC_P_2 */
10007   {
10008     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10009   },
10010
10011   /* VEX_LEN_0F38DD_P_2 */
10012   {
10013     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10014   },
10015
10016   /* VEX_LEN_0F38DE_P_2 */
10017   {
10018     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10019   },
10020
10021   /* VEX_LEN_0F38DF_P_2 */
10022   {
10023     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10024   },
10025
10026   /* VEX_LEN_0F38F2_P_0 */
10027   {
10028     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10029   },
10030
10031   /* VEX_LEN_0F38F3_R_1_P_0 */
10032   {
10033     { "blsrS",          { VexGdq, Edq }, 0 },
10034   },
10035
10036   /* VEX_LEN_0F38F3_R_2_P_0 */
10037   {
10038     { "blsmskS",        { VexGdq, Edq }, 0 },
10039   },
10040
10041   /* VEX_LEN_0F38F3_R_3_P_0 */
10042   {
10043     { "blsiS",          { VexGdq, Edq }, 0 },
10044   },
10045
10046   /* VEX_LEN_0F38F5_P_0 */
10047   {
10048     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10049   },
10050
10051   /* VEX_LEN_0F38F5_P_1 */
10052   {
10053     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10054   },
10055
10056   /* VEX_LEN_0F38F5_P_3 */
10057   {
10058     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10059   },
10060
10061   /* VEX_LEN_0F38F6_P_3 */
10062   {
10063     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10064   },
10065
10066   /* VEX_LEN_0F38F7_P_0 */
10067   {
10068     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10069   },
10070
10071   /* VEX_LEN_0F38F7_P_1 */
10072   {
10073     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10074   },
10075
10076   /* VEX_LEN_0F38F7_P_2 */
10077   {
10078     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10079   },
10080
10081   /* VEX_LEN_0F38F7_P_3 */
10082   {
10083     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10084   },
10085
10086   /* VEX_LEN_0F3A00_P_2 */
10087   {
10088     { Bad_Opcode },
10089     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10090   },
10091
10092   /* VEX_LEN_0F3A01_P_2 */
10093   {
10094     { Bad_Opcode },
10095     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10096   },
10097
10098   /* VEX_LEN_0F3A06_P_2 */
10099   {
10100     { Bad_Opcode },
10101     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10102   },
10103
10104   /* VEX_LEN_0F3A0A_P_2 */
10105   {
10106     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10107     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10108   },
10109
10110   /* VEX_LEN_0F3A0B_P_2 */
10111   {
10112     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10113     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10114   },
10115
10116   /* VEX_LEN_0F3A14_P_2 */
10117   {
10118     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10119   },
10120
10121   /* VEX_LEN_0F3A15_P_2 */
10122   {
10123     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10124   },
10125
10126   /* VEX_LEN_0F3A16_P_2  */
10127   {
10128     { "vpextrK",        { Edq, XM, Ib }, 0 },
10129   },
10130
10131   /* VEX_LEN_0F3A17_P_2 */
10132   {
10133     { "vextractps",     { Edqd, XM, Ib }, 0 },
10134   },
10135
10136   /* VEX_LEN_0F3A18_P_2 */
10137   {
10138     { Bad_Opcode },
10139     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10140   },
10141
10142   /* VEX_LEN_0F3A19_P_2 */
10143   {
10144     { Bad_Opcode },
10145     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10146   },
10147
10148   /* VEX_LEN_0F3A20_P_2 */
10149   {
10150     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10151   },
10152
10153   /* VEX_LEN_0F3A21_P_2 */
10154   {
10155     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10156   },
10157
10158   /* VEX_LEN_0F3A22_P_2 */
10159   {
10160     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10161   },
10162
10163   /* VEX_LEN_0F3A30_P_2 */
10164   {
10165     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10166   },
10167
10168   /* VEX_LEN_0F3A31_P_2 */
10169   {
10170     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10171   },
10172
10173   /* VEX_LEN_0F3A32_P_2 */
10174   {
10175     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10176   },
10177
10178   /* VEX_LEN_0F3A33_P_2 */
10179   {
10180     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10181   },
10182
10183   /* VEX_LEN_0F3A38_P_2 */
10184   {
10185     { Bad_Opcode },
10186     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10187   },
10188
10189   /* VEX_LEN_0F3A39_P_2 */
10190   {
10191     { Bad_Opcode },
10192     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10193   },
10194
10195   /* VEX_LEN_0F3A41_P_2 */
10196   {
10197     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10198   },
10199
10200   /* VEX_LEN_0F3A44_P_2 */
10201   {
10202     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10203   },
10204
10205   /* VEX_LEN_0F3A46_P_2 */
10206   {
10207     { Bad_Opcode },
10208     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10209   },
10210
10211   /* VEX_LEN_0F3A60_P_2 */
10212   {
10213     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10214   },
10215
10216   /* VEX_LEN_0F3A61_P_2 */
10217   {
10218     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10219   },
10220
10221   /* VEX_LEN_0F3A62_P_2 */
10222   {
10223     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10224   },
10225
10226   /* VEX_LEN_0F3A63_P_2 */
10227   {
10228     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10229   },
10230
10231   /* VEX_LEN_0F3A6A_P_2 */
10232   {
10233     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10234   },
10235
10236   /* VEX_LEN_0F3A6B_P_2 */
10237   {
10238     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10239   },
10240
10241   /* VEX_LEN_0F3A6E_P_2 */
10242   {
10243     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10244   },
10245
10246   /* VEX_LEN_0F3A6F_P_2 */
10247   {
10248     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10249   },
10250
10251   /* VEX_LEN_0F3A7A_P_2 */
10252   {
10253     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10254   },
10255
10256   /* VEX_LEN_0F3A7B_P_2 */
10257   {
10258     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10259   },
10260
10261   /* VEX_LEN_0F3A7E_P_2 */
10262   {
10263     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10264   },
10265
10266   /* VEX_LEN_0F3A7F_P_2 */
10267   {
10268     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10269   },
10270
10271   /* VEX_LEN_0F3ADF_P_2 */
10272   {
10273     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10274   },
10275
10276   /* VEX_LEN_0F3AF0_P_3 */
10277   {
10278     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10279   },
10280
10281   /* VEX_LEN_0FXOP_08_CC */
10282   {
10283      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10284   },
10285
10286   /* VEX_LEN_0FXOP_08_CD */
10287   {
10288      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10289   },
10290
10291   /* VEX_LEN_0FXOP_08_CE */
10292   {
10293      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10294   },
10295
10296   /* VEX_LEN_0FXOP_08_CF */
10297   {
10298      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10299   },
10300
10301   /* VEX_LEN_0FXOP_08_EC */
10302   {
10303      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10304   },
10305
10306   /* VEX_LEN_0FXOP_08_ED */
10307   {
10308      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10309   },
10310
10311   /* VEX_LEN_0FXOP_08_EE */
10312   {
10313      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10314   },
10315
10316   /* VEX_LEN_0FXOP_08_EF */
10317   {
10318      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10319   },
10320
10321   /* VEX_LEN_0FXOP_09_80 */
10322   {
10323     { "vfrczps",        { XM, EXxmm }, 0 },
10324     { "vfrczps",        { XM, EXymmq }, 0 },
10325   },
10326
10327   /* VEX_LEN_0FXOP_09_81 */
10328   {
10329     { "vfrczpd",        { XM, EXxmm }, 0 },
10330     { "vfrczpd",        { XM, EXymmq }, 0 },
10331   },
10332 };
10333
10334 static const struct dis386 vex_w_table[][2] = {
10335   {
10336     /* VEX_W_0F10_P_0 */
10337     { "vmovups",        { XM, EXx }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F10_P_1 */
10341     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F10_P_2 */
10345     { "vmovupd",        { XM, EXx }, 0 },
10346   },
10347   {
10348     /* VEX_W_0F10_P_3 */
10349     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10350   },
10351   {
10352     /* VEX_W_0F11_P_0 */
10353     { "vmovups",        { EXxS, XM }, 0 },
10354   },
10355   {
10356     /* VEX_W_0F11_P_1 */
10357     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10358   },
10359   {
10360     /* VEX_W_0F11_P_2 */
10361     { "vmovupd",        { EXxS, XM }, 0 },
10362   },
10363   {
10364     /* VEX_W_0F11_P_3 */
10365     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10366   },
10367   {
10368     /* VEX_W_0F12_P_0_M_0 */
10369     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10370   },
10371   {
10372     /* VEX_W_0F12_P_0_M_1 */
10373     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10374   },
10375   {
10376     /* VEX_W_0F12_P_1 */
10377     { "vmovsldup",      { XM, EXx }, 0 },
10378   },
10379   {
10380     /* VEX_W_0F12_P_2 */
10381     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10382   },
10383   {
10384     /* VEX_W_0F12_P_3 */
10385     { "vmovddup",       { XM, EXymmq }, 0 },
10386   },
10387   {
10388     /* VEX_W_0F13_M_0 */
10389     { "vmovlpX",        { EXq, XM }, 0 },
10390   },
10391   {
10392     /* VEX_W_0F14 */
10393     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10394   },
10395   {
10396     /* VEX_W_0F15 */
10397     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10398   },
10399   {
10400     /* VEX_W_0F16_P_0_M_0 */
10401     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10402   },
10403   {
10404     /* VEX_W_0F16_P_0_M_1 */
10405     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10406   },
10407   {
10408     /* VEX_W_0F16_P_1 */
10409     { "vmovshdup",      { XM, EXx }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F16_P_2 */
10413     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10414   },
10415   {
10416     /* VEX_W_0F17_M_0 */
10417     { "vmovhpX",        { EXq, XM }, 0 },
10418   },
10419   {
10420     /* VEX_W_0F28 */
10421     { "vmovapX",        { XM, EXx }, 0 },
10422   },
10423   {
10424     /* VEX_W_0F29 */
10425     { "vmovapX",        { EXxS, XM }, 0 },
10426   },
10427   {
10428     /* VEX_W_0F2B_M_0 */
10429     { "vmovntpX",       { Mx, XM }, 0 },
10430   },
10431   {
10432     /* VEX_W_0F2E_P_0 */
10433     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10434   },
10435   {
10436     /* VEX_W_0F2E_P_2 */
10437     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10438   },
10439   {
10440     /* VEX_W_0F2F_P_0 */
10441     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F2F_P_2 */
10445     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F41_P_0_LEN_1 */
10449     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10450     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F41_P_2_LEN_1 */
10454     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10455     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F42_P_0_LEN_1 */
10459     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10460     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10461   },
10462   {
10463     /* VEX_W_0F42_P_2_LEN_1 */
10464     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10465     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F44_P_0_LEN_0 */
10469     { "knotw",          { MaskG, MaskR }, 0 },
10470     { "knotq",          { MaskG, MaskR }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F44_P_2_LEN_0 */
10474     { "knotb",          { MaskG, MaskR }, 0 },
10475     { "knotd",          { MaskG, MaskR }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F45_P_0_LEN_1 */
10479     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10480     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10481   },
10482   {
10483     /* VEX_W_0F45_P_2_LEN_1 */
10484     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10485     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10486   },
10487   {
10488     /* VEX_W_0F46_P_0_LEN_1 */
10489     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10490     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10491   },
10492   {
10493     /* VEX_W_0F46_P_2_LEN_1 */
10494     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10495     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F47_P_0_LEN_1 */
10499     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10500     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F47_P_2_LEN_1 */
10504     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10505     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F4A_P_0_LEN_1 */
10509     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10510     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10511   },
10512   {
10513     /* VEX_W_0F4A_P_2_LEN_1 */
10514     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10515     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F4B_P_0_LEN_1 */
10519     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10520     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F4B_P_2_LEN_1 */
10524     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F50_M_0 */
10528     { "vmovmskpX",      { Gdq, XS }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F51_P_0 */
10532     { "vsqrtps",        { XM, EXx }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F51_P_1 */
10536     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F51_P_2  */
10540     { "vsqrtpd",        { XM, EXx }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F51_P_3 */
10544     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F52_P_0 */
10548     { "vrsqrtps",       { XM, EXx }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F52_P_1 */
10552     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F53_P_0  */
10556     { "vrcpps",         { XM, EXx }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F53_P_1  */
10560     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F58_P_0  */
10564     { "vaddps",         { XM, Vex, EXx }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F58_P_1  */
10568     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F58_P_2  */
10572     { "vaddpd",         { XM, Vex, EXx }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F58_P_3  */
10576     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F59_P_0  */
10580     { "vmulps",         { XM, Vex, EXx }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F59_P_1  */
10584     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F59_P_2  */
10588     { "vmulpd",         { XM, Vex, EXx }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F59_P_3  */
10592     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F5A_P_0  */
10596     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F5A_P_1  */
10600     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F5A_P_3  */
10604     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F5B_P_0  */
10608     { "vcvtdq2ps",      { XM, EXx }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F5B_P_1  */
10612     { "vcvttps2dq",     { XM, EXx }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F5B_P_2  */
10616     { "vcvtps2dq",      { XM, EXx }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F5C_P_0  */
10620     { "vsubps",         { XM, Vex, EXx }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F5C_P_1  */
10624     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F5C_P_2  */
10628     { "vsubpd",         { XM, Vex, EXx }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F5C_P_3  */
10632     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F5D_P_0  */
10636     { "vminps",         { XM, Vex, EXx }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F5D_P_1  */
10640     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F5D_P_2  */
10644     { "vminpd",         { XM, Vex, EXx }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F5D_P_3  */
10648     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F5E_P_0  */
10652     { "vdivps",         { XM, Vex, EXx }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F5E_P_1  */
10656     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F5E_P_2  */
10660     { "vdivpd",         { XM, Vex, EXx }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F5E_P_3  */
10664     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F5F_P_0  */
10668     { "vmaxps",         { XM, Vex, EXx }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F5F_P_1  */
10672     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F5F_P_2  */
10676     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F5F_P_3  */
10680     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F60_P_2  */
10684     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F61_P_2  */
10688     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F62_P_2  */
10692     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F63_P_2  */
10696     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F64_P_2  */
10700     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F65_P_2  */
10704     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10705   },
10706   {
10707     /* VEX_W_0F66_P_2  */
10708     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10709   },
10710   {
10711     /* VEX_W_0F67_P_2  */
10712     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10713   },
10714   {
10715     /* VEX_W_0F68_P_2  */
10716     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10717   },
10718   {
10719     /* VEX_W_0F69_P_2  */
10720     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10721   },
10722   {
10723     /* VEX_W_0F6A_P_2  */
10724     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10725   },
10726   {
10727     /* VEX_W_0F6B_P_2  */
10728     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10729   },
10730   {
10731     /* VEX_W_0F6C_P_2  */
10732     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10733   },
10734   {
10735     /* VEX_W_0F6D_P_2  */
10736     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10737   },
10738   {
10739     /* VEX_W_0F6F_P_1  */
10740     { "vmovdqu",        { XM, EXx }, 0 },
10741   },
10742   {
10743     /* VEX_W_0F6F_P_2  */
10744     { "vmovdqa",        { XM, EXx }, 0 },
10745   },
10746   {
10747     /* VEX_W_0F70_P_1 */
10748     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10749   },
10750   {
10751     /* VEX_W_0F70_P_2 */
10752     { "vpshufd",        { XM, EXx, Ib }, 0 },
10753   },
10754   {
10755     /* VEX_W_0F70_P_3 */
10756     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10757   },
10758   {
10759     /* VEX_W_0F71_R_2_P_2  */
10760     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10761   },
10762   {
10763     /* VEX_W_0F71_R_4_P_2  */
10764     { "vpsraw",         { Vex, XS, Ib }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F71_R_6_P_2  */
10768     { "vpsllw",         { Vex, XS, Ib }, 0 },
10769   },
10770   {
10771     /* VEX_W_0F72_R_2_P_2  */
10772     { "vpsrld",         { Vex, XS, Ib }, 0 },
10773   },
10774   {
10775     /* VEX_W_0F72_R_4_P_2  */
10776     { "vpsrad",         { Vex, XS, Ib }, 0 },
10777   },
10778   {
10779     /* VEX_W_0F72_R_6_P_2  */
10780     { "vpslld",         { Vex, XS, Ib }, 0 },
10781   },
10782   {
10783     /* VEX_W_0F73_R_2_P_2  */
10784     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10785   },
10786   {
10787     /* VEX_W_0F73_R_3_P_2  */
10788     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10789   },
10790   {
10791     /* VEX_W_0F73_R_6_P_2  */
10792     { "vpsllq",         { Vex, XS, Ib }, 0 },
10793   },
10794   {
10795     /* VEX_W_0F73_R_7_P_2  */
10796     { "vpslldq",        { Vex, XS, Ib }, 0 },
10797   },
10798   {
10799     /* VEX_W_0F74_P_2 */
10800     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10801   },
10802   {
10803     /* VEX_W_0F75_P_2 */
10804     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10805   },
10806   {
10807     /* VEX_W_0F76_P_2 */
10808     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10809   },
10810   {
10811     /* VEX_W_0F77_P_0 */
10812     { "",               { VZERO }, 0 },
10813   },
10814   {
10815     /* VEX_W_0F7C_P_2 */
10816     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10817   },
10818   {
10819     /* VEX_W_0F7C_P_3 */
10820     { "vhaddps",        { XM, Vex, EXx }, 0 },
10821   },
10822   {
10823     /* VEX_W_0F7D_P_2 */
10824     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10825   },
10826   {
10827     /* VEX_W_0F7D_P_3 */
10828     { "vhsubps",        { XM, Vex, EXx }, 0 },
10829   },
10830   {
10831     /* VEX_W_0F7E_P_1 */
10832     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10833   },
10834   {
10835     /* VEX_W_0F7F_P_1 */
10836     { "vmovdqu",        { EXxS, XM }, 0 },
10837   },
10838   {
10839     /* VEX_W_0F7F_P_2 */
10840     { "vmovdqa",        { EXxS, XM }, 0 },
10841   },
10842   {
10843     /* VEX_W_0F90_P_0_LEN_0 */
10844     { "kmovw",          { MaskG, MaskE }, 0 },
10845     { "kmovq",          { MaskG, MaskE }, 0 },
10846   },
10847   {
10848     /* VEX_W_0F90_P_2_LEN_0 */
10849     { "kmovb",          { MaskG, MaskBDE }, 0 },
10850     { "kmovd",          { MaskG, MaskBDE }, 0 },
10851   },
10852   {
10853     /* VEX_W_0F91_P_0_LEN_0 */
10854     { "kmovw",          { Ew, MaskG }, 0 },
10855     { "kmovq",          { Eq, MaskG }, 0 },
10856   },
10857   {
10858     /* VEX_W_0F91_P_2_LEN_0 */
10859     { "kmovb",          { Eb, MaskG }, 0 },
10860     { "kmovd",          { Ed, MaskG }, 0 },
10861   },
10862   {
10863     /* VEX_W_0F92_P_0_LEN_0 */
10864     { "kmovw",          { MaskG, Rdq }, 0 },
10865   },
10866   {
10867     /* VEX_W_0F92_P_2_LEN_0 */
10868     { "kmovb",          { MaskG, Rdq }, 0 },
10869   },
10870   {
10871     /* VEX_W_0F92_P_3_LEN_0 */
10872     { "kmovd",          { MaskG, Rdq }, 0 },
10873     { "kmovq",          { MaskG, Rdq }, 0 },
10874   },
10875   {
10876     /* VEX_W_0F93_P_0_LEN_0 */
10877     { "kmovw",          { Gdq, MaskR }, 0 },
10878   },
10879   {
10880     /* VEX_W_0F93_P_2_LEN_0 */
10881     { "kmovb",          { Gdq, MaskR }, 0 },
10882   },
10883   {
10884     /* VEX_W_0F93_P_3_LEN_0 */
10885     { "kmovd",          { Gdq, MaskR }, 0 },
10886     { "kmovq",          { Gdq, MaskR }, 0 },
10887   },
10888   {
10889     /* VEX_W_0F98_P_0_LEN_0 */
10890     { "kortestw",       { MaskG, MaskR }, 0 },
10891     { "kortestq",       { MaskG, MaskR }, 0 },
10892   },
10893   {
10894     /* VEX_W_0F98_P_2_LEN_0 */
10895     { "kortestb",       { MaskG, MaskR }, 0 },
10896     { "kortestd",       { MaskG, MaskR }, 0 },
10897   },
10898   {
10899     /* VEX_W_0F99_P_0_LEN_0 */
10900     { "ktestw", { MaskG, MaskR }, 0 },
10901     { "ktestq", { MaskG, MaskR }, 0 },
10902   },
10903   {
10904     /* VEX_W_0F99_P_2_LEN_0 */
10905     { "ktestb", { MaskG, MaskR }, 0 },
10906     { "ktestd", { MaskG, MaskR }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FAE_R_2_M_0 */
10910     { "vldmxcsr",       { Md }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FAE_R_3_M_0 */
10914     { "vstmxcsr",       { Md }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FC2_P_0 */
10918     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FC2_P_1 */
10922     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FC2_P_2 */
10926     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10927   },
10928   {
10929     /* VEX_W_0FC2_P_3 */
10930     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10931   },
10932   {
10933     /* VEX_W_0FC4_P_2 */
10934     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10935   },
10936   {
10937     /* VEX_W_0FC5_P_2 */
10938     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10939   },
10940   {
10941     /* VEX_W_0FD0_P_2 */
10942     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10943   },
10944   {
10945     /* VEX_W_0FD0_P_3 */
10946     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10947   },
10948   {
10949     /* VEX_W_0FD1_P_2 */
10950     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10951   },
10952   {
10953     /* VEX_W_0FD2_P_2 */
10954     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10955   },
10956   {
10957     /* VEX_W_0FD3_P_2 */
10958     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10959   },
10960   {
10961     /* VEX_W_0FD4_P_2 */
10962     { "vpaddq",         { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0FD5_P_2 */
10966     { "vpmullw",        { XM, Vex, EXx }, 0 },
10967   },
10968   {
10969     /* VEX_W_0FD6_P_2 */
10970     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10971   },
10972   {
10973     /* VEX_W_0FD7_P_2_M_1 */
10974     { "vpmovmskb",      { Gdq, XS }, 0 },
10975   },
10976   {
10977     /* VEX_W_0FD8_P_2 */
10978     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0FD9_P_2 */
10982     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FDA_P_2 */
10986     { "vpminub",        { XM, Vex, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0FDB_P_2 */
10990     { "vpand",          { XM, Vex, EXx }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FDC_P_2 */
10994     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10995   },
10996   {
10997     /* VEX_W_0FDD_P_2 */
10998     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10999   },
11000   {
11001     /* VEX_W_0FDE_P_2 */
11002     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11003   },
11004   {
11005     /* VEX_W_0FDF_P_2 */
11006     { "vpandn",         { XM, Vex, EXx }, 0 },
11007   },
11008   {
11009     /* VEX_W_0FE0_P_2  */
11010     { "vpavgb",         { XM, Vex, EXx }, 0 },
11011   },
11012   {
11013     /* VEX_W_0FE1_P_2  */
11014     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11015   },
11016   {
11017     /* VEX_W_0FE2_P_2  */
11018     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11019   },
11020   {
11021     /* VEX_W_0FE3_P_2  */
11022     { "vpavgw",         { XM, Vex, EXx }, 0 },
11023   },
11024   {
11025     /* VEX_W_0FE4_P_2  */
11026     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0FE5_P_2  */
11030     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11031   },
11032   {
11033     /* VEX_W_0FE6_P_1  */
11034     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11035   },
11036   {
11037     /* VEX_W_0FE6_P_2  */
11038     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11039   },
11040   {
11041     /* VEX_W_0FE6_P_3  */
11042     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11043   },
11044   {
11045     /* VEX_W_0FE7_P_2_M_0 */
11046     { "vmovntdq",       { Mx, XM }, 0 },
11047   },
11048   {
11049     /* VEX_W_0FE8_P_2  */
11050     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0FE9_P_2  */
11054     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0FEA_P_2  */
11058     { "vpminsw",        { XM, Vex, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0FEB_P_2  */
11062     { "vpor",           { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0FEC_P_2  */
11066     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11067   },
11068   {
11069     /* VEX_W_0FED_P_2  */
11070     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11071   },
11072   {
11073     /* VEX_W_0FEE_P_2  */
11074     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0FEF_P_2  */
11078     { "vpxor",          { XM, Vex, EXx }, 0 },
11079   },
11080   {
11081     /* VEX_W_0FF0_P_3_M_0 */
11082     { "vlddqu",         { XM, M }, 0 },
11083   },
11084   {
11085     /* VEX_W_0FF1_P_2 */
11086     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11087   },
11088   {
11089     /* VEX_W_0FF2_P_2 */
11090     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11091   },
11092   {
11093     /* VEX_W_0FF3_P_2 */
11094     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11095   },
11096   {
11097     /* VEX_W_0FF4_P_2 */
11098     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11099   },
11100   {
11101     /* VEX_W_0FF5_P_2 */
11102     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11103   },
11104   {
11105     /* VEX_W_0FF6_P_2 */
11106     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11107   },
11108   {
11109     /* VEX_W_0FF7_P_2 */
11110     { "vmaskmovdqu",    { XM, XS }, 0 },
11111   },
11112   {
11113     /* VEX_W_0FF8_P_2 */
11114     { "vpsubb",         { XM, Vex, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0FF9_P_2 */
11118     { "vpsubw",         { XM, Vex, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0FFA_P_2 */
11122     { "vpsubd",         { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0FFB_P_2 */
11126     { "vpsubq",         { XM, Vex, EXx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0FFC_P_2 */
11130     { "vpaddb",         { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0FFD_P_2 */
11134     { "vpaddw",         { XM, Vex, EXx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0FFE_P_2 */
11138     { "vpaddd",         { XM, Vex, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F3800_P_2  */
11142     { "vpshufb",        { XM, Vex, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F3801_P_2  */
11146     { "vphaddw",        { XM, Vex, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F3802_P_2  */
11150     { "vphaddd",        { XM, Vex, EXx }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F3803_P_2  */
11154     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F3804_P_2  */
11158     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F3805_P_2  */
11162     { "vphsubw",        { XM, Vex, EXx }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F3806_P_2  */
11166     { "vphsubd",        { XM, Vex, EXx }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F3807_P_2  */
11170     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F3808_P_2  */
11174     { "vpsignb",        { XM, Vex, EXx }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F3809_P_2  */
11178     { "vpsignw",        { XM, Vex, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F380A_P_2  */
11182     { "vpsignd",        { XM, Vex, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F380B_P_2  */
11186     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F380C_P_2  */
11190     { "vpermilps",      { XM, Vex, EXx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F380D_P_2  */
11194     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F380E_P_2  */
11198     { "vtestps",        { XM, EXx }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F380F_P_2  */
11202     { "vtestpd",        { XM, EXx }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F3816_P_2  */
11206     { "vpermps",        { XM, Vex, EXx }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F3817_P_2 */
11210     { "vptest",         { XM, EXx }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3818_P_2 */
11214     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3819_P_2 */
11218     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F381A_P_2_M_0 */
11222     { "vbroadcastf128", { XM, Mxmm }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F381C_P_2 */
11226     { "vpabsb",         { XM, EXx }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F381D_P_2 */
11230     { "vpabsw",         { XM, EXx }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F381E_P_2 */
11234     { "vpabsd",         { XM, EXx }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3820_P_2 */
11238     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3821_P_2 */
11242     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F3822_P_2 */
11246     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F3823_P_2 */
11250     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F3824_P_2 */
11254     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F3825_P_2 */
11258     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F3828_P_2 */
11262     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F3829_P_2 */
11266     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F382A_P_2_M_0 */
11270     { "vmovntdqa",      { XM, Mx }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F382B_P_2 */
11274     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F382C_P_2_M_0 */
11278     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11279   },
11280   {
11281     /* VEX_W_0F382D_P_2_M_0 */
11282     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11283   },
11284   {
11285     /* VEX_W_0F382E_P_2_M_0 */
11286     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11287   },
11288   {
11289     /* VEX_W_0F382F_P_2_M_0 */
11290     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11291   },
11292   {
11293     /* VEX_W_0F3830_P_2 */
11294     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11295   },
11296   {
11297     /* VEX_W_0F3831_P_2 */
11298     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F3832_P_2 */
11302     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F3833_P_2 */
11306     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F3834_P_2 */
11310     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11311   },
11312   {
11313     /* VEX_W_0F3835_P_2 */
11314     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11315   },
11316   {
11317     /* VEX_W_0F3836_P_2  */
11318     { "vpermd",         { XM, Vex, EXx }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3837_P_2 */
11322     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3838_P_2 */
11326     { "vpminsb",        { XM, Vex, EXx }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F3839_P_2 */
11330     { "vpminsd",        { XM, Vex, EXx }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F383A_P_2 */
11334     { "vpminuw",        { XM, Vex, EXx }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F383B_P_2 */
11338     { "vpminud",        { XM, Vex, EXx }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F383C_P_2 */
11342     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F383D_P_2 */
11346     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F383E_P_2 */
11350     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F383F_P_2 */
11354     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F3840_P_2 */
11358     { "vpmulld",        { XM, Vex, EXx }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F3841_P_2 */
11362     { "vphminposuw",    { XM, EXx }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F3846_P_2 */
11366     { "vpsravd",        { XM, Vex, EXx }, 0 },
11367   },
11368   {
11369     /* VEX_W_0F3858_P_2 */
11370     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F3859_P_2 */
11374     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11375   },
11376   {
11377     /* VEX_W_0F385A_P_2_M_0 */
11378     { "vbroadcasti128", { XM, Mxmm }, 0 },
11379   },
11380   {
11381     /* VEX_W_0F3878_P_2 */
11382     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11383   },
11384   {
11385     /* VEX_W_0F3879_P_2 */
11386     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F38DB_P_2 */
11390     { "vaesimc",        { XM, EXx }, 0 },
11391   },
11392   {
11393     /* VEX_W_0F38DC_P_2 */
11394     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F38DD_P_2 */
11398     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11399   },
11400   {
11401     /* VEX_W_0F38DE_P_2 */
11402     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11403   },
11404   {
11405     /* VEX_W_0F38DF_P_2 */
11406     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11407   },
11408   {
11409     /* VEX_W_0F3A00_P_2 */
11410     { Bad_Opcode },
11411     { "vpermq",         { XM, EXx, Ib }, 0 },
11412   },
11413   {
11414     /* VEX_W_0F3A01_P_2 */
11415     { Bad_Opcode },
11416     { "vpermpd",        { XM, EXx, Ib }, 0 },
11417   },
11418   {
11419     /* VEX_W_0F3A02_P_2 */
11420     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11421   },
11422   {
11423     /* VEX_W_0F3A04_P_2 */
11424     { "vpermilps",      { XM, EXx, Ib }, 0 },
11425   },
11426   {
11427     /* VEX_W_0F3A05_P_2 */
11428     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11429   },
11430   {
11431     /* VEX_W_0F3A06_P_2 */
11432     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11433   },
11434   {
11435     /* VEX_W_0F3A08_P_2 */
11436     { "vroundps",       { XM, EXx, Ib }, 0 },
11437   },
11438   {
11439     /* VEX_W_0F3A09_P_2 */
11440     { "vroundpd",       { XM, EXx, Ib }, 0 },
11441   },
11442   {
11443     /* VEX_W_0F3A0A_P_2 */
11444     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11445   },
11446   {
11447     /* VEX_W_0F3A0B_P_2 */
11448     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11449   },
11450   {
11451     /* VEX_W_0F3A0C_P_2 */
11452     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11453   },
11454   {
11455     /* VEX_W_0F3A0D_P_2 */
11456     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11457   },
11458   {
11459     /* VEX_W_0F3A0E_P_2 */
11460     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11461   },
11462   {
11463     /* VEX_W_0F3A0F_P_2 */
11464     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11465   },
11466   {
11467     /* VEX_W_0F3A14_P_2 */
11468     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11469   },
11470   {
11471     /* VEX_W_0F3A15_P_2 */
11472     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F3A18_P_2 */
11476     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11477   },
11478   {
11479     /* VEX_W_0F3A19_P_2 */
11480     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11481   },
11482   {
11483     /* VEX_W_0F3A20_P_2 */
11484     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11485   },
11486   {
11487     /* VEX_W_0F3A21_P_2 */
11488     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11489   },
11490   {
11491     /* VEX_W_0F3A30_P_2_LEN_0 */
11492     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11493     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11494   },
11495   {
11496     /* VEX_W_0F3A31_P_2_LEN_0 */
11497     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11498     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11499   },
11500   {
11501     /* VEX_W_0F3A32_P_2_LEN_0 */
11502     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11503     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11504   },
11505   {
11506     /* VEX_W_0F3A33_P_2_LEN_0 */
11507     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11508     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11509   },
11510   {
11511     /* VEX_W_0F3A38_P_2 */
11512     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11513   },
11514   {
11515     /* VEX_W_0F3A39_P_2 */
11516     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3A40_P_2 */
11520     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11521   },
11522   {
11523     /* VEX_W_0F3A41_P_2 */
11524     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11525   },
11526   {
11527     /* VEX_W_0F3A42_P_2 */
11528     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11529   },
11530   {
11531     /* VEX_W_0F3A44_P_2 */
11532     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11533   },
11534   {
11535     /* VEX_W_0F3A46_P_2 */
11536     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11537   },
11538   {
11539     /* VEX_W_0F3A48_P_2 */
11540     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11541     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11542   },
11543   {
11544     /* VEX_W_0F3A49_P_2 */
11545     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11546     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11547   },
11548   {
11549     /* VEX_W_0F3A4A_P_2 */
11550     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11551   },
11552   {
11553     /* VEX_W_0F3A4B_P_2 */
11554     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11555   },
11556   {
11557     /* VEX_W_0F3A4C_P_2 */
11558     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11559   },
11560   {
11561     /* VEX_W_0F3A60_P_2 */
11562     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11563   },
11564   {
11565     /* VEX_W_0F3A61_P_2 */
11566     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11567   },
11568   {
11569     /* VEX_W_0F3A62_P_2 */
11570     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11571   },
11572   {
11573     /* VEX_W_0F3A63_P_2 */
11574     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11575   },
11576   {
11577     /* VEX_W_0F3ADF_P_2 */
11578     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11579   },
11580 #define NEED_VEX_W_TABLE
11581 #include "i386-dis-evex.h"
11582 #undef NEED_VEX_W_TABLE
11583 };
11584
11585 static const struct dis386 mod_table[][2] = {
11586   {
11587     /* MOD_8D */
11588     { "leaS",           { Gv, M }, 0 },
11589   },
11590   {
11591     /* MOD_C6_REG_7 */
11592     { Bad_Opcode },
11593     { RM_TABLE (RM_C6_REG_7) },
11594   },
11595   {
11596     /* MOD_C7_REG_7 */
11597     { Bad_Opcode },
11598     { RM_TABLE (RM_C7_REG_7) },
11599   },
11600   {
11601     /* MOD_FF_REG_3 */
11602     { "Jcall^", { indirEp }, 0 },
11603   },
11604   {
11605     /* MOD_FF_REG_5 */
11606     { "Jjmp^", { indirEp }, 0 },
11607   },
11608   {
11609     /* MOD_0F01_REG_0 */
11610     { X86_64_TABLE (X86_64_0F01_REG_0) },
11611     { RM_TABLE (RM_0F01_REG_0) },
11612   },
11613   {
11614     /* MOD_0F01_REG_1 */
11615     { X86_64_TABLE (X86_64_0F01_REG_1) },
11616     { RM_TABLE (RM_0F01_REG_1) },
11617   },
11618   {
11619     /* MOD_0F01_REG_2 */
11620     { X86_64_TABLE (X86_64_0F01_REG_2) },
11621     { RM_TABLE (RM_0F01_REG_2) },
11622   },
11623   {
11624     /* MOD_0F01_REG_3 */
11625     { X86_64_TABLE (X86_64_0F01_REG_3) },
11626     { RM_TABLE (RM_0F01_REG_3) },
11627   },
11628   {
11629     /* MOD_0F01_REG_7 */
11630     { "invlpg",         { Mb }, 0 },
11631     { RM_TABLE (RM_0F01_REG_7) },
11632   },
11633   {
11634     /* MOD_0F12_PREFIX_0 */
11635     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11636     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11637   },
11638   {
11639     /* MOD_0F13 */
11640     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11641   },
11642   {
11643     /* MOD_0F16_PREFIX_0 */
11644     { "movhps",         { XM, EXq }, 0 },
11645     { "movlhps",        { XM, EXq }, 0 },
11646   },
11647   {
11648     /* MOD_0F17 */
11649     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11650   },
11651   {
11652     /* MOD_0F18_REG_0 */
11653     { "prefetchnta",    { Mb }, 0 },
11654   },
11655   {
11656     /* MOD_0F18_REG_1 */
11657     { "prefetcht0",     { Mb }, 0 },
11658   },
11659   {
11660     /* MOD_0F18_REG_2 */
11661     { "prefetcht1",     { Mb }, 0 },
11662   },
11663   {
11664     /* MOD_0F18_REG_3 */
11665     { "prefetcht2",     { Mb }, 0 },
11666   },
11667   {
11668     /* MOD_0F18_REG_4 */
11669     { "nop/reserved",   { Mb }, 0 },
11670   },
11671   {
11672     /* MOD_0F18_REG_5 */
11673     { "nop/reserved",   { Mb }, 0 },
11674   },
11675   {
11676     /* MOD_0F18_REG_6 */
11677     { "nop/reserved",   { Mb }, 0 },
11678   },
11679   {
11680     /* MOD_0F18_REG_7 */
11681     { "nop/reserved",   { Mb }, 0 },
11682   },
11683   {
11684     /* MOD_0F1A_PREFIX_0 */
11685     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11686     { "nopQ",           { Ev }, 0 },
11687   },
11688   {
11689     /* MOD_0F1B_PREFIX_0 */
11690     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11691     { "nopQ",           { Ev }, 0 },
11692   },
11693   {
11694     /* MOD_0F1B_PREFIX_1 */
11695     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11696     { "nopQ",           { Ev }, 0 },
11697   },
11698   {
11699     /* MOD_0F24 */
11700     { Bad_Opcode },
11701     { "movL",           { Rd, Td }, 0 },
11702   },
11703   {
11704     /* MOD_0F26 */
11705     { Bad_Opcode },
11706     { "movL",           { Td, Rd }, 0 },
11707   },
11708   {
11709     /* MOD_0F2B_PREFIX_0 */
11710     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11711   },
11712   {
11713     /* MOD_0F2B_PREFIX_1 */
11714     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11715   },
11716   {
11717     /* MOD_0F2B_PREFIX_2 */
11718     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11719   },
11720   {
11721     /* MOD_0F2B_PREFIX_3 */
11722     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11723   },
11724   {
11725     /* MOD_0F51 */
11726     { Bad_Opcode },
11727     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11728   },
11729   {
11730     /* MOD_0F71_REG_2 */
11731     { Bad_Opcode },
11732     { "psrlw",          { MS, Ib }, 0 },
11733   },
11734   {
11735     /* MOD_0F71_REG_4 */
11736     { Bad_Opcode },
11737     { "psraw",          { MS, Ib }, 0 },
11738   },
11739   {
11740     /* MOD_0F71_REG_6 */
11741     { Bad_Opcode },
11742     { "psllw",          { MS, Ib }, 0 },
11743   },
11744   {
11745     /* MOD_0F72_REG_2 */
11746     { Bad_Opcode },
11747     { "psrld",          { MS, Ib }, 0 },
11748   },
11749   {
11750     /* MOD_0F72_REG_4 */
11751     { Bad_Opcode },
11752     { "psrad",          { MS, Ib }, 0 },
11753   },
11754   {
11755     /* MOD_0F72_REG_6 */
11756     { Bad_Opcode },
11757     { "pslld",          { MS, Ib }, 0 },
11758   },
11759   {
11760     /* MOD_0F73_REG_2 */
11761     { Bad_Opcode },
11762     { "psrlq",          { MS, Ib }, 0 },
11763   },
11764   {
11765     /* MOD_0F73_REG_3 */
11766     { Bad_Opcode },
11767     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11768   },
11769   {
11770     /* MOD_0F73_REG_6 */
11771     { Bad_Opcode },
11772     { "psllq",          { MS, Ib }, 0 },
11773   },
11774   {
11775     /* MOD_0F73_REG_7 */
11776     { Bad_Opcode },
11777     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11778   },
11779   {
11780     /* MOD_0FAE_REG_0 */
11781     { "fxsave",         { FXSAVE }, 0 },
11782     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11783   },
11784   {
11785     /* MOD_0FAE_REG_1 */
11786     { "fxrstor",        { FXSAVE }, 0 },
11787     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11788   },
11789   {
11790     /* MOD_0FAE_REG_2 */
11791     { "ldmxcsr",        { Md }, 0 },
11792     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11793   },
11794   {
11795     /* MOD_0FAE_REG_3 */
11796     { "stmxcsr",        { Md }, 0 },
11797     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11798   },
11799   {
11800     /* MOD_0FAE_REG_4 */
11801     { "xsave",          { FXSAVE }, 0 },
11802   },
11803   {
11804     /* MOD_0FAE_REG_5 */
11805     { "xrstor",         { FXSAVE }, 0 },
11806     { RM_TABLE (RM_0FAE_REG_5) },
11807   },
11808   {
11809     /* MOD_0FAE_REG_6 */
11810     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11811     { RM_TABLE (RM_0FAE_REG_6) },
11812   },
11813   {
11814     /* MOD_0FAE_REG_7 */
11815     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11816     { RM_TABLE (RM_0FAE_REG_7) },
11817   },
11818   {
11819     /* MOD_0FB2 */
11820     { "lssS",           { Gv, Mp }, 0 },
11821   },
11822   {
11823     /* MOD_0FB4 */
11824     { "lfsS",           { Gv, Mp }, 0 },
11825   },
11826   {
11827     /* MOD_0FB5 */
11828     { "lgsS",           { Gv, Mp }, 0 },
11829   },
11830   {
11831     /* MOD_0FC3 */
11832     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11833   },
11834   {
11835     /* MOD_0FC7_REG_3 */
11836     { "xrstors",        { FXSAVE }, 0 },
11837   },
11838   {
11839     /* MOD_0FC7_REG_4 */
11840     { "xsavec",         { FXSAVE }, 0 },
11841   },
11842   {
11843     /* MOD_0FC7_REG_5 */
11844     { "xsaves",         { FXSAVE }, 0 },
11845   },
11846   {
11847     /* MOD_0FC7_REG_6 */
11848     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11849     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11850   },
11851   {
11852     /* MOD_0FC7_REG_7 */
11853     { "vmptrst",        { Mq }, 0 },
11854     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11855   },
11856   {
11857     /* MOD_0FD7 */
11858     { Bad_Opcode },
11859     { "pmovmskb",       { Gdq, MS }, 0 },
11860   },
11861   {
11862     /* MOD_0FE7_PREFIX_2 */
11863     { "movntdq",        { Mx, XM }, 0 },
11864   },
11865   {
11866     /* MOD_0FF0_PREFIX_3 */
11867     { "lddqu",          { XM, M }, 0 },
11868   },
11869   {
11870     /* MOD_0F382A_PREFIX_2 */
11871     { "movntdqa",       { XM, Mx }, 0 },
11872   },
11873   {
11874     /* MOD_62_32BIT */
11875     { "bound{S|}",      { Gv, Ma }, 0 },
11876     { EVEX_TABLE (EVEX_0F) },
11877   },
11878   {
11879     /* MOD_C4_32BIT */
11880     { "lesS",           { Gv, Mp }, 0 },
11881     { VEX_C4_TABLE (VEX_0F) },
11882   },
11883   {
11884     /* MOD_C5_32BIT */
11885     { "ldsS",           { Gv, Mp }, 0 },
11886     { VEX_C5_TABLE (VEX_0F) },
11887   },
11888   {
11889     /* MOD_VEX_0F12_PREFIX_0 */
11890     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11891     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11892   },
11893   {
11894     /* MOD_VEX_0F13 */
11895     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11896   },
11897   {
11898     /* MOD_VEX_0F16_PREFIX_0 */
11899     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11900     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11901   },
11902   {
11903     /* MOD_VEX_0F17 */
11904     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11905   },
11906   {
11907     /* MOD_VEX_0F2B */
11908     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11909   },
11910   {
11911     /* MOD_VEX_0F50 */
11912     { Bad_Opcode },
11913     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11914   },
11915   {
11916     /* MOD_VEX_0F71_REG_2 */
11917     { Bad_Opcode },
11918     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11919   },
11920   {
11921     /* MOD_VEX_0F71_REG_4 */
11922     { Bad_Opcode },
11923     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11924   },
11925   {
11926     /* MOD_VEX_0F71_REG_6 */
11927     { Bad_Opcode },
11928     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11929   },
11930   {
11931     /* MOD_VEX_0F72_REG_2 */
11932     { Bad_Opcode },
11933     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11934   },
11935   {
11936     /* MOD_VEX_0F72_REG_4 */
11937     { Bad_Opcode },
11938     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11939   },
11940   {
11941     /* MOD_VEX_0F72_REG_6 */
11942     { Bad_Opcode },
11943     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11944   },
11945   {
11946     /* MOD_VEX_0F73_REG_2 */
11947     { Bad_Opcode },
11948     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11949   },
11950   {
11951     /* MOD_VEX_0F73_REG_3 */
11952     { Bad_Opcode },
11953     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11954   },
11955   {
11956     /* MOD_VEX_0F73_REG_6 */
11957     { Bad_Opcode },
11958     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11959   },
11960   {
11961     /* MOD_VEX_0F73_REG_7 */
11962     { Bad_Opcode },
11963     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11964   },
11965   {
11966     /* MOD_VEX_0FAE_REG_2 */
11967     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11968   },
11969   {
11970     /* MOD_VEX_0FAE_REG_3 */
11971     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11972   },
11973   {
11974     /* MOD_VEX_0FD7_PREFIX_2 */
11975     { Bad_Opcode },
11976     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11977   },
11978   {
11979     /* MOD_VEX_0FE7_PREFIX_2 */
11980     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11981   },
11982   {
11983     /* MOD_VEX_0FF0_PREFIX_3 */
11984     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11985   },
11986   {
11987     /* MOD_VEX_0F381A_PREFIX_2 */
11988     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11989   },
11990   {
11991     /* MOD_VEX_0F382A_PREFIX_2 */
11992     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11993   },
11994   {
11995     /* MOD_VEX_0F382C_PREFIX_2 */
11996     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11997   },
11998   {
11999     /* MOD_VEX_0F382D_PREFIX_2 */
12000     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12001   },
12002   {
12003     /* MOD_VEX_0F382E_PREFIX_2 */
12004     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12005   },
12006   {
12007     /* MOD_VEX_0F382F_PREFIX_2 */
12008     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12009   },
12010   {
12011     /* MOD_VEX_0F385A_PREFIX_2 */
12012     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12013   },
12014   {
12015     /* MOD_VEX_0F388C_PREFIX_2 */
12016     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12017   },
12018   {
12019     /* MOD_VEX_0F388E_PREFIX_2 */
12020     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12021   },
12022 #define NEED_MOD_TABLE
12023 #include "i386-dis-evex.h"
12024 #undef NEED_MOD_TABLE
12025 };
12026
12027 static const struct dis386 rm_table[][8] = {
12028   {
12029     /* RM_C6_REG_7 */
12030     { "xabort",         { Skip_MODRM, Ib }, 0 },
12031   },
12032   {
12033     /* RM_C7_REG_7 */
12034     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12035   },
12036   {
12037     /* RM_0F01_REG_0 */
12038     { Bad_Opcode },
12039     { "vmcall",         { Skip_MODRM }, 0 },
12040     { "vmlaunch",       { Skip_MODRM }, 0 },
12041     { "vmresume",       { Skip_MODRM }, 0 },
12042     { "vmxoff",         { Skip_MODRM }, 0 },
12043   },
12044   {
12045     /* RM_0F01_REG_1 */
12046     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12047     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12048     { "clac",           { Skip_MODRM }, 0 },
12049     { "stac",           { Skip_MODRM }, 0 },
12050     { Bad_Opcode },
12051     { Bad_Opcode },
12052     { Bad_Opcode },
12053     { "encls",          { Skip_MODRM }, 0 },
12054   },
12055   {
12056     /* RM_0F01_REG_2 */
12057     { "xgetbv",         { Skip_MODRM }, 0 },
12058     { "xsetbv",         { Skip_MODRM }, 0 },
12059     { Bad_Opcode },
12060     { Bad_Opcode },
12061     { "vmfunc",         { Skip_MODRM }, 0 },
12062     { "xend",           { Skip_MODRM }, 0 },
12063     { "xtest",          { Skip_MODRM }, 0 },
12064     { "enclu",          { Skip_MODRM }, 0 },
12065   },
12066   {
12067     /* RM_0F01_REG_3 */
12068     { "vmrun",          { Skip_MODRM }, 0 },
12069     { "vmmcall",        { Skip_MODRM }, 0 },
12070     { "vmload",         { Skip_MODRM }, 0 },
12071     { "vmsave",         { Skip_MODRM }, 0 },
12072     { "stgi",           { Skip_MODRM }, 0 },
12073     { "clgi",           { Skip_MODRM }, 0 },
12074     { "skinit",         { Skip_MODRM }, 0 },
12075     { "invlpga",        { Skip_MODRM }, 0 },
12076   },
12077   {
12078     /* RM_0F01_REG_7 */
12079     { "swapgs",         { Skip_MODRM }, 0  },
12080     { "rdtscp",         { Skip_MODRM }, 0  },
12081     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12082     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12083     { "clzero",         { Skip_MODRM }, 0  },
12084   },
12085   {
12086     /* RM_0FAE_REG_5 */
12087     { "lfence",         { Skip_MODRM }, 0 },
12088   },
12089   {
12090     /* RM_0FAE_REG_6 */
12091     { "mfence",         { Skip_MODRM }, 0 },
12092   },
12093   {
12094     /* RM_0FAE_REG_7 */
12095     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12096   },
12097 };
12098
12099 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12100
12101 /* We use the high bit to indicate different name for the same
12102    prefix.  */
12103 #define REP_PREFIX      (0xf3 | 0x100)
12104 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12105 #define XRELEASE_PREFIX (0xf3 | 0x400)
12106 #define BND_PREFIX      (0xf2 | 0x400)
12107
12108 static int
12109 ckprefix (void)
12110 {
12111   int newrex, i, length;
12112   rex = 0;
12113   rex_ignored = 0;
12114   prefixes = 0;
12115   used_prefixes = 0;
12116   rex_used = 0;
12117   last_lock_prefix = -1;
12118   last_repz_prefix = -1;
12119   last_repnz_prefix = -1;
12120   last_data_prefix = -1;
12121   last_addr_prefix = -1;
12122   last_rex_prefix = -1;
12123   last_seg_prefix = -1;
12124   fwait_prefix = -1;
12125   active_seg_prefix = 0;
12126   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12127     all_prefixes[i] = 0;
12128   i = 0;
12129   length = 0;
12130   /* The maximum instruction length is 15bytes.  */
12131   while (length < MAX_CODE_LENGTH - 1)
12132     {
12133       FETCH_DATA (the_info, codep + 1);
12134       newrex = 0;
12135       switch (*codep)
12136         {
12137         /* REX prefixes family.  */
12138         case 0x40:
12139         case 0x41:
12140         case 0x42:
12141         case 0x43:
12142         case 0x44:
12143         case 0x45:
12144         case 0x46:
12145         case 0x47:
12146         case 0x48:
12147         case 0x49:
12148         case 0x4a:
12149         case 0x4b:
12150         case 0x4c:
12151         case 0x4d:
12152         case 0x4e:
12153         case 0x4f:
12154           if (address_mode == mode_64bit)
12155             newrex = *codep;
12156           else
12157             return 1;
12158           last_rex_prefix = i;
12159           break;
12160         case 0xf3:
12161           prefixes |= PREFIX_REPZ;
12162           last_repz_prefix = i;
12163           break;
12164         case 0xf2:
12165           prefixes |= PREFIX_REPNZ;
12166           last_repnz_prefix = i;
12167           break;
12168         case 0xf0:
12169           prefixes |= PREFIX_LOCK;
12170           last_lock_prefix = i;
12171           break;
12172         case 0x2e:
12173           prefixes |= PREFIX_CS;
12174           last_seg_prefix = i;
12175           active_seg_prefix = PREFIX_CS;
12176           break;
12177         case 0x36:
12178           prefixes |= PREFIX_SS;
12179           last_seg_prefix = i;
12180           active_seg_prefix = PREFIX_SS;
12181           break;
12182         case 0x3e:
12183           prefixes |= PREFIX_DS;
12184           last_seg_prefix = i;
12185           active_seg_prefix = PREFIX_DS;
12186           break;
12187         case 0x26:
12188           prefixes |= PREFIX_ES;
12189           last_seg_prefix = i;
12190           active_seg_prefix = PREFIX_ES;
12191           break;
12192         case 0x64:
12193           prefixes |= PREFIX_FS;
12194           last_seg_prefix = i;
12195           active_seg_prefix = PREFIX_FS;
12196           break;
12197         case 0x65:
12198           prefixes |= PREFIX_GS;
12199           last_seg_prefix = i;
12200           active_seg_prefix = PREFIX_GS;
12201           break;
12202         case 0x66:
12203           prefixes |= PREFIX_DATA;
12204           last_data_prefix = i;
12205           break;
12206         case 0x67:
12207           prefixes |= PREFIX_ADDR;
12208           last_addr_prefix = i;
12209           break;
12210         case FWAIT_OPCODE:
12211           /* fwait is really an instruction.  If there are prefixes
12212              before the fwait, they belong to the fwait, *not* to the
12213              following instruction.  */
12214           fwait_prefix = i;
12215           if (prefixes || rex)
12216             {
12217               prefixes |= PREFIX_FWAIT;
12218               codep++;
12219               /* This ensures that the previous REX prefixes are noticed
12220                  as unused prefixes, as in the return case below.  */
12221               rex_used = rex;
12222               return 1;
12223             }
12224           prefixes = PREFIX_FWAIT;
12225           break;
12226         default:
12227           return 1;
12228         }
12229       /* Rex is ignored when followed by another prefix.  */
12230       if (rex)
12231         {
12232           rex_used = rex;
12233           return 1;
12234         }
12235       if (*codep != FWAIT_OPCODE)
12236         all_prefixes[i++] = *codep;
12237       rex = newrex;
12238       codep++;
12239       length++;
12240     }
12241   return 0;
12242 }
12243
12244 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12245    prefix byte.  */
12246
12247 static const char *
12248 prefix_name (int pref, int sizeflag)
12249 {
12250   static const char *rexes [16] =
12251     {
12252       "rex",            /* 0x40 */
12253       "rex.B",          /* 0x41 */
12254       "rex.X",          /* 0x42 */
12255       "rex.XB",         /* 0x43 */
12256       "rex.R",          /* 0x44 */
12257       "rex.RB",         /* 0x45 */
12258       "rex.RX",         /* 0x46 */
12259       "rex.RXB",        /* 0x47 */
12260       "rex.W",          /* 0x48 */
12261       "rex.WB",         /* 0x49 */
12262       "rex.WX",         /* 0x4a */
12263       "rex.WXB",        /* 0x4b */
12264       "rex.WR",         /* 0x4c */
12265       "rex.WRB",        /* 0x4d */
12266       "rex.WRX",        /* 0x4e */
12267       "rex.WRXB",       /* 0x4f */
12268     };
12269
12270   switch (pref)
12271     {
12272     /* REX prefixes family.  */
12273     case 0x40:
12274     case 0x41:
12275     case 0x42:
12276     case 0x43:
12277     case 0x44:
12278     case 0x45:
12279     case 0x46:
12280     case 0x47:
12281     case 0x48:
12282     case 0x49:
12283     case 0x4a:
12284     case 0x4b:
12285     case 0x4c:
12286     case 0x4d:
12287     case 0x4e:
12288     case 0x4f:
12289       return rexes [pref - 0x40];
12290     case 0xf3:
12291       return "repz";
12292     case 0xf2:
12293       return "repnz";
12294     case 0xf0:
12295       return "lock";
12296     case 0x2e:
12297       return "cs";
12298     case 0x36:
12299       return "ss";
12300     case 0x3e:
12301       return "ds";
12302     case 0x26:
12303       return "es";
12304     case 0x64:
12305       return "fs";
12306     case 0x65:
12307       return "gs";
12308     case 0x66:
12309       return (sizeflag & DFLAG) ? "data16" : "data32";
12310     case 0x67:
12311       if (address_mode == mode_64bit)
12312         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12313       else
12314         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12315     case FWAIT_OPCODE:
12316       return "fwait";
12317     case REP_PREFIX:
12318       return "rep";
12319     case XACQUIRE_PREFIX:
12320       return "xacquire";
12321     case XRELEASE_PREFIX:
12322       return "xrelease";
12323     case BND_PREFIX:
12324       return "bnd";
12325     default:
12326       return NULL;
12327     }
12328 }
12329
12330 static char op_out[MAX_OPERANDS][100];
12331 static int op_ad, op_index[MAX_OPERANDS];
12332 static int two_source_ops;
12333 static bfd_vma op_address[MAX_OPERANDS];
12334 static bfd_vma op_riprel[MAX_OPERANDS];
12335 static bfd_vma start_pc;
12336
12337 /*
12338  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12339  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12340  *   section of the "Virtual 8086 Mode" chapter.)
12341  * 'pc' should be the address of this instruction, it will
12342  *   be used to print the target address if this is a relative jump or call
12343  * The function returns the length of this instruction in bytes.
12344  */
12345
12346 static char intel_syntax;
12347 static char intel_mnemonic = !SYSV386_COMPAT;
12348 static char open_char;
12349 static char close_char;
12350 static char separator_char;
12351 static char scale_char;
12352
12353 enum x86_64_isa
12354 {
12355   amd64 = 0,
12356   intel64
12357 };
12358
12359 static enum x86_64_isa isa64;
12360
12361 /* Here for backwards compatibility.  When gdb stops using
12362    print_insn_i386_att and print_insn_i386_intel these functions can
12363    disappear, and print_insn_i386 be merged into print_insn.  */
12364 int
12365 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12366 {
12367   intel_syntax = 0;
12368
12369   return print_insn (pc, info);
12370 }
12371
12372 int
12373 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12374 {
12375   intel_syntax = 1;
12376
12377   return print_insn (pc, info);
12378 }
12379
12380 int
12381 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12382 {
12383   intel_syntax = -1;
12384
12385   return print_insn (pc, info);
12386 }
12387
12388 void
12389 print_i386_disassembler_options (FILE *stream)
12390 {
12391   fprintf (stream, _("\n\
12392 The following i386/x86-64 specific disassembler options are supported for use\n\
12393 with the -M switch (multiple options should be separated by commas):\n"));
12394
12395   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12396   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12397   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12398   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12399   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12400   fprintf (stream, _("  att-mnemonic\n"
12401                      "              Display instruction in AT&T mnemonic\n"));
12402   fprintf (stream, _("  intel-mnemonic\n"
12403                      "              Display instruction in Intel mnemonic\n"));
12404   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12405   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12406   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12407   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12408   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12409   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12410   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12411   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12412 }
12413
12414 /* Bad opcode.  */
12415 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12416
12417 /* Get a pointer to struct dis386 with a valid name.  */
12418
12419 static const struct dis386 *
12420 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12421 {
12422   int vindex, vex_table_index;
12423
12424   if (dp->name != NULL)
12425     return dp;
12426
12427   switch (dp->op[0].bytemode)
12428     {
12429     case USE_REG_TABLE:
12430       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12431       break;
12432
12433     case USE_MOD_TABLE:
12434       vindex = modrm.mod == 0x3 ? 1 : 0;
12435       dp = &mod_table[dp->op[1].bytemode][vindex];
12436       break;
12437
12438     case USE_RM_TABLE:
12439       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12440       break;
12441
12442     case USE_PREFIX_TABLE:
12443       if (need_vex)
12444         {
12445           /* The prefix in VEX is implicit.  */
12446           switch (vex.prefix)
12447             {
12448             case 0:
12449               vindex = 0;
12450               break;
12451             case REPE_PREFIX_OPCODE:
12452               vindex = 1;
12453               break;
12454             case DATA_PREFIX_OPCODE:
12455               vindex = 2;
12456               break;
12457             case REPNE_PREFIX_OPCODE:
12458               vindex = 3;
12459               break;
12460             default:
12461               abort ();
12462               break;
12463             }
12464         }
12465       else
12466         {
12467           int last_prefix = -1;
12468           int prefix = 0;
12469           vindex = 0;
12470           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12471              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12472              last one wins.  */
12473           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12474             {
12475               if (last_repz_prefix > last_repnz_prefix)
12476                 {
12477                   vindex = 1;
12478                   prefix = PREFIX_REPZ;
12479                   last_prefix = last_repz_prefix;
12480                 }
12481               else
12482                 {
12483                   vindex = 3;
12484                   prefix = PREFIX_REPNZ;
12485                   last_prefix = last_repnz_prefix;
12486                 }
12487
12488               /* Check if prefix should be ignored.  */
12489               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12490                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12491                    & prefix) != 0)
12492                 vindex = 0;
12493             }
12494
12495           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12496             {
12497               vindex = 2;
12498               prefix = PREFIX_DATA;
12499               last_prefix = last_data_prefix;
12500             }
12501
12502           if (vindex != 0)
12503             {
12504               used_prefixes |= prefix;
12505               all_prefixes[last_prefix] = 0;
12506             }
12507         }
12508       dp = &prefix_table[dp->op[1].bytemode][vindex];
12509       break;
12510
12511     case USE_X86_64_TABLE:
12512       vindex = address_mode == mode_64bit ? 1 : 0;
12513       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12514       break;
12515
12516     case USE_3BYTE_TABLE:
12517       FETCH_DATA (info, codep + 2);
12518       vindex = *codep++;
12519       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12520       end_codep = codep;
12521       modrm.mod = (*codep >> 6) & 3;
12522       modrm.reg = (*codep >> 3) & 7;
12523       modrm.rm = *codep & 7;
12524       break;
12525
12526     case USE_VEX_LEN_TABLE:
12527       if (!need_vex)
12528         abort ();
12529
12530       switch (vex.length)
12531         {
12532         case 128:
12533           vindex = 0;
12534           break;
12535         case 256:
12536           vindex = 1;
12537           break;
12538         default:
12539           abort ();
12540           break;
12541         }
12542
12543       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12544       break;
12545
12546     case USE_XOP_8F_TABLE:
12547       FETCH_DATA (info, codep + 3);
12548       /* All bits in the REX prefix are ignored.  */
12549       rex_ignored = rex;
12550       rex = ~(*codep >> 5) & 0x7;
12551
12552       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12553       switch ((*codep & 0x1f))
12554         {
12555         default:
12556           dp = &bad_opcode;
12557           return dp;
12558         case 0x8:
12559           vex_table_index = XOP_08;
12560           break;
12561         case 0x9:
12562           vex_table_index = XOP_09;
12563           break;
12564         case 0xa:
12565           vex_table_index = XOP_0A;
12566           break;
12567         }
12568       codep++;
12569       vex.w = *codep & 0x80;
12570       if (vex.w && address_mode == mode_64bit)
12571         rex |= REX_W;
12572
12573       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12574       if (address_mode != mode_64bit
12575           && vex.register_specifier > 0x7)
12576         {
12577           dp = &bad_opcode;
12578           return dp;
12579         }
12580
12581       vex.length = (*codep & 0x4) ? 256 : 128;
12582       switch ((*codep & 0x3))
12583         {
12584         case 0:
12585           vex.prefix = 0;
12586           break;
12587         case 1:
12588           vex.prefix = DATA_PREFIX_OPCODE;
12589           break;
12590         case 2:
12591           vex.prefix = REPE_PREFIX_OPCODE;
12592           break;
12593         case 3:
12594           vex.prefix = REPNE_PREFIX_OPCODE;
12595           break;
12596         }
12597       need_vex = 1;
12598       need_vex_reg = 1;
12599       codep++;
12600       vindex = *codep++;
12601       dp = &xop_table[vex_table_index][vindex];
12602
12603       end_codep = codep;
12604       FETCH_DATA (info, codep + 1);
12605       modrm.mod = (*codep >> 6) & 3;
12606       modrm.reg = (*codep >> 3) & 7;
12607       modrm.rm = *codep & 7;
12608       break;
12609
12610     case USE_VEX_C4_TABLE:
12611       /* VEX prefix.  */
12612       FETCH_DATA (info, codep + 3);
12613       /* All bits in the REX prefix are ignored.  */
12614       rex_ignored = rex;
12615       rex = ~(*codep >> 5) & 0x7;
12616       switch ((*codep & 0x1f))
12617         {
12618         default:
12619           dp = &bad_opcode;
12620           return dp;
12621         case 0x1:
12622           vex_table_index = VEX_0F;
12623           break;
12624         case 0x2:
12625           vex_table_index = VEX_0F38;
12626           break;
12627         case 0x3:
12628           vex_table_index = VEX_0F3A;
12629           break;
12630         }
12631       codep++;
12632       vex.w = *codep & 0x80;
12633       if (vex.w && address_mode == mode_64bit)
12634         rex |= REX_W;
12635
12636       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12637       if (address_mode != mode_64bit
12638           && vex.register_specifier > 0x7)
12639         {
12640           dp = &bad_opcode;
12641           return dp;
12642         }
12643
12644       vex.length = (*codep & 0x4) ? 256 : 128;
12645       switch ((*codep & 0x3))
12646         {
12647         case 0:
12648           vex.prefix = 0;
12649           break;
12650         case 1:
12651           vex.prefix = DATA_PREFIX_OPCODE;
12652           break;
12653         case 2:
12654           vex.prefix = REPE_PREFIX_OPCODE;
12655           break;
12656         case 3:
12657           vex.prefix = REPNE_PREFIX_OPCODE;
12658           break;
12659         }
12660       need_vex = 1;
12661       need_vex_reg = 1;
12662       codep++;
12663       vindex = *codep++;
12664       dp = &vex_table[vex_table_index][vindex];
12665       end_codep = codep;
12666       /* There is no MODRM byte for VEX [82|77].  */
12667       if (vindex != 0x77 && vindex != 0x82)
12668         {
12669           FETCH_DATA (info, codep + 1);
12670           modrm.mod = (*codep >> 6) & 3;
12671           modrm.reg = (*codep >> 3) & 7;
12672           modrm.rm = *codep & 7;
12673         }
12674       break;
12675
12676     case USE_VEX_C5_TABLE:
12677       /* VEX prefix.  */
12678       FETCH_DATA (info, codep + 2);
12679       /* All bits in the REX prefix are ignored.  */
12680       rex_ignored = rex;
12681       rex = (*codep & 0x80) ? 0 : REX_R;
12682
12683       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12684       if (address_mode != mode_64bit
12685           && vex.register_specifier > 0x7)
12686         {
12687           dp = &bad_opcode;
12688           return dp;
12689         }
12690
12691       vex.w = 0;
12692
12693       vex.length = (*codep & 0x4) ? 256 : 128;
12694       switch ((*codep & 0x3))
12695         {
12696         case 0:
12697           vex.prefix = 0;
12698           break;
12699         case 1:
12700           vex.prefix = DATA_PREFIX_OPCODE;
12701           break;
12702         case 2:
12703           vex.prefix = REPE_PREFIX_OPCODE;
12704           break;
12705         case 3:
12706           vex.prefix = REPNE_PREFIX_OPCODE;
12707           break;
12708         }
12709       need_vex = 1;
12710       need_vex_reg = 1;
12711       codep++;
12712       vindex = *codep++;
12713       dp = &vex_table[dp->op[1].bytemode][vindex];
12714       end_codep = codep;
12715       /* There is no MODRM byte for VEX [82|77].  */
12716       if (vindex != 0x77 && vindex != 0x82)
12717         {
12718           FETCH_DATA (info, codep + 1);
12719           modrm.mod = (*codep >> 6) & 3;
12720           modrm.reg = (*codep >> 3) & 7;
12721           modrm.rm = *codep & 7;
12722         }
12723       break;
12724
12725     case USE_VEX_W_TABLE:
12726       if (!need_vex)
12727         abort ();
12728
12729       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12730       break;
12731
12732     case USE_EVEX_TABLE:
12733       two_source_ops = 0;
12734       /* EVEX prefix.  */
12735       vex.evex = 1;
12736       FETCH_DATA (info, codep + 4);
12737       /* All bits in the REX prefix are ignored.  */
12738       rex_ignored = rex;
12739       /* The first byte after 0x62.  */
12740       rex = ~(*codep >> 5) & 0x7;
12741       vex.r = *codep & 0x10;
12742       switch ((*codep & 0xf))
12743         {
12744         default:
12745           return &bad_opcode;
12746         case 0x1:
12747           vex_table_index = EVEX_0F;
12748           break;
12749         case 0x2:
12750           vex_table_index = EVEX_0F38;
12751           break;
12752         case 0x3:
12753           vex_table_index = EVEX_0F3A;
12754           break;
12755         }
12756
12757       /* The second byte after 0x62.  */
12758       codep++;
12759       vex.w = *codep & 0x80;
12760       if (vex.w && address_mode == mode_64bit)
12761         rex |= REX_W;
12762
12763       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12764       if (address_mode != mode_64bit)
12765         {
12766           /* In 16/32-bit mode silently ignore following bits.  */
12767           rex &= ~REX_B;
12768           vex.r = 1;
12769           vex.v = 1;
12770           vex.register_specifier &= 0x7;
12771         }
12772
12773       /* The U bit.  */
12774       if (!(*codep & 0x4))
12775         return &bad_opcode;
12776
12777       switch ((*codep & 0x3))
12778         {
12779         case 0:
12780           vex.prefix = 0;
12781           break;
12782         case 1:
12783           vex.prefix = DATA_PREFIX_OPCODE;
12784           break;
12785         case 2:
12786           vex.prefix = REPE_PREFIX_OPCODE;
12787           break;
12788         case 3:
12789           vex.prefix = REPNE_PREFIX_OPCODE;
12790           break;
12791         }
12792
12793       /* The third byte after 0x62.  */
12794       codep++;
12795
12796       /* Remember the static rounding bits.  */
12797       vex.ll = (*codep >> 5) & 3;
12798       vex.b = (*codep & 0x10) != 0;
12799
12800       vex.v = *codep & 0x8;
12801       vex.mask_register_specifier = *codep & 0x7;
12802       vex.zeroing = *codep & 0x80;
12803
12804       need_vex = 1;
12805       need_vex_reg = 1;
12806       codep++;
12807       vindex = *codep++;
12808       dp = &evex_table[vex_table_index][vindex];
12809       end_codep = codep;
12810       FETCH_DATA (info, codep + 1);
12811       modrm.mod = (*codep >> 6) & 3;
12812       modrm.reg = (*codep >> 3) & 7;
12813       modrm.rm = *codep & 7;
12814
12815       /* Set vector length.  */
12816       if (modrm.mod == 3 && vex.b)
12817         vex.length = 512;
12818       else
12819         {
12820           switch (vex.ll)
12821             {
12822             case 0x0:
12823               vex.length = 128;
12824               break;
12825             case 0x1:
12826               vex.length = 256;
12827               break;
12828             case 0x2:
12829               vex.length = 512;
12830               break;
12831             default:
12832               return &bad_opcode;
12833             }
12834         }
12835       break;
12836
12837     case 0:
12838       dp = &bad_opcode;
12839       break;
12840
12841     default:
12842       abort ();
12843     }
12844
12845   if (dp->name != NULL)
12846     return dp;
12847   else
12848     return get_valid_dis386 (dp, info);
12849 }
12850
12851 static void
12852 get_sib (disassemble_info *info, int sizeflag)
12853 {
12854   /* If modrm.mod == 3, operand must be register.  */
12855   if (need_modrm
12856       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12857       && modrm.mod != 3
12858       && modrm.rm == 4)
12859     {
12860       FETCH_DATA (info, codep + 2);
12861       sib.index = (codep [1] >> 3) & 7;
12862       sib.scale = (codep [1] >> 6) & 3;
12863       sib.base = codep [1] & 7;
12864     }
12865 }
12866
12867 static int
12868 print_insn (bfd_vma pc, disassemble_info *info)
12869 {
12870   const struct dis386 *dp;
12871   int i;
12872   char *op_txt[MAX_OPERANDS];
12873   int needcomma;
12874   int sizeflag, orig_sizeflag;
12875   const char *p;
12876   struct dis_private priv;
12877   int prefix_length;
12878
12879   priv.orig_sizeflag = AFLAG | DFLAG;
12880   if ((info->mach & bfd_mach_i386_i386) != 0)
12881     address_mode = mode_32bit;
12882   else if (info->mach == bfd_mach_i386_i8086)
12883     {
12884       address_mode = mode_16bit;
12885       priv.orig_sizeflag = 0;
12886     }
12887   else
12888     address_mode = mode_64bit;
12889
12890   if (intel_syntax == (char) -1)
12891     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12892
12893   for (p = info->disassembler_options; p != NULL; )
12894     {
12895       if (CONST_STRNEQ (p, "amd64"))
12896         isa64 = amd64;
12897       else if (CONST_STRNEQ (p, "intel64"))
12898         isa64 = intel64;
12899       else if (CONST_STRNEQ (p, "x86-64"))
12900         {
12901           address_mode = mode_64bit;
12902           priv.orig_sizeflag = AFLAG | DFLAG;
12903         }
12904       else if (CONST_STRNEQ (p, "i386"))
12905         {
12906           address_mode = mode_32bit;
12907           priv.orig_sizeflag = AFLAG | DFLAG;
12908         }
12909       else if (CONST_STRNEQ (p, "i8086"))
12910         {
12911           address_mode = mode_16bit;
12912           priv.orig_sizeflag = 0;
12913         }
12914       else if (CONST_STRNEQ (p, "intel"))
12915         {
12916           intel_syntax = 1;
12917           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12918             intel_mnemonic = 1;
12919         }
12920       else if (CONST_STRNEQ (p, "att"))
12921         {
12922           intel_syntax = 0;
12923           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12924             intel_mnemonic = 0;
12925         }
12926       else if (CONST_STRNEQ (p, "addr"))
12927         {
12928           if (address_mode == mode_64bit)
12929             {
12930               if (p[4] == '3' && p[5] == '2')
12931                 priv.orig_sizeflag &= ~AFLAG;
12932               else if (p[4] == '6' && p[5] == '4')
12933                 priv.orig_sizeflag |= AFLAG;
12934             }
12935           else
12936             {
12937               if (p[4] == '1' && p[5] == '6')
12938                 priv.orig_sizeflag &= ~AFLAG;
12939               else if (p[4] == '3' && p[5] == '2')
12940                 priv.orig_sizeflag |= AFLAG;
12941             }
12942         }
12943       else if (CONST_STRNEQ (p, "data"))
12944         {
12945           if (p[4] == '1' && p[5] == '6')
12946             priv.orig_sizeflag &= ~DFLAG;
12947           else if (p[4] == '3' && p[5] == '2')
12948             priv.orig_sizeflag |= DFLAG;
12949         }
12950       else if (CONST_STRNEQ (p, "suffix"))
12951         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12952
12953       p = strchr (p, ',');
12954       if (p != NULL)
12955         p++;
12956     }
12957
12958   if (intel_syntax)
12959     {
12960       names64 = intel_names64;
12961       names32 = intel_names32;
12962       names16 = intel_names16;
12963       names8 = intel_names8;
12964       names8rex = intel_names8rex;
12965       names_seg = intel_names_seg;
12966       names_mm = intel_names_mm;
12967       names_bnd = intel_names_bnd;
12968       names_xmm = intel_names_xmm;
12969       names_ymm = intel_names_ymm;
12970       names_zmm = intel_names_zmm;
12971       index64 = intel_index64;
12972       index32 = intel_index32;
12973       names_mask = intel_names_mask;
12974       index16 = intel_index16;
12975       open_char = '[';
12976       close_char = ']';
12977       separator_char = '+';
12978       scale_char = '*';
12979     }
12980   else
12981     {
12982       names64 = att_names64;
12983       names32 = att_names32;
12984       names16 = att_names16;
12985       names8 = att_names8;
12986       names8rex = att_names8rex;
12987       names_seg = att_names_seg;
12988       names_mm = att_names_mm;
12989       names_bnd = att_names_bnd;
12990       names_xmm = att_names_xmm;
12991       names_ymm = att_names_ymm;
12992       names_zmm = att_names_zmm;
12993       index64 = att_index64;
12994       index32 = att_index32;
12995       names_mask = att_names_mask;
12996       index16 = att_index16;
12997       open_char = '(';
12998       close_char =  ')';
12999       separator_char = ',';
13000       scale_char = ',';
13001     }
13002
13003   /* The output looks better if we put 7 bytes on a line, since that
13004      puts most long word instructions on a single line.  Use 8 bytes
13005      for Intel L1OM.  */
13006   if ((info->mach & bfd_mach_l1om) != 0)
13007     info->bytes_per_line = 8;
13008   else
13009     info->bytes_per_line = 7;
13010
13011   info->private_data = &priv;
13012   priv.max_fetched = priv.the_buffer;
13013   priv.insn_start = pc;
13014
13015   obuf[0] = 0;
13016   for (i = 0; i < MAX_OPERANDS; ++i)
13017     {
13018       op_out[i][0] = 0;
13019       op_index[i] = -1;
13020     }
13021
13022   the_info = info;
13023   start_pc = pc;
13024   start_codep = priv.the_buffer;
13025   codep = priv.the_buffer;
13026
13027   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13028     {
13029       const char *name;
13030
13031       /* Getting here means we tried for data but didn't get it.  That
13032          means we have an incomplete instruction of some sort.  Just
13033          print the first byte as a prefix or a .byte pseudo-op.  */
13034       if (codep > priv.the_buffer)
13035         {
13036           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13037           if (name != NULL)
13038             (*info->fprintf_func) (info->stream, "%s", name);
13039           else
13040             {
13041               /* Just print the first byte as a .byte instruction.  */
13042               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13043                                      (unsigned int) priv.the_buffer[0]);
13044             }
13045
13046           return 1;
13047         }
13048
13049       return -1;
13050     }
13051
13052   obufp = obuf;
13053   sizeflag = priv.orig_sizeflag;
13054
13055   if (!ckprefix () || rex_used)
13056     {
13057       /* Too many prefixes or unused REX prefixes.  */
13058       for (i = 0;
13059            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13060            i++)
13061         (*info->fprintf_func) (info->stream, "%s%s",
13062                                i == 0 ? "" : " ",
13063                                prefix_name (all_prefixes[i], sizeflag));
13064       return i;
13065     }
13066
13067   insn_codep = codep;
13068
13069   FETCH_DATA (info, codep + 1);
13070   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13071
13072   if (((prefixes & PREFIX_FWAIT)
13073        && ((*codep < 0xd8) || (*codep > 0xdf))))
13074     {
13075       /* Handle prefixes before fwait.  */
13076       for (i = 0; i < fwait_prefix && all_prefixes[i];
13077            i++)
13078         (*info->fprintf_func) (info->stream, "%s ",
13079                                prefix_name (all_prefixes[i], sizeflag));
13080       (*info->fprintf_func) (info->stream, "fwait");
13081       return i + 1;
13082     }
13083
13084   if (*codep == 0x0f)
13085     {
13086       unsigned char threebyte;
13087       FETCH_DATA (info, codep + 2);
13088       threebyte = *++codep;
13089       dp = &dis386_twobyte[threebyte];
13090       need_modrm = twobyte_has_modrm[*codep];
13091       codep++;
13092     }
13093   else
13094     {
13095       dp = &dis386[*codep];
13096       need_modrm = onebyte_has_modrm[*codep];
13097       codep++;
13098     }
13099
13100   /* Save sizeflag for printing the extra prefixes later before updating
13101      it for mnemonic and operand processing.  The prefix names depend
13102      only on the address mode.  */
13103   orig_sizeflag = sizeflag;
13104   if (prefixes & PREFIX_ADDR)
13105     sizeflag ^= AFLAG;
13106   if ((prefixes & PREFIX_DATA))
13107     sizeflag ^= DFLAG;
13108
13109   end_codep = codep;
13110   if (need_modrm)
13111     {
13112       FETCH_DATA (info, codep + 1);
13113       modrm.mod = (*codep >> 6) & 3;
13114       modrm.reg = (*codep >> 3) & 7;
13115       modrm.rm = *codep & 7;
13116     }
13117
13118   need_vex = 0;
13119   need_vex_reg = 0;
13120   vex_w_done = 0;
13121   vex.evex = 0;
13122
13123   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13124     {
13125       get_sib (info, sizeflag);
13126       dofloat (sizeflag);
13127     }
13128   else
13129     {
13130       dp = get_valid_dis386 (dp, info);
13131       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13132         {
13133           get_sib (info, sizeflag);
13134           for (i = 0; i < MAX_OPERANDS; ++i)
13135             {
13136               obufp = op_out[i];
13137               op_ad = MAX_OPERANDS - 1 - i;
13138               if (dp->op[i].rtn)
13139                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13140               /* For EVEX instruction after the last operand masking
13141                  should be printed.  */
13142               if (i == 0 && vex.evex)
13143                 {
13144                   /* Don't print {%k0}.  */
13145                   if (vex.mask_register_specifier)
13146                     {
13147                       oappend ("{");
13148                       oappend (names_mask[vex.mask_register_specifier]);
13149                       oappend ("}");
13150                     }
13151                   if (vex.zeroing)
13152                     oappend ("{z}");
13153                 }
13154             }
13155         }
13156     }
13157
13158   /* Check if the REX prefix is used.  */
13159   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13160     all_prefixes[last_rex_prefix] = 0;
13161
13162   /* Check if the SEG prefix is used.  */
13163   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13164                    | PREFIX_FS | PREFIX_GS)) != 0
13165       && (used_prefixes & active_seg_prefix) != 0)
13166     all_prefixes[last_seg_prefix] = 0;
13167
13168   /* Check if the ADDR prefix is used.  */
13169   if ((prefixes & PREFIX_ADDR) != 0
13170       && (used_prefixes & PREFIX_ADDR) != 0)
13171     all_prefixes[last_addr_prefix] = 0;
13172
13173   /* Check if the DATA prefix is used.  */
13174   if ((prefixes & PREFIX_DATA) != 0
13175       && (used_prefixes & PREFIX_DATA) != 0)
13176     all_prefixes[last_data_prefix] = 0;
13177
13178   /* Print the extra prefixes.  */
13179   prefix_length = 0;
13180   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13181     if (all_prefixes[i])
13182       {
13183         const char *name;
13184         name = prefix_name (all_prefixes[i], orig_sizeflag);
13185         if (name == NULL)
13186           abort ();
13187         prefix_length += strlen (name) + 1;
13188         (*info->fprintf_func) (info->stream, "%s ", name);
13189       }
13190
13191   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13192      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13193      used by putop and MMX/SSE operand and may be overriden by the
13194      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13195      separately.  */
13196   if (dp->prefix_requirement == PREFIX_OPCODE
13197       && dp != &bad_opcode
13198       && (((prefixes
13199             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13200            && (used_prefixes
13201                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13202           || ((((prefixes
13203                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13204                 == PREFIX_DATA)
13205                && (used_prefixes & PREFIX_DATA) == 0))))
13206     {
13207       (*info->fprintf_func) (info->stream, "(bad)");
13208       return end_codep - priv.the_buffer;
13209     }
13210
13211   /* Check maximum code length.  */
13212   if ((codep - start_codep) > MAX_CODE_LENGTH)
13213     {
13214       (*info->fprintf_func) (info->stream, "(bad)");
13215       return MAX_CODE_LENGTH;
13216     }
13217
13218   obufp = mnemonicendp;
13219   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13220     oappend (" ");
13221   oappend (" ");
13222   (*info->fprintf_func) (info->stream, "%s", obuf);
13223
13224   /* The enter and bound instructions are printed with operands in the same
13225      order as the intel book; everything else is printed in reverse order.  */
13226   if (intel_syntax || two_source_ops)
13227     {
13228       bfd_vma riprel;
13229
13230       for (i = 0; i < MAX_OPERANDS; ++i)
13231         op_txt[i] = op_out[i];
13232
13233       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13234           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13235         {
13236           op_txt[2] = op_out[3];
13237           op_txt[3] = op_out[2];
13238         }
13239
13240       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13241         {
13242           op_ad = op_index[i];
13243           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13244           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13245           riprel = op_riprel[i];
13246           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13247           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13248         }
13249     }
13250   else
13251     {
13252       for (i = 0; i < MAX_OPERANDS; ++i)
13253         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13254     }
13255
13256   needcomma = 0;
13257   for (i = 0; i < MAX_OPERANDS; ++i)
13258     if (*op_txt[i])
13259       {
13260         if (needcomma)
13261           (*info->fprintf_func) (info->stream, ",");
13262         if (op_index[i] != -1 && !op_riprel[i])
13263           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13264         else
13265           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13266         needcomma = 1;
13267       }
13268
13269   for (i = 0; i < MAX_OPERANDS; i++)
13270     if (op_index[i] != -1 && op_riprel[i])
13271       {
13272         (*info->fprintf_func) (info->stream, "        # ");
13273         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13274                                                 + op_address[op_index[i]]), info);
13275         break;
13276       }
13277   return codep - priv.the_buffer;
13278 }
13279
13280 static const char *float_mem[] = {
13281   /* d8 */
13282   "fadd{s|}",
13283   "fmul{s|}",
13284   "fcom{s|}",
13285   "fcomp{s|}",
13286   "fsub{s|}",
13287   "fsubr{s|}",
13288   "fdiv{s|}",
13289   "fdivr{s|}",
13290   /* d9 */
13291   "fld{s|}",
13292   "(bad)",
13293   "fst{s|}",
13294   "fstp{s|}",
13295   "fldenvIC",
13296   "fldcw",
13297   "fNstenvIC",
13298   "fNstcw",
13299   /* da */
13300   "fiadd{l|}",
13301   "fimul{l|}",
13302   "ficom{l|}",
13303   "ficomp{l|}",
13304   "fisub{l|}",
13305   "fisubr{l|}",
13306   "fidiv{l|}",
13307   "fidivr{l|}",
13308   /* db */
13309   "fild{l|}",
13310   "fisttp{l|}",
13311   "fist{l|}",
13312   "fistp{l|}",
13313   "(bad)",
13314   "fld{t||t|}",
13315   "(bad)",
13316   "fstp{t||t|}",
13317   /* dc */
13318   "fadd{l|}",
13319   "fmul{l|}",
13320   "fcom{l|}",
13321   "fcomp{l|}",
13322   "fsub{l|}",
13323   "fsubr{l|}",
13324   "fdiv{l|}",
13325   "fdivr{l|}",
13326   /* dd */
13327   "fld{l|}",
13328   "fisttp{ll|}",
13329   "fst{l||}",
13330   "fstp{l|}",
13331   "frstorIC",
13332   "(bad)",
13333   "fNsaveIC",
13334   "fNstsw",
13335   /* de */
13336   "fiadd",
13337   "fimul",
13338   "ficom",
13339   "ficomp",
13340   "fisub",
13341   "fisubr",
13342   "fidiv",
13343   "fidivr",
13344   /* df */
13345   "fild",
13346   "fisttp",
13347   "fist",
13348   "fistp",
13349   "fbld",
13350   "fild{ll|}",
13351   "fbstp",
13352   "fistp{ll|}",
13353 };
13354
13355 static const unsigned char float_mem_mode[] = {
13356   /* d8 */
13357   d_mode,
13358   d_mode,
13359   d_mode,
13360   d_mode,
13361   d_mode,
13362   d_mode,
13363   d_mode,
13364   d_mode,
13365   /* d9 */
13366   d_mode,
13367   0,
13368   d_mode,
13369   d_mode,
13370   0,
13371   w_mode,
13372   0,
13373   w_mode,
13374   /* da */
13375   d_mode,
13376   d_mode,
13377   d_mode,
13378   d_mode,
13379   d_mode,
13380   d_mode,
13381   d_mode,
13382   d_mode,
13383   /* db */
13384   d_mode,
13385   d_mode,
13386   d_mode,
13387   d_mode,
13388   0,
13389   t_mode,
13390   0,
13391   t_mode,
13392   /* dc */
13393   q_mode,
13394   q_mode,
13395   q_mode,
13396   q_mode,
13397   q_mode,
13398   q_mode,
13399   q_mode,
13400   q_mode,
13401   /* dd */
13402   q_mode,
13403   q_mode,
13404   q_mode,
13405   q_mode,
13406   0,
13407   0,
13408   0,
13409   w_mode,
13410   /* de */
13411   w_mode,
13412   w_mode,
13413   w_mode,
13414   w_mode,
13415   w_mode,
13416   w_mode,
13417   w_mode,
13418   w_mode,
13419   /* df */
13420   w_mode,
13421   w_mode,
13422   w_mode,
13423   w_mode,
13424   t_mode,
13425   q_mode,
13426   t_mode,
13427   q_mode
13428 };
13429
13430 #define ST { OP_ST, 0 }
13431 #define STi { OP_STi, 0 }
13432
13433 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13434 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13435 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13436 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13437 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13438 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13439 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13440 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13441 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13442
13443 static const struct dis386 float_reg[][8] = {
13444   /* d8 */
13445   {
13446     { "fadd",   { ST, STi }, 0 },
13447     { "fmul",   { ST, STi }, 0 },
13448     { "fcom",   { STi }, 0 },
13449     { "fcomp",  { STi }, 0 },
13450     { "fsub",   { ST, STi }, 0 },
13451     { "fsubr",  { ST, STi }, 0 },
13452     { "fdiv",   { ST, STi }, 0 },
13453     { "fdivr",  { ST, STi }, 0 },
13454   },
13455   /* d9 */
13456   {
13457     { "fld",    { STi }, 0 },
13458     { "fxch",   { STi }, 0 },
13459     { FGRPd9_2 },
13460     { Bad_Opcode },
13461     { FGRPd9_4 },
13462     { FGRPd9_5 },
13463     { FGRPd9_6 },
13464     { FGRPd9_7 },
13465   },
13466   /* da */
13467   {
13468     { "fcmovb", { ST, STi }, 0 },
13469     { "fcmove", { ST, STi }, 0 },
13470     { "fcmovbe",{ ST, STi }, 0 },
13471     { "fcmovu", { ST, STi }, 0 },
13472     { Bad_Opcode },
13473     { FGRPda_5 },
13474     { Bad_Opcode },
13475     { Bad_Opcode },
13476   },
13477   /* db */
13478   {
13479     { "fcmovnb",{ ST, STi }, 0 },
13480     { "fcmovne",{ ST, STi }, 0 },
13481     { "fcmovnbe",{ ST, STi }, 0 },
13482     { "fcmovnu",{ ST, STi }, 0 },
13483     { FGRPdb_4 },
13484     { "fucomi", { ST, STi }, 0 },
13485     { "fcomi",  { ST, STi }, 0 },
13486     { Bad_Opcode },
13487   },
13488   /* dc */
13489   {
13490     { "fadd",   { STi, ST }, 0 },
13491     { "fmul",   { STi, ST }, 0 },
13492     { Bad_Opcode },
13493     { Bad_Opcode },
13494     { "fsub!M", { STi, ST }, 0 },
13495     { "fsubM",  { STi, ST }, 0 },
13496     { "fdiv!M", { STi, ST }, 0 },
13497     { "fdivM",  { STi, ST }, 0 },
13498   },
13499   /* dd */
13500   {
13501     { "ffree",  { STi }, 0 },
13502     { Bad_Opcode },
13503     { "fst",    { STi }, 0 },
13504     { "fstp",   { STi }, 0 },
13505     { "fucom",  { STi }, 0 },
13506     { "fucomp", { STi }, 0 },
13507     { Bad_Opcode },
13508     { Bad_Opcode },
13509   },
13510   /* de */
13511   {
13512     { "faddp",  { STi, ST }, 0 },
13513     { "fmulp",  { STi, ST }, 0 },
13514     { Bad_Opcode },
13515     { FGRPde_3 },
13516     { "fsub!Mp", { STi, ST }, 0 },
13517     { "fsubMp", { STi, ST }, 0 },
13518     { "fdiv!Mp", { STi, ST }, 0 },
13519     { "fdivMp", { STi, ST }, 0 },
13520   },
13521   /* df */
13522   {
13523     { "ffreep", { STi }, 0 },
13524     { Bad_Opcode },
13525     { Bad_Opcode },
13526     { Bad_Opcode },
13527     { FGRPdf_4 },
13528     { "fucomip", { ST, STi }, 0 },
13529     { "fcomip", { ST, STi }, 0 },
13530     { Bad_Opcode },
13531   },
13532 };
13533
13534 static char *fgrps[][8] = {
13535   /* d9_2  0 */
13536   {
13537     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13538   },
13539
13540   /* d9_4  1 */
13541   {
13542     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13543   },
13544
13545   /* d9_5  2 */
13546   {
13547     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13548   },
13549
13550   /* d9_6  3 */
13551   {
13552     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13553   },
13554
13555   /* d9_7  4 */
13556   {
13557     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13558   },
13559
13560   /* da_5  5 */
13561   {
13562     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13563   },
13564
13565   /* db_4  6 */
13566   {
13567     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13568     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13569   },
13570
13571   /* de_3  7 */
13572   {
13573     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13574   },
13575
13576   /* df_4  8 */
13577   {
13578     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13579   },
13580 };
13581
13582 static void
13583 swap_operand (void)
13584 {
13585   mnemonicendp[0] = '.';
13586   mnemonicendp[1] = 's';
13587   mnemonicendp += 2;
13588 }
13589
13590 static void
13591 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13592                int sizeflag ATTRIBUTE_UNUSED)
13593 {
13594   /* Skip mod/rm byte.  */
13595   MODRM_CHECK;
13596   codep++;
13597 }
13598
13599 static void
13600 dofloat (int sizeflag)
13601 {
13602   const struct dis386 *dp;
13603   unsigned char floatop;
13604
13605   floatop = codep[-1];
13606
13607   if (modrm.mod != 3)
13608     {
13609       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13610
13611       putop (float_mem[fp_indx], sizeflag);
13612       obufp = op_out[0];
13613       op_ad = 2;
13614       OP_E (float_mem_mode[fp_indx], sizeflag);
13615       return;
13616     }
13617   /* Skip mod/rm byte.  */
13618   MODRM_CHECK;
13619   codep++;
13620
13621   dp = &float_reg[floatop - 0xd8][modrm.reg];
13622   if (dp->name == NULL)
13623     {
13624       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13625
13626       /* Instruction fnstsw is only one with strange arg.  */
13627       if (floatop == 0xdf && codep[-1] == 0xe0)
13628         strcpy (op_out[0], names16[0]);
13629     }
13630   else
13631     {
13632       putop (dp->name, sizeflag);
13633
13634       obufp = op_out[0];
13635       op_ad = 2;
13636       if (dp->op[0].rtn)
13637         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13638
13639       obufp = op_out[1];
13640       op_ad = 1;
13641       if (dp->op[1].rtn)
13642         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13643     }
13644 }
13645
13646 /* Like oappend (below), but S is a string starting with '%'.
13647    In Intel syntax, the '%' is elided.  */
13648 static void
13649 oappend_maybe_intel (const char *s)
13650 {
13651   oappend (s + intel_syntax);
13652 }
13653
13654 static void
13655 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13656 {
13657   oappend_maybe_intel ("%st");
13658 }
13659
13660 static void
13661 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13662 {
13663   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13664   oappend_maybe_intel (scratchbuf);
13665 }
13666
13667 /* Capital letters in template are macros.  */
13668 static int
13669 putop (const char *in_template, int sizeflag)
13670 {
13671   const char *p;
13672   int alt = 0;
13673   int cond = 1;
13674   unsigned int l = 0, len = 1;
13675   char last[4];
13676
13677 #define SAVE_LAST(c)                    \
13678   if (l < len && l < sizeof (last))     \
13679     last[l++] = c;                      \
13680   else                                  \
13681     abort ();
13682
13683   for (p = in_template; *p; p++)
13684     {
13685       switch (*p)
13686         {
13687         default:
13688           *obufp++ = *p;
13689           break;
13690         case '%':
13691           len++;
13692           break;
13693         case '!':
13694           cond = 0;
13695           break;
13696         case '{':
13697           alt = 0;
13698           if (intel_syntax)
13699             {
13700               while (*++p != '|')
13701                 if (*p == '}' || *p == '\0')
13702                   abort ();
13703             }
13704           /* Fall through.  */
13705         case 'I':
13706           alt = 1;
13707           continue;
13708         case '|':
13709           while (*++p != '}')
13710             {
13711               if (*p == '\0')
13712                 abort ();
13713             }
13714           break;
13715         case '}':
13716           break;
13717         case 'A':
13718           if (intel_syntax)
13719             break;
13720           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13721             *obufp++ = 'b';
13722           break;
13723         case 'B':
13724           if (l == 0 && len == 1)
13725             {
13726 case_B:
13727               if (intel_syntax)
13728                 break;
13729               if (sizeflag & SUFFIX_ALWAYS)
13730                 *obufp++ = 'b';
13731             }
13732           else
13733             {
13734               if (l != 1
13735                   || len != 2
13736                   || last[0] != 'L')
13737                 {
13738                   SAVE_LAST (*p);
13739                   break;
13740                 }
13741
13742               if (address_mode == mode_64bit
13743                   && !(prefixes & PREFIX_ADDR))
13744                 {
13745                   *obufp++ = 'a';
13746                   *obufp++ = 'b';
13747                   *obufp++ = 's';
13748                 }
13749
13750               goto case_B;
13751             }
13752           break;
13753         case 'C':
13754           if (intel_syntax && !alt)
13755             break;
13756           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13757             {
13758               if (sizeflag & DFLAG)
13759                 *obufp++ = intel_syntax ? 'd' : 'l';
13760               else
13761                 *obufp++ = intel_syntax ? 'w' : 's';
13762               used_prefixes |= (prefixes & PREFIX_DATA);
13763             }
13764           break;
13765         case 'D':
13766           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13767             break;
13768           USED_REX (REX_W);
13769           if (modrm.mod == 3)
13770             {
13771               if (rex & REX_W)
13772                 *obufp++ = 'q';
13773               else
13774                 {
13775                   if (sizeflag & DFLAG)
13776                     *obufp++ = intel_syntax ? 'd' : 'l';
13777                   else
13778                     *obufp++ = 'w';
13779                   used_prefixes |= (prefixes & PREFIX_DATA);
13780                 }
13781             }
13782           else
13783             *obufp++ = 'w';
13784           break;
13785         case 'E':               /* For jcxz/jecxz */
13786           if (address_mode == mode_64bit)
13787             {
13788               if (sizeflag & AFLAG)
13789                 *obufp++ = 'r';
13790               else
13791                 *obufp++ = 'e';
13792             }
13793           else
13794             if (sizeflag & AFLAG)
13795               *obufp++ = 'e';
13796           used_prefixes |= (prefixes & PREFIX_ADDR);
13797           break;
13798         case 'F':
13799           if (intel_syntax)
13800             break;
13801           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13802             {
13803               if (sizeflag & AFLAG)
13804                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13805               else
13806                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13807               used_prefixes |= (prefixes & PREFIX_ADDR);
13808             }
13809           break;
13810         case 'G':
13811           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13812             break;
13813           if ((rex & REX_W) || (sizeflag & DFLAG))
13814             *obufp++ = 'l';
13815           else
13816             *obufp++ = 'w';
13817           if (!(rex & REX_W))
13818             used_prefixes |= (prefixes & PREFIX_DATA);
13819           break;
13820         case 'H':
13821           if (intel_syntax)
13822             break;
13823           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13824               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13825             {
13826               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13827               *obufp++ = ',';
13828               *obufp++ = 'p';
13829               if (prefixes & PREFIX_DS)
13830                 *obufp++ = 't';
13831               else
13832                 *obufp++ = 'n';
13833             }
13834           break;
13835         case 'J':
13836           if (intel_syntax)
13837             break;
13838           *obufp++ = 'l';
13839           break;
13840         case 'K':
13841           USED_REX (REX_W);
13842           if (rex & REX_W)
13843             *obufp++ = 'q';
13844           else
13845             *obufp++ = 'd';
13846           break;
13847         case 'Z':
13848           if (l != 0 || len != 1)
13849             {
13850               if (l != 1 || len != 2 || last[0] != 'X')
13851                 {
13852                   SAVE_LAST (*p);
13853                   break;
13854                 }
13855               if (!need_vex || !vex.evex)
13856                 abort ();
13857               if (intel_syntax
13858                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13859                 break;
13860               switch (vex.length)
13861                 {
13862                 case 128:
13863                   *obufp++ = 'x';
13864                   break;
13865                 case 256:
13866                   *obufp++ = 'y';
13867                   break;
13868                 case 512:
13869                   *obufp++ = 'z';
13870                   break;
13871                 default:
13872                   abort ();
13873                 }
13874               break;
13875             }
13876           if (intel_syntax)
13877             break;
13878           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13879             {
13880               *obufp++ = 'q';
13881               break;
13882             }
13883           /* Fall through.  */
13884           goto case_L;
13885         case 'L':
13886           if (l != 0 || len != 1)
13887             {
13888               SAVE_LAST (*p);
13889               break;
13890             }
13891 case_L:
13892           if (intel_syntax)
13893             break;
13894           if (sizeflag & SUFFIX_ALWAYS)
13895             *obufp++ = 'l';
13896           break;
13897         case 'M':
13898           if (intel_mnemonic != cond)
13899             *obufp++ = 'r';
13900           break;
13901         case 'N':
13902           if ((prefixes & PREFIX_FWAIT) == 0)
13903             *obufp++ = 'n';
13904           else
13905             used_prefixes |= PREFIX_FWAIT;
13906           break;
13907         case 'O':
13908           USED_REX (REX_W);
13909           if (rex & REX_W)
13910             *obufp++ = 'o';
13911           else if (intel_syntax && (sizeflag & DFLAG))
13912             *obufp++ = 'q';
13913           else
13914             *obufp++ = 'd';
13915           if (!(rex & REX_W))
13916             used_prefixes |= (prefixes & PREFIX_DATA);
13917           break;
13918         case 'T':
13919           if (!intel_syntax
13920               && address_mode == mode_64bit
13921               && ((sizeflag & DFLAG) || (rex & REX_W)))
13922             {
13923               *obufp++ = 'q';
13924               break;
13925             }
13926           /* Fall through.  */
13927           goto case_P;
13928         case 'P':
13929           if (l == 0 && len == 1)
13930             {
13931 case_P:
13932               if (intel_syntax)
13933                 {
13934                   if ((rex & REX_W) == 0
13935                       && (prefixes & PREFIX_DATA))
13936                     {
13937                       if ((sizeflag & DFLAG) == 0)
13938                         *obufp++ = 'w';
13939                       used_prefixes |= (prefixes & PREFIX_DATA);
13940                     }
13941                   break;
13942                 }
13943               if ((prefixes & PREFIX_DATA)
13944                   || (rex & REX_W)
13945                   || (sizeflag & SUFFIX_ALWAYS))
13946                 {
13947                   USED_REX (REX_W);
13948                   if (rex & REX_W)
13949                     *obufp++ = 'q';
13950                   else
13951                     {
13952                       if (sizeflag & DFLAG)
13953                         *obufp++ = 'l';
13954                       else
13955                         *obufp++ = 'w';
13956                       used_prefixes |= (prefixes & PREFIX_DATA);
13957                     }
13958                 }
13959             }
13960           else
13961             {
13962               if (l != 1 || len != 2 || last[0] != 'L')
13963                 {
13964                   SAVE_LAST (*p);
13965                   break;
13966                 }
13967
13968               if ((prefixes & PREFIX_DATA)
13969                   || (rex & REX_W)
13970                   || (sizeflag & SUFFIX_ALWAYS))
13971                 {
13972                   USED_REX (REX_W);
13973                   if (rex & REX_W)
13974                     *obufp++ = 'q';
13975                   else
13976                     {
13977                       if (sizeflag & DFLAG)
13978                         *obufp++ = intel_syntax ? 'd' : 'l';
13979                       else
13980                         *obufp++ = 'w';
13981                       used_prefixes |= (prefixes & PREFIX_DATA);
13982                     }
13983                 }
13984             }
13985           break;
13986         case 'U':
13987           if (intel_syntax)
13988             break;
13989           if (address_mode == mode_64bit
13990               && ((sizeflag & DFLAG) || (rex & REX_W)))
13991             {
13992               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13993                 *obufp++ = 'q';
13994               break;
13995             }
13996           /* Fall through.  */
13997           goto case_Q;
13998         case 'Q':
13999           if (l == 0 && len == 1)
14000             {
14001 case_Q:
14002               if (intel_syntax && !alt)
14003                 break;
14004               USED_REX (REX_W);
14005               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14006                 {
14007                   if (rex & REX_W)
14008                     *obufp++ = 'q';
14009                   else
14010                     {
14011                       if (sizeflag & DFLAG)
14012                         *obufp++ = intel_syntax ? 'd' : 'l';
14013                       else
14014                         *obufp++ = 'w';
14015                       used_prefixes |= (prefixes & PREFIX_DATA);
14016                     }
14017                 }
14018             }
14019           else
14020             {
14021               if (l != 1 || len != 2 || last[0] != 'L')
14022                 {
14023                   SAVE_LAST (*p);
14024                   break;
14025                 }
14026               if (intel_syntax
14027                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14028                 break;
14029               if ((rex & REX_W))
14030                 {
14031                   USED_REX (REX_W);
14032                   *obufp++ = 'q';
14033                 }
14034               else
14035                 *obufp++ = 'l';
14036             }
14037           break;
14038         case 'R':
14039           USED_REX (REX_W);
14040           if (rex & REX_W)
14041             *obufp++ = 'q';
14042           else if (sizeflag & DFLAG)
14043             {
14044               if (intel_syntax)
14045                   *obufp++ = 'd';
14046               else
14047                   *obufp++ = 'l';
14048             }
14049           else
14050             *obufp++ = 'w';
14051           if (intel_syntax && !p[1]
14052               && ((rex & REX_W) || (sizeflag & DFLAG)))
14053             *obufp++ = 'e';
14054           if (!(rex & REX_W))
14055             used_prefixes |= (prefixes & PREFIX_DATA);
14056           break;
14057         case 'V':
14058           if (l == 0 && len == 1)
14059             {
14060               if (intel_syntax)
14061                 break;
14062               if (address_mode == mode_64bit
14063                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14064                 {
14065                   if (sizeflag & SUFFIX_ALWAYS)
14066                     *obufp++ = 'q';
14067                   break;
14068                 }
14069             }
14070           else
14071             {
14072               if (l != 1
14073                   || len != 2
14074                   || last[0] != 'L')
14075                 {
14076                   SAVE_LAST (*p);
14077                   break;
14078                 }
14079
14080               if (rex & REX_W)
14081                 {
14082                   *obufp++ = 'a';
14083                   *obufp++ = 'b';
14084                   *obufp++ = 's';
14085                 }
14086             }
14087           /* Fall through.  */
14088           goto case_S;
14089         case 'S':
14090           if (l == 0 && len == 1)
14091             {
14092 case_S:
14093               if (intel_syntax)
14094                 break;
14095               if (sizeflag & SUFFIX_ALWAYS)
14096                 {
14097                   if (rex & REX_W)
14098                     *obufp++ = 'q';
14099                   else
14100                     {
14101                       if (sizeflag & DFLAG)
14102                         *obufp++ = 'l';
14103                       else
14104                         *obufp++ = 'w';
14105                       used_prefixes |= (prefixes & PREFIX_DATA);
14106                     }
14107                 }
14108             }
14109           else
14110             {
14111               if (l != 1
14112                   || len != 2
14113                   || last[0] != 'L')
14114                 {
14115                   SAVE_LAST (*p);
14116                   break;
14117                 }
14118
14119               if (address_mode == mode_64bit
14120                   && !(prefixes & PREFIX_ADDR))
14121                 {
14122                   *obufp++ = 'a';
14123                   *obufp++ = 'b';
14124                   *obufp++ = 's';
14125                 }
14126
14127               goto case_S;
14128             }
14129           break;
14130         case 'X':
14131           if (l != 0 || len != 1)
14132             {
14133               SAVE_LAST (*p);
14134               break;
14135             }
14136           if (need_vex && vex.prefix)
14137             {
14138               if (vex.prefix == DATA_PREFIX_OPCODE)
14139                 *obufp++ = 'd';
14140               else
14141                 *obufp++ = 's';
14142             }
14143           else
14144             {
14145               if (prefixes & PREFIX_DATA)
14146                 *obufp++ = 'd';
14147               else
14148                 *obufp++ = 's';
14149               used_prefixes |= (prefixes & PREFIX_DATA);
14150             }
14151           break;
14152         case 'Y':
14153           if (l == 0 && len == 1)
14154             {
14155               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14156                 break;
14157               if (rex & REX_W)
14158                 {
14159                   USED_REX (REX_W);
14160                   *obufp++ = 'q';
14161                 }
14162               break;
14163             }
14164           else
14165             {
14166               if (l != 1 || len != 2 || last[0] != 'X')
14167                 {
14168                   SAVE_LAST (*p);
14169                   break;
14170                 }
14171               if (!need_vex)
14172                 abort ();
14173               if (intel_syntax
14174                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14175                 break;
14176               switch (vex.length)
14177                 {
14178                 case 128:
14179                   *obufp++ = 'x';
14180                   break;
14181                 case 256:
14182                   *obufp++ = 'y';
14183                   break;
14184                 case 512:
14185                   if (!vex.evex)
14186                 default:
14187                     abort ();
14188                 }
14189             }
14190           break;
14191         case 'W':
14192           if (l == 0 && len == 1)
14193             {
14194               /* operand size flag for cwtl, cbtw */
14195               USED_REX (REX_W);
14196               if (rex & REX_W)
14197                 {
14198                   if (intel_syntax)
14199                     *obufp++ = 'd';
14200                   else
14201                     *obufp++ = 'l';
14202                 }
14203               else if (sizeflag & DFLAG)
14204                 *obufp++ = 'w';
14205               else
14206                 *obufp++ = 'b';
14207               if (!(rex & REX_W))
14208                 used_prefixes |= (prefixes & PREFIX_DATA);
14209             }
14210           else
14211             {
14212               if (l != 1
14213                   || len != 2
14214                   || (last[0] != 'X'
14215                       && last[0] != 'L'))
14216                 {
14217                   SAVE_LAST (*p);
14218                   break;
14219                 }
14220               if (!need_vex)
14221                 abort ();
14222               if (last[0] == 'X')
14223                 *obufp++ = vex.w ? 'd': 's';
14224               else
14225                 *obufp++ = vex.w ? 'q': 'd';
14226             }
14227           break;
14228         case '^':
14229           if (intel_syntax)
14230             break;
14231           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14232             {
14233               if (sizeflag & DFLAG)
14234                 *obufp++ = 'l';
14235               else
14236                 *obufp++ = 'w';
14237               used_prefixes |= (prefixes & PREFIX_DATA);
14238             }
14239           break;
14240         case '@':
14241           if (intel_syntax)
14242             break;
14243           if (address_mode == mode_64bit
14244               && (isa64 == intel64
14245                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14246               *obufp++ = 'q';
14247           else if ((prefixes & PREFIX_DATA))
14248             {
14249               if (!(sizeflag & DFLAG))
14250                 *obufp++ = 'w';
14251               used_prefixes |= (prefixes & PREFIX_DATA);
14252             }
14253           break;
14254         }
14255       alt = 0;
14256     }
14257   *obufp = 0;
14258   mnemonicendp = obufp;
14259   return 0;
14260 }
14261
14262 static void
14263 oappend (const char *s)
14264 {
14265   obufp = stpcpy (obufp, s);
14266 }
14267
14268 static void
14269 append_seg (void)
14270 {
14271   /* Only print the active segment register.  */
14272   if (!active_seg_prefix)
14273     return;
14274
14275   used_prefixes |= active_seg_prefix;
14276   switch (active_seg_prefix)
14277     {
14278     case PREFIX_CS:
14279       oappend_maybe_intel ("%cs:");
14280       break;
14281     case PREFIX_DS:
14282       oappend_maybe_intel ("%ds:");
14283       break;
14284     case PREFIX_SS:
14285       oappend_maybe_intel ("%ss:");
14286       break;
14287     case PREFIX_ES:
14288       oappend_maybe_intel ("%es:");
14289       break;
14290     case PREFIX_FS:
14291       oappend_maybe_intel ("%fs:");
14292       break;
14293     case PREFIX_GS:
14294       oappend_maybe_intel ("%gs:");
14295       break;
14296     default:
14297       break;
14298     }
14299 }
14300
14301 static void
14302 OP_indirE (int bytemode, int sizeflag)
14303 {
14304   if (!intel_syntax)
14305     oappend ("*");
14306   OP_E (bytemode, sizeflag);
14307 }
14308
14309 static void
14310 print_operand_value (char *buf, int hex, bfd_vma disp)
14311 {
14312   if (address_mode == mode_64bit)
14313     {
14314       if (hex)
14315         {
14316           char tmp[30];
14317           int i;
14318           buf[0] = '0';
14319           buf[1] = 'x';
14320           sprintf_vma (tmp, disp);
14321           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14322           strcpy (buf + 2, tmp + i);
14323         }
14324       else
14325         {
14326           bfd_signed_vma v = disp;
14327           char tmp[30];
14328           int i;
14329           if (v < 0)
14330             {
14331               *(buf++) = '-';
14332               v = -disp;
14333               /* Check for possible overflow on 0x8000000000000000.  */
14334               if (v < 0)
14335                 {
14336                   strcpy (buf, "9223372036854775808");
14337                   return;
14338                 }
14339             }
14340           if (!v)
14341             {
14342               strcpy (buf, "0");
14343               return;
14344             }
14345
14346           i = 0;
14347           tmp[29] = 0;
14348           while (v)
14349             {
14350               tmp[28 - i] = (v % 10) + '0';
14351               v /= 10;
14352               i++;
14353             }
14354           strcpy (buf, tmp + 29 - i);
14355         }
14356     }
14357   else
14358     {
14359       if (hex)
14360         sprintf (buf, "0x%x", (unsigned int) disp);
14361       else
14362         sprintf (buf, "%d", (int) disp);
14363     }
14364 }
14365
14366 /* Put DISP in BUF as signed hex number.  */
14367
14368 static void
14369 print_displacement (char *buf, bfd_vma disp)
14370 {
14371   bfd_signed_vma val = disp;
14372   char tmp[30];
14373   int i, j = 0;
14374
14375   if (val < 0)
14376     {
14377       buf[j++] = '-';
14378       val = -disp;
14379
14380       /* Check for possible overflow.  */
14381       if (val < 0)
14382         {
14383           switch (address_mode)
14384             {
14385             case mode_64bit:
14386               strcpy (buf + j, "0x8000000000000000");
14387               break;
14388             case mode_32bit:
14389               strcpy (buf + j, "0x80000000");
14390               break;
14391             case mode_16bit:
14392               strcpy (buf + j, "0x8000");
14393               break;
14394             }
14395           return;
14396         }
14397     }
14398
14399   buf[j++] = '0';
14400   buf[j++] = 'x';
14401
14402   sprintf_vma (tmp, (bfd_vma) val);
14403   for (i = 0; tmp[i] == '0'; i++)
14404     continue;
14405   if (tmp[i] == '\0')
14406     i--;
14407   strcpy (buf + j, tmp + i);
14408 }
14409
14410 static void
14411 intel_operand_size (int bytemode, int sizeflag)
14412 {
14413   if (vex.evex
14414       && vex.b
14415       && (bytemode == x_mode
14416           || bytemode == evex_half_bcst_xmmq_mode))
14417     {
14418       if (vex.w)
14419         oappend ("QWORD PTR ");
14420       else
14421         oappend ("DWORD PTR ");
14422       return;
14423     }
14424   switch (bytemode)
14425     {
14426     case b_mode:
14427     case b_swap_mode:
14428     case dqb_mode:
14429     case db_mode:
14430       oappend ("BYTE PTR ");
14431       break;
14432     case w_mode:
14433     case dw_mode:
14434     case dqw_mode:
14435     case dqw_swap_mode:
14436       oappend ("WORD PTR ");
14437       break;
14438     case stack_v_mode:
14439       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14440         {
14441           oappend ("QWORD PTR ");
14442           break;
14443         }
14444       /* FALLTHRU */
14445     case v_mode:
14446     case v_swap_mode:
14447     case dq_mode:
14448       USED_REX (REX_W);
14449       if (rex & REX_W)
14450         oappend ("QWORD PTR ");
14451       else
14452         {
14453           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14454             oappend ("DWORD PTR ");
14455           else
14456             oappend ("WORD PTR ");
14457           used_prefixes |= (prefixes & PREFIX_DATA);
14458         }
14459       break;
14460     case z_mode:
14461       if ((rex & REX_W) || (sizeflag & DFLAG))
14462         *obufp++ = 'D';
14463       oappend ("WORD PTR ");
14464       if (!(rex & REX_W))
14465         used_prefixes |= (prefixes & PREFIX_DATA);
14466       break;
14467     case a_mode:
14468       if (sizeflag & DFLAG)
14469         oappend ("QWORD PTR ");
14470       else
14471         oappend ("DWORD PTR ");
14472       used_prefixes |= (prefixes & PREFIX_DATA);
14473       break;
14474     case d_mode:
14475     case d_scalar_mode:
14476     case d_scalar_swap_mode:
14477     case d_swap_mode:
14478     case dqd_mode:
14479       oappend ("DWORD PTR ");
14480       break;
14481     case q_mode:
14482     case q_scalar_mode:
14483     case q_scalar_swap_mode:
14484     case q_swap_mode:
14485       oappend ("QWORD PTR ");
14486       break;
14487     case m_mode:
14488       if (address_mode == mode_64bit)
14489         oappend ("QWORD PTR ");
14490       else
14491         oappend ("DWORD PTR ");
14492       break;
14493     case f_mode:
14494       if (sizeflag & DFLAG)
14495         oappend ("FWORD PTR ");
14496       else
14497         oappend ("DWORD PTR ");
14498       used_prefixes |= (prefixes & PREFIX_DATA);
14499       break;
14500     case t_mode:
14501       oappend ("TBYTE PTR ");
14502       break;
14503     case x_mode:
14504     case x_swap_mode:
14505     case evex_x_gscat_mode:
14506     case evex_x_nobcst_mode:
14507       if (need_vex)
14508         {
14509           switch (vex.length)
14510             {
14511             case 128:
14512               oappend ("XMMWORD PTR ");
14513               break;
14514             case 256:
14515               oappend ("YMMWORD PTR ");
14516               break;
14517             case 512:
14518               oappend ("ZMMWORD PTR ");
14519               break;
14520             default:
14521               abort ();
14522             }
14523         }
14524       else
14525         oappend ("XMMWORD PTR ");
14526       break;
14527     case xmm_mode:
14528       oappend ("XMMWORD PTR ");
14529       break;
14530     case ymm_mode:
14531       oappend ("YMMWORD PTR ");
14532       break;
14533     case xmmq_mode:
14534     case evex_half_bcst_xmmq_mode:
14535       if (!need_vex)
14536         abort ();
14537
14538       switch (vex.length)
14539         {
14540         case 128:
14541           oappend ("QWORD PTR ");
14542           break;
14543         case 256:
14544           oappend ("XMMWORD PTR ");
14545           break;
14546         case 512:
14547           oappend ("YMMWORD PTR ");
14548           break;
14549         default:
14550           abort ();
14551         }
14552       break;
14553     case xmm_mb_mode:
14554       if (!need_vex)
14555         abort ();
14556
14557       switch (vex.length)
14558         {
14559         case 128:
14560         case 256:
14561         case 512:
14562           oappend ("BYTE PTR ");
14563           break;
14564         default:
14565           abort ();
14566         }
14567       break;
14568     case xmm_mw_mode:
14569       if (!need_vex)
14570         abort ();
14571
14572       switch (vex.length)
14573         {
14574         case 128:
14575         case 256:
14576         case 512:
14577           oappend ("WORD PTR ");
14578           break;
14579         default:
14580           abort ();
14581         }
14582       break;
14583     case xmm_md_mode:
14584       if (!need_vex)
14585         abort ();
14586
14587       switch (vex.length)
14588         {
14589         case 128:
14590         case 256:
14591         case 512:
14592           oappend ("DWORD PTR ");
14593           break;
14594         default:
14595           abort ();
14596         }
14597       break;
14598     case xmm_mq_mode:
14599       if (!need_vex)
14600         abort ();
14601
14602       switch (vex.length)
14603         {
14604         case 128:
14605         case 256:
14606         case 512:
14607           oappend ("QWORD PTR ");
14608           break;
14609         default:
14610           abort ();
14611         }
14612       break;
14613     case xmmdw_mode:
14614       if (!need_vex)
14615         abort ();
14616
14617       switch (vex.length)
14618         {
14619         case 128:
14620           oappend ("WORD PTR ");
14621           break;
14622         case 256:
14623           oappend ("DWORD PTR ");
14624           break;
14625         case 512:
14626           oappend ("QWORD PTR ");
14627           break;
14628         default:
14629           abort ();
14630         }
14631       break;
14632     case xmmqd_mode:
14633       if (!need_vex)
14634         abort ();
14635
14636       switch (vex.length)
14637         {
14638         case 128:
14639           oappend ("DWORD PTR ");
14640           break;
14641         case 256:
14642           oappend ("QWORD PTR ");
14643           break;
14644         case 512:
14645           oappend ("XMMWORD PTR ");
14646           break;
14647         default:
14648           abort ();
14649         }
14650       break;
14651     case ymmq_mode:
14652       if (!need_vex)
14653         abort ();
14654
14655       switch (vex.length)
14656         {
14657         case 128:
14658           oappend ("QWORD PTR ");
14659           break;
14660         case 256:
14661           oappend ("YMMWORD PTR ");
14662           break;
14663         case 512:
14664           oappend ("ZMMWORD PTR ");
14665           break;
14666         default:
14667           abort ();
14668         }
14669       break;
14670     case ymmxmm_mode:
14671       if (!need_vex)
14672         abort ();
14673
14674       switch (vex.length)
14675         {
14676         case 128:
14677         case 256:
14678           oappend ("XMMWORD PTR ");
14679           break;
14680         default:
14681           abort ();
14682         }
14683       break;
14684     case o_mode:
14685       oappend ("OWORD PTR ");
14686       break;
14687     case xmm_mdq_mode:
14688     case vex_w_dq_mode:
14689     case vex_scalar_w_dq_mode:
14690       if (!need_vex)
14691         abort ();
14692
14693       if (vex.w)
14694         oappend ("QWORD PTR ");
14695       else
14696         oappend ("DWORD PTR ");
14697       break;
14698     case vex_vsib_d_w_dq_mode:
14699     case vex_vsib_q_w_dq_mode:
14700       if (!need_vex)
14701         abort ();
14702
14703       if (!vex.evex)
14704         {
14705           if (vex.w)
14706             oappend ("QWORD PTR ");
14707           else
14708             oappend ("DWORD PTR ");
14709         }
14710       else
14711         {
14712           switch (vex.length)
14713             {
14714             case 128:
14715               oappend ("XMMWORD PTR ");
14716               break;
14717             case 256:
14718               oappend ("YMMWORD PTR ");
14719               break;
14720             case 512:
14721               oappend ("ZMMWORD PTR ");
14722               break;
14723             default:
14724               abort ();
14725             }
14726         }
14727       break;
14728     case vex_vsib_q_w_d_mode:
14729     case vex_vsib_d_w_d_mode:
14730       if (!need_vex || !vex.evex)
14731         abort ();
14732
14733       switch (vex.length)
14734         {
14735         case 128:
14736           oappend ("QWORD PTR ");
14737           break;
14738         case 256:
14739           oappend ("XMMWORD PTR ");
14740           break;
14741         case 512:
14742           oappend ("YMMWORD PTR ");
14743           break;
14744         default:
14745           abort ();
14746         }
14747
14748       break;
14749     case mask_bd_mode:
14750       if (!need_vex || vex.length != 128)
14751         abort ();
14752       if (vex.w)
14753         oappend ("DWORD PTR ");
14754       else
14755         oappend ("BYTE PTR ");
14756       break;
14757     case mask_mode:
14758       if (!need_vex)
14759         abort ();
14760       if (vex.w)
14761         oappend ("QWORD PTR ");
14762       else
14763         oappend ("WORD PTR ");
14764       break;
14765     case v_bnd_mode:
14766     default:
14767       break;
14768     }
14769 }
14770
14771 static void
14772 OP_E_register (int bytemode, int sizeflag)
14773 {
14774   int reg = modrm.rm;
14775   const char **names;
14776
14777   USED_REX (REX_B);
14778   if ((rex & REX_B))
14779     reg += 8;
14780
14781   if ((sizeflag & SUFFIX_ALWAYS)
14782       && (bytemode == b_swap_mode
14783           || bytemode == v_swap_mode
14784           || bytemode == dqw_swap_mode))
14785     swap_operand ();
14786
14787   switch (bytemode)
14788     {
14789     case b_mode:
14790     case b_swap_mode:
14791       USED_REX (0);
14792       if (rex)
14793         names = names8rex;
14794       else
14795         names = names8;
14796       break;
14797     case w_mode:
14798       names = names16;
14799       break;
14800     case d_mode:
14801     case dw_mode:
14802     case db_mode:
14803       names = names32;
14804       break;
14805     case q_mode:
14806       names = names64;
14807       break;
14808     case m_mode:
14809     case v_bnd_mode:
14810       names = address_mode == mode_64bit ? names64 : names32;
14811       break;
14812     case bnd_mode:
14813       names = names_bnd;
14814       break;
14815     case stack_v_mode:
14816       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14817         {
14818           names = names64;
14819           break;
14820         }
14821       bytemode = v_mode;
14822       /* FALLTHRU */
14823     case v_mode:
14824     case v_swap_mode:
14825     case dq_mode:
14826     case dqb_mode:
14827     case dqd_mode:
14828     case dqw_mode:
14829     case dqw_swap_mode:
14830       USED_REX (REX_W);
14831       if (rex & REX_W)
14832         names = names64;
14833       else
14834         {
14835           if ((sizeflag & DFLAG)
14836               || (bytemode != v_mode
14837                   && bytemode != v_swap_mode))
14838             names = names32;
14839           else
14840             names = names16;
14841           used_prefixes |= (prefixes & PREFIX_DATA);
14842         }
14843       break;
14844     case mask_bd_mode:
14845     case mask_mode:
14846       names = names_mask;
14847       break;
14848     case 0:
14849       return;
14850     default:
14851       oappend (INTERNAL_DISASSEMBLER_ERROR);
14852       return;
14853     }
14854   oappend (names[reg]);
14855 }
14856
14857 static void
14858 OP_E_memory (int bytemode, int sizeflag)
14859 {
14860   bfd_vma disp = 0;
14861   int add = (rex & REX_B) ? 8 : 0;
14862   int riprel = 0;
14863   int shift;
14864
14865   if (vex.evex)
14866     {
14867       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14868       if (vex.b
14869           && bytemode != x_mode
14870           && bytemode != xmmq_mode
14871           && bytemode != evex_half_bcst_xmmq_mode)
14872         {
14873           BadOp ();
14874           return;
14875         }
14876       switch (bytemode)
14877         {
14878         case dqw_mode:
14879         case dw_mode:
14880         case dqw_swap_mode:
14881           shift = 1;
14882           break;
14883         case dqb_mode:
14884         case db_mode:
14885           shift = 0;
14886           break;
14887         case vex_vsib_d_w_dq_mode:
14888         case vex_vsib_d_w_d_mode:
14889         case vex_vsib_q_w_dq_mode:
14890         case vex_vsib_q_w_d_mode:
14891         case evex_x_gscat_mode:
14892         case xmm_mdq_mode:
14893           shift = vex.w ? 3 : 2;
14894           break;
14895         case x_mode:
14896         case evex_half_bcst_xmmq_mode:
14897         case xmmq_mode:
14898           if (vex.b)
14899             {
14900               shift = vex.w ? 3 : 2;
14901               break;
14902             }
14903           /* Fall through if vex.b == 0.  */
14904         case xmmqd_mode:
14905         case xmmdw_mode:
14906         case ymmq_mode:
14907         case evex_x_nobcst_mode:
14908         case x_swap_mode:
14909           switch (vex.length)
14910             {
14911             case 128:
14912               shift = 4;
14913               break;
14914             case 256:
14915               shift = 5;
14916               break;
14917             case 512:
14918               shift = 6;
14919               break;
14920             default:
14921               abort ();
14922             }
14923           break;
14924         case ymm_mode:
14925           shift = 5;
14926           break;
14927         case xmm_mode:
14928           shift = 4;
14929           break;
14930         case xmm_mq_mode:
14931         case q_mode:
14932         case q_scalar_mode:
14933         case q_swap_mode:
14934         case q_scalar_swap_mode:
14935           shift = 3;
14936           break;
14937         case dqd_mode:
14938         case xmm_md_mode:
14939         case d_mode:
14940         case d_scalar_mode:
14941         case d_swap_mode:
14942         case d_scalar_swap_mode:
14943           shift = 2;
14944           break;
14945         case xmm_mw_mode:
14946           shift = 1;
14947           break;
14948         case xmm_mb_mode:
14949           shift = 0;
14950           break;
14951         default:
14952           abort ();
14953         }
14954       /* Make necessary corrections to shift for modes that need it.
14955          For these modes we currently have shift 4, 5 or 6 depending on
14956          vex.length (it corresponds to xmmword, ymmword or zmmword
14957          operand).  We might want to make it 3, 4 or 5 (e.g. for
14958          xmmq_mode).  In case of broadcast enabled the corrections
14959          aren't needed, as element size is always 32 or 64 bits.  */
14960       if (!vex.b
14961           && (bytemode == xmmq_mode
14962               || bytemode == evex_half_bcst_xmmq_mode))
14963         shift -= 1;
14964       else if (bytemode == xmmqd_mode)
14965         shift -= 2;
14966       else if (bytemode == xmmdw_mode)
14967         shift -= 3;
14968       else if (bytemode == ymmq_mode && vex.length == 128)
14969         shift -= 1;
14970     }
14971   else
14972     shift = 0;
14973
14974   USED_REX (REX_B);
14975   if (intel_syntax)
14976     intel_operand_size (bytemode, sizeflag);
14977   append_seg ();
14978
14979   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14980     {
14981       /* 32/64 bit address mode */
14982       int havedisp;
14983       int havesib;
14984       int havebase;
14985       int haveindex;
14986       int needindex;
14987       int base, rbase;
14988       int vindex = 0;
14989       int scale = 0;
14990       int addr32flag = !((sizeflag & AFLAG)
14991                          || bytemode == v_bnd_mode
14992                          || bytemode == bnd_mode);
14993       const char **indexes64 = names64;
14994       const char **indexes32 = names32;
14995
14996       havesib = 0;
14997       havebase = 1;
14998       haveindex = 0;
14999       base = modrm.rm;
15000
15001       if (base == 4)
15002         {
15003           havesib = 1;
15004           vindex = sib.index;
15005           USED_REX (REX_X);
15006           if (rex & REX_X)
15007             vindex += 8;
15008           switch (bytemode)
15009             {
15010             case vex_vsib_d_w_dq_mode:
15011             case vex_vsib_d_w_d_mode:
15012             case vex_vsib_q_w_dq_mode:
15013             case vex_vsib_q_w_d_mode:
15014               if (!need_vex)
15015                 abort ();
15016               if (vex.evex)
15017                 {
15018                   if (!vex.v)
15019                     vindex += 16;
15020                 }
15021
15022               haveindex = 1;
15023               switch (vex.length)
15024                 {
15025                 case 128:
15026                   indexes64 = indexes32 = names_xmm;
15027                   break;
15028                 case 256:
15029                   if (!vex.w
15030                       || bytemode == vex_vsib_q_w_dq_mode
15031                       || bytemode == vex_vsib_q_w_d_mode)
15032                     indexes64 = indexes32 = names_ymm;
15033                   else
15034                     indexes64 = indexes32 = names_xmm;
15035                   break;
15036                 case 512:
15037                   if (!vex.w
15038                       || bytemode == vex_vsib_q_w_dq_mode
15039                       || bytemode == vex_vsib_q_w_d_mode)
15040                     indexes64 = indexes32 = names_zmm;
15041                   else
15042                     indexes64 = indexes32 = names_ymm;
15043                   break;
15044                 default:
15045                   abort ();
15046                 }
15047               break;
15048             default:
15049               haveindex = vindex != 4;
15050               break;
15051             }
15052           scale = sib.scale;
15053           base = sib.base;
15054           codep++;
15055         }
15056       rbase = base + add;
15057
15058       switch (modrm.mod)
15059         {
15060         case 0:
15061           if (base == 5)
15062             {
15063               havebase = 0;
15064               if (address_mode == mode_64bit && !havesib)
15065                 riprel = 1;
15066               disp = get32s ();
15067             }
15068           break;
15069         case 1:
15070           FETCH_DATA (the_info, codep + 1);
15071           disp = *codep++;
15072           if ((disp & 0x80) != 0)
15073             disp -= 0x100;
15074           if (vex.evex && shift > 0)
15075             disp <<= shift;
15076           break;
15077         case 2:
15078           disp = get32s ();
15079           break;
15080         }
15081
15082       /* In 32bit mode, we need index register to tell [offset] from
15083          [eiz*1 + offset].  */
15084       needindex = (havesib
15085                    && !havebase
15086                    && !haveindex
15087                    && address_mode == mode_32bit);
15088       havedisp = (havebase
15089                   || needindex
15090                   || (havesib && (haveindex || scale != 0)));
15091
15092       if (!intel_syntax)
15093         if (modrm.mod != 0 || base == 5)
15094           {
15095             if (havedisp || riprel)
15096               print_displacement (scratchbuf, disp);
15097             else
15098               print_operand_value (scratchbuf, 1, disp);
15099             oappend (scratchbuf);
15100             if (riprel)
15101               {
15102                 set_op (disp, 1);
15103                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15104               }
15105           }
15106
15107       if ((havebase || haveindex || riprel)
15108           && (bytemode != v_bnd_mode)
15109           && (bytemode != bnd_mode))
15110         used_prefixes |= PREFIX_ADDR;
15111
15112       if (havedisp || (intel_syntax && riprel))
15113         {
15114           *obufp++ = open_char;
15115           if (intel_syntax && riprel)
15116             {
15117               set_op (disp, 1);
15118               oappend (sizeflag & AFLAG ? "rip" : "eip");
15119             }
15120           *obufp = '\0';
15121           if (havebase)
15122             oappend (address_mode == mode_64bit && !addr32flag
15123                      ? names64[rbase] : names32[rbase]);
15124           if (havesib)
15125             {
15126               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15127                  print index to tell base + index from base.  */
15128               if (scale != 0
15129                   || needindex
15130                   || haveindex
15131                   || (havebase && base != ESP_REG_NUM))
15132                 {
15133                   if (!intel_syntax || havebase)
15134                     {
15135                       *obufp++ = separator_char;
15136                       *obufp = '\0';
15137                     }
15138                   if (haveindex)
15139                     oappend (address_mode == mode_64bit && !addr32flag
15140                              ? indexes64[vindex] : indexes32[vindex]);
15141                   else
15142                     oappend (address_mode == mode_64bit && !addr32flag
15143                              ? index64 : index32);
15144
15145                   *obufp++ = scale_char;
15146                   *obufp = '\0';
15147                   sprintf (scratchbuf, "%d", 1 << scale);
15148                   oappend (scratchbuf);
15149                 }
15150             }
15151           if (intel_syntax
15152               && (disp || modrm.mod != 0 || base == 5))
15153             {
15154               if (!havedisp || (bfd_signed_vma) disp >= 0)
15155                 {
15156                   *obufp++ = '+';
15157                   *obufp = '\0';
15158                 }
15159               else if (modrm.mod != 1 && disp != -disp)
15160                 {
15161                   *obufp++ = '-';
15162                   *obufp = '\0';
15163                   disp = - (bfd_signed_vma) disp;
15164                 }
15165
15166               if (havedisp)
15167                 print_displacement (scratchbuf, disp);
15168               else
15169                 print_operand_value (scratchbuf, 1, disp);
15170               oappend (scratchbuf);
15171             }
15172
15173           *obufp++ = close_char;
15174           *obufp = '\0';
15175         }
15176       else if (intel_syntax)
15177         {
15178           if (modrm.mod != 0 || base == 5)
15179             {
15180               if (!active_seg_prefix)
15181                 {
15182                   oappend (names_seg[ds_reg - es_reg]);
15183                   oappend (":");
15184                 }
15185               print_operand_value (scratchbuf, 1, disp);
15186               oappend (scratchbuf);
15187             }
15188         }
15189     }
15190   else
15191     {
15192       /* 16 bit address mode */
15193       used_prefixes |= prefixes & PREFIX_ADDR;
15194       switch (modrm.mod)
15195         {
15196         case 0:
15197           if (modrm.rm == 6)
15198             {
15199               disp = get16 ();
15200               if ((disp & 0x8000) != 0)
15201                 disp -= 0x10000;
15202             }
15203           break;
15204         case 1:
15205           FETCH_DATA (the_info, codep + 1);
15206           disp = *codep++;
15207           if ((disp & 0x80) != 0)
15208             disp -= 0x100;
15209           break;
15210         case 2:
15211           disp = get16 ();
15212           if ((disp & 0x8000) != 0)
15213             disp -= 0x10000;
15214           break;
15215         }
15216
15217       if (!intel_syntax)
15218         if (modrm.mod != 0 || modrm.rm == 6)
15219           {
15220             print_displacement (scratchbuf, disp);
15221             oappend (scratchbuf);
15222           }
15223
15224       if (modrm.mod != 0 || modrm.rm != 6)
15225         {
15226           *obufp++ = open_char;
15227           *obufp = '\0';
15228           oappend (index16[modrm.rm]);
15229           if (intel_syntax
15230               && (disp || modrm.mod != 0 || modrm.rm == 6))
15231             {
15232               if ((bfd_signed_vma) disp >= 0)
15233                 {
15234                   *obufp++ = '+';
15235                   *obufp = '\0';
15236                 }
15237               else if (modrm.mod != 1)
15238                 {
15239                   *obufp++ = '-';
15240                   *obufp = '\0';
15241                   disp = - (bfd_signed_vma) disp;
15242                 }
15243
15244               print_displacement (scratchbuf, disp);
15245               oappend (scratchbuf);
15246             }
15247
15248           *obufp++ = close_char;
15249           *obufp = '\0';
15250         }
15251       else if (intel_syntax)
15252         {
15253           if (!active_seg_prefix)
15254             {
15255               oappend (names_seg[ds_reg - es_reg]);
15256               oappend (":");
15257             }
15258           print_operand_value (scratchbuf, 1, disp & 0xffff);
15259           oappend (scratchbuf);
15260         }
15261     }
15262   if (vex.evex && vex.b
15263       && (bytemode == x_mode
15264           || bytemode == xmmq_mode
15265           || bytemode == evex_half_bcst_xmmq_mode))
15266     {
15267       if (vex.w
15268           || bytemode == xmmq_mode
15269           || bytemode == evex_half_bcst_xmmq_mode)
15270         {
15271           switch (vex.length)
15272             {
15273             case 128:
15274               oappend ("{1to2}");
15275               break;
15276             case 256:
15277               oappend ("{1to4}");
15278               break;
15279             case 512:
15280               oappend ("{1to8}");
15281               break;
15282             default:
15283               abort ();
15284             }
15285         }
15286       else
15287         {
15288           switch (vex.length)
15289             {
15290             case 128:
15291               oappend ("{1to4}");
15292               break;
15293             case 256:
15294               oappend ("{1to8}");
15295               break;
15296             case 512:
15297               oappend ("{1to16}");
15298               break;
15299             default:
15300               abort ();
15301             }
15302         }
15303     }
15304 }
15305
15306 static void
15307 OP_E (int bytemode, int sizeflag)
15308 {
15309   /* Skip mod/rm byte.  */
15310   MODRM_CHECK;
15311   codep++;
15312
15313   if (modrm.mod == 3)
15314     OP_E_register (bytemode, sizeflag);
15315   else
15316     OP_E_memory (bytemode, sizeflag);
15317 }
15318
15319 static void
15320 OP_G (int bytemode, int sizeflag)
15321 {
15322   int add = 0;
15323   USED_REX (REX_R);
15324   if (rex & REX_R)
15325     add += 8;
15326   switch (bytemode)
15327     {
15328     case b_mode:
15329       USED_REX (0);
15330       if (rex)
15331         oappend (names8rex[modrm.reg + add]);
15332       else
15333         oappend (names8[modrm.reg + add]);
15334       break;
15335     case w_mode:
15336       oappend (names16[modrm.reg + add]);
15337       break;
15338     case d_mode:
15339     case db_mode:
15340     case dw_mode:
15341       oappend (names32[modrm.reg + add]);
15342       break;
15343     case q_mode:
15344       oappend (names64[modrm.reg + add]);
15345       break;
15346     case bnd_mode:
15347       oappend (names_bnd[modrm.reg]);
15348       break;
15349     case v_mode:
15350     case dq_mode:
15351     case dqb_mode:
15352     case dqd_mode:
15353     case dqw_mode:
15354     case dqw_swap_mode:
15355       USED_REX (REX_W);
15356       if (rex & REX_W)
15357         oappend (names64[modrm.reg + add]);
15358       else
15359         {
15360           if ((sizeflag & DFLAG) || bytemode != v_mode)
15361             oappend (names32[modrm.reg + add]);
15362           else
15363             oappend (names16[modrm.reg + add]);
15364           used_prefixes |= (prefixes & PREFIX_DATA);
15365         }
15366       break;
15367     case m_mode:
15368       if (address_mode == mode_64bit)
15369         oappend (names64[modrm.reg + add]);
15370       else
15371         oappend (names32[modrm.reg + add]);
15372       break;
15373     case mask_bd_mode:
15374     case mask_mode:
15375       oappend (names_mask[modrm.reg + add]);
15376       break;
15377     default:
15378       oappend (INTERNAL_DISASSEMBLER_ERROR);
15379       break;
15380     }
15381 }
15382
15383 static bfd_vma
15384 get64 (void)
15385 {
15386   bfd_vma x;
15387 #ifdef BFD64
15388   unsigned int a;
15389   unsigned int b;
15390
15391   FETCH_DATA (the_info, codep + 8);
15392   a = *codep++ & 0xff;
15393   a |= (*codep++ & 0xff) << 8;
15394   a |= (*codep++ & 0xff) << 16;
15395   a |= (*codep++ & 0xffu) << 24;
15396   b = *codep++ & 0xff;
15397   b |= (*codep++ & 0xff) << 8;
15398   b |= (*codep++ & 0xff) << 16;
15399   b |= (*codep++ & 0xffu) << 24;
15400   x = a + ((bfd_vma) b << 32);
15401 #else
15402   abort ();
15403   x = 0;
15404 #endif
15405   return x;
15406 }
15407
15408 static bfd_signed_vma
15409 get32 (void)
15410 {
15411   bfd_signed_vma x = 0;
15412
15413   FETCH_DATA (the_info, codep + 4);
15414   x = *codep++ & (bfd_signed_vma) 0xff;
15415   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15416   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15417   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15418   return x;
15419 }
15420
15421 static bfd_signed_vma
15422 get32s (void)
15423 {
15424   bfd_signed_vma x = 0;
15425
15426   FETCH_DATA (the_info, codep + 4);
15427   x = *codep++ & (bfd_signed_vma) 0xff;
15428   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15429   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15430   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15431
15432   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15433
15434   return x;
15435 }
15436
15437 static int
15438 get16 (void)
15439 {
15440   int x = 0;
15441
15442   FETCH_DATA (the_info, codep + 2);
15443   x = *codep++ & 0xff;
15444   x |= (*codep++ & 0xff) << 8;
15445   return x;
15446 }
15447
15448 static void
15449 set_op (bfd_vma op, int riprel)
15450 {
15451   op_index[op_ad] = op_ad;
15452   if (address_mode == mode_64bit)
15453     {
15454       op_address[op_ad] = op;
15455       op_riprel[op_ad] = riprel;
15456     }
15457   else
15458     {
15459       /* Mask to get a 32-bit address.  */
15460       op_address[op_ad] = op & 0xffffffff;
15461       op_riprel[op_ad] = riprel & 0xffffffff;
15462     }
15463 }
15464
15465 static void
15466 OP_REG (int code, int sizeflag)
15467 {
15468   const char *s;
15469   int add;
15470
15471   switch (code)
15472     {
15473     case es_reg: case ss_reg: case cs_reg:
15474     case ds_reg: case fs_reg: case gs_reg:
15475       oappend (names_seg[code - es_reg]);
15476       return;
15477     }
15478
15479   USED_REX (REX_B);
15480   if (rex & REX_B)
15481     add = 8;
15482   else
15483     add = 0;
15484
15485   switch (code)
15486     {
15487     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15488     case sp_reg: case bp_reg: case si_reg: case di_reg:
15489       s = names16[code - ax_reg + add];
15490       break;
15491     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15492     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15493       USED_REX (0);
15494       if (rex)
15495         s = names8rex[code - al_reg + add];
15496       else
15497         s = names8[code - al_reg];
15498       break;
15499     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15500     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15501       if (address_mode == mode_64bit
15502           && ((sizeflag & DFLAG) || (rex & REX_W)))
15503         {
15504           s = names64[code - rAX_reg + add];
15505           break;
15506         }
15507       code += eAX_reg - rAX_reg;
15508       /* Fall through.  */
15509     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15510     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15511       USED_REX (REX_W);
15512       if (rex & REX_W)
15513         s = names64[code - eAX_reg + add];
15514       else
15515         {
15516           if (sizeflag & DFLAG)
15517             s = names32[code - eAX_reg + add];
15518           else
15519             s = names16[code - eAX_reg + add];
15520           used_prefixes |= (prefixes & PREFIX_DATA);
15521         }
15522       break;
15523     default:
15524       s = INTERNAL_DISASSEMBLER_ERROR;
15525       break;
15526     }
15527   oappend (s);
15528 }
15529
15530 static void
15531 OP_IMREG (int code, int sizeflag)
15532 {
15533   const char *s;
15534
15535   switch (code)
15536     {
15537     case indir_dx_reg:
15538       if (intel_syntax)
15539         s = "dx";
15540       else
15541         s = "(%dx)";
15542       break;
15543     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15544     case sp_reg: case bp_reg: case si_reg: case di_reg:
15545       s = names16[code - ax_reg];
15546       break;
15547     case es_reg: case ss_reg: case cs_reg:
15548     case ds_reg: case fs_reg: case gs_reg:
15549       s = names_seg[code - es_reg];
15550       break;
15551     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15552     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15553       USED_REX (0);
15554       if (rex)
15555         s = names8rex[code - al_reg];
15556       else
15557         s = names8[code - al_reg];
15558       break;
15559     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15560     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15561       USED_REX (REX_W);
15562       if (rex & REX_W)
15563         s = names64[code - eAX_reg];
15564       else
15565         {
15566           if (sizeflag & DFLAG)
15567             s = names32[code - eAX_reg];
15568           else
15569             s = names16[code - eAX_reg];
15570           used_prefixes |= (prefixes & PREFIX_DATA);
15571         }
15572       break;
15573     case z_mode_ax_reg:
15574       if ((rex & REX_W) || (sizeflag & DFLAG))
15575         s = *names32;
15576       else
15577         s = *names16;
15578       if (!(rex & REX_W))
15579         used_prefixes |= (prefixes & PREFIX_DATA);
15580       break;
15581     default:
15582       s = INTERNAL_DISASSEMBLER_ERROR;
15583       break;
15584     }
15585   oappend (s);
15586 }
15587
15588 static void
15589 OP_I (int bytemode, int sizeflag)
15590 {
15591   bfd_signed_vma op;
15592   bfd_signed_vma mask = -1;
15593
15594   switch (bytemode)
15595     {
15596     case b_mode:
15597       FETCH_DATA (the_info, codep + 1);
15598       op = *codep++;
15599       mask = 0xff;
15600       break;
15601     case q_mode:
15602       if (address_mode == mode_64bit)
15603         {
15604           op = get32s ();
15605           break;
15606         }
15607       /* Fall through.  */
15608     case v_mode:
15609       USED_REX (REX_W);
15610       if (rex & REX_W)
15611         op = get32s ();
15612       else
15613         {
15614           if (sizeflag & DFLAG)
15615             {
15616               op = get32 ();
15617               mask = 0xffffffff;
15618             }
15619           else
15620             {
15621               op = get16 ();
15622               mask = 0xfffff;
15623             }
15624           used_prefixes |= (prefixes & PREFIX_DATA);
15625         }
15626       break;
15627     case w_mode:
15628       mask = 0xfffff;
15629       op = get16 ();
15630       break;
15631     case const_1_mode:
15632       if (intel_syntax)
15633         oappend ("1");
15634       return;
15635     default:
15636       oappend (INTERNAL_DISASSEMBLER_ERROR);
15637       return;
15638     }
15639
15640   op &= mask;
15641   scratchbuf[0] = '$';
15642   print_operand_value (scratchbuf + 1, 1, op);
15643   oappend_maybe_intel (scratchbuf);
15644   scratchbuf[0] = '\0';
15645 }
15646
15647 static void
15648 OP_I64 (int bytemode, int sizeflag)
15649 {
15650   bfd_signed_vma op;
15651   bfd_signed_vma mask = -1;
15652
15653   if (address_mode != mode_64bit)
15654     {
15655       OP_I (bytemode, sizeflag);
15656       return;
15657     }
15658
15659   switch (bytemode)
15660     {
15661     case b_mode:
15662       FETCH_DATA (the_info, codep + 1);
15663       op = *codep++;
15664       mask = 0xff;
15665       break;
15666     case v_mode:
15667       USED_REX (REX_W);
15668       if (rex & REX_W)
15669         op = get64 ();
15670       else
15671         {
15672           if (sizeflag & DFLAG)
15673             {
15674               op = get32 ();
15675               mask = 0xffffffff;
15676             }
15677           else
15678             {
15679               op = get16 ();
15680               mask = 0xfffff;
15681             }
15682           used_prefixes |= (prefixes & PREFIX_DATA);
15683         }
15684       break;
15685     case w_mode:
15686       mask = 0xfffff;
15687       op = get16 ();
15688       break;
15689     default:
15690       oappend (INTERNAL_DISASSEMBLER_ERROR);
15691       return;
15692     }
15693
15694   op &= mask;
15695   scratchbuf[0] = '$';
15696   print_operand_value (scratchbuf + 1, 1, op);
15697   oappend_maybe_intel (scratchbuf);
15698   scratchbuf[0] = '\0';
15699 }
15700
15701 static void
15702 OP_sI (int bytemode, int sizeflag)
15703 {
15704   bfd_signed_vma op;
15705
15706   switch (bytemode)
15707     {
15708     case b_mode:
15709     case b_T_mode:
15710       FETCH_DATA (the_info, codep + 1);
15711       op = *codep++;
15712       if ((op & 0x80) != 0)
15713         op -= 0x100;
15714       if (bytemode == b_T_mode)
15715         {
15716           if (address_mode != mode_64bit
15717               || !((sizeflag & DFLAG) || (rex & REX_W)))
15718             {
15719               /* The operand-size prefix is overridden by a REX prefix.  */
15720               if ((sizeflag & DFLAG) || (rex & REX_W))
15721                 op &= 0xffffffff;
15722               else
15723                 op &= 0xffff;
15724           }
15725         }
15726       else
15727         {
15728           if (!(rex & REX_W))
15729             {
15730               if (sizeflag & DFLAG)
15731                 op &= 0xffffffff;
15732               else
15733                 op &= 0xffff;
15734             }
15735         }
15736       break;
15737     case v_mode:
15738       /* The operand-size prefix is overridden by a REX prefix.  */
15739       if ((sizeflag & DFLAG) || (rex & REX_W))
15740         op = get32s ();
15741       else
15742         op = get16 ();
15743       break;
15744     default:
15745       oappend (INTERNAL_DISASSEMBLER_ERROR);
15746       return;
15747     }
15748
15749   scratchbuf[0] = '$';
15750   print_operand_value (scratchbuf + 1, 1, op);
15751   oappend_maybe_intel (scratchbuf);
15752 }
15753
15754 static void
15755 OP_J (int bytemode, int sizeflag)
15756 {
15757   bfd_vma disp;
15758   bfd_vma mask = -1;
15759   bfd_vma segment = 0;
15760
15761   switch (bytemode)
15762     {
15763     case b_mode:
15764       FETCH_DATA (the_info, codep + 1);
15765       disp = *codep++;
15766       if ((disp & 0x80) != 0)
15767         disp -= 0x100;
15768       break;
15769     case v_mode:
15770       if (isa64 == amd64)
15771         USED_REX (REX_W);
15772       if ((sizeflag & DFLAG)
15773           || (address_mode == mode_64bit
15774               && (isa64 != amd64 || (rex & REX_W))))
15775         disp = get32s ();
15776       else
15777         {
15778           disp = get16 ();
15779           if ((disp & 0x8000) != 0)
15780             disp -= 0x10000;
15781           /* In 16bit mode, address is wrapped around at 64k within
15782              the same segment.  Otherwise, a data16 prefix on a jump
15783              instruction means that the pc is masked to 16 bits after
15784              the displacement is added!  */
15785           mask = 0xffff;
15786           if ((prefixes & PREFIX_DATA) == 0)
15787             segment = ((start_pc + codep - start_codep)
15788                        & ~((bfd_vma) 0xffff));
15789         }
15790       if (address_mode != mode_64bit
15791           || (isa64 == amd64 && !(rex & REX_W)))
15792         used_prefixes |= (prefixes & PREFIX_DATA);
15793       break;
15794     default:
15795       oappend (INTERNAL_DISASSEMBLER_ERROR);
15796       return;
15797     }
15798   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15799   set_op (disp, 0);
15800   print_operand_value (scratchbuf, 1, disp);
15801   oappend (scratchbuf);
15802 }
15803
15804 static void
15805 OP_SEG (int bytemode, int sizeflag)
15806 {
15807   if (bytemode == w_mode)
15808     oappend (names_seg[modrm.reg]);
15809   else
15810     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15811 }
15812
15813 static void
15814 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15815 {
15816   int seg, offset;
15817
15818   if (sizeflag & DFLAG)
15819     {
15820       offset = get32 ();
15821       seg = get16 ();
15822     }
15823   else
15824     {
15825       offset = get16 ();
15826       seg = get16 ();
15827     }
15828   used_prefixes |= (prefixes & PREFIX_DATA);
15829   if (intel_syntax)
15830     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15831   else
15832     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15833   oappend (scratchbuf);
15834 }
15835
15836 static void
15837 OP_OFF (int bytemode, int sizeflag)
15838 {
15839   bfd_vma off;
15840
15841   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15842     intel_operand_size (bytemode, sizeflag);
15843   append_seg ();
15844
15845   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15846     off = get32 ();
15847   else
15848     off = get16 ();
15849
15850   if (intel_syntax)
15851     {
15852       if (!active_seg_prefix)
15853         {
15854           oappend (names_seg[ds_reg - es_reg]);
15855           oappend (":");
15856         }
15857     }
15858   print_operand_value (scratchbuf, 1, off);
15859   oappend (scratchbuf);
15860 }
15861
15862 static void
15863 OP_OFF64 (int bytemode, int sizeflag)
15864 {
15865   bfd_vma off;
15866
15867   if (address_mode != mode_64bit
15868       || (prefixes & PREFIX_ADDR))
15869     {
15870       OP_OFF (bytemode, sizeflag);
15871       return;
15872     }
15873
15874   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15875     intel_operand_size (bytemode, sizeflag);
15876   append_seg ();
15877
15878   off = get64 ();
15879
15880   if (intel_syntax)
15881     {
15882       if (!active_seg_prefix)
15883         {
15884           oappend (names_seg[ds_reg - es_reg]);
15885           oappend (":");
15886         }
15887     }
15888   print_operand_value (scratchbuf, 1, off);
15889   oappend (scratchbuf);
15890 }
15891
15892 static void
15893 ptr_reg (int code, int sizeflag)
15894 {
15895   const char *s;
15896
15897   *obufp++ = open_char;
15898   used_prefixes |= (prefixes & PREFIX_ADDR);
15899   if (address_mode == mode_64bit)
15900     {
15901       if (!(sizeflag & AFLAG))
15902         s = names32[code - eAX_reg];
15903       else
15904         s = names64[code - eAX_reg];
15905     }
15906   else if (sizeflag & AFLAG)
15907     s = names32[code - eAX_reg];
15908   else
15909     s = names16[code - eAX_reg];
15910   oappend (s);
15911   *obufp++ = close_char;
15912   *obufp = 0;
15913 }
15914
15915 static void
15916 OP_ESreg (int code, int sizeflag)
15917 {
15918   if (intel_syntax)
15919     {
15920       switch (codep[-1])
15921         {
15922         case 0x6d:      /* insw/insl */
15923           intel_operand_size (z_mode, sizeflag);
15924           break;
15925         case 0xa5:      /* movsw/movsl/movsq */
15926         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15927         case 0xab:      /* stosw/stosl */
15928         case 0xaf:      /* scasw/scasl */
15929           intel_operand_size (v_mode, sizeflag);
15930           break;
15931         default:
15932           intel_operand_size (b_mode, sizeflag);
15933         }
15934     }
15935   oappend_maybe_intel ("%es:");
15936   ptr_reg (code, sizeflag);
15937 }
15938
15939 static void
15940 OP_DSreg (int code, int sizeflag)
15941 {
15942   if (intel_syntax)
15943     {
15944       switch (codep[-1])
15945         {
15946         case 0x6f:      /* outsw/outsl */
15947           intel_operand_size (z_mode, sizeflag);
15948           break;
15949         case 0xa5:      /* movsw/movsl/movsq */
15950         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15951         case 0xad:      /* lodsw/lodsl/lodsq */
15952           intel_operand_size (v_mode, sizeflag);
15953           break;
15954         default:
15955           intel_operand_size (b_mode, sizeflag);
15956         }
15957     }
15958   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15959      default segment register DS is printed.  */
15960   if (!active_seg_prefix)
15961     active_seg_prefix = PREFIX_DS;
15962   append_seg ();
15963   ptr_reg (code, sizeflag);
15964 }
15965
15966 static void
15967 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15968 {
15969   int add;
15970   if (rex & REX_R)
15971     {
15972       USED_REX (REX_R);
15973       add = 8;
15974     }
15975   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15976     {
15977       all_prefixes[last_lock_prefix] = 0;
15978       used_prefixes |= PREFIX_LOCK;
15979       add = 8;
15980     }
15981   else
15982     add = 0;
15983   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15984   oappend_maybe_intel (scratchbuf);
15985 }
15986
15987 static void
15988 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15989 {
15990   int add;
15991   USED_REX (REX_R);
15992   if (rex & REX_R)
15993     add = 8;
15994   else
15995     add = 0;
15996   if (intel_syntax)
15997     sprintf (scratchbuf, "db%d", modrm.reg + add);
15998   else
15999     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16000   oappend (scratchbuf);
16001 }
16002
16003 static void
16004 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16005 {
16006   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16007   oappend_maybe_intel (scratchbuf);
16008 }
16009
16010 static void
16011 OP_R (int bytemode, int sizeflag)
16012 {
16013   /* Skip mod/rm byte.  */
16014   MODRM_CHECK;
16015   codep++;
16016   OP_E_register (bytemode, sizeflag);
16017 }
16018
16019 static void
16020 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16021 {
16022   int reg = modrm.reg;
16023   const char **names;
16024
16025   used_prefixes |= (prefixes & PREFIX_DATA);
16026   if (prefixes & PREFIX_DATA)
16027     {
16028       names = names_xmm;
16029       USED_REX (REX_R);
16030       if (rex & REX_R)
16031         reg += 8;
16032     }
16033   else
16034     names = names_mm;
16035   oappend (names[reg]);
16036 }
16037
16038 static void
16039 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16040 {
16041   int reg = modrm.reg;
16042   const char **names;
16043
16044   USED_REX (REX_R);
16045   if (rex & REX_R)
16046     reg += 8;
16047   if (vex.evex)
16048     {
16049       if (!vex.r)
16050         reg += 16;
16051     }
16052
16053   if (need_vex
16054       && bytemode != xmm_mode
16055       && bytemode != xmmq_mode
16056       && bytemode != evex_half_bcst_xmmq_mode
16057       && bytemode != ymm_mode
16058       && bytemode != scalar_mode)
16059     {
16060       switch (vex.length)
16061         {
16062         case 128:
16063           names = names_xmm;
16064           break;
16065         case 256:
16066           if (vex.w
16067               || (bytemode != vex_vsib_q_w_dq_mode
16068                   && bytemode != vex_vsib_q_w_d_mode))
16069             names = names_ymm;
16070           else
16071             names = names_xmm;
16072           break;
16073         case 512:
16074           names = names_zmm;
16075           break;
16076         default:
16077           abort ();
16078         }
16079     }
16080   else if (bytemode == xmmq_mode
16081            || bytemode == evex_half_bcst_xmmq_mode)
16082     {
16083       switch (vex.length)
16084         {
16085         case 128:
16086         case 256:
16087           names = names_xmm;
16088           break;
16089         case 512:
16090           names = names_ymm;
16091           break;
16092         default:
16093           abort ();
16094         }
16095     }
16096   else if (bytemode == ymm_mode)
16097     names = names_ymm;
16098   else
16099     names = names_xmm;
16100   oappend (names[reg]);
16101 }
16102
16103 static void
16104 OP_EM (int bytemode, int sizeflag)
16105 {
16106   int reg;
16107   const char **names;
16108
16109   if (modrm.mod != 3)
16110     {
16111       if (intel_syntax
16112           && (bytemode == v_mode || bytemode == v_swap_mode))
16113         {
16114           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16115           used_prefixes |= (prefixes & PREFIX_DATA);
16116         }
16117       OP_E (bytemode, sizeflag);
16118       return;
16119     }
16120
16121   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16122     swap_operand ();
16123
16124   /* Skip mod/rm byte.  */
16125   MODRM_CHECK;
16126   codep++;
16127   used_prefixes |= (prefixes & PREFIX_DATA);
16128   reg = modrm.rm;
16129   if (prefixes & PREFIX_DATA)
16130     {
16131       names = names_xmm;
16132       USED_REX (REX_B);
16133       if (rex & REX_B)
16134         reg += 8;
16135     }
16136   else
16137     names = names_mm;
16138   oappend (names[reg]);
16139 }
16140
16141 /* cvt* are the only instructions in sse2 which have
16142    both SSE and MMX operands and also have 0x66 prefix
16143    in their opcode. 0x66 was originally used to differentiate
16144    between SSE and MMX instruction(operands). So we have to handle the
16145    cvt* separately using OP_EMC and OP_MXC */
16146 static void
16147 OP_EMC (int bytemode, int sizeflag)
16148 {
16149   if (modrm.mod != 3)
16150     {
16151       if (intel_syntax && bytemode == v_mode)
16152         {
16153           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16154           used_prefixes |= (prefixes & PREFIX_DATA);
16155         }
16156       OP_E (bytemode, sizeflag);
16157       return;
16158     }
16159
16160   /* Skip mod/rm byte.  */
16161   MODRM_CHECK;
16162   codep++;
16163   used_prefixes |= (prefixes & PREFIX_DATA);
16164   oappend (names_mm[modrm.rm]);
16165 }
16166
16167 static void
16168 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16169 {
16170   used_prefixes |= (prefixes & PREFIX_DATA);
16171   oappend (names_mm[modrm.reg]);
16172 }
16173
16174 static void
16175 OP_EX (int bytemode, int sizeflag)
16176 {
16177   int reg;
16178   const char **names;
16179
16180   /* Skip mod/rm byte.  */
16181   MODRM_CHECK;
16182   codep++;
16183
16184   if (modrm.mod != 3)
16185     {
16186       OP_E_memory (bytemode, sizeflag);
16187       return;
16188     }
16189
16190   reg = modrm.rm;
16191   USED_REX (REX_B);
16192   if (rex & REX_B)
16193     reg += 8;
16194   if (vex.evex)
16195     {
16196       USED_REX (REX_X);
16197       if ((rex & REX_X))
16198         reg += 16;
16199     }
16200
16201   if ((sizeflag & SUFFIX_ALWAYS)
16202       && (bytemode == x_swap_mode
16203           || bytemode == d_swap_mode
16204           || bytemode == dqw_swap_mode
16205           || bytemode == d_scalar_swap_mode
16206           || bytemode == q_swap_mode
16207           || bytemode == q_scalar_swap_mode))
16208     swap_operand ();
16209
16210   if (need_vex
16211       && bytemode != xmm_mode
16212       && bytemode != xmmdw_mode
16213       && bytemode != xmmqd_mode
16214       && bytemode != xmm_mb_mode
16215       && bytemode != xmm_mw_mode
16216       && bytemode != xmm_md_mode
16217       && bytemode != xmm_mq_mode
16218       && bytemode != xmm_mdq_mode
16219       && bytemode != xmmq_mode
16220       && bytemode != evex_half_bcst_xmmq_mode
16221       && bytemode != ymm_mode
16222       && bytemode != d_scalar_mode
16223       && bytemode != d_scalar_swap_mode
16224       && bytemode != q_scalar_mode
16225       && bytemode != q_scalar_swap_mode
16226       && bytemode != vex_scalar_w_dq_mode)
16227     {
16228       switch (vex.length)
16229         {
16230         case 128:
16231           names = names_xmm;
16232           break;
16233         case 256:
16234           names = names_ymm;
16235           break;
16236         case 512:
16237           names = names_zmm;
16238           break;
16239         default:
16240           abort ();
16241         }
16242     }
16243   else if (bytemode == xmmq_mode
16244            || bytemode == evex_half_bcst_xmmq_mode)
16245     {
16246       switch (vex.length)
16247         {
16248         case 128:
16249         case 256:
16250           names = names_xmm;
16251           break;
16252         case 512:
16253           names = names_ymm;
16254           break;
16255         default:
16256           abort ();
16257         }
16258     }
16259   else if (bytemode == ymm_mode)
16260     names = names_ymm;
16261   else
16262     names = names_xmm;
16263   oappend (names[reg]);
16264 }
16265
16266 static void
16267 OP_MS (int bytemode, int sizeflag)
16268 {
16269   if (modrm.mod == 3)
16270     OP_EM (bytemode, sizeflag);
16271   else
16272     BadOp ();
16273 }
16274
16275 static void
16276 OP_XS (int bytemode, int sizeflag)
16277 {
16278   if (modrm.mod == 3)
16279     OP_EX (bytemode, sizeflag);
16280   else
16281     BadOp ();
16282 }
16283
16284 static void
16285 OP_M (int bytemode, int sizeflag)
16286 {
16287   if (modrm.mod == 3)
16288     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16289     BadOp ();
16290   else
16291     OP_E (bytemode, sizeflag);
16292 }
16293
16294 static void
16295 OP_0f07 (int bytemode, int sizeflag)
16296 {
16297   if (modrm.mod != 3 || modrm.rm != 0)
16298     BadOp ();
16299   else
16300     OP_E (bytemode, sizeflag);
16301 }
16302
16303 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16304    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16305
16306 static void
16307 NOP_Fixup1 (int bytemode, int sizeflag)
16308 {
16309   if ((prefixes & PREFIX_DATA) != 0
16310       || (rex != 0
16311           && rex != 0x48
16312           && address_mode == mode_64bit))
16313     OP_REG (bytemode, sizeflag);
16314   else
16315     strcpy (obuf, "nop");
16316 }
16317
16318 static void
16319 NOP_Fixup2 (int bytemode, int sizeflag)
16320 {
16321   if ((prefixes & PREFIX_DATA) != 0
16322       || (rex != 0
16323           && rex != 0x48
16324           && address_mode == mode_64bit))
16325     OP_IMREG (bytemode, sizeflag);
16326 }
16327
16328 static const char *const Suffix3DNow[] = {
16329 /* 00 */        NULL,           NULL,           NULL,           NULL,
16330 /* 04 */        NULL,           NULL,           NULL,           NULL,
16331 /* 08 */        NULL,           NULL,           NULL,           NULL,
16332 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16333 /* 10 */        NULL,           NULL,           NULL,           NULL,
16334 /* 14 */        NULL,           NULL,           NULL,           NULL,
16335 /* 18 */        NULL,           NULL,           NULL,           NULL,
16336 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16337 /* 20 */        NULL,           NULL,           NULL,           NULL,
16338 /* 24 */        NULL,           NULL,           NULL,           NULL,
16339 /* 28 */        NULL,           NULL,           NULL,           NULL,
16340 /* 2C */        NULL,           NULL,           NULL,           NULL,
16341 /* 30 */        NULL,           NULL,           NULL,           NULL,
16342 /* 34 */        NULL,           NULL,           NULL,           NULL,
16343 /* 38 */        NULL,           NULL,           NULL,           NULL,
16344 /* 3C */        NULL,           NULL,           NULL,           NULL,
16345 /* 40 */        NULL,           NULL,           NULL,           NULL,
16346 /* 44 */        NULL,           NULL,           NULL,           NULL,
16347 /* 48 */        NULL,           NULL,           NULL,           NULL,
16348 /* 4C */        NULL,           NULL,           NULL,           NULL,
16349 /* 50 */        NULL,           NULL,           NULL,           NULL,
16350 /* 54 */        NULL,           NULL,           NULL,           NULL,
16351 /* 58 */        NULL,           NULL,           NULL,           NULL,
16352 /* 5C */        NULL,           NULL,           NULL,           NULL,
16353 /* 60 */        NULL,           NULL,           NULL,           NULL,
16354 /* 64 */        NULL,           NULL,           NULL,           NULL,
16355 /* 68 */        NULL,           NULL,           NULL,           NULL,
16356 /* 6C */        NULL,           NULL,           NULL,           NULL,
16357 /* 70 */        NULL,           NULL,           NULL,           NULL,
16358 /* 74 */        NULL,           NULL,           NULL,           NULL,
16359 /* 78 */        NULL,           NULL,           NULL,           NULL,
16360 /* 7C */        NULL,           NULL,           NULL,           NULL,
16361 /* 80 */        NULL,           NULL,           NULL,           NULL,
16362 /* 84 */        NULL,           NULL,           NULL,           NULL,
16363 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16364 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16365 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16366 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16367 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16368 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16369 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16370 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16371 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16372 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16373 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16374 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16375 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16376 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16377 /* C0 */        NULL,           NULL,           NULL,           NULL,
16378 /* C4 */        NULL,           NULL,           NULL,           NULL,
16379 /* C8 */        NULL,           NULL,           NULL,           NULL,
16380 /* CC */        NULL,           NULL,           NULL,           NULL,
16381 /* D0 */        NULL,           NULL,           NULL,           NULL,
16382 /* D4 */        NULL,           NULL,           NULL,           NULL,
16383 /* D8 */        NULL,           NULL,           NULL,           NULL,
16384 /* DC */        NULL,           NULL,           NULL,           NULL,
16385 /* E0 */        NULL,           NULL,           NULL,           NULL,
16386 /* E4 */        NULL,           NULL,           NULL,           NULL,
16387 /* E8 */        NULL,           NULL,           NULL,           NULL,
16388 /* EC */        NULL,           NULL,           NULL,           NULL,
16389 /* F0 */        NULL,           NULL,           NULL,           NULL,
16390 /* F4 */        NULL,           NULL,           NULL,           NULL,
16391 /* F8 */        NULL,           NULL,           NULL,           NULL,
16392 /* FC */        NULL,           NULL,           NULL,           NULL,
16393 };
16394
16395 static void
16396 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16397 {
16398   const char *mnemonic;
16399
16400   FETCH_DATA (the_info, codep + 1);
16401   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16402      place where an 8-bit immediate would normally go.  ie. the last
16403      byte of the instruction.  */
16404   obufp = mnemonicendp;
16405   mnemonic = Suffix3DNow[*codep++ & 0xff];
16406   if (mnemonic)
16407     oappend (mnemonic);
16408   else
16409     {
16410       /* Since a variable sized modrm/sib chunk is between the start
16411          of the opcode (0x0f0f) and the opcode suffix, we need to do
16412          all the modrm processing first, and don't know until now that
16413          we have a bad opcode.  This necessitates some cleaning up.  */
16414       op_out[0][0] = '\0';
16415       op_out[1][0] = '\0';
16416       BadOp ();
16417     }
16418   mnemonicendp = obufp;
16419 }
16420
16421 static struct op simd_cmp_op[] =
16422 {
16423   { STRING_COMMA_LEN ("eq") },
16424   { STRING_COMMA_LEN ("lt") },
16425   { STRING_COMMA_LEN ("le") },
16426   { STRING_COMMA_LEN ("unord") },
16427   { STRING_COMMA_LEN ("neq") },
16428   { STRING_COMMA_LEN ("nlt") },
16429   { STRING_COMMA_LEN ("nle") },
16430   { STRING_COMMA_LEN ("ord") }
16431 };
16432
16433 static void
16434 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16435 {
16436   unsigned int cmp_type;
16437
16438   FETCH_DATA (the_info, codep + 1);
16439   cmp_type = *codep++ & 0xff;
16440   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16441     {
16442       char suffix [3];
16443       char *p = mnemonicendp - 2;
16444       suffix[0] = p[0];
16445       suffix[1] = p[1];
16446       suffix[2] = '\0';
16447       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16448       mnemonicendp += simd_cmp_op[cmp_type].len;
16449     }
16450   else
16451     {
16452       /* We have a reserved extension byte.  Output it directly.  */
16453       scratchbuf[0] = '$';
16454       print_operand_value (scratchbuf + 1, 1, cmp_type);
16455       oappend_maybe_intel (scratchbuf);
16456       scratchbuf[0] = '\0';
16457     }
16458 }
16459
16460 static void
16461 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16462           int sizeflag ATTRIBUTE_UNUSED)
16463 {
16464   /* mwaitx %eax,%ecx,%ebx */
16465   if (!intel_syntax)
16466     {
16467       const char **names = (address_mode == mode_64bit
16468                             ? names64 : names32);
16469       strcpy (op_out[0], names[0]);
16470       strcpy (op_out[1], names[1]);
16471       strcpy (op_out[2], names[3]);
16472       two_source_ops = 1;
16473     }
16474   /* Skip mod/rm byte.  */
16475   MODRM_CHECK;
16476   codep++;
16477 }
16478
16479 static void
16480 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16481           int sizeflag ATTRIBUTE_UNUSED)
16482 {
16483   /* mwait %eax,%ecx  */
16484   if (!intel_syntax)
16485     {
16486       const char **names = (address_mode == mode_64bit
16487                             ? names64 : names32);
16488       strcpy (op_out[0], names[0]);
16489       strcpy (op_out[1], names[1]);
16490       two_source_ops = 1;
16491     }
16492   /* Skip mod/rm byte.  */
16493   MODRM_CHECK;
16494   codep++;
16495 }
16496
16497 static void
16498 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16499             int sizeflag ATTRIBUTE_UNUSED)
16500 {
16501   /* monitor %eax,%ecx,%edx"  */
16502   if (!intel_syntax)
16503     {
16504       const char **op1_names;
16505       const char **names = (address_mode == mode_64bit
16506                             ? names64 : names32);
16507
16508       if (!(prefixes & PREFIX_ADDR))
16509         op1_names = (address_mode == mode_16bit
16510                      ? names16 : names);
16511       else
16512         {
16513           /* Remove "addr16/addr32".  */
16514           all_prefixes[last_addr_prefix] = 0;
16515           op1_names = (address_mode != mode_32bit
16516                        ? names32 : names16);
16517           used_prefixes |= PREFIX_ADDR;
16518         }
16519       strcpy (op_out[0], op1_names[0]);
16520       strcpy (op_out[1], names[1]);
16521       strcpy (op_out[2], names[2]);
16522       two_source_ops = 1;
16523     }
16524   /* Skip mod/rm byte.  */
16525   MODRM_CHECK;
16526   codep++;
16527 }
16528
16529 static void
16530 BadOp (void)
16531 {
16532   /* Throw away prefixes and 1st. opcode byte.  */
16533   codep = insn_codep + 1;
16534   oappend ("(bad)");
16535 }
16536
16537 static void
16538 REP_Fixup (int bytemode, int sizeflag)
16539 {
16540   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16541      lods and stos.  */
16542   if (prefixes & PREFIX_REPZ)
16543     all_prefixes[last_repz_prefix] = REP_PREFIX;
16544
16545   switch (bytemode)
16546     {
16547     case al_reg:
16548     case eAX_reg:
16549     case indir_dx_reg:
16550       OP_IMREG (bytemode, sizeflag);
16551       break;
16552     case eDI_reg:
16553       OP_ESreg (bytemode, sizeflag);
16554       break;
16555     case eSI_reg:
16556       OP_DSreg (bytemode, sizeflag);
16557       break;
16558     default:
16559       abort ();
16560       break;
16561     }
16562 }
16563
16564 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16565    "bnd".  */
16566
16567 static void
16568 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16569 {
16570   if (prefixes & PREFIX_REPNZ)
16571     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16572 }
16573
16574 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16575    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16576  */
16577
16578 static void
16579 HLE_Fixup1 (int bytemode, int sizeflag)
16580 {
16581   if (modrm.mod != 3
16582       && (prefixes & PREFIX_LOCK) != 0)
16583     {
16584       if (prefixes & PREFIX_REPZ)
16585         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16586       if (prefixes & PREFIX_REPNZ)
16587         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16588     }
16589
16590   OP_E (bytemode, sizeflag);
16591 }
16592
16593 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16594    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16595  */
16596
16597 static void
16598 HLE_Fixup2 (int bytemode, int sizeflag)
16599 {
16600   if (modrm.mod != 3)
16601     {
16602       if (prefixes & PREFIX_REPZ)
16603         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16604       if (prefixes & PREFIX_REPNZ)
16605         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16606     }
16607
16608   OP_E (bytemode, sizeflag);
16609 }
16610
16611 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16612    "xrelease" for memory operand.  No check for LOCK prefix.   */
16613
16614 static void
16615 HLE_Fixup3 (int bytemode, int sizeflag)
16616 {
16617   if (modrm.mod != 3
16618       && last_repz_prefix > last_repnz_prefix
16619       && (prefixes & PREFIX_REPZ) != 0)
16620     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16621
16622   OP_E (bytemode, sizeflag);
16623 }
16624
16625 static void
16626 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16627 {
16628   USED_REX (REX_W);
16629   if (rex & REX_W)
16630     {
16631       /* Change cmpxchg8b to cmpxchg16b.  */
16632       char *p = mnemonicendp - 2;
16633       mnemonicendp = stpcpy (p, "16b");
16634       bytemode = o_mode;
16635     }
16636   else if ((prefixes & PREFIX_LOCK) != 0)
16637     {
16638       if (prefixes & PREFIX_REPZ)
16639         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16640       if (prefixes & PREFIX_REPNZ)
16641         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16642     }
16643
16644   OP_M (bytemode, sizeflag);
16645 }
16646
16647 static void
16648 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16649 {
16650   const char **names;
16651
16652   if (need_vex)
16653     {
16654       switch (vex.length)
16655         {
16656         case 128:
16657           names = names_xmm;
16658           break;
16659         case 256:
16660           names = names_ymm;
16661           break;
16662         default:
16663           abort ();
16664         }
16665     }
16666   else
16667     names = names_xmm;
16668   oappend (names[reg]);
16669 }
16670
16671 static void
16672 CRC32_Fixup (int bytemode, int sizeflag)
16673 {
16674   /* Add proper suffix to "crc32".  */
16675   char *p = mnemonicendp;
16676
16677   switch (bytemode)
16678     {
16679     case b_mode:
16680       if (intel_syntax)
16681         goto skip;
16682
16683       *p++ = 'b';
16684       break;
16685     case v_mode:
16686       if (intel_syntax)
16687         goto skip;
16688
16689       USED_REX (REX_W);
16690       if (rex & REX_W)
16691         *p++ = 'q';
16692       else
16693         {
16694           if (sizeflag & DFLAG)
16695             *p++ = 'l';
16696           else
16697             *p++ = 'w';
16698           used_prefixes |= (prefixes & PREFIX_DATA);
16699         }
16700       break;
16701     default:
16702       oappend (INTERNAL_DISASSEMBLER_ERROR);
16703       break;
16704     }
16705   mnemonicendp = p;
16706   *p = '\0';
16707
16708 skip:
16709   if (modrm.mod == 3)
16710     {
16711       int add;
16712
16713       /* Skip mod/rm byte.  */
16714       MODRM_CHECK;
16715       codep++;
16716
16717       USED_REX (REX_B);
16718       add = (rex & REX_B) ? 8 : 0;
16719       if (bytemode == b_mode)
16720         {
16721           USED_REX (0);
16722           if (rex)
16723             oappend (names8rex[modrm.rm + add]);
16724           else
16725             oappend (names8[modrm.rm + add]);
16726         }
16727       else
16728         {
16729           USED_REX (REX_W);
16730           if (rex & REX_W)
16731             oappend (names64[modrm.rm + add]);
16732           else if ((prefixes & PREFIX_DATA))
16733             oappend (names16[modrm.rm + add]);
16734           else
16735             oappend (names32[modrm.rm + add]);
16736         }
16737     }
16738   else
16739     OP_E (bytemode, sizeflag);
16740 }
16741
16742 static void
16743 FXSAVE_Fixup (int bytemode, int sizeflag)
16744 {
16745   /* Add proper suffix to "fxsave" and "fxrstor".  */
16746   USED_REX (REX_W);
16747   if (rex & REX_W)
16748     {
16749       char *p = mnemonicendp;
16750       *p++ = '6';
16751       *p++ = '4';
16752       *p = '\0';
16753       mnemonicendp = p;
16754     }
16755   OP_M (bytemode, sizeflag);
16756 }
16757
16758 /* Display the destination register operand for instructions with
16759    VEX. */
16760
16761 static void
16762 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16763 {
16764   int reg;
16765   const char **names;
16766
16767   if (!need_vex)
16768     abort ();
16769
16770   if (!need_vex_reg)
16771     return;
16772
16773   reg = vex.register_specifier;
16774   if (vex.evex)
16775     {
16776       if (!vex.v)
16777         reg += 16;
16778     }
16779
16780   if (bytemode == vex_scalar_mode)
16781     {
16782       oappend (names_xmm[reg]);
16783       return;
16784     }
16785
16786   switch (vex.length)
16787     {
16788     case 128:
16789       switch (bytemode)
16790         {
16791         case vex_mode:
16792         case vex128_mode:
16793         case vex_vsib_q_w_dq_mode:
16794         case vex_vsib_q_w_d_mode:
16795           names = names_xmm;
16796           break;
16797         case dq_mode:
16798           if (vex.w)
16799             names = names64;
16800           else
16801             names = names32;
16802           break;
16803         case mask_bd_mode:
16804         case mask_mode:
16805           names = names_mask;
16806           break;
16807         default:
16808           abort ();
16809           return;
16810         }
16811       break;
16812     case 256:
16813       switch (bytemode)
16814         {
16815         case vex_mode:
16816         case vex256_mode:
16817           names = names_ymm;
16818           break;
16819         case vex_vsib_q_w_dq_mode:
16820         case vex_vsib_q_w_d_mode:
16821           names = vex.w ? names_ymm : names_xmm;
16822           break;
16823         case mask_bd_mode:
16824         case mask_mode:
16825           names = names_mask;
16826           break;
16827         default:
16828           abort ();
16829           return;
16830         }
16831       break;
16832     case 512:
16833       names = names_zmm;
16834       break;
16835     default:
16836       abort ();
16837       break;
16838     }
16839   oappend (names[reg]);
16840 }
16841
16842 /* Get the VEX immediate byte without moving codep.  */
16843
16844 static unsigned char
16845 get_vex_imm8 (int sizeflag, int opnum)
16846 {
16847   int bytes_before_imm = 0;
16848
16849   if (modrm.mod != 3)
16850     {
16851       /* There are SIB/displacement bytes.  */
16852       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16853         {
16854           /* 32/64 bit address mode */
16855           int base = modrm.rm;
16856
16857           /* Check SIB byte.  */
16858           if (base == 4)
16859             {
16860               FETCH_DATA (the_info, codep + 1);
16861               base = *codep & 7;
16862               /* When decoding the third source, don't increase
16863                  bytes_before_imm as this has already been incremented
16864                  by one in OP_E_memory while decoding the second
16865                  source operand.  */
16866               if (opnum == 0)
16867                 bytes_before_imm++;
16868             }
16869
16870           /* Don't increase bytes_before_imm when decoding the third source,
16871              it has already been incremented by OP_E_memory while decoding
16872              the second source operand.  */
16873           if (opnum == 0)
16874             {
16875               switch (modrm.mod)
16876                 {
16877                   case 0:
16878                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16879                        SIB == 5, there is a 4 byte displacement.  */
16880                     if (base != 5)
16881                       /* No displacement. */
16882                       break;
16883                   case 2:
16884                     /* 4 byte displacement.  */
16885                     bytes_before_imm += 4;
16886                     break;
16887                   case 1:
16888                     /* 1 byte displacement.  */
16889                     bytes_before_imm++;
16890                     break;
16891                 }
16892             }
16893         }
16894       else
16895         {
16896           /* 16 bit address mode */
16897           /* Don't increase bytes_before_imm when decoding the third source,
16898              it has already been incremented by OP_E_memory while decoding
16899              the second source operand.  */
16900           if (opnum == 0)
16901             {
16902               switch (modrm.mod)
16903                 {
16904                 case 0:
16905                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16906                   if (modrm.rm != 6)
16907                     /* No displacement. */
16908                     break;
16909                 case 2:
16910                   /* 2 byte displacement.  */
16911                   bytes_before_imm += 2;
16912                   break;
16913                 case 1:
16914                   /* 1 byte displacement: when decoding the third source,
16915                      don't increase bytes_before_imm as this has already
16916                      been incremented by one in OP_E_memory while decoding
16917                      the second source operand.  */
16918                   if (opnum == 0)
16919                     bytes_before_imm++;
16920
16921                   break;
16922                 }
16923             }
16924         }
16925     }
16926
16927   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16928   return codep [bytes_before_imm];
16929 }
16930
16931 static void
16932 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16933 {
16934   const char **names;
16935
16936   if (reg == -1 && modrm.mod != 3)
16937     {
16938       OP_E_memory (bytemode, sizeflag);
16939       return;
16940     }
16941   else
16942     {
16943       if (reg == -1)
16944         {
16945           reg = modrm.rm;
16946           USED_REX (REX_B);
16947           if (rex & REX_B)
16948             reg += 8;
16949         }
16950       else if (reg > 7 && address_mode != mode_64bit)
16951         BadOp ();
16952     }
16953
16954   switch (vex.length)
16955     {
16956     case 128:
16957       names = names_xmm;
16958       break;
16959     case 256:
16960       names = names_ymm;
16961       break;
16962     default:
16963       abort ();
16964     }
16965   oappend (names[reg]);
16966 }
16967
16968 static void
16969 OP_EX_VexImmW (int bytemode, int sizeflag)
16970 {
16971   int reg = -1;
16972   static unsigned char vex_imm8;
16973
16974   if (vex_w_done == 0)
16975     {
16976       vex_w_done = 1;
16977
16978       /* Skip mod/rm byte.  */
16979       MODRM_CHECK;
16980       codep++;
16981
16982       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16983
16984       if (vex.w)
16985           reg = vex_imm8 >> 4;
16986
16987       OP_EX_VexReg (bytemode, sizeflag, reg);
16988     }
16989   else if (vex_w_done == 1)
16990     {
16991       vex_w_done = 2;
16992
16993       if (!vex.w)
16994           reg = vex_imm8 >> 4;
16995
16996       OP_EX_VexReg (bytemode, sizeflag, reg);
16997     }
16998   else
16999     {
17000       /* Output the imm8 directly.  */
17001       scratchbuf[0] = '$';
17002       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17003       oappend_maybe_intel (scratchbuf);
17004       scratchbuf[0] = '\0';
17005       codep++;
17006     }
17007 }
17008
17009 static void
17010 OP_Vex_2src (int bytemode, int sizeflag)
17011 {
17012   if (modrm.mod == 3)
17013     {
17014       int reg = modrm.rm;
17015       USED_REX (REX_B);
17016       if (rex & REX_B)
17017         reg += 8;
17018       oappend (names_xmm[reg]);
17019     }
17020   else
17021     {
17022       if (intel_syntax
17023           && (bytemode == v_mode || bytemode == v_swap_mode))
17024         {
17025           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17026           used_prefixes |= (prefixes & PREFIX_DATA);
17027         }
17028       OP_E (bytemode, sizeflag);
17029     }
17030 }
17031
17032 static void
17033 OP_Vex_2src_1 (int bytemode, int sizeflag)
17034 {
17035   if (modrm.mod == 3)
17036     {
17037       /* Skip mod/rm byte.   */
17038       MODRM_CHECK;
17039       codep++;
17040     }
17041
17042   if (vex.w)
17043     oappend (names_xmm[vex.register_specifier]);
17044   else
17045     OP_Vex_2src (bytemode, sizeflag);
17046 }
17047
17048 static void
17049 OP_Vex_2src_2 (int bytemode, int sizeflag)
17050 {
17051   if (vex.w)
17052     OP_Vex_2src (bytemode, sizeflag);
17053   else
17054     oappend (names_xmm[vex.register_specifier]);
17055 }
17056
17057 static void
17058 OP_EX_VexW (int bytemode, int sizeflag)
17059 {
17060   int reg = -1;
17061
17062   if (!vex_w_done)
17063     {
17064       vex_w_done = 1;
17065
17066       /* Skip mod/rm byte.  */
17067       MODRM_CHECK;
17068       codep++;
17069
17070       if (vex.w)
17071         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17072     }
17073   else
17074     {
17075       if (!vex.w)
17076         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17077     }
17078
17079   OP_EX_VexReg (bytemode, sizeflag, reg);
17080 }
17081
17082 static void
17083 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17084              int sizeflag ATTRIBUTE_UNUSED)
17085 {
17086   /* Skip the immediate byte and check for invalid bits.  */
17087   FETCH_DATA (the_info, codep + 1);
17088   if (*codep++ & 0xf)
17089     BadOp ();
17090 }
17091
17092 static void
17093 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17094 {
17095   int reg;
17096   const char **names;
17097
17098   FETCH_DATA (the_info, codep + 1);
17099   reg = *codep++;
17100
17101   if (bytemode != x_mode)
17102     abort ();
17103
17104   if (reg & 0xf)
17105       BadOp ();
17106
17107   reg >>= 4;
17108   if (reg > 7 && address_mode != mode_64bit)
17109     BadOp ();
17110
17111   switch (vex.length)
17112     {
17113     case 128:
17114       names = names_xmm;
17115       break;
17116     case 256:
17117       names = names_ymm;
17118       break;
17119     default:
17120       abort ();
17121     }
17122   oappend (names[reg]);
17123 }
17124
17125 static void
17126 OP_XMM_VexW (int bytemode, int sizeflag)
17127 {
17128   /* Turn off the REX.W bit since it is used for swapping operands
17129      now.  */
17130   rex &= ~REX_W;
17131   OP_XMM (bytemode, sizeflag);
17132 }
17133
17134 static void
17135 OP_EX_Vex (int bytemode, int sizeflag)
17136 {
17137   if (modrm.mod != 3)
17138     {
17139       if (vex.register_specifier != 0)
17140         BadOp ();
17141       need_vex_reg = 0;
17142     }
17143   OP_EX (bytemode, sizeflag);
17144 }
17145
17146 static void
17147 OP_XMM_Vex (int bytemode, int sizeflag)
17148 {
17149   if (modrm.mod != 3)
17150     {
17151       if (vex.register_specifier != 0)
17152         BadOp ();
17153       need_vex_reg = 0;
17154     }
17155   OP_XMM (bytemode, sizeflag);
17156 }
17157
17158 static void
17159 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17160 {
17161   switch (vex.length)
17162     {
17163     case 128:
17164       mnemonicendp = stpcpy (obuf, "vzeroupper");
17165       break;
17166     case 256:
17167       mnemonicendp = stpcpy (obuf, "vzeroall");
17168       break;
17169     default:
17170       abort ();
17171     }
17172 }
17173
17174 static struct op vex_cmp_op[] =
17175 {
17176   { STRING_COMMA_LEN ("eq") },
17177   { STRING_COMMA_LEN ("lt") },
17178   { STRING_COMMA_LEN ("le") },
17179   { STRING_COMMA_LEN ("unord") },
17180   { STRING_COMMA_LEN ("neq") },
17181   { STRING_COMMA_LEN ("nlt") },
17182   { STRING_COMMA_LEN ("nle") },
17183   { STRING_COMMA_LEN ("ord") },
17184   { STRING_COMMA_LEN ("eq_uq") },
17185   { STRING_COMMA_LEN ("nge") },
17186   { STRING_COMMA_LEN ("ngt") },
17187   { STRING_COMMA_LEN ("false") },
17188   { STRING_COMMA_LEN ("neq_oq") },
17189   { STRING_COMMA_LEN ("ge") },
17190   { STRING_COMMA_LEN ("gt") },
17191   { STRING_COMMA_LEN ("true") },
17192   { STRING_COMMA_LEN ("eq_os") },
17193   { STRING_COMMA_LEN ("lt_oq") },
17194   { STRING_COMMA_LEN ("le_oq") },
17195   { STRING_COMMA_LEN ("unord_s") },
17196   { STRING_COMMA_LEN ("neq_us") },
17197   { STRING_COMMA_LEN ("nlt_uq") },
17198   { STRING_COMMA_LEN ("nle_uq") },
17199   { STRING_COMMA_LEN ("ord_s") },
17200   { STRING_COMMA_LEN ("eq_us") },
17201   { STRING_COMMA_LEN ("nge_uq") },
17202   { STRING_COMMA_LEN ("ngt_uq") },
17203   { STRING_COMMA_LEN ("false_os") },
17204   { STRING_COMMA_LEN ("neq_os") },
17205   { STRING_COMMA_LEN ("ge_oq") },
17206   { STRING_COMMA_LEN ("gt_oq") },
17207   { STRING_COMMA_LEN ("true_us") },
17208 };
17209
17210 static void
17211 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17212 {
17213   unsigned int cmp_type;
17214
17215   FETCH_DATA (the_info, codep + 1);
17216   cmp_type = *codep++ & 0xff;
17217   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17218     {
17219       char suffix [3];
17220       char *p = mnemonicendp - 2;
17221       suffix[0] = p[0];
17222       suffix[1] = p[1];
17223       suffix[2] = '\0';
17224       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17225       mnemonicendp += vex_cmp_op[cmp_type].len;
17226     }
17227   else
17228     {
17229       /* We have a reserved extension byte.  Output it directly.  */
17230       scratchbuf[0] = '$';
17231       print_operand_value (scratchbuf + 1, 1, cmp_type);
17232       oappend_maybe_intel (scratchbuf);
17233       scratchbuf[0] = '\0';
17234     }
17235 }
17236
17237 static void
17238 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17239              int sizeflag ATTRIBUTE_UNUSED)
17240 {
17241   unsigned int cmp_type;
17242
17243   if (!vex.evex)
17244     abort ();
17245
17246   FETCH_DATA (the_info, codep + 1);
17247   cmp_type = *codep++ & 0xff;
17248   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17249      If it's the case, print suffix, otherwise - print the immediate.  */
17250   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17251       && cmp_type != 3
17252       && cmp_type != 7)
17253     {
17254       char suffix [3];
17255       char *p = mnemonicendp - 2;
17256
17257       /* vpcmp* can have both one- and two-lettered suffix.  */
17258       if (p[0] == 'p')
17259         {
17260           p++;
17261           suffix[0] = p[0];
17262           suffix[1] = '\0';
17263         }
17264       else
17265         {
17266           suffix[0] = p[0];
17267           suffix[1] = p[1];
17268           suffix[2] = '\0';
17269         }
17270
17271       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17272       mnemonicendp += simd_cmp_op[cmp_type].len;
17273     }
17274   else
17275     {
17276       /* We have a reserved extension byte.  Output it directly.  */
17277       scratchbuf[0] = '$';
17278       print_operand_value (scratchbuf + 1, 1, cmp_type);
17279       oappend_maybe_intel (scratchbuf);
17280       scratchbuf[0] = '\0';
17281     }
17282 }
17283
17284 static const struct op pclmul_op[] =
17285 {
17286   { STRING_COMMA_LEN ("lql") },
17287   { STRING_COMMA_LEN ("hql") },
17288   { STRING_COMMA_LEN ("lqh") },
17289   { STRING_COMMA_LEN ("hqh") }
17290 };
17291
17292 static void
17293 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17294               int sizeflag ATTRIBUTE_UNUSED)
17295 {
17296   unsigned int pclmul_type;
17297
17298   FETCH_DATA (the_info, codep + 1);
17299   pclmul_type = *codep++ & 0xff;
17300   switch (pclmul_type)
17301     {
17302     case 0x10:
17303       pclmul_type = 2;
17304       break;
17305     case 0x11:
17306       pclmul_type = 3;
17307       break;
17308     default:
17309       break;
17310     }
17311   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17312     {
17313       char suffix [4];
17314       char *p = mnemonicendp - 3;
17315       suffix[0] = p[0];
17316       suffix[1] = p[1];
17317       suffix[2] = p[2];
17318       suffix[3] = '\0';
17319       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17320       mnemonicendp += pclmul_op[pclmul_type].len;
17321     }
17322   else
17323     {
17324       /* We have a reserved extension byte.  Output it directly.  */
17325       scratchbuf[0] = '$';
17326       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17327       oappend_maybe_intel (scratchbuf);
17328       scratchbuf[0] = '\0';
17329     }
17330 }
17331
17332 static void
17333 MOVBE_Fixup (int bytemode, int sizeflag)
17334 {
17335   /* Add proper suffix to "movbe".  */
17336   char *p = mnemonicendp;
17337
17338   switch (bytemode)
17339     {
17340     case v_mode:
17341       if (intel_syntax)
17342         goto skip;
17343
17344       USED_REX (REX_W);
17345       if (sizeflag & SUFFIX_ALWAYS)
17346         {
17347           if (rex & REX_W)
17348             *p++ = 'q';
17349           else
17350             {
17351               if (sizeflag & DFLAG)
17352                 *p++ = 'l';
17353               else
17354                 *p++ = 'w';
17355               used_prefixes |= (prefixes & PREFIX_DATA);
17356             }
17357         }
17358       break;
17359     default:
17360       oappend (INTERNAL_DISASSEMBLER_ERROR);
17361       break;
17362     }
17363   mnemonicendp = p;
17364   *p = '\0';
17365
17366 skip:
17367   OP_M (bytemode, sizeflag);
17368 }
17369
17370 static void
17371 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17372 {
17373   int reg;
17374   const char **names;
17375
17376   /* Skip mod/rm byte.  */
17377   MODRM_CHECK;
17378   codep++;
17379
17380   if (vex.w)
17381     names = names64;
17382   else
17383     names = names32;
17384
17385   reg = modrm.rm;
17386   USED_REX (REX_B);
17387   if (rex & REX_B)
17388     reg += 8;
17389
17390   oappend (names[reg]);
17391 }
17392
17393 static void
17394 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17395 {
17396   const char **names;
17397
17398   if (vex.w)
17399     names = names64;
17400   else
17401     names = names32;
17402
17403   oappend (names[vex.register_specifier]);
17404 }
17405
17406 static void
17407 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17408 {
17409   if (!vex.evex
17410       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17411     abort ();
17412
17413   USED_REX (REX_R);
17414   if ((rex & REX_R) != 0 || !vex.r)
17415     {
17416       BadOp ();
17417       return;
17418     }
17419
17420   oappend (names_mask [modrm.reg]);
17421 }
17422
17423 static void
17424 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17425 {
17426   if (!vex.evex
17427       || (bytemode != evex_rounding_mode
17428           && bytemode != evex_sae_mode))
17429     abort ();
17430   if (modrm.mod == 3 && vex.b)
17431     switch (bytemode)
17432       {
17433       case evex_rounding_mode:
17434         oappend (names_rounding[vex.ll]);
17435         break;
17436       case evex_sae_mode:
17437         oappend ("{sae}");
17438         break;
17439       default:
17440         break;
17441       }
17442 }