opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define EdqwS { OP_E, dqw_swap_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, stack_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   dqw_swap_mode,
 560   bnd_mode,
 561   /* 4- or 6-byte pointer operand */
 562   f_mode,
 563   const_1_mode,
 564   /* v_mode for stack-related opcodes.  */
 565   stack_v_mode,
 566   /* non-quad operand size depends on prefixes */
 567   z_mode,
 568   /* 16-byte operand */
 569   o_mode,
 570   /* registers like dq_mode, memory like b_mode.  */
 571   dqb_mode,
 572   /* registers like d_mode, memory like b_mode.  */
 573   db_mode,
 574   /* registers like d_mode, memory like w_mode.  */
 575   dw_mode,
 576   /* registers like dq_mode, memory like d_mode.  */
 577   dqd_mode,
 578   /* normal vex mode */
 579   vex_mode,
 580   /* 128bit vex mode */
 581   vex128_mode,
 582   /* 256bit vex mode */
 583   vex256_mode,
 584   /* operand size depends on the VEX.W bit.  */
 585   vex_w_dq_mode,
 586
 587   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 588   vex_vsib_d_w_dq_mode,
 589   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 590   vex_vsib_d_w_d_mode,
 591   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 592   vex_vsib_q_w_dq_mode,
 593   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 594   vex_vsib_q_w_d_mode,
 595
 596   /* scalar, ignore vector length.  */
 597   scalar_mode,
 598   /* like d_mode, ignore vector length.  */
 599   d_scalar_mode,
 600   /* like d_swap_mode, ignore vector length.  */
 601   d_scalar_swap_mode,
 602   /* like q_mode, ignore vector length.  */
 603   q_scalar_mode,
 604   /* like q_swap_mode, ignore vector length.  */
 605   q_scalar_swap_mode,
 606   /* like vex_mode, ignore vector length.  */
 607   vex_scalar_mode,
 608   /* like vex_w_dq_mode, ignore vector length.  */
 609   vex_scalar_w_dq_mode,
 610
 611   /* Static rounding.  */
 612   evex_rounding_mode,
 613   /* Supress all exceptions.  */
 614   evex_sae_mode,
 615
 616   /* Mask register operand.  */
 617   mask_mode,
 618   /* Mask register operand.  */
 619   mask_bd_mode,
 620
 621   es_reg,
 622   cs_reg,
 623   ss_reg,
 624   ds_reg,
 625   fs_reg,
 626   gs_reg,
 627
 628   eAX_reg,
 629   eCX_reg,
 630   eDX_reg,
 631   eBX_reg,
 632   eSP_reg,
 633   eBP_reg,
 634   eSI_reg,
 635   eDI_reg,
 636
 637   al_reg,
 638   cl_reg,
 639   dl_reg,
 640   bl_reg,
 641   ah_reg,
 642   ch_reg,
 643   dh_reg,
 644   bh_reg,
 645
 646   ax_reg,
 647   cx_reg,
 648   dx_reg,
 649   bx_reg,
 650   sp_reg,
 651   bp_reg,
 652   si_reg,
 653   di_reg,
 654
 655   rAX_reg,
 656   rCX_reg,
 657   rDX_reg,
 658   rBX_reg,
 659   rSP_reg,
 660   rBP_reg,
 661   rSI_reg,
 662   rDI_reg,
 663
 664   z_mode_ax_reg,
 665   indir_dx_reg
 666 };
 667
 668 enum
 669 {
 670   FLOATCODE = 1,
 671   USE_REG_TABLE,
 672   USE_MOD_TABLE,
 673   USE_RM_TABLE,
 674   USE_PREFIX_TABLE,
 675   USE_X86_64_TABLE,
 676   USE_3BYTE_TABLE,
 677   USE_XOP_8F_TABLE,
 678   USE_VEX_C4_TABLE,
 679   USE_VEX_C5_TABLE,
 680   USE_VEX_LEN_TABLE,
 681   USE_VEX_W_TABLE,
 682   USE_EVEX_TABLE
 683 };
 684
 685 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 686
 687 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 688 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 689 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 690 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 691 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 692 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 693 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 694 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 695 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 696 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 697 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 698 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 699 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 700 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 701 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 702
 703 enum
 704 {
 705   REG_80 = 0,
 706   REG_81,
 707   REG_82,
 708   REG_8F,
 709   REG_C0,
 710   REG_C1,
 711   REG_C6,
 712   REG_C7,
 713   REG_D0,
 714   REG_D1,
 715   REG_D2,
 716   REG_D3,
 717   REG_F6,
 718   REG_F7,
 719   REG_FE,
 720   REG_FF,
 721   REG_0F00,
 722   REG_0F01,
 723   REG_0F0D,
 724   REG_0F18,
 725   REG_0F71,
 726   REG_0F72,
 727   REG_0F73,
 728   REG_0FA6,
 729   REG_0FA7,
 730   REG_0FAE,
 731   REG_0FBA,
 732   REG_0FC7,
 733   REG_VEX_0F71,
 734   REG_VEX_0F72,
 735   REG_VEX_0F73,
 736   REG_VEX_0FAE,
 737   REG_VEX_0F38F3,
 738   REG_XOP_LWPCB,
 739   REG_XOP_LWP,
 740   REG_XOP_TBM_01,
 741   REG_XOP_TBM_02,
 742
 743   REG_EVEX_0F71,
 744   REG_EVEX_0F72,
 745   REG_EVEX_0F73,
 746   REG_EVEX_0F38C6,
 747   REG_EVEX_0F38C7
 748 };
 749
 750 enum
 751 {
 752   MOD_8D = 0,
 753   MOD_C6_REG_7,
 754   MOD_C7_REG_7,
 755   MOD_FF_REG_3,
 756   MOD_FF_REG_5,
 757   MOD_0F01_REG_0,
 758   MOD_0F01_REG_1,
 759   MOD_0F01_REG_2,
 760   MOD_0F01_REG_3,
 761   MOD_0F01_REG_7,
 762   MOD_0F12_PREFIX_0,
 763   MOD_0F13,
 764   MOD_0F16_PREFIX_0,
 765   MOD_0F17,
 766   MOD_0F18_REG_0,
 767   MOD_0F18_REG_1,
 768   MOD_0F18_REG_2,
 769   MOD_0F18_REG_3,
 770   MOD_0F18_REG_4,
 771   MOD_0F18_REG_5,
 772   MOD_0F18_REG_6,
 773   MOD_0F18_REG_7,
 774   MOD_0F1A_PREFIX_0,
 775   MOD_0F1B_PREFIX_0,
 776   MOD_0F1B_PREFIX_1,
 777   MOD_0F24,
 778   MOD_0F26,
 779   MOD_0F2B_PREFIX_0,
 780   MOD_0F2B_PREFIX_1,
 781   MOD_0F2B_PREFIX_2,
 782   MOD_0F2B_PREFIX_3,
 783   MOD_0F51,
 784   MOD_0F71_REG_2,
 785   MOD_0F71_REG_4,
 786   MOD_0F71_REG_6,
 787   MOD_0F72_REG_2,
 788   MOD_0F72_REG_4,
 789   MOD_0F72_REG_6,
 790   MOD_0F73_REG_2,
 791   MOD_0F73_REG_3,
 792   MOD_0F73_REG_6,
 793   MOD_0F73_REG_7,
 794   MOD_0FAE_REG_0,
 795   MOD_0FAE_REG_1,
 796   MOD_0FAE_REG_2,
 797   MOD_0FAE_REG_3,
 798   MOD_0FAE_REG_4,
 799   MOD_0FAE_REG_5,
 800   MOD_0FAE_REG_6,
 801   MOD_0FAE_REG_7,
 802   MOD_0FB2,
 803   MOD_0FB4,
 804   MOD_0FB5,
 805   MOD_0FC3,
 806   MOD_0FC7_REG_3,
 807   MOD_0FC7_REG_4,
 808   MOD_0FC7_REG_5,
 809   MOD_0FC7_REG_6,
 810   MOD_0FC7_REG_7,
 811   MOD_0FD7,
 812   MOD_0FE7_PREFIX_2,
 813   MOD_0FF0_PREFIX_3,
 814   MOD_0F382A_PREFIX_2,
 815   MOD_62_32BIT,
 816   MOD_C4_32BIT,
 817   MOD_C5_32BIT,
 818   MOD_VEX_0F12_PREFIX_0,
 819   MOD_VEX_0F13,
 820   MOD_VEX_0F16_PREFIX_0,
 821   MOD_VEX_0F17,
 822   MOD_VEX_0F2B,
 823   MOD_VEX_W_0_0F41_P_0_LEN_1,
 824   MOD_VEX_W_1_0F41_P_0_LEN_1,
 825   MOD_VEX_W_0_0F41_P_2_LEN_1,
 826   MOD_VEX_W_1_0F41_P_2_LEN_1,
 827   MOD_VEX_W_0_0F42_P_0_LEN_1,
 828   MOD_VEX_W_1_0F42_P_0_LEN_1,
 829   MOD_VEX_W_0_0F42_P_2_LEN_1,
 830   MOD_VEX_W_1_0F42_P_2_LEN_1,
 831   MOD_VEX_W_0_0F44_P_0_LEN_1,
 832   MOD_VEX_W_1_0F44_P_0_LEN_1,
 833   MOD_VEX_W_0_0F44_P_2_LEN_1,
 834   MOD_VEX_W_1_0F44_P_2_LEN_1,
 835   MOD_VEX_W_0_0F45_P_0_LEN_1,
 836   MOD_VEX_W_1_0F45_P_0_LEN_1,
 837   MOD_VEX_W_0_0F45_P_2_LEN_1,
 838   MOD_VEX_W_1_0F45_P_2_LEN_1,
 839   MOD_VEX_W_0_0F46_P_0_LEN_1,
 840   MOD_VEX_W_1_0F46_P_0_LEN_1,
 841   MOD_VEX_W_0_0F46_P_2_LEN_1,
 842   MOD_VEX_W_1_0F46_P_2_LEN_1,
 843   MOD_VEX_W_0_0F47_P_0_LEN_1,
 844   MOD_VEX_W_1_0F47_P_0_LEN_1,
 845   MOD_VEX_W_0_0F47_P_2_LEN_1,
 846   MOD_VEX_W_1_0F47_P_2_LEN_1,
 847   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 848   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 849   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 850   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 851   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 852   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 853   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 854   MOD_VEX_0F50,
 855   MOD_VEX_0F71_REG_2,
 856   MOD_VEX_0F71_REG_4,
 857   MOD_VEX_0F71_REG_6,
 858   MOD_VEX_0F72_REG_2,
 859   MOD_VEX_0F72_REG_4,
 860   MOD_VEX_0F72_REG_6,
 861   MOD_VEX_0F73_REG_2,
 862   MOD_VEX_0F73_REG_3,
 863   MOD_VEX_0F73_REG_6,
 864   MOD_VEX_0F73_REG_7,
 865   MOD_VEX_W_0_0F91_P_0_LEN_0,
 866   MOD_VEX_W_1_0F91_P_0_LEN_0,
 867   MOD_VEX_W_0_0F91_P_2_LEN_0,
 868   MOD_VEX_W_1_0F91_P_2_LEN_0,
 869   MOD_VEX_W_0_0F92_P_0_LEN_0,
 870   MOD_VEX_W_0_0F92_P_2_LEN_0,
 871   MOD_VEX_W_0_0F92_P_3_LEN_0,
 872   MOD_VEX_W_1_0F92_P_3_LEN_0,
 873   MOD_VEX_W_0_0F93_P_0_LEN_0,
 874   MOD_VEX_W_0_0F93_P_2_LEN_0,
 875   MOD_VEX_W_0_0F93_P_3_LEN_0,
 876   MOD_VEX_W_1_0F93_P_3_LEN_0,
 877   MOD_VEX_W_0_0F98_P_0_LEN_0,
 878   MOD_VEX_W_1_0F98_P_0_LEN_0,
 879   MOD_VEX_W_0_0F98_P_2_LEN_0,
 880   MOD_VEX_W_1_0F98_P_2_LEN_0,
 881   MOD_VEX_W_0_0F99_P_0_LEN_0,
 882   MOD_VEX_W_1_0F99_P_0_LEN_0,
 883   MOD_VEX_W_0_0F99_P_2_LEN_0,
 884   MOD_VEX_W_1_0F99_P_2_LEN_0,
 885   MOD_VEX_0FAE_REG_2,
 886   MOD_VEX_0FAE_REG_3,
 887   MOD_VEX_0FD7_PREFIX_2,
 888   MOD_VEX_0FE7_PREFIX_2,
 889   MOD_VEX_0FF0_PREFIX_3,
 890   MOD_VEX_0F381A_PREFIX_2,
 891   MOD_VEX_0F382A_PREFIX_2,
 892   MOD_VEX_0F382C_PREFIX_2,
 893   MOD_VEX_0F382D_PREFIX_2,
 894   MOD_VEX_0F382E_PREFIX_2,
 895   MOD_VEX_0F382F_PREFIX_2,
 896   MOD_VEX_0F385A_PREFIX_2,
 897   MOD_VEX_0F388C_PREFIX_2,
 898   MOD_VEX_0F388E_PREFIX_2,
 899   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 900   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 901   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 902   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 903   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 904   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 905   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 906   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 907
 908   MOD_EVEX_0F10_PREFIX_1,
 909   MOD_EVEX_0F10_PREFIX_3,
 910   MOD_EVEX_0F11_PREFIX_1,
 911   MOD_EVEX_0F11_PREFIX_3,
 912   MOD_EVEX_0F12_PREFIX_0,
 913   MOD_EVEX_0F16_PREFIX_0,
 914   MOD_EVEX_0F38C6_REG_1,
 915   MOD_EVEX_0F38C6_REG_2,
 916   MOD_EVEX_0F38C6_REG_5,
 917   MOD_EVEX_0F38C6_REG_6,
 918   MOD_EVEX_0F38C7_REG_1,
 919   MOD_EVEX_0F38C7_REG_2,
 920   MOD_EVEX_0F38C7_REG_5,
 921   MOD_EVEX_0F38C7_REG_6
 922 };
 923
 924 enum
 925 {
 926   RM_C6_REG_7 = 0,
 927   RM_C7_REG_7,
 928   RM_0F01_REG_0,
 929   RM_0F01_REG_1,
 930   RM_0F01_REG_2,
 931   RM_0F01_REG_3,
 932   RM_0F01_REG_7,
 933   RM_0FAE_REG_5,
 934   RM_0FAE_REG_6,
 935   RM_0FAE_REG_7
 936 };
 937
 938 enum
 939 {
 940   PREFIX_90 = 0,
 941   PREFIX_0F10,
 942   PREFIX_0F11,
 943   PREFIX_0F12,
 944   PREFIX_0F16,
 945   PREFIX_0F1A,
 946   PREFIX_0F1B,
 947   PREFIX_0F2A,
 948   PREFIX_0F2B,
 949   PREFIX_0F2C,
 950   PREFIX_0F2D,
 951   PREFIX_0F2E,
 952   PREFIX_0F2F,
 953   PREFIX_0F51,
 954   PREFIX_0F52,
 955   PREFIX_0F53,
 956   PREFIX_0F58,
 957   PREFIX_0F59,
 958   PREFIX_0F5A,
 959   PREFIX_0F5B,
 960   PREFIX_0F5C,
 961   PREFIX_0F5D,
 962   PREFIX_0F5E,
 963   PREFIX_0F5F,
 964   PREFIX_0F60,
 965   PREFIX_0F61,
 966   PREFIX_0F62,
 967   PREFIX_0F6C,
 968   PREFIX_0F6D,
 969   PREFIX_0F6F,
 970   PREFIX_0F70,
 971   PREFIX_0F73_REG_3,
 972   PREFIX_0F73_REG_7,
 973   PREFIX_0F78,
 974   PREFIX_0F79,
 975   PREFIX_0F7C,
 976   PREFIX_0F7D,
 977   PREFIX_0F7E,
 978   PREFIX_0F7F,
 979   PREFIX_0FAE_REG_0,
 980   PREFIX_0FAE_REG_1,
 981   PREFIX_0FAE_REG_2,
 982   PREFIX_0FAE_REG_3,
 983   PREFIX_0FAE_REG_6,
 984   PREFIX_0FAE_REG_7,
 985   PREFIX_RM_0_0FAE_REG_7,
 986   PREFIX_0FB8,
 987   PREFIX_0FBC,
 988   PREFIX_0FBD,
 989   PREFIX_0FC2,
 990   PREFIX_MOD_0_0FC3,
 991   PREFIX_MOD_0_0FC7_REG_6,
 992   PREFIX_MOD_3_0FC7_REG_6,
 993   PREFIX_MOD_3_0FC7_REG_7,
 994   PREFIX_0FD0,
 995   PREFIX_0FD6,
 996   PREFIX_0FE6,
 997   PREFIX_0FE7,
 998   PREFIX_0FF0,
 999   PREFIX_0FF7,
1000   PREFIX_0F3810,
1001   PREFIX_0F3814,
1002   PREFIX_0F3815,
1003   PREFIX_0F3817,
1004   PREFIX_0F3820,
1005   PREFIX_0F3821,
1006   PREFIX_0F3822,
1007   PREFIX_0F3823,
1008   PREFIX_0F3824,
1009   PREFIX_0F3825,
1010   PREFIX_0F3828,
1011   PREFIX_0F3829,
1012   PREFIX_0F382A,
1013   PREFIX_0F382B,
1014   PREFIX_0F3830,
1015   PREFIX_0F3831,
1016   PREFIX_0F3832,
1017   PREFIX_0F3833,
1018   PREFIX_0F3834,
1019   PREFIX_0F3835,
1020   PREFIX_0F3837,
1021   PREFIX_0F3838,
1022   PREFIX_0F3839,
1023   PREFIX_0F383A,
1024   PREFIX_0F383B,
1025   PREFIX_0F383C,
1026   PREFIX_0F383D,
1027   PREFIX_0F383E,
1028   PREFIX_0F383F,
1029   PREFIX_0F3840,
1030   PREFIX_0F3841,
1031   PREFIX_0F3880,
1032   PREFIX_0F3881,
1033   PREFIX_0F3882,
1034   PREFIX_0F38C8,
1035   PREFIX_0F38C9,
1036   PREFIX_0F38CA,
1037   PREFIX_0F38CB,
1038   PREFIX_0F38CC,
1039   PREFIX_0F38CD,
1040   PREFIX_0F38DB,
1041   PREFIX_0F38DC,
1042   PREFIX_0F38DD,
1043   PREFIX_0F38DE,
1044   PREFIX_0F38DF,
1045   PREFIX_0F38F0,
1046   PREFIX_0F38F1,
1047   PREFIX_0F38F6,
1048   PREFIX_0F3A08,
1049   PREFIX_0F3A09,
1050   PREFIX_0F3A0A,
1051   PREFIX_0F3A0B,
1052   PREFIX_0F3A0C,
1053   PREFIX_0F3A0D,
1054   PREFIX_0F3A0E,
1055   PREFIX_0F3A14,
1056   PREFIX_0F3A15,
1057   PREFIX_0F3A16,
1058   PREFIX_0F3A17,
1059   PREFIX_0F3A20,
1060   PREFIX_0F3A21,
1061   PREFIX_0F3A22,
1062   PREFIX_0F3A40,
1063   PREFIX_0F3A41,
1064   PREFIX_0F3A42,
1065   PREFIX_0F3A44,
1066   PREFIX_0F3A60,
1067   PREFIX_0F3A61,
1068   PREFIX_0F3A62,
1069   PREFIX_0F3A63,
1070   PREFIX_0F3ACC,
1071   PREFIX_0F3ADF,
1072   PREFIX_VEX_0F10,
1073   PREFIX_VEX_0F11,
1074   PREFIX_VEX_0F12,
1075   PREFIX_VEX_0F16,
1076   PREFIX_VEX_0F2A,
1077   PREFIX_VEX_0F2C,
1078   PREFIX_VEX_0F2D,
1079   PREFIX_VEX_0F2E,
1080   PREFIX_VEX_0F2F,
1081   PREFIX_VEX_0F41,
1082   PREFIX_VEX_0F42,
1083   PREFIX_VEX_0F44,
1084   PREFIX_VEX_0F45,
1085   PREFIX_VEX_0F46,
1086   PREFIX_VEX_0F47,
1087   PREFIX_VEX_0F4A,
1088   PREFIX_VEX_0F4B,
1089   PREFIX_VEX_0F51,
1090   PREFIX_VEX_0F52,
1091   PREFIX_VEX_0F53,
1092   PREFIX_VEX_0F58,
1093   PREFIX_VEX_0F59,
1094   PREFIX_VEX_0F5A,
1095   PREFIX_VEX_0F5B,
1096   PREFIX_VEX_0F5C,
1097   PREFIX_VEX_0F5D,
1098   PREFIX_VEX_0F5E,
1099   PREFIX_VEX_0F5F,
1100   PREFIX_VEX_0F60,
1101   PREFIX_VEX_0F61,
1102   PREFIX_VEX_0F62,
1103   PREFIX_VEX_0F63,
1104   PREFIX_VEX_0F64,
1105   PREFIX_VEX_0F65,
1106   PREFIX_VEX_0F66,
1107   PREFIX_VEX_0F67,
1108   PREFIX_VEX_0F68,
1109   PREFIX_VEX_0F69,
1110   PREFIX_VEX_0F6A,
1111   PREFIX_VEX_0F6B,
1112   PREFIX_VEX_0F6C,
1113   PREFIX_VEX_0F6D,
1114   PREFIX_VEX_0F6E,
1115   PREFIX_VEX_0F6F,
1116   PREFIX_VEX_0F70,
1117   PREFIX_VEX_0F71_REG_2,
1118   PREFIX_VEX_0F71_REG_4,
1119   PREFIX_VEX_0F71_REG_6,
1120   PREFIX_VEX_0F72_REG_2,
1121   PREFIX_VEX_0F72_REG_4,
1122   PREFIX_VEX_0F72_REG_6,
1123   PREFIX_VEX_0F73_REG_2,
1124   PREFIX_VEX_0F73_REG_3,
1125   PREFIX_VEX_0F73_REG_6,
1126   PREFIX_VEX_0F73_REG_7,
1127   PREFIX_VEX_0F74,
1128   PREFIX_VEX_0F75,
1129   PREFIX_VEX_0F76,
1130   PREFIX_VEX_0F77,
1131   PREFIX_VEX_0F7C,
1132   PREFIX_VEX_0F7D,
1133   PREFIX_VEX_0F7E,
1134   PREFIX_VEX_0F7F,
1135   PREFIX_VEX_0F90,
1136   PREFIX_VEX_0F91,
1137   PREFIX_VEX_0F92,
1138   PREFIX_VEX_0F93,
1139   PREFIX_VEX_0F98,
1140   PREFIX_VEX_0F99,
1141   PREFIX_VEX_0FC2,
1142   PREFIX_VEX_0FC4,
1143   PREFIX_VEX_0FC5,
1144   PREFIX_VEX_0FD0,
1145   PREFIX_VEX_0FD1,
1146   PREFIX_VEX_0FD2,
1147   PREFIX_VEX_0FD3,
1148   PREFIX_VEX_0FD4,
1149   PREFIX_VEX_0FD5,
1150   PREFIX_VEX_0FD6,
1151   PREFIX_VEX_0FD7,
1152   PREFIX_VEX_0FD8,
1153   PREFIX_VEX_0FD9,
1154   PREFIX_VEX_0FDA,
1155   PREFIX_VEX_0FDB,
1156   PREFIX_VEX_0FDC,
1157   PREFIX_VEX_0FDD,
1158   PREFIX_VEX_0FDE,
1159   PREFIX_VEX_0FDF,
1160   PREFIX_VEX_0FE0,
1161   PREFIX_VEX_0FE1,
1162   PREFIX_VEX_0FE2,
1163   PREFIX_VEX_0FE3,
1164   PREFIX_VEX_0FE4,
1165   PREFIX_VEX_0FE5,
1166   PREFIX_VEX_0FE6,
1167   PREFIX_VEX_0FE7,
1168   PREFIX_VEX_0FE8,
1169   PREFIX_VEX_0FE9,
1170   PREFIX_VEX_0FEA,
1171   PREFIX_VEX_0FEB,
1172   PREFIX_VEX_0FEC,
1173   PREFIX_VEX_0FED,
1174   PREFIX_VEX_0FEE,
1175   PREFIX_VEX_0FEF,
1176   PREFIX_VEX_0FF0,
1177   PREFIX_VEX_0FF1,
1178   PREFIX_VEX_0FF2,
1179   PREFIX_VEX_0FF3,
1180   PREFIX_VEX_0FF4,
1181   PREFIX_VEX_0FF5,
1182   PREFIX_VEX_0FF6,
1183   PREFIX_VEX_0FF7,
1184   PREFIX_VEX_0FF8,
1185   PREFIX_VEX_0FF9,
1186   PREFIX_VEX_0FFA,
1187   PREFIX_VEX_0FFB,
1188   PREFIX_VEX_0FFC,
1189   PREFIX_VEX_0FFD,
1190   PREFIX_VEX_0FFE,
1191   PREFIX_VEX_0F3800,
1192   PREFIX_VEX_0F3801,
1193   PREFIX_VEX_0F3802,
1194   PREFIX_VEX_0F3803,
1195   PREFIX_VEX_0F3804,
1196   PREFIX_VEX_0F3805,
1197   PREFIX_VEX_0F3806,
1198   PREFIX_VEX_0F3807,
1199   PREFIX_VEX_0F3808,
1200   PREFIX_VEX_0F3809,
1201   PREFIX_VEX_0F380A,
1202   PREFIX_VEX_0F380B,
1203   PREFIX_VEX_0F380C,
1204   PREFIX_VEX_0F380D,
1205   PREFIX_VEX_0F380E,
1206   PREFIX_VEX_0F380F,
1207   PREFIX_VEX_0F3813,
1208   PREFIX_VEX_0F3816,
1209   PREFIX_VEX_0F3817,
1210   PREFIX_VEX_0F3818,
1211   PREFIX_VEX_0F3819,
1212   PREFIX_VEX_0F381A,
1213   PREFIX_VEX_0F381C,
1214   PREFIX_VEX_0F381D,
1215   PREFIX_VEX_0F381E,
1216   PREFIX_VEX_0F3820,
1217   PREFIX_VEX_0F3821,
1218   PREFIX_VEX_0F3822,
1219   PREFIX_VEX_0F3823,
1220   PREFIX_VEX_0F3824,
1221   PREFIX_VEX_0F3825,
1222   PREFIX_VEX_0F3828,
1223   PREFIX_VEX_0F3829,
1224   PREFIX_VEX_0F382A,
1225   PREFIX_VEX_0F382B,
1226   PREFIX_VEX_0F382C,
1227   PREFIX_VEX_0F382D,
1228   PREFIX_VEX_0F382E,
1229   PREFIX_VEX_0F382F,
1230   PREFIX_VEX_0F3830,
1231   PREFIX_VEX_0F3831,
1232   PREFIX_VEX_0F3832,
1233   PREFIX_VEX_0F3833,
1234   PREFIX_VEX_0F3834,
1235   PREFIX_VEX_0F3835,
1236   PREFIX_VEX_0F3836,
1237   PREFIX_VEX_0F3837,
1238   PREFIX_VEX_0F3838,
1239   PREFIX_VEX_0F3839,
1240   PREFIX_VEX_0F383A,
1241   PREFIX_VEX_0F383B,
1242   PREFIX_VEX_0F383C,
1243   PREFIX_VEX_0F383D,
1244   PREFIX_VEX_0F383E,
1245   PREFIX_VEX_0F383F,
1246   PREFIX_VEX_0F3840,
1247   PREFIX_VEX_0F3841,
1248   PREFIX_VEX_0F3845,
1249   PREFIX_VEX_0F3846,
1250   PREFIX_VEX_0F3847,
1251   PREFIX_VEX_0F3858,
1252   PREFIX_VEX_0F3859,
1253   PREFIX_VEX_0F385A,
1254   PREFIX_VEX_0F3878,
1255   PREFIX_VEX_0F3879,
1256   PREFIX_VEX_0F388C,
1257   PREFIX_VEX_0F388E,
1258   PREFIX_VEX_0F3890,
1259   PREFIX_VEX_0F3891,
1260   PREFIX_VEX_0F3892,
1261   PREFIX_VEX_0F3893,
1262   PREFIX_VEX_0F3896,
1263   PREFIX_VEX_0F3897,
1264   PREFIX_VEX_0F3898,
1265   PREFIX_VEX_0F3899,
1266   PREFIX_VEX_0F389A,
1267   PREFIX_VEX_0F389B,
1268   PREFIX_VEX_0F389C,
1269   PREFIX_VEX_0F389D,
1270   PREFIX_VEX_0F389E,
1271   PREFIX_VEX_0F389F,
1272   PREFIX_VEX_0F38A6,
1273   PREFIX_VEX_0F38A7,
1274   PREFIX_VEX_0F38A8,
1275   PREFIX_VEX_0F38A9,
1276   PREFIX_VEX_0F38AA,
1277   PREFIX_VEX_0F38AB,
1278   PREFIX_VEX_0F38AC,
1279   PREFIX_VEX_0F38AD,
1280   PREFIX_VEX_0F38AE,
1281   PREFIX_VEX_0F38AF,
1282   PREFIX_VEX_0F38B6,
1283   PREFIX_VEX_0F38B7,
1284   PREFIX_VEX_0F38B8,
1285   PREFIX_VEX_0F38B9,
1286   PREFIX_VEX_0F38BA,
1287   PREFIX_VEX_0F38BB,
1288   PREFIX_VEX_0F38BC,
1289   PREFIX_VEX_0F38BD,
1290   PREFIX_VEX_0F38BE,
1291   PREFIX_VEX_0F38BF,
1292   PREFIX_VEX_0F38DB,
1293   PREFIX_VEX_0F38DC,
1294   PREFIX_VEX_0F38DD,
1295   PREFIX_VEX_0F38DE,
1296   PREFIX_VEX_0F38DF,
1297   PREFIX_VEX_0F38F2,
1298   PREFIX_VEX_0F38F3_REG_1,
1299   PREFIX_VEX_0F38F3_REG_2,
1300   PREFIX_VEX_0F38F3_REG_3,
1301   PREFIX_VEX_0F38F5,
1302   PREFIX_VEX_0F38F6,
1303   PREFIX_VEX_0F38F7,
1304   PREFIX_VEX_0F3A00,
1305   PREFIX_VEX_0F3A01,
1306   PREFIX_VEX_0F3A02,
1307   PREFIX_VEX_0F3A04,
1308   PREFIX_VEX_0F3A05,
1309   PREFIX_VEX_0F3A06,
1310   PREFIX_VEX_0F3A08,
1311   PREFIX_VEX_0F3A09,
1312   PREFIX_VEX_0F3A0A,
1313   PREFIX_VEX_0F3A0B,
1314   PREFIX_VEX_0F3A0C,
1315   PREFIX_VEX_0F3A0D,
1316   PREFIX_VEX_0F3A0E,
1317   PREFIX_VEX_0F3A0F,
1318   PREFIX_VEX_0F3A14,
1319   PREFIX_VEX_0F3A15,
1320   PREFIX_VEX_0F3A16,
1321   PREFIX_VEX_0F3A17,
1322   PREFIX_VEX_0F3A18,
1323   PREFIX_VEX_0F3A19,
1324   PREFIX_VEX_0F3A1D,
1325   PREFIX_VEX_0F3A20,
1326   PREFIX_VEX_0F3A21,
1327   PREFIX_VEX_0F3A22,
1328   PREFIX_VEX_0F3A30,
1329   PREFIX_VEX_0F3A31,
1330   PREFIX_VEX_0F3A32,
1331   PREFIX_VEX_0F3A33,
1332   PREFIX_VEX_0F3A38,
1333   PREFIX_VEX_0F3A39,
1334   PREFIX_VEX_0F3A40,
1335   PREFIX_VEX_0F3A41,
1336   PREFIX_VEX_0F3A42,
1337   PREFIX_VEX_0F3A44,
1338   PREFIX_VEX_0F3A46,
1339   PREFIX_VEX_0F3A48,
1340   PREFIX_VEX_0F3A49,
1341   PREFIX_VEX_0F3A4A,
1342   PREFIX_VEX_0F3A4B,
1343   PREFIX_VEX_0F3A4C,
1344   PREFIX_VEX_0F3A5C,
1345   PREFIX_VEX_0F3A5D,
1346   PREFIX_VEX_0F3A5E,
1347   PREFIX_VEX_0F3A5F,
1348   PREFIX_VEX_0F3A60,
1349   PREFIX_VEX_0F3A61,
1350   PREFIX_VEX_0F3A62,
1351   PREFIX_VEX_0F3A63,
1352   PREFIX_VEX_0F3A68,
1353   PREFIX_VEX_0F3A69,
1354   PREFIX_VEX_0F3A6A,
1355   PREFIX_VEX_0F3A6B,
1356   PREFIX_VEX_0F3A6C,
1357   PREFIX_VEX_0F3A6D,
1358   PREFIX_VEX_0F3A6E,
1359   PREFIX_VEX_0F3A6F,
1360   PREFIX_VEX_0F3A78,
1361   PREFIX_VEX_0F3A79,
1362   PREFIX_VEX_0F3A7A,
1363   PREFIX_VEX_0F3A7B,
1364   PREFIX_VEX_0F3A7C,
1365   PREFIX_VEX_0F3A7D,
1366   PREFIX_VEX_0F3A7E,
1367   PREFIX_VEX_0F3A7F,
1368   PREFIX_VEX_0F3ADF,
1369   PREFIX_VEX_0F3AF0,
1370
1371   PREFIX_EVEX_0F10,
1372   PREFIX_EVEX_0F11,
1373   PREFIX_EVEX_0F12,
1374   PREFIX_EVEX_0F13,
1375   PREFIX_EVEX_0F14,
1376   PREFIX_EVEX_0F15,
1377   PREFIX_EVEX_0F16,
1378   PREFIX_EVEX_0F17,
1379   PREFIX_EVEX_0F28,
1380   PREFIX_EVEX_0F29,
1381   PREFIX_EVEX_0F2A,
1382   PREFIX_EVEX_0F2B,
1383   PREFIX_EVEX_0F2C,
1384   PREFIX_EVEX_0F2D,
1385   PREFIX_EVEX_0F2E,
1386   PREFIX_EVEX_0F2F,
1387   PREFIX_EVEX_0F51,
1388   PREFIX_EVEX_0F54,
1389   PREFIX_EVEX_0F55,
1390   PREFIX_EVEX_0F56,
1391   PREFIX_EVEX_0F57,
1392   PREFIX_EVEX_0F58,
1393   PREFIX_EVEX_0F59,
1394   PREFIX_EVEX_0F5A,
1395   PREFIX_EVEX_0F5B,
1396   PREFIX_EVEX_0F5C,
1397   PREFIX_EVEX_0F5D,
1398   PREFIX_EVEX_0F5E,
1399   PREFIX_EVEX_0F5F,
1400   PREFIX_EVEX_0F60,
1401   PREFIX_EVEX_0F61,
1402   PREFIX_EVEX_0F62,
1403   PREFIX_EVEX_0F63,
1404   PREFIX_EVEX_0F64,
1405   PREFIX_EVEX_0F65,
1406   PREFIX_EVEX_0F66,
1407   PREFIX_EVEX_0F67,
1408   PREFIX_EVEX_0F68,
1409   PREFIX_EVEX_0F69,
1410   PREFIX_EVEX_0F6A,
1411   PREFIX_EVEX_0F6B,
1412   PREFIX_EVEX_0F6C,
1413   PREFIX_EVEX_0F6D,
1414   PREFIX_EVEX_0F6E,
1415   PREFIX_EVEX_0F6F,
1416   PREFIX_EVEX_0F70,
1417   PREFIX_EVEX_0F71_REG_2,
1418   PREFIX_EVEX_0F71_REG_4,
1419   PREFIX_EVEX_0F71_REG_6,
1420   PREFIX_EVEX_0F72_REG_0,
1421   PREFIX_EVEX_0F72_REG_1,
1422   PREFIX_EVEX_0F72_REG_2,
1423   PREFIX_EVEX_0F72_REG_4,
1424   PREFIX_EVEX_0F72_REG_6,
1425   PREFIX_EVEX_0F73_REG_2,
1426   PREFIX_EVEX_0F73_REG_3,
1427   PREFIX_EVEX_0F73_REG_6,
1428   PREFIX_EVEX_0F73_REG_7,
1429   PREFIX_EVEX_0F74,
1430   PREFIX_EVEX_0F75,
1431   PREFIX_EVEX_0F76,
1432   PREFIX_EVEX_0F78,
1433   PREFIX_EVEX_0F79,
1434   PREFIX_EVEX_0F7A,
1435   PREFIX_EVEX_0F7B,
1436   PREFIX_EVEX_0F7E,
1437   PREFIX_EVEX_0F7F,
1438   PREFIX_EVEX_0FC2,
1439   PREFIX_EVEX_0FC4,
1440   PREFIX_EVEX_0FC5,
1441   PREFIX_EVEX_0FC6,
1442   PREFIX_EVEX_0FD1,
1443   PREFIX_EVEX_0FD2,
1444   PREFIX_EVEX_0FD3,
1445   PREFIX_EVEX_0FD4,
1446   PREFIX_EVEX_0FD5,
1447   PREFIX_EVEX_0FD6,
1448   PREFIX_EVEX_0FD8,
1449   PREFIX_EVEX_0FD9,
1450   PREFIX_EVEX_0FDA,
1451   PREFIX_EVEX_0FDB,
1452   PREFIX_EVEX_0FDC,
1453   PREFIX_EVEX_0FDD,
1454   PREFIX_EVEX_0FDE,
1455   PREFIX_EVEX_0FDF,
1456   PREFIX_EVEX_0FE0,
1457   PREFIX_EVEX_0FE1,
1458   PREFIX_EVEX_0FE2,
1459   PREFIX_EVEX_0FE3,
1460   PREFIX_EVEX_0FE4,
1461   PREFIX_EVEX_0FE5,
1462   PREFIX_EVEX_0FE6,
1463   PREFIX_EVEX_0FE7,
1464   PREFIX_EVEX_0FE8,
1465   PREFIX_EVEX_0FE9,
1466   PREFIX_EVEX_0FEA,
1467   PREFIX_EVEX_0FEB,
1468   PREFIX_EVEX_0FEC,
1469   PREFIX_EVEX_0FED,
1470   PREFIX_EVEX_0FEE,
1471   PREFIX_EVEX_0FEF,
1472   PREFIX_EVEX_0FF1,
1473   PREFIX_EVEX_0FF2,
1474   PREFIX_EVEX_0FF3,
1475   PREFIX_EVEX_0FF4,
1476   PREFIX_EVEX_0FF5,
1477   PREFIX_EVEX_0FF6,
1478   PREFIX_EVEX_0FF8,
1479   PREFIX_EVEX_0FF9,
1480   PREFIX_EVEX_0FFA,
1481   PREFIX_EVEX_0FFB,
1482   PREFIX_EVEX_0FFC,
1483   PREFIX_EVEX_0FFD,
1484   PREFIX_EVEX_0FFE,
1485   PREFIX_EVEX_0F3800,
1486   PREFIX_EVEX_0F3804,
1487   PREFIX_EVEX_0F380B,
1488   PREFIX_EVEX_0F380C,
1489   PREFIX_EVEX_0F380D,
1490   PREFIX_EVEX_0F3810,
1491   PREFIX_EVEX_0F3811,
1492   PREFIX_EVEX_0F3812,
1493   PREFIX_EVEX_0F3813,
1494   PREFIX_EVEX_0F3814,
1495   PREFIX_EVEX_0F3815,
1496   PREFIX_EVEX_0F3816,
1497   PREFIX_EVEX_0F3818,
1498   PREFIX_EVEX_0F3819,
1499   PREFIX_EVEX_0F381A,
1500   PREFIX_EVEX_0F381B,
1501   PREFIX_EVEX_0F381C,
1502   PREFIX_EVEX_0F381D,
1503   PREFIX_EVEX_0F381E,
1504   PREFIX_EVEX_0F381F,
1505   PREFIX_EVEX_0F3820,
1506   PREFIX_EVEX_0F3821,
1507   PREFIX_EVEX_0F3822,
1508   PREFIX_EVEX_0F3823,
1509   PREFIX_EVEX_0F3824,
1510   PREFIX_EVEX_0F3825,
1511   PREFIX_EVEX_0F3826,
1512   PREFIX_EVEX_0F3827,
1513   PREFIX_EVEX_0F3828,
1514   PREFIX_EVEX_0F3829,
1515   PREFIX_EVEX_0F382A,
1516   PREFIX_EVEX_0F382B,
1517   PREFIX_EVEX_0F382C,
1518   PREFIX_EVEX_0F382D,
1519   PREFIX_EVEX_0F3830,
1520   PREFIX_EVEX_0F3831,
1521   PREFIX_EVEX_0F3832,
1522   PREFIX_EVEX_0F3833,
1523   PREFIX_EVEX_0F3834,
1524   PREFIX_EVEX_0F3835,
1525   PREFIX_EVEX_0F3836,
1526   PREFIX_EVEX_0F3837,
1527   PREFIX_EVEX_0F3838,
1528   PREFIX_EVEX_0F3839,
1529   PREFIX_EVEX_0F383A,
1530   PREFIX_EVEX_0F383B,
1531   PREFIX_EVEX_0F383C,
1532   PREFIX_EVEX_0F383D,
1533   PREFIX_EVEX_0F383E,
1534   PREFIX_EVEX_0F383F,
1535   PREFIX_EVEX_0F3840,
1536   PREFIX_EVEX_0F3842,
1537   PREFIX_EVEX_0F3843,
1538   PREFIX_EVEX_0F3844,
1539   PREFIX_EVEX_0F3845,
1540   PREFIX_EVEX_0F3846,
1541   PREFIX_EVEX_0F3847,
1542   PREFIX_EVEX_0F384C,
1543   PREFIX_EVEX_0F384D,
1544   PREFIX_EVEX_0F384E,
1545   PREFIX_EVEX_0F384F,
1546   PREFIX_EVEX_0F3858,
1547   PREFIX_EVEX_0F3859,
1548   PREFIX_EVEX_0F385A,
1549   PREFIX_EVEX_0F385B,
1550   PREFIX_EVEX_0F3864,
1551   PREFIX_EVEX_0F3865,
1552   PREFIX_EVEX_0F3866,
1553   PREFIX_EVEX_0F3875,
1554   PREFIX_EVEX_0F3876,
1555   PREFIX_EVEX_0F3877,
1556   PREFIX_EVEX_0F3878,
1557   PREFIX_EVEX_0F3879,
1558   PREFIX_EVEX_0F387A,
1559   PREFIX_EVEX_0F387B,
1560   PREFIX_EVEX_0F387C,
1561   PREFIX_EVEX_0F387D,
1562   PREFIX_EVEX_0F387E,
1563   PREFIX_EVEX_0F387F,
1564   PREFIX_EVEX_0F3883,
1565   PREFIX_EVEX_0F3888,
1566   PREFIX_EVEX_0F3889,
1567   PREFIX_EVEX_0F388A,
1568   PREFIX_EVEX_0F388B,
1569   PREFIX_EVEX_0F388D,
1570   PREFIX_EVEX_0F3890,
1571   PREFIX_EVEX_0F3891,
1572   PREFIX_EVEX_0F3892,
1573   PREFIX_EVEX_0F3893,
1574   PREFIX_EVEX_0F3896,
1575   PREFIX_EVEX_0F3897,
1576   PREFIX_EVEX_0F3898,
1577   PREFIX_EVEX_0F3899,
1578   PREFIX_EVEX_0F389A,
1579   PREFIX_EVEX_0F389B,
1580   PREFIX_EVEX_0F389C,
1581   PREFIX_EVEX_0F389D,
1582   PREFIX_EVEX_0F389E,
1583   PREFIX_EVEX_0F389F,
1584   PREFIX_EVEX_0F38A0,
1585   PREFIX_EVEX_0F38A1,
1586   PREFIX_EVEX_0F38A2,
1587   PREFIX_EVEX_0F38A3,
1588   PREFIX_EVEX_0F38A6,
1589   PREFIX_EVEX_0F38A7,
1590   PREFIX_EVEX_0F38A8,
1591   PREFIX_EVEX_0F38A9,
1592   PREFIX_EVEX_0F38AA,
1593   PREFIX_EVEX_0F38AB,
1594   PREFIX_EVEX_0F38AC,
1595   PREFIX_EVEX_0F38AD,
1596   PREFIX_EVEX_0F38AE,
1597   PREFIX_EVEX_0F38AF,
1598   PREFIX_EVEX_0F38B4,
1599   PREFIX_EVEX_0F38B5,
1600   PREFIX_EVEX_0F38B6,
1601   PREFIX_EVEX_0F38B7,
1602   PREFIX_EVEX_0F38B8,
1603   PREFIX_EVEX_0F38B9,
1604   PREFIX_EVEX_0F38BA,
1605   PREFIX_EVEX_0F38BB,
1606   PREFIX_EVEX_0F38BC,
1607   PREFIX_EVEX_0F38BD,
1608   PREFIX_EVEX_0F38BE,
1609   PREFIX_EVEX_0F38BF,
1610   PREFIX_EVEX_0F38C4,
1611   PREFIX_EVEX_0F38C6_REG_1,
1612   PREFIX_EVEX_0F38C6_REG_2,
1613   PREFIX_EVEX_0F38C6_REG_5,
1614   PREFIX_EVEX_0F38C6_REG_6,
1615   PREFIX_EVEX_0F38C7_REG_1,
1616   PREFIX_EVEX_0F38C7_REG_2,
1617   PREFIX_EVEX_0F38C7_REG_5,
1618   PREFIX_EVEX_0F38C7_REG_6,
1619   PREFIX_EVEX_0F38C8,
1620   PREFIX_EVEX_0F38CA,
1621   PREFIX_EVEX_0F38CB,
1622   PREFIX_EVEX_0F38CC,
1623   PREFIX_EVEX_0F38CD,
1624
1625   PREFIX_EVEX_0F3A00,
1626   PREFIX_EVEX_0F3A01,
1627   PREFIX_EVEX_0F3A03,
1628   PREFIX_EVEX_0F3A04,
1629   PREFIX_EVEX_0F3A05,
1630   PREFIX_EVEX_0F3A08,
1631   PREFIX_EVEX_0F3A09,
1632   PREFIX_EVEX_0F3A0A,
1633   PREFIX_EVEX_0F3A0B,
1634   PREFIX_EVEX_0F3A0F,
1635   PREFIX_EVEX_0F3A14,
1636   PREFIX_EVEX_0F3A15,
1637   PREFIX_EVEX_0F3A16,
1638   PREFIX_EVEX_0F3A17,
1639   PREFIX_EVEX_0F3A18,
1640   PREFIX_EVEX_0F3A19,
1641   PREFIX_EVEX_0F3A1A,
1642   PREFIX_EVEX_0F3A1B,
1643   PREFIX_EVEX_0F3A1D,
1644   PREFIX_EVEX_0F3A1E,
1645   PREFIX_EVEX_0F3A1F,
1646   PREFIX_EVEX_0F3A20,
1647   PREFIX_EVEX_0F3A21,
1648   PREFIX_EVEX_0F3A22,
1649   PREFIX_EVEX_0F3A23,
1650   PREFIX_EVEX_0F3A25,
1651   PREFIX_EVEX_0F3A26,
1652   PREFIX_EVEX_0F3A27,
1653   PREFIX_EVEX_0F3A38,
1654   PREFIX_EVEX_0F3A39,
1655   PREFIX_EVEX_0F3A3A,
1656   PREFIX_EVEX_0F3A3B,
1657   PREFIX_EVEX_0F3A3E,
1658   PREFIX_EVEX_0F3A3F,
1659   PREFIX_EVEX_0F3A42,
1660   PREFIX_EVEX_0F3A43,
1661   PREFIX_EVEX_0F3A50,
1662   PREFIX_EVEX_0F3A51,
1663   PREFIX_EVEX_0F3A54,
1664   PREFIX_EVEX_0F3A55,
1665   PREFIX_EVEX_0F3A56,
1666   PREFIX_EVEX_0F3A57,
1667   PREFIX_EVEX_0F3A66,
1668   PREFIX_EVEX_0F3A67
1669 };
1670
1671 enum
1672 {
1673   X86_64_06 = 0,
1674   X86_64_07,
1675   X86_64_0D,
1676   X86_64_16,
1677   X86_64_17,
1678   X86_64_1E,
1679   X86_64_1F,
1680   X86_64_27,
1681   X86_64_2F,
1682   X86_64_37,
1683   X86_64_3F,
1684   X86_64_60,
1685   X86_64_61,
1686   X86_64_62,
1687   X86_64_63,
1688   X86_64_6D,
1689   X86_64_6F,
1690   X86_64_9A,
1691   X86_64_C4,
1692   X86_64_C5,
1693   X86_64_CE,
1694   X86_64_D4,
1695   X86_64_D5,
1696   X86_64_E8,
1697   X86_64_E9,
1698   X86_64_EA,
1699   X86_64_0F01_REG_0,
1700   X86_64_0F01_REG_1,
1701   X86_64_0F01_REG_2,
1702   X86_64_0F01_REG_3
1703 };
1704
1705 enum
1706 {
1707   THREE_BYTE_0F38 = 0,
1708   THREE_BYTE_0F3A,
1709   THREE_BYTE_0F7A
1710 };
1711
1712 enum
1713 {
1714   XOP_08 = 0,
1715   XOP_09,
1716   XOP_0A
1717 };
1718
1719 enum
1720 {
1721   VEX_0F = 0,
1722   VEX_0F38,
1723   VEX_0F3A
1724 };
1725
1726 enum
1727 {
1728   EVEX_0F = 0,
1729   EVEX_0F38,
1730   EVEX_0F3A
1731 };
1732
1733 enum
1734 {
1735   VEX_LEN_0F10_P_1 = 0,
1736   VEX_LEN_0F10_P_3,
1737   VEX_LEN_0F11_P_1,
1738   VEX_LEN_0F11_P_3,
1739   VEX_LEN_0F12_P_0_M_0,
1740   VEX_LEN_0F12_P_0_M_1,
1741   VEX_LEN_0F12_P_2,
1742   VEX_LEN_0F13_M_0,
1743   VEX_LEN_0F16_P_0_M_0,
1744   VEX_LEN_0F16_P_0_M_1,
1745   VEX_LEN_0F16_P_2,
1746   VEX_LEN_0F17_M_0,
1747   VEX_LEN_0F2A_P_1,
1748   VEX_LEN_0F2A_P_3,
1749   VEX_LEN_0F2C_P_1,
1750   VEX_LEN_0F2C_P_3,
1751   VEX_LEN_0F2D_P_1,
1752   VEX_LEN_0F2D_P_3,
1753   VEX_LEN_0F2E_P_0,
1754   VEX_LEN_0F2E_P_2,
1755   VEX_LEN_0F2F_P_0,
1756   VEX_LEN_0F2F_P_2,
1757   VEX_LEN_0F41_P_0,
1758   VEX_LEN_0F41_P_2,
1759   VEX_LEN_0F42_P_0,
1760   VEX_LEN_0F42_P_2,
1761   VEX_LEN_0F44_P_0,
1762   VEX_LEN_0F44_P_2,
1763   VEX_LEN_0F45_P_0,
1764   VEX_LEN_0F45_P_2,
1765   VEX_LEN_0F46_P_0,
1766   VEX_LEN_0F46_P_2,
1767   VEX_LEN_0F47_P_0,
1768   VEX_LEN_0F47_P_2,
1769   VEX_LEN_0F4A_P_0,
1770   VEX_LEN_0F4A_P_2,
1771   VEX_LEN_0F4B_P_0,
1772   VEX_LEN_0F4B_P_2,
1773   VEX_LEN_0F51_P_1,
1774   VEX_LEN_0F51_P_3,
1775   VEX_LEN_0F52_P_1,
1776   VEX_LEN_0F53_P_1,
1777   VEX_LEN_0F58_P_1,
1778   VEX_LEN_0F58_P_3,
1779   VEX_LEN_0F59_P_1,
1780   VEX_LEN_0F59_P_3,
1781   VEX_LEN_0F5A_P_1,
1782   VEX_LEN_0F5A_P_3,
1783   VEX_LEN_0F5C_P_1,
1784   VEX_LEN_0F5C_P_3,
1785   VEX_LEN_0F5D_P_1,
1786   VEX_LEN_0F5D_P_3,
1787   VEX_LEN_0F5E_P_1,
1788   VEX_LEN_0F5E_P_3,
1789   VEX_LEN_0F5F_P_1,
1790   VEX_LEN_0F5F_P_3,
1791   VEX_LEN_0F6E_P_2,
1792   VEX_LEN_0F7E_P_1,
1793   VEX_LEN_0F7E_P_2,
1794   VEX_LEN_0F90_P_0,
1795   VEX_LEN_0F90_P_2,
1796   VEX_LEN_0F91_P_0,
1797   VEX_LEN_0F91_P_2,
1798   VEX_LEN_0F92_P_0,
1799   VEX_LEN_0F92_P_2,
1800   VEX_LEN_0F92_P_3,
1801   VEX_LEN_0F93_P_0,
1802   VEX_LEN_0F93_P_2,
1803   VEX_LEN_0F93_P_3,
1804   VEX_LEN_0F98_P_0,
1805   VEX_LEN_0F98_P_2,
1806   VEX_LEN_0F99_P_0,
1807   VEX_LEN_0F99_P_2,
1808   VEX_LEN_0FAE_R_2_M_0,
1809   VEX_LEN_0FAE_R_3_M_0,
1810   VEX_LEN_0FC2_P_1,
1811   VEX_LEN_0FC2_P_3,
1812   VEX_LEN_0FC4_P_2,
1813   VEX_LEN_0FC5_P_2,
1814   VEX_LEN_0FD6_P_2,
1815   VEX_LEN_0FF7_P_2,
1816   VEX_LEN_0F3816_P_2,
1817   VEX_LEN_0F3819_P_2,
1818   VEX_LEN_0F381A_P_2_M_0,
1819   VEX_LEN_0F3836_P_2,
1820   VEX_LEN_0F3841_P_2,
1821   VEX_LEN_0F385A_P_2_M_0,
1822   VEX_LEN_0F38DB_P_2,
1823   VEX_LEN_0F38DC_P_2,
1824   VEX_LEN_0F38DD_P_2,
1825   VEX_LEN_0F38DE_P_2,
1826   VEX_LEN_0F38DF_P_2,
1827   VEX_LEN_0F38F2_P_0,
1828   VEX_LEN_0F38F3_R_1_P_0,
1829   VEX_LEN_0F38F3_R_2_P_0,
1830   VEX_LEN_0F38F3_R_3_P_0,
1831   VEX_LEN_0F38F5_P_0,
1832   VEX_LEN_0F38F5_P_1,
1833   VEX_LEN_0F38F5_P_3,
1834   VEX_LEN_0F38F6_P_3,
1835   VEX_LEN_0F38F7_P_0,
1836   VEX_LEN_0F38F7_P_1,
1837   VEX_LEN_0F38F7_P_2,
1838   VEX_LEN_0F38F7_P_3,
1839   VEX_LEN_0F3A00_P_2,
1840   VEX_LEN_0F3A01_P_2,
1841   VEX_LEN_0F3A06_P_2,
1842   VEX_LEN_0F3A0A_P_2,
1843   VEX_LEN_0F3A0B_P_2,
1844   VEX_LEN_0F3A14_P_2,
1845   VEX_LEN_0F3A15_P_2,
1846   VEX_LEN_0F3A16_P_2,
1847   VEX_LEN_0F3A17_P_2,
1848   VEX_LEN_0F3A18_P_2,
1849   VEX_LEN_0F3A19_P_2,
1850   VEX_LEN_0F3A20_P_2,
1851   VEX_LEN_0F3A21_P_2,
1852   VEX_LEN_0F3A22_P_2,
1853   VEX_LEN_0F3A30_P_2,
1854   VEX_LEN_0F3A31_P_2,
1855   VEX_LEN_0F3A32_P_2,
1856   VEX_LEN_0F3A33_P_2,
1857   VEX_LEN_0F3A38_P_2,
1858   VEX_LEN_0F3A39_P_2,
1859   VEX_LEN_0F3A41_P_2,
1860   VEX_LEN_0F3A44_P_2,
1861   VEX_LEN_0F3A46_P_2,
1862   VEX_LEN_0F3A60_P_2,
1863   VEX_LEN_0F3A61_P_2,
1864   VEX_LEN_0F3A62_P_2,
1865   VEX_LEN_0F3A63_P_2,
1866   VEX_LEN_0F3A6A_P_2,
1867   VEX_LEN_0F3A6B_P_2,
1868   VEX_LEN_0F3A6E_P_2,
1869   VEX_LEN_0F3A6F_P_2,
1870   VEX_LEN_0F3A7A_P_2,
1871   VEX_LEN_0F3A7B_P_2,
1872   VEX_LEN_0F3A7E_P_2,
1873   VEX_LEN_0F3A7F_P_2,
1874   VEX_LEN_0F3ADF_P_2,
1875   VEX_LEN_0F3AF0_P_3,
1876   VEX_LEN_0FXOP_08_CC,
1877   VEX_LEN_0FXOP_08_CD,
1878   VEX_LEN_0FXOP_08_CE,
1879   VEX_LEN_0FXOP_08_CF,
1880   VEX_LEN_0FXOP_08_EC,
1881   VEX_LEN_0FXOP_08_ED,
1882   VEX_LEN_0FXOP_08_EE,
1883   VEX_LEN_0FXOP_08_EF,
1884   VEX_LEN_0FXOP_09_80,
1885   VEX_LEN_0FXOP_09_81
1886 };
1887
1888 enum
1889 {
1890   VEX_W_0F10_P_0 = 0,
1891   VEX_W_0F10_P_1,
1892   VEX_W_0F10_P_2,
1893   VEX_W_0F10_P_3,
1894   VEX_W_0F11_P_0,
1895   VEX_W_0F11_P_1,
1896   VEX_W_0F11_P_2,
1897   VEX_W_0F11_P_3,
1898   VEX_W_0F12_P_0_M_0,
1899   VEX_W_0F12_P_0_M_1,
1900   VEX_W_0F12_P_1,
1901   VEX_W_0F12_P_2,
1902   VEX_W_0F12_P_3,
1903   VEX_W_0F13_M_0,
1904   VEX_W_0F14,
1905   VEX_W_0F15,
1906   VEX_W_0F16_P_0_M_0,
1907   VEX_W_0F16_P_0_M_1,
1908   VEX_W_0F16_P_1,
1909   VEX_W_0F16_P_2,
1910   VEX_W_0F17_M_0,
1911   VEX_W_0F28,
1912   VEX_W_0F29,
1913   VEX_W_0F2B_M_0,
1914   VEX_W_0F2E_P_0,
1915   VEX_W_0F2E_P_2,
1916   VEX_W_0F2F_P_0,
1917   VEX_W_0F2F_P_2,
1918   VEX_W_0F41_P_0_LEN_1,
1919   VEX_W_0F41_P_2_LEN_1,
1920   VEX_W_0F42_P_0_LEN_1,
1921   VEX_W_0F42_P_2_LEN_1,
1922   VEX_W_0F44_P_0_LEN_0,
1923   VEX_W_0F44_P_2_LEN_0,
1924   VEX_W_0F45_P_0_LEN_1,
1925   VEX_W_0F45_P_2_LEN_1,
1926   VEX_W_0F46_P_0_LEN_1,
1927   VEX_W_0F46_P_2_LEN_1,
1928   VEX_W_0F47_P_0_LEN_1,
1929   VEX_W_0F47_P_2_LEN_1,
1930   VEX_W_0F4A_P_0_LEN_1,
1931   VEX_W_0F4A_P_2_LEN_1,
1932   VEX_W_0F4B_P_0_LEN_1,
1933   VEX_W_0F4B_P_2_LEN_1,
1934   VEX_W_0F50_M_0,
1935   VEX_W_0F51_P_0,
1936   VEX_W_0F51_P_1,
1937   VEX_W_0F51_P_2,
1938   VEX_W_0F51_P_3,
1939   VEX_W_0F52_P_0,
1940   VEX_W_0F52_P_1,
1941   VEX_W_0F53_P_0,
1942   VEX_W_0F53_P_1,
1943   VEX_W_0F58_P_0,
1944   VEX_W_0F58_P_1,
1945   VEX_W_0F58_P_2,
1946   VEX_W_0F58_P_3,
1947   VEX_W_0F59_P_0,
1948   VEX_W_0F59_P_1,
1949   VEX_W_0F59_P_2,
1950   VEX_W_0F59_P_3,
1951   VEX_W_0F5A_P_0,
1952   VEX_W_0F5A_P_1,
1953   VEX_W_0F5A_P_3,
1954   VEX_W_0F5B_P_0,
1955   VEX_W_0F5B_P_1,
1956   VEX_W_0F5B_P_2,
1957   VEX_W_0F5C_P_0,
1958   VEX_W_0F5C_P_1,
1959   VEX_W_0F5C_P_2,
1960   VEX_W_0F5C_P_3,
1961   VEX_W_0F5D_P_0,
1962   VEX_W_0F5D_P_1,
1963   VEX_W_0F5D_P_2,
1964   VEX_W_0F5D_P_3,
1965   VEX_W_0F5E_P_0,
1966   VEX_W_0F5E_P_1,
1967   VEX_W_0F5E_P_2,
1968   VEX_W_0F5E_P_3,
1969   VEX_W_0F5F_P_0,
1970   VEX_W_0F5F_P_1,
1971   VEX_W_0F5F_P_2,
1972   VEX_W_0F5F_P_3,
1973   VEX_W_0F60_P_2,
1974   VEX_W_0F61_P_2,
1975   VEX_W_0F62_P_2,
1976   VEX_W_0F63_P_2,
1977   VEX_W_0F64_P_2,
1978   VEX_W_0F65_P_2,
1979   VEX_W_0F66_P_2,
1980   VEX_W_0F67_P_2,
1981   VEX_W_0F68_P_2,
1982   VEX_W_0F69_P_2,
1983   VEX_W_0F6A_P_2,
1984   VEX_W_0F6B_P_2,
1985   VEX_W_0F6C_P_2,
1986   VEX_W_0F6D_P_2,
1987   VEX_W_0F6F_P_1,
1988   VEX_W_0F6F_P_2,
1989   VEX_W_0F70_P_1,
1990   VEX_W_0F70_P_2,
1991   VEX_W_0F70_P_3,
1992   VEX_W_0F71_R_2_P_2,
1993   VEX_W_0F71_R_4_P_2,
1994   VEX_W_0F71_R_6_P_2,
1995   VEX_W_0F72_R_2_P_2,
1996   VEX_W_0F72_R_4_P_2,
1997   VEX_W_0F72_R_6_P_2,
1998   VEX_W_0F73_R_2_P_2,
1999   VEX_W_0F73_R_3_P_2,
2000   VEX_W_0F73_R_6_P_2,
2001   VEX_W_0F73_R_7_P_2,
2002   VEX_W_0F74_P_2,
2003   VEX_W_0F75_P_2,
2004   VEX_W_0F76_P_2,
2005   VEX_W_0F77_P_0,
2006   VEX_W_0F7C_P_2,
2007   VEX_W_0F7C_P_3,
2008   VEX_W_0F7D_P_2,
2009   VEX_W_0F7D_P_3,
2010   VEX_W_0F7E_P_1,
2011   VEX_W_0F7F_P_1,
2012   VEX_W_0F7F_P_2,
2013   VEX_W_0F90_P_0_LEN_0,
2014   VEX_W_0F90_P_2_LEN_0,
2015   VEX_W_0F91_P_0_LEN_0,
2016   VEX_W_0F91_P_2_LEN_0,
2017   VEX_W_0F92_P_0_LEN_0,
2018   VEX_W_0F92_P_2_LEN_0,
2019   VEX_W_0F92_P_3_LEN_0,
2020   VEX_W_0F93_P_0_LEN_0,
2021   VEX_W_0F93_P_2_LEN_0,
2022   VEX_W_0F93_P_3_LEN_0,
2023   VEX_W_0F98_P_0_LEN_0,
2024   VEX_W_0F98_P_2_LEN_0,
2025   VEX_W_0F99_P_0_LEN_0,
2026   VEX_W_0F99_P_2_LEN_0,
2027   VEX_W_0FAE_R_2_M_0,
2028   VEX_W_0FAE_R_3_M_0,
2029   VEX_W_0FC2_P_0,
2030   VEX_W_0FC2_P_1,
2031   VEX_W_0FC2_P_2,
2032   VEX_W_0FC2_P_3,
2033   VEX_W_0FC4_P_2,
2034   VEX_W_0FC5_P_2,
2035   VEX_W_0FD0_P_2,
2036   VEX_W_0FD0_P_3,
2037   VEX_W_0FD1_P_2,
2038   VEX_W_0FD2_P_2,
2039   VEX_W_0FD3_P_2,
2040   VEX_W_0FD4_P_2,
2041   VEX_W_0FD5_P_2,
2042   VEX_W_0FD6_P_2,
2043   VEX_W_0FD7_P_2_M_1,
2044   VEX_W_0FD8_P_2,
2045   VEX_W_0FD9_P_2,
2046   VEX_W_0FDA_P_2,
2047   VEX_W_0FDB_P_2,
2048   VEX_W_0FDC_P_2,
2049   VEX_W_0FDD_P_2,
2050   VEX_W_0FDE_P_2,
2051   VEX_W_0FDF_P_2,
2052   VEX_W_0FE0_P_2,
2053   VEX_W_0FE1_P_2,
2054   VEX_W_0FE2_P_2,
2055   VEX_W_0FE3_P_2,
2056   VEX_W_0FE4_P_2,
2057   VEX_W_0FE5_P_2,
2058   VEX_W_0FE6_P_1,
2059   VEX_W_0FE6_P_2,
2060   VEX_W_0FE6_P_3,
2061   VEX_W_0FE7_P_2_M_0,
2062   VEX_W_0FE8_P_2,
2063   VEX_W_0FE9_P_2,
2064   VEX_W_0FEA_P_2,
2065   VEX_W_0FEB_P_2,
2066   VEX_W_0FEC_P_2,
2067   VEX_W_0FED_P_2,
2068   VEX_W_0FEE_P_2,
2069   VEX_W_0FEF_P_2,
2070   VEX_W_0FF0_P_3_M_0,
2071   VEX_W_0FF1_P_2,
2072   VEX_W_0FF2_P_2,
2073   VEX_W_0FF3_P_2,
2074   VEX_W_0FF4_P_2,
2075   VEX_W_0FF5_P_2,
2076   VEX_W_0FF6_P_2,
2077   VEX_W_0FF7_P_2,
2078   VEX_W_0FF8_P_2,
2079   VEX_W_0FF9_P_2,
2080   VEX_W_0FFA_P_2,
2081   VEX_W_0FFB_P_2,
2082   VEX_W_0FFC_P_2,
2083   VEX_W_0FFD_P_2,
2084   VEX_W_0FFE_P_2,
2085   VEX_W_0F3800_P_2,
2086   VEX_W_0F3801_P_2,
2087   VEX_W_0F3802_P_2,
2088   VEX_W_0F3803_P_2,
2089   VEX_W_0F3804_P_2,
2090   VEX_W_0F3805_P_2,
2091   VEX_W_0F3806_P_2,
2092   VEX_W_0F3807_P_2,
2093   VEX_W_0F3808_P_2,
2094   VEX_W_0F3809_P_2,
2095   VEX_W_0F380A_P_2,
2096   VEX_W_0F380B_P_2,
2097   VEX_W_0F380C_P_2,
2098   VEX_W_0F380D_P_2,
2099   VEX_W_0F380E_P_2,
2100   VEX_W_0F380F_P_2,
2101   VEX_W_0F3816_P_2,
2102   VEX_W_0F3817_P_2,
2103   VEX_W_0F3818_P_2,
2104   VEX_W_0F3819_P_2,
2105   VEX_W_0F381A_P_2_M_0,
2106   VEX_W_0F381C_P_2,
2107   VEX_W_0F381D_P_2,
2108   VEX_W_0F381E_P_2,
2109   VEX_W_0F3820_P_2,
2110   VEX_W_0F3821_P_2,
2111   VEX_W_0F3822_P_2,
2112   VEX_W_0F3823_P_2,
2113   VEX_W_0F3824_P_2,
2114   VEX_W_0F3825_P_2,
2115   VEX_W_0F3828_P_2,
2116   VEX_W_0F3829_P_2,
2117   VEX_W_0F382A_P_2_M_0,
2118   VEX_W_0F382B_P_2,
2119   VEX_W_0F382C_P_2_M_0,
2120   VEX_W_0F382D_P_2_M_0,
2121   VEX_W_0F382E_P_2_M_0,
2122   VEX_W_0F382F_P_2_M_0,
2123   VEX_W_0F3830_P_2,
2124   VEX_W_0F3831_P_2,
2125   VEX_W_0F3832_P_2,
2126   VEX_W_0F3833_P_2,
2127   VEX_W_0F3834_P_2,
2128   VEX_W_0F3835_P_2,
2129   VEX_W_0F3836_P_2,
2130   VEX_W_0F3837_P_2,
2131   VEX_W_0F3838_P_2,
2132   VEX_W_0F3839_P_2,
2133   VEX_W_0F383A_P_2,
2134   VEX_W_0F383B_P_2,
2135   VEX_W_0F383C_P_2,
2136   VEX_W_0F383D_P_2,
2137   VEX_W_0F383E_P_2,
2138   VEX_W_0F383F_P_2,
2139   VEX_W_0F3840_P_2,
2140   VEX_W_0F3841_P_2,
2141   VEX_W_0F3846_P_2,
2142   VEX_W_0F3858_P_2,
2143   VEX_W_0F3859_P_2,
2144   VEX_W_0F385A_P_2_M_0,
2145   VEX_W_0F3878_P_2,
2146   VEX_W_0F3879_P_2,
2147   VEX_W_0F38DB_P_2,
2148   VEX_W_0F38DC_P_2,
2149   VEX_W_0F38DD_P_2,
2150   VEX_W_0F38DE_P_2,
2151   VEX_W_0F38DF_P_2,
2152   VEX_W_0F3A00_P_2,
2153   VEX_W_0F3A01_P_2,
2154   VEX_W_0F3A02_P_2,
2155   VEX_W_0F3A04_P_2,
2156   VEX_W_0F3A05_P_2,
2157   VEX_W_0F3A06_P_2,
2158   VEX_W_0F3A08_P_2,
2159   VEX_W_0F3A09_P_2,
2160   VEX_W_0F3A0A_P_2,
2161   VEX_W_0F3A0B_P_2,
2162   VEX_W_0F3A0C_P_2,
2163   VEX_W_0F3A0D_P_2,
2164   VEX_W_0F3A0E_P_2,
2165   VEX_W_0F3A0F_P_2,
2166   VEX_W_0F3A14_P_2,
2167   VEX_W_0F3A15_P_2,
2168   VEX_W_0F3A18_P_2,
2169   VEX_W_0F3A19_P_2,
2170   VEX_W_0F3A20_P_2,
2171   VEX_W_0F3A21_P_2,
2172   VEX_W_0F3A30_P_2_LEN_0,
2173   VEX_W_0F3A31_P_2_LEN_0,
2174   VEX_W_0F3A32_P_2_LEN_0,
2175   VEX_W_0F3A33_P_2_LEN_0,
2176   VEX_W_0F3A38_P_2,
2177   VEX_W_0F3A39_P_2,
2178   VEX_W_0F3A40_P_2,
2179   VEX_W_0F3A41_P_2,
2180   VEX_W_0F3A42_P_2,
2181   VEX_W_0F3A44_P_2,
2182   VEX_W_0F3A46_P_2,
2183   VEX_W_0F3A48_P_2,
2184   VEX_W_0F3A49_P_2,
2185   VEX_W_0F3A4A_P_2,
2186   VEX_W_0F3A4B_P_2,
2187   VEX_W_0F3A4C_P_2,
2188   VEX_W_0F3A60_P_2,
2189   VEX_W_0F3A61_P_2,
2190   VEX_W_0F3A62_P_2,
2191   VEX_W_0F3A63_P_2,
2192   VEX_W_0F3ADF_P_2,
2193
2194   EVEX_W_0F10_P_0,
2195   EVEX_W_0F10_P_1_M_0,
2196   EVEX_W_0F10_P_1_M_1,
2197   EVEX_W_0F10_P_2,
2198   EVEX_W_0F10_P_3_M_0,
2199   EVEX_W_0F10_P_3_M_1,
2200   EVEX_W_0F11_P_0,
2201   EVEX_W_0F11_P_1_M_0,
2202   EVEX_W_0F11_P_1_M_1,
2203   EVEX_W_0F11_P_2,
2204   EVEX_W_0F11_P_3_M_0,
2205   EVEX_W_0F11_P_3_M_1,
2206   EVEX_W_0F12_P_0_M_0,
2207   EVEX_W_0F12_P_0_M_1,
2208   EVEX_W_0F12_P_1,
2209   EVEX_W_0F12_P_2,
2210   EVEX_W_0F12_P_3,
2211   EVEX_W_0F13_P_0,
2212   EVEX_W_0F13_P_2,
2213   EVEX_W_0F14_P_0,
2214   EVEX_W_0F14_P_2,
2215   EVEX_W_0F15_P_0,
2216   EVEX_W_0F15_P_2,
2217   EVEX_W_0F16_P_0_M_0,
2218   EVEX_W_0F16_P_0_M_1,
2219   EVEX_W_0F16_P_1,
2220   EVEX_W_0F16_P_2,
2221   EVEX_W_0F17_P_0,
2222   EVEX_W_0F17_P_2,
2223   EVEX_W_0F28_P_0,
2224   EVEX_W_0F28_P_2,
2225   EVEX_W_0F29_P_0,
2226   EVEX_W_0F29_P_2,
2227   EVEX_W_0F2A_P_1,
2228   EVEX_W_0F2A_P_3,
2229   EVEX_W_0F2B_P_0,
2230   EVEX_W_0F2B_P_2,
2231   EVEX_W_0F2E_P_0,
2232   EVEX_W_0F2E_P_2,
2233   EVEX_W_0F2F_P_0,
2234   EVEX_W_0F2F_P_2,
2235   EVEX_W_0F51_P_0,
2236   EVEX_W_0F51_P_1,
2237   EVEX_W_0F51_P_2,
2238   EVEX_W_0F51_P_3,
2239   EVEX_W_0F54_P_0,
2240   EVEX_W_0F54_P_2,
2241   EVEX_W_0F55_P_0,
2242   EVEX_W_0F55_P_2,
2243   EVEX_W_0F56_P_0,
2244   EVEX_W_0F56_P_2,
2245   EVEX_W_0F57_P_0,
2246   EVEX_W_0F57_P_2,
2247   EVEX_W_0F58_P_0,
2248   EVEX_W_0F58_P_1,
2249   EVEX_W_0F58_P_2,
2250   EVEX_W_0F58_P_3,
2251   EVEX_W_0F59_P_0,
2252   EVEX_W_0F59_P_1,
2253   EVEX_W_0F59_P_2,
2254   EVEX_W_0F59_P_3,
2255   EVEX_W_0F5A_P_0,
2256   EVEX_W_0F5A_P_1,
2257   EVEX_W_0F5A_P_2,
2258   EVEX_W_0F5A_P_3,
2259   EVEX_W_0F5B_P_0,
2260   EVEX_W_0F5B_P_1,
2261   EVEX_W_0F5B_P_2,
2262   EVEX_W_0F5C_P_0,
2263   EVEX_W_0F5C_P_1,
2264   EVEX_W_0F5C_P_2,
2265   EVEX_W_0F5C_P_3,
2266   EVEX_W_0F5D_P_0,
2267   EVEX_W_0F5D_P_1,
2268   EVEX_W_0F5D_P_2,
2269   EVEX_W_0F5D_P_3,
2270   EVEX_W_0F5E_P_0,
2271   EVEX_W_0F5E_P_1,
2272   EVEX_W_0F5E_P_2,
2273   EVEX_W_0F5E_P_3,
2274   EVEX_W_0F5F_P_0,
2275   EVEX_W_0F5F_P_1,
2276   EVEX_W_0F5F_P_2,
2277   EVEX_W_0F5F_P_3,
2278   EVEX_W_0F62_P_2,
2279   EVEX_W_0F66_P_2,
2280   EVEX_W_0F6A_P_2,
2281   EVEX_W_0F6B_P_2,
2282   EVEX_W_0F6C_P_2,
2283   EVEX_W_0F6D_P_2,
2284   EVEX_W_0F6E_P_2,
2285   EVEX_W_0F6F_P_1,
2286   EVEX_W_0F6F_P_2,
2287   EVEX_W_0F6F_P_3,
2288   EVEX_W_0F70_P_2,
2289   EVEX_W_0F72_R_2_P_2,
2290   EVEX_W_0F72_R_6_P_2,
2291   EVEX_W_0F73_R_2_P_2,
2292   EVEX_W_0F73_R_6_P_2,
2293   EVEX_W_0F76_P_2,
2294   EVEX_W_0F78_P_0,
2295   EVEX_W_0F78_P_2,
2296   EVEX_W_0F79_P_0,
2297   EVEX_W_0F79_P_2,
2298   EVEX_W_0F7A_P_1,
2299   EVEX_W_0F7A_P_2,
2300   EVEX_W_0F7A_P_3,
2301   EVEX_W_0F7B_P_1,
2302   EVEX_W_0F7B_P_2,
2303   EVEX_W_0F7B_P_3,
2304   EVEX_W_0F7E_P_1,
2305   EVEX_W_0F7E_P_2,
2306   EVEX_W_0F7F_P_1,
2307   EVEX_W_0F7F_P_2,
2308   EVEX_W_0F7F_P_3,
2309   EVEX_W_0FC2_P_0,
2310   EVEX_W_0FC2_P_1,
2311   EVEX_W_0FC2_P_2,
2312   EVEX_W_0FC2_P_3,
2313   EVEX_W_0FC6_P_0,
2314   EVEX_W_0FC6_P_2,
2315   EVEX_W_0FD2_P_2,
2316   EVEX_W_0FD3_P_2,
2317   EVEX_W_0FD4_P_2,
2318   EVEX_W_0FD6_P_2,
2319   EVEX_W_0FE6_P_1,
2320   EVEX_W_0FE6_P_2,
2321   EVEX_W_0FE6_P_3,
2322   EVEX_W_0FE7_P_2,
2323   EVEX_W_0FF2_P_2,
2324   EVEX_W_0FF3_P_2,
2325   EVEX_W_0FF4_P_2,
2326   EVEX_W_0FFA_P_2,
2327   EVEX_W_0FFB_P_2,
2328   EVEX_W_0FFE_P_2,
2329   EVEX_W_0F380C_P_2,
2330   EVEX_W_0F380D_P_2,
2331   EVEX_W_0F3810_P_1,
2332   EVEX_W_0F3810_P_2,
2333   EVEX_W_0F3811_P_1,
2334   EVEX_W_0F3811_P_2,
2335   EVEX_W_0F3812_P_1,
2336   EVEX_W_0F3812_P_2,
2337   EVEX_W_0F3813_P_1,
2338   EVEX_W_0F3813_P_2,
2339   EVEX_W_0F3814_P_1,
2340   EVEX_W_0F3815_P_1,
2341   EVEX_W_0F3818_P_2,
2342   EVEX_W_0F3819_P_2,
2343   EVEX_W_0F381A_P_2,
2344   EVEX_W_0F381B_P_2,
2345   EVEX_W_0F381E_P_2,
2346   EVEX_W_0F381F_P_2,
2347   EVEX_W_0F3820_P_1,
2348   EVEX_W_0F3821_P_1,
2349   EVEX_W_0F3822_P_1,
2350   EVEX_W_0F3823_P_1,
2351   EVEX_W_0F3824_P_1,
2352   EVEX_W_0F3825_P_1,
2353   EVEX_W_0F3825_P_2,
2354   EVEX_W_0F3826_P_1,
2355   EVEX_W_0F3826_P_2,
2356   EVEX_W_0F3828_P_1,
2357   EVEX_W_0F3828_P_2,
2358   EVEX_W_0F3829_P_1,
2359   EVEX_W_0F3829_P_2,
2360   EVEX_W_0F382A_P_1,
2361   EVEX_W_0F382A_P_2,
2362   EVEX_W_0F382B_P_2,
2363   EVEX_W_0F3830_P_1,
2364   EVEX_W_0F3831_P_1,
2365   EVEX_W_0F3832_P_1,
2366   EVEX_W_0F3833_P_1,
2367   EVEX_W_0F3834_P_1,
2368   EVEX_W_0F3835_P_1,
2369   EVEX_W_0F3835_P_2,
2370   EVEX_W_0F3837_P_2,
2371   EVEX_W_0F3838_P_1,
2372   EVEX_W_0F3839_P_1,
2373   EVEX_W_0F383A_P_1,
2374   EVEX_W_0F3840_P_2,
2375   EVEX_W_0F3858_P_2,
2376   EVEX_W_0F3859_P_2,
2377   EVEX_W_0F385A_P_2,
2378   EVEX_W_0F385B_P_2,
2379   EVEX_W_0F3866_P_2,
2380   EVEX_W_0F3875_P_2,
2381   EVEX_W_0F3878_P_2,
2382   EVEX_W_0F3879_P_2,
2383   EVEX_W_0F387A_P_2,
2384   EVEX_W_0F387B_P_2,
2385   EVEX_W_0F387D_P_2,
2386   EVEX_W_0F3883_P_2,
2387   EVEX_W_0F388D_P_2,
2388   EVEX_W_0F3891_P_2,
2389   EVEX_W_0F3893_P_2,
2390   EVEX_W_0F38A1_P_2,
2391   EVEX_W_0F38A3_P_2,
2392   EVEX_W_0F38C7_R_1_P_2,
2393   EVEX_W_0F38C7_R_2_P_2,
2394   EVEX_W_0F38C7_R_5_P_2,
2395   EVEX_W_0F38C7_R_6_P_2,
2396
2397   EVEX_W_0F3A00_P_2,
2398   EVEX_W_0F3A01_P_2,
2399   EVEX_W_0F3A04_P_2,
2400   EVEX_W_0F3A05_P_2,
2401   EVEX_W_0F3A08_P_2,
2402   EVEX_W_0F3A09_P_2,
2403   EVEX_W_0F3A0A_P_2,
2404   EVEX_W_0F3A0B_P_2,
2405   EVEX_W_0F3A16_P_2,
2406   EVEX_W_0F3A18_P_2,
2407   EVEX_W_0F3A19_P_2,
2408   EVEX_W_0F3A1A_P_2,
2409   EVEX_W_0F3A1B_P_2,
2410   EVEX_W_0F3A1D_P_2,
2411   EVEX_W_0F3A21_P_2,
2412   EVEX_W_0F3A22_P_2,
2413   EVEX_W_0F3A23_P_2,
2414   EVEX_W_0F3A38_P_2,
2415   EVEX_W_0F3A39_P_2,
2416   EVEX_W_0F3A3A_P_2,
2417   EVEX_W_0F3A3B_P_2,
2418   EVEX_W_0F3A3E_P_2,
2419   EVEX_W_0F3A3F_P_2,
2420   EVEX_W_0F3A42_P_2,
2421   EVEX_W_0F3A43_P_2,
2422   EVEX_W_0F3A50_P_2,
2423   EVEX_W_0F3A51_P_2,
2424   EVEX_W_0F3A56_P_2,
2425   EVEX_W_0F3A57_P_2,
2426   EVEX_W_0F3A66_P_2,
2427   EVEX_W_0F3A67_P_2
2428 };
2429
2430 typedef void (*op_rtn) (int bytemode, int sizeflag);
2431
2432 struct dis386 {
2433   const char *name;
2434   struct
2435     {
2436       op_rtn rtn;
2437       int bytemode;
2438     } op[MAX_OPERANDS];
2439   unsigned int prefix_requirement;
2440 };
2441
2442 /* Upper case letters in the instruction names here are macros.
2443    'A' => print 'b' if no register operands or suffix_always is true
2444    'B' => print 'b' if suffix_always is true
2445    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2446           size prefix
2447    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2448           suffix_always is true
2449    'E' => print 'e' if 32-bit form of jcxz
2450    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2451    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2452    'H' => print ",pt" or ",pn" branch hint
2453    'I' => honor following macro letter even in Intel mode (implemented only
2454           for some of the macro letters)
2455    'J' => print 'l'
2456    'K' => print 'd' or 'q' if rex prefix is present.
2457    'L' => print 'l' if suffix_always is true
2458    'M' => print 'r' if intel_mnemonic is false.
2459    'N' => print 'n' if instruction has no wait "prefix"
2460    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2461    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2462           or suffix_always is true.  print 'q' if rex prefix is present.
2463    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2464           is true
2465    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2466    'S' => print 'w', 'l' or 'q' if suffix_always is true
2467    'T' => print 'q' in 64bit mode if instruction has no operand size
2468           prefix and behave as 'P' otherwise
2469    'U' => print 'q' in 64bit mode if instruction has no operand size
2470           prefix and behave as 'Q' otherwise
2471    'V' => print 'q' in 64bit mode if instruction has no operand size
2472           prefix and behave as 'S' otherwise
2473    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2474    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2475    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2476           suffix_always is true.
2477    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2478    '!' => change condition from true to false or from false to true.
2479    '%' => add 1 upper case letter to the macro.
2480    '^' => print 'w' or 'l' depending on operand size prefix or
2481           suffix_always is true (lcall/ljmp).
2482    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2483           on operand size prefix.
2484
2485    2 upper case letter macros:
2486    "XY" => print 'x' or 'y' if suffix_always is true or no register
2487            operands and no broadcast.
2488    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2489            register operands and no broadcast.
2490    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2491    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2492            or suffix_always is true
2493    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2494    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2495    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2496    "LW" => print 'd', 'q' depending on the VEX.W bit
2497    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2498            an operand size prefix, or suffix_always is true.  print
2499            'q' if rex prefix is present.
2500
2501    Many of the above letters print nothing in Intel mode.  See "putop"
2502    for the details.
2503
2504    Braces '{' and '}', and vertical bars '|', indicate alternative
2505    mnemonic strings for AT&T and Intel.  */
2506
2507 static const struct dis386 dis386[] = {
2508   /* 00 */
2509   { "addB",             { Ebh1, Gb }, 0 },
2510   { "addS",             { Evh1, Gv }, 0 },
2511   { "addB",             { Gb, EbS }, 0 },
2512   { "addS",             { Gv, EvS }, 0 },
2513   { "addB",             { AL, Ib }, 0 },
2514   { "addS",             { eAX, Iv }, 0 },
2515   { X86_64_TABLE (X86_64_06) },
2516   { X86_64_TABLE (X86_64_07) },
2517   /* 08 */
2518   { "orB",              { Ebh1, Gb }, 0 },
2519   { "orS",              { Evh1, Gv }, 0 },
2520   { "orB",              { Gb, EbS }, 0 },
2521   { "orS",              { Gv, EvS }, 0 },
2522   { "orB",              { AL, Ib }, 0 },
2523   { "orS",              { eAX, Iv }, 0 },
2524   { X86_64_TABLE (X86_64_0D) },
2525   { Bad_Opcode },       /* 0x0f extended opcode escape */
2526   /* 10 */
2527   { "adcB",             { Ebh1, Gb }, 0 },
2528   { "adcS",             { Evh1, Gv }, 0 },
2529   { "adcB",             { Gb, EbS }, 0 },
2530   { "adcS",             { Gv, EvS }, 0 },
2531   { "adcB",             { AL, Ib }, 0 },
2532   { "adcS",             { eAX, Iv }, 0 },
2533   { X86_64_TABLE (X86_64_16) },
2534   { X86_64_TABLE (X86_64_17) },
2535   /* 18 */
2536   { "sbbB",             { Ebh1, Gb }, 0 },
2537   { "sbbS",             { Evh1, Gv }, 0 },
2538   { "sbbB",             { Gb, EbS }, 0 },
2539   { "sbbS",             { Gv, EvS }, 0 },
2540   { "sbbB",             { AL, Ib }, 0 },
2541   { "sbbS",             { eAX, Iv }, 0 },
2542   { X86_64_TABLE (X86_64_1E) },
2543   { X86_64_TABLE (X86_64_1F) },
2544   /* 20 */
2545   { "andB",             { Ebh1, Gb }, 0 },
2546   { "andS",             { Evh1, Gv }, 0 },
2547   { "andB",             { Gb, EbS }, 0 },
2548   { "andS",             { Gv, EvS }, 0 },
2549   { "andB",             { AL, Ib }, 0 },
2550   { "andS",             { eAX, Iv }, 0 },
2551   { Bad_Opcode },       /* SEG ES prefix */
2552   { X86_64_TABLE (X86_64_27) },
2553   /* 28 */
2554   { "subB",             { Ebh1, Gb }, 0 },
2555   { "subS",             { Evh1, Gv }, 0 },
2556   { "subB",             { Gb, EbS }, 0 },
2557   { "subS",             { Gv, EvS }, 0 },
2558   { "subB",             { AL, Ib }, 0 },
2559   { "subS",             { eAX, Iv }, 0 },
2560   { Bad_Opcode },       /* SEG CS prefix */
2561   { X86_64_TABLE (X86_64_2F) },
2562   /* 30 */
2563   { "xorB",             { Ebh1, Gb }, 0 },
2564   { "xorS",             { Evh1, Gv }, 0 },
2565   { "xorB",             { Gb, EbS }, 0 },
2566   { "xorS",             { Gv, EvS }, 0 },
2567   { "xorB",             { AL, Ib }, 0 },
2568   { "xorS",             { eAX, Iv }, 0 },
2569   { Bad_Opcode },       /* SEG SS prefix */
2570   { X86_64_TABLE (X86_64_37) },
2571   /* 38 */
2572   { "cmpB",             { Eb, Gb }, 0 },
2573   { "cmpS",             { Ev, Gv }, 0 },
2574   { "cmpB",             { Gb, EbS }, 0 },
2575   { "cmpS",             { Gv, EvS }, 0 },
2576   { "cmpB",             { AL, Ib }, 0 },
2577   { "cmpS",             { eAX, Iv }, 0 },
2578   { Bad_Opcode },       /* SEG DS prefix */
2579   { X86_64_TABLE (X86_64_3F) },
2580   /* 40 */
2581   { "inc{S|}",          { RMeAX }, 0 },
2582   { "inc{S|}",          { RMeCX }, 0 },
2583   { "inc{S|}",          { RMeDX }, 0 },
2584   { "inc{S|}",          { RMeBX }, 0 },
2585   { "inc{S|}",          { RMeSP }, 0 },
2586   { "inc{S|}",          { RMeBP }, 0 },
2587   { "inc{S|}",          { RMeSI }, 0 },
2588   { "inc{S|}",          { RMeDI }, 0 },
2589   /* 48 */
2590   { "dec{S|}",          { RMeAX }, 0 },
2591   { "dec{S|}",          { RMeCX }, 0 },
2592   { "dec{S|}",          { RMeDX }, 0 },
2593   { "dec{S|}",          { RMeBX }, 0 },
2594   { "dec{S|}",          { RMeSP }, 0 },
2595   { "dec{S|}",          { RMeBP }, 0 },
2596   { "dec{S|}",          { RMeSI }, 0 },
2597   { "dec{S|}",          { RMeDI }, 0 },
2598   /* 50 */
2599   { "pushV",            { RMrAX }, 0 },
2600   { "pushV",            { RMrCX }, 0 },
2601   { "pushV",            { RMrDX }, 0 },
2602   { "pushV",            { RMrBX }, 0 },
2603   { "pushV",            { RMrSP }, 0 },
2604   { "pushV",            { RMrBP }, 0 },
2605   { "pushV",            { RMrSI }, 0 },
2606   { "pushV",            { RMrDI }, 0 },
2607   /* 58 */
2608   { "popV",             { RMrAX }, 0 },
2609   { "popV",             { RMrCX }, 0 },
2610   { "popV",             { RMrDX }, 0 },
2611   { "popV",             { RMrBX }, 0 },
2612   { "popV",             { RMrSP }, 0 },
2613   { "popV",             { RMrBP }, 0 },
2614   { "popV",             { RMrSI }, 0 },
2615   { "popV",             { RMrDI }, 0 },
2616   /* 60 */
2617   { X86_64_TABLE (X86_64_60) },
2618   { X86_64_TABLE (X86_64_61) },
2619   { X86_64_TABLE (X86_64_62) },
2620   { X86_64_TABLE (X86_64_63) },
2621   { Bad_Opcode },       /* seg fs */
2622   { Bad_Opcode },       /* seg gs */
2623   { Bad_Opcode },       /* op size prefix */
2624   { Bad_Opcode },       /* adr size prefix */
2625   /* 68 */
2626   { "pushT",            { sIv }, 0 },
2627   { "imulS",            { Gv, Ev, Iv }, 0 },
2628   { "pushT",            { sIbT }, 0 },
2629   { "imulS",            { Gv, Ev, sIb }, 0 },
2630   { "ins{b|}",          { Ybr, indirDX }, 0 },
2631   { X86_64_TABLE (X86_64_6D) },
2632   { "outs{b|}",         { indirDXr, Xb }, 0 },
2633   { X86_64_TABLE (X86_64_6F) },
2634   /* 70 */
2635   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2636   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2637   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2638   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2639   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2640   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2641   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2642   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2643   /* 78 */
2644   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2645   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2646   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2647   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2648   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2649   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2650   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2651   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2652   /* 80 */
2653   { REG_TABLE (REG_80) },
2654   { REG_TABLE (REG_81) },
2655   { Bad_Opcode },
2656   { REG_TABLE (REG_82) },
2657   { "testB",            { Eb, Gb }, 0 },
2658   { "testS",            { Ev, Gv }, 0 },
2659   { "xchgB",            { Ebh2, Gb }, 0 },
2660   { "xchgS",            { Evh2, Gv }, 0 },
2661   /* 88 */
2662   { "movB",             { Ebh3, Gb }, 0 },
2663   { "movS",             { Evh3, Gv }, 0 },
2664   { "movB",             { Gb, EbS }, 0 },
2665   { "movS",             { Gv, EvS }, 0 },
2666   { "movD",             { Sv, Sw }, 0 },
2667   { MOD_TABLE (MOD_8D) },
2668   { "movD",             { Sw, Sv }, 0 },
2669   { REG_TABLE (REG_8F) },
2670   /* 90 */
2671   { PREFIX_TABLE (PREFIX_90) },
2672   { "xchgS",            { RMeCX, eAX }, 0 },
2673   { "xchgS",            { RMeDX, eAX }, 0 },
2674   { "xchgS",            { RMeBX, eAX }, 0 },
2675   { "xchgS",            { RMeSP, eAX }, 0 },
2676   { "xchgS",            { RMeBP, eAX }, 0 },
2677   { "xchgS",            { RMeSI, eAX }, 0 },
2678   { "xchgS",            { RMeDI, eAX }, 0 },
2679   /* 98 */
2680   { "cW{t|}R",          { XX }, 0 },
2681   { "cR{t|}O",          { XX }, 0 },
2682   { X86_64_TABLE (X86_64_9A) },
2683   { Bad_Opcode },       /* fwait */
2684   { "pushfT",           { XX }, 0 },
2685   { "popfT",            { XX }, 0 },
2686   { "sahf",             { XX }, 0 },
2687   { "lahf",             { XX }, 0 },
2688   /* a0 */
2689   { "mov%LB",           { AL, Ob }, 0 },
2690   { "mov%LS",           { eAX, Ov }, 0 },
2691   { "mov%LB",           { Ob, AL }, 0 },
2692   { "mov%LS",           { Ov, eAX }, 0 },
2693   { "movs{b|}",         { Ybr, Xb }, 0 },
2694   { "movs{R|}",         { Yvr, Xv }, 0 },
2695   { "cmps{b|}",         { Xb, Yb }, 0 },
2696   { "cmps{R|}",         { Xv, Yv }, 0 },
2697   /* a8 */
2698   { "testB",            { AL, Ib }, 0 },
2699   { "testS",            { eAX, Iv }, 0 },
2700   { "stosB",            { Ybr, AL }, 0 },
2701   { "stosS",            { Yvr, eAX }, 0 },
2702   { "lodsB",            { ALr, Xb }, 0 },
2703   { "lodsS",            { eAXr, Xv }, 0 },
2704   { "scasB",            { AL, Yb }, 0 },
2705   { "scasS",            { eAX, Yv }, 0 },
2706   /* b0 */
2707   { "movB",             { RMAL, Ib }, 0 },
2708   { "movB",             { RMCL, Ib }, 0 },
2709   { "movB",             { RMDL, Ib }, 0 },
2710   { "movB",             { RMBL, Ib }, 0 },
2711   { "movB",             { RMAH, Ib }, 0 },
2712   { "movB",             { RMCH, Ib }, 0 },
2713   { "movB",             { RMDH, Ib }, 0 },
2714   { "movB",             { RMBH, Ib }, 0 },
2715   /* b8 */
2716   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2717   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2718   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2719   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2720   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2721   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2722   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2723   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2724   /* c0 */
2725   { REG_TABLE (REG_C0) },
2726   { REG_TABLE (REG_C1) },
2727   { "retT",             { Iw, BND }, 0 },
2728   { "retT",             { BND }, 0 },
2729   { X86_64_TABLE (X86_64_C4) },
2730   { X86_64_TABLE (X86_64_C5) },
2731   { REG_TABLE (REG_C6) },
2732   { REG_TABLE (REG_C7) },
2733   /* c8 */
2734   { "enterT",           { Iw, Ib }, 0 },
2735   { "leaveT",           { XX }, 0 },
2736   { "Jret{|f}P",        { Iw }, 0 },
2737   { "Jret{|f}P",        { XX }, 0 },
2738   { "int3",             { XX }, 0 },
2739   { "int",              { Ib }, 0 },
2740   { X86_64_TABLE (X86_64_CE) },
2741   { "iret%LP",          { XX }, 0 },
2742   /* d0 */
2743   { REG_TABLE (REG_D0) },
2744   { REG_TABLE (REG_D1) },
2745   { REG_TABLE (REG_D2) },
2746   { REG_TABLE (REG_D3) },
2747   { X86_64_TABLE (X86_64_D4) },
2748   { X86_64_TABLE (X86_64_D5) },
2749   { Bad_Opcode },
2750   { "xlat",             { DSBX }, 0 },
2751   /* d8 */
2752   { FLOAT },
2753   { FLOAT },
2754   { FLOAT },
2755   { FLOAT },
2756   { FLOAT },
2757   { FLOAT },
2758   { FLOAT },
2759   { FLOAT },
2760   /* e0 */
2761   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2762   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2763   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2764   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2765   { "inB",              { AL, Ib }, 0 },
2766   { "inG",              { zAX, Ib }, 0 },
2767   { "outB",             { Ib, AL }, 0 },
2768   { "outG",             { Ib, zAX }, 0 },
2769   /* e8 */
2770   { X86_64_TABLE (X86_64_E8) },
2771   { X86_64_TABLE (X86_64_E9) },
2772   { X86_64_TABLE (X86_64_EA) },
2773   { "jmp",              { Jb, BND }, 0 },
2774   { "inB",              { AL, indirDX }, 0 },
2775   { "inG",              { zAX, indirDX }, 0 },
2776   { "outB",             { indirDX, AL }, 0 },
2777   { "outG",             { indirDX, zAX }, 0 },
2778   /* f0 */
2779   { Bad_Opcode },       /* lock prefix */
2780   { "icebp",            { XX }, 0 },
2781   { Bad_Opcode },       /* repne */
2782   { Bad_Opcode },       /* repz */
2783   { "hlt",              { XX }, 0 },
2784   { "cmc",              { XX }, 0 },
2785   { REG_TABLE (REG_F6) },
2786   { REG_TABLE (REG_F7) },
2787   /* f8 */
2788   { "clc",              { XX }, 0 },
2789   { "stc",              { XX }, 0 },
2790   { "cli",              { XX }, 0 },
2791   { "sti",              { XX }, 0 },
2792   { "cld",              { XX }, 0 },
2793   { "std",              { XX }, 0 },
2794   { REG_TABLE (REG_FE) },
2795   { REG_TABLE (REG_FF) },
2796 };
2797
2798 static const struct dis386 dis386_twobyte[] = {
2799   /* 00 */
2800   { REG_TABLE (REG_0F00 ) },
2801   { REG_TABLE (REG_0F01 ) },
2802   { "larS",             { Gv, Ew }, 0 },
2803   { "lslS",             { Gv, Ew }, 0 },
2804   { Bad_Opcode },
2805   { "syscall",          { XX }, 0 },
2806   { "clts",             { XX }, 0 },
2807   { "sysret%LP",                { XX }, 0 },
2808   /* 08 */
2809   { "invd",             { XX }, 0 },
2810   { "wbinvd",           { XX }, 0 },
2811   { Bad_Opcode },
2812   { "ud2",              { XX }, 0 },
2813   { Bad_Opcode },
2814   { REG_TABLE (REG_0F0D) },
2815   { "femms",            { XX }, 0 },
2816   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2817   /* 10 */
2818   { PREFIX_TABLE (PREFIX_0F10) },
2819   { PREFIX_TABLE (PREFIX_0F11) },
2820   { PREFIX_TABLE (PREFIX_0F12) },
2821   { MOD_TABLE (MOD_0F13) },
2822   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2823   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2824   { PREFIX_TABLE (PREFIX_0F16) },
2825   { MOD_TABLE (MOD_0F17) },
2826   /* 18 */
2827   { REG_TABLE (REG_0F18) },
2828   { "nopQ",             { Ev }, 0 },
2829   { PREFIX_TABLE (PREFIX_0F1A) },
2830   { PREFIX_TABLE (PREFIX_0F1B) },
2831   { "nopQ",             { Ev }, 0 },
2832   { "nopQ",             { Ev }, 0 },
2833   { "nopQ",             { Ev }, 0 },
2834   { "nopQ",             { Ev }, 0 },
2835   /* 20 */
2836   { "movZ",             { Rm, Cm }, 0 },
2837   { "movZ",             { Rm, Dm }, 0 },
2838   { "movZ",             { Cm, Rm }, 0 },
2839   { "movZ",             { Dm, Rm }, 0 },
2840   { MOD_TABLE (MOD_0F24) },
2841   { Bad_Opcode },
2842   { MOD_TABLE (MOD_0F26) },
2843   { Bad_Opcode },
2844   /* 28 */
2845   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2846   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2847   { PREFIX_TABLE (PREFIX_0F2A) },
2848   { PREFIX_TABLE (PREFIX_0F2B) },
2849   { PREFIX_TABLE (PREFIX_0F2C) },
2850   { PREFIX_TABLE (PREFIX_0F2D) },
2851   { PREFIX_TABLE (PREFIX_0F2E) },
2852   { PREFIX_TABLE (PREFIX_0F2F) },
2853   /* 30 */
2854   { "wrmsr",            { XX }, 0 },
2855   { "rdtsc",            { XX }, 0 },
2856   { "rdmsr",            { XX }, 0 },
2857   { "rdpmc",            { XX }, 0 },
2858   { "sysenter",         { XX }, 0 },
2859   { "sysexit",          { XX }, 0 },
2860   { Bad_Opcode },
2861   { "getsec",           { XX }, 0 },
2862   /* 38 */
2863   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2864   { Bad_Opcode },
2865   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2866   { Bad_Opcode },
2867   { Bad_Opcode },
2868   { Bad_Opcode },
2869   { Bad_Opcode },
2870   { Bad_Opcode },
2871   /* 40 */
2872   { "cmovoS",           { Gv, Ev }, 0 },
2873   { "cmovnoS",          { Gv, Ev }, 0 },
2874   { "cmovbS",           { Gv, Ev }, 0 },
2875   { "cmovaeS",          { Gv, Ev }, 0 },
2876   { "cmoveS",           { Gv, Ev }, 0 },
2877   { "cmovneS",          { Gv, Ev }, 0 },
2878   { "cmovbeS",          { Gv, Ev }, 0 },
2879   { "cmovaS",           { Gv, Ev }, 0 },
2880   /* 48 */
2881   { "cmovsS",           { Gv, Ev }, 0 },
2882   { "cmovnsS",          { Gv, Ev }, 0 },
2883   { "cmovpS",           { Gv, Ev }, 0 },
2884   { "cmovnpS",          { Gv, Ev }, 0 },
2885   { "cmovlS",           { Gv, Ev }, 0 },
2886   { "cmovgeS",          { Gv, Ev }, 0 },
2887   { "cmovleS",          { Gv, Ev }, 0 },
2888   { "cmovgS",           { Gv, Ev }, 0 },
2889   /* 50 */
2890   { MOD_TABLE (MOD_0F51) },
2891   { PREFIX_TABLE (PREFIX_0F51) },
2892   { PREFIX_TABLE (PREFIX_0F52) },
2893   { PREFIX_TABLE (PREFIX_0F53) },
2894   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2895   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2896   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2897   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2898   /* 58 */
2899   { PREFIX_TABLE (PREFIX_0F58) },
2900   { PREFIX_TABLE (PREFIX_0F59) },
2901   { PREFIX_TABLE (PREFIX_0F5A) },
2902   { PREFIX_TABLE (PREFIX_0F5B) },
2903   { PREFIX_TABLE (PREFIX_0F5C) },
2904   { PREFIX_TABLE (PREFIX_0F5D) },
2905   { PREFIX_TABLE (PREFIX_0F5E) },
2906   { PREFIX_TABLE (PREFIX_0F5F) },
2907   /* 60 */
2908   { PREFIX_TABLE (PREFIX_0F60) },
2909   { PREFIX_TABLE (PREFIX_0F61) },
2910   { PREFIX_TABLE (PREFIX_0F62) },
2911   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2912   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2913   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2914   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2915   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2916   /* 68 */
2917   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2918   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2919   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2920   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2921   { PREFIX_TABLE (PREFIX_0F6C) },
2922   { PREFIX_TABLE (PREFIX_0F6D) },
2923   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2924   { PREFIX_TABLE (PREFIX_0F6F) },
2925   /* 70 */
2926   { PREFIX_TABLE (PREFIX_0F70) },
2927   { REG_TABLE (REG_0F71) },
2928   { REG_TABLE (REG_0F72) },
2929   { REG_TABLE (REG_0F73) },
2930   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2931   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2932   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2933   { "emms",             { XX }, PREFIX_OPCODE },
2934   /* 78 */
2935   { PREFIX_TABLE (PREFIX_0F78) },
2936   { PREFIX_TABLE (PREFIX_0F79) },
2937   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2938   { Bad_Opcode },
2939   { PREFIX_TABLE (PREFIX_0F7C) },
2940   { PREFIX_TABLE (PREFIX_0F7D) },
2941   { PREFIX_TABLE (PREFIX_0F7E) },
2942   { PREFIX_TABLE (PREFIX_0F7F) },
2943   /* 80 */
2944   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2945   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2946   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2947   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2948   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2949   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2950   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2951   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2952   /* 88 */
2953   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2954   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2955   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2956   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2957   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2958   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2959   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2960   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2961   /* 90 */
2962   { "seto",             { Eb }, 0 },
2963   { "setno",            { Eb }, 0 },
2964   { "setb",             { Eb }, 0 },
2965   { "setae",            { Eb }, 0 },
2966   { "sete",             { Eb }, 0 },
2967   { "setne",            { Eb }, 0 },
2968   { "setbe",            { Eb }, 0 },
2969   { "seta",             { Eb }, 0 },
2970   /* 98 */
2971   { "sets",             { Eb }, 0 },
2972   { "setns",            { Eb }, 0 },
2973   { "setp",             { Eb }, 0 },
2974   { "setnp",            { Eb }, 0 },
2975   { "setl",             { Eb }, 0 },
2976   { "setge",            { Eb }, 0 },
2977   { "setle",            { Eb }, 0 },
2978   { "setg",             { Eb }, 0 },
2979   /* a0 */
2980   { "pushT",            { fs }, 0 },
2981   { "popT",             { fs }, 0 },
2982   { "cpuid",            { XX }, 0 },
2983   { "btS",              { Ev, Gv }, 0 },
2984   { "shldS",            { Ev, Gv, Ib }, 0 },
2985   { "shldS",            { Ev, Gv, CL }, 0 },
2986   { REG_TABLE (REG_0FA6) },
2987   { REG_TABLE (REG_0FA7) },
2988   /* a8 */
2989   { "pushT",            { gs }, 0 },
2990   { "popT",             { gs }, 0 },
2991   { "rsm",              { XX }, 0 },
2992   { "btsS",             { Evh1, Gv }, 0 },
2993   { "shrdS",            { Ev, Gv, Ib }, 0 },
2994   { "shrdS",            { Ev, Gv, CL }, 0 },
2995   { REG_TABLE (REG_0FAE) },
2996   { "imulS",            { Gv, Ev }, 0 },
2997   /* b0 */
2998   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2999   { "cmpxchgS",         { Evh1, Gv }, 0 },
3000   { MOD_TABLE (MOD_0FB2) },
3001   { "btrS",             { Evh1, Gv }, 0 },
3002   { MOD_TABLE (MOD_0FB4) },
3003   { MOD_TABLE (MOD_0FB5) },
3004   { "movz{bR|x}",       { Gv, Eb }, 0 },
3005   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3006   /* b8 */
3007   { PREFIX_TABLE (PREFIX_0FB8) },
3008   { "ud1",              { XX }, 0 },
3009   { REG_TABLE (REG_0FBA) },
3010   { "btcS",             { Evh1, Gv }, 0 },
3011   { PREFIX_TABLE (PREFIX_0FBC) },
3012   { PREFIX_TABLE (PREFIX_0FBD) },
3013   { "movs{bR|x}",       { Gv, Eb }, 0 },
3014   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3015   /* c0 */
3016   { "xaddB",            { Ebh1, Gb }, 0 },
3017   { "xaddS",            { Evh1, Gv }, 0 },
3018   { PREFIX_TABLE (PREFIX_0FC2) },
3019   { MOD_TABLE (MOD_0FC3) },
3020   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3021   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3022   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3023   { REG_TABLE (REG_0FC7) },
3024   /* c8 */
3025   { "bswap",            { RMeAX }, 0 },
3026   { "bswap",            { RMeCX }, 0 },
3027   { "bswap",            { RMeDX }, 0 },
3028   { "bswap",            { RMeBX }, 0 },
3029   { "bswap",            { RMeSP }, 0 },
3030   { "bswap",            { RMeBP }, 0 },
3031   { "bswap",            { RMeSI }, 0 },
3032   { "bswap",            { RMeDI }, 0 },
3033   /* d0 */
3034   { PREFIX_TABLE (PREFIX_0FD0) },
3035   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3036   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3037   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3038   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3039   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3040   { PREFIX_TABLE (PREFIX_0FD6) },
3041   { MOD_TABLE (MOD_0FD7) },
3042   /* d8 */
3043   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3044   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3045   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3046   { "pand",             { MX, EM }, PREFIX_OPCODE },
3047   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3048   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3049   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3050   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3051   /* e0 */
3052   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3053   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3054   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3055   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3056   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3057   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3058   { PREFIX_TABLE (PREFIX_0FE6) },
3059   { PREFIX_TABLE (PREFIX_0FE7) },
3060   /* e8 */
3061   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3062   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3063   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3064   { "por",              { MX, EM }, PREFIX_OPCODE },
3065   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3066   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3067   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3068   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3069   /* f0 */
3070   { PREFIX_TABLE (PREFIX_0FF0) },
3071   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3072   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3073   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3074   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3075   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3076   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3077   { PREFIX_TABLE (PREFIX_0FF7) },
3078   /* f8 */
3079   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3080   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3081   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3082   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3083   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3084   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3085   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3086   { Bad_Opcode },
3087 };
3088
3089 static const unsigned char onebyte_has_modrm[256] = {
3090   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3091   /*       -------------------------------        */
3092   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3093   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3094   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3095   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3096   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3097   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3098   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3099   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3100   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3101   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3102   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3103   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3104   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3105   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3106   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3107   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3108   /*       -------------------------------        */
3109   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3110 };
3111
3112 static const unsigned char twobyte_has_modrm[256] = {
3113   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3114   /*       -------------------------------        */
3115   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3116   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3117   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3118   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3119   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3120   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3121   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3122   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3123   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3124   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3125   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3126   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3127   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3128   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3129   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3130   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3131   /*       -------------------------------        */
3132   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3133 };
3134
3135 static char obuf[100];
3136 static char *obufp;
3137 static char *mnemonicendp;
3138 static char scratchbuf[100];
3139 static unsigned char *start_codep;
3140 static unsigned char *insn_codep;
3141 static unsigned char *codep;
3142 static unsigned char *end_codep;
3143 static int last_lock_prefix;
3144 static int last_repz_prefix;
3145 static int last_repnz_prefix;
3146 static int last_data_prefix;
3147 static int last_addr_prefix;
3148 static int last_rex_prefix;
3149 static int last_seg_prefix;
3150 static int fwait_prefix;
3151 /* The active segment register prefix.  */
3152 static int active_seg_prefix;
3153 #define MAX_CODE_LENGTH 15
3154 /* We can up to 14 prefixes since the maximum instruction length is
3155    15bytes.  */
3156 static int all_prefixes[MAX_CODE_LENGTH - 1];
3157 static disassemble_info *the_info;
3158 static struct
3159   {
3160     int mod;
3161     int reg;
3162     int rm;
3163   }
3164 modrm;
3165 static unsigned char need_modrm;
3166 static struct
3167   {
3168     int scale;
3169     int index;
3170     int base;
3171   }
3172 sib;
3173 static struct
3174   {
3175     int register_specifier;
3176     int length;
3177     int prefix;
3178     int w;
3179     int evex;
3180     int r;
3181     int v;
3182     int mask_register_specifier;
3183     int zeroing;
3184     int ll;
3185     int b;
3186   }
3187 vex;
3188 static unsigned char need_vex;
3189 static unsigned char need_vex_reg;
3190 static unsigned char vex_w_done;
3191
3192 struct op
3193   {
3194     const char *name;
3195     unsigned int len;
3196   };
3197
3198 /* If we are accessing mod/rm/reg without need_modrm set, then the
3199    values are stale.  Hitting this abort likely indicates that you
3200    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3201 #define MODRM_CHECK  if (!need_modrm) abort ()
3202
3203 static const char **names64;
3204 static const char **names32;
3205 static const char **names16;
3206 static const char **names8;
3207 static const char **names8rex;
3208 static const char **names_seg;
3209 static const char *index64;
3210 static const char *index32;
3211 static const char **index16;
3212 static const char **names_bnd;
3213
3214 static const char *intel_names64[] = {
3215   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3216   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3217 };
3218 static const char *intel_names32[] = {
3219   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3220   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3221 };
3222 static const char *intel_names16[] = {
3223   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3224   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3225 };
3226 static const char *intel_names8[] = {
3227   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3228 };
3229 static const char *intel_names8rex[] = {
3230   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3231   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3232 };
3233 static const char *intel_names_seg[] = {
3234   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3235 };
3236 static const char *intel_index64 = "riz";
3237 static const char *intel_index32 = "eiz";
3238 static const char *intel_index16[] = {
3239   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3240 };
3241
3242 static const char *att_names64[] = {
3243   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3244   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3245 };
3246 static const char *att_names32[] = {
3247   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3248   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3249 };
3250 static const char *att_names16[] = {
3251   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3252   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3253 };
3254 static const char *att_names8[] = {
3255   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3256 };
3257 static const char *att_names8rex[] = {
3258   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3259   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3260 };
3261 static const char *att_names_seg[] = {
3262   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3263 };
3264 static const char *att_index64 = "%riz";
3265 static const char *att_index32 = "%eiz";
3266 static const char *att_index16[] = {
3267   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3268 };
3269
3270 static const char **names_mm;
3271 static const char *intel_names_mm[] = {
3272   "mm0", "mm1", "mm2", "mm3",
3273   "mm4", "mm5", "mm6", "mm7"
3274 };
3275 static const char *att_names_mm[] = {
3276   "%mm0", "%mm1", "%mm2", "%mm3",
3277   "%mm4", "%mm5", "%mm6", "%mm7"
3278 };
3279
3280 static const char *intel_names_bnd[] = {
3281   "bnd0", "bnd1", "bnd2", "bnd3"
3282 };
3283
3284 static const char *att_names_bnd[] = {
3285   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3286 };
3287
3288 static const char **names_xmm;
3289 static const char *intel_names_xmm[] = {
3290   "xmm0", "xmm1", "xmm2", "xmm3",
3291   "xmm4", "xmm5", "xmm6", "xmm7",
3292   "xmm8", "xmm9", "xmm10", "xmm11",
3293   "xmm12", "xmm13", "xmm14", "xmm15",
3294   "xmm16", "xmm17", "xmm18", "xmm19",
3295   "xmm20", "xmm21", "xmm22", "xmm23",
3296   "xmm24", "xmm25", "xmm26", "xmm27",
3297   "xmm28", "xmm29", "xmm30", "xmm31"
3298 };
3299 static const char *att_names_xmm[] = {
3300   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3301   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3302   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3303   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3304   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3305   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3306   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3307   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3308 };
3309
3310 static const char **names_ymm;
3311 static const char *intel_names_ymm[] = {
3312   "ymm0", "ymm1", "ymm2", "ymm3",
3313   "ymm4", "ymm5", "ymm6", "ymm7",
3314   "ymm8", "ymm9", "ymm10", "ymm11",
3315   "ymm12", "ymm13", "ymm14", "ymm15",
3316   "ymm16", "ymm17", "ymm18", "ymm19",
3317   "ymm20", "ymm21", "ymm22", "ymm23",
3318   "ymm24", "ymm25", "ymm26", "ymm27",
3319   "ymm28", "ymm29", "ymm30", "ymm31"
3320 };
3321 static const char *att_names_ymm[] = {
3322   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3323   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3324   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3325   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3326   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3327   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3328   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3329   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3330 };
3331
3332 static const char **names_zmm;
3333 static const char *intel_names_zmm[] = {
3334   "zmm0", "zmm1", "zmm2", "zmm3",
3335   "zmm4", "zmm5", "zmm6", "zmm7",
3336   "zmm8", "zmm9", "zmm10", "zmm11",
3337   "zmm12", "zmm13", "zmm14", "zmm15",
3338   "zmm16", "zmm17", "zmm18", "zmm19",
3339   "zmm20", "zmm21", "zmm22", "zmm23",
3340   "zmm24", "zmm25", "zmm26", "zmm27",
3341   "zmm28", "zmm29", "zmm30", "zmm31"
3342 };
3343 static const char *att_names_zmm[] = {
3344   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3345   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3346   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3347   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3348   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3349   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3350   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3351   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3352 };
3353
3354 static const char **names_mask;
3355 static const char *intel_names_mask[] = {
3356   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3357 };
3358 static const char *att_names_mask[] = {
3359   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3360 };
3361
3362 static const char *names_rounding[] =
3363 {
3364   "{rn-sae}",
3365   "{rd-sae}",
3366   "{ru-sae}",
3367   "{rz-sae}"
3368 };
3369
3370 static const struct dis386 reg_table[][8] = {
3371   /* REG_80 */
3372   {
3373     { "addA",   { Ebh1, Ib }, 0 },
3374     { "orA",    { Ebh1, Ib }, 0 },
3375     { "adcA",   { Ebh1, Ib }, 0 },
3376     { "sbbA",   { Ebh1, Ib }, 0 },
3377     { "andA",   { Ebh1, Ib }, 0 },
3378     { "subA",   { Ebh1, Ib }, 0 },
3379     { "xorA",   { Ebh1, Ib }, 0 },
3380     { "cmpA",   { Eb, Ib }, 0 },
3381   },
3382   /* REG_81 */
3383   {
3384     { "addQ",   { Evh1, Iv }, 0 },
3385     { "orQ",    { Evh1, Iv }, 0 },
3386     { "adcQ",   { Evh1, Iv }, 0 },
3387     { "sbbQ",   { Evh1, Iv }, 0 },
3388     { "andQ",   { Evh1, Iv }, 0 },
3389     { "subQ",   { Evh1, Iv }, 0 },
3390     { "xorQ",   { Evh1, Iv }, 0 },
3391     { "cmpQ",   { Ev, Iv }, 0 },
3392   },
3393   /* REG_82 */
3394   {
3395     { "addQ",   { Evh1, sIb }, 0 },
3396     { "orQ",    { Evh1, sIb }, 0 },
3397     { "adcQ",   { Evh1, sIb }, 0 },
3398     { "sbbQ",   { Evh1, sIb }, 0 },
3399     { "andQ",   { Evh1, sIb }, 0 },
3400     { "subQ",   { Evh1, sIb }, 0 },
3401     { "xorQ",   { Evh1, sIb }, 0 },
3402     { "cmpQ",   { Ev, sIb }, 0 },
3403   },
3404   /* REG_8F */
3405   {
3406     { "popU",   { stackEv }, 0 },
3407     { XOP_8F_TABLE (XOP_09) },
3408     { Bad_Opcode },
3409     { Bad_Opcode },
3410     { Bad_Opcode },
3411     { XOP_8F_TABLE (XOP_09) },
3412   },
3413   /* REG_C0 */
3414   {
3415     { "rolA",   { Eb, Ib }, 0 },
3416     { "rorA",   { Eb, Ib }, 0 },
3417     { "rclA",   { Eb, Ib }, 0 },
3418     { "rcrA",   { Eb, Ib }, 0 },
3419     { "shlA",   { Eb, Ib }, 0 },
3420     { "shrA",   { Eb, Ib }, 0 },
3421     { Bad_Opcode },
3422     { "sarA",   { Eb, Ib }, 0 },
3423   },
3424   /* REG_C1 */
3425   {
3426     { "rolQ",   { Ev, Ib }, 0 },
3427     { "rorQ",   { Ev, Ib }, 0 },
3428     { "rclQ",   { Ev, Ib }, 0 },
3429     { "rcrQ",   { Ev, Ib }, 0 },
3430     { "shlQ",   { Ev, Ib }, 0 },
3431     { "shrQ",   { Ev, Ib }, 0 },
3432     { Bad_Opcode },
3433     { "sarQ",   { Ev, Ib }, 0 },
3434   },
3435   /* REG_C6 */
3436   {
3437     { "movA",   { Ebh3, Ib }, 0 },
3438     { Bad_Opcode },
3439     { Bad_Opcode },
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { Bad_Opcode },
3444     { MOD_TABLE (MOD_C6_REG_7) },
3445   },
3446   /* REG_C7 */
3447   {
3448     { "movQ",   { Evh3, Iv }, 0 },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { Bad_Opcode },
3454     { Bad_Opcode },
3455     { MOD_TABLE (MOD_C7_REG_7) },
3456   },
3457   /* REG_D0 */
3458   {
3459     { "rolA",   { Eb, I1 }, 0 },
3460     { "rorA",   { Eb, I1 }, 0 },
3461     { "rclA",   { Eb, I1 }, 0 },
3462     { "rcrA",   { Eb, I1 }, 0 },
3463     { "shlA",   { Eb, I1 }, 0 },
3464     { "shrA",   { Eb, I1 }, 0 },
3465     { Bad_Opcode },
3466     { "sarA",   { Eb, I1 }, 0 },
3467   },
3468   /* REG_D1 */
3469   {
3470     { "rolQ",   { Ev, I1 }, 0 },
3471     { "rorQ",   { Ev, I1 }, 0 },
3472     { "rclQ",   { Ev, I1 }, 0 },
3473     { "rcrQ",   { Ev, I1 }, 0 },
3474     { "shlQ",   { Ev, I1 }, 0 },
3475     { "shrQ",   { Ev, I1 }, 0 },
3476     { Bad_Opcode },
3477     { "sarQ",   { Ev, I1 }, 0 },
3478   },
3479   /* REG_D2 */
3480   {
3481     { "rolA",   { Eb, CL }, 0 },
3482     { "rorA",   { Eb, CL }, 0 },
3483     { "rclA",   { Eb, CL }, 0 },
3484     { "rcrA",   { Eb, CL }, 0 },
3485     { "shlA",   { Eb, CL }, 0 },
3486     { "shrA",   { Eb, CL }, 0 },
3487     { Bad_Opcode },
3488     { "sarA",   { Eb, CL }, 0 },
3489   },
3490   /* REG_D3 */
3491   {
3492     { "rolQ",   { Ev, CL }, 0 },
3493     { "rorQ",   { Ev, CL }, 0 },
3494     { "rclQ",   { Ev, CL }, 0 },
3495     { "rcrQ",   { Ev, CL }, 0 },
3496     { "shlQ",   { Ev, CL }, 0 },
3497     { "shrQ",   { Ev, CL }, 0 },
3498     { Bad_Opcode },
3499     { "sarQ",   { Ev, CL }, 0 },
3500   },
3501   /* REG_F6 */
3502   {
3503     { "testA",  { Eb, Ib }, 0 },
3504     { Bad_Opcode },
3505     { "notA",   { Ebh1 }, 0 },
3506     { "negA",   { Ebh1 }, 0 },
3507     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3508     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3509     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3510     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3511   },
3512   /* REG_F7 */
3513   {
3514     { "testQ",  { Ev, Iv }, 0 },
3515     { Bad_Opcode },
3516     { "notQ",   { Evh1 }, 0 },
3517     { "negQ",   { Evh1 }, 0 },
3518     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3519     { "imulQ",  { Ev }, 0 },
3520     { "divQ",   { Ev }, 0 },
3521     { "idivQ",  { Ev }, 0 },
3522   },
3523   /* REG_FE */
3524   {
3525     { "incA",   { Ebh1 }, 0 },
3526     { "decA",   { Ebh1 }, 0 },
3527   },
3528   /* REG_FF */
3529   {
3530     { "incQ",   { Evh1 }, 0 },
3531     { "decQ",   { Evh1 }, 0 },
3532     { "call{T|}", { indirEv, BND }, 0 },
3533     { MOD_TABLE (MOD_FF_REG_3) },
3534     { "jmp{T|}", { indirEv, BND }, 0 },
3535     { MOD_TABLE (MOD_FF_REG_5) },
3536     { "pushU",  { stackEv }, 0 },
3537     { Bad_Opcode },
3538   },
3539   /* REG_0F00 */
3540   {
3541     { "sldtD",  { Sv }, 0 },
3542     { "strD",   { Sv }, 0 },
3543     { "lldt",   { Ew }, 0 },
3544     { "ltr",    { Ew }, 0 },
3545     { "verr",   { Ew }, 0 },
3546     { "verw",   { Ew }, 0 },
3547     { Bad_Opcode },
3548     { Bad_Opcode },
3549   },
3550   /* REG_0F01 */
3551   {
3552     { MOD_TABLE (MOD_0F01_REG_0) },
3553     { MOD_TABLE (MOD_0F01_REG_1) },
3554     { MOD_TABLE (MOD_0F01_REG_2) },
3555     { MOD_TABLE (MOD_0F01_REG_3) },
3556     { "smswD",  { Sv }, 0 },
3557     { Bad_Opcode },
3558     { "lmsw",   { Ew }, 0 },
3559     { MOD_TABLE (MOD_0F01_REG_7) },
3560   },
3561   /* REG_0F0D */
3562   {
3563     { "prefetch",       { Mb }, 0 },
3564     { "prefetchw",      { Mb }, 0 },
3565     { "prefetchwt1",    { Mb }, 0 },
3566     { "prefetch",       { Mb }, 0 },
3567     { "prefetch",       { Mb }, 0 },
3568     { "prefetch",       { Mb }, 0 },
3569     { "prefetch",       { Mb }, 0 },
3570     { "prefetch",       { Mb }, 0 },
3571   },
3572   /* REG_0F18 */
3573   {
3574     { MOD_TABLE (MOD_0F18_REG_0) },
3575     { MOD_TABLE (MOD_0F18_REG_1) },
3576     { MOD_TABLE (MOD_0F18_REG_2) },
3577     { MOD_TABLE (MOD_0F18_REG_3) },
3578     { MOD_TABLE (MOD_0F18_REG_4) },
3579     { MOD_TABLE (MOD_0F18_REG_5) },
3580     { MOD_TABLE (MOD_0F18_REG_6) },
3581     { MOD_TABLE (MOD_0F18_REG_7) },
3582   },
3583   /* REG_0F71 */
3584   {
3585     { Bad_Opcode },
3586     { Bad_Opcode },
3587     { MOD_TABLE (MOD_0F71_REG_2) },
3588     { Bad_Opcode },
3589     { MOD_TABLE (MOD_0F71_REG_4) },
3590     { Bad_Opcode },
3591     { MOD_TABLE (MOD_0F71_REG_6) },
3592   },
3593   /* REG_0F72 */
3594   {
3595     { Bad_Opcode },
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_0F72_REG_2) },
3598     { Bad_Opcode },
3599     { MOD_TABLE (MOD_0F72_REG_4) },
3600     { Bad_Opcode },
3601     { MOD_TABLE (MOD_0F72_REG_6) },
3602   },
3603   /* REG_0F73 */
3604   {
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_0F73_REG_2) },
3608     { MOD_TABLE (MOD_0F73_REG_3) },
3609     { Bad_Opcode },
3610     { Bad_Opcode },
3611     { MOD_TABLE (MOD_0F73_REG_6) },
3612     { MOD_TABLE (MOD_0F73_REG_7) },
3613   },
3614   /* REG_0FA6 */
3615   {
3616     { "montmul",        { { OP_0f07, 0 } }, 0 },
3617     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3618     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3619   },
3620   /* REG_0FA7 */
3621   {
3622     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3623     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3624     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3625     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3626     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3627     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3628   },
3629   /* REG_0FAE */
3630   {
3631     { MOD_TABLE (MOD_0FAE_REG_0) },
3632     { MOD_TABLE (MOD_0FAE_REG_1) },
3633     { MOD_TABLE (MOD_0FAE_REG_2) },
3634     { MOD_TABLE (MOD_0FAE_REG_3) },
3635     { MOD_TABLE (MOD_0FAE_REG_4) },
3636     { MOD_TABLE (MOD_0FAE_REG_5) },
3637     { MOD_TABLE (MOD_0FAE_REG_6) },
3638     { MOD_TABLE (MOD_0FAE_REG_7) },
3639   },
3640   /* REG_0FBA */
3641   {
3642     { Bad_Opcode },
3643     { Bad_Opcode },
3644     { Bad_Opcode },
3645     { Bad_Opcode },
3646     { "btQ",    { Ev, Ib }, 0 },
3647     { "btsQ",   { Evh1, Ib }, 0 },
3648     { "btrQ",   { Evh1, Ib }, 0 },
3649     { "btcQ",   { Evh1, Ib }, 0 },
3650   },
3651   /* REG_0FC7 */
3652   {
3653     { Bad_Opcode },
3654     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3655     { Bad_Opcode },
3656     { MOD_TABLE (MOD_0FC7_REG_3) },
3657     { MOD_TABLE (MOD_0FC7_REG_4) },
3658     { MOD_TABLE (MOD_0FC7_REG_5) },
3659     { MOD_TABLE (MOD_0FC7_REG_6) },
3660     { MOD_TABLE (MOD_0FC7_REG_7) },
3661   },
3662   /* REG_VEX_0F71 */
3663   {
3664     { Bad_Opcode },
3665     { Bad_Opcode },
3666     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3667     { Bad_Opcode },
3668     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3669     { Bad_Opcode },
3670     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3671   },
3672   /* REG_VEX_0F72 */
3673   {
3674     { Bad_Opcode },
3675     { Bad_Opcode },
3676     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3677     { Bad_Opcode },
3678     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3679     { Bad_Opcode },
3680     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3681   },
3682   /* REG_VEX_0F73 */
3683   {
3684     { Bad_Opcode },
3685     { Bad_Opcode },
3686     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3687     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3688     { Bad_Opcode },
3689     { Bad_Opcode },
3690     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3691     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3692   },
3693   /* REG_VEX_0FAE */
3694   {
3695     { Bad_Opcode },
3696     { Bad_Opcode },
3697     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3698     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3699   },
3700   /* REG_VEX_0F38F3 */
3701   {
3702     { Bad_Opcode },
3703     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3704     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3705     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3706   },
3707   /* REG_XOP_LWPCB */
3708   {
3709     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3710     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3711   },
3712   /* REG_XOP_LWP */
3713   {
3714     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3715     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3716   },
3717   /* REG_XOP_TBM_01 */
3718   {
3719     { Bad_Opcode },
3720     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3721     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3722     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3723     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3724     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3725     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3726     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3727   },
3728   /* REG_XOP_TBM_02 */
3729   {
3730     { Bad_Opcode },
3731     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3732     { Bad_Opcode },
3733     { Bad_Opcode },
3734     { Bad_Opcode },
3735     { Bad_Opcode },
3736     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3737   },
3738 #define NEED_REG_TABLE
3739 #include "i386-dis-evex.h"
3740 #undef NEED_REG_TABLE
3741 };
3742
3743 static const struct dis386 prefix_table[][4] = {
3744   /* PREFIX_90 */
3745   {
3746     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3747     { "pause", { XX }, 0 },
3748     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3749     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3750   },
3751
3752   /* PREFIX_0F10 */
3753   {
3754     { "movups", { XM, EXx }, PREFIX_OPCODE },
3755     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3756     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3757     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F11 */
3761   {
3762     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3763     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3764     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3765     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3766   },
3767
3768   /* PREFIX_0F12 */
3769   {
3770     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3771     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3772     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3773     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3774   },
3775
3776   /* PREFIX_0F16 */
3777   {
3778     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3779     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3780     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F1A */
3784   {
3785     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3786     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3787     { "bndmov", { Gbnd, Ebnd }, 0 },
3788     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3789   },
3790
3791   /* PREFIX_0F1B */
3792   {
3793     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3794     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3795     { "bndmov", { Ebnd, Gbnd }, 0 },
3796     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3797   },
3798
3799   /* PREFIX_0F2A */
3800   {
3801     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3802     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3803     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3804     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3805   },
3806
3807   /* PREFIX_0F2B */
3808   {
3809     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3810     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3811     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3812     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3813   },
3814
3815   /* PREFIX_0F2C */
3816   {
3817     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3818     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3819     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3820     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3821   },
3822
3823   /* PREFIX_0F2D */
3824   {
3825     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3826     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3827     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3828     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3829   },
3830
3831   /* PREFIX_0F2E */
3832   {
3833     { "ucomiss",{ XM, EXd }, 0 },
3834     { Bad_Opcode },
3835     { "ucomisd",{ XM, EXq }, 0 },
3836   },
3837
3838   /* PREFIX_0F2F */
3839   {
3840     { "comiss", { XM, EXd }, 0 },
3841     { Bad_Opcode },
3842     { "comisd", { XM, EXq }, 0 },
3843   },
3844
3845   /* PREFIX_0F51 */
3846   {
3847     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3848     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3849     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3850     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F52 */
3854   {
3855     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3856     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_0F53 */
3860   {
3861     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3862     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F58 */
3866   {
3867     { "addps", { XM, EXx }, PREFIX_OPCODE },
3868     { "addss", { XM, EXd }, PREFIX_OPCODE },
3869     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3870     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0F59 */
3874   {
3875     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3876     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3877     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3878     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F5A */
3882   {
3883     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3884     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3885     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3886     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3887   },
3888
3889   /* PREFIX_0F5B */
3890   {
3891     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3892     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3893     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3894   },
3895
3896   /* PREFIX_0F5C */
3897   {
3898     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3899     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3900     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3901     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3902   },
3903
3904   /* PREFIX_0F5D */
3905   {
3906     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3907     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3908     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3909     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3910   },
3911
3912   /* PREFIX_0F5E */
3913   {
3914     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3915     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3916     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3917     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3918   },
3919
3920   /* PREFIX_0F5F */
3921   {
3922     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3923     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3924     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3925     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3926   },
3927
3928   /* PREFIX_0F60 */
3929   {
3930     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3931     { Bad_Opcode },
3932     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3933   },
3934
3935   /* PREFIX_0F61 */
3936   {
3937     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3938     { Bad_Opcode },
3939     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3940   },
3941
3942   /* PREFIX_0F62 */
3943   {
3944     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3945     { Bad_Opcode },
3946     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3947   },
3948
3949   /* PREFIX_0F6C */
3950   {
3951     { Bad_Opcode },
3952     { Bad_Opcode },
3953     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3954   },
3955
3956   /* PREFIX_0F6D */
3957   {
3958     { Bad_Opcode },
3959     { Bad_Opcode },
3960     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3961   },
3962
3963   /* PREFIX_0F6F */
3964   {
3965     { "movq",   { MX, EM }, PREFIX_OPCODE },
3966     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3967     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3968   },
3969
3970   /* PREFIX_0F70 */
3971   {
3972     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3973     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3974     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3975     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3976   },
3977
3978   /* PREFIX_0F73_REG_3 */
3979   {
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { "psrldq", { XS, Ib }, 0 },
3983   },
3984
3985   /* PREFIX_0F73_REG_7 */
3986   {
3987     { Bad_Opcode },
3988     { Bad_Opcode },
3989     { "pslldq", { XS, Ib }, 0 },
3990   },
3991
3992   /* PREFIX_0F78 */
3993   {
3994     {"vmread",  { Em, Gm }, 0 },
3995     { Bad_Opcode },
3996     {"extrq",   { XS, Ib, Ib }, 0 },
3997     {"insertq", { XM, XS, Ib, Ib }, 0 },
3998   },
3999
4000   /* PREFIX_0F79 */
4001   {
4002     {"vmwrite", { Gm, Em }, 0 },
4003     { Bad_Opcode },
4004     {"extrq",   { XM, XS }, 0 },
4005     {"insertq", { XM, XS }, 0 },
4006   },
4007
4008   /* PREFIX_0F7C */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4013     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4014   },
4015
4016   /* PREFIX_0F7D */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4021     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0F7E */
4025   {
4026     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4027     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4028     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4029   },
4030
4031   /* PREFIX_0F7F */
4032   {
4033     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4034     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4035     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0FAE_REG_0 */
4039   {
4040     { Bad_Opcode },
4041     { "rdfsbase", { Ev }, 0 },
4042   },
4043
4044   /* PREFIX_0FAE_REG_1 */
4045   {
4046     { Bad_Opcode },
4047     { "rdgsbase", { Ev }, 0 },
4048   },
4049
4050   /* PREFIX_0FAE_REG_2 */
4051   {
4052     { Bad_Opcode },
4053     { "wrfsbase", { Ev }, 0 },
4054   },
4055
4056   /* PREFIX_0FAE_REG_3 */
4057   {
4058     { Bad_Opcode },
4059     { "wrgsbase", { Ev }, 0 },
4060   },
4061
4062   /* PREFIX_0FAE_REG_6 */
4063   {
4064     { "xsaveopt",      { FXSAVE }, 0 },
4065     { Bad_Opcode },
4066     { "clwb",   { Mb }, 0 },
4067   },
4068
4069   /* PREFIX_0FAE_REG_7 */
4070   {
4071     { "clflush",        { Mb }, 0 },
4072     { Bad_Opcode },
4073     { "clflushopt",     { Mb }, 0 },
4074   },
4075
4076   /* PREFIX_RM_0_0FAE_REG_7 */
4077   {
4078     { "sfence",         { Skip_MODRM }, 0 },
4079     { Bad_Opcode },
4080     { "pcommit",                { Skip_MODRM }, 0 },
4081   },
4082
4083   /* PREFIX_0FB8 */
4084   {
4085     { Bad_Opcode },
4086     { "popcntS", { Gv, Ev }, 0 },
4087   },
4088
4089   /* PREFIX_0FBC */
4090   {
4091     { "bsfS",   { Gv, Ev }, 0 },
4092     { "tzcntS", { Gv, Ev }, 0 },
4093     { "bsfS",   { Gv, Ev }, 0 },
4094   },
4095
4096   /* PREFIX_0FBD */
4097   {
4098     { "bsrS",   { Gv, Ev }, 0 },
4099     { "lzcntS", { Gv, Ev }, 0 },
4100     { "bsrS",   { Gv, Ev }, 0 },
4101   },
4102
4103   /* PREFIX_0FC2 */
4104   {
4105     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4106     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4107     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4108     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4109   },
4110
4111   /* PREFIX_MOD_0_0FC3 */
4112   {
4113     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4114   },
4115
4116   /* PREFIX_MOD_0_0FC7_REG_6 */
4117   {
4118     { "vmptrld",{ Mq }, 0 },
4119     { "vmxon",  { Mq }, 0 },
4120     { "vmclear",{ Mq }, 0 },
4121   },
4122
4123   /* PREFIX_MOD_3_0FC7_REG_6 */
4124   {
4125     { "rdrand", { Ev }, 0 },
4126     { Bad_Opcode },
4127     { "rdrand", { Ev }, 0 }
4128   },
4129
4130   /* PREFIX_MOD_3_0FC7_REG_7 */
4131   {
4132     { "rdseed", { Ev }, 0 },
4133     { Bad_Opcode },
4134     { "rdseed", { Ev }, 0 },
4135   },
4136
4137   /* PREFIX_0FD0 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "addsubpd", { XM, EXx }, 0 },
4142     { "addsubps", { XM, EXx }, 0 },
4143   },
4144
4145   /* PREFIX_0FD6 */
4146   {
4147     { Bad_Opcode },
4148     { "movq2dq",{ XM, MS }, 0 },
4149     { "movq",   { EXqS, XM }, 0 },
4150     { "movdq2q",{ MX, XS }, 0 },
4151   },
4152
4153   /* PREFIX_0FE6 */
4154   {
4155     { Bad_Opcode },
4156     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4157     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4158     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4159   },
4160
4161   /* PREFIX_0FE7 */
4162   {
4163     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4164     { Bad_Opcode },
4165     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4166   },
4167
4168   /* PREFIX_0FF0 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4174   },
4175
4176   /* PREFIX_0FF7 */
4177   {
4178     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4179     { Bad_Opcode },
4180     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3810 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3814 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F3815 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3817 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3820 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3821 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3822 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3823 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3824 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3825 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3828 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3829 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F382A */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4272   },
4273
4274   /* PREFIX_0F382B */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F3830 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F3831 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F3832 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F3833 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F3834 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3835 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3837 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3838 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3839 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F383A */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F383B */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F383C */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F383D */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F383E */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F383F */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F3840 */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F3841 */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F3880 */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F3881 */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F3882 */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F38C8 */
4422   {
4423     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F38C9 */
4427   {
4428     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38CA */
4432   {
4433     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4434   },
4435
4436   /* PREFIX_0F38CB */
4437   {
4438     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F38CC */
4442   {
4443     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F38CD */
4447   {
4448     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4449   },
4450
4451   /* PREFIX_0F38DB */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4456   },
4457
4458   /* PREFIX_0F38DC */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4463   },
4464
4465   /* PREFIX_0F38DD */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4470   },
4471
4472   /* PREFIX_0F38DE */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4477   },
4478
4479   /* PREFIX_0F38DF */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F38F0 */
4487   {
4488     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4489     { Bad_Opcode },
4490     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4491     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F38F1 */
4495   {
4496     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4497     { Bad_Opcode },
4498     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4499     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F38F6 */
4503   {
4504     { Bad_Opcode },
4505     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4506     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4507     { Bad_Opcode },
4508   },
4509
4510   /* PREFIX_0F3A08 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A09 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A0A */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A0B */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A0C */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A0D */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A0E */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A14 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A15 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A16 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A17 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A20 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A21 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A22 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A40 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A41 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3A42 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3A44 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3A60 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3A61 */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3A62 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3A63 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3ACC */
4665   {
4666     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4667   },
4668
4669   /* PREFIX_0F3ADF */
4670   {
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4674   },
4675
4676   /* PREFIX_VEX_0F10 */
4677   {
4678     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4679     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4680     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4681     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4682   },
4683
4684   /* PREFIX_VEX_0F11 */
4685   {
4686     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4687     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4688     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4689     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4690   },
4691
4692   /* PREFIX_VEX_0F12 */
4693   {
4694     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4695     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4696     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4697     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4698   },
4699
4700   /* PREFIX_VEX_0F16 */
4701   {
4702     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4703     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4704     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4705   },
4706
4707   /* PREFIX_VEX_0F2A */
4708   {
4709     { Bad_Opcode },
4710     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4711     { Bad_Opcode },
4712     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4713   },
4714
4715   /* PREFIX_VEX_0F2C */
4716   {
4717     { Bad_Opcode },
4718     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4719     { Bad_Opcode },
4720     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4721   },
4722
4723   /* PREFIX_VEX_0F2D */
4724   {
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4729   },
4730
4731   /* PREFIX_VEX_0F2E */
4732   {
4733     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F2F */
4739   {
4740     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F41 */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F42 */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F44 */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F45 */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F46 */
4774   {
4775     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4776     { Bad_Opcode },
4777     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F47 */
4781   {
4782     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4783     { Bad_Opcode },
4784     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F4A */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4790     { Bad_Opcode },
4791     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F4B */
4795   {
4796     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4797     { Bad_Opcode },
4798     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4799   },
4800
4801   /* PREFIX_VEX_0F51 */
4802   {
4803     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4804     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4805     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4806     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4807   },
4808
4809   /* PREFIX_VEX_0F52 */
4810   {
4811     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4812     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4813   },
4814
4815   /* PREFIX_VEX_0F53 */
4816   {
4817     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4818     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4819   },
4820
4821   /* PREFIX_VEX_0F58 */
4822   {
4823     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4824     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4825     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4826     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4827   },
4828
4829   /* PREFIX_VEX_0F59 */
4830   {
4831     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4832     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4833     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4834     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4835   },
4836
4837   /* PREFIX_VEX_0F5A */
4838   {
4839     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4840     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4841     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4842     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4843   },
4844
4845   /* PREFIX_VEX_0F5B */
4846   {
4847     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4848     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4849     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4850   },
4851
4852   /* PREFIX_VEX_0F5C */
4853   {
4854     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4855     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4856     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4857     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4858   },
4859
4860   /* PREFIX_VEX_0F5D */
4861   {
4862     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4863     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4864     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4865     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4866   },
4867
4868   /* PREFIX_VEX_0F5E */
4869   {
4870     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4871     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4872     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4873     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4874   },
4875
4876   /* PREFIX_VEX_0F5F */
4877   {
4878     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4879     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4880     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4881     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4882   },
4883
4884   /* PREFIX_VEX_0F60 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4889   },
4890
4891   /* PREFIX_VEX_0F61 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4896   },
4897
4898   /* PREFIX_VEX_0F62 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_0F63 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0F64 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0F65 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F66 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0F67 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0F68 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0F69 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F6A */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0F6B */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_0F6C */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0F6D */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F6E */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4987   },
4988
4989   /* PREFIX_VEX_0F6F */
4990   {
4991     { Bad_Opcode },
4992     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4993     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4994   },
4995
4996   /* PREFIX_VEX_0F70 */
4997   {
4998     { Bad_Opcode },
4999     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5000     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5001     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5002   },
5003
5004   /* PREFIX_VEX_0F71_REG_2 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_0F71_REG_4 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_0F71_REG_6 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0F72_REG_2 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0F72_REG_4 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0F72_REG_6 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_0F73_REG_2 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0F73_REG_3 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F73_REG_6 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F73_REG_7 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F74 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_0F75 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_0F76 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F77 */
5096   {
5097     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5098   },
5099
5100   /* PREFIX_VEX_0F7C */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5105     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5106   },
5107
5108   /* PREFIX_VEX_0F7D */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5113     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5114   },
5115
5116   /* PREFIX_VEX_0F7E */
5117   {
5118     { Bad_Opcode },
5119     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5120     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_0F7F */
5124   {
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5127     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0F90 */
5131   {
5132     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0F91 */
5138   {
5139     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5140     { Bad_Opcode },
5141     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5142   },
5143
5144   /* PREFIX_VEX_0F92 */
5145   {
5146     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5147     { Bad_Opcode },
5148     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5149     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5150   },
5151
5152   /* PREFIX_VEX_0F93 */
5153   {
5154     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5157     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5158   },
5159
5160   /* PREFIX_VEX_0F98 */
5161   {
5162     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5163     { Bad_Opcode },
5164     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0F99 */
5168   {
5169     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5170     { Bad_Opcode },
5171     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5172   },
5173
5174   /* PREFIX_VEX_0FC2 */
5175   {
5176     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5177     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5178     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5179     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5180   },
5181
5182   /* PREFIX_VEX_0FC4 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0FC5 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5194   },
5195
5196   /* PREFIX_VEX_0FD0 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5201     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5202   },
5203
5204   /* PREFIX_VEX_0FD1 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0FD2 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0FD3 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0FD4 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0FD5 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FD6 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FD7 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5251   },
5252
5253   /* PREFIX_VEX_0FD8 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0FD9 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FDA */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0FDB */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0FDC */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0FDD */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0FDE */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0FDF */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5307   },
5308
5309   /* PREFIX_VEX_0FE0 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0FE1 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FE2 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0FE3 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0FE4 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0FE5 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0FE6 */
5352   {
5353     { Bad_Opcode },
5354     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5355     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5356     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5357   },
5358
5359   /* PREFIX_VEX_0FE7 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5364   },
5365
5366   /* PREFIX_VEX_0FE8 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5371   },
5372
5373   /* PREFIX_VEX_0FE9 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0FEA */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0FEB */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0FEC */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0FED */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0FEE */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0FEF */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0FF0 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5428   },
5429
5430   /* PREFIX_VEX_0FF1 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5435   },
5436
5437   /* PREFIX_VEX_0FF2 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5442   },
5443
5444   /* PREFIX_VEX_0FF3 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0FF4 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0FF5 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0FF6 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0FF7 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0FF8 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0FF9 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0FFA */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0FFB */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0FFC */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0FFD */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0FFE */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0F3800 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0F3801 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0F3802 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F3803 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F3804 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F3805 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F3806 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F3807 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F3808 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3809 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F380A */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F380B */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F380C */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F380D */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F380E */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F380F */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F3813 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5645   },
5646
5647   /* PREFIX_VEX_0F3816 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F3817 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F3818 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F3819 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F381A */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F381C */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F381D */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F381E */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F3820 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F3821 */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F3822 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F3823 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F3824 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3825 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3828 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3829 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F382A */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F382B */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F382C */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F382D */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F382E */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F382F */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F3830 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F3831 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F3832 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F3833 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F3834 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F3835 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F3836 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3837 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F3838 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3839 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F383A */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F383B */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F383C */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F383D */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F383E */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F383F */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F3840 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F3841 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F3845 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5932   },
5933
5934   /* PREFIX_VEX_0F3846 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F3847 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5946   },
5947
5948   /* PREFIX_VEX_0F3858 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F3859 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F385A */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5967   },
5968
5969   /* PREFIX_VEX_0F3878 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F3879 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F388C */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F388E */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5995   },
5996
5997   /* PREFIX_VEX_0F3890 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F3891 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F3892 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F3893 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F3896 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F3897 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F3898 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F3899 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F389A */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F389B */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F389C */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F389D */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F389E */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F389F */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F38A6 */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6100     { Bad_Opcode },
6101   },
6102
6103   /* PREFIX_VEX_0F38A7 */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38A8 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38A9 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38AA */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38AB */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38AC */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38AD */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38AE */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38AF */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38B6 */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38B7 */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38B8 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38B9 */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38BA */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38BB */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38BC */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38BD */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38BE */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38BF */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6234   },
6235
6236   /* PREFIX_VEX_0F38DB */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6241   },
6242
6243   /* PREFIX_VEX_0F38DC */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6248   },
6249
6250   /* PREFIX_VEX_0F38DD */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6255   },
6256
6257   /* PREFIX_VEX_0F38DE */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6262   },
6263
6264   /* PREFIX_VEX_0F38DF */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6269   },
6270
6271   /* PREFIX_VEX_0F38F2 */
6272   {
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6274   },
6275
6276   /* PREFIX_VEX_0F38F3_REG_1 */
6277   {
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6279   },
6280
6281   /* PREFIX_VEX_0F38F3_REG_2 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F3_REG_3 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6289   },
6290
6291   /* PREFIX_VEX_0F38F5 */
6292   {
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6297   },
6298
6299   /* PREFIX_VEX_0F38F6 */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6305   },
6306
6307   /* PREFIX_VEX_0F38F7 */
6308   {
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A00 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6320   },
6321
6322   /* PREFIX_VEX_0F3A01 */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A02 */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A04 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A05 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A06 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A08 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A09 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A0A */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A0B */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A0C */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A0D */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A0E */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A0F */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A14 */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A15 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A16 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A17 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A18 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A19 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A1D */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6460   },
6461
6462   /* PREFIX_VEX_0F3A20 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A21 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A22 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A30 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A31 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A32 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A33 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A38 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A39 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A40 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A41 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A42 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A44 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A46 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A48 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A49 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A4A */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A4B */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A4C */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A5C */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6600   },
6601
6602   /* PREFIX_VEX_0F3A5D */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6607   },
6608
6609   /* PREFIX_VEX_0F3A5E */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6614   },
6615
6616   /* PREFIX_VEX_0F3A5F */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A60 */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6628     { Bad_Opcode },
6629   },
6630
6631   /* PREFIX_VEX_0F3A61 */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A62 */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6643   },
6644
6645   /* PREFIX_VEX_0F3A63 */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6650   },
6651
6652   /* PREFIX_VEX_0F3A68 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6657   },
6658
6659   /* PREFIX_VEX_0F3A69 */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6664   },
6665
6666   /* PREFIX_VEX_0F3A6A */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A6B */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6678   },
6679
6680   /* PREFIX_VEX_0F3A6C */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A6D */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6692   },
6693
6694   /* PREFIX_VEX_0F3A6E */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3A6F */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6706   },
6707
6708   /* PREFIX_VEX_0F3A78 */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6713   },
6714
6715   /* PREFIX_VEX_0F3A79 */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6720   },
6721
6722   /* PREFIX_VEX_0F3A7A */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6727   },
6728
6729   /* PREFIX_VEX_0F3A7B */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6734   },
6735
6736   /* PREFIX_VEX_0F3A7C */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6741     { Bad_Opcode },
6742   },
6743
6744   /* PREFIX_VEX_0F3A7D */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6749   },
6750
6751   /* PREFIX_VEX_0F3A7E */
6752   {
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6756   },
6757
6758   /* PREFIX_VEX_0F3A7F */
6759   {
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6763   },
6764
6765   /* PREFIX_VEX_0F3ADF */
6766   {
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6770   },
6771
6772   /* PREFIX_VEX_0F3AF0 */
6773   {
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6778   },
6779
6780 #define NEED_PREFIX_TABLE
6781 #include "i386-dis-evex.h"
6782 #undef NEED_PREFIX_TABLE
6783 };
6784
6785 static const struct dis386 x86_64_table[][2] = {
6786   /* X86_64_06 */
6787   {
6788     { "pushP", { es }, 0 },
6789   },
6790
6791   /* X86_64_07 */
6792   {
6793     { "popP", { es }, 0 },
6794   },
6795
6796   /* X86_64_0D */
6797   {
6798     { "pushP", { cs }, 0 },
6799   },
6800
6801   /* X86_64_16 */
6802   {
6803     { "pushP", { ss }, 0 },
6804   },
6805
6806   /* X86_64_17 */
6807   {
6808     { "popP", { ss }, 0 },
6809   },
6810
6811   /* X86_64_1E */
6812   {
6813     { "pushP", { ds }, 0 },
6814   },
6815
6816   /* X86_64_1F */
6817   {
6818     { "popP", { ds }, 0 },
6819   },
6820
6821   /* X86_64_27 */
6822   {
6823     { "daa", { XX }, 0 },
6824   },
6825
6826   /* X86_64_2F */
6827   {
6828     { "das", { XX }, 0 },
6829   },
6830
6831   /* X86_64_37 */
6832   {
6833     { "aaa", { XX }, 0 },
6834   },
6835
6836   /* X86_64_3F */
6837   {
6838     { "aas", { XX }, 0 },
6839   },
6840
6841   /* X86_64_60 */
6842   {
6843     { "pushaP", { XX }, 0 },
6844   },
6845
6846   /* X86_64_61 */
6847   {
6848     { "popaP", { XX }, 0 },
6849   },
6850
6851   /* X86_64_62 */
6852   {
6853     { MOD_TABLE (MOD_62_32BIT) },
6854     { EVEX_TABLE (EVEX_0F) },
6855   },
6856
6857   /* X86_64_63 */
6858   {
6859     { "arpl", { Ew, Gw }, 0 },
6860     { "movs{lq|xd}", { Gv, Ed }, 0 },
6861   },
6862
6863   /* X86_64_6D */
6864   {
6865     { "ins{R|}", { Yzr, indirDX }, 0 },
6866     { "ins{G|}", { Yzr, indirDX }, 0 },
6867   },
6868
6869   /* X86_64_6F */
6870   {
6871     { "outs{R|}", { indirDXr, Xz }, 0 },
6872     { "outs{G|}", { indirDXr, Xz }, 0 },
6873   },
6874
6875   /* X86_64_9A */
6876   {
6877     { "Jcall{T|}", { Ap }, 0 },
6878   },
6879
6880   /* X86_64_C4 */
6881   {
6882     { MOD_TABLE (MOD_C4_32BIT) },
6883     { VEX_C4_TABLE (VEX_0F) },
6884   },
6885
6886   /* X86_64_C5 */
6887   {
6888     { MOD_TABLE (MOD_C5_32BIT) },
6889     { VEX_C5_TABLE (VEX_0F) },
6890   },
6891
6892   /* X86_64_CE */
6893   {
6894     { "into", { XX }, 0 },
6895   },
6896
6897   /* X86_64_D4 */
6898   {
6899     { "aam", { Ib }, 0 },
6900   },
6901
6902   /* X86_64_D5 */
6903   {
6904     { "aad", { Ib }, 0 },
6905   },
6906
6907   /* X86_64_E8 */
6908   {
6909     { "callP",          { Jv, BND }, 0 },
6910     { "call@",          { Jv, BND }, 0 }
6911   },
6912
6913   /* X86_64_E9 */
6914   {
6915     { "jmpP",           { Jv, BND }, 0 },
6916     { "jmp@",           { Jv, BND }, 0 }
6917   },
6918
6919   /* X86_64_EA */
6920   {
6921     { "Jjmp{T|}", { Ap }, 0 },
6922   },
6923
6924   /* X86_64_0F01_REG_0 */
6925   {
6926     { "sgdt{Q|IQ}", { M }, 0 },
6927     { "sgdt", { M }, 0 },
6928   },
6929
6930   /* X86_64_0F01_REG_1 */
6931   {
6932     { "sidt{Q|IQ}", { M }, 0 },
6933     { "sidt", { M }, 0 },
6934   },
6935
6936   /* X86_64_0F01_REG_2 */
6937   {
6938     { "lgdt{Q|Q}", { M }, 0 },
6939     { "lgdt", { M }, 0 },
6940   },
6941
6942   /* X86_64_0F01_REG_3 */
6943   {
6944     { "lidt{Q|Q}", { M }, 0 },
6945     { "lidt", { M }, 0 },
6946   },
6947 };
6948
6949 static const struct dis386 three_byte_table[][256] = {
6950
6951   /* THREE_BYTE_0F38 */
6952   {
6953     /* 00 */
6954     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6955     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6956     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6957     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6958     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6959     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6960     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6961     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6962     /* 08 */
6963     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6964     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6965     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6966     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 10 */
6972     { PREFIX_TABLE (PREFIX_0F3810) },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { PREFIX_TABLE (PREFIX_0F3814) },
6977     { PREFIX_TABLE (PREFIX_0F3815) },
6978     { Bad_Opcode },
6979     { PREFIX_TABLE (PREFIX_0F3817) },
6980     /* 18 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6986     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6987     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6988     { Bad_Opcode },
6989     /* 20 */
6990     { PREFIX_TABLE (PREFIX_0F3820) },
6991     { PREFIX_TABLE (PREFIX_0F3821) },
6992     { PREFIX_TABLE (PREFIX_0F3822) },
6993     { PREFIX_TABLE (PREFIX_0F3823) },
6994     { PREFIX_TABLE (PREFIX_0F3824) },
6995     { PREFIX_TABLE (PREFIX_0F3825) },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 28 */
6999     { PREFIX_TABLE (PREFIX_0F3828) },
7000     { PREFIX_TABLE (PREFIX_0F3829) },
7001     { PREFIX_TABLE (PREFIX_0F382A) },
7002     { PREFIX_TABLE (PREFIX_0F382B) },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 30 */
7008     { PREFIX_TABLE (PREFIX_0F3830) },
7009     { PREFIX_TABLE (PREFIX_0F3831) },
7010     { PREFIX_TABLE (PREFIX_0F3832) },
7011     { PREFIX_TABLE (PREFIX_0F3833) },
7012     { PREFIX_TABLE (PREFIX_0F3834) },
7013     { PREFIX_TABLE (PREFIX_0F3835) },
7014     { Bad_Opcode },
7015     { PREFIX_TABLE (PREFIX_0F3837) },
7016     /* 38 */
7017     { PREFIX_TABLE (PREFIX_0F3838) },
7018     { PREFIX_TABLE (PREFIX_0F3839) },
7019     { PREFIX_TABLE (PREFIX_0F383A) },
7020     { PREFIX_TABLE (PREFIX_0F383B) },
7021     { PREFIX_TABLE (PREFIX_0F383C) },
7022     { PREFIX_TABLE (PREFIX_0F383D) },
7023     { PREFIX_TABLE (PREFIX_0F383E) },
7024     { PREFIX_TABLE (PREFIX_0F383F) },
7025     /* 40 */
7026     { PREFIX_TABLE (PREFIX_0F3840) },
7027     { PREFIX_TABLE (PREFIX_0F3841) },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* 48 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* 50 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 58 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 60 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* 68 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* 70 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* 78 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* 80 */
7098     { PREFIX_TABLE (PREFIX_0F3880) },
7099     { PREFIX_TABLE (PREFIX_0F3881) },
7100     { PREFIX_TABLE (PREFIX_0F3882) },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* 88 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 90 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 98 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* a0 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* a8 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* b0 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* b8 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* c0 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* c8 */
7179     { PREFIX_TABLE (PREFIX_0F38C8) },
7180     { PREFIX_TABLE (PREFIX_0F38C9) },
7181     { PREFIX_TABLE (PREFIX_0F38CA) },
7182     { PREFIX_TABLE (PREFIX_0F38CB) },
7183     { PREFIX_TABLE (PREFIX_0F38CC) },
7184     { PREFIX_TABLE (PREFIX_0F38CD) },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* d0 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* d8 */
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { PREFIX_TABLE (PREFIX_0F38DB) },
7201     { PREFIX_TABLE (PREFIX_0F38DC) },
7202     { PREFIX_TABLE (PREFIX_0F38DD) },
7203     { PREFIX_TABLE (PREFIX_0F38DE) },
7204     { PREFIX_TABLE (PREFIX_0F38DF) },
7205     /* e0 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* e8 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     /* f0 */
7224     { PREFIX_TABLE (PREFIX_0F38F0) },
7225     { PREFIX_TABLE (PREFIX_0F38F1) },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { PREFIX_TABLE (PREFIX_0F38F6) },
7231     { Bad_Opcode },
7232     /* f8 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241   },
7242   /* THREE_BYTE_0F3A */
7243   {
7244     /* 00 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* 08 */
7254     { PREFIX_TABLE (PREFIX_0F3A08) },
7255     { PREFIX_TABLE (PREFIX_0F3A09) },
7256     { PREFIX_TABLE (PREFIX_0F3A0A) },
7257     { PREFIX_TABLE (PREFIX_0F3A0B) },
7258     { PREFIX_TABLE (PREFIX_0F3A0C) },
7259     { PREFIX_TABLE (PREFIX_0F3A0D) },
7260     { PREFIX_TABLE (PREFIX_0F3A0E) },
7261     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7262     /* 10 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { PREFIX_TABLE (PREFIX_0F3A14) },
7268     { PREFIX_TABLE (PREFIX_0F3A15) },
7269     { PREFIX_TABLE (PREFIX_0F3A16) },
7270     { PREFIX_TABLE (PREFIX_0F3A17) },
7271     /* 18 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 20 */
7281     { PREFIX_TABLE (PREFIX_0F3A20) },
7282     { PREFIX_TABLE (PREFIX_0F3A21) },
7283     { PREFIX_TABLE (PREFIX_0F3A22) },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 28 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 30 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 38 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 40 */
7317     { PREFIX_TABLE (PREFIX_0F3A40) },
7318     { PREFIX_TABLE (PREFIX_0F3A41) },
7319     { PREFIX_TABLE (PREFIX_0F3A42) },
7320     { Bad_Opcode },
7321     { PREFIX_TABLE (PREFIX_0F3A44) },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 48 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 50 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 58 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 60 */
7353     { PREFIX_TABLE (PREFIX_0F3A60) },
7354     { PREFIX_TABLE (PREFIX_0F3A61) },
7355     { PREFIX_TABLE (PREFIX_0F3A62) },
7356     { PREFIX_TABLE (PREFIX_0F3A63) },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 68 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 70 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 78 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 80 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* 88 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* 90 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 98 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* a0 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* a8 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* b0 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* b8 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* c0 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* c8 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { PREFIX_TABLE (PREFIX_0F3ACC) },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* d0 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* d8 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { PREFIX_TABLE (PREFIX_0F3ADF) },
7496     /* e0 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* e8 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* f0 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* f8 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532   },
7533
7534   /* THREE_BYTE_0F7A */
7535   {
7536     /* 00 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* 08 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* 10 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* 18 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     /* 20 */
7573     { "ptest",          { XX }, PREFIX_OPCODE },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     /* 28 */
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     /* 30 */
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     /* 38 */
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     /* 40 */
7609     { Bad_Opcode },
7610     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7611     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7612     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7616     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7617     /* 48 */
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     /* 50 */
7627     { Bad_Opcode },
7628     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7629     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7630     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7634     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7635     /* 58 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     /* 60 */
7645     { Bad_Opcode },
7646     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7647     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7648     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     /* 68 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     /* 70 */
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* 78 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     /* 80 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     /* 88 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     /* 90 */
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     /* 98 */
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     /* a0 */
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     /* a8 */
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     /* b0 */
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     /* b8 */
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     /* c0 */
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     /* c8 */
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     /* d0 */
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     /* d8 */
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     /* e0 */
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     /* e8 */
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     /* f0 */
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     /* f8 */
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824   },
7825 };
7826
7827 static const struct dis386 xop_table[][256] = {
7828   /* XOP_08 */
7829   {
7830     /* 00 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 08 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 10 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 18 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 20 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 28 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 30 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 38 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 40 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 48 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* 50 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 58 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 60 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 68 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* 70 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* 78 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* 80 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7981     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7982     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7983     /* 88 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7991     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7992     /* 90 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7999     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8000     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8001     /* 98 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8009     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8010     /* a0 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8014     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8018     { Bad_Opcode },
8019     /* a8 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* b0 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8036     { Bad_Opcode },
8037     /* b8 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* c0 */
8047     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
8048     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
8049     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
8050     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* c8 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8061     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8063     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8064     /* d0 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* d8 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* e0 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* e8 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8097     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8098     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8099     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8100     /* f0 */
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* f8 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118   },
8119   /* XOP_09 */
8120   {
8121     /* 00 */
8122     { Bad_Opcode },
8123     { REG_TABLE (REG_XOP_TBM_01) },
8124     { REG_TABLE (REG_XOP_TBM_02) },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 08 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 10 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { REG_TABLE (REG_XOP_LWPCB) },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 18 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 20 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 28 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 30 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 38 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 40 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 48 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 50 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 58 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* 60 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* 68 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* 70 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* 78 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* 80 */
8266     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8267     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8268     { "vfrczss",        { XM, EXd }, 0 },
8269     { "vfrczsd",        { XM, EXq }, 0 },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* 88 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* 90 */
8284     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8285     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8286     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8287     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8288     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8289     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8290     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8291     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8292     /* 98 */
8293     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8294     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8295     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8296     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* a0 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* a8 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* b0 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* b8 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* c0 */
8338     { Bad_Opcode },
8339     { "vphaddbw",       { XM, EXxmm }, 0 },
8340     { "vphaddbd",       { XM, EXxmm }, 0 },
8341     { "vphaddbq",       { XM, EXxmm }, 0 },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { "vphaddwd",       { XM, EXxmm }, 0 },
8345     { "vphaddwq",       { XM, EXxmm }, 0 },
8346     /* c8 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { "vphadddq",       { XM, EXxmm }, 0 },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* d0 */
8356     { Bad_Opcode },
8357     { "vphaddubw",      { XM, EXxmm }, 0 },
8358     { "vphaddubd",      { XM, EXxmm }, 0 },
8359     { "vphaddubq",      { XM, EXxmm }, 0 },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { "vphadduwd",      { XM, EXxmm }, 0 },
8363     { "vphadduwq",      { XM, EXxmm }, 0 },
8364     /* d8 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { "vphaddudq",      { XM, EXxmm }, 0 },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* e0 */
8374     { Bad_Opcode },
8375     { "vphsubbw",       { XM, EXxmm }, 0 },
8376     { "vphsubwd",       { XM, EXxmm }, 0 },
8377     { "vphsubdq",       { XM, EXxmm }, 0 },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* e8 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* f0 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* f8 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409   },
8410   /* XOP_0A */
8411   {
8412     /* 00 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* 08 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* 10 */
8431     { "bextr",  { Gv, Ev, Iq }, 0 },
8432     { Bad_Opcode },
8433     { REG_TABLE (REG_XOP_LWP) },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* 18 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* 20 */
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     /* 28 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     /* 30 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* 38 */
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     /* 40 */
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     /* 48 */
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     /* 50 */
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     /* 58 */
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     /* 60 */
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     /* 68 */
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     /* 70 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     /* 78 */
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     /* 80 */
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     /* 88 */
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     /* 90 */
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     /* 98 */
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     /* a0 */
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     /* a8 */
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     /* b0 */
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     /* b8 */
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     /* c0 */
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     /* c8 */
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     /* d0 */
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     /* d8 */
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     /* e0 */
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     /* e8 */
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     /* f0 */
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     /* f8 */
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700   },
8701 };
8702
8703 static const struct dis386 vex_table[][256] = {
8704   /* VEX_0F */
8705   {
8706     /* 00 */
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     /* 08 */
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     /* 10 */
8725     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8728     { MOD_TABLE (MOD_VEX_0F13) },
8729     { VEX_W_TABLE (VEX_W_0F14) },
8730     { VEX_W_TABLE (VEX_W_0F15) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8732     { MOD_TABLE (MOD_VEX_0F17) },
8733     /* 18 */
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     /* 20 */
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     /* 28 */
8752     { VEX_W_TABLE (VEX_W_0F28) },
8753     { VEX_W_TABLE (VEX_W_0F29) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8755     { MOD_TABLE (MOD_VEX_0F2B) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8760     /* 30 */
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     /* 38 */
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     /* 40 */
8779     { Bad_Opcode },
8780     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8782     { Bad_Opcode },
8783     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8787     /* 48 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     /* 50 */
8797     { MOD_TABLE (MOD_VEX_0F50) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8801     { "vandpX",         { XM, Vex, EXx }, 0 },
8802     { "vandnpX",        { XM, Vex, EXx }, 0 },
8803     { "vorpX",          { XM, Vex, EXx }, 0 },
8804     { "vxorpX",         { XM, Vex, EXx }, 0 },
8805     /* 58 */
8806     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8814     /* 60 */
8815     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8823     /* 68 */
8824     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8832     /* 70 */
8833     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8834     { REG_TABLE (REG_VEX_0F71) },
8835     { REG_TABLE (REG_VEX_0F72) },
8836     { REG_TABLE (REG_VEX_0F73) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8841     /* 78 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8850     /* 80 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* 88 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* 90 */
8869     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     /* 98 */
8878     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     /* a0 */
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     /* a8 */
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { REG_TABLE (REG_VEX_0FAE) },
8903     { Bad_Opcode },
8904     /* b0 */
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     /* b8 */
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     /* c0 */
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8926     { Bad_Opcode },
8927     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8928     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8929     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8930     { Bad_Opcode },
8931     /* c8 */
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     /* d0 */
8941     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8942     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8943     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8944     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8945     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8946     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8947     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8948     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8949     /* d8 */
8950     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8951     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8952     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8953     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8954     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8955     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8956     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8957     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8958     /* e0 */
8959     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8960     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8961     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8962     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8963     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8964     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8965     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8966     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8967     /* e8 */
8968     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8969     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8970     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8971     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8972     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8973     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8974     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8975     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8976     /* f0 */
8977     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8978     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8979     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8980     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8981     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8982     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8983     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8984     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8985     /* f8 */
8986     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8987     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8988     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8989     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8990     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8991     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8992     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8993     { Bad_Opcode },
8994   },
8995   /* VEX_0F38 */
8996   {
8997     /* 00 */
8998     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9006     /* 08 */
9007     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9015     /* 10 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9024     /* 18 */
9025     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9028     { Bad_Opcode },
9029     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9032     { Bad_Opcode },
9033     /* 20 */
9034     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     /* 28 */
9043     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9051     /* 30 */
9052     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9060     /* 38 */
9061     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9069     /* 40 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9078     /* 48 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* 50 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* 58 */
9097     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* 60 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* 68 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* 70 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* 78 */
9133     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* 80 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* 88 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9156     { Bad_Opcode },
9157     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9158     { Bad_Opcode },
9159     /* 90 */
9160     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9162     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9168     /* 98 */
9169     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9177     /* a0 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9186     /* a8 */
9187     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9195     /* b0 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9204     /* b8 */
9205     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9207     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9208     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9213     /* c0 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* c8 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* d0 */
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* d8 */
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9249     /* e0 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* e8 */
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     /* f0 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9271     { REG_TABLE (REG_VEX_0F38F3) },
9272     { Bad_Opcode },
9273     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9274     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9275     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9276     /* f8 */
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285   },
9286   /* VEX_0F3A */
9287   {
9288     /* 00 */
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9292     { Bad_Opcode },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9296     { Bad_Opcode },
9297     /* 08 */
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9305     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9306     /* 10 */
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9315     /* 18 */
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     /* 20 */
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     /* 28 */
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     /* 30 */
9343     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9344     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     /* 38 */
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9353     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     /* 40 */
9361     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9362     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9363     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9364     { Bad_Opcode },
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9366     { Bad_Opcode },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9368     { Bad_Opcode },
9369     /* 48 */
9370     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9371     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9372     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9373     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     /* 50 */
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     /* 58 */
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9393     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9394     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9395     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9396     /* 60 */
9397     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9398     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9399     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9400     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     /* 68 */
9406     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9407     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9408     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9409     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9410     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9411     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9412     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9413     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9414     /* 70 */
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     /* 78 */
9424     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9425     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9426     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9427     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9428     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9429     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9430     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9431     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9432     /* 80 */
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     /* 88 */
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     /* 90 */
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     /* 98 */
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     /* a0 */
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     /* a8 */
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     /* b0 */
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     /* b8 */
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     { Bad_Opcode },
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     /* c0 */
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     { Bad_Opcode },
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     /* c8 */
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     { Bad_Opcode },
9517     { Bad_Opcode },
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521     { Bad_Opcode },
9522     /* d0 */
9523     { Bad_Opcode },
9524     { Bad_Opcode },
9525     { Bad_Opcode },
9526     { Bad_Opcode },
9527     { Bad_Opcode },
9528     { Bad_Opcode },
9529     { Bad_Opcode },
9530     { Bad_Opcode },
9531     /* d8 */
9532     { Bad_Opcode },
9533     { Bad_Opcode },
9534     { Bad_Opcode },
9535     { Bad_Opcode },
9536     { Bad_Opcode },
9537     { Bad_Opcode },
9538     { Bad_Opcode },
9539     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9540     /* e0 */
9541     { Bad_Opcode },
9542     { Bad_Opcode },
9543     { Bad_Opcode },
9544     { Bad_Opcode },
9545     { Bad_Opcode },
9546     { Bad_Opcode },
9547     { Bad_Opcode },
9548     { Bad_Opcode },
9549     /* e8 */
9550     { Bad_Opcode },
9551     { Bad_Opcode },
9552     { Bad_Opcode },
9553     { Bad_Opcode },
9554     { Bad_Opcode },
9555     { Bad_Opcode },
9556     { Bad_Opcode },
9557     { Bad_Opcode },
9558     /* f0 */
9559     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9560     { Bad_Opcode },
9561     { Bad_Opcode },
9562     { Bad_Opcode },
9563     { Bad_Opcode },
9564     { Bad_Opcode },
9565     { Bad_Opcode },
9566     { Bad_Opcode },
9567     /* f8 */
9568     { Bad_Opcode },
9569     { Bad_Opcode },
9570     { Bad_Opcode },
9571     { Bad_Opcode },
9572     { Bad_Opcode },
9573     { Bad_Opcode },
9574     { Bad_Opcode },
9575     { Bad_Opcode },
9576   },
9577 };
9578
9579 #define NEED_OPCODE_TABLE
9580 #include "i386-dis-evex.h"
9581 #undef NEED_OPCODE_TABLE
9582 static const struct dis386 vex_len_table[][2] = {
9583   /* VEX_LEN_0F10_P_1 */
9584   {
9585     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9586     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9587   },
9588
9589   /* VEX_LEN_0F10_P_3 */
9590   {
9591     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9592     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9593   },
9594
9595   /* VEX_LEN_0F11_P_1 */
9596   {
9597     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9598     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9599   },
9600
9601   /* VEX_LEN_0F11_P_3 */
9602   {
9603     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9604     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9605   },
9606
9607   /* VEX_LEN_0F12_P_0_M_0 */
9608   {
9609     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9610   },
9611
9612   /* VEX_LEN_0F12_P_0_M_1 */
9613   {
9614     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9615   },
9616
9617   /* VEX_LEN_0F12_P_2 */
9618   {
9619     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9620   },
9621
9622   /* VEX_LEN_0F13_M_0 */
9623   {
9624     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9625   },
9626
9627   /* VEX_LEN_0F16_P_0_M_0 */
9628   {
9629     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9630   },
9631
9632   /* VEX_LEN_0F16_P_0_M_1 */
9633   {
9634     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9635   },
9636
9637   /* VEX_LEN_0F16_P_2 */
9638   {
9639     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9640   },
9641
9642   /* VEX_LEN_0F17_M_0 */
9643   {
9644     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9645   },
9646
9647   /* VEX_LEN_0F2A_P_1 */
9648   {
9649     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9650     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9651   },
9652
9653   /* VEX_LEN_0F2A_P_3 */
9654   {
9655     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9656     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F2C_P_1 */
9660   {
9661     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9662     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9663   },
9664
9665   /* VEX_LEN_0F2C_P_3 */
9666   {
9667     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9668     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9669   },
9670
9671   /* VEX_LEN_0F2D_P_1 */
9672   {
9673     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9674     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9675   },
9676
9677   /* VEX_LEN_0F2D_P_3 */
9678   {
9679     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9680     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9681   },
9682
9683   /* VEX_LEN_0F2E_P_0 */
9684   {
9685     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9686     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9687   },
9688
9689   /* VEX_LEN_0F2E_P_2 */
9690   {
9691     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9692     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9693   },
9694
9695   /* VEX_LEN_0F2F_P_0 */
9696   {
9697     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9698     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9699   },
9700
9701   /* VEX_LEN_0F2F_P_2 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9704     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9705   },
9706
9707   /* VEX_LEN_0F41_P_0 */
9708   {
9709     { Bad_Opcode },
9710     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9711   },
9712   /* VEX_LEN_0F41_P_2 */
9713   {
9714     { Bad_Opcode },
9715     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9716   },
9717   /* VEX_LEN_0F42_P_0 */
9718   {
9719     { Bad_Opcode },
9720     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9721   },
9722   /* VEX_LEN_0F42_P_2 */
9723   {
9724     { Bad_Opcode },
9725     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9726   },
9727   /* VEX_LEN_0F44_P_0 */
9728   {
9729     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9730   },
9731   /* VEX_LEN_0F44_P_2 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9734   },
9735   /* VEX_LEN_0F45_P_0 */
9736   {
9737     { Bad_Opcode },
9738     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9739   },
9740   /* VEX_LEN_0F45_P_2 */
9741   {
9742     { Bad_Opcode },
9743     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9744   },
9745   /* VEX_LEN_0F46_P_0 */
9746   {
9747     { Bad_Opcode },
9748     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9749   },
9750   /* VEX_LEN_0F46_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9754   },
9755   /* VEX_LEN_0F47_P_0 */
9756   {
9757     { Bad_Opcode },
9758     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9759   },
9760   /* VEX_LEN_0F47_P_2 */
9761   {
9762     { Bad_Opcode },
9763     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9764   },
9765   /* VEX_LEN_0F4A_P_0 */
9766   {
9767     { Bad_Opcode },
9768     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9769   },
9770   /* VEX_LEN_0F4A_P_2 */
9771   {
9772     { Bad_Opcode },
9773     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9774   },
9775   /* VEX_LEN_0F4B_P_0 */
9776   {
9777     { Bad_Opcode },
9778     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9779   },
9780   /* VEX_LEN_0F4B_P_2 */
9781   {
9782     { Bad_Opcode },
9783     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9784   },
9785
9786   /* VEX_LEN_0F51_P_1 */
9787   {
9788     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9789     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9790   },
9791
9792   /* VEX_LEN_0F51_P_3 */
9793   {
9794     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9795     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9796   },
9797
9798   /* VEX_LEN_0F52_P_1 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9801     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9802   },
9803
9804   /* VEX_LEN_0F53_P_1 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9807     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9808   },
9809
9810   /* VEX_LEN_0F58_P_1 */
9811   {
9812     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9813     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9814   },
9815
9816   /* VEX_LEN_0F58_P_3 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9819     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9820   },
9821
9822   /* VEX_LEN_0F59_P_1 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9825     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9826   },
9827
9828   /* VEX_LEN_0F59_P_3 */
9829   {
9830     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9831     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9832   },
9833
9834   /* VEX_LEN_0F5A_P_1 */
9835   {
9836     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9837     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9838   },
9839
9840   /* VEX_LEN_0F5A_P_3 */
9841   {
9842     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9843     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9844   },
9845
9846   /* VEX_LEN_0F5C_P_1 */
9847   {
9848     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9849     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9850   },
9851
9852   /* VEX_LEN_0F5C_P_3 */
9853   {
9854     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9855     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9856   },
9857
9858   /* VEX_LEN_0F5D_P_1 */
9859   {
9860     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9861     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9862   },
9863
9864   /* VEX_LEN_0F5D_P_3 */
9865   {
9866     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9867     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9868   },
9869
9870   /* VEX_LEN_0F5E_P_1 */
9871   {
9872     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9873     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9874   },
9875
9876   /* VEX_LEN_0F5E_P_3 */
9877   {
9878     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9879     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9880   },
9881
9882   /* VEX_LEN_0F5F_P_1 */
9883   {
9884     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9885     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9886   },
9887
9888   /* VEX_LEN_0F5F_P_3 */
9889   {
9890     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9891     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9892   },
9893
9894   /* VEX_LEN_0F6E_P_2 */
9895   {
9896     { "vmovK",          { XMScalar, Edq }, 0 },
9897     { "vmovK",          { XMScalar, Edq }, 0 },
9898   },
9899
9900   /* VEX_LEN_0F7E_P_1 */
9901   {
9902     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9903     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9904   },
9905
9906   /* VEX_LEN_0F7E_P_2 */
9907   {
9908     { "vmovK",          { Edq, XMScalar }, 0 },
9909     { "vmovK",          { Edq, XMScalar }, 0 },
9910   },
9911
9912   /* VEX_LEN_0F90_P_0 */
9913   {
9914     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9915   },
9916
9917   /* VEX_LEN_0F90_P_2 */
9918   {
9919     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9920   },
9921
9922   /* VEX_LEN_0F91_P_0 */
9923   {
9924     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9925   },
9926
9927   /* VEX_LEN_0F91_P_2 */
9928   {
9929     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9930   },
9931
9932   /* VEX_LEN_0F92_P_0 */
9933   {
9934     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9935   },
9936
9937   /* VEX_LEN_0F92_P_2 */
9938   {
9939     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9940   },
9941
9942   /* VEX_LEN_0F92_P_3 */
9943   {
9944     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9945   },
9946
9947   /* VEX_LEN_0F93_P_0 */
9948   {
9949     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9950   },
9951
9952   /* VEX_LEN_0F93_P_2 */
9953   {
9954     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9955   },
9956
9957   /* VEX_LEN_0F93_P_3 */
9958   {
9959     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9960   },
9961
9962   /* VEX_LEN_0F98_P_0 */
9963   {
9964     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9965   },
9966
9967   /* VEX_LEN_0F98_P_2 */
9968   {
9969     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9970   },
9971
9972   /* VEX_LEN_0F99_P_0 */
9973   {
9974     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9975   },
9976
9977   /* VEX_LEN_0F99_P_2 */
9978   {
9979     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9980   },
9981
9982   /* VEX_LEN_0FAE_R_2_M_0 */
9983   {
9984     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9985   },
9986
9987   /* VEX_LEN_0FAE_R_3_M_0 */
9988   {
9989     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9990   },
9991
9992   /* VEX_LEN_0FC2_P_1 */
9993   {
9994     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9995     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9996   },
9997
9998   /* VEX_LEN_0FC2_P_3 */
9999   {
10000     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10001     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10002   },
10003
10004   /* VEX_LEN_0FC4_P_2 */
10005   {
10006     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10007   },
10008
10009   /* VEX_LEN_0FC5_P_2 */
10010   {
10011     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10012   },
10013
10014   /* VEX_LEN_0FD6_P_2 */
10015   {
10016     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10017     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10018   },
10019
10020   /* VEX_LEN_0FF7_P_2 */
10021   {
10022     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10023   },
10024
10025   /* VEX_LEN_0F3816_P_2 */
10026   {
10027     { Bad_Opcode },
10028     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10029   },
10030
10031   /* VEX_LEN_0F3819_P_2 */
10032   {
10033     { Bad_Opcode },
10034     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10035   },
10036
10037   /* VEX_LEN_0F381A_P_2_M_0 */
10038   {
10039     { Bad_Opcode },
10040     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10041   },
10042
10043   /* VEX_LEN_0F3836_P_2 */
10044   {
10045     { Bad_Opcode },
10046     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10047   },
10048
10049   /* VEX_LEN_0F3841_P_2 */
10050   {
10051     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10052   },
10053
10054   /* VEX_LEN_0F385A_P_2_M_0 */
10055   {
10056     { Bad_Opcode },
10057     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10058   },
10059
10060   /* VEX_LEN_0F38DB_P_2 */
10061   {
10062     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10063   },
10064
10065   /* VEX_LEN_0F38DC_P_2 */
10066   {
10067     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10068   },
10069
10070   /* VEX_LEN_0F38DD_P_2 */
10071   {
10072     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10073   },
10074
10075   /* VEX_LEN_0F38DE_P_2 */
10076   {
10077     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10078   },
10079
10080   /* VEX_LEN_0F38DF_P_2 */
10081   {
10082     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F38F2_P_0 */
10086   {
10087     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10088   },
10089
10090   /* VEX_LEN_0F38F3_R_1_P_0 */
10091   {
10092     { "blsrS",          { VexGdq, Edq }, 0 },
10093   },
10094
10095   /* VEX_LEN_0F38F3_R_2_P_0 */
10096   {
10097     { "blsmskS",        { VexGdq, Edq }, 0 },
10098   },
10099
10100   /* VEX_LEN_0F38F3_R_3_P_0 */
10101   {
10102     { "blsiS",          { VexGdq, Edq }, 0 },
10103   },
10104
10105   /* VEX_LEN_0F38F5_P_0 */
10106   {
10107     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10108   },
10109
10110   /* VEX_LEN_0F38F5_P_1 */
10111   {
10112     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10113   },
10114
10115   /* VEX_LEN_0F38F5_P_3 */
10116   {
10117     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10118   },
10119
10120   /* VEX_LEN_0F38F6_P_3 */
10121   {
10122     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10123   },
10124
10125   /* VEX_LEN_0F38F7_P_0 */
10126   {
10127     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10128   },
10129
10130   /* VEX_LEN_0F38F7_P_1 */
10131   {
10132     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10133   },
10134
10135   /* VEX_LEN_0F38F7_P_2 */
10136   {
10137     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10138   },
10139
10140   /* VEX_LEN_0F38F7_P_3 */
10141   {
10142     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10143   },
10144
10145   /* VEX_LEN_0F3A00_P_2 */
10146   {
10147     { Bad_Opcode },
10148     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10149   },
10150
10151   /* VEX_LEN_0F3A01_P_2 */
10152   {
10153     { Bad_Opcode },
10154     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10155   },
10156
10157   /* VEX_LEN_0F3A06_P_2 */
10158   {
10159     { Bad_Opcode },
10160     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10161   },
10162
10163   /* VEX_LEN_0F3A0A_P_2 */
10164   {
10165     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10166     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10167   },
10168
10169   /* VEX_LEN_0F3A0B_P_2 */
10170   {
10171     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10172     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10173   },
10174
10175   /* VEX_LEN_0F3A14_P_2 */
10176   {
10177     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10178   },
10179
10180   /* VEX_LEN_0F3A15_P_2 */
10181   {
10182     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10183   },
10184
10185   /* VEX_LEN_0F3A16_P_2  */
10186   {
10187     { "vpextrK",        { Edq, XM, Ib }, 0 },
10188   },
10189
10190   /* VEX_LEN_0F3A17_P_2 */
10191   {
10192     { "vextractps",     { Edqd, XM, Ib }, 0 },
10193   },
10194
10195   /* VEX_LEN_0F3A18_P_2 */
10196   {
10197     { Bad_Opcode },
10198     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10199   },
10200
10201   /* VEX_LEN_0F3A19_P_2 */
10202   {
10203     { Bad_Opcode },
10204     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10205   },
10206
10207   /* VEX_LEN_0F3A20_P_2 */
10208   {
10209     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10210   },
10211
10212   /* VEX_LEN_0F3A21_P_2 */
10213   {
10214     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10215   },
10216
10217   /* VEX_LEN_0F3A22_P_2 */
10218   {
10219     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10220   },
10221
10222   /* VEX_LEN_0F3A30_P_2 */
10223   {
10224     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10225   },
10226
10227   /* VEX_LEN_0F3A31_P_2 */
10228   {
10229     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10230   },
10231
10232   /* VEX_LEN_0F3A32_P_2 */
10233   {
10234     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10235   },
10236
10237   /* VEX_LEN_0F3A33_P_2 */
10238   {
10239     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10240   },
10241
10242   /* VEX_LEN_0F3A38_P_2 */
10243   {
10244     { Bad_Opcode },
10245     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10246   },
10247
10248   /* VEX_LEN_0F3A39_P_2 */
10249   {
10250     { Bad_Opcode },
10251     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10252   },
10253
10254   /* VEX_LEN_0F3A41_P_2 */
10255   {
10256     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10257   },
10258
10259   /* VEX_LEN_0F3A44_P_2 */
10260   {
10261     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10262   },
10263
10264   /* VEX_LEN_0F3A46_P_2 */
10265   {
10266     { Bad_Opcode },
10267     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10268   },
10269
10270   /* VEX_LEN_0F3A60_P_2 */
10271   {
10272     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10273   },
10274
10275   /* VEX_LEN_0F3A61_P_2 */
10276   {
10277     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10278   },
10279
10280   /* VEX_LEN_0F3A62_P_2 */
10281   {
10282     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10283   },
10284
10285   /* VEX_LEN_0F3A63_P_2 */
10286   {
10287     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10288   },
10289
10290   /* VEX_LEN_0F3A6A_P_2 */
10291   {
10292     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10293   },
10294
10295   /* VEX_LEN_0F3A6B_P_2 */
10296   {
10297     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10298   },
10299
10300   /* VEX_LEN_0F3A6E_P_2 */
10301   {
10302     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10303   },
10304
10305   /* VEX_LEN_0F3A6F_P_2 */
10306   {
10307     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10308   },
10309
10310   /* VEX_LEN_0F3A7A_P_2 */
10311   {
10312     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10313   },
10314
10315   /* VEX_LEN_0F3A7B_P_2 */
10316   {
10317     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10318   },
10319
10320   /* VEX_LEN_0F3A7E_P_2 */
10321   {
10322     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10323   },
10324
10325   /* VEX_LEN_0F3A7F_P_2 */
10326   {
10327     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10328   },
10329
10330   /* VEX_LEN_0F3ADF_P_2 */
10331   {
10332     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10333   },
10334
10335   /* VEX_LEN_0F3AF0_P_3 */
10336   {
10337     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10338   },
10339
10340   /* VEX_LEN_0FXOP_08_CC */
10341   {
10342      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10343   },
10344
10345   /* VEX_LEN_0FXOP_08_CD */
10346   {
10347      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10348   },
10349
10350   /* VEX_LEN_0FXOP_08_CE */
10351   {
10352      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10353   },
10354
10355   /* VEX_LEN_0FXOP_08_CF */
10356   {
10357      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10358   },
10359
10360   /* VEX_LEN_0FXOP_08_EC */
10361   {
10362      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10363   },
10364
10365   /* VEX_LEN_0FXOP_08_ED */
10366   {
10367      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10368   },
10369
10370   /* VEX_LEN_0FXOP_08_EE */
10371   {
10372      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10373   },
10374
10375   /* VEX_LEN_0FXOP_08_EF */
10376   {
10377      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10378   },
10379
10380   /* VEX_LEN_0FXOP_09_80 */
10381   {
10382     { "vfrczps",        { XM, EXxmm }, 0 },
10383     { "vfrczps",        { XM, EXymmq }, 0 },
10384   },
10385
10386   /* VEX_LEN_0FXOP_09_81 */
10387   {
10388     { "vfrczpd",        { XM, EXxmm }, 0 },
10389     { "vfrczpd",        { XM, EXymmq }, 0 },
10390   },
10391 };
10392
10393 static const struct dis386 vex_w_table[][2] = {
10394   {
10395     /* VEX_W_0F10_P_0 */
10396     { "vmovups",        { XM, EXx }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F10_P_1 */
10400     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F10_P_2 */
10404     { "vmovupd",        { XM, EXx }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F10_P_3 */
10408     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10409   },
10410   {
10411     /* VEX_W_0F11_P_0 */
10412     { "vmovups",        { EXxS, XM }, 0 },
10413   },
10414   {
10415     /* VEX_W_0F11_P_1 */
10416     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10417   },
10418   {
10419     /* VEX_W_0F11_P_2 */
10420     { "vmovupd",        { EXxS, XM }, 0 },
10421   },
10422   {
10423     /* VEX_W_0F11_P_3 */
10424     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10425   },
10426   {
10427     /* VEX_W_0F12_P_0_M_0 */
10428     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10429   },
10430   {
10431     /* VEX_W_0F12_P_0_M_1 */
10432     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10433   },
10434   {
10435     /* VEX_W_0F12_P_1 */
10436     { "vmovsldup",      { XM, EXx }, 0 },
10437   },
10438   {
10439     /* VEX_W_0F12_P_2 */
10440     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10441   },
10442   {
10443     /* VEX_W_0F12_P_3 */
10444     { "vmovddup",       { XM, EXymmq }, 0 },
10445   },
10446   {
10447     /* VEX_W_0F13_M_0 */
10448     { "vmovlpX",        { EXq, XM }, 0 },
10449   },
10450   {
10451     /* VEX_W_0F14 */
10452     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10453   },
10454   {
10455     /* VEX_W_0F15 */
10456     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10457   },
10458   {
10459     /* VEX_W_0F16_P_0_M_0 */
10460     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10461   },
10462   {
10463     /* VEX_W_0F16_P_0_M_1 */
10464     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10465   },
10466   {
10467     /* VEX_W_0F16_P_1 */
10468     { "vmovshdup",      { XM, EXx }, 0 },
10469   },
10470   {
10471     /* VEX_W_0F16_P_2 */
10472     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10473   },
10474   {
10475     /* VEX_W_0F17_M_0 */
10476     { "vmovhpX",        { EXq, XM }, 0 },
10477   },
10478   {
10479     /* VEX_W_0F28 */
10480     { "vmovapX",        { XM, EXx }, 0 },
10481   },
10482   {
10483     /* VEX_W_0F29 */
10484     { "vmovapX",        { EXxS, XM }, 0 },
10485   },
10486   {
10487     /* VEX_W_0F2B_M_0 */
10488     { "vmovntpX",       { Mx, XM }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F2E_P_0 */
10492     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10493   },
10494   {
10495     /* VEX_W_0F2E_P_2 */
10496     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F2F_P_0 */
10500     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F2F_P_2 */
10504     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10505   },
10506   {
10507     /* VEX_W_0F41_P_0_LEN_1 */
10508     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10509     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10510   },
10511   {
10512     /* VEX_W_0F41_P_2_LEN_1 */
10513     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10514     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10515   },
10516   {
10517     /* VEX_W_0F42_P_0_LEN_1 */
10518     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10519     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10520   },
10521   {
10522     /* VEX_W_0F42_P_2_LEN_1 */
10523     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10524     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10525   },
10526   {
10527     /* VEX_W_0F44_P_0_LEN_0 */
10528     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10529     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10530   },
10531   {
10532     /* VEX_W_0F44_P_2_LEN_0 */
10533     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10534     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10535   },
10536   {
10537     /* VEX_W_0F45_P_0_LEN_1 */
10538     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10539     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10540   },
10541   {
10542     /* VEX_W_0F45_P_2_LEN_1 */
10543     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10544     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10545   },
10546   {
10547     /* VEX_W_0F46_P_0_LEN_1 */
10548     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10549     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10550   },
10551   {
10552     /* VEX_W_0F46_P_2_LEN_1 */
10553     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10554     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10555   },
10556   {
10557     /* VEX_W_0F47_P_0_LEN_1 */
10558     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10559     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10560   },
10561   {
10562     /* VEX_W_0F47_P_2_LEN_1 */
10563     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10564     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10565   },
10566   {
10567     /* VEX_W_0F4A_P_0_LEN_1 */
10568     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10569     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10570   },
10571   {
10572     /* VEX_W_0F4A_P_2_LEN_1 */
10573     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10574     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10575   },
10576   {
10577     /* VEX_W_0F4B_P_0_LEN_1 */
10578     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10579     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10580   },
10581   {
10582     /* VEX_W_0F4B_P_2_LEN_1 */
10583     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10584   },
10585   {
10586     /* VEX_W_0F50_M_0 */
10587     { "vmovmskpX",      { Gdq, XS }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F51_P_0 */
10591     { "vsqrtps",        { XM, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F51_P_1 */
10595     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F51_P_2  */
10599     { "vsqrtpd",        { XM, EXx }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F51_P_3 */
10603     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F52_P_0 */
10607     { "vrsqrtps",       { XM, EXx }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F52_P_1 */
10611     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F53_P_0  */
10615     { "vrcpps",         { XM, EXx }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F53_P_1  */
10619     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F58_P_0  */
10623     { "vaddps",         { XM, Vex, EXx }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F58_P_1  */
10627     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F58_P_2  */
10631     { "vaddpd",         { XM, Vex, EXx }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F58_P_3  */
10635     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F59_P_0  */
10639     { "vmulps",         { XM, Vex, EXx }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F59_P_1  */
10643     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F59_P_2  */
10647     { "vmulpd",         { XM, Vex, EXx }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F59_P_3  */
10651     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F5A_P_0  */
10655     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F5A_P_1  */
10659     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F5A_P_3  */
10663     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F5B_P_0  */
10667     { "vcvtdq2ps",      { XM, EXx }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F5B_P_1  */
10671     { "vcvttps2dq",     { XM, EXx }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F5B_P_2  */
10675     { "vcvtps2dq",      { XM, EXx }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F5C_P_0  */
10679     { "vsubps",         { XM, Vex, EXx }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F5C_P_1  */
10683     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F5C_P_2  */
10687     { "vsubpd",         { XM, Vex, EXx }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F5C_P_3  */
10691     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F5D_P_0  */
10695     { "vminps",         { XM, Vex, EXx }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F5D_P_1  */
10699     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F5D_P_2  */
10703     { "vminpd",         { XM, Vex, EXx }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F5D_P_3  */
10707     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F5E_P_0  */
10711     { "vdivps",         { XM, Vex, EXx }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F5E_P_1  */
10715     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F5E_P_2  */
10719     { "vdivpd",         { XM, Vex, EXx }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F5E_P_3  */
10723     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F5F_P_0  */
10727     { "vmaxps",         { XM, Vex, EXx }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F5F_P_1  */
10731     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F5F_P_2  */
10735     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F5F_P_3  */
10739     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F60_P_2  */
10743     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F61_P_2  */
10747     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F62_P_2  */
10751     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F63_P_2  */
10755     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F64_P_2  */
10759     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F65_P_2  */
10763     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10764   },
10765   {
10766     /* VEX_W_0F66_P_2  */
10767     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10768   },
10769   {
10770     /* VEX_W_0F67_P_2  */
10771     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10772   },
10773   {
10774     /* VEX_W_0F68_P_2  */
10775     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10776   },
10777   {
10778     /* VEX_W_0F69_P_2  */
10779     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10780   },
10781   {
10782     /* VEX_W_0F6A_P_2  */
10783     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10784   },
10785   {
10786     /* VEX_W_0F6B_P_2  */
10787     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10788   },
10789   {
10790     /* VEX_W_0F6C_P_2  */
10791     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10792   },
10793   {
10794     /* VEX_W_0F6D_P_2  */
10795     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10796   },
10797   {
10798     /* VEX_W_0F6F_P_1  */
10799     { "vmovdqu",        { XM, EXx }, 0 },
10800   },
10801   {
10802     /* VEX_W_0F6F_P_2  */
10803     { "vmovdqa",        { XM, EXx }, 0 },
10804   },
10805   {
10806     /* VEX_W_0F70_P_1 */
10807     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10808   },
10809   {
10810     /* VEX_W_0F70_P_2 */
10811     { "vpshufd",        { XM, EXx, Ib }, 0 },
10812   },
10813   {
10814     /* VEX_W_0F70_P_3 */
10815     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10816   },
10817   {
10818     /* VEX_W_0F71_R_2_P_2  */
10819     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10820   },
10821   {
10822     /* VEX_W_0F71_R_4_P_2  */
10823     { "vpsraw",         { Vex, XS, Ib }, 0 },
10824   },
10825   {
10826     /* VEX_W_0F71_R_6_P_2  */
10827     { "vpsllw",         { Vex, XS, Ib }, 0 },
10828   },
10829   {
10830     /* VEX_W_0F72_R_2_P_2  */
10831     { "vpsrld",         { Vex, XS, Ib }, 0 },
10832   },
10833   {
10834     /* VEX_W_0F72_R_4_P_2  */
10835     { "vpsrad",         { Vex, XS, Ib }, 0 },
10836   },
10837   {
10838     /* VEX_W_0F72_R_6_P_2  */
10839     { "vpslld",         { Vex, XS, Ib }, 0 },
10840   },
10841   {
10842     /* VEX_W_0F73_R_2_P_2  */
10843     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10844   },
10845   {
10846     /* VEX_W_0F73_R_3_P_2  */
10847     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10848   },
10849   {
10850     /* VEX_W_0F73_R_6_P_2  */
10851     { "vpsllq",         { Vex, XS, Ib }, 0 },
10852   },
10853   {
10854     /* VEX_W_0F73_R_7_P_2  */
10855     { "vpslldq",        { Vex, XS, Ib }, 0 },
10856   },
10857   {
10858     /* VEX_W_0F74_P_2 */
10859     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10860   },
10861   {
10862     /* VEX_W_0F75_P_2 */
10863     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10864   },
10865   {
10866     /* VEX_W_0F76_P_2 */
10867     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10868   },
10869   {
10870     /* VEX_W_0F77_P_0 */
10871     { "",               { VZERO }, 0 },
10872   },
10873   {
10874     /* VEX_W_0F7C_P_2 */
10875     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10876   },
10877   {
10878     /* VEX_W_0F7C_P_3 */
10879     { "vhaddps",        { XM, Vex, EXx }, 0 },
10880   },
10881   {
10882     /* VEX_W_0F7D_P_2 */
10883     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10884   },
10885   {
10886     /* VEX_W_0F7D_P_3 */
10887     { "vhsubps",        { XM, Vex, EXx }, 0 },
10888   },
10889   {
10890     /* VEX_W_0F7E_P_1 */
10891     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10892   },
10893   {
10894     /* VEX_W_0F7F_P_1 */
10895     { "vmovdqu",        { EXxS, XM }, 0 },
10896   },
10897   {
10898     /* VEX_W_0F7F_P_2 */
10899     { "vmovdqa",        { EXxS, XM }, 0 },
10900   },
10901   {
10902     /* VEX_W_0F90_P_0_LEN_0 */
10903     { "kmovw",          { MaskG, MaskE }, 0 },
10904     { "kmovq",          { MaskG, MaskE }, 0 },
10905   },
10906   {
10907     /* VEX_W_0F90_P_2_LEN_0 */
10908     { "kmovb",          { MaskG, MaskBDE }, 0 },
10909     { "kmovd",          { MaskG, MaskBDE }, 0 },
10910   },
10911   {
10912     /* VEX_W_0F91_P_0_LEN_0 */
10913     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10914     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10915   },
10916   {
10917     /* VEX_W_0F91_P_2_LEN_0 */
10918     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10919     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10920   },
10921   {
10922     /* VEX_W_0F92_P_0_LEN_0 */
10923     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10924   },
10925   {
10926     /* VEX_W_0F92_P_2_LEN_0 */
10927     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10928   },
10929   {
10930     /* VEX_W_0F92_P_3_LEN_0 */
10931     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10932     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10933   },
10934   {
10935     /* VEX_W_0F93_P_0_LEN_0 */
10936     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10937   },
10938   {
10939     /* VEX_W_0F93_P_2_LEN_0 */
10940     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10941   },
10942   {
10943     /* VEX_W_0F93_P_3_LEN_0 */
10944     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10945     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10946   },
10947   {
10948     /* VEX_W_0F98_P_0_LEN_0 */
10949     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10950     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10951   },
10952   {
10953     /* VEX_W_0F98_P_2_LEN_0 */
10954     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10955     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10956   },
10957   {
10958     /* VEX_W_0F99_P_0_LEN_0 */
10959     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10960     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10961   },
10962   {
10963     /* VEX_W_0F99_P_2_LEN_0 */
10964     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10965     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10966   },
10967   {
10968     /* VEX_W_0FAE_R_2_M_0 */
10969     { "vldmxcsr",       { Md }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FAE_R_3_M_0 */
10973     { "vstmxcsr",       { Md }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FC2_P_0 */
10977     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FC2_P_1 */
10981     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FC2_P_2 */
10985     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FC2_P_3 */
10989     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FC4_P_2 */
10993     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FC5_P_2 */
10997     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FD0_P_2 */
11001     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FD0_P_3 */
11005     { "vaddsubps",      { XM, Vex, EXx }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FD1_P_2 */
11009     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FD2_P_2 */
11013     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FD3_P_2 */
11017     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FD4_P_2 */
11021     { "vpaddq",         { XM, Vex, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FD5_P_2 */
11025     { "vpmullw",        { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FD6_P_2 */
11029     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FD7_P_2_M_1 */
11033     { "vpmovmskb",      { Gdq, XS }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FD8_P_2 */
11037     { "vpsubusb",       { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FD9_P_2 */
11041     { "vpsubusw",       { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FDA_P_2 */
11045     { "vpminub",        { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FDB_P_2 */
11049     { "vpand",          { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FDC_P_2 */
11053     { "vpaddusb",       { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FDD_P_2 */
11057     { "vpaddusw",       { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0FDE_P_2 */
11061     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0FDF_P_2 */
11065     { "vpandn",         { XM, Vex, EXx }, 0 },
11066   },
11067   {
11068     /* VEX_W_0FE0_P_2  */
11069     { "vpavgb",         { XM, Vex, EXx }, 0 },
11070   },
11071   {
11072     /* VEX_W_0FE1_P_2  */
11073     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11074   },
11075   {
11076     /* VEX_W_0FE2_P_2  */
11077     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11078   },
11079   {
11080     /* VEX_W_0FE3_P_2  */
11081     { "vpavgw",         { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0FE4_P_2  */
11085     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0FE5_P_2  */
11089     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0FE6_P_1  */
11093     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11094   },
11095   {
11096     /* VEX_W_0FE6_P_2  */
11097     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0FE6_P_3  */
11101     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0FE7_P_2_M_0 */
11105     { "vmovntdq",       { Mx, XM }, 0 },
11106   },
11107   {
11108     /* VEX_W_0FE8_P_2  */
11109     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0FE9_P_2  */
11113     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0FEA_P_2  */
11117     { "vpminsw",        { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0FEB_P_2  */
11121     { "vpor",           { XM, Vex, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0FEC_P_2  */
11125     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0FED_P_2  */
11129     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0FEE_P_2  */
11133     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0FEF_P_2  */
11137     { "vpxor",          { XM, Vex, EXx }, 0 },
11138   },
11139   {
11140     /* VEX_W_0FF0_P_3_M_0 */
11141     { "vlddqu",         { XM, M }, 0 },
11142   },
11143   {
11144     /* VEX_W_0FF1_P_2 */
11145     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11146   },
11147   {
11148     /* VEX_W_0FF2_P_2 */
11149     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11150   },
11151   {
11152     /* VEX_W_0FF3_P_2 */
11153     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11154   },
11155   {
11156     /* VEX_W_0FF4_P_2 */
11157     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11158   },
11159   {
11160     /* VEX_W_0FF5_P_2 */
11161     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11162   },
11163   {
11164     /* VEX_W_0FF6_P_2 */
11165     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11166   },
11167   {
11168     /* VEX_W_0FF7_P_2 */
11169     { "vmaskmovdqu",    { XM, XS }, 0 },
11170   },
11171   {
11172     /* VEX_W_0FF8_P_2 */
11173     { "vpsubb",         { XM, Vex, EXx }, 0 },
11174   },
11175   {
11176     /* VEX_W_0FF9_P_2 */
11177     { "vpsubw",         { XM, Vex, EXx }, 0 },
11178   },
11179   {
11180     /* VEX_W_0FFA_P_2 */
11181     { "vpsubd",         { XM, Vex, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0FFB_P_2 */
11185     { "vpsubq",         { XM, Vex, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0FFC_P_2 */
11189     { "vpaddb",         { XM, Vex, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0FFD_P_2 */
11193     { "vpaddw",         { XM, Vex, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0FFE_P_2 */
11197     { "vpaddd",         { XM, Vex, EXx }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F3800_P_2  */
11201     { "vpshufb",        { XM, Vex, EXx }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F3801_P_2  */
11205     { "vphaddw",        { XM, Vex, EXx }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F3802_P_2  */
11209     { "vphaddd",        { XM, Vex, EXx }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F3803_P_2  */
11213     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3804_P_2  */
11217     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3805_P_2  */
11221     { "vphsubw",        { XM, Vex, EXx }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3806_P_2  */
11225     { "vphsubd",        { XM, Vex, EXx }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3807_P_2  */
11229     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3808_P_2  */
11233     { "vpsignb",        { XM, Vex, EXx }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3809_P_2  */
11237     { "vpsignw",        { XM, Vex, EXx }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F380A_P_2  */
11241     { "vpsignd",        { XM, Vex, EXx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F380B_P_2  */
11245     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F380C_P_2  */
11249     { "vpermilps",      { XM, Vex, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F380D_P_2  */
11253     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F380E_P_2  */
11257     { "vtestps",        { XM, EXx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F380F_P_2  */
11261     { "vtestpd",        { XM, EXx }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F3816_P_2  */
11265     { "vpermps",        { XM, Vex, EXx }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F3817_P_2 */
11269     { "vptest",         { XM, EXx }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F3818_P_2 */
11273     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F3819_P_2 */
11277     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F381A_P_2_M_0 */
11281     { "vbroadcastf128", { XM, Mxmm }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F381C_P_2 */
11285     { "vpabsb",         { XM, EXx }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F381D_P_2 */
11289     { "vpabsw",         { XM, EXx }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F381E_P_2 */
11293     { "vpabsd",         { XM, EXx }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F3820_P_2 */
11297     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F3821_P_2 */
11301     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3822_P_2 */
11305     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F3823_P_2 */
11309     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F3824_P_2 */
11313     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F3825_P_2 */
11317     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F3828_P_2 */
11321     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F3829_P_2 */
11325     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11326   },
11327   {
11328     /* VEX_W_0F382A_P_2_M_0 */
11329     { "vmovntdqa",      { XM, Mx }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F382B_P_2 */
11333     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F382C_P_2_M_0 */
11337     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F382D_P_2_M_0 */
11341     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F382E_P_2_M_0 */
11345     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F382F_P_2_M_0 */
11349     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F3830_P_2 */
11353     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F3831_P_2 */
11357     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11358   },
11359   {
11360     /* VEX_W_0F3832_P_2 */
11361     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11362   },
11363   {
11364     /* VEX_W_0F3833_P_2 */
11365     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11366   },
11367   {
11368     /* VEX_W_0F3834_P_2 */
11369     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11370   },
11371   {
11372     /* VEX_W_0F3835_P_2 */
11373     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11374   },
11375   {
11376     /* VEX_W_0F3836_P_2  */
11377     { "vpermd",         { XM, Vex, EXx }, 0 },
11378   },
11379   {
11380     /* VEX_W_0F3837_P_2 */
11381     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11382   },
11383   {
11384     /* VEX_W_0F3838_P_2 */
11385     { "vpminsb",        { XM, Vex, EXx }, 0 },
11386   },
11387   {
11388     /* VEX_W_0F3839_P_2 */
11389     { "vpminsd",        { XM, Vex, EXx }, 0 },
11390   },
11391   {
11392     /* VEX_W_0F383A_P_2 */
11393     { "vpminuw",        { XM, Vex, EXx }, 0 },
11394   },
11395   {
11396     /* VEX_W_0F383B_P_2 */
11397     { "vpminud",        { XM, Vex, EXx }, 0 },
11398   },
11399   {
11400     /* VEX_W_0F383C_P_2 */
11401     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11402   },
11403   {
11404     /* VEX_W_0F383D_P_2 */
11405     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11406   },
11407   {
11408     /* VEX_W_0F383E_P_2 */
11409     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11410   },
11411   {
11412     /* VEX_W_0F383F_P_2 */
11413     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11414   },
11415   {
11416     /* VEX_W_0F3840_P_2 */
11417     { "vpmulld",        { XM, Vex, EXx }, 0 },
11418   },
11419   {
11420     /* VEX_W_0F3841_P_2 */
11421     { "vphminposuw",    { XM, EXx }, 0 },
11422   },
11423   {
11424     /* VEX_W_0F3846_P_2 */
11425     { "vpsravd",        { XM, Vex, EXx }, 0 },
11426   },
11427   {
11428     /* VEX_W_0F3858_P_2 */
11429     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11430   },
11431   {
11432     /* VEX_W_0F3859_P_2 */
11433     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11434   },
11435   {
11436     /* VEX_W_0F385A_P_2_M_0 */
11437     { "vbroadcasti128", { XM, Mxmm }, 0 },
11438   },
11439   {
11440     /* VEX_W_0F3878_P_2 */
11441     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11442   },
11443   {
11444     /* VEX_W_0F3879_P_2 */
11445     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11446   },
11447   {
11448     /* VEX_W_0F38DB_P_2 */
11449     { "vaesimc",        { XM, EXx }, 0 },
11450   },
11451   {
11452     /* VEX_W_0F38DC_P_2 */
11453     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11454   },
11455   {
11456     /* VEX_W_0F38DD_P_2 */
11457     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11458   },
11459   {
11460     /* VEX_W_0F38DE_P_2 */
11461     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11462   },
11463   {
11464     /* VEX_W_0F38DF_P_2 */
11465     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11466   },
11467   {
11468     /* VEX_W_0F3A00_P_2 */
11469     { Bad_Opcode },
11470     { "vpermq",         { XM, EXx, Ib }, 0 },
11471   },
11472   {
11473     /* VEX_W_0F3A01_P_2 */
11474     { Bad_Opcode },
11475     { "vpermpd",        { XM, EXx, Ib }, 0 },
11476   },
11477   {
11478     /* VEX_W_0F3A02_P_2 */
11479     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11480   },
11481   {
11482     /* VEX_W_0F3A04_P_2 */
11483     { "vpermilps",      { XM, EXx, Ib }, 0 },
11484   },
11485   {
11486     /* VEX_W_0F3A05_P_2 */
11487     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11488   },
11489   {
11490     /* VEX_W_0F3A06_P_2 */
11491     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11492   },
11493   {
11494     /* VEX_W_0F3A08_P_2 */
11495     { "vroundps",       { XM, EXx, Ib }, 0 },
11496   },
11497   {
11498     /* VEX_W_0F3A09_P_2 */
11499     { "vroundpd",       { XM, EXx, Ib }, 0 },
11500   },
11501   {
11502     /* VEX_W_0F3A0A_P_2 */
11503     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11504   },
11505   {
11506     /* VEX_W_0F3A0B_P_2 */
11507     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11508   },
11509   {
11510     /* VEX_W_0F3A0C_P_2 */
11511     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11512   },
11513   {
11514     /* VEX_W_0F3A0D_P_2 */
11515     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11516   },
11517   {
11518     /* VEX_W_0F3A0E_P_2 */
11519     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11520   },
11521   {
11522     /* VEX_W_0F3A0F_P_2 */
11523     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11524   },
11525   {
11526     /* VEX_W_0F3A14_P_2 */
11527     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11528   },
11529   {
11530     /* VEX_W_0F3A15_P_2 */
11531     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11532   },
11533   {
11534     /* VEX_W_0F3A18_P_2 */
11535     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11536   },
11537   {
11538     /* VEX_W_0F3A19_P_2 */
11539     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11540   },
11541   {
11542     /* VEX_W_0F3A20_P_2 */
11543     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11544   },
11545   {
11546     /* VEX_W_0F3A21_P_2 */
11547     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11548   },
11549   {
11550     /* VEX_W_0F3A30_P_2_LEN_0 */
11551     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11552     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11553   },
11554   {
11555     /* VEX_W_0F3A31_P_2_LEN_0 */
11556     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11557     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11558   },
11559   {
11560     /* VEX_W_0F3A32_P_2_LEN_0 */
11561     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11562     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11563   },
11564   {
11565     /* VEX_W_0F3A33_P_2_LEN_0 */
11566     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11567     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11568   },
11569   {
11570     /* VEX_W_0F3A38_P_2 */
11571     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11572   },
11573   {
11574     /* VEX_W_0F3A39_P_2 */
11575     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11576   },
11577   {
11578     /* VEX_W_0F3A40_P_2 */
11579     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11580   },
11581   {
11582     /* VEX_W_0F3A41_P_2 */
11583     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11584   },
11585   {
11586     /* VEX_W_0F3A42_P_2 */
11587     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11588   },
11589   {
11590     /* VEX_W_0F3A44_P_2 */
11591     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11592   },
11593   {
11594     /* VEX_W_0F3A46_P_2 */
11595     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11596   },
11597   {
11598     /* VEX_W_0F3A48_P_2 */
11599     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11600     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11601   },
11602   {
11603     /* VEX_W_0F3A49_P_2 */
11604     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11605     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11606   },
11607   {
11608     /* VEX_W_0F3A4A_P_2 */
11609     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11610   },
11611   {
11612     /* VEX_W_0F3A4B_P_2 */
11613     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11614   },
11615   {
11616     /* VEX_W_0F3A4C_P_2 */
11617     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11618   },
11619   {
11620     /* VEX_W_0F3A60_P_2 */
11621     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11622   },
11623   {
11624     /* VEX_W_0F3A61_P_2 */
11625     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11626   },
11627   {
11628     /* VEX_W_0F3A62_P_2 */
11629     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11630   },
11631   {
11632     /* VEX_W_0F3A63_P_2 */
11633     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11634   },
11635   {
11636     /* VEX_W_0F3ADF_P_2 */
11637     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11638   },
11639 #define NEED_VEX_W_TABLE
11640 #include "i386-dis-evex.h"
11641 #undef NEED_VEX_W_TABLE
11642 };
11643
11644 static const struct dis386 mod_table[][2] = {
11645   {
11646     /* MOD_8D */
11647     { "leaS",           { Gv, M }, 0 },
11648   },
11649   {
11650     /* MOD_C6_REG_7 */
11651     { Bad_Opcode },
11652     { RM_TABLE (RM_C6_REG_7) },
11653   },
11654   {
11655     /* MOD_C7_REG_7 */
11656     { Bad_Opcode },
11657     { RM_TABLE (RM_C7_REG_7) },
11658   },
11659   {
11660     /* MOD_FF_REG_3 */
11661     { "Jcall^", { indirEp }, 0 },
11662   },
11663   {
11664     /* MOD_FF_REG_5 */
11665     { "Jjmp^", { indirEp }, 0 },
11666   },
11667   {
11668     /* MOD_0F01_REG_0 */
11669     { X86_64_TABLE (X86_64_0F01_REG_0) },
11670     { RM_TABLE (RM_0F01_REG_0) },
11671   },
11672   {
11673     /* MOD_0F01_REG_1 */
11674     { X86_64_TABLE (X86_64_0F01_REG_1) },
11675     { RM_TABLE (RM_0F01_REG_1) },
11676   },
11677   {
11678     /* MOD_0F01_REG_2 */
11679     { X86_64_TABLE (X86_64_0F01_REG_2) },
11680     { RM_TABLE (RM_0F01_REG_2) },
11681   },
11682   {
11683     /* MOD_0F01_REG_3 */
11684     { X86_64_TABLE (X86_64_0F01_REG_3) },
11685     { RM_TABLE (RM_0F01_REG_3) },
11686   },
11687   {
11688     /* MOD_0F01_REG_7 */
11689     { "invlpg",         { Mb }, 0 },
11690     { RM_TABLE (RM_0F01_REG_7) },
11691   },
11692   {
11693     /* MOD_0F12_PREFIX_0 */
11694     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11695     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11696   },
11697   {
11698     /* MOD_0F13 */
11699     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11700   },
11701   {
11702     /* MOD_0F16_PREFIX_0 */
11703     { "movhps",         { XM, EXq }, 0 },
11704     { "movlhps",        { XM, EXq }, 0 },
11705   },
11706   {
11707     /* MOD_0F17 */
11708     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11709   },
11710   {
11711     /* MOD_0F18_REG_0 */
11712     { "prefetchnta",    { Mb }, 0 },
11713   },
11714   {
11715     /* MOD_0F18_REG_1 */
11716     { "prefetcht0",     { Mb }, 0 },
11717   },
11718   {
11719     /* MOD_0F18_REG_2 */
11720     { "prefetcht1",     { Mb }, 0 },
11721   },
11722   {
11723     /* MOD_0F18_REG_3 */
11724     { "prefetcht2",     { Mb }, 0 },
11725   },
11726   {
11727     /* MOD_0F18_REG_4 */
11728     { "nop/reserved",   { Mb }, 0 },
11729   },
11730   {
11731     /* MOD_0F18_REG_5 */
11732     { "nop/reserved",   { Mb }, 0 },
11733   },
11734   {
11735     /* MOD_0F18_REG_6 */
11736     { "nop/reserved",   { Mb }, 0 },
11737   },
11738   {
11739     /* MOD_0F18_REG_7 */
11740     { "nop/reserved",   { Mb }, 0 },
11741   },
11742   {
11743     /* MOD_0F1A_PREFIX_0 */
11744     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11745     { "nopQ",           { Ev }, 0 },
11746   },
11747   {
11748     /* MOD_0F1B_PREFIX_0 */
11749     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11750     { "nopQ",           { Ev }, 0 },
11751   },
11752   {
11753     /* MOD_0F1B_PREFIX_1 */
11754     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11755     { "nopQ",           { Ev }, 0 },
11756   },
11757   {
11758     /* MOD_0F24 */
11759     { Bad_Opcode },
11760     { "movL",           { Rd, Td }, 0 },
11761   },
11762   {
11763     /* MOD_0F26 */
11764     { Bad_Opcode },
11765     { "movL",           { Td, Rd }, 0 },
11766   },
11767   {
11768     /* MOD_0F2B_PREFIX_0 */
11769     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11770   },
11771   {
11772     /* MOD_0F2B_PREFIX_1 */
11773     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11774   },
11775   {
11776     /* MOD_0F2B_PREFIX_2 */
11777     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11778   },
11779   {
11780     /* MOD_0F2B_PREFIX_3 */
11781     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11782   },
11783   {
11784     /* MOD_0F51 */
11785     { Bad_Opcode },
11786     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11787   },
11788   {
11789     /* MOD_0F71_REG_2 */
11790     { Bad_Opcode },
11791     { "psrlw",          { MS, Ib }, 0 },
11792   },
11793   {
11794     /* MOD_0F71_REG_4 */
11795     { Bad_Opcode },
11796     { "psraw",          { MS, Ib }, 0 },
11797   },
11798   {
11799     /* MOD_0F71_REG_6 */
11800     { Bad_Opcode },
11801     { "psllw",          { MS, Ib }, 0 },
11802   },
11803   {
11804     /* MOD_0F72_REG_2 */
11805     { Bad_Opcode },
11806     { "psrld",          { MS, Ib }, 0 },
11807   },
11808   {
11809     /* MOD_0F72_REG_4 */
11810     { Bad_Opcode },
11811     { "psrad",          { MS, Ib }, 0 },
11812   },
11813   {
11814     /* MOD_0F72_REG_6 */
11815     { Bad_Opcode },
11816     { "pslld",          { MS, Ib }, 0 },
11817   },
11818   {
11819     /* MOD_0F73_REG_2 */
11820     { Bad_Opcode },
11821     { "psrlq",          { MS, Ib }, 0 },
11822   },
11823   {
11824     /* MOD_0F73_REG_3 */
11825     { Bad_Opcode },
11826     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11827   },
11828   {
11829     /* MOD_0F73_REG_6 */
11830     { Bad_Opcode },
11831     { "psllq",          { MS, Ib }, 0 },
11832   },
11833   {
11834     /* MOD_0F73_REG_7 */
11835     { Bad_Opcode },
11836     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11837   },
11838   {
11839     /* MOD_0FAE_REG_0 */
11840     { "fxsave",         { FXSAVE }, 0 },
11841     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11842   },
11843   {
11844     /* MOD_0FAE_REG_1 */
11845     { "fxrstor",        { FXSAVE }, 0 },
11846     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11847   },
11848   {
11849     /* MOD_0FAE_REG_2 */
11850     { "ldmxcsr",        { Md }, 0 },
11851     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11852   },
11853   {
11854     /* MOD_0FAE_REG_3 */
11855     { "stmxcsr",        { Md }, 0 },
11856     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11857   },
11858   {
11859     /* MOD_0FAE_REG_4 */
11860     { "xsave",          { FXSAVE }, 0 },
11861   },
11862   {
11863     /* MOD_0FAE_REG_5 */
11864     { "xrstor",         { FXSAVE }, 0 },
11865     { RM_TABLE (RM_0FAE_REG_5) },
11866   },
11867   {
11868     /* MOD_0FAE_REG_6 */
11869     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11870     { RM_TABLE (RM_0FAE_REG_6) },
11871   },
11872   {
11873     /* MOD_0FAE_REG_7 */
11874     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11875     { RM_TABLE (RM_0FAE_REG_7) },
11876   },
11877   {
11878     /* MOD_0FB2 */
11879     { "lssS",           { Gv, Mp }, 0 },
11880   },
11881   {
11882     /* MOD_0FB4 */
11883     { "lfsS",           { Gv, Mp }, 0 },
11884   },
11885   {
11886     /* MOD_0FB5 */
11887     { "lgsS",           { Gv, Mp }, 0 },
11888   },
11889   {
11890     /* MOD_0FC3 */
11891     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11892   },
11893   {
11894     /* MOD_0FC7_REG_3 */
11895     { "xrstors",        { FXSAVE }, 0 },
11896   },
11897   {
11898     /* MOD_0FC7_REG_4 */
11899     { "xsavec",         { FXSAVE }, 0 },
11900   },
11901   {
11902     /* MOD_0FC7_REG_5 */
11903     { "xsaves",         { FXSAVE }, 0 },
11904   },
11905   {
11906     /* MOD_0FC7_REG_6 */
11907     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11908     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11909   },
11910   {
11911     /* MOD_0FC7_REG_7 */
11912     { "vmptrst",        { Mq }, 0 },
11913     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11914   },
11915   {
11916     /* MOD_0FD7 */
11917     { Bad_Opcode },
11918     { "pmovmskb",       { Gdq, MS }, 0 },
11919   },
11920   {
11921     /* MOD_0FE7_PREFIX_2 */
11922     { "movntdq",        { Mx, XM }, 0 },
11923   },
11924   {
11925     /* MOD_0FF0_PREFIX_3 */
11926     { "lddqu",          { XM, M }, 0 },
11927   },
11928   {
11929     /* MOD_0F382A_PREFIX_2 */
11930     { "movntdqa",       { XM, Mx }, 0 },
11931   },
11932   {
11933     /* MOD_62_32BIT */
11934     { "bound{S|}",      { Gv, Ma }, 0 },
11935     { EVEX_TABLE (EVEX_0F) },
11936   },
11937   {
11938     /* MOD_C4_32BIT */
11939     { "lesS",           { Gv, Mp }, 0 },
11940     { VEX_C4_TABLE (VEX_0F) },
11941   },
11942   {
11943     /* MOD_C5_32BIT */
11944     { "ldsS",           { Gv, Mp }, 0 },
11945     { VEX_C5_TABLE (VEX_0F) },
11946   },
11947   {
11948     /* MOD_VEX_0F12_PREFIX_0 */
11949     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11950     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11951   },
11952   {
11953     /* MOD_VEX_0F13 */
11954     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11955   },
11956   {
11957     /* MOD_VEX_0F16_PREFIX_0 */
11958     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11959     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11960   },
11961   {
11962     /* MOD_VEX_0F17 */
11963     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11964   },
11965   {
11966     /* MOD_VEX_0F2B */
11967     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11968   },
11969   {
11970     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11971     { Bad_Opcode },
11972     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11973   },
11974   {
11975     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11976     { Bad_Opcode },
11977     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11978   },
11979   {
11980     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11981     { Bad_Opcode },
11982     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11983   },
11984   {
11985     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11986     { Bad_Opcode },
11987     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11988   },
11989   {
11990     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11991     { Bad_Opcode },
11992     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11993   },
11994   {
11995     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11996     { Bad_Opcode },
11997     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11998   },
11999   {
12000     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12001     { Bad_Opcode },
12002     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
12003   },
12004   {
12005     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12006     { Bad_Opcode },
12007     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
12008   },
12009   {
12010     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12011     { Bad_Opcode },
12012     { "knotw",          { MaskG, MaskR }, 0 },
12013   },
12014   {
12015     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12016     { Bad_Opcode },
12017     { "knotq",          { MaskG, MaskR }, 0 },
12018   },
12019   {
12020     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12021     { Bad_Opcode },
12022     { "knotb",          { MaskG, MaskR }, 0 },
12023   },
12024   {
12025     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12026     { Bad_Opcode },
12027     { "knotd",          { MaskG, MaskR }, 0 },
12028   },
12029   {
12030     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12031     { Bad_Opcode },
12032     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
12033   },
12034   {
12035     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12036     { Bad_Opcode },
12037     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
12038   },
12039   {
12040     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12041     { Bad_Opcode },
12042     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
12043   },
12044   {
12045     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12046     { Bad_Opcode },
12047     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
12048   },
12049  {
12050     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12051     { Bad_Opcode },
12052     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
12053   },
12054   {
12055     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12056     { Bad_Opcode },
12057     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
12058   },
12059   {
12060     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12061     { Bad_Opcode },
12062     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12063   },
12064   {
12065     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12066     { Bad_Opcode },
12067     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12068   },
12069   {
12070     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12071     { Bad_Opcode },
12072     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12073   },
12074   {
12075     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12076     { Bad_Opcode },
12077     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12078   },
12079   {
12080     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12081     { Bad_Opcode },
12082     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12083   },
12084   {
12085     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12086     { Bad_Opcode },
12087     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12088   },
12089   {
12090     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12091     { Bad_Opcode },
12092     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12093   },
12094   {
12095     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12096     { Bad_Opcode },
12097     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12098   },
12099   {
12100     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12101     { Bad_Opcode },
12102     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12103   },
12104   {
12105     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12106     { Bad_Opcode },
12107     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12108   },
12109   {
12110     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12111     { Bad_Opcode },
12112     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12113   },
12114   {
12115     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12116     { Bad_Opcode },
12117     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12118   },
12119   {
12120     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12121     { Bad_Opcode },
12122     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12123   },
12124   {
12125     /* MOD_VEX_0F50 */
12126     { Bad_Opcode },
12127     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12128   },
12129   {
12130     /* MOD_VEX_0F71_REG_2 */
12131     { Bad_Opcode },
12132     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12133   },
12134   {
12135     /* MOD_VEX_0F71_REG_4 */
12136     { Bad_Opcode },
12137     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12138   },
12139   {
12140     /* MOD_VEX_0F71_REG_6 */
12141     { Bad_Opcode },
12142     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12143   },
12144   {
12145     /* MOD_VEX_0F72_REG_2 */
12146     { Bad_Opcode },
12147     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12148   },
12149   {
12150     /* MOD_VEX_0F72_REG_4 */
12151     { Bad_Opcode },
12152     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12153   },
12154   {
12155     /* MOD_VEX_0F72_REG_6 */
12156     { Bad_Opcode },
12157     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12158   },
12159   {
12160     /* MOD_VEX_0F73_REG_2 */
12161     { Bad_Opcode },
12162     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12163   },
12164   {
12165     /* MOD_VEX_0F73_REG_3 */
12166     { Bad_Opcode },
12167     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12168   },
12169   {
12170     /* MOD_VEX_0F73_REG_6 */
12171     { Bad_Opcode },
12172     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12173   },
12174   {
12175     /* MOD_VEX_0F73_REG_7 */
12176     { Bad_Opcode },
12177     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12178   },
12179   {
12180     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12181     { "kmovw",          { Ew, MaskG }, 0 },
12182     { Bad_Opcode },
12183   },
12184   {
12185     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12186     { "kmovq",          { Eq, MaskG }, 0 },
12187     { Bad_Opcode },
12188   },
12189   {
12190     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12191     { "kmovb",          { Eb, MaskG }, 0 },
12192     { Bad_Opcode },
12193   },
12194   {
12195     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12196     { "kmovd",          { Ed, MaskG }, 0 },
12197     { Bad_Opcode },
12198   },
12199   {
12200     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12201     { Bad_Opcode },
12202     { "kmovw",          { MaskG, Rdq }, 0 },
12203   },
12204   {
12205     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12206     { Bad_Opcode },
12207     { "kmovb",          { MaskG, Rdq }, 0 },
12208   },
12209   {
12210     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12211     { Bad_Opcode },
12212     { "kmovd",          { MaskG, Rdq }, 0 },
12213   },
12214   {
12215     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12216     { Bad_Opcode },
12217     { "kmovq",          { MaskG, Rdq }, 0 },
12218   },
12219   {
12220     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12221     { Bad_Opcode },
12222     { "kmovw",          { Gdq, MaskR }, 0 },
12223   },
12224   {
12225     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12226     { Bad_Opcode },
12227     { "kmovb",          { Gdq, MaskR }, 0 },
12228   },
12229   {
12230     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12231     { Bad_Opcode },
12232     { "kmovd",          { Gdq, MaskR }, 0 },
12233   },
12234   {
12235     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12236     { Bad_Opcode },
12237     { "kmovq",          { Gdq, MaskR }, 0 },
12238   },
12239   {
12240     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12241     { Bad_Opcode },
12242     { "kortestw", { MaskG, MaskR }, 0 },
12243   },
12244   {
12245     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12246     { Bad_Opcode },
12247     { "kortestq", { MaskG, MaskR }, 0 },
12248   },
12249   {
12250     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12251     { Bad_Opcode },
12252     { "kortestb", { MaskG, MaskR }, 0 },
12253   },
12254   {
12255     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12256     { Bad_Opcode },
12257     { "kortestd", { MaskG, MaskR }, 0 },
12258   },
12259   {
12260     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12261     { Bad_Opcode },
12262     { "ktestw", { MaskG, MaskR }, 0 },
12263   },
12264   {
12265     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12266     { Bad_Opcode },
12267     { "ktestq", { MaskG, MaskR }, 0 },
12268   },
12269   {
12270     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12271     { Bad_Opcode },
12272     { "ktestb", { MaskG, MaskR }, 0 },
12273   },
12274   {
12275     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12276     { Bad_Opcode },
12277     { "ktestd", { MaskG, MaskR }, 0 },
12278   },
12279   {
12280     /* MOD_VEX_0FAE_REG_2 */
12281     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12282   },
12283   {
12284     /* MOD_VEX_0FAE_REG_3 */
12285     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12286   },
12287   {
12288     /* MOD_VEX_0FD7_PREFIX_2 */
12289     { Bad_Opcode },
12290     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12291   },
12292   {
12293     /* MOD_VEX_0FE7_PREFIX_2 */
12294     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12295   },
12296   {
12297     /* MOD_VEX_0FF0_PREFIX_3 */
12298     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12299   },
12300   {
12301     /* MOD_VEX_0F381A_PREFIX_2 */
12302     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12303   },
12304   {
12305     /* MOD_VEX_0F382A_PREFIX_2 */
12306     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12307   },
12308   {
12309     /* MOD_VEX_0F382C_PREFIX_2 */
12310     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12311   },
12312   {
12313     /* MOD_VEX_0F382D_PREFIX_2 */
12314     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12315   },
12316   {
12317     /* MOD_VEX_0F382E_PREFIX_2 */
12318     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12319   },
12320   {
12321     /* MOD_VEX_0F382F_PREFIX_2 */
12322     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12323   },
12324   {
12325     /* MOD_VEX_0F385A_PREFIX_2 */
12326     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12327   },
12328   {
12329     /* MOD_VEX_0F388C_PREFIX_2 */
12330     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12331   },
12332   {
12333     /* MOD_VEX_0F388E_PREFIX_2 */
12334     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12335   },
12336   {
12337     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12338     { Bad_Opcode },
12339     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12340   },
12341   {
12342     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12343     { Bad_Opcode },
12344     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12345   },
12346   {
12347     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12348     { Bad_Opcode },
12349     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12350   },
12351   {
12352     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12353     { Bad_Opcode },
12354     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12355   },
12356   {
12357     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12358     { Bad_Opcode },
12359     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12360   },
12361   {
12362     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12363     { Bad_Opcode },
12364     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12365   },
12366   {
12367     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12368     { Bad_Opcode },
12369     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12370   },
12371   {
12372     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12373     { Bad_Opcode },
12374     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12375   },
12376 #define NEED_MOD_TABLE
12377 #include "i386-dis-evex.h"
12378 #undef NEED_MOD_TABLE
12379 };
12380
12381 static const struct dis386 rm_table[][8] = {
12382   {
12383     /* RM_C6_REG_7 */
12384     { "xabort",         { Skip_MODRM, Ib }, 0 },
12385   },
12386   {
12387     /* RM_C7_REG_7 */
12388     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12389   },
12390   {
12391     /* RM_0F01_REG_0 */
12392     { Bad_Opcode },
12393     { "vmcall",         { Skip_MODRM }, 0 },
12394     { "vmlaunch",       { Skip_MODRM }, 0 },
12395     { "vmresume",       { Skip_MODRM }, 0 },
12396     { "vmxoff",         { Skip_MODRM }, 0 },
12397   },
12398   {
12399     /* RM_0F01_REG_1 */
12400     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12401     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12402     { "clac",           { Skip_MODRM }, 0 },
12403     { "stac",           { Skip_MODRM }, 0 },
12404     { Bad_Opcode },
12405     { Bad_Opcode },
12406     { Bad_Opcode },
12407     { "encls",          { Skip_MODRM }, 0 },
12408   },
12409   {
12410     /* RM_0F01_REG_2 */
12411     { "xgetbv",         { Skip_MODRM }, 0 },
12412     { "xsetbv",         { Skip_MODRM }, 0 },
12413     { Bad_Opcode },
12414     { Bad_Opcode },
12415     { "vmfunc",         { Skip_MODRM }, 0 },
12416     { "xend",           { Skip_MODRM }, 0 },
12417     { "xtest",          { Skip_MODRM }, 0 },
12418     { "enclu",          { Skip_MODRM }, 0 },
12419   },
12420   {
12421     /* RM_0F01_REG_3 */
12422     { "vmrun",          { Skip_MODRM }, 0 },
12423     { "vmmcall",        { Skip_MODRM }, 0 },
12424     { "vmload",         { Skip_MODRM }, 0 },
12425     { "vmsave",         { Skip_MODRM }, 0 },
12426     { "stgi",           { Skip_MODRM }, 0 },
12427     { "clgi",           { Skip_MODRM }, 0 },
12428     { "skinit",         { Skip_MODRM }, 0 },
12429     { "invlpga",        { Skip_MODRM }, 0 },
12430   },
12431   {
12432     /* RM_0F01_REG_7 */
12433     { "swapgs",         { Skip_MODRM }, 0  },
12434     { "rdtscp",         { Skip_MODRM }, 0  },
12435     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12436     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12437     { "clzero",         { Skip_MODRM }, 0  },
12438   },
12439   {
12440     /* RM_0FAE_REG_5 */
12441     { "lfence",         { Skip_MODRM }, 0 },
12442   },
12443   {
12444     /* RM_0FAE_REG_6 */
12445     { "mfence",         { Skip_MODRM }, 0 },
12446   },
12447   {
12448     /* RM_0FAE_REG_7 */
12449     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12450   },
12451 };
12452
12453 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12454
12455 /* We use the high bit to indicate different name for the same
12456    prefix.  */
12457 #define REP_PREFIX      (0xf3 | 0x100)
12458 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12459 #define XRELEASE_PREFIX (0xf3 | 0x400)
12460 #define BND_PREFIX      (0xf2 | 0x400)
12461
12462 static int
12463 ckprefix (void)
12464 {
12465   int newrex, i, length;
12466   rex = 0;
12467   rex_ignored = 0;
12468   prefixes = 0;
12469   used_prefixes = 0;
12470   rex_used = 0;
12471   last_lock_prefix = -1;
12472   last_repz_prefix = -1;
12473   last_repnz_prefix = -1;
12474   last_data_prefix = -1;
12475   last_addr_prefix = -1;
12476   last_rex_prefix = -1;
12477   last_seg_prefix = -1;
12478   fwait_prefix = -1;
12479   active_seg_prefix = 0;
12480   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12481     all_prefixes[i] = 0;
12482   i = 0;
12483   length = 0;
12484   /* The maximum instruction length is 15bytes.  */
12485   while (length < MAX_CODE_LENGTH - 1)
12486     {
12487       FETCH_DATA (the_info, codep + 1);
12488       newrex = 0;
12489       switch (*codep)
12490         {
12491         /* REX prefixes family.  */
12492         case 0x40:
12493         case 0x41:
12494         case 0x42:
12495         case 0x43:
12496         case 0x44:
12497         case 0x45:
12498         case 0x46:
12499         case 0x47:
12500         case 0x48:
12501         case 0x49:
12502         case 0x4a:
12503         case 0x4b:
12504         case 0x4c:
12505         case 0x4d:
12506         case 0x4e:
12507         case 0x4f:
12508           if (address_mode == mode_64bit)
12509             newrex = *codep;
12510           else
12511             return 1;
12512           last_rex_prefix = i;
12513           break;
12514         case 0xf3:
12515           prefixes |= PREFIX_REPZ;
12516           last_repz_prefix = i;
12517           break;
12518         case 0xf2:
12519           prefixes |= PREFIX_REPNZ;
12520           last_repnz_prefix = i;
12521           break;
12522         case 0xf0:
12523           prefixes |= PREFIX_LOCK;
12524           last_lock_prefix = i;
12525           break;
12526         case 0x2e:
12527           prefixes |= PREFIX_CS;
12528           last_seg_prefix = i;
12529           active_seg_prefix = PREFIX_CS;
12530           break;
12531         case 0x36:
12532           prefixes |= PREFIX_SS;
12533           last_seg_prefix = i;
12534           active_seg_prefix = PREFIX_SS;
12535           break;
12536         case 0x3e:
12537           prefixes |= PREFIX_DS;
12538           last_seg_prefix = i;
12539           active_seg_prefix = PREFIX_DS;
12540           break;
12541         case 0x26:
12542           prefixes |= PREFIX_ES;
12543           last_seg_prefix = i;
12544           active_seg_prefix = PREFIX_ES;
12545           break;
12546         case 0x64:
12547           prefixes |= PREFIX_FS;
12548           last_seg_prefix = i;
12549           active_seg_prefix = PREFIX_FS;
12550           break;
12551         case 0x65:
12552           prefixes |= PREFIX_GS;
12553           last_seg_prefix = i;
12554           active_seg_prefix = PREFIX_GS;
12555           break;
12556         case 0x66:
12557           prefixes |= PREFIX_DATA;
12558           last_data_prefix = i;
12559           break;
12560         case 0x67:
12561           prefixes |= PREFIX_ADDR;
12562           last_addr_prefix = i;
12563           break;
12564         case FWAIT_OPCODE:
12565           /* fwait is really an instruction.  If there are prefixes
12566              before the fwait, they belong to the fwait, *not* to the
12567              following instruction.  */
12568           fwait_prefix = i;
12569           if (prefixes || rex)
12570             {
12571               prefixes |= PREFIX_FWAIT;
12572               codep++;
12573               /* This ensures that the previous REX prefixes are noticed
12574                  as unused prefixes, as in the return case below.  */
12575               rex_used = rex;
12576               return 1;
12577             }
12578           prefixes = PREFIX_FWAIT;
12579           break;
12580         default:
12581           return 1;
12582         }
12583       /* Rex is ignored when followed by another prefix.  */
12584       if (rex)
12585         {
12586           rex_used = rex;
12587           return 1;
12588         }
12589       if (*codep != FWAIT_OPCODE)
12590         all_prefixes[i++] = *codep;
12591       rex = newrex;
12592       codep++;
12593       length++;
12594     }
12595   return 0;
12596 }
12597
12598 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12599    prefix byte.  */
12600
12601 static const char *
12602 prefix_name (int pref, int sizeflag)
12603 {
12604   static const char *rexes [16] =
12605     {
12606       "rex",            /* 0x40 */
12607       "rex.B",          /* 0x41 */
12608       "rex.X",          /* 0x42 */
12609       "rex.XB",         /* 0x43 */
12610       "rex.R",          /* 0x44 */
12611       "rex.RB",         /* 0x45 */
12612       "rex.RX",         /* 0x46 */
12613       "rex.RXB",        /* 0x47 */
12614       "rex.W",          /* 0x48 */
12615       "rex.WB",         /* 0x49 */
12616       "rex.WX",         /* 0x4a */
12617       "rex.WXB",        /* 0x4b */
12618       "rex.WR",         /* 0x4c */
12619       "rex.WRB",        /* 0x4d */
12620       "rex.WRX",        /* 0x4e */
12621       "rex.WRXB",       /* 0x4f */
12622     };
12623
12624   switch (pref)
12625     {
12626     /* REX prefixes family.  */
12627     case 0x40:
12628     case 0x41:
12629     case 0x42:
12630     case 0x43:
12631     case 0x44:
12632     case 0x45:
12633     case 0x46:
12634     case 0x47:
12635     case 0x48:
12636     case 0x49:
12637     case 0x4a:
12638     case 0x4b:
12639     case 0x4c:
12640     case 0x4d:
12641     case 0x4e:
12642     case 0x4f:
12643       return rexes [pref - 0x40];
12644     case 0xf3:
12645       return "repz";
12646     case 0xf2:
12647       return "repnz";
12648     case 0xf0:
12649       return "lock";
12650     case 0x2e:
12651       return "cs";
12652     case 0x36:
12653       return "ss";
12654     case 0x3e:
12655       return "ds";
12656     case 0x26:
12657       return "es";
12658     case 0x64:
12659       return "fs";
12660     case 0x65:
12661       return "gs";
12662     case 0x66:
12663       return (sizeflag & DFLAG) ? "data16" : "data32";
12664     case 0x67:
12665       if (address_mode == mode_64bit)
12666         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12667       else
12668         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12669     case FWAIT_OPCODE:
12670       return "fwait";
12671     case REP_PREFIX:
12672       return "rep";
12673     case XACQUIRE_PREFIX:
12674       return "xacquire";
12675     case XRELEASE_PREFIX:
12676       return "xrelease";
12677     case BND_PREFIX:
12678       return "bnd";
12679     default:
12680       return NULL;
12681     }
12682 }
12683
12684 static char op_out[MAX_OPERANDS][100];
12685 static int op_ad, op_index[MAX_OPERANDS];
12686 static int two_source_ops;
12687 static bfd_vma op_address[MAX_OPERANDS];
12688 static bfd_vma op_riprel[MAX_OPERANDS];
12689 static bfd_vma start_pc;
12690
12691 /*
12692  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12693  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12694  *   section of the "Virtual 8086 Mode" chapter.)
12695  * 'pc' should be the address of this instruction, it will
12696  *   be used to print the target address if this is a relative jump or call
12697  * The function returns the length of this instruction in bytes.
12698  */
12699
12700 static char intel_syntax;
12701 static char intel_mnemonic = !SYSV386_COMPAT;
12702 static char open_char;
12703 static char close_char;
12704 static char separator_char;
12705 static char scale_char;
12706
12707 enum x86_64_isa
12708 {
12709   amd64 = 0,
12710   intel64
12711 };
12712
12713 static enum x86_64_isa isa64;
12714
12715 /* Here for backwards compatibility.  When gdb stops using
12716    print_insn_i386_att and print_insn_i386_intel these functions can
12717    disappear, and print_insn_i386 be merged into print_insn.  */
12718 int
12719 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12720 {
12721   intel_syntax = 0;
12722
12723   return print_insn (pc, info);
12724 }
12725
12726 int
12727 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12728 {
12729   intel_syntax = 1;
12730
12731   return print_insn (pc, info);
12732 }
12733
12734 int
12735 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12736 {
12737   intel_syntax = -1;
12738
12739   return print_insn (pc, info);
12740 }
12741
12742 void
12743 print_i386_disassembler_options (FILE *stream)
12744 {
12745   fprintf (stream, _("\n\
12746 The following i386/x86-64 specific disassembler options are supported for use\n\
12747 with the -M switch (multiple options should be separated by commas):\n"));
12748
12749   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12750   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12751   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12752   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12753   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12754   fprintf (stream, _("  att-mnemonic\n"
12755                      "              Display instruction in AT&T mnemonic\n"));
12756   fprintf (stream, _("  intel-mnemonic\n"
12757                      "              Display instruction in Intel mnemonic\n"));
12758   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12759   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12760   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12761   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12762   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12763   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12764   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12765   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12766 }
12767
12768 /* Bad opcode.  */
12769 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12770
12771 /* Get a pointer to struct dis386 with a valid name.  */
12772
12773 static const struct dis386 *
12774 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12775 {
12776   int vindex, vex_table_index;
12777
12778   if (dp->name != NULL)
12779     return dp;
12780
12781   switch (dp->op[0].bytemode)
12782     {
12783     case USE_REG_TABLE:
12784       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12785       break;
12786
12787     case USE_MOD_TABLE:
12788       vindex = modrm.mod == 0x3 ? 1 : 0;
12789       dp = &mod_table[dp->op[1].bytemode][vindex];
12790       break;
12791
12792     case USE_RM_TABLE:
12793       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12794       break;
12795
12796     case USE_PREFIX_TABLE:
12797       if (need_vex)
12798         {
12799           /* The prefix in VEX is implicit.  */
12800           switch (vex.prefix)
12801             {
12802             case 0:
12803               vindex = 0;
12804               break;
12805             case REPE_PREFIX_OPCODE:
12806               vindex = 1;
12807               break;
12808             case DATA_PREFIX_OPCODE:
12809               vindex = 2;
12810               break;
12811             case REPNE_PREFIX_OPCODE:
12812               vindex = 3;
12813               break;
12814             default:
12815               abort ();
12816               break;
12817             }
12818         }
12819       else
12820         {
12821           int last_prefix = -1;
12822           int prefix = 0;
12823           vindex = 0;
12824           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12825              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12826              last one wins.  */
12827           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12828             {
12829               if (last_repz_prefix > last_repnz_prefix)
12830                 {
12831                   vindex = 1;
12832                   prefix = PREFIX_REPZ;
12833                   last_prefix = last_repz_prefix;
12834                 }
12835               else
12836                 {
12837                   vindex = 3;
12838                   prefix = PREFIX_REPNZ;
12839                   last_prefix = last_repnz_prefix;
12840                 }
12841
12842               /* Check if prefix should be ignored.  */
12843               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12844                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12845                    & prefix) != 0)
12846                 vindex = 0;
12847             }
12848
12849           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12850             {
12851               vindex = 2;
12852               prefix = PREFIX_DATA;
12853               last_prefix = last_data_prefix;
12854             }
12855
12856           if (vindex != 0)
12857             {
12858               used_prefixes |= prefix;
12859               all_prefixes[last_prefix] = 0;
12860             }
12861         }
12862       dp = &prefix_table[dp->op[1].bytemode][vindex];
12863       break;
12864
12865     case USE_X86_64_TABLE:
12866       vindex = address_mode == mode_64bit ? 1 : 0;
12867       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12868       break;
12869
12870     case USE_3BYTE_TABLE:
12871       FETCH_DATA (info, codep + 2);
12872       vindex = *codep++;
12873       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12874       end_codep = codep;
12875       modrm.mod = (*codep >> 6) & 3;
12876       modrm.reg = (*codep >> 3) & 7;
12877       modrm.rm = *codep & 7;
12878       break;
12879
12880     case USE_VEX_LEN_TABLE:
12881       if (!need_vex)
12882         abort ();
12883
12884       switch (vex.length)
12885         {
12886         case 128:
12887           vindex = 0;
12888           break;
12889         case 256:
12890           vindex = 1;
12891           break;
12892         default:
12893           abort ();
12894           break;
12895         }
12896
12897       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12898       break;
12899
12900     case USE_XOP_8F_TABLE:
12901       FETCH_DATA (info, codep + 3);
12902       /* All bits in the REX prefix are ignored.  */
12903       rex_ignored = rex;
12904       rex = ~(*codep >> 5) & 0x7;
12905
12906       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12907       switch ((*codep & 0x1f))
12908         {
12909         default:
12910           dp = &bad_opcode;
12911           return dp;
12912         case 0x8:
12913           vex_table_index = XOP_08;
12914           break;
12915         case 0x9:
12916           vex_table_index = XOP_09;
12917           break;
12918         case 0xa:
12919           vex_table_index = XOP_0A;
12920           break;
12921         }
12922       codep++;
12923       vex.w = *codep & 0x80;
12924       if (vex.w && address_mode == mode_64bit)
12925         rex |= REX_W;
12926
12927       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12928       if (address_mode != mode_64bit
12929           && vex.register_specifier > 0x7)
12930         {
12931           dp = &bad_opcode;
12932           return dp;
12933         }
12934
12935       vex.length = (*codep & 0x4) ? 256 : 128;
12936       switch ((*codep & 0x3))
12937         {
12938         case 0:
12939           vex.prefix = 0;
12940           break;
12941         case 1:
12942           vex.prefix = DATA_PREFIX_OPCODE;
12943           break;
12944         case 2:
12945           vex.prefix = REPE_PREFIX_OPCODE;
12946           break;
12947         case 3:
12948           vex.prefix = REPNE_PREFIX_OPCODE;
12949           break;
12950         }
12951       need_vex = 1;
12952       need_vex_reg = 1;
12953       codep++;
12954       vindex = *codep++;
12955       dp = &xop_table[vex_table_index][vindex];
12956
12957       end_codep = codep;
12958       FETCH_DATA (info, codep + 1);
12959       modrm.mod = (*codep >> 6) & 3;
12960       modrm.reg = (*codep >> 3) & 7;
12961       modrm.rm = *codep & 7;
12962       break;
12963
12964     case USE_VEX_C4_TABLE:
12965       /* VEX prefix.  */
12966       FETCH_DATA (info, codep + 3);
12967       /* All bits in the REX prefix are ignored.  */
12968       rex_ignored = rex;
12969       rex = ~(*codep >> 5) & 0x7;
12970       switch ((*codep & 0x1f))
12971         {
12972         default:
12973           dp = &bad_opcode;
12974           return dp;
12975         case 0x1:
12976           vex_table_index = VEX_0F;
12977           break;
12978         case 0x2:
12979           vex_table_index = VEX_0F38;
12980           break;
12981         case 0x3:
12982           vex_table_index = VEX_0F3A;
12983           break;
12984         }
12985       codep++;
12986       vex.w = *codep & 0x80;
12987       if (vex.w && address_mode == mode_64bit)
12988         rex |= REX_W;
12989
12990       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12991       if (address_mode != mode_64bit
12992           && vex.register_specifier > 0x7)
12993         {
12994           dp = &bad_opcode;
12995           return dp;
12996         }
12997
12998       vex.length = (*codep & 0x4) ? 256 : 128;
12999       switch ((*codep & 0x3))
13000         {
13001         case 0:
13002           vex.prefix = 0;
13003           break;
13004         case 1:
13005           vex.prefix = DATA_PREFIX_OPCODE;
13006           break;
13007         case 2:
13008           vex.prefix = REPE_PREFIX_OPCODE;
13009           break;
13010         case 3:
13011           vex.prefix = REPNE_PREFIX_OPCODE;
13012           break;
13013         }
13014       need_vex = 1;
13015       need_vex_reg = 1;
13016       codep++;
13017       vindex = *codep++;
13018       dp = &vex_table[vex_table_index][vindex];
13019       end_codep = codep;
13020       /* There is no MODRM byte for VEX [82|77].  */
13021       if (vindex != 0x77 && vindex != 0x82)
13022         {
13023           FETCH_DATA (info, codep + 1);
13024           modrm.mod = (*codep >> 6) & 3;
13025           modrm.reg = (*codep >> 3) & 7;
13026           modrm.rm = *codep & 7;
13027         }
13028       break;
13029
13030     case USE_VEX_C5_TABLE:
13031       /* VEX prefix.  */
13032       FETCH_DATA (info, codep + 2);
13033       /* All bits in the REX prefix are ignored.  */
13034       rex_ignored = rex;
13035       rex = (*codep & 0x80) ? 0 : REX_R;
13036
13037       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13038       if (address_mode != mode_64bit
13039           && vex.register_specifier > 0x7)
13040         {
13041           dp = &bad_opcode;
13042           return dp;
13043         }
13044
13045       vex.w = 0;
13046
13047       vex.length = (*codep & 0x4) ? 256 : 128;
13048       switch ((*codep & 0x3))
13049         {
13050         case 0:
13051           vex.prefix = 0;
13052           break;
13053         case 1:
13054           vex.prefix = DATA_PREFIX_OPCODE;
13055           break;
13056         case 2:
13057           vex.prefix = REPE_PREFIX_OPCODE;
13058           break;
13059         case 3:
13060           vex.prefix = REPNE_PREFIX_OPCODE;
13061           break;
13062         }
13063       need_vex = 1;
13064       need_vex_reg = 1;
13065       codep++;
13066       vindex = *codep++;
13067       dp = &vex_table[dp->op[1].bytemode][vindex];
13068       end_codep = codep;
13069       /* There is no MODRM byte for VEX [82|77].  */
13070       if (vindex != 0x77 && vindex != 0x82)
13071         {
13072           FETCH_DATA (info, codep + 1);
13073           modrm.mod = (*codep >> 6) & 3;
13074           modrm.reg = (*codep >> 3) & 7;
13075           modrm.rm = *codep & 7;
13076         }
13077       break;
13078
13079     case USE_VEX_W_TABLE:
13080       if (!need_vex)
13081         abort ();
13082
13083       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13084       break;
13085
13086     case USE_EVEX_TABLE:
13087       two_source_ops = 0;
13088       /* EVEX prefix.  */
13089       vex.evex = 1;
13090       FETCH_DATA (info, codep + 4);
13091       /* All bits in the REX prefix are ignored.  */
13092       rex_ignored = rex;
13093       /* The first byte after 0x62.  */
13094       rex = ~(*codep >> 5) & 0x7;
13095       vex.r = *codep & 0x10;
13096       switch ((*codep & 0xf))
13097         {
13098         default:
13099           return &bad_opcode;
13100         case 0x1:
13101           vex_table_index = EVEX_0F;
13102           break;
13103         case 0x2:
13104           vex_table_index = EVEX_0F38;
13105           break;
13106         case 0x3:
13107           vex_table_index = EVEX_0F3A;
13108           break;
13109         }
13110
13111       /* The second byte after 0x62.  */
13112       codep++;
13113       vex.w = *codep & 0x80;
13114       if (vex.w && address_mode == mode_64bit)
13115         rex |= REX_W;
13116
13117       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13118       if (address_mode != mode_64bit)
13119         {
13120           /* In 16/32-bit mode silently ignore following bits.  */
13121           rex &= ~REX_B;
13122           vex.r = 1;
13123           vex.v = 1;
13124           vex.register_specifier &= 0x7;
13125         }
13126
13127       /* The U bit.  */
13128       if (!(*codep & 0x4))
13129         return &bad_opcode;
13130
13131       switch ((*codep & 0x3))
13132         {
13133         case 0:
13134           vex.prefix = 0;
13135           break;
13136         case 1:
13137           vex.prefix = DATA_PREFIX_OPCODE;
13138           break;
13139         case 2:
13140           vex.prefix = REPE_PREFIX_OPCODE;
13141           break;
13142         case 3:
13143           vex.prefix = REPNE_PREFIX_OPCODE;
13144           break;
13145         }
13146
13147       /* The third byte after 0x62.  */
13148       codep++;
13149
13150       /* Remember the static rounding bits.  */
13151       vex.ll = (*codep >> 5) & 3;
13152       vex.b = (*codep & 0x10) != 0;
13153
13154       vex.v = *codep & 0x8;
13155       vex.mask_register_specifier = *codep & 0x7;
13156       vex.zeroing = *codep & 0x80;
13157
13158       need_vex = 1;
13159       need_vex_reg = 1;
13160       codep++;
13161       vindex = *codep++;
13162       dp = &evex_table[vex_table_index][vindex];
13163       end_codep = codep;
13164       FETCH_DATA (info, codep + 1);
13165       modrm.mod = (*codep >> 6) & 3;
13166       modrm.reg = (*codep >> 3) & 7;
13167       modrm.rm = *codep & 7;
13168
13169       /* Set vector length.  */
13170       if (modrm.mod == 3 && vex.b)
13171         vex.length = 512;
13172       else
13173         {
13174           switch (vex.ll)
13175             {
13176             case 0x0:
13177               vex.length = 128;
13178               break;
13179             case 0x1:
13180               vex.length = 256;
13181               break;
13182             case 0x2:
13183               vex.length = 512;
13184               break;
13185             default:
13186               return &bad_opcode;
13187             }
13188         }
13189       break;
13190
13191     case 0:
13192       dp = &bad_opcode;
13193       break;
13194
13195     default:
13196       abort ();
13197     }
13198
13199   if (dp->name != NULL)
13200     return dp;
13201   else
13202     return get_valid_dis386 (dp, info);
13203 }
13204
13205 static void
13206 get_sib (disassemble_info *info, int sizeflag)
13207 {
13208   /* If modrm.mod == 3, operand must be register.  */
13209   if (need_modrm
13210       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13211       && modrm.mod != 3
13212       && modrm.rm == 4)
13213     {
13214       FETCH_DATA (info, codep + 2);
13215       sib.index = (codep [1] >> 3) & 7;
13216       sib.scale = (codep [1] >> 6) & 3;
13217       sib.base = codep [1] & 7;
13218     }
13219 }
13220
13221 static int
13222 print_insn (bfd_vma pc, disassemble_info *info)
13223 {
13224   const struct dis386 *dp;
13225   int i;
13226   char *op_txt[MAX_OPERANDS];
13227   int needcomma;
13228   int sizeflag, orig_sizeflag;
13229   const char *p;
13230   struct dis_private priv;
13231   int prefix_length;
13232
13233   priv.orig_sizeflag = AFLAG | DFLAG;
13234   if ((info->mach & bfd_mach_i386_i386) != 0)
13235     address_mode = mode_32bit;
13236   else if (info->mach == bfd_mach_i386_i8086)
13237     {
13238       address_mode = mode_16bit;
13239       priv.orig_sizeflag = 0;
13240     }
13241   else
13242     address_mode = mode_64bit;
13243
13244   if (intel_syntax == (char) -1)
13245     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13246
13247   for (p = info->disassembler_options; p != NULL; )
13248     {
13249       if (CONST_STRNEQ (p, "amd64"))
13250         isa64 = amd64;
13251       else if (CONST_STRNEQ (p, "intel64"))
13252         isa64 = intel64;
13253       else if (CONST_STRNEQ (p, "x86-64"))
13254         {
13255           address_mode = mode_64bit;
13256           priv.orig_sizeflag = AFLAG | DFLAG;
13257         }
13258       else if (CONST_STRNEQ (p, "i386"))
13259         {
13260           address_mode = mode_32bit;
13261           priv.orig_sizeflag = AFLAG | DFLAG;
13262         }
13263       else if (CONST_STRNEQ (p, "i8086"))
13264         {
13265           address_mode = mode_16bit;
13266           priv.orig_sizeflag = 0;
13267         }
13268       else if (CONST_STRNEQ (p, "intel"))
13269         {
13270           intel_syntax = 1;
13271           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13272             intel_mnemonic = 1;
13273         }
13274       else if (CONST_STRNEQ (p, "att"))
13275         {
13276           intel_syntax = 0;
13277           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13278             intel_mnemonic = 0;
13279         }
13280       else if (CONST_STRNEQ (p, "addr"))
13281         {
13282           if (address_mode == mode_64bit)
13283             {
13284               if (p[4] == '3' && p[5] == '2')
13285                 priv.orig_sizeflag &= ~AFLAG;
13286               else if (p[4] == '6' && p[5] == '4')
13287                 priv.orig_sizeflag |= AFLAG;
13288             }
13289           else
13290             {
13291               if (p[4] == '1' && p[5] == '6')
13292                 priv.orig_sizeflag &= ~AFLAG;
13293               else if (p[4] == '3' && p[5] == '2')
13294                 priv.orig_sizeflag |= AFLAG;
13295             }
13296         }
13297       else if (CONST_STRNEQ (p, "data"))
13298         {
13299           if (p[4] == '1' && p[5] == '6')
13300             priv.orig_sizeflag &= ~DFLAG;
13301           else if (p[4] == '3' && p[5] == '2')
13302             priv.orig_sizeflag |= DFLAG;
13303         }
13304       else if (CONST_STRNEQ (p, "suffix"))
13305         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13306
13307       p = strchr (p, ',');
13308       if (p != NULL)
13309         p++;
13310     }
13311
13312   if (intel_syntax)
13313     {
13314       names64 = intel_names64;
13315       names32 = intel_names32;
13316       names16 = intel_names16;
13317       names8 = intel_names8;
13318       names8rex = intel_names8rex;
13319       names_seg = intel_names_seg;
13320       names_mm = intel_names_mm;
13321       names_bnd = intel_names_bnd;
13322       names_xmm = intel_names_xmm;
13323       names_ymm = intel_names_ymm;
13324       names_zmm = intel_names_zmm;
13325       index64 = intel_index64;
13326       index32 = intel_index32;
13327       names_mask = intel_names_mask;
13328       index16 = intel_index16;
13329       open_char = '[';
13330       close_char = ']';
13331       separator_char = '+';
13332       scale_char = '*';
13333     }
13334   else
13335     {
13336       names64 = att_names64;
13337       names32 = att_names32;
13338       names16 = att_names16;
13339       names8 = att_names8;
13340       names8rex = att_names8rex;
13341       names_seg = att_names_seg;
13342       names_mm = att_names_mm;
13343       names_bnd = att_names_bnd;
13344       names_xmm = att_names_xmm;
13345       names_ymm = att_names_ymm;
13346       names_zmm = att_names_zmm;
13347       index64 = att_index64;
13348       index32 = att_index32;
13349       names_mask = att_names_mask;
13350       index16 = att_index16;
13351       open_char = '(';
13352       close_char =  ')';
13353       separator_char = ',';
13354       scale_char = ',';
13355     }
13356
13357   /* The output looks better if we put 7 bytes on a line, since that
13358      puts most long word instructions on a single line.  Use 8 bytes
13359      for Intel L1OM.  */
13360   if ((info->mach & bfd_mach_l1om) != 0)
13361     info->bytes_per_line = 8;
13362   else
13363     info->bytes_per_line = 7;
13364
13365   info->private_data = &priv;
13366   priv.max_fetched = priv.the_buffer;
13367   priv.insn_start = pc;
13368
13369   obuf[0] = 0;
13370   for (i = 0; i < MAX_OPERANDS; ++i)
13371     {
13372       op_out[i][0] = 0;
13373       op_index[i] = -1;
13374     }
13375
13376   the_info = info;
13377   start_pc = pc;
13378   start_codep = priv.the_buffer;
13379   codep = priv.the_buffer;
13380
13381   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13382     {
13383       const char *name;
13384
13385       /* Getting here means we tried for data but didn't get it.  That
13386          means we have an incomplete instruction of some sort.  Just
13387          print the first byte as a prefix or a .byte pseudo-op.  */
13388       if (codep > priv.the_buffer)
13389         {
13390           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13391           if (name != NULL)
13392             (*info->fprintf_func) (info->stream, "%s", name);
13393           else
13394             {
13395               /* Just print the first byte as a .byte instruction.  */
13396               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13397                                      (unsigned int) priv.the_buffer[0]);
13398             }
13399
13400           return 1;
13401         }
13402
13403       return -1;
13404     }
13405
13406   obufp = obuf;
13407   sizeflag = priv.orig_sizeflag;
13408
13409   if (!ckprefix () || rex_used)
13410     {
13411       /* Too many prefixes or unused REX prefixes.  */
13412       for (i = 0;
13413            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13414            i++)
13415         (*info->fprintf_func) (info->stream, "%s%s",
13416                                i == 0 ? "" : " ",
13417                                prefix_name (all_prefixes[i], sizeflag));
13418       return i;
13419     }
13420
13421   insn_codep = codep;
13422
13423   FETCH_DATA (info, codep + 1);
13424   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13425
13426   if (((prefixes & PREFIX_FWAIT)
13427        && ((*codep < 0xd8) || (*codep > 0xdf))))
13428     {
13429       /* Handle prefixes before fwait.  */
13430       for (i = 0; i < fwait_prefix && all_prefixes[i];
13431            i++)
13432         (*info->fprintf_func) (info->stream, "%s ",
13433                                prefix_name (all_prefixes[i], sizeflag));
13434       (*info->fprintf_func) (info->stream, "fwait");
13435       return i + 1;
13436     }
13437
13438   if (*codep == 0x0f)
13439     {
13440       unsigned char threebyte;
13441       FETCH_DATA (info, codep + 2);
13442       threebyte = *++codep;
13443       dp = &dis386_twobyte[threebyte];
13444       need_modrm = twobyte_has_modrm[*codep];
13445       codep++;
13446     }
13447   else
13448     {
13449       dp = &dis386[*codep];
13450       need_modrm = onebyte_has_modrm[*codep];
13451       codep++;
13452     }
13453
13454   /* Save sizeflag for printing the extra prefixes later before updating
13455      it for mnemonic and operand processing.  The prefix names depend
13456      only on the address mode.  */
13457   orig_sizeflag = sizeflag;
13458   if (prefixes & PREFIX_ADDR)
13459     sizeflag ^= AFLAG;
13460   if ((prefixes & PREFIX_DATA))
13461     sizeflag ^= DFLAG;
13462
13463   end_codep = codep;
13464   if (need_modrm)
13465     {
13466       FETCH_DATA (info, codep + 1);
13467       modrm.mod = (*codep >> 6) & 3;
13468       modrm.reg = (*codep >> 3) & 7;
13469       modrm.rm = *codep & 7;
13470     }
13471
13472   need_vex = 0;
13473   need_vex_reg = 0;
13474   vex_w_done = 0;
13475   vex.evex = 0;
13476
13477   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13478     {
13479       get_sib (info, sizeflag);
13480       dofloat (sizeflag);
13481     }
13482   else
13483     {
13484       dp = get_valid_dis386 (dp, info);
13485       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13486         {
13487           get_sib (info, sizeflag);
13488           for (i = 0; i < MAX_OPERANDS; ++i)
13489             {
13490               obufp = op_out[i];
13491               op_ad = MAX_OPERANDS - 1 - i;
13492               if (dp->op[i].rtn)
13493                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13494               /* For EVEX instruction after the last operand masking
13495                  should be printed.  */
13496               if (i == 0 && vex.evex)
13497                 {
13498                   /* Don't print {%k0}.  */
13499                   if (vex.mask_register_specifier)
13500                     {
13501                       oappend ("{");
13502                       oappend (names_mask[vex.mask_register_specifier]);
13503                       oappend ("}");
13504                     }
13505                   if (vex.zeroing)
13506                     oappend ("{z}");
13507                 }
13508             }
13509         }
13510     }
13511
13512   /* Check if the REX prefix is used.  */
13513   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13514     all_prefixes[last_rex_prefix] = 0;
13515
13516   /* Check if the SEG prefix is used.  */
13517   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13518                    | PREFIX_FS | PREFIX_GS)) != 0
13519       && (used_prefixes & active_seg_prefix) != 0)
13520     all_prefixes[last_seg_prefix] = 0;
13521
13522   /* Check if the ADDR prefix is used.  */
13523   if ((prefixes & PREFIX_ADDR) != 0
13524       && (used_prefixes & PREFIX_ADDR) != 0)
13525     all_prefixes[last_addr_prefix] = 0;
13526
13527   /* Check if the DATA prefix is used.  */
13528   if ((prefixes & PREFIX_DATA) != 0
13529       && (used_prefixes & PREFIX_DATA) != 0)
13530     all_prefixes[last_data_prefix] = 0;
13531
13532   /* Print the extra prefixes.  */
13533   prefix_length = 0;
13534   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13535     if (all_prefixes[i])
13536       {
13537         const char *name;
13538         name = prefix_name (all_prefixes[i], orig_sizeflag);
13539         if (name == NULL)
13540           abort ();
13541         prefix_length += strlen (name) + 1;
13542         (*info->fprintf_func) (info->stream, "%s ", name);
13543       }
13544
13545   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13546      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13547      used by putop and MMX/SSE operand and may be overriden by the
13548      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13549      separately.  */
13550   if (dp->prefix_requirement == PREFIX_OPCODE
13551       && dp != &bad_opcode
13552       && (((prefixes
13553             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13554            && (used_prefixes
13555                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13556           || ((((prefixes
13557                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13558                 == PREFIX_DATA)
13559                && (used_prefixes & PREFIX_DATA) == 0))))
13560     {
13561       (*info->fprintf_func) (info->stream, "(bad)");
13562       return end_codep - priv.the_buffer;
13563     }
13564
13565   /* Check maximum code length.  */
13566   if ((codep - start_codep) > MAX_CODE_LENGTH)
13567     {
13568       (*info->fprintf_func) (info->stream, "(bad)");
13569       return MAX_CODE_LENGTH;
13570     }
13571
13572   obufp = mnemonicendp;
13573   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13574     oappend (" ");
13575   oappend (" ");
13576   (*info->fprintf_func) (info->stream, "%s", obuf);
13577
13578   /* The enter and bound instructions are printed with operands in the same
13579      order as the intel book; everything else is printed in reverse order.  */
13580   if (intel_syntax || two_source_ops)
13581     {
13582       bfd_vma riprel;
13583
13584       for (i = 0; i < MAX_OPERANDS; ++i)
13585         op_txt[i] = op_out[i];
13586
13587       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13588           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13589         {
13590           op_txt[2] = op_out[3];
13591           op_txt[3] = op_out[2];
13592         }
13593
13594       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13595         {
13596           op_ad = op_index[i];
13597           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13598           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13599           riprel = op_riprel[i];
13600           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13601           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13602         }
13603     }
13604   else
13605     {
13606       for (i = 0; i < MAX_OPERANDS; ++i)
13607         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13608     }
13609
13610   needcomma = 0;
13611   for (i = 0; i < MAX_OPERANDS; ++i)
13612     if (*op_txt[i])
13613       {
13614         if (needcomma)
13615           (*info->fprintf_func) (info->stream, ",");
13616         if (op_index[i] != -1 && !op_riprel[i])
13617           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13618         else
13619           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13620         needcomma = 1;
13621       }
13622
13623   for (i = 0; i < MAX_OPERANDS; i++)
13624     if (op_index[i] != -1 && op_riprel[i])
13625       {
13626         (*info->fprintf_func) (info->stream, "        # ");
13627         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13628                                                 + op_address[op_index[i]]), info);
13629         break;
13630       }
13631   return codep - priv.the_buffer;
13632 }
13633
13634 static const char *float_mem[] = {
13635   /* d8 */
13636   "fadd{s|}",
13637   "fmul{s|}",
13638   "fcom{s|}",
13639   "fcomp{s|}",
13640   "fsub{s|}",
13641   "fsubr{s|}",
13642   "fdiv{s|}",
13643   "fdivr{s|}",
13644   /* d9 */
13645   "fld{s|}",
13646   "(bad)",
13647   "fst{s|}",
13648   "fstp{s|}",
13649   "fldenvIC",
13650   "fldcw",
13651   "fNstenvIC",
13652   "fNstcw",
13653   /* da */
13654   "fiadd{l|}",
13655   "fimul{l|}",
13656   "ficom{l|}",
13657   "ficomp{l|}",
13658   "fisub{l|}",
13659   "fisubr{l|}",
13660   "fidiv{l|}",
13661   "fidivr{l|}",
13662   /* db */
13663   "fild{l|}",
13664   "fisttp{l|}",
13665   "fist{l|}",
13666   "fistp{l|}",
13667   "(bad)",
13668   "fld{t||t|}",
13669   "(bad)",
13670   "fstp{t||t|}",
13671   /* dc */
13672   "fadd{l|}",
13673   "fmul{l|}",
13674   "fcom{l|}",
13675   "fcomp{l|}",
13676   "fsub{l|}",
13677   "fsubr{l|}",
13678   "fdiv{l|}",
13679   "fdivr{l|}",
13680   /* dd */
13681   "fld{l|}",
13682   "fisttp{ll|}",
13683   "fst{l||}",
13684   "fstp{l|}",
13685   "frstorIC",
13686   "(bad)",
13687   "fNsaveIC",
13688   "fNstsw",
13689   /* de */
13690   "fiadd",
13691   "fimul",
13692   "ficom",
13693   "ficomp",
13694   "fisub",
13695   "fisubr",
13696   "fidiv",
13697   "fidivr",
13698   /* df */
13699   "fild",
13700   "fisttp",
13701   "fist",
13702   "fistp",
13703   "fbld",
13704   "fild{ll|}",
13705   "fbstp",
13706   "fistp{ll|}",
13707 };
13708
13709 static const unsigned char float_mem_mode[] = {
13710   /* d8 */
13711   d_mode,
13712   d_mode,
13713   d_mode,
13714   d_mode,
13715   d_mode,
13716   d_mode,
13717   d_mode,
13718   d_mode,
13719   /* d9 */
13720   d_mode,
13721   0,
13722   d_mode,
13723   d_mode,
13724   0,
13725   w_mode,
13726   0,
13727   w_mode,
13728   /* da */
13729   d_mode,
13730   d_mode,
13731   d_mode,
13732   d_mode,
13733   d_mode,
13734   d_mode,
13735   d_mode,
13736   d_mode,
13737   /* db */
13738   d_mode,
13739   d_mode,
13740   d_mode,
13741   d_mode,
13742   0,
13743   t_mode,
13744   0,
13745   t_mode,
13746   /* dc */
13747   q_mode,
13748   q_mode,
13749   q_mode,
13750   q_mode,
13751   q_mode,
13752   q_mode,
13753   q_mode,
13754   q_mode,
13755   /* dd */
13756   q_mode,
13757   q_mode,
13758   q_mode,
13759   q_mode,
13760   0,
13761   0,
13762   0,
13763   w_mode,
13764   /* de */
13765   w_mode,
13766   w_mode,
13767   w_mode,
13768   w_mode,
13769   w_mode,
13770   w_mode,
13771   w_mode,
13772   w_mode,
13773   /* df */
13774   w_mode,
13775   w_mode,
13776   w_mode,
13777   w_mode,
13778   t_mode,
13779   q_mode,
13780   t_mode,
13781   q_mode
13782 };
13783
13784 #define ST { OP_ST, 0 }
13785 #define STi { OP_STi, 0 }
13786
13787 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13788 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13789 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13790 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13791 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13792 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13793 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13794 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13795 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13796
13797 static const struct dis386 float_reg[][8] = {
13798   /* d8 */
13799   {
13800     { "fadd",   { ST, STi }, 0 },
13801     { "fmul",   { ST, STi }, 0 },
13802     { "fcom",   { STi }, 0 },
13803     { "fcomp",  { STi }, 0 },
13804     { "fsub",   { ST, STi }, 0 },
13805     { "fsubr",  { ST, STi }, 0 },
13806     { "fdiv",   { ST, STi }, 0 },
13807     { "fdivr",  { ST, STi }, 0 },
13808   },
13809   /* d9 */
13810   {
13811     { "fld",    { STi }, 0 },
13812     { "fxch",   { STi }, 0 },
13813     { FGRPd9_2 },
13814     { Bad_Opcode },
13815     { FGRPd9_4 },
13816     { FGRPd9_5 },
13817     { FGRPd9_6 },
13818     { FGRPd9_7 },
13819   },
13820   /* da */
13821   {
13822     { "fcmovb", { ST, STi }, 0 },
13823     { "fcmove", { ST, STi }, 0 },
13824     { "fcmovbe",{ ST, STi }, 0 },
13825     { "fcmovu", { ST, STi }, 0 },
13826     { Bad_Opcode },
13827     { FGRPda_5 },
13828     { Bad_Opcode },
13829     { Bad_Opcode },
13830   },
13831   /* db */
13832   {
13833     { "fcmovnb",{ ST, STi }, 0 },
13834     { "fcmovne",{ ST, STi }, 0 },
13835     { "fcmovnbe",{ ST, STi }, 0 },
13836     { "fcmovnu",{ ST, STi }, 0 },
13837     { FGRPdb_4 },
13838     { "fucomi", { ST, STi }, 0 },
13839     { "fcomi",  { ST, STi }, 0 },
13840     { Bad_Opcode },
13841   },
13842   /* dc */
13843   {
13844     { "fadd",   { STi, ST }, 0 },
13845     { "fmul",   { STi, ST }, 0 },
13846     { Bad_Opcode },
13847     { Bad_Opcode },
13848     { "fsub!M", { STi, ST }, 0 },
13849     { "fsubM",  { STi, ST }, 0 },
13850     { "fdiv!M", { STi, ST }, 0 },
13851     { "fdivM",  { STi, ST }, 0 },
13852   },
13853   /* dd */
13854   {
13855     { "ffree",  { STi }, 0 },
13856     { Bad_Opcode },
13857     { "fst",    { STi }, 0 },
13858     { "fstp",   { STi }, 0 },
13859     { "fucom",  { STi }, 0 },
13860     { "fucomp", { STi }, 0 },
13861     { Bad_Opcode },
13862     { Bad_Opcode },
13863   },
13864   /* de */
13865   {
13866     { "faddp",  { STi, ST }, 0 },
13867     { "fmulp",  { STi, ST }, 0 },
13868     { Bad_Opcode },
13869     { FGRPde_3 },
13870     { "fsub!Mp", { STi, ST }, 0 },
13871     { "fsubMp", { STi, ST }, 0 },
13872     { "fdiv!Mp", { STi, ST }, 0 },
13873     { "fdivMp", { STi, ST }, 0 },
13874   },
13875   /* df */
13876   {
13877     { "ffreep", { STi }, 0 },
13878     { Bad_Opcode },
13879     { Bad_Opcode },
13880     { Bad_Opcode },
13881     { FGRPdf_4 },
13882     { "fucomip", { ST, STi }, 0 },
13883     { "fcomip", { ST, STi }, 0 },
13884     { Bad_Opcode },
13885   },
13886 };
13887
13888 static char *fgrps[][8] = {
13889   /* d9_2  0 */
13890   {
13891     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13892   },
13893
13894   /* d9_4  1 */
13895   {
13896     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13897   },
13898
13899   /* d9_5  2 */
13900   {
13901     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13902   },
13903
13904   /* d9_6  3 */
13905   {
13906     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13907   },
13908
13909   /* d9_7  4 */
13910   {
13911     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13912   },
13913
13914   /* da_5  5 */
13915   {
13916     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13917   },
13918
13919   /* db_4  6 */
13920   {
13921     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13922     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13923   },
13924
13925   /* de_3  7 */
13926   {
13927     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13928   },
13929
13930   /* df_4  8 */
13931   {
13932     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13933   },
13934 };
13935
13936 static void
13937 swap_operand (void)
13938 {
13939   mnemonicendp[0] = '.';
13940   mnemonicendp[1] = 's';
13941   mnemonicendp += 2;
13942 }
13943
13944 static void
13945 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13946                int sizeflag ATTRIBUTE_UNUSED)
13947 {
13948   /* Skip mod/rm byte.  */
13949   MODRM_CHECK;
13950   codep++;
13951 }
13952
13953 static void
13954 dofloat (int sizeflag)
13955 {
13956   const struct dis386 *dp;
13957   unsigned char floatop;
13958
13959   floatop = codep[-1];
13960
13961   if (modrm.mod != 3)
13962     {
13963       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13964
13965       putop (float_mem[fp_indx], sizeflag);
13966       obufp = op_out[0];
13967       op_ad = 2;
13968       OP_E (float_mem_mode[fp_indx], sizeflag);
13969       return;
13970     }
13971   /* Skip mod/rm byte.  */
13972   MODRM_CHECK;
13973   codep++;
13974
13975   dp = &float_reg[floatop - 0xd8][modrm.reg];
13976   if (dp->name == NULL)
13977     {
13978       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13979
13980       /* Instruction fnstsw is only one with strange arg.  */
13981       if (floatop == 0xdf && codep[-1] == 0xe0)
13982         strcpy (op_out[0], names16[0]);
13983     }
13984   else
13985     {
13986       putop (dp->name, sizeflag);
13987
13988       obufp = op_out[0];
13989       op_ad = 2;
13990       if (dp->op[0].rtn)
13991         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13992
13993       obufp = op_out[1];
13994       op_ad = 1;
13995       if (dp->op[1].rtn)
13996         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13997     }
13998 }
13999
14000 /* Like oappend (below), but S is a string starting with '%'.
14001    In Intel syntax, the '%' is elided.  */
14002 static void
14003 oappend_maybe_intel (const char *s)
14004 {
14005   oappend (s + intel_syntax);
14006 }
14007
14008 static void
14009 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14010 {
14011   oappend_maybe_intel ("%st");
14012 }
14013
14014 static void
14015 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14016 {
14017   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14018   oappend_maybe_intel (scratchbuf);
14019 }
14020
14021 /* Capital letters in template are macros.  */
14022 static int
14023 putop (const char *in_template, int sizeflag)
14024 {
14025   const char *p;
14026   int alt = 0;
14027   int cond = 1;
14028   unsigned int l = 0, len = 1;
14029   char last[4];
14030
14031 #define SAVE_LAST(c)                    \
14032   if (l < len && l < sizeof (last))     \
14033     last[l++] = c;                      \
14034   else                                  \
14035     abort ();
14036
14037   for (p = in_template; *p; p++)
14038     {
14039       switch (*p)
14040         {
14041         default:
14042           *obufp++ = *p;
14043           break;
14044         case '%':
14045           len++;
14046           break;
14047         case '!':
14048           cond = 0;
14049           break;
14050         case '{':
14051           alt = 0;
14052           if (intel_syntax)
14053             {
14054               while (*++p != '|')
14055                 if (*p == '}' || *p == '\0')
14056                   abort ();
14057             }
14058           /* Fall through.  */
14059         case 'I':
14060           alt = 1;
14061           continue;
14062         case '|':
14063           while (*++p != '}')
14064             {
14065               if (*p == '\0')
14066                 abort ();
14067             }
14068           break;
14069         case '}':
14070           break;
14071         case 'A':
14072           if (intel_syntax)
14073             break;
14074           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14075             *obufp++ = 'b';
14076           break;
14077         case 'B':
14078           if (l == 0 && len == 1)
14079             {
14080 case_B:
14081               if (intel_syntax)
14082                 break;
14083               if (sizeflag & SUFFIX_ALWAYS)
14084                 *obufp++ = 'b';
14085             }
14086           else
14087             {
14088               if (l != 1
14089                   || len != 2
14090                   || last[0] != 'L')
14091                 {
14092                   SAVE_LAST (*p);
14093                   break;
14094                 }
14095
14096               if (address_mode == mode_64bit
14097                   && !(prefixes & PREFIX_ADDR))
14098                 {
14099                   *obufp++ = 'a';
14100                   *obufp++ = 'b';
14101                   *obufp++ = 's';
14102                 }
14103
14104               goto case_B;
14105             }
14106           break;
14107         case 'C':
14108           if (intel_syntax && !alt)
14109             break;
14110           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14111             {
14112               if (sizeflag & DFLAG)
14113                 *obufp++ = intel_syntax ? 'd' : 'l';
14114               else
14115                 *obufp++ = intel_syntax ? 'w' : 's';
14116               used_prefixes |= (prefixes & PREFIX_DATA);
14117             }
14118           break;
14119         case 'D':
14120           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14121             break;
14122           USED_REX (REX_W);
14123           if (modrm.mod == 3)
14124             {
14125               if (rex & REX_W)
14126                 *obufp++ = 'q';
14127               else
14128                 {
14129                   if (sizeflag & DFLAG)
14130                     *obufp++ = intel_syntax ? 'd' : 'l';
14131                   else
14132                     *obufp++ = 'w';
14133                   used_prefixes |= (prefixes & PREFIX_DATA);
14134                 }
14135             }
14136           else
14137             *obufp++ = 'w';
14138           break;
14139         case 'E':               /* For jcxz/jecxz */
14140           if (address_mode == mode_64bit)
14141             {
14142               if (sizeflag & AFLAG)
14143                 *obufp++ = 'r';
14144               else
14145                 *obufp++ = 'e';
14146             }
14147           else
14148             if (sizeflag & AFLAG)
14149               *obufp++ = 'e';
14150           used_prefixes |= (prefixes & PREFIX_ADDR);
14151           break;
14152         case 'F':
14153           if (intel_syntax)
14154             break;
14155           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14156             {
14157               if (sizeflag & AFLAG)
14158                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14159               else
14160                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14161               used_prefixes |= (prefixes & PREFIX_ADDR);
14162             }
14163           break;
14164         case 'G':
14165           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14166             break;
14167           if ((rex & REX_W) || (sizeflag & DFLAG))
14168             *obufp++ = 'l';
14169           else
14170             *obufp++ = 'w';
14171           if (!(rex & REX_W))
14172             used_prefixes |= (prefixes & PREFIX_DATA);
14173           break;
14174         case 'H':
14175           if (intel_syntax)
14176             break;
14177           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14178               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14179             {
14180               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14181               *obufp++ = ',';
14182               *obufp++ = 'p';
14183               if (prefixes & PREFIX_DS)
14184                 *obufp++ = 't';
14185               else
14186                 *obufp++ = 'n';
14187             }
14188           break;
14189         case 'J':
14190           if (intel_syntax)
14191             break;
14192           *obufp++ = 'l';
14193           break;
14194         case 'K':
14195           USED_REX (REX_W);
14196           if (rex & REX_W)
14197             *obufp++ = 'q';
14198           else
14199             *obufp++ = 'd';
14200           break;
14201         case 'Z':
14202           if (l != 0 || len != 1)
14203             {
14204               if (l != 1 || len != 2 || last[0] != 'X')
14205                 {
14206                   SAVE_LAST (*p);
14207                   break;
14208                 }
14209               if (!need_vex || !vex.evex)
14210                 abort ();
14211               if (intel_syntax
14212                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14213                 break;
14214               switch (vex.length)
14215                 {
14216                 case 128:
14217                   *obufp++ = 'x';
14218                   break;
14219                 case 256:
14220                   *obufp++ = 'y';
14221                   break;
14222                 case 512:
14223                   *obufp++ = 'z';
14224                   break;
14225                 default:
14226                   abort ();
14227                 }
14228               break;
14229             }
14230           if (intel_syntax)
14231             break;
14232           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14233             {
14234               *obufp++ = 'q';
14235               break;
14236             }
14237           /* Fall through.  */
14238           goto case_L;
14239         case 'L':
14240           if (l != 0 || len != 1)
14241             {
14242               SAVE_LAST (*p);
14243               break;
14244             }
14245 case_L:
14246           if (intel_syntax)
14247             break;
14248           if (sizeflag & SUFFIX_ALWAYS)
14249             *obufp++ = 'l';
14250           break;
14251         case 'M':
14252           if (intel_mnemonic != cond)
14253             *obufp++ = 'r';
14254           break;
14255         case 'N':
14256           if ((prefixes & PREFIX_FWAIT) == 0)
14257             *obufp++ = 'n';
14258           else
14259             used_prefixes |= PREFIX_FWAIT;
14260           break;
14261         case 'O':
14262           USED_REX (REX_W);
14263           if (rex & REX_W)
14264             *obufp++ = 'o';
14265           else if (intel_syntax && (sizeflag & DFLAG))
14266             *obufp++ = 'q';
14267           else
14268             *obufp++ = 'd';
14269           if (!(rex & REX_W))
14270             used_prefixes |= (prefixes & PREFIX_DATA);
14271           break;
14272         case 'T':
14273           if (!intel_syntax
14274               && address_mode == mode_64bit
14275               && ((sizeflag & DFLAG) || (rex & REX_W)))
14276             {
14277               *obufp++ = 'q';
14278               break;
14279             }
14280           /* Fall through.  */
14281           goto case_P;
14282         case 'P':
14283           if (l == 0 && len == 1)
14284             {
14285 case_P:
14286               if (intel_syntax)
14287                 {
14288                   if ((rex & REX_W) == 0
14289                       && (prefixes & PREFIX_DATA))
14290                     {
14291                       if ((sizeflag & DFLAG) == 0)
14292                         *obufp++ = 'w';
14293                       used_prefixes |= (prefixes & PREFIX_DATA);
14294                     }
14295                   break;
14296                 }
14297               if ((prefixes & PREFIX_DATA)
14298                   || (rex & REX_W)
14299                   || (sizeflag & SUFFIX_ALWAYS))
14300                 {
14301                   USED_REX (REX_W);
14302                   if (rex & REX_W)
14303                     *obufp++ = 'q';
14304                   else
14305                     {
14306                       if (sizeflag & DFLAG)
14307                         *obufp++ = 'l';
14308                       else
14309                         *obufp++ = 'w';
14310                       used_prefixes |= (prefixes & PREFIX_DATA);
14311                     }
14312                 }
14313             }
14314           else
14315             {
14316               if (l != 1 || len != 2 || last[0] != 'L')
14317                 {
14318                   SAVE_LAST (*p);
14319                   break;
14320                 }
14321
14322               if ((prefixes & PREFIX_DATA)
14323                   || (rex & REX_W)
14324                   || (sizeflag & SUFFIX_ALWAYS))
14325                 {
14326                   USED_REX (REX_W);
14327                   if (rex & REX_W)
14328                     *obufp++ = 'q';
14329                   else
14330                     {
14331                       if (sizeflag & DFLAG)
14332                         *obufp++ = intel_syntax ? 'd' : 'l';
14333                       else
14334                         *obufp++ = 'w';
14335                       used_prefixes |= (prefixes & PREFIX_DATA);
14336                     }
14337                 }
14338             }
14339           break;
14340         case 'U':
14341           if (intel_syntax)
14342             break;
14343           if (address_mode == mode_64bit
14344               && ((sizeflag & DFLAG) || (rex & REX_W)))
14345             {
14346               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14347                 *obufp++ = 'q';
14348               break;
14349             }
14350           /* Fall through.  */
14351           goto case_Q;
14352         case 'Q':
14353           if (l == 0 && len == 1)
14354             {
14355 case_Q:
14356               if (intel_syntax && !alt)
14357                 break;
14358               USED_REX (REX_W);
14359               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14360                 {
14361                   if (rex & REX_W)
14362                     *obufp++ = 'q';
14363                   else
14364                     {
14365                       if (sizeflag & DFLAG)
14366                         *obufp++ = intel_syntax ? 'd' : 'l';
14367                       else
14368                         *obufp++ = 'w';
14369                       used_prefixes |= (prefixes & PREFIX_DATA);
14370                     }
14371                 }
14372             }
14373           else
14374             {
14375               if (l != 1 || len != 2 || last[0] != 'L')
14376                 {
14377                   SAVE_LAST (*p);
14378                   break;
14379                 }
14380               if (intel_syntax
14381                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14382                 break;
14383               if ((rex & REX_W))
14384                 {
14385                   USED_REX (REX_W);
14386                   *obufp++ = 'q';
14387                 }
14388               else
14389                 *obufp++ = 'l';
14390             }
14391           break;
14392         case 'R':
14393           USED_REX (REX_W);
14394           if (rex & REX_W)
14395             *obufp++ = 'q';
14396           else if (sizeflag & DFLAG)
14397             {
14398               if (intel_syntax)
14399                   *obufp++ = 'd';
14400               else
14401                   *obufp++ = 'l';
14402             }
14403           else
14404             *obufp++ = 'w';
14405           if (intel_syntax && !p[1]
14406               && ((rex & REX_W) || (sizeflag & DFLAG)))
14407             *obufp++ = 'e';
14408           if (!(rex & REX_W))
14409             used_prefixes |= (prefixes & PREFIX_DATA);
14410           break;
14411         case 'V':
14412           if (l == 0 && len == 1)
14413             {
14414               if (intel_syntax)
14415                 break;
14416               if (address_mode == mode_64bit
14417                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14418                 {
14419                   if (sizeflag & SUFFIX_ALWAYS)
14420                     *obufp++ = 'q';
14421                   break;
14422                 }
14423             }
14424           else
14425             {
14426               if (l != 1
14427                   || len != 2
14428                   || last[0] != 'L')
14429                 {
14430                   SAVE_LAST (*p);
14431                   break;
14432                 }
14433
14434               if (rex & REX_W)
14435                 {
14436                   *obufp++ = 'a';
14437                   *obufp++ = 'b';
14438                   *obufp++ = 's';
14439                 }
14440             }
14441           /* Fall through.  */
14442           goto case_S;
14443         case 'S':
14444           if (l == 0 && len == 1)
14445             {
14446 case_S:
14447               if (intel_syntax)
14448                 break;
14449               if (sizeflag & SUFFIX_ALWAYS)
14450                 {
14451                   if (rex & REX_W)
14452                     *obufp++ = 'q';
14453                   else
14454                     {
14455                       if (sizeflag & DFLAG)
14456                         *obufp++ = 'l';
14457                       else
14458                         *obufp++ = 'w';
14459                       used_prefixes |= (prefixes & PREFIX_DATA);
14460                     }
14461                 }
14462             }
14463           else
14464             {
14465               if (l != 1
14466                   || len != 2
14467                   || last[0] != 'L')
14468                 {
14469                   SAVE_LAST (*p);
14470                   break;
14471                 }
14472
14473               if (address_mode == mode_64bit
14474                   && !(prefixes & PREFIX_ADDR))
14475                 {
14476                   *obufp++ = 'a';
14477                   *obufp++ = 'b';
14478                   *obufp++ = 's';
14479                 }
14480
14481               goto case_S;
14482             }
14483           break;
14484         case 'X':
14485           if (l != 0 || len != 1)
14486             {
14487               SAVE_LAST (*p);
14488               break;
14489             }
14490           if (need_vex && vex.prefix)
14491             {
14492               if (vex.prefix == DATA_PREFIX_OPCODE)
14493                 *obufp++ = 'd';
14494               else
14495                 *obufp++ = 's';
14496             }
14497           else
14498             {
14499               if (prefixes & PREFIX_DATA)
14500                 *obufp++ = 'd';
14501               else
14502                 *obufp++ = 's';
14503               used_prefixes |= (prefixes & PREFIX_DATA);
14504             }
14505           break;
14506         case 'Y':
14507           if (l == 0 && len == 1)
14508             {
14509               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14510                 break;
14511               if (rex & REX_W)
14512                 {
14513                   USED_REX (REX_W);
14514                   *obufp++ = 'q';
14515                 }
14516               break;
14517             }
14518           else
14519             {
14520               if (l != 1 || len != 2 || last[0] != 'X')
14521                 {
14522                   SAVE_LAST (*p);
14523                   break;
14524                 }
14525               if (!need_vex)
14526                 abort ();
14527               if (intel_syntax
14528                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14529                 break;
14530               switch (vex.length)
14531                 {
14532                 case 128:
14533                   *obufp++ = 'x';
14534                   break;
14535                 case 256:
14536                   *obufp++ = 'y';
14537                   break;
14538                 case 512:
14539                   if (!vex.evex)
14540                 default:
14541                     abort ();
14542                 }
14543             }
14544           break;
14545         case 'W':
14546           if (l == 0 && len == 1)
14547             {
14548               /* operand size flag for cwtl, cbtw */
14549               USED_REX (REX_W);
14550               if (rex & REX_W)
14551                 {
14552                   if (intel_syntax)
14553                     *obufp++ = 'd';
14554                   else
14555                     *obufp++ = 'l';
14556                 }
14557               else if (sizeflag & DFLAG)
14558                 *obufp++ = 'w';
14559               else
14560                 *obufp++ = 'b';
14561               if (!(rex & REX_W))
14562                 used_prefixes |= (prefixes & PREFIX_DATA);
14563             }
14564           else
14565             {
14566               if (l != 1
14567                   || len != 2
14568                   || (last[0] != 'X'
14569                       && last[0] != 'L'))
14570                 {
14571                   SAVE_LAST (*p);
14572                   break;
14573                 }
14574               if (!need_vex)
14575                 abort ();
14576               if (last[0] == 'X')
14577                 *obufp++ = vex.w ? 'd': 's';
14578               else
14579                 *obufp++ = vex.w ? 'q': 'd';
14580             }
14581           break;
14582         case '^':
14583           if (intel_syntax)
14584             break;
14585           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14586             {
14587               if (sizeflag & DFLAG)
14588                 *obufp++ = 'l';
14589               else
14590                 *obufp++ = 'w';
14591               used_prefixes |= (prefixes & PREFIX_DATA);
14592             }
14593           break;
14594         case '@':
14595           if (intel_syntax)
14596             break;
14597           if (address_mode == mode_64bit
14598               && (isa64 == intel64
14599                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14600               *obufp++ = 'q';
14601           else if ((prefixes & PREFIX_DATA))
14602             {
14603               if (!(sizeflag & DFLAG))
14604                 *obufp++ = 'w';
14605               used_prefixes |= (prefixes & PREFIX_DATA);
14606             }
14607           break;
14608         }
14609       alt = 0;
14610     }
14611   *obufp = 0;
14612   mnemonicendp = obufp;
14613   return 0;
14614 }
14615
14616 static void
14617 oappend (const char *s)
14618 {
14619   obufp = stpcpy (obufp, s);
14620 }
14621
14622 static void
14623 append_seg (void)
14624 {
14625   /* Only print the active segment register.  */
14626   if (!active_seg_prefix)
14627     return;
14628
14629   used_prefixes |= active_seg_prefix;
14630   switch (active_seg_prefix)
14631     {
14632     case PREFIX_CS:
14633       oappend_maybe_intel ("%cs:");
14634       break;
14635     case PREFIX_DS:
14636       oappend_maybe_intel ("%ds:");
14637       break;
14638     case PREFIX_SS:
14639       oappend_maybe_intel ("%ss:");
14640       break;
14641     case PREFIX_ES:
14642       oappend_maybe_intel ("%es:");
14643       break;
14644     case PREFIX_FS:
14645       oappend_maybe_intel ("%fs:");
14646       break;
14647     case PREFIX_GS:
14648       oappend_maybe_intel ("%gs:");
14649       break;
14650     default:
14651       break;
14652     }
14653 }
14654
14655 static void
14656 OP_indirE (int bytemode, int sizeflag)
14657 {
14658   if (!intel_syntax)
14659     oappend ("*");
14660   OP_E (bytemode, sizeflag);
14661 }
14662
14663 static void
14664 print_operand_value (char *buf, int hex, bfd_vma disp)
14665 {
14666   if (address_mode == mode_64bit)
14667     {
14668       if (hex)
14669         {
14670           char tmp[30];
14671           int i;
14672           buf[0] = '0';
14673           buf[1] = 'x';
14674           sprintf_vma (tmp, disp);
14675           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14676           strcpy (buf + 2, tmp + i);
14677         }
14678       else
14679         {
14680           bfd_signed_vma v = disp;
14681           char tmp[30];
14682           int i;
14683           if (v < 0)
14684             {
14685               *(buf++) = '-';
14686               v = -disp;
14687               /* Check for possible overflow on 0x8000000000000000.  */
14688               if (v < 0)
14689                 {
14690                   strcpy (buf, "9223372036854775808");
14691                   return;
14692                 }
14693             }
14694           if (!v)
14695             {
14696               strcpy (buf, "0");
14697               return;
14698             }
14699
14700           i = 0;
14701           tmp[29] = 0;
14702           while (v)
14703             {
14704               tmp[28 - i] = (v % 10) + '0';
14705               v /= 10;
14706               i++;
14707             }
14708           strcpy (buf, tmp + 29 - i);
14709         }
14710     }
14711   else
14712     {
14713       if (hex)
14714         sprintf (buf, "0x%x", (unsigned int) disp);
14715       else
14716         sprintf (buf, "%d", (int) disp);
14717     }
14718 }
14719
14720 /* Put DISP in BUF as signed hex number.  */
14721
14722 static void
14723 print_displacement (char *buf, bfd_vma disp)
14724 {
14725   bfd_signed_vma val = disp;
14726   char tmp[30];
14727   int i, j = 0;
14728
14729   if (val < 0)
14730     {
14731       buf[j++] = '-';
14732       val = -disp;
14733
14734       /* Check for possible overflow.  */
14735       if (val < 0)
14736         {
14737           switch (address_mode)
14738             {
14739             case mode_64bit:
14740               strcpy (buf + j, "0x8000000000000000");
14741               break;
14742             case mode_32bit:
14743               strcpy (buf + j, "0x80000000");
14744               break;
14745             case mode_16bit:
14746               strcpy (buf + j, "0x8000");
14747               break;
14748             }
14749           return;
14750         }
14751     }
14752
14753   buf[j++] = '0';
14754   buf[j++] = 'x';
14755
14756   sprintf_vma (tmp, (bfd_vma) val);
14757   for (i = 0; tmp[i] == '0'; i++)
14758     continue;
14759   if (tmp[i] == '\0')
14760     i--;
14761   strcpy (buf + j, tmp + i);
14762 }
14763
14764 static void
14765 intel_operand_size (int bytemode, int sizeflag)
14766 {
14767   if (vex.evex
14768       && vex.b
14769       && (bytemode == x_mode
14770           || bytemode == evex_half_bcst_xmmq_mode))
14771     {
14772       if (vex.w)
14773         oappend ("QWORD PTR ");
14774       else
14775         oappend ("DWORD PTR ");
14776       return;
14777     }
14778   switch (bytemode)
14779     {
14780     case b_mode:
14781     case b_swap_mode:
14782     case dqb_mode:
14783     case db_mode:
14784       oappend ("BYTE PTR ");
14785       break;
14786     case w_mode:
14787     case dw_mode:
14788     case dqw_mode:
14789     case dqw_swap_mode:
14790       oappend ("WORD PTR ");
14791       break;
14792     case stack_v_mode:
14793       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14794         {
14795           oappend ("QWORD PTR ");
14796           break;
14797         }
14798       /* FALLTHRU */
14799     case v_mode:
14800     case v_swap_mode:
14801     case dq_mode:
14802       USED_REX (REX_W);
14803       if (rex & REX_W)
14804         oappend ("QWORD PTR ");
14805       else
14806         {
14807           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14808             oappend ("DWORD PTR ");
14809           else
14810             oappend ("WORD PTR ");
14811           used_prefixes |= (prefixes & PREFIX_DATA);
14812         }
14813       break;
14814     case z_mode:
14815       if ((rex & REX_W) || (sizeflag & DFLAG))
14816         *obufp++ = 'D';
14817       oappend ("WORD PTR ");
14818       if (!(rex & REX_W))
14819         used_prefixes |= (prefixes & PREFIX_DATA);
14820       break;
14821     case a_mode:
14822       if (sizeflag & DFLAG)
14823         oappend ("QWORD PTR ");
14824       else
14825         oappend ("DWORD PTR ");
14826       used_prefixes |= (prefixes & PREFIX_DATA);
14827       break;
14828     case d_mode:
14829     case d_scalar_mode:
14830     case d_scalar_swap_mode:
14831     case d_swap_mode:
14832     case dqd_mode:
14833       oappend ("DWORD PTR ");
14834       break;
14835     case q_mode:
14836     case q_scalar_mode:
14837     case q_scalar_swap_mode:
14838     case q_swap_mode:
14839       oappend ("QWORD PTR ");
14840       break;
14841     case m_mode:
14842       if (address_mode == mode_64bit)
14843         oappend ("QWORD PTR ");
14844       else
14845         oappend ("DWORD PTR ");
14846       break;
14847     case f_mode:
14848       if (sizeflag & DFLAG)
14849         oappend ("FWORD PTR ");
14850       else
14851         oappend ("DWORD PTR ");
14852       used_prefixes |= (prefixes & PREFIX_DATA);
14853       break;
14854     case t_mode:
14855       oappend ("TBYTE PTR ");
14856       break;
14857     case x_mode:
14858     case x_swap_mode:
14859     case evex_x_gscat_mode:
14860     case evex_x_nobcst_mode:
14861       if (need_vex)
14862         {
14863           switch (vex.length)
14864             {
14865             case 128:
14866               oappend ("XMMWORD PTR ");
14867               break;
14868             case 256:
14869               oappend ("YMMWORD PTR ");
14870               break;
14871             case 512:
14872               oappend ("ZMMWORD PTR ");
14873               break;
14874             default:
14875               abort ();
14876             }
14877         }
14878       else
14879         oappend ("XMMWORD PTR ");
14880       break;
14881     case xmm_mode:
14882       oappend ("XMMWORD PTR ");
14883       break;
14884     case ymm_mode:
14885       oappend ("YMMWORD PTR ");
14886       break;
14887     case xmmq_mode:
14888     case evex_half_bcst_xmmq_mode:
14889       if (!need_vex)
14890         abort ();
14891
14892       switch (vex.length)
14893         {
14894         case 128:
14895           oappend ("QWORD PTR ");
14896           break;
14897         case 256:
14898           oappend ("XMMWORD PTR ");
14899           break;
14900         case 512:
14901           oappend ("YMMWORD PTR ");
14902           break;
14903         default:
14904           abort ();
14905         }
14906       break;
14907     case xmm_mb_mode:
14908       if (!need_vex)
14909         abort ();
14910
14911       switch (vex.length)
14912         {
14913         case 128:
14914         case 256:
14915         case 512:
14916           oappend ("BYTE PTR ");
14917           break;
14918         default:
14919           abort ();
14920         }
14921       break;
14922     case xmm_mw_mode:
14923       if (!need_vex)
14924         abort ();
14925
14926       switch (vex.length)
14927         {
14928         case 128:
14929         case 256:
14930         case 512:
14931           oappend ("WORD PTR ");
14932           break;
14933         default:
14934           abort ();
14935         }
14936       break;
14937     case xmm_md_mode:
14938       if (!need_vex)
14939         abort ();
14940
14941       switch (vex.length)
14942         {
14943         case 128:
14944         case 256:
14945         case 512:
14946           oappend ("DWORD PTR ");
14947           break;
14948         default:
14949           abort ();
14950         }
14951       break;
14952     case xmm_mq_mode:
14953       if (!need_vex)
14954         abort ();
14955
14956       switch (vex.length)
14957         {
14958         case 128:
14959         case 256:
14960         case 512:
14961           oappend ("QWORD PTR ");
14962           break;
14963         default:
14964           abort ();
14965         }
14966       break;
14967     case xmmdw_mode:
14968       if (!need_vex)
14969         abort ();
14970
14971       switch (vex.length)
14972         {
14973         case 128:
14974           oappend ("WORD PTR ");
14975           break;
14976         case 256:
14977           oappend ("DWORD PTR ");
14978           break;
14979         case 512:
14980           oappend ("QWORD PTR ");
14981           break;
14982         default:
14983           abort ();
14984         }
14985       break;
14986     case xmmqd_mode:
14987       if (!need_vex)
14988         abort ();
14989
14990       switch (vex.length)
14991         {
14992         case 128:
14993           oappend ("DWORD PTR ");
14994           break;
14995         case 256:
14996           oappend ("QWORD PTR ");
14997           break;
14998         case 512:
14999           oappend ("XMMWORD PTR ");
15000           break;
15001         default:
15002           abort ();
15003         }
15004       break;
15005     case ymmq_mode:
15006       if (!need_vex)
15007         abort ();
15008
15009       switch (vex.length)
15010         {
15011         case 128:
15012           oappend ("QWORD PTR ");
15013           break;
15014         case 256:
15015           oappend ("YMMWORD PTR ");
15016           break;
15017         case 512:
15018           oappend ("ZMMWORD PTR ");
15019           break;
15020         default:
15021           abort ();
15022         }
15023       break;
15024     case ymmxmm_mode:
15025       if (!need_vex)
15026         abort ();
15027
15028       switch (vex.length)
15029         {
15030         case 128:
15031         case 256:
15032           oappend ("XMMWORD PTR ");
15033           break;
15034         default:
15035           abort ();
15036         }
15037       break;
15038     case o_mode:
15039       oappend ("OWORD PTR ");
15040       break;
15041     case xmm_mdq_mode:
15042     case vex_w_dq_mode:
15043     case vex_scalar_w_dq_mode:
15044       if (!need_vex)
15045         abort ();
15046
15047       if (vex.w)
15048         oappend ("QWORD PTR ");
15049       else
15050         oappend ("DWORD PTR ");
15051       break;
15052     case vex_vsib_d_w_dq_mode:
15053     case vex_vsib_q_w_dq_mode:
15054       if (!need_vex)
15055         abort ();
15056
15057       if (!vex.evex)
15058         {
15059           if (vex.w)
15060             oappend ("QWORD PTR ");
15061           else
15062             oappend ("DWORD PTR ");
15063         }
15064       else
15065         {
15066           switch (vex.length)
15067             {
15068             case 128:
15069               oappend ("XMMWORD PTR ");
15070               break;
15071             case 256:
15072               oappend ("YMMWORD PTR ");
15073               break;
15074             case 512:
15075               oappend ("ZMMWORD PTR ");
15076               break;
15077             default:
15078               abort ();
15079             }
15080         }
15081       break;
15082     case vex_vsib_q_w_d_mode:
15083     case vex_vsib_d_w_d_mode:
15084       if (!need_vex || !vex.evex)
15085         abort ();
15086
15087       switch (vex.length)
15088         {
15089         case 128:
15090           oappend ("QWORD PTR ");
15091           break;
15092         case 256:
15093           oappend ("XMMWORD PTR ");
15094           break;
15095         case 512:
15096           oappend ("YMMWORD PTR ");
15097           break;
15098         default:
15099           abort ();
15100         }
15101
15102       break;
15103     case mask_bd_mode:
15104       if (!need_vex || vex.length != 128)
15105         abort ();
15106       if (vex.w)
15107         oappend ("DWORD PTR ");
15108       else
15109         oappend ("BYTE PTR ");
15110       break;
15111     case mask_mode:
15112       if (!need_vex)
15113         abort ();
15114       if (vex.w)
15115         oappend ("QWORD PTR ");
15116       else
15117         oappend ("WORD PTR ");
15118       break;
15119     case v_bnd_mode:
15120     default:
15121       break;
15122     }
15123 }
15124
15125 static void
15126 OP_E_register (int bytemode, int sizeflag)
15127 {
15128   int reg = modrm.rm;
15129   const char **names;
15130
15131   USED_REX (REX_B);
15132   if ((rex & REX_B))
15133     reg += 8;
15134
15135   if ((sizeflag & SUFFIX_ALWAYS)
15136       && (bytemode == b_swap_mode
15137           || bytemode == v_swap_mode
15138           || bytemode == dqw_swap_mode))
15139     swap_operand ();
15140
15141   switch (bytemode)
15142     {
15143     case b_mode:
15144     case b_swap_mode:
15145       USED_REX (0);
15146       if (rex)
15147         names = names8rex;
15148       else
15149         names = names8;
15150       break;
15151     case w_mode:
15152       names = names16;
15153       break;
15154     case d_mode:
15155     case dw_mode:
15156     case db_mode:
15157       names = names32;
15158       break;
15159     case q_mode:
15160       names = names64;
15161       break;
15162     case m_mode:
15163     case v_bnd_mode:
15164       names = address_mode == mode_64bit ? names64 : names32;
15165       break;
15166     case bnd_mode:
15167       names = names_bnd;
15168       break;
15169     case stack_v_mode:
15170       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15171         {
15172           names = names64;
15173           break;
15174         }
15175       bytemode = v_mode;
15176       /* FALLTHRU */
15177     case v_mode:
15178     case v_swap_mode:
15179     case dq_mode:
15180     case dqb_mode:
15181     case dqd_mode:
15182     case dqw_mode:
15183     case dqw_swap_mode:
15184       USED_REX (REX_W);
15185       if (rex & REX_W)
15186         names = names64;
15187       else
15188         {
15189           if ((sizeflag & DFLAG)
15190               || (bytemode != v_mode
15191                   && bytemode != v_swap_mode))
15192             names = names32;
15193           else
15194             names = names16;
15195           used_prefixes |= (prefixes & PREFIX_DATA);
15196         }
15197       break;
15198     case mask_bd_mode:
15199     case mask_mode:
15200       names = names_mask;
15201       break;
15202     case 0:
15203       return;
15204     default:
15205       oappend (INTERNAL_DISASSEMBLER_ERROR);
15206       return;
15207     }
15208   oappend (names[reg]);
15209 }
15210
15211 static void
15212 OP_E_memory (int bytemode, int sizeflag)
15213 {
15214   bfd_vma disp = 0;
15215   int add = (rex & REX_B) ? 8 : 0;
15216   int riprel = 0;
15217   int shift;
15218
15219   if (vex.evex)
15220     {
15221       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15222       if (vex.b
15223           && bytemode != x_mode
15224           && bytemode != xmmq_mode
15225           && bytemode != evex_half_bcst_xmmq_mode)
15226         {
15227           BadOp ();
15228           return;
15229         }
15230       switch (bytemode)
15231         {
15232         case dqw_mode:
15233         case dw_mode:
15234         case dqw_swap_mode:
15235           shift = 1;
15236           break;
15237         case dqb_mode:
15238         case db_mode:
15239           shift = 0;
15240           break;
15241         case vex_vsib_d_w_dq_mode:
15242         case vex_vsib_d_w_d_mode:
15243         case vex_vsib_q_w_dq_mode:
15244         case vex_vsib_q_w_d_mode:
15245         case evex_x_gscat_mode:
15246         case xmm_mdq_mode:
15247           shift = vex.w ? 3 : 2;
15248           break;
15249         case x_mode:
15250         case evex_half_bcst_xmmq_mode:
15251         case xmmq_mode:
15252           if (vex.b)
15253             {
15254               shift = vex.w ? 3 : 2;
15255               break;
15256             }
15257           /* Fall through if vex.b == 0.  */
15258         case xmmqd_mode:
15259         case xmmdw_mode:
15260         case ymmq_mode:
15261         case evex_x_nobcst_mode:
15262         case x_swap_mode:
15263           switch (vex.length)
15264             {
15265             case 128:
15266               shift = 4;
15267               break;
15268             case 256:
15269               shift = 5;
15270               break;
15271             case 512:
15272               shift = 6;
15273               break;
15274             default:
15275               abort ();
15276             }
15277           break;
15278         case ymm_mode:
15279           shift = 5;
15280           break;
15281         case xmm_mode:
15282           shift = 4;
15283           break;
15284         case xmm_mq_mode:
15285         case q_mode:
15286         case q_scalar_mode:
15287         case q_swap_mode:
15288         case q_scalar_swap_mode:
15289           shift = 3;
15290           break;
15291         case dqd_mode:
15292         case xmm_md_mode:
15293         case d_mode:
15294         case d_scalar_mode:
15295         case d_swap_mode:
15296         case d_scalar_swap_mode:
15297           shift = 2;
15298           break;
15299         case xmm_mw_mode:
15300           shift = 1;
15301           break;
15302         case xmm_mb_mode:
15303           shift = 0;
15304           break;
15305         default:
15306           abort ();
15307         }
15308       /* Make necessary corrections to shift for modes that need it.
15309          For these modes we currently have shift 4, 5 or 6 depending on
15310          vex.length (it corresponds to xmmword, ymmword or zmmword
15311          operand).  We might want to make it 3, 4 or 5 (e.g. for
15312          xmmq_mode).  In case of broadcast enabled the corrections
15313          aren't needed, as element size is always 32 or 64 bits.  */
15314       if (!vex.b
15315           && (bytemode == xmmq_mode
15316               || bytemode == evex_half_bcst_xmmq_mode))
15317         shift -= 1;
15318       else if (bytemode == xmmqd_mode)
15319         shift -= 2;
15320       else if (bytemode == xmmdw_mode)
15321         shift -= 3;
15322       else if (bytemode == ymmq_mode && vex.length == 128)
15323         shift -= 1;
15324     }
15325   else
15326     shift = 0;
15327
15328   USED_REX (REX_B);
15329   if (intel_syntax)
15330     intel_operand_size (bytemode, sizeflag);
15331   append_seg ();
15332
15333   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15334     {
15335       /* 32/64 bit address mode */
15336       int havedisp;
15337       int havesib;
15338       int havebase;
15339       int haveindex;
15340       int needindex;
15341       int base, rbase;
15342       int vindex = 0;
15343       int scale = 0;
15344       int addr32flag = !((sizeflag & AFLAG)
15345                          || bytemode == v_bnd_mode
15346                          || bytemode == bnd_mode);
15347       const char **indexes64 = names64;
15348       const char **indexes32 = names32;
15349
15350       havesib = 0;
15351       havebase = 1;
15352       haveindex = 0;
15353       base = modrm.rm;
15354
15355       if (base == 4)
15356         {
15357           havesib = 1;
15358           vindex = sib.index;
15359           USED_REX (REX_X);
15360           if (rex & REX_X)
15361             vindex += 8;
15362           switch (bytemode)
15363             {
15364             case vex_vsib_d_w_dq_mode:
15365             case vex_vsib_d_w_d_mode:
15366             case vex_vsib_q_w_dq_mode:
15367             case vex_vsib_q_w_d_mode:
15368               if (!need_vex)
15369                 abort ();
15370               if (vex.evex)
15371                 {
15372                   if (!vex.v)
15373                     vindex += 16;
15374                 }
15375
15376               haveindex = 1;
15377               switch (vex.length)
15378                 {
15379                 case 128:
15380                   indexes64 = indexes32 = names_xmm;
15381                   break;
15382                 case 256:
15383                   if (!vex.w
15384                       || bytemode == vex_vsib_q_w_dq_mode
15385                       || bytemode == vex_vsib_q_w_d_mode)
15386                     indexes64 = indexes32 = names_ymm;
15387                   else
15388                     indexes64 = indexes32 = names_xmm;
15389                   break;
15390                 case 512:
15391                   if (!vex.w
15392                       || bytemode == vex_vsib_q_w_dq_mode
15393                       || bytemode == vex_vsib_q_w_d_mode)
15394                     indexes64 = indexes32 = names_zmm;
15395                   else
15396                     indexes64 = indexes32 = names_ymm;
15397                   break;
15398                 default:
15399                   abort ();
15400                 }
15401               break;
15402             default:
15403               haveindex = vindex != 4;
15404               break;
15405             }
15406           scale = sib.scale;
15407           base = sib.base;
15408           codep++;
15409         }
15410       rbase = base + add;
15411
15412       switch (modrm.mod)
15413         {
15414         case 0:
15415           if (base == 5)
15416             {
15417               havebase = 0;
15418               if (address_mode == mode_64bit && !havesib)
15419                 riprel = 1;
15420               disp = get32s ();
15421             }
15422           break;
15423         case 1:
15424           FETCH_DATA (the_info, codep + 1);
15425           disp = *codep++;
15426           if ((disp & 0x80) != 0)
15427             disp -= 0x100;
15428           if (vex.evex && shift > 0)
15429             disp <<= shift;
15430           break;
15431         case 2:
15432           disp = get32s ();
15433           break;
15434         }
15435
15436       /* In 32bit mode, we need index register to tell [offset] from
15437          [eiz*1 + offset].  */
15438       needindex = (havesib
15439                    && !havebase
15440                    && !haveindex
15441                    && address_mode == mode_32bit);
15442       havedisp = (havebase
15443                   || needindex
15444                   || (havesib && (haveindex || scale != 0)));
15445
15446       if (!intel_syntax)
15447         if (modrm.mod != 0 || base == 5)
15448           {
15449             if (havedisp || riprel)
15450               print_displacement (scratchbuf, disp);
15451             else
15452               print_operand_value (scratchbuf, 1, disp);
15453             oappend (scratchbuf);
15454             if (riprel)
15455               {
15456                 set_op (disp, 1);
15457                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15458               }
15459           }
15460
15461       if ((havebase || haveindex || riprel)
15462           && (bytemode != v_bnd_mode)
15463           && (bytemode != bnd_mode))
15464         used_prefixes |= PREFIX_ADDR;
15465
15466       if (havedisp || (intel_syntax && riprel))
15467         {
15468           *obufp++ = open_char;
15469           if (intel_syntax && riprel)
15470             {
15471               set_op (disp, 1);
15472               oappend (sizeflag & AFLAG ? "rip" : "eip");
15473             }
15474           *obufp = '\0';
15475           if (havebase)
15476             oappend (address_mode == mode_64bit && !addr32flag
15477                      ? names64[rbase] : names32[rbase]);
15478           if (havesib)
15479             {
15480               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15481                  print index to tell base + index from base.  */
15482               if (scale != 0
15483                   || needindex
15484                   || haveindex
15485                   || (havebase && base != ESP_REG_NUM))
15486                 {
15487                   if (!intel_syntax || havebase)
15488                     {
15489                       *obufp++ = separator_char;
15490                       *obufp = '\0';
15491                     }
15492                   if (haveindex)
15493                     oappend (address_mode == mode_64bit && !addr32flag
15494                              ? indexes64[vindex] : indexes32[vindex]);
15495                   else
15496                     oappend (address_mode == mode_64bit && !addr32flag
15497                              ? index64 : index32);
15498
15499                   *obufp++ = scale_char;
15500                   *obufp = '\0';
15501                   sprintf (scratchbuf, "%d", 1 << scale);
15502                   oappend (scratchbuf);
15503                 }
15504             }
15505           if (intel_syntax
15506               && (disp || modrm.mod != 0 || base == 5))
15507             {
15508               if (!havedisp || (bfd_signed_vma) disp >= 0)
15509                 {
15510                   *obufp++ = '+';
15511                   *obufp = '\0';
15512                 }
15513               else if (modrm.mod != 1 && disp != -disp)
15514                 {
15515                   *obufp++ = '-';
15516                   *obufp = '\0';
15517                   disp = - (bfd_signed_vma) disp;
15518                 }
15519
15520               if (havedisp)
15521                 print_displacement (scratchbuf, disp);
15522               else
15523                 print_operand_value (scratchbuf, 1, disp);
15524               oappend (scratchbuf);
15525             }
15526
15527           *obufp++ = close_char;
15528           *obufp = '\0';
15529         }
15530       else if (intel_syntax)
15531         {
15532           if (modrm.mod != 0 || base == 5)
15533             {
15534               if (!active_seg_prefix)
15535                 {
15536                   oappend (names_seg[ds_reg - es_reg]);
15537                   oappend (":");
15538                 }
15539               print_operand_value (scratchbuf, 1, disp);
15540               oappend (scratchbuf);
15541             }
15542         }
15543     }
15544   else
15545     {
15546       /* 16 bit address mode */
15547       used_prefixes |= prefixes & PREFIX_ADDR;
15548       switch (modrm.mod)
15549         {
15550         case 0:
15551           if (modrm.rm == 6)
15552             {
15553               disp = get16 ();
15554               if ((disp & 0x8000) != 0)
15555                 disp -= 0x10000;
15556             }
15557           break;
15558         case 1:
15559           FETCH_DATA (the_info, codep + 1);
15560           disp = *codep++;
15561           if ((disp & 0x80) != 0)
15562             disp -= 0x100;
15563           break;
15564         case 2:
15565           disp = get16 ();
15566           if ((disp & 0x8000) != 0)
15567             disp -= 0x10000;
15568           break;
15569         }
15570
15571       if (!intel_syntax)
15572         if (modrm.mod != 0 || modrm.rm == 6)
15573           {
15574             print_displacement (scratchbuf, disp);
15575             oappend (scratchbuf);
15576           }
15577
15578       if (modrm.mod != 0 || modrm.rm != 6)
15579         {
15580           *obufp++ = open_char;
15581           *obufp = '\0';
15582           oappend (index16[modrm.rm]);
15583           if (intel_syntax
15584               && (disp || modrm.mod != 0 || modrm.rm == 6))
15585             {
15586               if ((bfd_signed_vma) disp >= 0)
15587                 {
15588                   *obufp++ = '+';
15589                   *obufp = '\0';
15590                 }
15591               else if (modrm.mod != 1)
15592                 {
15593                   *obufp++ = '-';
15594                   *obufp = '\0';
15595                   disp = - (bfd_signed_vma) disp;
15596                 }
15597
15598               print_displacement (scratchbuf, disp);
15599               oappend (scratchbuf);
15600             }
15601
15602           *obufp++ = close_char;
15603           *obufp = '\0';
15604         }
15605       else if (intel_syntax)
15606         {
15607           if (!active_seg_prefix)
15608             {
15609               oappend (names_seg[ds_reg - es_reg]);
15610               oappend (":");
15611             }
15612           print_operand_value (scratchbuf, 1, disp & 0xffff);
15613           oappend (scratchbuf);
15614         }
15615     }
15616   if (vex.evex && vex.b
15617       && (bytemode == x_mode
15618           || bytemode == xmmq_mode
15619           || bytemode == evex_half_bcst_xmmq_mode))
15620     {
15621       if (vex.w
15622           || bytemode == xmmq_mode
15623           || bytemode == evex_half_bcst_xmmq_mode)
15624         {
15625           switch (vex.length)
15626             {
15627             case 128:
15628               oappend ("{1to2}");
15629               break;
15630             case 256:
15631               oappend ("{1to4}");
15632               break;
15633             case 512:
15634               oappend ("{1to8}");
15635               break;
15636             default:
15637               abort ();
15638             }
15639         }
15640       else
15641         {
15642           switch (vex.length)
15643             {
15644             case 128:
15645               oappend ("{1to4}");
15646               break;
15647             case 256:
15648               oappend ("{1to8}");
15649               break;
15650             case 512:
15651               oappend ("{1to16}");
15652               break;
15653             default:
15654               abort ();
15655             }
15656         }
15657     }
15658 }
15659
15660 static void
15661 OP_E (int bytemode, int sizeflag)
15662 {
15663   /* Skip mod/rm byte.  */
15664   MODRM_CHECK;
15665   codep++;
15666
15667   if (modrm.mod == 3)
15668     OP_E_register (bytemode, sizeflag);
15669   else
15670     OP_E_memory (bytemode, sizeflag);
15671 }
15672
15673 static void
15674 OP_G (int bytemode, int sizeflag)
15675 {
15676   int add = 0;
15677   USED_REX (REX_R);
15678   if (rex & REX_R)
15679     add += 8;
15680   switch (bytemode)
15681     {
15682     case b_mode:
15683       USED_REX (0);
15684       if (rex)
15685         oappend (names8rex[modrm.reg + add]);
15686       else
15687         oappend (names8[modrm.reg + add]);
15688       break;
15689     case w_mode:
15690       oappend (names16[modrm.reg + add]);
15691       break;
15692     case d_mode:
15693     case db_mode:
15694     case dw_mode:
15695       oappend (names32[modrm.reg + add]);
15696       break;
15697     case q_mode:
15698       oappend (names64[modrm.reg + add]);
15699       break;
15700     case bnd_mode:
15701       oappend (names_bnd[modrm.reg]);
15702       break;
15703     case v_mode:
15704     case dq_mode:
15705     case dqb_mode:
15706     case dqd_mode:
15707     case dqw_mode:
15708     case dqw_swap_mode:
15709       USED_REX (REX_W);
15710       if (rex & REX_W)
15711         oappend (names64[modrm.reg + add]);
15712       else
15713         {
15714           if ((sizeflag & DFLAG) || bytemode != v_mode)
15715             oappend (names32[modrm.reg + add]);
15716           else
15717             oappend (names16[modrm.reg + add]);
15718           used_prefixes |= (prefixes & PREFIX_DATA);
15719         }
15720       break;
15721     case m_mode:
15722       if (address_mode == mode_64bit)
15723         oappend (names64[modrm.reg + add]);
15724       else
15725         oappend (names32[modrm.reg + add]);
15726       break;
15727     case mask_bd_mode:
15728     case mask_mode:
15729       oappend (names_mask[modrm.reg + add]);
15730       break;
15731     default:
15732       oappend (INTERNAL_DISASSEMBLER_ERROR);
15733       break;
15734     }
15735 }
15736
15737 static bfd_vma
15738 get64 (void)
15739 {
15740   bfd_vma x;
15741 #ifdef BFD64
15742   unsigned int a;
15743   unsigned int b;
15744
15745   FETCH_DATA (the_info, codep + 8);
15746   a = *codep++ & 0xff;
15747   a |= (*codep++ & 0xff) << 8;
15748   a |= (*codep++ & 0xff) << 16;
15749   a |= (*codep++ & 0xffu) << 24;
15750   b = *codep++ & 0xff;
15751   b |= (*codep++ & 0xff) << 8;
15752   b |= (*codep++ & 0xff) << 16;
15753   b |= (*codep++ & 0xffu) << 24;
15754   x = a + ((bfd_vma) b << 32);
15755 #else
15756   abort ();
15757   x = 0;
15758 #endif
15759   return x;
15760 }
15761
15762 static bfd_signed_vma
15763 get32 (void)
15764 {
15765   bfd_signed_vma x = 0;
15766
15767   FETCH_DATA (the_info, codep + 4);
15768   x = *codep++ & (bfd_signed_vma) 0xff;
15769   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15770   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15771   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15772   return x;
15773 }
15774
15775 static bfd_signed_vma
15776 get32s (void)
15777 {
15778   bfd_signed_vma x = 0;
15779
15780   FETCH_DATA (the_info, codep + 4);
15781   x = *codep++ & (bfd_signed_vma) 0xff;
15782   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15783   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15784   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15785
15786   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15787
15788   return x;
15789 }
15790
15791 static int
15792 get16 (void)
15793 {
15794   int x = 0;
15795
15796   FETCH_DATA (the_info, codep + 2);
15797   x = *codep++ & 0xff;
15798   x |= (*codep++ & 0xff) << 8;
15799   return x;
15800 }
15801
15802 static void
15803 set_op (bfd_vma op, int riprel)
15804 {
15805   op_index[op_ad] = op_ad;
15806   if (address_mode == mode_64bit)
15807     {
15808       op_address[op_ad] = op;
15809       op_riprel[op_ad] = riprel;
15810     }
15811   else
15812     {
15813       /* Mask to get a 32-bit address.  */
15814       op_address[op_ad] = op & 0xffffffff;
15815       op_riprel[op_ad] = riprel & 0xffffffff;
15816     }
15817 }
15818
15819 static void
15820 OP_REG (int code, int sizeflag)
15821 {
15822   const char *s;
15823   int add;
15824
15825   switch (code)
15826     {
15827     case es_reg: case ss_reg: case cs_reg:
15828     case ds_reg: case fs_reg: case gs_reg:
15829       oappend (names_seg[code - es_reg]);
15830       return;
15831     }
15832
15833   USED_REX (REX_B);
15834   if (rex & REX_B)
15835     add = 8;
15836   else
15837     add = 0;
15838
15839   switch (code)
15840     {
15841     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15842     case sp_reg: case bp_reg: case si_reg: case di_reg:
15843       s = names16[code - ax_reg + add];
15844       break;
15845     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15846     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15847       USED_REX (0);
15848       if (rex)
15849         s = names8rex[code - al_reg + add];
15850       else
15851         s = names8[code - al_reg];
15852       break;
15853     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15854     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15855       if (address_mode == mode_64bit
15856           && ((sizeflag & DFLAG) || (rex & REX_W)))
15857         {
15858           s = names64[code - rAX_reg + add];
15859           break;
15860         }
15861       code += eAX_reg - rAX_reg;
15862       /* Fall through.  */
15863     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15864     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15865       USED_REX (REX_W);
15866       if (rex & REX_W)
15867         s = names64[code - eAX_reg + add];
15868       else
15869         {
15870           if (sizeflag & DFLAG)
15871             s = names32[code - eAX_reg + add];
15872           else
15873             s = names16[code - eAX_reg + add];
15874           used_prefixes |= (prefixes & PREFIX_DATA);
15875         }
15876       break;
15877     default:
15878       s = INTERNAL_DISASSEMBLER_ERROR;
15879       break;
15880     }
15881   oappend (s);
15882 }
15883
15884 static void
15885 OP_IMREG (int code, int sizeflag)
15886 {
15887   const char *s;
15888
15889   switch (code)
15890     {
15891     case indir_dx_reg:
15892       if (intel_syntax)
15893         s = "dx";
15894       else
15895         s = "(%dx)";
15896       break;
15897     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15898     case sp_reg: case bp_reg: case si_reg: case di_reg:
15899       s = names16[code - ax_reg];
15900       break;
15901     case es_reg: case ss_reg: case cs_reg:
15902     case ds_reg: case fs_reg: case gs_reg:
15903       s = names_seg[code - es_reg];
15904       break;
15905     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15906     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15907       USED_REX (0);
15908       if (rex)
15909         s = names8rex[code - al_reg];
15910       else
15911         s = names8[code - al_reg];
15912       break;
15913     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15914     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15915       USED_REX (REX_W);
15916       if (rex & REX_W)
15917         s = names64[code - eAX_reg];
15918       else
15919         {
15920           if (sizeflag & DFLAG)
15921             s = names32[code - eAX_reg];
15922           else
15923             s = names16[code - eAX_reg];
15924           used_prefixes |= (prefixes & PREFIX_DATA);
15925         }
15926       break;
15927     case z_mode_ax_reg:
15928       if ((rex & REX_W) || (sizeflag & DFLAG))
15929         s = *names32;
15930       else
15931         s = *names16;
15932       if (!(rex & REX_W))
15933         used_prefixes |= (prefixes & PREFIX_DATA);
15934       break;
15935     default:
15936       s = INTERNAL_DISASSEMBLER_ERROR;
15937       break;
15938     }
15939   oappend (s);
15940 }
15941
15942 static void
15943 OP_I (int bytemode, int sizeflag)
15944 {
15945   bfd_signed_vma op;
15946   bfd_signed_vma mask = -1;
15947
15948   switch (bytemode)
15949     {
15950     case b_mode:
15951       FETCH_DATA (the_info, codep + 1);
15952       op = *codep++;
15953       mask = 0xff;
15954       break;
15955     case q_mode:
15956       if (address_mode == mode_64bit)
15957         {
15958           op = get32s ();
15959           break;
15960         }
15961       /* Fall through.  */
15962     case v_mode:
15963       USED_REX (REX_W);
15964       if (rex & REX_W)
15965         op = get32s ();
15966       else
15967         {
15968           if (sizeflag & DFLAG)
15969             {
15970               op = get32 ();
15971               mask = 0xffffffff;
15972             }
15973           else
15974             {
15975               op = get16 ();
15976               mask = 0xfffff;
15977             }
15978           used_prefixes |= (prefixes & PREFIX_DATA);
15979         }
15980       break;
15981     case w_mode:
15982       mask = 0xfffff;
15983       op = get16 ();
15984       break;
15985     case const_1_mode:
15986       if (intel_syntax)
15987         oappend ("1");
15988       return;
15989     default:
15990       oappend (INTERNAL_DISASSEMBLER_ERROR);
15991       return;
15992     }
15993
15994   op &= mask;
15995   scratchbuf[0] = '$';
15996   print_operand_value (scratchbuf + 1, 1, op);
15997   oappend_maybe_intel (scratchbuf);
15998   scratchbuf[0] = '\0';
15999 }
16000
16001 static void
16002 OP_I64 (int bytemode, int sizeflag)
16003 {
16004   bfd_signed_vma op;
16005   bfd_signed_vma mask = -1;
16006
16007   if (address_mode != mode_64bit)
16008     {
16009       OP_I (bytemode, sizeflag);
16010       return;
16011     }
16012
16013   switch (bytemode)
16014     {
16015     case b_mode:
16016       FETCH_DATA (the_info, codep + 1);
16017       op = *codep++;
16018       mask = 0xff;
16019       break;
16020     case v_mode:
16021       USED_REX (REX_W);
16022       if (rex & REX_W)
16023         op = get64 ();
16024       else
16025         {
16026           if (sizeflag & DFLAG)
16027             {
16028               op = get32 ();
16029               mask = 0xffffffff;
16030             }
16031           else
16032             {
16033               op = get16 ();
16034               mask = 0xfffff;
16035             }
16036           used_prefixes |= (prefixes & PREFIX_DATA);
16037         }
16038       break;
16039     case w_mode:
16040       mask = 0xfffff;
16041       op = get16 ();
16042       break;
16043     default:
16044       oappend (INTERNAL_DISASSEMBLER_ERROR);
16045       return;
16046     }
16047
16048   op &= mask;
16049   scratchbuf[0] = '$';
16050   print_operand_value (scratchbuf + 1, 1, op);
16051   oappend_maybe_intel (scratchbuf);
16052   scratchbuf[0] = '\0';
16053 }
16054
16055 static void
16056 OP_sI (int bytemode, int sizeflag)
16057 {
16058   bfd_signed_vma op;
16059
16060   switch (bytemode)
16061     {
16062     case b_mode:
16063     case b_T_mode:
16064       FETCH_DATA (the_info, codep + 1);
16065       op = *codep++;
16066       if ((op & 0x80) != 0)
16067         op -= 0x100;
16068       if (bytemode == b_T_mode)
16069         {
16070           if (address_mode != mode_64bit
16071               || !((sizeflag & DFLAG) || (rex & REX_W)))
16072             {
16073               /* The operand-size prefix is overridden by a REX prefix.  */
16074               if ((sizeflag & DFLAG) || (rex & REX_W))
16075                 op &= 0xffffffff;
16076               else
16077                 op &= 0xffff;
16078           }
16079         }
16080       else
16081         {
16082           if (!(rex & REX_W))
16083             {
16084               if (sizeflag & DFLAG)
16085                 op &= 0xffffffff;
16086               else
16087                 op &= 0xffff;
16088             }
16089         }
16090       break;
16091     case v_mode:
16092       /* The operand-size prefix is overridden by a REX prefix.  */
16093       if ((sizeflag & DFLAG) || (rex & REX_W))
16094         op = get32s ();
16095       else
16096         op = get16 ();
16097       break;
16098     default:
16099       oappend (INTERNAL_DISASSEMBLER_ERROR);
16100       return;
16101     }
16102
16103   scratchbuf[0] = '$';
16104   print_operand_value (scratchbuf + 1, 1, op);
16105   oappend_maybe_intel (scratchbuf);
16106 }
16107
16108 static void
16109 OP_J (int bytemode, int sizeflag)
16110 {
16111   bfd_vma disp;
16112   bfd_vma mask = -1;
16113   bfd_vma segment = 0;
16114
16115   switch (bytemode)
16116     {
16117     case b_mode:
16118       FETCH_DATA (the_info, codep + 1);
16119       disp = *codep++;
16120       if ((disp & 0x80) != 0)
16121         disp -= 0x100;
16122       break;
16123     case v_mode:
16124       if (isa64 == amd64)
16125         USED_REX (REX_W);
16126       if ((sizeflag & DFLAG)
16127           || (address_mode == mode_64bit
16128               && (isa64 != amd64 || (rex & REX_W))))
16129         disp = get32s ();
16130       else
16131         {
16132           disp = get16 ();
16133           if ((disp & 0x8000) != 0)
16134             disp -= 0x10000;
16135           /* In 16bit mode, address is wrapped around at 64k within
16136              the same segment.  Otherwise, a data16 prefix on a jump
16137              instruction means that the pc is masked to 16 bits after
16138              the displacement is added!  */
16139           mask = 0xffff;
16140           if ((prefixes & PREFIX_DATA) == 0)
16141             segment = ((start_pc + codep - start_codep)
16142                        & ~((bfd_vma) 0xffff));
16143         }
16144       if (address_mode != mode_64bit
16145           || (isa64 == amd64 && !(rex & REX_W)))
16146         used_prefixes |= (prefixes & PREFIX_DATA);
16147       break;
16148     default:
16149       oappend (INTERNAL_DISASSEMBLER_ERROR);
16150       return;
16151     }
16152   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16153   set_op (disp, 0);
16154   print_operand_value (scratchbuf, 1, disp);
16155   oappend (scratchbuf);
16156 }
16157
16158 static void
16159 OP_SEG (int bytemode, int sizeflag)
16160 {
16161   if (bytemode == w_mode)
16162     oappend (names_seg[modrm.reg]);
16163   else
16164     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16165 }
16166
16167 static void
16168 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16169 {
16170   int seg, offset;
16171
16172   if (sizeflag & DFLAG)
16173     {
16174       offset = get32 ();
16175       seg = get16 ();
16176     }
16177   else
16178     {
16179       offset = get16 ();
16180       seg = get16 ();
16181     }
16182   used_prefixes |= (prefixes & PREFIX_DATA);
16183   if (intel_syntax)
16184     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16185   else
16186     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16187   oappend (scratchbuf);
16188 }
16189
16190 static void
16191 OP_OFF (int bytemode, int sizeflag)
16192 {
16193   bfd_vma off;
16194
16195   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16196     intel_operand_size (bytemode, sizeflag);
16197   append_seg ();
16198
16199   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16200     off = get32 ();
16201   else
16202     off = get16 ();
16203
16204   if (intel_syntax)
16205     {
16206       if (!active_seg_prefix)
16207         {
16208           oappend (names_seg[ds_reg - es_reg]);
16209           oappend (":");
16210         }
16211     }
16212   print_operand_value (scratchbuf, 1, off);
16213   oappend (scratchbuf);
16214 }
16215
16216 static void
16217 OP_OFF64 (int bytemode, int sizeflag)
16218 {
16219   bfd_vma off;
16220
16221   if (address_mode != mode_64bit
16222       || (prefixes & PREFIX_ADDR))
16223     {
16224       OP_OFF (bytemode, sizeflag);
16225       return;
16226     }
16227
16228   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16229     intel_operand_size (bytemode, sizeflag);
16230   append_seg ();
16231
16232   off = get64 ();
16233
16234   if (intel_syntax)
16235     {
16236       if (!active_seg_prefix)
16237         {
16238           oappend (names_seg[ds_reg - es_reg]);
16239           oappend (":");
16240         }
16241     }
16242   print_operand_value (scratchbuf, 1, off);
16243   oappend (scratchbuf);
16244 }
16245
16246 static void
16247 ptr_reg (int code, int sizeflag)
16248 {
16249   const char *s;
16250
16251   *obufp++ = open_char;
16252   used_prefixes |= (prefixes & PREFIX_ADDR);
16253   if (address_mode == mode_64bit)
16254     {
16255       if (!(sizeflag & AFLAG))
16256         s = names32[code - eAX_reg];
16257       else
16258         s = names64[code - eAX_reg];
16259     }
16260   else if (sizeflag & AFLAG)
16261     s = names32[code - eAX_reg];
16262   else
16263     s = names16[code - eAX_reg];
16264   oappend (s);
16265   *obufp++ = close_char;
16266   *obufp = 0;
16267 }
16268
16269 static void
16270 OP_ESreg (int code, int sizeflag)
16271 {
16272   if (intel_syntax)
16273     {
16274       switch (codep[-1])
16275         {
16276         case 0x6d:      /* insw/insl */
16277           intel_operand_size (z_mode, sizeflag);
16278           break;
16279         case 0xa5:      /* movsw/movsl/movsq */
16280         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16281         case 0xab:      /* stosw/stosl */
16282         case 0xaf:      /* scasw/scasl */
16283           intel_operand_size (v_mode, sizeflag);
16284           break;
16285         default:
16286           intel_operand_size (b_mode, sizeflag);
16287         }
16288     }
16289   oappend_maybe_intel ("%es:");
16290   ptr_reg (code, sizeflag);
16291 }
16292
16293 static void
16294 OP_DSreg (int code, int sizeflag)
16295 {
16296   if (intel_syntax)
16297     {
16298       switch (codep[-1])
16299         {
16300         case 0x6f:      /* outsw/outsl */
16301           intel_operand_size (z_mode, sizeflag);
16302           break;
16303         case 0xa5:      /* movsw/movsl/movsq */
16304         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16305         case 0xad:      /* lodsw/lodsl/lodsq */
16306           intel_operand_size (v_mode, sizeflag);
16307           break;
16308         default:
16309           intel_operand_size (b_mode, sizeflag);
16310         }
16311     }
16312   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16313      default segment register DS is printed.  */
16314   if (!active_seg_prefix)
16315     active_seg_prefix = PREFIX_DS;
16316   append_seg ();
16317   ptr_reg (code, sizeflag);
16318 }
16319
16320 static void
16321 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16322 {
16323   int add;
16324   if (rex & REX_R)
16325     {
16326       USED_REX (REX_R);
16327       add = 8;
16328     }
16329   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16330     {
16331       all_prefixes[last_lock_prefix] = 0;
16332       used_prefixes |= PREFIX_LOCK;
16333       add = 8;
16334     }
16335   else
16336     add = 0;
16337   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16338   oappend_maybe_intel (scratchbuf);
16339 }
16340
16341 static void
16342 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16343 {
16344   int add;
16345   USED_REX (REX_R);
16346   if (rex & REX_R)
16347     add = 8;
16348   else
16349     add = 0;
16350   if (intel_syntax)
16351     sprintf (scratchbuf, "db%d", modrm.reg + add);
16352   else
16353     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16354   oappend (scratchbuf);
16355 }
16356
16357 static void
16358 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16359 {
16360   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16361   oappend_maybe_intel (scratchbuf);
16362 }
16363
16364 static void
16365 OP_R (int bytemode, int sizeflag)
16366 {
16367   /* Skip mod/rm byte.  */
16368   MODRM_CHECK;
16369   codep++;
16370   OP_E_register (bytemode, sizeflag);
16371 }
16372
16373 static void
16374 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16375 {
16376   int reg = modrm.reg;
16377   const char **names;
16378
16379   used_prefixes |= (prefixes & PREFIX_DATA);
16380   if (prefixes & PREFIX_DATA)
16381     {
16382       names = names_xmm;
16383       USED_REX (REX_R);
16384       if (rex & REX_R)
16385         reg += 8;
16386     }
16387   else
16388     names = names_mm;
16389   oappend (names[reg]);
16390 }
16391
16392 static void
16393 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16394 {
16395   int reg = modrm.reg;
16396   const char **names;
16397
16398   USED_REX (REX_R);
16399   if (rex & REX_R)
16400     reg += 8;
16401   if (vex.evex)
16402     {
16403       if (!vex.r)
16404         reg += 16;
16405     }
16406
16407   if (need_vex
16408       && bytemode != xmm_mode
16409       && bytemode != xmmq_mode
16410       && bytemode != evex_half_bcst_xmmq_mode
16411       && bytemode != ymm_mode
16412       && bytemode != scalar_mode)
16413     {
16414       switch (vex.length)
16415         {
16416         case 128:
16417           names = names_xmm;
16418           break;
16419         case 256:
16420           if (vex.w
16421               || (bytemode != vex_vsib_q_w_dq_mode
16422                   && bytemode != vex_vsib_q_w_d_mode))
16423             names = names_ymm;
16424           else
16425             names = names_xmm;
16426           break;
16427         case 512:
16428           names = names_zmm;
16429           break;
16430         default:
16431           abort ();
16432         }
16433     }
16434   else if (bytemode == xmmq_mode
16435            || bytemode == evex_half_bcst_xmmq_mode)
16436     {
16437       switch (vex.length)
16438         {
16439         case 128:
16440         case 256:
16441           names = names_xmm;
16442           break;
16443         case 512:
16444           names = names_ymm;
16445           break;
16446         default:
16447           abort ();
16448         }
16449     }
16450   else if (bytemode == ymm_mode)
16451     names = names_ymm;
16452   else
16453     names = names_xmm;
16454   oappend (names[reg]);
16455 }
16456
16457 static void
16458 OP_EM (int bytemode, int sizeflag)
16459 {
16460   int reg;
16461   const char **names;
16462
16463   if (modrm.mod != 3)
16464     {
16465       if (intel_syntax
16466           && (bytemode == v_mode || bytemode == v_swap_mode))
16467         {
16468           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16469           used_prefixes |= (prefixes & PREFIX_DATA);
16470         }
16471       OP_E (bytemode, sizeflag);
16472       return;
16473     }
16474
16475   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16476     swap_operand ();
16477
16478   /* Skip mod/rm byte.  */
16479   MODRM_CHECK;
16480   codep++;
16481   used_prefixes |= (prefixes & PREFIX_DATA);
16482   reg = modrm.rm;
16483   if (prefixes & PREFIX_DATA)
16484     {
16485       names = names_xmm;
16486       USED_REX (REX_B);
16487       if (rex & REX_B)
16488         reg += 8;
16489     }
16490   else
16491     names = names_mm;
16492   oappend (names[reg]);
16493 }
16494
16495 /* cvt* are the only instructions in sse2 which have
16496    both SSE and MMX operands and also have 0x66 prefix
16497    in their opcode. 0x66 was originally used to differentiate
16498    between SSE and MMX instruction(operands). So we have to handle the
16499    cvt* separately using OP_EMC and OP_MXC */
16500 static void
16501 OP_EMC (int bytemode, int sizeflag)
16502 {
16503   if (modrm.mod != 3)
16504     {
16505       if (intel_syntax && bytemode == v_mode)
16506         {
16507           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16508           used_prefixes |= (prefixes & PREFIX_DATA);
16509         }
16510       OP_E (bytemode, sizeflag);
16511       return;
16512     }
16513
16514   /* Skip mod/rm byte.  */
16515   MODRM_CHECK;
16516   codep++;
16517   used_prefixes |= (prefixes & PREFIX_DATA);
16518   oappend (names_mm[modrm.rm]);
16519 }
16520
16521 static void
16522 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16523 {
16524   used_prefixes |= (prefixes & PREFIX_DATA);
16525   oappend (names_mm[modrm.reg]);
16526 }
16527
16528 static void
16529 OP_EX (int bytemode, int sizeflag)
16530 {
16531   int reg;
16532   const char **names;
16533
16534   /* Skip mod/rm byte.  */
16535   MODRM_CHECK;
16536   codep++;
16537
16538   if (modrm.mod != 3)
16539     {
16540       OP_E_memory (bytemode, sizeflag);
16541       return;
16542     }
16543
16544   reg = modrm.rm;
16545   USED_REX (REX_B);
16546   if (rex & REX_B)
16547     reg += 8;
16548   if (vex.evex)
16549     {
16550       USED_REX (REX_X);
16551       if ((rex & REX_X))
16552         reg += 16;
16553     }
16554
16555   if ((sizeflag & SUFFIX_ALWAYS)
16556       && (bytemode == x_swap_mode
16557           || bytemode == d_swap_mode
16558           || bytemode == dqw_swap_mode
16559           || bytemode == d_scalar_swap_mode
16560           || bytemode == q_swap_mode
16561           || bytemode == q_scalar_swap_mode))
16562     swap_operand ();
16563
16564   if (need_vex
16565       && bytemode != xmm_mode
16566       && bytemode != xmmdw_mode
16567       && bytemode != xmmqd_mode
16568       && bytemode != xmm_mb_mode
16569       && bytemode != xmm_mw_mode
16570       && bytemode != xmm_md_mode
16571       && bytemode != xmm_mq_mode
16572       && bytemode != xmm_mdq_mode
16573       && bytemode != xmmq_mode
16574       && bytemode != evex_half_bcst_xmmq_mode
16575       && bytemode != ymm_mode
16576       && bytemode != d_scalar_mode
16577       && bytemode != d_scalar_swap_mode
16578       && bytemode != q_scalar_mode
16579       && bytemode != q_scalar_swap_mode
16580       && bytemode != vex_scalar_w_dq_mode)
16581     {
16582       switch (vex.length)
16583         {
16584         case 128:
16585           names = names_xmm;
16586           break;
16587         case 256:
16588           names = names_ymm;
16589           break;
16590         case 512:
16591           names = names_zmm;
16592           break;
16593         default:
16594           abort ();
16595         }
16596     }
16597   else if (bytemode == xmmq_mode
16598            || bytemode == evex_half_bcst_xmmq_mode)
16599     {
16600       switch (vex.length)
16601         {
16602         case 128:
16603         case 256:
16604           names = names_xmm;
16605           break;
16606         case 512:
16607           names = names_ymm;
16608           break;
16609         default:
16610           abort ();
16611         }
16612     }
16613   else if (bytemode == ymm_mode)
16614     names = names_ymm;
16615   else
16616     names = names_xmm;
16617   oappend (names[reg]);
16618 }
16619
16620 static void
16621 OP_MS (int bytemode, int sizeflag)
16622 {
16623   if (modrm.mod == 3)
16624     OP_EM (bytemode, sizeflag);
16625   else
16626     BadOp ();
16627 }
16628
16629 static void
16630 OP_XS (int bytemode, int sizeflag)
16631 {
16632   if (modrm.mod == 3)
16633     OP_EX (bytemode, sizeflag);
16634   else
16635     BadOp ();
16636 }
16637
16638 static void
16639 OP_M (int bytemode, int sizeflag)
16640 {
16641   if (modrm.mod == 3)
16642     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16643     BadOp ();
16644   else
16645     OP_E (bytemode, sizeflag);
16646 }
16647
16648 static void
16649 OP_0f07 (int bytemode, int sizeflag)
16650 {
16651   if (modrm.mod != 3 || modrm.rm != 0)
16652     BadOp ();
16653   else
16654     OP_E (bytemode, sizeflag);
16655 }
16656
16657 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16658    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16659
16660 static void
16661 NOP_Fixup1 (int bytemode, int sizeflag)
16662 {
16663   if ((prefixes & PREFIX_DATA) != 0
16664       || (rex != 0
16665           && rex != 0x48
16666           && address_mode == mode_64bit))
16667     OP_REG (bytemode, sizeflag);
16668   else
16669     strcpy (obuf, "nop");
16670 }
16671
16672 static void
16673 NOP_Fixup2 (int bytemode, int sizeflag)
16674 {
16675   if ((prefixes & PREFIX_DATA) != 0
16676       || (rex != 0
16677           && rex != 0x48
16678           && address_mode == mode_64bit))
16679     OP_IMREG (bytemode, sizeflag);
16680 }
16681
16682 static const char *const Suffix3DNow[] = {
16683 /* 00 */        NULL,           NULL,           NULL,           NULL,
16684 /* 04 */        NULL,           NULL,           NULL,           NULL,
16685 /* 08 */        NULL,           NULL,           NULL,           NULL,
16686 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16687 /* 10 */        NULL,           NULL,           NULL,           NULL,
16688 /* 14 */        NULL,           NULL,           NULL,           NULL,
16689 /* 18 */        NULL,           NULL,           NULL,           NULL,
16690 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16691 /* 20 */        NULL,           NULL,           NULL,           NULL,
16692 /* 24 */        NULL,           NULL,           NULL,           NULL,
16693 /* 28 */        NULL,           NULL,           NULL,           NULL,
16694 /* 2C */        NULL,           NULL,           NULL,           NULL,
16695 /* 30 */        NULL,           NULL,           NULL,           NULL,
16696 /* 34 */        NULL,           NULL,           NULL,           NULL,
16697 /* 38 */        NULL,           NULL,           NULL,           NULL,
16698 /* 3C */        NULL,           NULL,           NULL,           NULL,
16699 /* 40 */        NULL,           NULL,           NULL,           NULL,
16700 /* 44 */        NULL,           NULL,           NULL,           NULL,
16701 /* 48 */        NULL,           NULL,           NULL,           NULL,
16702 /* 4C */        NULL,           NULL,           NULL,           NULL,
16703 /* 50 */        NULL,           NULL,           NULL,           NULL,
16704 /* 54 */        NULL,           NULL,           NULL,           NULL,
16705 /* 58 */        NULL,           NULL,           NULL,           NULL,
16706 /* 5C */        NULL,           NULL,           NULL,           NULL,
16707 /* 60 */        NULL,           NULL,           NULL,           NULL,
16708 /* 64 */        NULL,           NULL,           NULL,           NULL,
16709 /* 68 */        NULL,           NULL,           NULL,           NULL,
16710 /* 6C */        NULL,           NULL,           NULL,           NULL,
16711 /* 70 */        NULL,           NULL,           NULL,           NULL,
16712 /* 74 */        NULL,           NULL,           NULL,           NULL,
16713 /* 78 */        NULL,           NULL,           NULL,           NULL,
16714 /* 7C */        NULL,           NULL,           NULL,           NULL,
16715 /* 80 */        NULL,           NULL,           NULL,           NULL,
16716 /* 84 */        NULL,           NULL,           NULL,           NULL,
16717 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16718 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16719 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16720 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16721 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16722 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16723 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16724 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16725 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16726 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16727 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16728 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16729 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16730 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16731 /* C0 */        NULL,           NULL,           NULL,           NULL,
16732 /* C4 */        NULL,           NULL,           NULL,           NULL,
16733 /* C8 */        NULL,           NULL,           NULL,           NULL,
16734 /* CC */        NULL,           NULL,           NULL,           NULL,
16735 /* D0 */        NULL,           NULL,           NULL,           NULL,
16736 /* D4 */        NULL,           NULL,           NULL,           NULL,
16737 /* D8 */        NULL,           NULL,           NULL,           NULL,
16738 /* DC */        NULL,           NULL,           NULL,           NULL,
16739 /* E0 */        NULL,           NULL,           NULL,           NULL,
16740 /* E4 */        NULL,           NULL,           NULL,           NULL,
16741 /* E8 */        NULL,           NULL,           NULL,           NULL,
16742 /* EC */        NULL,           NULL,           NULL,           NULL,
16743 /* F0 */        NULL,           NULL,           NULL,           NULL,
16744 /* F4 */        NULL,           NULL,           NULL,           NULL,
16745 /* F8 */        NULL,           NULL,           NULL,           NULL,
16746 /* FC */        NULL,           NULL,           NULL,           NULL,
16747 };
16748
16749 static void
16750 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16751 {
16752   const char *mnemonic;
16753
16754   FETCH_DATA (the_info, codep + 1);
16755   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16756      place where an 8-bit immediate would normally go.  ie. the last
16757      byte of the instruction.  */
16758   obufp = mnemonicendp;
16759   mnemonic = Suffix3DNow[*codep++ & 0xff];
16760   if (mnemonic)
16761     oappend (mnemonic);
16762   else
16763     {
16764       /* Since a variable sized modrm/sib chunk is between the start
16765          of the opcode (0x0f0f) and the opcode suffix, we need to do
16766          all the modrm processing first, and don't know until now that
16767          we have a bad opcode.  This necessitates some cleaning up.  */
16768       op_out[0][0] = '\0';
16769       op_out[1][0] = '\0';
16770       BadOp ();
16771     }
16772   mnemonicendp = obufp;
16773 }
16774
16775 static struct op simd_cmp_op[] =
16776 {
16777   { STRING_COMMA_LEN ("eq") },
16778   { STRING_COMMA_LEN ("lt") },
16779   { STRING_COMMA_LEN ("le") },
16780   { STRING_COMMA_LEN ("unord") },
16781   { STRING_COMMA_LEN ("neq") },
16782   { STRING_COMMA_LEN ("nlt") },
16783   { STRING_COMMA_LEN ("nle") },
16784   { STRING_COMMA_LEN ("ord") }
16785 };
16786
16787 static void
16788 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16789 {
16790   unsigned int cmp_type;
16791
16792   FETCH_DATA (the_info, codep + 1);
16793   cmp_type = *codep++ & 0xff;
16794   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16795     {
16796       char suffix [3];
16797       char *p = mnemonicendp - 2;
16798       suffix[0] = p[0];
16799       suffix[1] = p[1];
16800       suffix[2] = '\0';
16801       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16802       mnemonicendp += simd_cmp_op[cmp_type].len;
16803     }
16804   else
16805     {
16806       /* We have a reserved extension byte.  Output it directly.  */
16807       scratchbuf[0] = '$';
16808       print_operand_value (scratchbuf + 1, 1, cmp_type);
16809       oappend_maybe_intel (scratchbuf);
16810       scratchbuf[0] = '\0';
16811     }
16812 }
16813
16814 static void
16815 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16816           int sizeflag ATTRIBUTE_UNUSED)
16817 {
16818   /* mwaitx %eax,%ecx,%ebx */
16819   if (!intel_syntax)
16820     {
16821       const char **names = (address_mode == mode_64bit
16822                             ? names64 : names32);
16823       strcpy (op_out[0], names[0]);
16824       strcpy (op_out[1], names[1]);
16825       strcpy (op_out[2], names[3]);
16826       two_source_ops = 1;
16827     }
16828   /* Skip mod/rm byte.  */
16829   MODRM_CHECK;
16830   codep++;
16831 }
16832
16833 static void
16834 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16835           int sizeflag ATTRIBUTE_UNUSED)
16836 {
16837   /* mwait %eax,%ecx  */
16838   if (!intel_syntax)
16839     {
16840       const char **names = (address_mode == mode_64bit
16841                             ? names64 : names32);
16842       strcpy (op_out[0], names[0]);
16843       strcpy (op_out[1], names[1]);
16844       two_source_ops = 1;
16845     }
16846   /* Skip mod/rm byte.  */
16847   MODRM_CHECK;
16848   codep++;
16849 }
16850
16851 static void
16852 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16853             int sizeflag ATTRIBUTE_UNUSED)
16854 {
16855   /* monitor %eax,%ecx,%edx"  */
16856   if (!intel_syntax)
16857     {
16858       const char **op1_names;
16859       const char **names = (address_mode == mode_64bit
16860                             ? names64 : names32);
16861
16862       if (!(prefixes & PREFIX_ADDR))
16863         op1_names = (address_mode == mode_16bit
16864                      ? names16 : names);
16865       else
16866         {
16867           /* Remove "addr16/addr32".  */
16868           all_prefixes[last_addr_prefix] = 0;
16869           op1_names = (address_mode != mode_32bit
16870                        ? names32 : names16);
16871           used_prefixes |= PREFIX_ADDR;
16872         }
16873       strcpy (op_out[0], op1_names[0]);
16874       strcpy (op_out[1], names[1]);
16875       strcpy (op_out[2], names[2]);
16876       two_source_ops = 1;
16877     }
16878   /* Skip mod/rm byte.  */
16879   MODRM_CHECK;
16880   codep++;
16881 }
16882
16883 static void
16884 BadOp (void)
16885 {
16886   /* Throw away prefixes and 1st. opcode byte.  */
16887   codep = insn_codep + 1;
16888   oappend ("(bad)");
16889 }
16890
16891 static void
16892 REP_Fixup (int bytemode, int sizeflag)
16893 {
16894   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16895      lods and stos.  */
16896   if (prefixes & PREFIX_REPZ)
16897     all_prefixes[last_repz_prefix] = REP_PREFIX;
16898
16899   switch (bytemode)
16900     {
16901     case al_reg:
16902     case eAX_reg:
16903     case indir_dx_reg:
16904       OP_IMREG (bytemode, sizeflag);
16905       break;
16906     case eDI_reg:
16907       OP_ESreg (bytemode, sizeflag);
16908       break;
16909     case eSI_reg:
16910       OP_DSreg (bytemode, sizeflag);
16911       break;
16912     default:
16913       abort ();
16914       break;
16915     }
16916 }
16917
16918 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16919    "bnd".  */
16920
16921 static void
16922 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16923 {
16924   if (prefixes & PREFIX_REPNZ)
16925     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16926 }
16927
16928 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16929    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16930  */
16931
16932 static void
16933 HLE_Fixup1 (int bytemode, int sizeflag)
16934 {
16935   if (modrm.mod != 3
16936       && (prefixes & PREFIX_LOCK) != 0)
16937     {
16938       if (prefixes & PREFIX_REPZ)
16939         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16940       if (prefixes & PREFIX_REPNZ)
16941         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16942     }
16943
16944   OP_E (bytemode, sizeflag);
16945 }
16946
16947 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16948    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16949  */
16950
16951 static void
16952 HLE_Fixup2 (int bytemode, int sizeflag)
16953 {
16954   if (modrm.mod != 3)
16955     {
16956       if (prefixes & PREFIX_REPZ)
16957         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16958       if (prefixes & PREFIX_REPNZ)
16959         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16960     }
16961
16962   OP_E (bytemode, sizeflag);
16963 }
16964
16965 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16966    "xrelease" for memory operand.  No check for LOCK prefix.   */
16967
16968 static void
16969 HLE_Fixup3 (int bytemode, int sizeflag)
16970 {
16971   if (modrm.mod != 3
16972       && last_repz_prefix > last_repnz_prefix
16973       && (prefixes & PREFIX_REPZ) != 0)
16974     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16975
16976   OP_E (bytemode, sizeflag);
16977 }
16978
16979 static void
16980 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16981 {
16982   USED_REX (REX_W);
16983   if (rex & REX_W)
16984     {
16985       /* Change cmpxchg8b to cmpxchg16b.  */
16986       char *p = mnemonicendp - 2;
16987       mnemonicendp = stpcpy (p, "16b");
16988       bytemode = o_mode;
16989     }
16990   else if ((prefixes & PREFIX_LOCK) != 0)
16991     {
16992       if (prefixes & PREFIX_REPZ)
16993         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16994       if (prefixes & PREFIX_REPNZ)
16995         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16996     }
16997
16998   OP_M (bytemode, sizeflag);
16999 }
17000
17001 static void
17002 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17003 {
17004   const char **names;
17005
17006   if (need_vex)
17007     {
17008       switch (vex.length)
17009         {
17010         case 128:
17011           names = names_xmm;
17012           break;
17013         case 256:
17014           names = names_ymm;
17015           break;
17016         default:
17017           abort ();
17018         }
17019     }
17020   else
17021     names = names_xmm;
17022   oappend (names[reg]);
17023 }
17024
17025 static void
17026 CRC32_Fixup (int bytemode, int sizeflag)
17027 {
17028   /* Add proper suffix to "crc32".  */
17029   char *p = mnemonicendp;
17030
17031   switch (bytemode)
17032     {
17033     case b_mode:
17034       if (intel_syntax)
17035         goto skip;
17036
17037       *p++ = 'b';
17038       break;
17039     case v_mode:
17040       if (intel_syntax)
17041         goto skip;
17042
17043       USED_REX (REX_W);
17044       if (rex & REX_W)
17045         *p++ = 'q';
17046       else
17047         {
17048           if (sizeflag & DFLAG)
17049             *p++ = 'l';
17050           else
17051             *p++ = 'w';
17052           used_prefixes |= (prefixes & PREFIX_DATA);
17053         }
17054       break;
17055     default:
17056       oappend (INTERNAL_DISASSEMBLER_ERROR);
17057       break;
17058     }
17059   mnemonicendp = p;
17060   *p = '\0';
17061
17062 skip:
17063   if (modrm.mod == 3)
17064     {
17065       int add;
17066
17067       /* Skip mod/rm byte.  */
17068       MODRM_CHECK;
17069       codep++;
17070
17071       USED_REX (REX_B);
17072       add = (rex & REX_B) ? 8 : 0;
17073       if (bytemode == b_mode)
17074         {
17075           USED_REX (0);
17076           if (rex)
17077             oappend (names8rex[modrm.rm + add]);
17078           else
17079             oappend (names8[modrm.rm + add]);
17080         }
17081       else
17082         {
17083           USED_REX (REX_W);
17084           if (rex & REX_W)
17085             oappend (names64[modrm.rm + add]);
17086           else if ((prefixes & PREFIX_DATA))
17087             oappend (names16[modrm.rm + add]);
17088           else
17089             oappend (names32[modrm.rm + add]);
17090         }
17091     }
17092   else
17093     OP_E (bytemode, sizeflag);
17094 }
17095
17096 static void
17097 FXSAVE_Fixup (int bytemode, int sizeflag)
17098 {
17099   /* Add proper suffix to "fxsave" and "fxrstor".  */
17100   USED_REX (REX_W);
17101   if (rex & REX_W)
17102     {
17103       char *p = mnemonicendp;
17104       *p++ = '6';
17105       *p++ = '4';
17106       *p = '\0';
17107       mnemonicendp = p;
17108     }
17109   OP_M (bytemode, sizeflag);
17110 }
17111
17112 /* Display the destination register operand for instructions with
17113    VEX. */
17114
17115 static void
17116 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17117 {
17118   int reg;
17119   const char **names;
17120
17121   if (!need_vex)
17122     abort ();
17123
17124   if (!need_vex_reg)
17125     return;
17126
17127   reg = vex.register_specifier;
17128   if (vex.evex)
17129     {
17130       if (!vex.v)
17131         reg += 16;
17132     }
17133
17134   if (bytemode == vex_scalar_mode)
17135     {
17136       oappend (names_xmm[reg]);
17137       return;
17138     }
17139
17140   switch (vex.length)
17141     {
17142     case 128:
17143       switch (bytemode)
17144         {
17145         case vex_mode:
17146         case vex128_mode:
17147         case vex_vsib_q_w_dq_mode:
17148         case vex_vsib_q_w_d_mode:
17149           names = names_xmm;
17150           break;
17151         case dq_mode:
17152           if (vex.w)
17153             names = names64;
17154           else
17155             names = names32;
17156           break;
17157         case mask_bd_mode:
17158         case mask_mode:
17159           names = names_mask;
17160           break;
17161         default:
17162           abort ();
17163           return;
17164         }
17165       break;
17166     case 256:
17167       switch (bytemode)
17168         {
17169         case vex_mode:
17170         case vex256_mode:
17171           names = names_ymm;
17172           break;
17173         case vex_vsib_q_w_dq_mode:
17174         case vex_vsib_q_w_d_mode:
17175           names = vex.w ? names_ymm : names_xmm;
17176           break;
17177         case mask_bd_mode:
17178         case mask_mode:
17179           names = names_mask;
17180           break;
17181         default:
17182           abort ();
17183           return;
17184         }
17185       break;
17186     case 512:
17187       names = names_zmm;
17188       break;
17189     default:
17190       abort ();
17191       break;
17192     }
17193   oappend (names[reg]);
17194 }
17195
17196 /* Get the VEX immediate byte without moving codep.  */
17197
17198 static unsigned char
17199 get_vex_imm8 (int sizeflag, int opnum)
17200 {
17201   int bytes_before_imm = 0;
17202
17203   if (modrm.mod != 3)
17204     {
17205       /* There are SIB/displacement bytes.  */
17206       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17207         {
17208           /* 32/64 bit address mode */
17209           int base = modrm.rm;
17210
17211           /* Check SIB byte.  */
17212           if (base == 4)
17213             {
17214               FETCH_DATA (the_info, codep + 1);
17215               base = *codep & 7;
17216               /* When decoding the third source, don't increase
17217                  bytes_before_imm as this has already been incremented
17218                  by one in OP_E_memory while decoding the second
17219                  source operand.  */
17220               if (opnum == 0)
17221                 bytes_before_imm++;
17222             }
17223
17224           /* Don't increase bytes_before_imm when decoding the third source,
17225              it has already been incremented by OP_E_memory while decoding
17226              the second source operand.  */
17227           if (opnum == 0)
17228             {
17229               switch (modrm.mod)
17230                 {
17231                   case 0:
17232                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17233                        SIB == 5, there is a 4 byte displacement.  */
17234                     if (base != 5)
17235                       /* No displacement. */
17236                       break;
17237                   case 2:
17238                     /* 4 byte displacement.  */
17239                     bytes_before_imm += 4;
17240                     break;
17241                   case 1:
17242                     /* 1 byte displacement.  */
17243                     bytes_before_imm++;
17244                     break;
17245                 }
17246             }
17247         }
17248       else
17249         {
17250           /* 16 bit address mode */
17251           /* Don't increase bytes_before_imm when decoding the third source,
17252              it has already been incremented by OP_E_memory while decoding
17253              the second source operand.  */
17254           if (opnum == 0)
17255             {
17256               switch (modrm.mod)
17257                 {
17258                 case 0:
17259                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17260                   if (modrm.rm != 6)
17261                     /* No displacement. */
17262                     break;
17263                 case 2:
17264                   /* 2 byte displacement.  */
17265                   bytes_before_imm += 2;
17266                   break;
17267                 case 1:
17268                   /* 1 byte displacement: when decoding the third source,
17269                      don't increase bytes_before_imm as this has already
17270                      been incremented by one in OP_E_memory while decoding
17271                      the second source operand.  */
17272                   if (opnum == 0)
17273                     bytes_before_imm++;
17274
17275                   break;
17276                 }
17277             }
17278         }
17279     }
17280
17281   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17282   return codep [bytes_before_imm];
17283 }
17284
17285 static void
17286 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17287 {
17288   const char **names;
17289
17290   if (reg == -1 && modrm.mod != 3)
17291     {
17292       OP_E_memory (bytemode, sizeflag);
17293       return;
17294     }
17295   else
17296     {
17297       if (reg == -1)
17298         {
17299           reg = modrm.rm;
17300           USED_REX (REX_B);
17301           if (rex & REX_B)
17302             reg += 8;
17303         }
17304       else if (reg > 7 && address_mode != mode_64bit)
17305         BadOp ();
17306     }
17307
17308   switch (vex.length)
17309     {
17310     case 128:
17311       names = names_xmm;
17312       break;
17313     case 256:
17314       names = names_ymm;
17315       break;
17316     default:
17317       abort ();
17318     }
17319   oappend (names[reg]);
17320 }
17321
17322 static void
17323 OP_EX_VexImmW (int bytemode, int sizeflag)
17324 {
17325   int reg = -1;
17326   static unsigned char vex_imm8;
17327
17328   if (vex_w_done == 0)
17329     {
17330       vex_w_done = 1;
17331
17332       /* Skip mod/rm byte.  */
17333       MODRM_CHECK;
17334       codep++;
17335
17336       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17337
17338       if (vex.w)
17339           reg = vex_imm8 >> 4;
17340
17341       OP_EX_VexReg (bytemode, sizeflag, reg);
17342     }
17343   else if (vex_w_done == 1)
17344     {
17345       vex_w_done = 2;
17346
17347       if (!vex.w)
17348           reg = vex_imm8 >> 4;
17349
17350       OP_EX_VexReg (bytemode, sizeflag, reg);
17351     }
17352   else
17353     {
17354       /* Output the imm8 directly.  */
17355       scratchbuf[0] = '$';
17356       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17357       oappend_maybe_intel (scratchbuf);
17358       scratchbuf[0] = '\0';
17359       codep++;
17360     }
17361 }
17362
17363 static void
17364 OP_Vex_2src (int bytemode, int sizeflag)
17365 {
17366   if (modrm.mod == 3)
17367     {
17368       int reg = modrm.rm;
17369       USED_REX (REX_B);
17370       if (rex & REX_B)
17371         reg += 8;
17372       oappend (names_xmm[reg]);
17373     }
17374   else
17375     {
17376       if (intel_syntax
17377           && (bytemode == v_mode || bytemode == v_swap_mode))
17378         {
17379           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17380           used_prefixes |= (prefixes & PREFIX_DATA);
17381         }
17382       OP_E (bytemode, sizeflag);
17383     }
17384 }
17385
17386 static void
17387 OP_Vex_2src_1 (int bytemode, int sizeflag)
17388 {
17389   if (modrm.mod == 3)
17390     {
17391       /* Skip mod/rm byte.   */
17392       MODRM_CHECK;
17393       codep++;
17394     }
17395
17396   if (vex.w)
17397     oappend (names_xmm[vex.register_specifier]);
17398   else
17399     OP_Vex_2src (bytemode, sizeflag);
17400 }
17401
17402 static void
17403 OP_Vex_2src_2 (int bytemode, int sizeflag)
17404 {
17405   if (vex.w)
17406     OP_Vex_2src (bytemode, sizeflag);
17407   else
17408     oappend (names_xmm[vex.register_specifier]);
17409 }
17410
17411 static void
17412 OP_EX_VexW (int bytemode, int sizeflag)
17413 {
17414   int reg = -1;
17415
17416   if (!vex_w_done)
17417     {
17418       vex_w_done = 1;
17419
17420       /* Skip mod/rm byte.  */
17421       MODRM_CHECK;
17422       codep++;
17423
17424       if (vex.w)
17425         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17426     }
17427   else
17428     {
17429       if (!vex.w)
17430         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17431     }
17432
17433   OP_EX_VexReg (bytemode, sizeflag, reg);
17434 }
17435
17436 static void
17437 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17438              int sizeflag ATTRIBUTE_UNUSED)
17439 {
17440   /* Skip the immediate byte and check for invalid bits.  */
17441   FETCH_DATA (the_info, codep + 1);
17442   if (*codep++ & 0xf)
17443     BadOp ();
17444 }
17445
17446 static void
17447 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17448 {
17449   int reg;
17450   const char **names;
17451
17452   FETCH_DATA (the_info, codep + 1);
17453   reg = *codep++;
17454
17455   if (bytemode != x_mode)
17456     abort ();
17457
17458   if (reg & 0xf)
17459       BadOp ();
17460
17461   reg >>= 4;
17462   if (reg > 7 && address_mode != mode_64bit)
17463     BadOp ();
17464
17465   switch (vex.length)
17466     {
17467     case 128:
17468       names = names_xmm;
17469       break;
17470     case 256:
17471       names = names_ymm;
17472       break;
17473     default:
17474       abort ();
17475     }
17476   oappend (names[reg]);
17477 }
17478
17479 static void
17480 OP_XMM_VexW (int bytemode, int sizeflag)
17481 {
17482   /* Turn off the REX.W bit since it is used for swapping operands
17483      now.  */
17484   rex &= ~REX_W;
17485   OP_XMM (bytemode, sizeflag);
17486 }
17487
17488 static void
17489 OP_EX_Vex (int bytemode, int sizeflag)
17490 {
17491   if (modrm.mod != 3)
17492     {
17493       if (vex.register_specifier != 0)
17494         BadOp ();
17495       need_vex_reg = 0;
17496     }
17497   OP_EX (bytemode, sizeflag);
17498 }
17499
17500 static void
17501 OP_XMM_Vex (int bytemode, int sizeflag)
17502 {
17503   if (modrm.mod != 3)
17504     {
17505       if (vex.register_specifier != 0)
17506         BadOp ();
17507       need_vex_reg = 0;
17508     }
17509   OP_XMM (bytemode, sizeflag);
17510 }
17511
17512 static void
17513 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17514 {
17515   switch (vex.length)
17516     {
17517     case 128:
17518       mnemonicendp = stpcpy (obuf, "vzeroupper");
17519       break;
17520     case 256:
17521       mnemonicendp = stpcpy (obuf, "vzeroall");
17522       break;
17523     default:
17524       abort ();
17525     }
17526 }
17527
17528 static struct op vex_cmp_op[] =
17529 {
17530   { STRING_COMMA_LEN ("eq") },
17531   { STRING_COMMA_LEN ("lt") },
17532   { STRING_COMMA_LEN ("le") },
17533   { STRING_COMMA_LEN ("unord") },
17534   { STRING_COMMA_LEN ("neq") },
17535   { STRING_COMMA_LEN ("nlt") },
17536   { STRING_COMMA_LEN ("nle") },
17537   { STRING_COMMA_LEN ("ord") },
17538   { STRING_COMMA_LEN ("eq_uq") },
17539   { STRING_COMMA_LEN ("nge") },
17540   { STRING_COMMA_LEN ("ngt") },
17541   { STRING_COMMA_LEN ("false") },
17542   { STRING_COMMA_LEN ("neq_oq") },
17543   { STRING_COMMA_LEN ("ge") },
17544   { STRING_COMMA_LEN ("gt") },
17545   { STRING_COMMA_LEN ("true") },
17546   { STRING_COMMA_LEN ("eq_os") },
17547   { STRING_COMMA_LEN ("lt_oq") },
17548   { STRING_COMMA_LEN ("le_oq") },
17549   { STRING_COMMA_LEN ("unord_s") },
17550   { STRING_COMMA_LEN ("neq_us") },
17551   { STRING_COMMA_LEN ("nlt_uq") },
17552   { STRING_COMMA_LEN ("nle_uq") },
17553   { STRING_COMMA_LEN ("ord_s") },
17554   { STRING_COMMA_LEN ("eq_us") },
17555   { STRING_COMMA_LEN ("nge_uq") },
17556   { STRING_COMMA_LEN ("ngt_uq") },
17557   { STRING_COMMA_LEN ("false_os") },
17558   { STRING_COMMA_LEN ("neq_os") },
17559   { STRING_COMMA_LEN ("ge_oq") },
17560   { STRING_COMMA_LEN ("gt_oq") },
17561   { STRING_COMMA_LEN ("true_us") },
17562 };
17563
17564 static void
17565 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17566 {
17567   unsigned int cmp_type;
17568
17569   FETCH_DATA (the_info, codep + 1);
17570   cmp_type = *codep++ & 0xff;
17571   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17572     {
17573       char suffix [3];
17574       char *p = mnemonicendp - 2;
17575       suffix[0] = p[0];
17576       suffix[1] = p[1];
17577       suffix[2] = '\0';
17578       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17579       mnemonicendp += vex_cmp_op[cmp_type].len;
17580     }
17581   else
17582     {
17583       /* We have a reserved extension byte.  Output it directly.  */
17584       scratchbuf[0] = '$';
17585       print_operand_value (scratchbuf + 1, 1, cmp_type);
17586       oappend_maybe_intel (scratchbuf);
17587       scratchbuf[0] = '\0';
17588     }
17589 }
17590
17591 static void
17592 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17593              int sizeflag ATTRIBUTE_UNUSED)
17594 {
17595   unsigned int cmp_type;
17596
17597   if (!vex.evex)
17598     abort ();
17599
17600   FETCH_DATA (the_info, codep + 1);
17601   cmp_type = *codep++ & 0xff;
17602   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17603      If it's the case, print suffix, otherwise - print the immediate.  */
17604   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17605       && cmp_type != 3
17606       && cmp_type != 7)
17607     {
17608       char suffix [3];
17609       char *p = mnemonicendp - 2;
17610
17611       /* vpcmp* can have both one- and two-lettered suffix.  */
17612       if (p[0] == 'p')
17613         {
17614           p++;
17615           suffix[0] = p[0];
17616           suffix[1] = '\0';
17617         }
17618       else
17619         {
17620           suffix[0] = p[0];
17621           suffix[1] = p[1];
17622           suffix[2] = '\0';
17623         }
17624
17625       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17626       mnemonicendp += simd_cmp_op[cmp_type].len;
17627     }
17628   else
17629     {
17630       /* We have a reserved extension byte.  Output it directly.  */
17631       scratchbuf[0] = '$';
17632       print_operand_value (scratchbuf + 1, 1, cmp_type);
17633       oappend_maybe_intel (scratchbuf);
17634       scratchbuf[0] = '\0';
17635     }
17636 }
17637
17638 static const struct op pclmul_op[] =
17639 {
17640   { STRING_COMMA_LEN ("lql") },
17641   { STRING_COMMA_LEN ("hql") },
17642   { STRING_COMMA_LEN ("lqh") },
17643   { STRING_COMMA_LEN ("hqh") }
17644 };
17645
17646 static void
17647 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17648               int sizeflag ATTRIBUTE_UNUSED)
17649 {
17650   unsigned int pclmul_type;
17651
17652   FETCH_DATA (the_info, codep + 1);
17653   pclmul_type = *codep++ & 0xff;
17654   switch (pclmul_type)
17655     {
17656     case 0x10:
17657       pclmul_type = 2;
17658       break;
17659     case 0x11:
17660       pclmul_type = 3;
17661       break;
17662     default:
17663       break;
17664     }
17665   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17666     {
17667       char suffix [4];
17668       char *p = mnemonicendp - 3;
17669       suffix[0] = p[0];
17670       suffix[1] = p[1];
17671       suffix[2] = p[2];
17672       suffix[3] = '\0';
17673       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17674       mnemonicendp += pclmul_op[pclmul_type].len;
17675     }
17676   else
17677     {
17678       /* We have a reserved extension byte.  Output it directly.  */
17679       scratchbuf[0] = '$';
17680       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17681       oappend_maybe_intel (scratchbuf);
17682       scratchbuf[0] = '\0';
17683     }
17684 }
17685
17686 static void
17687 MOVBE_Fixup (int bytemode, int sizeflag)
17688 {
17689   /* Add proper suffix to "movbe".  */
17690   char *p = mnemonicendp;
17691
17692   switch (bytemode)
17693     {
17694     case v_mode:
17695       if (intel_syntax)
17696         goto skip;
17697
17698       USED_REX (REX_W);
17699       if (sizeflag & SUFFIX_ALWAYS)
17700         {
17701           if (rex & REX_W)
17702             *p++ = 'q';
17703           else
17704             {
17705               if (sizeflag & DFLAG)
17706                 *p++ = 'l';
17707               else
17708                 *p++ = 'w';
17709               used_prefixes |= (prefixes & PREFIX_DATA);
17710             }
17711         }
17712       break;
17713     default:
17714       oappend (INTERNAL_DISASSEMBLER_ERROR);
17715       break;
17716     }
17717   mnemonicendp = p;
17718   *p = '\0';
17719
17720 skip:
17721   OP_M (bytemode, sizeflag);
17722 }
17723
17724 static void
17725 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17726 {
17727   int reg;
17728   const char **names;
17729
17730   /* Skip mod/rm byte.  */
17731   MODRM_CHECK;
17732   codep++;
17733
17734   if (vex.w)
17735     names = names64;
17736   else
17737     names = names32;
17738
17739   reg = modrm.rm;
17740   USED_REX (REX_B);
17741   if (rex & REX_B)
17742     reg += 8;
17743
17744   oappend (names[reg]);
17745 }
17746
17747 static void
17748 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17749 {
17750   const char **names;
17751
17752   if (vex.w)
17753     names = names64;
17754   else
17755     names = names32;
17756
17757   oappend (names[vex.register_specifier]);
17758 }
17759
17760 static void
17761 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17762 {
17763   if (!vex.evex
17764       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17765     abort ();
17766
17767   USED_REX (REX_R);
17768   if ((rex & REX_R) != 0 || !vex.r)
17769     {
17770       BadOp ();
17771       return;
17772     }
17773
17774   oappend (names_mask [modrm.reg]);
17775 }
17776
17777 static void
17778 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17779 {
17780   if (!vex.evex
17781       || (bytemode != evex_rounding_mode
17782           && bytemode != evex_sae_mode))
17783     abort ();
17784   if (modrm.mod == 3 && vex.b)
17785     switch (bytemode)
17786       {
17787       case evex_rounding_mode:
17788         oappend (names_rounding[vex.ll]);
17789         break;
17790       case evex_sae_mode:
17791         oappend ("{sae}");
17792         break;
17793       default:
17794         break;
17795       }
17796 }