opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void VPCOM_Fixup (int, int);
 103 static void OP_0f07 (int, int);
 104 static void OP_Monitor (int, int);
 105 static void OP_Mwait (int, int);
 106 static void OP_Mwaitx (int, int);
 107 static void NOP_Fixup1 (int, int);
 108 static void NOP_Fixup2 (int, int);
 109 static void OP_3DNowSuffix (int, int);
 110 static void CMP_Fixup (int, int);
 111 static void BadOp (void);
 112 static void REP_Fixup (int, int);
 113 static void BND_Fixup (int, int);
 114 static void NOTRACK_Fixup (int, int);
 115 static void HLE_Fixup1 (int, int);
 116 static void HLE_Fixup2 (int, int);
 117 static void HLE_Fixup3 (int, int);
 118 static void CMPXCHG8B_Fixup (int, int);
 119 static void XMM_Fixup (int, int);
 120 static void CRC32_Fixup (int, int);
 121 static void FXSAVE_Fixup (int, int);
 122 static void PCMPESTR_Fixup (int, int);
 123 static void OP_LWPCB_E (int, int);
 124 static void OP_LWP_E (int, int);
 125 static void OP_Vex_2src_1 (int, int);
 126 static void OP_Vex_2src_2 (int, int);
 127
 128 static void MOVBE_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* REX bits in original REX prefix ignored.  */
 158 static int rex_ignored;
 159 /* Mark parts used in the REX prefix.  When we are testing for
 160    empty prefix (for 8bit register REX extension), just mask it
 161    out.  Otherwise test for REX bit is excuse for existence of REX
 162    only in case value is nonzero.  */
 163 #define USED_REX(value)                                 \
 164   {                                                     \
 165     if (value)                                          \
 166       {                                                 \
 167         if ((rex & value))                              \
 168           rex_used |= (value) | REX_OPCODE;             \
 169       }                                                 \
 170     else                                                \
 171       rex_used |= REX_OPCODE;                           \
 172   }
 173
 174 /* Flags for prefixes which we somehow handled when printing the
 175    current instruction.  */
 176 static int used_prefixes;
 177
 178 /* Flags stored in PREFIXES.  */
 179 #define PREFIX_REPZ 1
 180 #define PREFIX_REPNZ 2
 181 #define PREFIX_LOCK 4
 182 #define PREFIX_CS 8
 183 #define PREFIX_SS 0x10
 184 #define PREFIX_DS 0x20
 185 #define PREFIX_ES 0x40
 186 #define PREFIX_FS 0x80
 187 #define PREFIX_GS 0x100
 188 #define PREFIX_DATA 0x200
 189 #define PREFIX_ADDR 0x400
 190 #define PREFIX_FWAIT 0x800
 191
 192 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 193    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 194    on error.  */
 195 #define FETCH_DATA(info, addr) \
 196   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 197    ? 1 : fetch_data ((info), (addr)))
 198
 199 static int
 200 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 201 {
 202   int status;
 203   struct dis_private *priv = (struct dis_private *) info->private_data;
 204   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 205
 206   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 207     status = (*info->read_memory_func) (start,
 208                                         priv->max_fetched,
 209                                         addr - priv->max_fetched,
 210                                         info);
 211   else
 212     status = -1;
 213   if (status != 0)
 214     {
 215       /* If we did manage to read at least one byte, then
 216          print_insn_i386 will do something sensible.  Otherwise, print
 217          an error.  We do that here because this is where we know
 218          STATUS.  */
 219       if (priv->max_fetched == priv->the_buffer)
 220         (*info->memory_error_func) (status, start, info);
 221       OPCODES_SIGLONGJMP (priv->bailout, 1);
 222     }
 223   else
 224     priv->max_fetched = addr;
 225   return 1;
 226 }
 227
 228 /* Possible values for prefix requirement.  */
 229 #define PREFIX_IGNORED_SHIFT    16
 230 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 234 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 235
 236 /* Opcode prefixes.  */
 237 #define PREFIX_OPCODE           (PREFIX_REPZ \
 238                                  | PREFIX_REPNZ \
 239                                  | PREFIX_DATA)
 240
 241 /* Prefixes ignored.  */
 242 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 243                                  | PREFIX_IGNORED_REPNZ \
 244                                  | PREFIX_IGNORED_DATA)
 245
 246 #define XX { NULL, 0 }
 247 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 248
 249 #define Eb { OP_E, b_mode }
 250 #define Ebnd { OP_E, bnd_mode }
 251 #define EbS { OP_E, b_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mx { OP_M, x_mode }
 276 #define Mxmm { OP_M, xmm_mode }
 277 #define Gb { OP_G, b_mode }
 278 #define Gbnd { OP_G, bnd_mode }
 279 #define Gv { OP_G, v_mode }
 280 #define Gd { OP_G, d_mode }
 281 #define Gdq { OP_G, dq_mode }
 282 #define Gm { OP_G, m_mode }
 283 #define Gw { OP_G, w_mode }
 284 #define Rd { OP_R, d_mode }
 285 #define Rdq { OP_R, dq_mode }
 286 #define Rm { OP_R, m_mode }
 287 #define Ib { OP_I, b_mode }
 288 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 289 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 290 #define Iv { OP_I, v_mode }
 291 #define sIv { OP_sI, v_mode }
 292 #define Iq { OP_I, q_mode }
 293 #define Iv64 { OP_I64, v_mode }
 294 #define Iw { OP_I, w_mode }
 295 #define I1 { OP_I, const_1_mode }
 296 #define Jb { OP_J, b_mode }
 297 #define Jv { OP_J, v_mode }
 298 #define Cm { OP_C, m_mode }
 299 #define Dm { OP_D, m_mode }
 300 #define Td { OP_T, d_mode }
 301 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 302
 303 #define RMeAX { OP_REG, eAX_reg }
 304 #define RMeBX { OP_REG, eBX_reg }
 305 #define RMeCX { OP_REG, eCX_reg }
 306 #define RMeDX { OP_REG, eDX_reg }
 307 #define RMeSP { OP_REG, eSP_reg }
 308 #define RMeBP { OP_REG, eBP_reg }
 309 #define RMeSI { OP_REG, eSI_reg }
 310 #define RMeDI { OP_REG, eDI_reg }
 311 #define RMrAX { OP_REG, rAX_reg }
 312 #define RMrBX { OP_REG, rBX_reg }
 313 #define RMrCX { OP_REG, rCX_reg }
 314 #define RMrDX { OP_REG, rDX_reg }
 315 #define RMrSP { OP_REG, rSP_reg }
 316 #define RMrBP { OP_REG, rBP_reg }
 317 #define RMrSI { OP_REG, rSI_reg }
 318 #define RMrDI { OP_REG, rDI_reg }
 319 #define RMAL { OP_REG, al_reg }
 320 #define RMCL { OP_REG, cl_reg }
 321 #define RMDL { OP_REG, dl_reg }
 322 #define RMBL { OP_REG, bl_reg }
 323 #define RMAH { OP_REG, ah_reg }
 324 #define RMCH { OP_REG, ch_reg }
 325 #define RMDH { OP_REG, dh_reg }
 326 #define RMBH { OP_REG, bh_reg }
 327 #define RMAX { OP_REG, ax_reg }
 328 #define RMDX { OP_REG, dx_reg }
 329
 330 #define eAX { OP_IMREG, eAX_reg }
 331 #define eBX { OP_IMREG, eBX_reg }
 332 #define eCX { OP_IMREG, eCX_reg }
 333 #define eDX { OP_IMREG, eDX_reg }
 334 #define eSP { OP_IMREG, eSP_reg }
 335 #define eBP { OP_IMREG, eBP_reg }
 336 #define eSI { OP_IMREG, eSI_reg }
 337 #define eDI { OP_IMREG, eDI_reg }
 338 #define AL { OP_IMREG, al_reg }
 339 #define CL { OP_IMREG, cl_reg }
 340 #define DL { OP_IMREG, dl_reg }
 341 #define BL { OP_IMREG, bl_reg }
 342 #define AH { OP_IMREG, ah_reg }
 343 #define CH { OP_IMREG, ch_reg }
 344 #define DH { OP_IMREG, dh_reg }
 345 #define BH { OP_IMREG, bh_reg }
 346 #define AX { OP_IMREG, ax_reg }
 347 #define DX { OP_IMREG, dx_reg }
 348 #define zAX { OP_IMREG, z_mode_ax_reg }
 349 #define indirDX { OP_IMREG, indir_dx_reg }
 350
 351 #define Sw { OP_SEG, w_mode }
 352 #define Sv { OP_SEG, v_mode }
 353 #define Ap { OP_DIR, 0 }
 354 #define Ob { OP_OFF64, b_mode }
 355 #define Ov { OP_OFF64, v_mode }
 356 #define Xb { OP_DSreg, eSI_reg }
 357 #define Xv { OP_DSreg, eSI_reg }
 358 #define Xz { OP_DSreg, eSI_reg }
 359 #define Yb { OP_ESreg, eDI_reg }
 360 #define Yv { OP_ESreg, eDI_reg }
 361 #define DSBX { OP_DSreg, eBX_reg }
 362
 363 #define es { OP_REG, es_reg }
 364 #define ss { OP_REG, ss_reg }
 365 #define cs { OP_REG, cs_reg }
 366 #define ds { OP_REG, ds_reg }
 367 #define fs { OP_REG, fs_reg }
 368 #define gs { OP_REG, gs_reg }
 369
 370 #define MX { OP_MMX, 0 }
 371 #define XM { OP_XMM, 0 }
 372 #define XMScalar { OP_XMM, scalar_mode }
 373 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 374 #define XMM { OP_XMM, xmm_mode }
 375 #define XMxmmq { OP_XMM, xmmq_mode }
 376 #define EM { OP_EM, v_mode }
 377 #define EMS { OP_EM, v_swap_mode }
 378 #define EMd { OP_EM, d_mode }
 379 #define EMx { OP_EM, x_mode }
 380 #define EXbScalar { OP_EX, b_scalar_mode }
 381 #define EXw { OP_EX, w_mode }
 382 #define EXwScalar { OP_EX, w_scalar_mode }
 383 #define EXd { OP_EX, d_mode }
 384 #define EXdScalar { OP_EX, d_scalar_mode }
 385 #define EXdS { OP_EX, d_swap_mode }
 386 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 387 #define EXq { OP_EX, q_mode }
 388 #define EXqScalar { OP_EX, q_scalar_mode }
 389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 390 #define EXqS { OP_EX, q_swap_mode }
 391 #define EXx { OP_EX, x_mode }
 392 #define EXxS { OP_EX, x_swap_mode }
 393 #define EXxmm { OP_EX, xmm_mode }
 394 #define EXymm { OP_EX, ymm_mode }
 395 #define EXxmmq { OP_EX, xmmq_mode }
 396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 399 #define EXxmm_md { OP_EX, xmm_md_mode }
 400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 402 #define EXxmmdw { OP_EX, xmmdw_mode }
 403 #define EXxmmqd { OP_EX, xmmqd_mode }
 404 #define EXymmq { OP_EX, ymmq_mode }
 405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 409 #define MS { OP_MS, v_mode }
 410 #define XS { OP_XS, v_mode }
 411 #define EMCq { OP_EMC, q_mode }
 412 #define MXC { OP_MXC, 0 }
 413 #define OPSUF { OP_3DNowSuffix, 0 }
 414 #define CMP { CMP_Fixup, 0 }
 415 #define XMM0 { XMM_Fixup, 0 }
 416 #define FXSAVE { FXSAVE_Fixup, 0 }
 417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 419
 420 #define Vex { OP_VEX, vex_mode }
 421 #define VexScalar { OP_VEX, vex_scalar_mode }
 422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 423 #define Vex128 { OP_VEX, vex128_mode }
 424 #define Vex256 { OP_VEX, vex256_mode }
 425 #define VexGdq { OP_VEX, dq_mode }
 426 #define VexI4 { VEXI4_Fixup, 0}
 427 #define EXdVex { OP_EX_Vex, d_mode }
 428 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 429 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 430 #define EXqVex { OP_EX_Vex, q_mode }
 431 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 432 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 433 #define EXVexW { OP_EX_VexW, x_mode }
 434 #define EXdVexW { OP_EX_VexW, d_mode }
 435 #define EXqVexW { OP_EX_VexW, q_mode }
 436 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 437 #define XMVex { OP_XMM_Vex, 0 }
 438 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 439 #define XMVexW { OP_XMM_VexW, 0 }
 440 #define XMVexI4 { OP_REG_VexI4, x_mode }
 441 #define PCLMUL { PCLMUL_Fixup, 0 }
 442 #define VZERO { VZERO_Fixup, 0 }
 443 #define VCMP { VCMP_Fixup, 0 }
 444 #define VPCMP { VPCMP_Fixup, 0 }
 445 #define VPCOM { VPCOM_Fixup, 0 }
 446
 447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 448 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 449
 450 #define XMask { OP_Mask, mask_mode }
 451 #define MaskG { OP_G, mask_mode }
 452 #define MaskE { OP_E, mask_mode }
 453 #define MaskBDE { OP_E, mask_bd_mode }
 454 #define MaskR { OP_R, mask_mode }
 455 #define MaskVex { OP_VEX, mask_mode }
 456
 457 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 458 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 459 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 460 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 461
 462 /* Used handle "rep" prefix for string instructions.  */
 463 #define Xbr { REP_Fixup, eSI_reg }
 464 #define Xvr { REP_Fixup, eSI_reg }
 465 #define Ybr { REP_Fixup, eDI_reg }
 466 #define Yvr { REP_Fixup, eDI_reg }
 467 #define Yzr { REP_Fixup, eDI_reg }
 468 #define indirDXr { REP_Fixup, indir_dx_reg }
 469 #define ALr { REP_Fixup, al_reg }
 470 #define eAXr { REP_Fixup, eAX_reg }
 471
 472 /* Used handle HLE prefix for lockable instructions.  */
 473 #define Ebh1 { HLE_Fixup1, b_mode }
 474 #define Evh1 { HLE_Fixup1, v_mode }
 475 #define Ebh2 { HLE_Fixup2, b_mode }
 476 #define Evh2 { HLE_Fixup2, v_mode }
 477 #define Ebh3 { HLE_Fixup3, b_mode }
 478 #define Evh3 { HLE_Fixup3, v_mode }
 479
 480 #define BND { BND_Fixup, 0 }
 481 #define NOTRACK { NOTRACK_Fixup, 0 }
 482
 483 #define cond_jump_flag { NULL, cond_jump_mode }
 484 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 485
 486 /* bits in sizeflag */
 487 #define SUFFIX_ALWAYS 4
 488 #define AFLAG 2
 489 #define DFLAG 1
 490
 491 enum
 492 {
 493   /* byte operand */
 494   b_mode = 1,
 495   /* byte operand with operand swapped */
 496   b_swap_mode,
 497   /* byte operand, sign extend like 'T' suffix */
 498   b_T_mode,
 499   /* operand size depends on prefixes */
 500   v_mode,
 501   /* operand size depends on prefixes with operand swapped */
 502   v_swap_mode,
 503   /* word operand */
 504   w_mode,
 505   /* double word operand  */
 506   d_mode,
 507   /* double word operand with operand swapped */
 508   d_swap_mode,
 509   /* quad word operand */
 510   q_mode,
 511   /* quad word operand with operand swapped */
 512   q_swap_mode,
 513   /* ten-byte operand */
 514   t_mode,
 515   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 516      broadcast enabled.  */
 517   x_mode,
 518   /* Similar to x_mode, but with different EVEX mem shifts.  */
 519   evex_x_gscat_mode,
 520   /* Similar to x_mode, but with disabled broadcast.  */
 521   evex_x_nobcst_mode,
 522   /* Similar to x_mode, but with operands swapped and disabled broadcast
 523      in EVEX.  */
 524   x_swap_mode,
 525   /* 16-byte XMM operand */
 526   xmm_mode,
 527   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 528      memory operand (depending on vector length).  Broadcast isn't
 529      allowed.  */
 530   xmmq_mode,
 531   /* Same as xmmq_mode, but broadcast is allowed.  */
 532   evex_half_bcst_xmmq_mode,
 533   /* XMM register or byte memory operand */
 534   xmm_mb_mode,
 535   /* XMM register or word memory operand */
 536   xmm_mw_mode,
 537   /* XMM register or double word memory operand */
 538   xmm_md_mode,
 539   /* XMM register or quad word memory operand */
 540   xmm_mq_mode,
 541   /* XMM register or double/quad word memory operand, depending on
 542      VEX.W.  */
 543   xmm_mdq_mode,
 544   /* 16-byte XMM, word, double word or quad word operand.  */
 545   xmmdw_mode,
 546   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 547   xmmqd_mode,
 548   /* 32-byte YMM operand */
 549   ymm_mode,
 550   /* quad word, ymmword or zmmword memory operand.  */
 551   ymmq_mode,
 552   /* 32-byte YMM or 16-byte word operand */
 553   ymmxmm_mode,
 554   /* d_mode in 32bit, q_mode in 64bit mode.  */
 555   m_mode,
 556   /* pair of v_mode operands */
 557   a_mode,
 558   cond_jump_mode,
 559   loop_jcxz_mode,
 560   v_bnd_mode,
 561   /* operand size depends on REX prefixes.  */
 562   dq_mode,
 563   /* registers like dq_mode, memory like w_mode.  */
 564   dqw_mode,
 565   bnd_mode,
 566   /* 4- or 6-byte pointer operand */
 567   f_mode,
 568   const_1_mode,
 569   /* v_mode for indirect branch opcodes.  */
 570   indir_v_mode,
 571   /* v_mode for stack-related opcodes.  */
 572   stack_v_mode,
 573   /* non-quad operand size depends on prefixes */
 574   z_mode,
 575   /* 16-byte operand */
 576   o_mode,
 577   /* registers like dq_mode, memory like b_mode.  */
 578   dqb_mode,
 579   /* registers like d_mode, memory like b_mode.  */
 580   db_mode,
 581   /* registers like d_mode, memory like w_mode.  */
 582   dw_mode,
 583   /* registers like dq_mode, memory like d_mode.  */
 584   dqd_mode,
 585   /* normal vex mode */
 586   vex_mode,
 587   /* 128bit vex mode */
 588   vex128_mode,
 589   /* 256bit vex mode */
 590   vex256_mode,
 591   /* operand size depends on the VEX.W bit.  */
 592   vex_w_dq_mode,
 593
 594   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 595   vex_vsib_d_w_dq_mode,
 596   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 597   vex_vsib_d_w_d_mode,
 598   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 599   vex_vsib_q_w_dq_mode,
 600   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 601   vex_vsib_q_w_d_mode,
 602
 603   /* scalar, ignore vector length.  */
 604   scalar_mode,
 605   /* like b_mode, ignore vector length.  */
 606   b_scalar_mode,
 607   /* like w_mode, ignore vector length.  */
 608   w_scalar_mode,
 609   /* like d_mode, ignore vector length.  */
 610   d_scalar_mode,
 611   /* like d_swap_mode, ignore vector length.  */
 612   d_scalar_swap_mode,
 613   /* like q_mode, ignore vector length.  */
 614   q_scalar_mode,
 615   /* like q_swap_mode, ignore vector length.  */
 616   q_scalar_swap_mode,
 617   /* like vex_mode, ignore vector length.  */
 618   vex_scalar_mode,
 619   /* like vex_w_dq_mode, ignore vector length.  */
 620   vex_scalar_w_dq_mode,
 621
 622   /* Static rounding.  */
 623   evex_rounding_mode,
 624   /* Supress all exceptions.  */
 625   evex_sae_mode,
 626
 627   /* Mask register operand.  */
 628   mask_mode,
 629   /* Mask register operand.  */
 630   mask_bd_mode,
 631
 632   es_reg,
 633   cs_reg,
 634   ss_reg,
 635   ds_reg,
 636   fs_reg,
 637   gs_reg,
 638
 639   eAX_reg,
 640   eCX_reg,
 641   eDX_reg,
 642   eBX_reg,
 643   eSP_reg,
 644   eBP_reg,
 645   eSI_reg,
 646   eDI_reg,
 647
 648   al_reg,
 649   cl_reg,
 650   dl_reg,
 651   bl_reg,
 652   ah_reg,
 653   ch_reg,
 654   dh_reg,
 655   bh_reg,
 656
 657   ax_reg,
 658   cx_reg,
 659   dx_reg,
 660   bx_reg,
 661   sp_reg,
 662   bp_reg,
 663   si_reg,
 664   di_reg,
 665
 666   rAX_reg,
 667   rCX_reg,
 668   rDX_reg,
 669   rBX_reg,
 670   rSP_reg,
 671   rBP_reg,
 672   rSI_reg,
 673   rDI_reg,
 674
 675   z_mode_ax_reg,
 676   indir_dx_reg
 677 };
 678
 679 enum
 680 {
 681   FLOATCODE = 1,
 682   USE_REG_TABLE,
 683   USE_MOD_TABLE,
 684   USE_RM_TABLE,
 685   USE_PREFIX_TABLE,
 686   USE_X86_64_TABLE,
 687   USE_3BYTE_TABLE,
 688   USE_XOP_8F_TABLE,
 689   USE_VEX_C4_TABLE,
 690   USE_VEX_C5_TABLE,
 691   USE_VEX_LEN_TABLE,
 692   USE_VEX_W_TABLE,
 693   USE_EVEX_TABLE
 694 };
 695
 696 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 697
 698 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 699 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 700 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 701 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 702 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 703 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 704 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 705 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 706 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 707 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 708 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 709 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 710 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 711 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 712 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 713
 714 enum
 715 {
 716   REG_80 = 0,
 717   REG_81,
 718   REG_83,
 719   REG_8F,
 720   REG_C0,
 721   REG_C1,
 722   REG_C6,
 723   REG_C7,
 724   REG_D0,
 725   REG_D1,
 726   REG_D2,
 727   REG_D3,
 728   REG_F6,
 729   REG_F7,
 730   REG_FE,
 731   REG_FF,
 732   REG_0F00,
 733   REG_0F01,
 734   REG_0F0D,
 735   REG_0F18,
 736   REG_0F1E_MOD_3,
 737   REG_0F71,
 738   REG_0F72,
 739   REG_0F73,
 740   REG_0FA6,
 741   REG_0FA7,
 742   REG_0FAE,
 743   REG_0FBA,
 744   REG_0FC7,
 745   REG_VEX_0F71,
 746   REG_VEX_0F72,
 747   REG_VEX_0F73,
 748   REG_VEX_0FAE,
 749   REG_VEX_0F38F3,
 750   REG_XOP_LWPCB,
 751   REG_XOP_LWP,
 752   REG_XOP_TBM_01,
 753   REG_XOP_TBM_02,
 754
 755   REG_EVEX_0F71,
 756   REG_EVEX_0F72,
 757   REG_EVEX_0F73,
 758   REG_EVEX_0F38C6,
 759   REG_EVEX_0F38C7
 760 };
 761
 762 enum
 763 {
 764   MOD_8D = 0,
 765   MOD_C6_REG_7,
 766   MOD_C7_REG_7,
 767   MOD_FF_REG_3,
 768   MOD_FF_REG_5,
 769   MOD_0F01_REG_0,
 770   MOD_0F01_REG_1,
 771   MOD_0F01_REG_2,
 772   MOD_0F01_REG_3,
 773   MOD_0F01_REG_5,
 774   MOD_0F01_REG_7,
 775   MOD_0F12_PREFIX_0,
 776   MOD_0F13,
 777   MOD_0F16_PREFIX_0,
 778   MOD_0F17,
 779   MOD_0F18_REG_0,
 780   MOD_0F18_REG_1,
 781   MOD_0F18_REG_2,
 782   MOD_0F18_REG_3,
 783   MOD_0F18_REG_4,
 784   MOD_0F18_REG_5,
 785   MOD_0F18_REG_6,
 786   MOD_0F18_REG_7,
 787   MOD_0F1A_PREFIX_0,
 788   MOD_0F1B_PREFIX_0,
 789   MOD_0F1B_PREFIX_1,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F51,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_62_32BIT,
 832   MOD_C4_32BIT,
 833   MOD_C5_32BIT,
 834   MOD_VEX_0F12_PREFIX_0,
 835   MOD_VEX_0F13,
 836   MOD_VEX_0F16_PREFIX_0,
 837   MOD_VEX_0F17,
 838   MOD_VEX_0F2B,
 839   MOD_VEX_W_0_0F41_P_0_LEN_1,
 840   MOD_VEX_W_1_0F41_P_0_LEN_1,
 841   MOD_VEX_W_0_0F41_P_2_LEN_1,
 842   MOD_VEX_W_1_0F41_P_2_LEN_1,
 843   MOD_VEX_W_0_0F42_P_0_LEN_1,
 844   MOD_VEX_W_1_0F42_P_0_LEN_1,
 845   MOD_VEX_W_0_0F42_P_2_LEN_1,
 846   MOD_VEX_W_1_0F42_P_2_LEN_1,
 847   MOD_VEX_W_0_0F44_P_0_LEN_1,
 848   MOD_VEX_W_1_0F44_P_0_LEN_1,
 849   MOD_VEX_W_0_0F44_P_2_LEN_1,
 850   MOD_VEX_W_1_0F44_P_2_LEN_1,
 851   MOD_VEX_W_0_0F45_P_0_LEN_1,
 852   MOD_VEX_W_1_0F45_P_0_LEN_1,
 853   MOD_VEX_W_0_0F45_P_2_LEN_1,
 854   MOD_VEX_W_1_0F45_P_2_LEN_1,
 855   MOD_VEX_W_0_0F46_P_0_LEN_1,
 856   MOD_VEX_W_1_0F46_P_0_LEN_1,
 857   MOD_VEX_W_0_0F46_P_2_LEN_1,
 858   MOD_VEX_W_1_0F46_P_2_LEN_1,
 859   MOD_VEX_W_0_0F47_P_0_LEN_1,
 860   MOD_VEX_W_1_0F47_P_0_LEN_1,
 861   MOD_VEX_W_0_0F47_P_2_LEN_1,
 862   MOD_VEX_W_1_0F47_P_2_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 865   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 866   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 868   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 869   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 870   MOD_VEX_0F50,
 871   MOD_VEX_0F71_REG_2,
 872   MOD_VEX_0F71_REG_4,
 873   MOD_VEX_0F71_REG_6,
 874   MOD_VEX_0F72_REG_2,
 875   MOD_VEX_0F72_REG_4,
 876   MOD_VEX_0F72_REG_6,
 877   MOD_VEX_0F73_REG_2,
 878   MOD_VEX_0F73_REG_3,
 879   MOD_VEX_0F73_REG_6,
 880   MOD_VEX_0F73_REG_7,
 881   MOD_VEX_W_0_0F91_P_0_LEN_0,
 882   MOD_VEX_W_1_0F91_P_0_LEN_0,
 883   MOD_VEX_W_0_0F91_P_2_LEN_0,
 884   MOD_VEX_W_1_0F91_P_2_LEN_0,
 885   MOD_VEX_W_0_0F92_P_0_LEN_0,
 886   MOD_VEX_W_0_0F92_P_2_LEN_0,
 887   MOD_VEX_W_0_0F92_P_3_LEN_0,
 888   MOD_VEX_W_1_0F92_P_3_LEN_0,
 889   MOD_VEX_W_0_0F93_P_0_LEN_0,
 890   MOD_VEX_W_0_0F93_P_2_LEN_0,
 891   MOD_VEX_W_0_0F93_P_3_LEN_0,
 892   MOD_VEX_W_1_0F93_P_3_LEN_0,
 893   MOD_VEX_W_0_0F98_P_0_LEN_0,
 894   MOD_VEX_W_1_0F98_P_0_LEN_0,
 895   MOD_VEX_W_0_0F98_P_2_LEN_0,
 896   MOD_VEX_W_1_0F98_P_2_LEN_0,
 897   MOD_VEX_W_0_0F99_P_0_LEN_0,
 898   MOD_VEX_W_1_0F99_P_0_LEN_0,
 899   MOD_VEX_W_0_0F99_P_2_LEN_0,
 900   MOD_VEX_W_1_0F99_P_2_LEN_0,
 901   MOD_VEX_0FAE_REG_2,
 902   MOD_VEX_0FAE_REG_3,
 903   MOD_VEX_0FD7_PREFIX_2,
 904   MOD_VEX_0FE7_PREFIX_2,
 905   MOD_VEX_0FF0_PREFIX_3,
 906   MOD_VEX_0F381A_PREFIX_2,
 907   MOD_VEX_0F382A_PREFIX_2,
 908   MOD_VEX_0F382C_PREFIX_2,
 909   MOD_VEX_0F382D_PREFIX_2,
 910   MOD_VEX_0F382E_PREFIX_2,
 911   MOD_VEX_0F382F_PREFIX_2,
 912   MOD_VEX_0F385A_PREFIX_2,
 913   MOD_VEX_0F388C_PREFIX_2,
 914   MOD_VEX_0F388E_PREFIX_2,
 915   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 923
 924   MOD_EVEX_0F10_PREFIX_1,
 925   MOD_EVEX_0F10_PREFIX_3,
 926   MOD_EVEX_0F11_PREFIX_1,
 927   MOD_EVEX_0F11_PREFIX_3,
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F16_PREFIX_0,
 930   MOD_EVEX_0F38C6_REG_1,
 931   MOD_EVEX_0F38C6_REG_2,
 932   MOD_EVEX_0F38C6_REG_5,
 933   MOD_EVEX_0F38C6_REG_6,
 934   MOD_EVEX_0F38C7_REG_1,
 935   MOD_EVEX_0F38C7_REG_2,
 936   MOD_EVEX_0F38C7_REG_5,
 937   MOD_EVEX_0F38C7_REG_6
 938 };
 939
 940 enum
 941 {
 942   RM_C6_REG_7 = 0,
 943   RM_C7_REG_7,
 944   RM_0F01_REG_0,
 945   RM_0F01_REG_1,
 946   RM_0F01_REG_2,
 947   RM_0F01_REG_3,
 948   RM_0F01_REG_5,
 949   RM_0F01_REG_7,
 950   RM_0F1E_MOD_3_REG_7,
 951   RM_0FAE_REG_6,
 952   RM_0FAE_REG_7
 953 };
 954
 955 enum
 956 {
 957   PREFIX_90 = 0,
 958   PREFIX_MOD_0_0F01_REG_5,
 959   PREFIX_MOD_3_0F01_REG_5_RM_0,
 960   PREFIX_MOD_3_0F01_REG_5_RM_2,
 961   PREFIX_0F10,
 962   PREFIX_0F11,
 963   PREFIX_0F12,
 964   PREFIX_0F16,
 965   PREFIX_0F1A,
 966   PREFIX_0F1B,
 967   PREFIX_0F1E,
 968   PREFIX_0F2A,
 969   PREFIX_0F2B,
 970   PREFIX_0F2C,
 971   PREFIX_0F2D,
 972   PREFIX_0F2E,
 973   PREFIX_0F2F,
 974   PREFIX_0F51,
 975   PREFIX_0F52,
 976   PREFIX_0F53,
 977   PREFIX_0F58,
 978   PREFIX_0F59,
 979   PREFIX_0F5A,
 980   PREFIX_0F5B,
 981   PREFIX_0F5C,
 982   PREFIX_0F5D,
 983   PREFIX_0F5E,
 984   PREFIX_0F5F,
 985   PREFIX_0F60,
 986   PREFIX_0F61,
 987   PREFIX_0F62,
 988   PREFIX_0F6C,
 989   PREFIX_0F6D,
 990   PREFIX_0F6F,
 991   PREFIX_0F70,
 992   PREFIX_0F73_REG_3,
 993   PREFIX_0F73_REG_7,
 994   PREFIX_0F78,
 995   PREFIX_0F79,
 996   PREFIX_0F7C,
 997   PREFIX_0F7D,
 998   PREFIX_0F7E,
 999   PREFIX_0F7F,
1000   PREFIX_0FAE_REG_0,
1001   PREFIX_0FAE_REG_1,
1002   PREFIX_0FAE_REG_2,
1003   PREFIX_0FAE_REG_3,
1004   PREFIX_MOD_0_0FAE_REG_4,
1005   PREFIX_MOD_3_0FAE_REG_4,
1006   PREFIX_MOD_0_0FAE_REG_5,
1007   PREFIX_MOD_3_0FAE_REG_5,
1008   PREFIX_0FAE_REG_6,
1009   PREFIX_0FAE_REG_7,
1010   PREFIX_0FB8,
1011   PREFIX_0FBC,
1012   PREFIX_0FBD,
1013   PREFIX_0FC2,
1014   PREFIX_MOD_0_0FC3,
1015   PREFIX_MOD_0_0FC7_REG_6,
1016   PREFIX_MOD_3_0FC7_REG_6,
1017   PREFIX_MOD_3_0FC7_REG_7,
1018   PREFIX_0FD0,
1019   PREFIX_0FD6,
1020   PREFIX_0FE6,
1021   PREFIX_0FE7,
1022   PREFIX_0FF0,
1023   PREFIX_0FF7,
1024   PREFIX_0F3810,
1025   PREFIX_0F3814,
1026   PREFIX_0F3815,
1027   PREFIX_0F3817,
1028   PREFIX_0F3820,
1029   PREFIX_0F3821,
1030   PREFIX_0F3822,
1031   PREFIX_0F3823,
1032   PREFIX_0F3824,
1033   PREFIX_0F3825,
1034   PREFIX_0F3828,
1035   PREFIX_0F3829,
1036   PREFIX_0F382A,
1037   PREFIX_0F382B,
1038   PREFIX_0F3830,
1039   PREFIX_0F3831,
1040   PREFIX_0F3832,
1041   PREFIX_0F3833,
1042   PREFIX_0F3834,
1043   PREFIX_0F3835,
1044   PREFIX_0F3837,
1045   PREFIX_0F3838,
1046   PREFIX_0F3839,
1047   PREFIX_0F383A,
1048   PREFIX_0F383B,
1049   PREFIX_0F383C,
1050   PREFIX_0F383D,
1051   PREFIX_0F383E,
1052   PREFIX_0F383F,
1053   PREFIX_0F3840,
1054   PREFIX_0F3841,
1055   PREFIX_0F3880,
1056   PREFIX_0F3881,
1057   PREFIX_0F3882,
1058   PREFIX_0F38C8,
1059   PREFIX_0F38C9,
1060   PREFIX_0F38CA,
1061   PREFIX_0F38CB,
1062   PREFIX_0F38CC,
1063   PREFIX_0F38CD,
1064   PREFIX_0F38CF,
1065   PREFIX_0F38DB,
1066   PREFIX_0F38DC,
1067   PREFIX_0F38DD,
1068   PREFIX_0F38DE,
1069   PREFIX_0F38DF,
1070   PREFIX_0F38F0,
1071   PREFIX_0F38F1,
1072   PREFIX_0F38F5,
1073   PREFIX_0F38F6,
1074   PREFIX_0F3A08,
1075   PREFIX_0F3A09,
1076   PREFIX_0F3A0A,
1077   PREFIX_0F3A0B,
1078   PREFIX_0F3A0C,
1079   PREFIX_0F3A0D,
1080   PREFIX_0F3A0E,
1081   PREFIX_0F3A14,
1082   PREFIX_0F3A15,
1083   PREFIX_0F3A16,
1084   PREFIX_0F3A17,
1085   PREFIX_0F3A20,
1086   PREFIX_0F3A21,
1087   PREFIX_0F3A22,
1088   PREFIX_0F3A40,
1089   PREFIX_0F3A41,
1090   PREFIX_0F3A42,
1091   PREFIX_0F3A44,
1092   PREFIX_0F3A60,
1093   PREFIX_0F3A61,
1094   PREFIX_0F3A62,
1095   PREFIX_0F3A63,
1096   PREFIX_0F3ACC,
1097   PREFIX_0F3ACE,
1098   PREFIX_0F3ACF,
1099   PREFIX_0F3ADF,
1100   PREFIX_VEX_0F10,
1101   PREFIX_VEX_0F11,
1102   PREFIX_VEX_0F12,
1103   PREFIX_VEX_0F16,
1104   PREFIX_VEX_0F2A,
1105   PREFIX_VEX_0F2C,
1106   PREFIX_VEX_0F2D,
1107   PREFIX_VEX_0F2E,
1108   PREFIX_VEX_0F2F,
1109   PREFIX_VEX_0F41,
1110   PREFIX_VEX_0F42,
1111   PREFIX_VEX_0F44,
1112   PREFIX_VEX_0F45,
1113   PREFIX_VEX_0F46,
1114   PREFIX_VEX_0F47,
1115   PREFIX_VEX_0F4A,
1116   PREFIX_VEX_0F4B,
1117   PREFIX_VEX_0F51,
1118   PREFIX_VEX_0F52,
1119   PREFIX_VEX_0F53,
1120   PREFIX_VEX_0F58,
1121   PREFIX_VEX_0F59,
1122   PREFIX_VEX_0F5A,
1123   PREFIX_VEX_0F5B,
1124   PREFIX_VEX_0F5C,
1125   PREFIX_VEX_0F5D,
1126   PREFIX_VEX_0F5E,
1127   PREFIX_VEX_0F5F,
1128   PREFIX_VEX_0F60,
1129   PREFIX_VEX_0F61,
1130   PREFIX_VEX_0F62,
1131   PREFIX_VEX_0F63,
1132   PREFIX_VEX_0F64,
1133   PREFIX_VEX_0F65,
1134   PREFIX_VEX_0F66,
1135   PREFIX_VEX_0F67,
1136   PREFIX_VEX_0F68,
1137   PREFIX_VEX_0F69,
1138   PREFIX_VEX_0F6A,
1139   PREFIX_VEX_0F6B,
1140   PREFIX_VEX_0F6C,
1141   PREFIX_VEX_0F6D,
1142   PREFIX_VEX_0F6E,
1143   PREFIX_VEX_0F6F,
1144   PREFIX_VEX_0F70,
1145   PREFIX_VEX_0F71_REG_2,
1146   PREFIX_VEX_0F71_REG_4,
1147   PREFIX_VEX_0F71_REG_6,
1148   PREFIX_VEX_0F72_REG_2,
1149   PREFIX_VEX_0F72_REG_4,
1150   PREFIX_VEX_0F72_REG_6,
1151   PREFIX_VEX_0F73_REG_2,
1152   PREFIX_VEX_0F73_REG_3,
1153   PREFIX_VEX_0F73_REG_6,
1154   PREFIX_VEX_0F73_REG_7,
1155   PREFIX_VEX_0F74,
1156   PREFIX_VEX_0F75,
1157   PREFIX_VEX_0F76,
1158   PREFIX_VEX_0F77,
1159   PREFIX_VEX_0F7C,
1160   PREFIX_VEX_0F7D,
1161   PREFIX_VEX_0F7E,
1162   PREFIX_VEX_0F7F,
1163   PREFIX_VEX_0F90,
1164   PREFIX_VEX_0F91,
1165   PREFIX_VEX_0F92,
1166   PREFIX_VEX_0F93,
1167   PREFIX_VEX_0F98,
1168   PREFIX_VEX_0F99,
1169   PREFIX_VEX_0FC2,
1170   PREFIX_VEX_0FC4,
1171   PREFIX_VEX_0FC5,
1172   PREFIX_VEX_0FD0,
1173   PREFIX_VEX_0FD1,
1174   PREFIX_VEX_0FD2,
1175   PREFIX_VEX_0FD3,
1176   PREFIX_VEX_0FD4,
1177   PREFIX_VEX_0FD5,
1178   PREFIX_VEX_0FD6,
1179   PREFIX_VEX_0FD7,
1180   PREFIX_VEX_0FD8,
1181   PREFIX_VEX_0FD9,
1182   PREFIX_VEX_0FDA,
1183   PREFIX_VEX_0FDB,
1184   PREFIX_VEX_0FDC,
1185   PREFIX_VEX_0FDD,
1186   PREFIX_VEX_0FDE,
1187   PREFIX_VEX_0FDF,
1188   PREFIX_VEX_0FE0,
1189   PREFIX_VEX_0FE1,
1190   PREFIX_VEX_0FE2,
1191   PREFIX_VEX_0FE3,
1192   PREFIX_VEX_0FE4,
1193   PREFIX_VEX_0FE5,
1194   PREFIX_VEX_0FE6,
1195   PREFIX_VEX_0FE7,
1196   PREFIX_VEX_0FE8,
1197   PREFIX_VEX_0FE9,
1198   PREFIX_VEX_0FEA,
1199   PREFIX_VEX_0FEB,
1200   PREFIX_VEX_0FEC,
1201   PREFIX_VEX_0FED,
1202   PREFIX_VEX_0FEE,
1203   PREFIX_VEX_0FEF,
1204   PREFIX_VEX_0FF0,
1205   PREFIX_VEX_0FF1,
1206   PREFIX_VEX_0FF2,
1207   PREFIX_VEX_0FF3,
1208   PREFIX_VEX_0FF4,
1209   PREFIX_VEX_0FF5,
1210   PREFIX_VEX_0FF6,
1211   PREFIX_VEX_0FF7,
1212   PREFIX_VEX_0FF8,
1213   PREFIX_VEX_0FF9,
1214   PREFIX_VEX_0FFA,
1215   PREFIX_VEX_0FFB,
1216   PREFIX_VEX_0FFC,
1217   PREFIX_VEX_0FFD,
1218   PREFIX_VEX_0FFE,
1219   PREFIX_VEX_0F3800,
1220   PREFIX_VEX_0F3801,
1221   PREFIX_VEX_0F3802,
1222   PREFIX_VEX_0F3803,
1223   PREFIX_VEX_0F3804,
1224   PREFIX_VEX_0F3805,
1225   PREFIX_VEX_0F3806,
1226   PREFIX_VEX_0F3807,
1227   PREFIX_VEX_0F3808,
1228   PREFIX_VEX_0F3809,
1229   PREFIX_VEX_0F380A,
1230   PREFIX_VEX_0F380B,
1231   PREFIX_VEX_0F380C,
1232   PREFIX_VEX_0F380D,
1233   PREFIX_VEX_0F380E,
1234   PREFIX_VEX_0F380F,
1235   PREFIX_VEX_0F3813,
1236   PREFIX_VEX_0F3816,
1237   PREFIX_VEX_0F3817,
1238   PREFIX_VEX_0F3818,
1239   PREFIX_VEX_0F3819,
1240   PREFIX_VEX_0F381A,
1241   PREFIX_VEX_0F381C,
1242   PREFIX_VEX_0F381D,
1243   PREFIX_VEX_0F381E,
1244   PREFIX_VEX_0F3820,
1245   PREFIX_VEX_0F3821,
1246   PREFIX_VEX_0F3822,
1247   PREFIX_VEX_0F3823,
1248   PREFIX_VEX_0F3824,
1249   PREFIX_VEX_0F3825,
1250   PREFIX_VEX_0F3828,
1251   PREFIX_VEX_0F3829,
1252   PREFIX_VEX_0F382A,
1253   PREFIX_VEX_0F382B,
1254   PREFIX_VEX_0F382C,
1255   PREFIX_VEX_0F382D,
1256   PREFIX_VEX_0F382E,
1257   PREFIX_VEX_0F382F,
1258   PREFIX_VEX_0F3830,
1259   PREFIX_VEX_0F3831,
1260   PREFIX_VEX_0F3832,
1261   PREFIX_VEX_0F3833,
1262   PREFIX_VEX_0F3834,
1263   PREFIX_VEX_0F3835,
1264   PREFIX_VEX_0F3836,
1265   PREFIX_VEX_0F3837,
1266   PREFIX_VEX_0F3838,
1267   PREFIX_VEX_0F3839,
1268   PREFIX_VEX_0F383A,
1269   PREFIX_VEX_0F383B,
1270   PREFIX_VEX_0F383C,
1271   PREFIX_VEX_0F383D,
1272   PREFIX_VEX_0F383E,
1273   PREFIX_VEX_0F383F,
1274   PREFIX_VEX_0F3840,
1275   PREFIX_VEX_0F3841,
1276   PREFIX_VEX_0F3845,
1277   PREFIX_VEX_0F3846,
1278   PREFIX_VEX_0F3847,
1279   PREFIX_VEX_0F3858,
1280   PREFIX_VEX_0F3859,
1281   PREFIX_VEX_0F385A,
1282   PREFIX_VEX_0F3878,
1283   PREFIX_VEX_0F3879,
1284   PREFIX_VEX_0F388C,
1285   PREFIX_VEX_0F388E,
1286   PREFIX_VEX_0F3890,
1287   PREFIX_VEX_0F3891,
1288   PREFIX_VEX_0F3892,
1289   PREFIX_VEX_0F3893,
1290   PREFIX_VEX_0F3896,
1291   PREFIX_VEX_0F3897,
1292   PREFIX_VEX_0F3898,
1293   PREFIX_VEX_0F3899,
1294   PREFIX_VEX_0F389A,
1295   PREFIX_VEX_0F389B,
1296   PREFIX_VEX_0F389C,
1297   PREFIX_VEX_0F389D,
1298   PREFIX_VEX_0F389E,
1299   PREFIX_VEX_0F389F,
1300   PREFIX_VEX_0F38A6,
1301   PREFIX_VEX_0F38A7,
1302   PREFIX_VEX_0F38A8,
1303   PREFIX_VEX_0F38A9,
1304   PREFIX_VEX_0F38AA,
1305   PREFIX_VEX_0F38AB,
1306   PREFIX_VEX_0F38AC,
1307   PREFIX_VEX_0F38AD,
1308   PREFIX_VEX_0F38AE,
1309   PREFIX_VEX_0F38AF,
1310   PREFIX_VEX_0F38B6,
1311   PREFIX_VEX_0F38B7,
1312   PREFIX_VEX_0F38B8,
1313   PREFIX_VEX_0F38B9,
1314   PREFIX_VEX_0F38BA,
1315   PREFIX_VEX_0F38BB,
1316   PREFIX_VEX_0F38BC,
1317   PREFIX_VEX_0F38BD,
1318   PREFIX_VEX_0F38BE,
1319   PREFIX_VEX_0F38BF,
1320   PREFIX_VEX_0F38CF,
1321   PREFIX_VEX_0F38DB,
1322   PREFIX_VEX_0F38DC,
1323   PREFIX_VEX_0F38DD,
1324   PREFIX_VEX_0F38DE,
1325   PREFIX_VEX_0F38DF,
1326   PREFIX_VEX_0F38F2,
1327   PREFIX_VEX_0F38F3_REG_1,
1328   PREFIX_VEX_0F38F3_REG_2,
1329   PREFIX_VEX_0F38F3_REG_3,
1330   PREFIX_VEX_0F38F5,
1331   PREFIX_VEX_0F38F6,
1332   PREFIX_VEX_0F38F7,
1333   PREFIX_VEX_0F3A00,
1334   PREFIX_VEX_0F3A01,
1335   PREFIX_VEX_0F3A02,
1336   PREFIX_VEX_0F3A04,
1337   PREFIX_VEX_0F3A05,
1338   PREFIX_VEX_0F3A06,
1339   PREFIX_VEX_0F3A08,
1340   PREFIX_VEX_0F3A09,
1341   PREFIX_VEX_0F3A0A,
1342   PREFIX_VEX_0F3A0B,
1343   PREFIX_VEX_0F3A0C,
1344   PREFIX_VEX_0F3A0D,
1345   PREFIX_VEX_0F3A0E,
1346   PREFIX_VEX_0F3A0F,
1347   PREFIX_VEX_0F3A14,
1348   PREFIX_VEX_0F3A15,
1349   PREFIX_VEX_0F3A16,
1350   PREFIX_VEX_0F3A17,
1351   PREFIX_VEX_0F3A18,
1352   PREFIX_VEX_0F3A19,
1353   PREFIX_VEX_0F3A1D,
1354   PREFIX_VEX_0F3A20,
1355   PREFIX_VEX_0F3A21,
1356   PREFIX_VEX_0F3A22,
1357   PREFIX_VEX_0F3A30,
1358   PREFIX_VEX_0F3A31,
1359   PREFIX_VEX_0F3A32,
1360   PREFIX_VEX_0F3A33,
1361   PREFIX_VEX_0F3A38,
1362   PREFIX_VEX_0F3A39,
1363   PREFIX_VEX_0F3A40,
1364   PREFIX_VEX_0F3A41,
1365   PREFIX_VEX_0F3A42,
1366   PREFIX_VEX_0F3A44,
1367   PREFIX_VEX_0F3A46,
1368   PREFIX_VEX_0F3A48,
1369   PREFIX_VEX_0F3A49,
1370   PREFIX_VEX_0F3A4A,
1371   PREFIX_VEX_0F3A4B,
1372   PREFIX_VEX_0F3A4C,
1373   PREFIX_VEX_0F3A5C,
1374   PREFIX_VEX_0F3A5D,
1375   PREFIX_VEX_0F3A5E,
1376   PREFIX_VEX_0F3A5F,
1377   PREFIX_VEX_0F3A60,
1378   PREFIX_VEX_0F3A61,
1379   PREFIX_VEX_0F3A62,
1380   PREFIX_VEX_0F3A63,
1381   PREFIX_VEX_0F3A68,
1382   PREFIX_VEX_0F3A69,
1383   PREFIX_VEX_0F3A6A,
1384   PREFIX_VEX_0F3A6B,
1385   PREFIX_VEX_0F3A6C,
1386   PREFIX_VEX_0F3A6D,
1387   PREFIX_VEX_0F3A6E,
1388   PREFIX_VEX_0F3A6F,
1389   PREFIX_VEX_0F3A78,
1390   PREFIX_VEX_0F3A79,
1391   PREFIX_VEX_0F3A7A,
1392   PREFIX_VEX_0F3A7B,
1393   PREFIX_VEX_0F3A7C,
1394   PREFIX_VEX_0F3A7D,
1395   PREFIX_VEX_0F3A7E,
1396   PREFIX_VEX_0F3A7F,
1397   PREFIX_VEX_0F3ACE,
1398   PREFIX_VEX_0F3ACF,
1399   PREFIX_VEX_0F3ADF,
1400   PREFIX_VEX_0F3AF0,
1401
1402   PREFIX_EVEX_0F10,
1403   PREFIX_EVEX_0F11,
1404   PREFIX_EVEX_0F12,
1405   PREFIX_EVEX_0F13,
1406   PREFIX_EVEX_0F14,
1407   PREFIX_EVEX_0F15,
1408   PREFIX_EVEX_0F16,
1409   PREFIX_EVEX_0F17,
1410   PREFIX_EVEX_0F28,
1411   PREFIX_EVEX_0F29,
1412   PREFIX_EVEX_0F2A,
1413   PREFIX_EVEX_0F2B,
1414   PREFIX_EVEX_0F2C,
1415   PREFIX_EVEX_0F2D,
1416   PREFIX_EVEX_0F2E,
1417   PREFIX_EVEX_0F2F,
1418   PREFIX_EVEX_0F51,
1419   PREFIX_EVEX_0F54,
1420   PREFIX_EVEX_0F55,
1421   PREFIX_EVEX_0F56,
1422   PREFIX_EVEX_0F57,
1423   PREFIX_EVEX_0F58,
1424   PREFIX_EVEX_0F59,
1425   PREFIX_EVEX_0F5A,
1426   PREFIX_EVEX_0F5B,
1427   PREFIX_EVEX_0F5C,
1428   PREFIX_EVEX_0F5D,
1429   PREFIX_EVEX_0F5E,
1430   PREFIX_EVEX_0F5F,
1431   PREFIX_EVEX_0F60,
1432   PREFIX_EVEX_0F61,
1433   PREFIX_EVEX_0F62,
1434   PREFIX_EVEX_0F63,
1435   PREFIX_EVEX_0F64,
1436   PREFIX_EVEX_0F65,
1437   PREFIX_EVEX_0F66,
1438   PREFIX_EVEX_0F67,
1439   PREFIX_EVEX_0F68,
1440   PREFIX_EVEX_0F69,
1441   PREFIX_EVEX_0F6A,
1442   PREFIX_EVEX_0F6B,
1443   PREFIX_EVEX_0F6C,
1444   PREFIX_EVEX_0F6D,
1445   PREFIX_EVEX_0F6E,
1446   PREFIX_EVEX_0F6F,
1447   PREFIX_EVEX_0F70,
1448   PREFIX_EVEX_0F71_REG_2,
1449   PREFIX_EVEX_0F71_REG_4,
1450   PREFIX_EVEX_0F71_REG_6,
1451   PREFIX_EVEX_0F72_REG_0,
1452   PREFIX_EVEX_0F72_REG_1,
1453   PREFIX_EVEX_0F72_REG_2,
1454   PREFIX_EVEX_0F72_REG_4,
1455   PREFIX_EVEX_0F72_REG_6,
1456   PREFIX_EVEX_0F73_REG_2,
1457   PREFIX_EVEX_0F73_REG_3,
1458   PREFIX_EVEX_0F73_REG_6,
1459   PREFIX_EVEX_0F73_REG_7,
1460   PREFIX_EVEX_0F74,
1461   PREFIX_EVEX_0F75,
1462   PREFIX_EVEX_0F76,
1463   PREFIX_EVEX_0F78,
1464   PREFIX_EVEX_0F79,
1465   PREFIX_EVEX_0F7A,
1466   PREFIX_EVEX_0F7B,
1467   PREFIX_EVEX_0F7E,
1468   PREFIX_EVEX_0F7F,
1469   PREFIX_EVEX_0FC2,
1470   PREFIX_EVEX_0FC4,
1471   PREFIX_EVEX_0FC5,
1472   PREFIX_EVEX_0FC6,
1473   PREFIX_EVEX_0FD1,
1474   PREFIX_EVEX_0FD2,
1475   PREFIX_EVEX_0FD3,
1476   PREFIX_EVEX_0FD4,
1477   PREFIX_EVEX_0FD5,
1478   PREFIX_EVEX_0FD6,
1479   PREFIX_EVEX_0FD8,
1480   PREFIX_EVEX_0FD9,
1481   PREFIX_EVEX_0FDA,
1482   PREFIX_EVEX_0FDB,
1483   PREFIX_EVEX_0FDC,
1484   PREFIX_EVEX_0FDD,
1485   PREFIX_EVEX_0FDE,
1486   PREFIX_EVEX_0FDF,
1487   PREFIX_EVEX_0FE0,
1488   PREFIX_EVEX_0FE1,
1489   PREFIX_EVEX_0FE2,
1490   PREFIX_EVEX_0FE3,
1491   PREFIX_EVEX_0FE4,
1492   PREFIX_EVEX_0FE5,
1493   PREFIX_EVEX_0FE6,
1494   PREFIX_EVEX_0FE7,
1495   PREFIX_EVEX_0FE8,
1496   PREFIX_EVEX_0FE9,
1497   PREFIX_EVEX_0FEA,
1498   PREFIX_EVEX_0FEB,
1499   PREFIX_EVEX_0FEC,
1500   PREFIX_EVEX_0FED,
1501   PREFIX_EVEX_0FEE,
1502   PREFIX_EVEX_0FEF,
1503   PREFIX_EVEX_0FF1,
1504   PREFIX_EVEX_0FF2,
1505   PREFIX_EVEX_0FF3,
1506   PREFIX_EVEX_0FF4,
1507   PREFIX_EVEX_0FF5,
1508   PREFIX_EVEX_0FF6,
1509   PREFIX_EVEX_0FF8,
1510   PREFIX_EVEX_0FF9,
1511   PREFIX_EVEX_0FFA,
1512   PREFIX_EVEX_0FFB,
1513   PREFIX_EVEX_0FFC,
1514   PREFIX_EVEX_0FFD,
1515   PREFIX_EVEX_0FFE,
1516   PREFIX_EVEX_0F3800,
1517   PREFIX_EVEX_0F3804,
1518   PREFIX_EVEX_0F380B,
1519   PREFIX_EVEX_0F380C,
1520   PREFIX_EVEX_0F380D,
1521   PREFIX_EVEX_0F3810,
1522   PREFIX_EVEX_0F3811,
1523   PREFIX_EVEX_0F3812,
1524   PREFIX_EVEX_0F3813,
1525   PREFIX_EVEX_0F3814,
1526   PREFIX_EVEX_0F3815,
1527   PREFIX_EVEX_0F3816,
1528   PREFIX_EVEX_0F3818,
1529   PREFIX_EVEX_0F3819,
1530   PREFIX_EVEX_0F381A,
1531   PREFIX_EVEX_0F381B,
1532   PREFIX_EVEX_0F381C,
1533   PREFIX_EVEX_0F381D,
1534   PREFIX_EVEX_0F381E,
1535   PREFIX_EVEX_0F381F,
1536   PREFIX_EVEX_0F3820,
1537   PREFIX_EVEX_0F3821,
1538   PREFIX_EVEX_0F3822,
1539   PREFIX_EVEX_0F3823,
1540   PREFIX_EVEX_0F3824,
1541   PREFIX_EVEX_0F3825,
1542   PREFIX_EVEX_0F3826,
1543   PREFIX_EVEX_0F3827,
1544   PREFIX_EVEX_0F3828,
1545   PREFIX_EVEX_0F3829,
1546   PREFIX_EVEX_0F382A,
1547   PREFIX_EVEX_0F382B,
1548   PREFIX_EVEX_0F382C,
1549   PREFIX_EVEX_0F382D,
1550   PREFIX_EVEX_0F3830,
1551   PREFIX_EVEX_0F3831,
1552   PREFIX_EVEX_0F3832,
1553   PREFIX_EVEX_0F3833,
1554   PREFIX_EVEX_0F3834,
1555   PREFIX_EVEX_0F3835,
1556   PREFIX_EVEX_0F3836,
1557   PREFIX_EVEX_0F3837,
1558   PREFIX_EVEX_0F3838,
1559   PREFIX_EVEX_0F3839,
1560   PREFIX_EVEX_0F383A,
1561   PREFIX_EVEX_0F383B,
1562   PREFIX_EVEX_0F383C,
1563   PREFIX_EVEX_0F383D,
1564   PREFIX_EVEX_0F383E,
1565   PREFIX_EVEX_0F383F,
1566   PREFIX_EVEX_0F3840,
1567   PREFIX_EVEX_0F3842,
1568   PREFIX_EVEX_0F3843,
1569   PREFIX_EVEX_0F3844,
1570   PREFIX_EVEX_0F3845,
1571   PREFIX_EVEX_0F3846,
1572   PREFIX_EVEX_0F3847,
1573   PREFIX_EVEX_0F384C,
1574   PREFIX_EVEX_0F384D,
1575   PREFIX_EVEX_0F384E,
1576   PREFIX_EVEX_0F384F,
1577   PREFIX_EVEX_0F3850,
1578   PREFIX_EVEX_0F3851,
1579   PREFIX_EVEX_0F3852,
1580   PREFIX_EVEX_0F3853,
1581   PREFIX_EVEX_0F3854,
1582   PREFIX_EVEX_0F3855,
1583   PREFIX_EVEX_0F3858,
1584   PREFIX_EVEX_0F3859,
1585   PREFIX_EVEX_0F385A,
1586   PREFIX_EVEX_0F385B,
1587   PREFIX_EVEX_0F3862,
1588   PREFIX_EVEX_0F3863,
1589   PREFIX_EVEX_0F3864,
1590   PREFIX_EVEX_0F3865,
1591   PREFIX_EVEX_0F3866,
1592   PREFIX_EVEX_0F3870,
1593   PREFIX_EVEX_0F3871,
1594   PREFIX_EVEX_0F3872,
1595   PREFIX_EVEX_0F3873,
1596   PREFIX_EVEX_0F3875,
1597   PREFIX_EVEX_0F3876,
1598   PREFIX_EVEX_0F3877,
1599   PREFIX_EVEX_0F3878,
1600   PREFIX_EVEX_0F3879,
1601   PREFIX_EVEX_0F387A,
1602   PREFIX_EVEX_0F387B,
1603   PREFIX_EVEX_0F387C,
1604   PREFIX_EVEX_0F387D,
1605   PREFIX_EVEX_0F387E,
1606   PREFIX_EVEX_0F387F,
1607   PREFIX_EVEX_0F3883,
1608   PREFIX_EVEX_0F3888,
1609   PREFIX_EVEX_0F3889,
1610   PREFIX_EVEX_0F388A,
1611   PREFIX_EVEX_0F388B,
1612   PREFIX_EVEX_0F388D,
1613   PREFIX_EVEX_0F388F,
1614   PREFIX_EVEX_0F3890,
1615   PREFIX_EVEX_0F3891,
1616   PREFIX_EVEX_0F3892,
1617   PREFIX_EVEX_0F3893,
1618   PREFIX_EVEX_0F3896,
1619   PREFIX_EVEX_0F3897,
1620   PREFIX_EVEX_0F3898,
1621   PREFIX_EVEX_0F3899,
1622   PREFIX_EVEX_0F389A,
1623   PREFIX_EVEX_0F389B,
1624   PREFIX_EVEX_0F389C,
1625   PREFIX_EVEX_0F389D,
1626   PREFIX_EVEX_0F389E,
1627   PREFIX_EVEX_0F389F,
1628   PREFIX_EVEX_0F38A0,
1629   PREFIX_EVEX_0F38A1,
1630   PREFIX_EVEX_0F38A2,
1631   PREFIX_EVEX_0F38A3,
1632   PREFIX_EVEX_0F38A6,
1633   PREFIX_EVEX_0F38A7,
1634   PREFIX_EVEX_0F38A8,
1635   PREFIX_EVEX_0F38A9,
1636   PREFIX_EVEX_0F38AA,
1637   PREFIX_EVEX_0F38AB,
1638   PREFIX_EVEX_0F38AC,
1639   PREFIX_EVEX_0F38AD,
1640   PREFIX_EVEX_0F38AE,
1641   PREFIX_EVEX_0F38AF,
1642   PREFIX_EVEX_0F38B4,
1643   PREFIX_EVEX_0F38B5,
1644   PREFIX_EVEX_0F38B6,
1645   PREFIX_EVEX_0F38B7,
1646   PREFIX_EVEX_0F38B8,
1647   PREFIX_EVEX_0F38B9,
1648   PREFIX_EVEX_0F38BA,
1649   PREFIX_EVEX_0F38BB,
1650   PREFIX_EVEX_0F38BC,
1651   PREFIX_EVEX_0F38BD,
1652   PREFIX_EVEX_0F38BE,
1653   PREFIX_EVEX_0F38BF,
1654   PREFIX_EVEX_0F38C4,
1655   PREFIX_EVEX_0F38C6_REG_1,
1656   PREFIX_EVEX_0F38C6_REG_2,
1657   PREFIX_EVEX_0F38C6_REG_5,
1658   PREFIX_EVEX_0F38C6_REG_6,
1659   PREFIX_EVEX_0F38C7_REG_1,
1660   PREFIX_EVEX_0F38C7_REG_2,
1661   PREFIX_EVEX_0F38C7_REG_5,
1662   PREFIX_EVEX_0F38C7_REG_6,
1663   PREFIX_EVEX_0F38C8,
1664   PREFIX_EVEX_0F38CA,
1665   PREFIX_EVEX_0F38CB,
1666   PREFIX_EVEX_0F38CC,
1667   PREFIX_EVEX_0F38CD,
1668   PREFIX_EVEX_0F38CF,
1669   PREFIX_EVEX_0F38DC,
1670   PREFIX_EVEX_0F38DD,
1671   PREFIX_EVEX_0F38DE,
1672   PREFIX_EVEX_0F38DF,
1673
1674   PREFIX_EVEX_0F3A00,
1675   PREFIX_EVEX_0F3A01,
1676   PREFIX_EVEX_0F3A03,
1677   PREFIX_EVEX_0F3A04,
1678   PREFIX_EVEX_0F3A05,
1679   PREFIX_EVEX_0F3A08,
1680   PREFIX_EVEX_0F3A09,
1681   PREFIX_EVEX_0F3A0A,
1682   PREFIX_EVEX_0F3A0B,
1683   PREFIX_EVEX_0F3A0F,
1684   PREFIX_EVEX_0F3A14,
1685   PREFIX_EVEX_0F3A15,
1686   PREFIX_EVEX_0F3A16,
1687   PREFIX_EVEX_0F3A17,
1688   PREFIX_EVEX_0F3A18,
1689   PREFIX_EVEX_0F3A19,
1690   PREFIX_EVEX_0F3A1A,
1691   PREFIX_EVEX_0F3A1B,
1692   PREFIX_EVEX_0F3A1D,
1693   PREFIX_EVEX_0F3A1E,
1694   PREFIX_EVEX_0F3A1F,
1695   PREFIX_EVEX_0F3A20,
1696   PREFIX_EVEX_0F3A21,
1697   PREFIX_EVEX_0F3A22,
1698   PREFIX_EVEX_0F3A23,
1699   PREFIX_EVEX_0F3A25,
1700   PREFIX_EVEX_0F3A26,
1701   PREFIX_EVEX_0F3A27,
1702   PREFIX_EVEX_0F3A38,
1703   PREFIX_EVEX_0F3A39,
1704   PREFIX_EVEX_0F3A3A,
1705   PREFIX_EVEX_0F3A3B,
1706   PREFIX_EVEX_0F3A3E,
1707   PREFIX_EVEX_0F3A3F,
1708   PREFIX_EVEX_0F3A42,
1709   PREFIX_EVEX_0F3A43,
1710   PREFIX_EVEX_0F3A44,
1711   PREFIX_EVEX_0F3A50,
1712   PREFIX_EVEX_0F3A51,
1713   PREFIX_EVEX_0F3A54,
1714   PREFIX_EVEX_0F3A55,
1715   PREFIX_EVEX_0F3A56,
1716   PREFIX_EVEX_0F3A57,
1717   PREFIX_EVEX_0F3A66,
1718   PREFIX_EVEX_0F3A67,
1719   PREFIX_EVEX_0F3A70,
1720   PREFIX_EVEX_0F3A71,
1721   PREFIX_EVEX_0F3A72,
1722   PREFIX_EVEX_0F3A73,
1723   PREFIX_EVEX_0F3ACE,
1724   PREFIX_EVEX_0F3ACF
1725 };
1726
1727 enum
1728 {
1729   X86_64_06 = 0,
1730   X86_64_07,
1731   X86_64_0D,
1732   X86_64_16,
1733   X86_64_17,
1734   X86_64_1E,
1735   X86_64_1F,
1736   X86_64_27,
1737   X86_64_2F,
1738   X86_64_37,
1739   X86_64_3F,
1740   X86_64_60,
1741   X86_64_61,
1742   X86_64_62,
1743   X86_64_63,
1744   X86_64_6D,
1745   X86_64_6F,
1746   X86_64_82,
1747   X86_64_9A,
1748   X86_64_C4,
1749   X86_64_C5,
1750   X86_64_CE,
1751   X86_64_D4,
1752   X86_64_D5,
1753   X86_64_E8,
1754   X86_64_E9,
1755   X86_64_EA,
1756   X86_64_0F01_REG_0,
1757   X86_64_0F01_REG_1,
1758   X86_64_0F01_REG_2,
1759   X86_64_0F01_REG_3
1760 };
1761
1762 enum
1763 {
1764   THREE_BYTE_0F38 = 0,
1765   THREE_BYTE_0F3A
1766 };
1767
1768 enum
1769 {
1770   XOP_08 = 0,
1771   XOP_09,
1772   XOP_0A
1773 };
1774
1775 enum
1776 {
1777   VEX_0F = 0,
1778   VEX_0F38,
1779   VEX_0F3A
1780 };
1781
1782 enum
1783 {
1784   EVEX_0F = 0,
1785   EVEX_0F38,
1786   EVEX_0F3A
1787 };
1788
1789 enum
1790 {
1791   VEX_LEN_0F10_P_1 = 0,
1792   VEX_LEN_0F10_P_3,
1793   VEX_LEN_0F11_P_1,
1794   VEX_LEN_0F11_P_3,
1795   VEX_LEN_0F12_P_0_M_0,
1796   VEX_LEN_0F12_P_0_M_1,
1797   VEX_LEN_0F12_P_2,
1798   VEX_LEN_0F13_M_0,
1799   VEX_LEN_0F16_P_0_M_0,
1800   VEX_LEN_0F16_P_0_M_1,
1801   VEX_LEN_0F16_P_2,
1802   VEX_LEN_0F17_M_0,
1803   VEX_LEN_0F2A_P_1,
1804   VEX_LEN_0F2A_P_3,
1805   VEX_LEN_0F2C_P_1,
1806   VEX_LEN_0F2C_P_3,
1807   VEX_LEN_0F2D_P_1,
1808   VEX_LEN_0F2D_P_3,
1809   VEX_LEN_0F2E_P_0,
1810   VEX_LEN_0F2E_P_2,
1811   VEX_LEN_0F2F_P_0,
1812   VEX_LEN_0F2F_P_2,
1813   VEX_LEN_0F41_P_0,
1814   VEX_LEN_0F41_P_2,
1815   VEX_LEN_0F42_P_0,
1816   VEX_LEN_0F42_P_2,
1817   VEX_LEN_0F44_P_0,
1818   VEX_LEN_0F44_P_2,
1819   VEX_LEN_0F45_P_0,
1820   VEX_LEN_0F45_P_2,
1821   VEX_LEN_0F46_P_0,
1822   VEX_LEN_0F46_P_2,
1823   VEX_LEN_0F47_P_0,
1824   VEX_LEN_0F47_P_2,
1825   VEX_LEN_0F4A_P_0,
1826   VEX_LEN_0F4A_P_2,
1827   VEX_LEN_0F4B_P_0,
1828   VEX_LEN_0F4B_P_2,
1829   VEX_LEN_0F51_P_1,
1830   VEX_LEN_0F51_P_3,
1831   VEX_LEN_0F52_P_1,
1832   VEX_LEN_0F53_P_1,
1833   VEX_LEN_0F58_P_1,
1834   VEX_LEN_0F58_P_3,
1835   VEX_LEN_0F59_P_1,
1836   VEX_LEN_0F59_P_3,
1837   VEX_LEN_0F5A_P_1,
1838   VEX_LEN_0F5A_P_3,
1839   VEX_LEN_0F5C_P_1,
1840   VEX_LEN_0F5C_P_3,
1841   VEX_LEN_0F5D_P_1,
1842   VEX_LEN_0F5D_P_3,
1843   VEX_LEN_0F5E_P_1,
1844   VEX_LEN_0F5E_P_3,
1845   VEX_LEN_0F5F_P_1,
1846   VEX_LEN_0F5F_P_3,
1847   VEX_LEN_0F6E_P_2,
1848   VEX_LEN_0F7E_P_1,
1849   VEX_LEN_0F7E_P_2,
1850   VEX_LEN_0F90_P_0,
1851   VEX_LEN_0F90_P_2,
1852   VEX_LEN_0F91_P_0,
1853   VEX_LEN_0F91_P_2,
1854   VEX_LEN_0F92_P_0,
1855   VEX_LEN_0F92_P_2,
1856   VEX_LEN_0F92_P_3,
1857   VEX_LEN_0F93_P_0,
1858   VEX_LEN_0F93_P_2,
1859   VEX_LEN_0F93_P_3,
1860   VEX_LEN_0F98_P_0,
1861   VEX_LEN_0F98_P_2,
1862   VEX_LEN_0F99_P_0,
1863   VEX_LEN_0F99_P_2,
1864   VEX_LEN_0FAE_R_2_M_0,
1865   VEX_LEN_0FAE_R_3_M_0,
1866   VEX_LEN_0FC2_P_1,
1867   VEX_LEN_0FC2_P_3,
1868   VEX_LEN_0FC4_P_2,
1869   VEX_LEN_0FC5_P_2,
1870   VEX_LEN_0FD6_P_2,
1871   VEX_LEN_0FF7_P_2,
1872   VEX_LEN_0F3816_P_2,
1873   VEX_LEN_0F3819_P_2,
1874   VEX_LEN_0F381A_P_2_M_0,
1875   VEX_LEN_0F3836_P_2,
1876   VEX_LEN_0F3841_P_2,
1877   VEX_LEN_0F385A_P_2_M_0,
1878   VEX_LEN_0F38DB_P_2,
1879   VEX_LEN_0F38F2_P_0,
1880   VEX_LEN_0F38F3_R_1_P_0,
1881   VEX_LEN_0F38F3_R_2_P_0,
1882   VEX_LEN_0F38F3_R_3_P_0,
1883   VEX_LEN_0F38F5_P_0,
1884   VEX_LEN_0F38F5_P_1,
1885   VEX_LEN_0F38F5_P_3,
1886   VEX_LEN_0F38F6_P_3,
1887   VEX_LEN_0F38F7_P_0,
1888   VEX_LEN_0F38F7_P_1,
1889   VEX_LEN_0F38F7_P_2,
1890   VEX_LEN_0F38F7_P_3,
1891   VEX_LEN_0F3A00_P_2,
1892   VEX_LEN_0F3A01_P_2,
1893   VEX_LEN_0F3A06_P_2,
1894   VEX_LEN_0F3A0A_P_2,
1895   VEX_LEN_0F3A0B_P_2,
1896   VEX_LEN_0F3A14_P_2,
1897   VEX_LEN_0F3A15_P_2,
1898   VEX_LEN_0F3A16_P_2,
1899   VEX_LEN_0F3A17_P_2,
1900   VEX_LEN_0F3A18_P_2,
1901   VEX_LEN_0F3A19_P_2,
1902   VEX_LEN_0F3A20_P_2,
1903   VEX_LEN_0F3A21_P_2,
1904   VEX_LEN_0F3A22_P_2,
1905   VEX_LEN_0F3A30_P_2,
1906   VEX_LEN_0F3A31_P_2,
1907   VEX_LEN_0F3A32_P_2,
1908   VEX_LEN_0F3A33_P_2,
1909   VEX_LEN_0F3A38_P_2,
1910   VEX_LEN_0F3A39_P_2,
1911   VEX_LEN_0F3A41_P_2,
1912   VEX_LEN_0F3A46_P_2,
1913   VEX_LEN_0F3A60_P_2,
1914   VEX_LEN_0F3A61_P_2,
1915   VEX_LEN_0F3A62_P_2,
1916   VEX_LEN_0F3A63_P_2,
1917   VEX_LEN_0F3A6A_P_2,
1918   VEX_LEN_0F3A6B_P_2,
1919   VEX_LEN_0F3A6E_P_2,
1920   VEX_LEN_0F3A6F_P_2,
1921   VEX_LEN_0F3A7A_P_2,
1922   VEX_LEN_0F3A7B_P_2,
1923   VEX_LEN_0F3A7E_P_2,
1924   VEX_LEN_0F3A7F_P_2,
1925   VEX_LEN_0F3ADF_P_2,
1926   VEX_LEN_0F3AF0_P_3,
1927   VEX_LEN_0FXOP_08_CC,
1928   VEX_LEN_0FXOP_08_CD,
1929   VEX_LEN_0FXOP_08_CE,
1930   VEX_LEN_0FXOP_08_CF,
1931   VEX_LEN_0FXOP_08_EC,
1932   VEX_LEN_0FXOP_08_ED,
1933   VEX_LEN_0FXOP_08_EE,
1934   VEX_LEN_0FXOP_08_EF,
1935   VEX_LEN_0FXOP_09_80,
1936   VEX_LEN_0FXOP_09_81
1937 };
1938
1939 enum
1940 {
1941   VEX_W_0F10_P_0 = 0,
1942   VEX_W_0F10_P_1,
1943   VEX_W_0F10_P_2,
1944   VEX_W_0F10_P_3,
1945   VEX_W_0F11_P_0,
1946   VEX_W_0F11_P_1,
1947   VEX_W_0F11_P_2,
1948   VEX_W_0F11_P_3,
1949   VEX_W_0F12_P_0_M_0,
1950   VEX_W_0F12_P_0_M_1,
1951   VEX_W_0F12_P_1,
1952   VEX_W_0F12_P_2,
1953   VEX_W_0F12_P_3,
1954   VEX_W_0F13_M_0,
1955   VEX_W_0F14,
1956   VEX_W_0F15,
1957   VEX_W_0F16_P_0_M_0,
1958   VEX_W_0F16_P_0_M_1,
1959   VEX_W_0F16_P_1,
1960   VEX_W_0F16_P_2,
1961   VEX_W_0F17_M_0,
1962   VEX_W_0F28,
1963   VEX_W_0F29,
1964   VEX_W_0F2B_M_0,
1965   VEX_W_0F2E_P_0,
1966   VEX_W_0F2E_P_2,
1967   VEX_W_0F2F_P_0,
1968   VEX_W_0F2F_P_2,
1969   VEX_W_0F41_P_0_LEN_1,
1970   VEX_W_0F41_P_2_LEN_1,
1971   VEX_W_0F42_P_0_LEN_1,
1972   VEX_W_0F42_P_2_LEN_1,
1973   VEX_W_0F44_P_0_LEN_0,
1974   VEX_W_0F44_P_2_LEN_0,
1975   VEX_W_0F45_P_0_LEN_1,
1976   VEX_W_0F45_P_2_LEN_1,
1977   VEX_W_0F46_P_0_LEN_1,
1978   VEX_W_0F46_P_2_LEN_1,
1979   VEX_W_0F47_P_0_LEN_1,
1980   VEX_W_0F47_P_2_LEN_1,
1981   VEX_W_0F4A_P_0_LEN_1,
1982   VEX_W_0F4A_P_2_LEN_1,
1983   VEX_W_0F4B_P_0_LEN_1,
1984   VEX_W_0F4B_P_2_LEN_1,
1985   VEX_W_0F50_M_0,
1986   VEX_W_0F51_P_0,
1987   VEX_W_0F51_P_1,
1988   VEX_W_0F51_P_2,
1989   VEX_W_0F51_P_3,
1990   VEX_W_0F52_P_0,
1991   VEX_W_0F52_P_1,
1992   VEX_W_0F53_P_0,
1993   VEX_W_0F53_P_1,
1994   VEX_W_0F58_P_0,
1995   VEX_W_0F58_P_1,
1996   VEX_W_0F58_P_2,
1997   VEX_W_0F58_P_3,
1998   VEX_W_0F59_P_0,
1999   VEX_W_0F59_P_1,
2000   VEX_W_0F59_P_2,
2001   VEX_W_0F59_P_3,
2002   VEX_W_0F5A_P_0,
2003   VEX_W_0F5A_P_1,
2004   VEX_W_0F5A_P_3,
2005   VEX_W_0F5B_P_0,
2006   VEX_W_0F5B_P_1,
2007   VEX_W_0F5B_P_2,
2008   VEX_W_0F5C_P_0,
2009   VEX_W_0F5C_P_1,
2010   VEX_W_0F5C_P_2,
2011   VEX_W_0F5C_P_3,
2012   VEX_W_0F5D_P_0,
2013   VEX_W_0F5D_P_1,
2014   VEX_W_0F5D_P_2,
2015   VEX_W_0F5D_P_3,
2016   VEX_W_0F5E_P_0,
2017   VEX_W_0F5E_P_1,
2018   VEX_W_0F5E_P_2,
2019   VEX_W_0F5E_P_3,
2020   VEX_W_0F5F_P_0,
2021   VEX_W_0F5F_P_1,
2022   VEX_W_0F5F_P_2,
2023   VEX_W_0F5F_P_3,
2024   VEX_W_0F60_P_2,
2025   VEX_W_0F61_P_2,
2026   VEX_W_0F62_P_2,
2027   VEX_W_0F63_P_2,
2028   VEX_W_0F64_P_2,
2029   VEX_W_0F65_P_2,
2030   VEX_W_0F66_P_2,
2031   VEX_W_0F67_P_2,
2032   VEX_W_0F68_P_2,
2033   VEX_W_0F69_P_2,
2034   VEX_W_0F6A_P_2,
2035   VEX_W_0F6B_P_2,
2036   VEX_W_0F6C_P_2,
2037   VEX_W_0F6D_P_2,
2038   VEX_W_0F6F_P_1,
2039   VEX_W_0F6F_P_2,
2040   VEX_W_0F70_P_1,
2041   VEX_W_0F70_P_2,
2042   VEX_W_0F70_P_3,
2043   VEX_W_0F71_R_2_P_2,
2044   VEX_W_0F71_R_4_P_2,
2045   VEX_W_0F71_R_6_P_2,
2046   VEX_W_0F72_R_2_P_2,
2047   VEX_W_0F72_R_4_P_2,
2048   VEX_W_0F72_R_6_P_2,
2049   VEX_W_0F73_R_2_P_2,
2050   VEX_W_0F73_R_3_P_2,
2051   VEX_W_0F73_R_6_P_2,
2052   VEX_W_0F73_R_7_P_2,
2053   VEX_W_0F74_P_2,
2054   VEX_W_0F75_P_2,
2055   VEX_W_0F76_P_2,
2056   VEX_W_0F77_P_0,
2057   VEX_W_0F7C_P_2,
2058   VEX_W_0F7C_P_3,
2059   VEX_W_0F7D_P_2,
2060   VEX_W_0F7D_P_3,
2061   VEX_W_0F7E_P_1,
2062   VEX_W_0F7F_P_1,
2063   VEX_W_0F7F_P_2,
2064   VEX_W_0F90_P_0_LEN_0,
2065   VEX_W_0F90_P_2_LEN_0,
2066   VEX_W_0F91_P_0_LEN_0,
2067   VEX_W_0F91_P_2_LEN_0,
2068   VEX_W_0F92_P_0_LEN_0,
2069   VEX_W_0F92_P_2_LEN_0,
2070   VEX_W_0F92_P_3_LEN_0,
2071   VEX_W_0F93_P_0_LEN_0,
2072   VEX_W_0F93_P_2_LEN_0,
2073   VEX_W_0F93_P_3_LEN_0,
2074   VEX_W_0F98_P_0_LEN_0,
2075   VEX_W_0F98_P_2_LEN_0,
2076   VEX_W_0F99_P_0_LEN_0,
2077   VEX_W_0F99_P_2_LEN_0,
2078   VEX_W_0FAE_R_2_M_0,
2079   VEX_W_0FAE_R_3_M_0,
2080   VEX_W_0FC2_P_0,
2081   VEX_W_0FC2_P_1,
2082   VEX_W_0FC2_P_2,
2083   VEX_W_0FC2_P_3,
2084   VEX_W_0FC4_P_2,
2085   VEX_W_0FC5_P_2,
2086   VEX_W_0FD0_P_2,
2087   VEX_W_0FD0_P_3,
2088   VEX_W_0FD1_P_2,
2089   VEX_W_0FD2_P_2,
2090   VEX_W_0FD3_P_2,
2091   VEX_W_0FD4_P_2,
2092   VEX_W_0FD5_P_2,
2093   VEX_W_0FD6_P_2,
2094   VEX_W_0FD7_P_2_M_1,
2095   VEX_W_0FD8_P_2,
2096   VEX_W_0FD9_P_2,
2097   VEX_W_0FDA_P_2,
2098   VEX_W_0FDB_P_2,
2099   VEX_W_0FDC_P_2,
2100   VEX_W_0FDD_P_2,
2101   VEX_W_0FDE_P_2,
2102   VEX_W_0FDF_P_2,
2103   VEX_W_0FE0_P_2,
2104   VEX_W_0FE1_P_2,
2105   VEX_W_0FE2_P_2,
2106   VEX_W_0FE3_P_2,
2107   VEX_W_0FE4_P_2,
2108   VEX_W_0FE5_P_2,
2109   VEX_W_0FE6_P_1,
2110   VEX_W_0FE6_P_2,
2111   VEX_W_0FE6_P_3,
2112   VEX_W_0FE7_P_2_M_0,
2113   VEX_W_0FE8_P_2,
2114   VEX_W_0FE9_P_2,
2115   VEX_W_0FEA_P_2,
2116   VEX_W_0FEB_P_2,
2117   VEX_W_0FEC_P_2,
2118   VEX_W_0FED_P_2,
2119   VEX_W_0FEE_P_2,
2120   VEX_W_0FEF_P_2,
2121   VEX_W_0FF0_P_3_M_0,
2122   VEX_W_0FF1_P_2,
2123   VEX_W_0FF2_P_2,
2124   VEX_W_0FF3_P_2,
2125   VEX_W_0FF4_P_2,
2126   VEX_W_0FF5_P_2,
2127   VEX_W_0FF6_P_2,
2128   VEX_W_0FF7_P_2,
2129   VEX_W_0FF8_P_2,
2130   VEX_W_0FF9_P_2,
2131   VEX_W_0FFA_P_2,
2132   VEX_W_0FFB_P_2,
2133   VEX_W_0FFC_P_2,
2134   VEX_W_0FFD_P_2,
2135   VEX_W_0FFE_P_2,
2136   VEX_W_0F3800_P_2,
2137   VEX_W_0F3801_P_2,
2138   VEX_W_0F3802_P_2,
2139   VEX_W_0F3803_P_2,
2140   VEX_W_0F3804_P_2,
2141   VEX_W_0F3805_P_2,
2142   VEX_W_0F3806_P_2,
2143   VEX_W_0F3807_P_2,
2144   VEX_W_0F3808_P_2,
2145   VEX_W_0F3809_P_2,
2146   VEX_W_0F380A_P_2,
2147   VEX_W_0F380B_P_2,
2148   VEX_W_0F380C_P_2,
2149   VEX_W_0F380D_P_2,
2150   VEX_W_0F380E_P_2,
2151   VEX_W_0F380F_P_2,
2152   VEX_W_0F3816_P_2,
2153   VEX_W_0F3817_P_2,
2154   VEX_W_0F3818_P_2,
2155   VEX_W_0F3819_P_2,
2156   VEX_W_0F381A_P_2_M_0,
2157   VEX_W_0F381C_P_2,
2158   VEX_W_0F381D_P_2,
2159   VEX_W_0F381E_P_2,
2160   VEX_W_0F3820_P_2,
2161   VEX_W_0F3821_P_2,
2162   VEX_W_0F3822_P_2,
2163   VEX_W_0F3823_P_2,
2164   VEX_W_0F3824_P_2,
2165   VEX_W_0F3825_P_2,
2166   VEX_W_0F3828_P_2,
2167   VEX_W_0F3829_P_2,
2168   VEX_W_0F382A_P_2_M_0,
2169   VEX_W_0F382B_P_2,
2170   VEX_W_0F382C_P_2_M_0,
2171   VEX_W_0F382D_P_2_M_0,
2172   VEX_W_0F382E_P_2_M_0,
2173   VEX_W_0F382F_P_2_M_0,
2174   VEX_W_0F3830_P_2,
2175   VEX_W_0F3831_P_2,
2176   VEX_W_0F3832_P_2,
2177   VEX_W_0F3833_P_2,
2178   VEX_W_0F3834_P_2,
2179   VEX_W_0F3835_P_2,
2180   VEX_W_0F3836_P_2,
2181   VEX_W_0F3837_P_2,
2182   VEX_W_0F3838_P_2,
2183   VEX_W_0F3839_P_2,
2184   VEX_W_0F383A_P_2,
2185   VEX_W_0F383B_P_2,
2186   VEX_W_0F383C_P_2,
2187   VEX_W_0F383D_P_2,
2188   VEX_W_0F383E_P_2,
2189   VEX_W_0F383F_P_2,
2190   VEX_W_0F3840_P_2,
2191   VEX_W_0F3841_P_2,
2192   VEX_W_0F3846_P_2,
2193   VEX_W_0F3858_P_2,
2194   VEX_W_0F3859_P_2,
2195   VEX_W_0F385A_P_2_M_0,
2196   VEX_W_0F3878_P_2,
2197   VEX_W_0F3879_P_2,
2198   VEX_W_0F38CF_P_2,
2199   VEX_W_0F38DB_P_2,
2200   VEX_W_0F3A00_P_2,
2201   VEX_W_0F3A01_P_2,
2202   VEX_W_0F3A02_P_2,
2203   VEX_W_0F3A04_P_2,
2204   VEX_W_0F3A05_P_2,
2205   VEX_W_0F3A06_P_2,
2206   VEX_W_0F3A08_P_2,
2207   VEX_W_0F3A09_P_2,
2208   VEX_W_0F3A0A_P_2,
2209   VEX_W_0F3A0B_P_2,
2210   VEX_W_0F3A0C_P_2,
2211   VEX_W_0F3A0D_P_2,
2212   VEX_W_0F3A0E_P_2,
2213   VEX_W_0F3A0F_P_2,
2214   VEX_W_0F3A14_P_2,
2215   VEX_W_0F3A15_P_2,
2216   VEX_W_0F3A18_P_2,
2217   VEX_W_0F3A19_P_2,
2218   VEX_W_0F3A20_P_2,
2219   VEX_W_0F3A21_P_2,
2220   VEX_W_0F3A30_P_2_LEN_0,
2221   VEX_W_0F3A31_P_2_LEN_0,
2222   VEX_W_0F3A32_P_2_LEN_0,
2223   VEX_W_0F3A33_P_2_LEN_0,
2224   VEX_W_0F3A38_P_2,
2225   VEX_W_0F3A39_P_2,
2226   VEX_W_0F3A40_P_2,
2227   VEX_W_0F3A41_P_2,
2228   VEX_W_0F3A42_P_2,
2229   VEX_W_0F3A46_P_2,
2230   VEX_W_0F3A48_P_2,
2231   VEX_W_0F3A49_P_2,
2232   VEX_W_0F3A4A_P_2,
2233   VEX_W_0F3A4B_P_2,
2234   VEX_W_0F3A4C_P_2,
2235   VEX_W_0F3A62_P_2,
2236   VEX_W_0F3A63_P_2,
2237   VEX_W_0F3ACE_P_2,
2238   VEX_W_0F3ACF_P_2,
2239   VEX_W_0F3ADF_P_2,
2240
2241   EVEX_W_0F10_P_0,
2242   EVEX_W_0F10_P_1_M_0,
2243   EVEX_W_0F10_P_1_M_1,
2244   EVEX_W_0F10_P_2,
2245   EVEX_W_0F10_P_3_M_0,
2246   EVEX_W_0F10_P_3_M_1,
2247   EVEX_W_0F11_P_0,
2248   EVEX_W_0F11_P_1_M_0,
2249   EVEX_W_0F11_P_1_M_1,
2250   EVEX_W_0F11_P_2,
2251   EVEX_W_0F11_P_3_M_0,
2252   EVEX_W_0F11_P_3_M_1,
2253   EVEX_W_0F12_P_0_M_0,
2254   EVEX_W_0F12_P_0_M_1,
2255   EVEX_W_0F12_P_1,
2256   EVEX_W_0F12_P_2,
2257   EVEX_W_0F12_P_3,
2258   EVEX_W_0F13_P_0,
2259   EVEX_W_0F13_P_2,
2260   EVEX_W_0F14_P_0,
2261   EVEX_W_0F14_P_2,
2262   EVEX_W_0F15_P_0,
2263   EVEX_W_0F15_P_2,
2264   EVEX_W_0F16_P_0_M_0,
2265   EVEX_W_0F16_P_0_M_1,
2266   EVEX_W_0F16_P_1,
2267   EVEX_W_0F16_P_2,
2268   EVEX_W_0F17_P_0,
2269   EVEX_W_0F17_P_2,
2270   EVEX_W_0F28_P_0,
2271   EVEX_W_0F28_P_2,
2272   EVEX_W_0F29_P_0,
2273   EVEX_W_0F29_P_2,
2274   EVEX_W_0F2A_P_1,
2275   EVEX_W_0F2A_P_3,
2276   EVEX_W_0F2B_P_0,
2277   EVEX_W_0F2B_P_2,
2278   EVEX_W_0F2E_P_0,
2279   EVEX_W_0F2E_P_2,
2280   EVEX_W_0F2F_P_0,
2281   EVEX_W_0F2F_P_2,
2282   EVEX_W_0F51_P_0,
2283   EVEX_W_0F51_P_1,
2284   EVEX_W_0F51_P_2,
2285   EVEX_W_0F51_P_3,
2286   EVEX_W_0F54_P_0,
2287   EVEX_W_0F54_P_2,
2288   EVEX_W_0F55_P_0,
2289   EVEX_W_0F55_P_2,
2290   EVEX_W_0F56_P_0,
2291   EVEX_W_0F56_P_2,
2292   EVEX_W_0F57_P_0,
2293   EVEX_W_0F57_P_2,
2294   EVEX_W_0F58_P_0,
2295   EVEX_W_0F58_P_1,
2296   EVEX_W_0F58_P_2,
2297   EVEX_W_0F58_P_3,
2298   EVEX_W_0F59_P_0,
2299   EVEX_W_0F59_P_1,
2300   EVEX_W_0F59_P_2,
2301   EVEX_W_0F59_P_3,
2302   EVEX_W_0F5A_P_0,
2303   EVEX_W_0F5A_P_1,
2304   EVEX_W_0F5A_P_2,
2305   EVEX_W_0F5A_P_3,
2306   EVEX_W_0F5B_P_0,
2307   EVEX_W_0F5B_P_1,
2308   EVEX_W_0F5B_P_2,
2309   EVEX_W_0F5C_P_0,
2310   EVEX_W_0F5C_P_1,
2311   EVEX_W_0F5C_P_2,
2312   EVEX_W_0F5C_P_3,
2313   EVEX_W_0F5D_P_0,
2314   EVEX_W_0F5D_P_1,
2315   EVEX_W_0F5D_P_2,
2316   EVEX_W_0F5D_P_3,
2317   EVEX_W_0F5E_P_0,
2318   EVEX_W_0F5E_P_1,
2319   EVEX_W_0F5E_P_2,
2320   EVEX_W_0F5E_P_3,
2321   EVEX_W_0F5F_P_0,
2322   EVEX_W_0F5F_P_1,
2323   EVEX_W_0F5F_P_2,
2324   EVEX_W_0F5F_P_3,
2325   EVEX_W_0F62_P_2,
2326   EVEX_W_0F66_P_2,
2327   EVEX_W_0F6A_P_2,
2328   EVEX_W_0F6B_P_2,
2329   EVEX_W_0F6C_P_2,
2330   EVEX_W_0F6D_P_2,
2331   EVEX_W_0F6E_P_2,
2332   EVEX_W_0F6F_P_1,
2333   EVEX_W_0F6F_P_2,
2334   EVEX_W_0F6F_P_3,
2335   EVEX_W_0F70_P_2,
2336   EVEX_W_0F72_R_2_P_2,
2337   EVEX_W_0F72_R_6_P_2,
2338   EVEX_W_0F73_R_2_P_2,
2339   EVEX_W_0F73_R_6_P_2,
2340   EVEX_W_0F76_P_2,
2341   EVEX_W_0F78_P_0,
2342   EVEX_W_0F78_P_2,
2343   EVEX_W_0F79_P_0,
2344   EVEX_W_0F79_P_2,
2345   EVEX_W_0F7A_P_1,
2346   EVEX_W_0F7A_P_2,
2347   EVEX_W_0F7A_P_3,
2348   EVEX_W_0F7B_P_1,
2349   EVEX_W_0F7B_P_2,
2350   EVEX_W_0F7B_P_3,
2351   EVEX_W_0F7E_P_1,
2352   EVEX_W_0F7E_P_2,
2353   EVEX_W_0F7F_P_1,
2354   EVEX_W_0F7F_P_2,
2355   EVEX_W_0F7F_P_3,
2356   EVEX_W_0FC2_P_0,
2357   EVEX_W_0FC2_P_1,
2358   EVEX_W_0FC2_P_2,
2359   EVEX_W_0FC2_P_3,
2360   EVEX_W_0FC6_P_0,
2361   EVEX_W_0FC6_P_2,
2362   EVEX_W_0FD2_P_2,
2363   EVEX_W_0FD3_P_2,
2364   EVEX_W_0FD4_P_2,
2365   EVEX_W_0FD6_P_2,
2366   EVEX_W_0FE6_P_1,
2367   EVEX_W_0FE6_P_2,
2368   EVEX_W_0FE6_P_3,
2369   EVEX_W_0FE7_P_2,
2370   EVEX_W_0FF2_P_2,
2371   EVEX_W_0FF3_P_2,
2372   EVEX_W_0FF4_P_2,
2373   EVEX_W_0FFA_P_2,
2374   EVEX_W_0FFB_P_2,
2375   EVEX_W_0FFE_P_2,
2376   EVEX_W_0F380C_P_2,
2377   EVEX_W_0F380D_P_2,
2378   EVEX_W_0F3810_P_1,
2379   EVEX_W_0F3810_P_2,
2380   EVEX_W_0F3811_P_1,
2381   EVEX_W_0F3811_P_2,
2382   EVEX_W_0F3812_P_1,
2383   EVEX_W_0F3812_P_2,
2384   EVEX_W_0F3813_P_1,
2385   EVEX_W_0F3813_P_2,
2386   EVEX_W_0F3814_P_1,
2387   EVEX_W_0F3815_P_1,
2388   EVEX_W_0F3818_P_2,
2389   EVEX_W_0F3819_P_2,
2390   EVEX_W_0F381A_P_2,
2391   EVEX_W_0F381B_P_2,
2392   EVEX_W_0F381E_P_2,
2393   EVEX_W_0F381F_P_2,
2394   EVEX_W_0F3820_P_1,
2395   EVEX_W_0F3821_P_1,
2396   EVEX_W_0F3822_P_1,
2397   EVEX_W_0F3823_P_1,
2398   EVEX_W_0F3824_P_1,
2399   EVEX_W_0F3825_P_1,
2400   EVEX_W_0F3825_P_2,
2401   EVEX_W_0F3826_P_1,
2402   EVEX_W_0F3826_P_2,
2403   EVEX_W_0F3828_P_1,
2404   EVEX_W_0F3828_P_2,
2405   EVEX_W_0F3829_P_1,
2406   EVEX_W_0F3829_P_2,
2407   EVEX_W_0F382A_P_1,
2408   EVEX_W_0F382A_P_2,
2409   EVEX_W_0F382B_P_2,
2410   EVEX_W_0F3830_P_1,
2411   EVEX_W_0F3831_P_1,
2412   EVEX_W_0F3832_P_1,
2413   EVEX_W_0F3833_P_1,
2414   EVEX_W_0F3834_P_1,
2415   EVEX_W_0F3835_P_1,
2416   EVEX_W_0F3835_P_2,
2417   EVEX_W_0F3837_P_2,
2418   EVEX_W_0F3838_P_1,
2419   EVEX_W_0F3839_P_1,
2420   EVEX_W_0F383A_P_1,
2421   EVEX_W_0F3840_P_2,
2422   EVEX_W_0F3854_P_2,
2423   EVEX_W_0F3855_P_2,
2424   EVEX_W_0F3858_P_2,
2425   EVEX_W_0F3859_P_2,
2426   EVEX_W_0F385A_P_2,
2427   EVEX_W_0F385B_P_2,
2428   EVEX_W_0F3862_P_2,
2429   EVEX_W_0F3863_P_2,
2430   EVEX_W_0F3866_P_2,
2431   EVEX_W_0F3870_P_2,
2432   EVEX_W_0F3871_P_2,
2433   EVEX_W_0F3872_P_2,
2434   EVEX_W_0F3873_P_2,
2435   EVEX_W_0F3875_P_2,
2436   EVEX_W_0F3878_P_2,
2437   EVEX_W_0F3879_P_2,
2438   EVEX_W_0F387A_P_2,
2439   EVEX_W_0F387B_P_2,
2440   EVEX_W_0F387D_P_2,
2441   EVEX_W_0F3883_P_2,
2442   EVEX_W_0F388D_P_2,
2443   EVEX_W_0F3891_P_2,
2444   EVEX_W_0F3893_P_2,
2445   EVEX_W_0F38A1_P_2,
2446   EVEX_W_0F38A3_P_2,
2447   EVEX_W_0F38C7_R_1_P_2,
2448   EVEX_W_0F38C7_R_2_P_2,
2449   EVEX_W_0F38C7_R_5_P_2,
2450   EVEX_W_0F38C7_R_6_P_2,
2451
2452   EVEX_W_0F3A00_P_2,
2453   EVEX_W_0F3A01_P_2,
2454   EVEX_W_0F3A04_P_2,
2455   EVEX_W_0F3A05_P_2,
2456   EVEX_W_0F3A08_P_2,
2457   EVEX_W_0F3A09_P_2,
2458   EVEX_W_0F3A0A_P_2,
2459   EVEX_W_0F3A0B_P_2,
2460   EVEX_W_0F3A16_P_2,
2461   EVEX_W_0F3A18_P_2,
2462   EVEX_W_0F3A19_P_2,
2463   EVEX_W_0F3A1A_P_2,
2464   EVEX_W_0F3A1B_P_2,
2465   EVEX_W_0F3A1D_P_2,
2466   EVEX_W_0F3A21_P_2,
2467   EVEX_W_0F3A22_P_2,
2468   EVEX_W_0F3A23_P_2,
2469   EVEX_W_0F3A38_P_2,
2470   EVEX_W_0F3A39_P_2,
2471   EVEX_W_0F3A3A_P_2,
2472   EVEX_W_0F3A3B_P_2,
2473   EVEX_W_0F3A3E_P_2,
2474   EVEX_W_0F3A3F_P_2,
2475   EVEX_W_0F3A42_P_2,
2476   EVEX_W_0F3A43_P_2,
2477   EVEX_W_0F3A50_P_2,
2478   EVEX_W_0F3A51_P_2,
2479   EVEX_W_0F3A56_P_2,
2480   EVEX_W_0F3A57_P_2,
2481   EVEX_W_0F3A66_P_2,
2482   EVEX_W_0F3A67_P_2,
2483   EVEX_W_0F3A70_P_2,
2484   EVEX_W_0F3A71_P_2,
2485   EVEX_W_0F3A72_P_2,
2486   EVEX_W_0F3A73_P_2,
2487   EVEX_W_0F3ACE_P_2,
2488   EVEX_W_0F3ACF_P_2
2489 };
2490
2491 typedef void (*op_rtn) (int bytemode, int sizeflag);
2492
2493 struct dis386 {
2494   const char *name;
2495   struct
2496     {
2497       op_rtn rtn;
2498       int bytemode;
2499     } op[MAX_OPERANDS];
2500   unsigned int prefix_requirement;
2501 };
2502
2503 /* Upper case letters in the instruction names here are macros.
2504    'A' => print 'b' if no register operands or suffix_always is true
2505    'B' => print 'b' if suffix_always is true
2506    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2507           size prefix
2508    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2509           suffix_always is true
2510    'E' => print 'e' if 32-bit form of jcxz
2511    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2512    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2513    'H' => print ",pt" or ",pn" branch hint
2514    'I' => honor following macro letter even in Intel mode (implemented only
2515           for some of the macro letters)
2516    'J' => print 'l'
2517    'K' => print 'd' or 'q' if rex prefix is present.
2518    'L' => print 'l' if suffix_always is true
2519    'M' => print 'r' if intel_mnemonic is false.
2520    'N' => print 'n' if instruction has no wait "prefix"
2521    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2522    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2523           or suffix_always is true.  print 'q' if rex prefix is present.
2524    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2525           is true
2526    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2527    'S' => print 'w', 'l' or 'q' if suffix_always is true
2528    'T' => print 'q' in 64bit mode if instruction has no operand size
2529           prefix and behave as 'P' otherwise
2530    'U' => print 'q' in 64bit mode if instruction has no operand size
2531           prefix and behave as 'Q' otherwise
2532    'V' => print 'q' in 64bit mode if instruction has no operand size
2533           prefix and behave as 'S' otherwise
2534    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2535    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2536    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2537           suffix_always is true.
2538    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2539    '!' => change condition from true to false or from false to true.
2540    '%' => add 1 upper case letter to the macro.
2541    '^' => print 'w' or 'l' depending on operand size prefix or
2542           suffix_always is true (lcall/ljmp).
2543    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2544           on operand size prefix.
2545    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2546           has no operand size prefix for AMD64 ISA, behave as 'P'
2547           otherwise
2548
2549    2 upper case letter macros:
2550    "XY" => print 'x' or 'y' if suffix_always is true or no register
2551            operands and no broadcast.
2552    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2553            register operands and no broadcast.
2554    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2555    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2556            or suffix_always is true
2557    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2558    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2559    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2560    "LW" => print 'd', 'q' depending on the VEX.W bit
2561    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2562            an operand size prefix, or suffix_always is true.  print
2563            'q' if rex prefix is present.
2564
2565    Many of the above letters print nothing in Intel mode.  See "putop"
2566    for the details.
2567
2568    Braces '{' and '}', and vertical bars '|', indicate alternative
2569    mnemonic strings for AT&T and Intel.  */
2570
2571 static const struct dis386 dis386[] = {
2572   /* 00 */
2573   { "addB",             { Ebh1, Gb }, 0 },
2574   { "addS",             { Evh1, Gv }, 0 },
2575   { "addB",             { Gb, EbS }, 0 },
2576   { "addS",             { Gv, EvS }, 0 },
2577   { "addB",             { AL, Ib }, 0 },
2578   { "addS",             { eAX, Iv }, 0 },
2579   { X86_64_TABLE (X86_64_06) },
2580   { X86_64_TABLE (X86_64_07) },
2581   /* 08 */
2582   { "orB",              { Ebh1, Gb }, 0 },
2583   { "orS",              { Evh1, Gv }, 0 },
2584   { "orB",              { Gb, EbS }, 0 },
2585   { "orS",              { Gv, EvS }, 0 },
2586   { "orB",              { AL, Ib }, 0 },
2587   { "orS",              { eAX, Iv }, 0 },
2588   { X86_64_TABLE (X86_64_0D) },
2589   { Bad_Opcode },       /* 0x0f extended opcode escape */
2590   /* 10 */
2591   { "adcB",             { Ebh1, Gb }, 0 },
2592   { "adcS",             { Evh1, Gv }, 0 },
2593   { "adcB",             { Gb, EbS }, 0 },
2594   { "adcS",             { Gv, EvS }, 0 },
2595   { "adcB",             { AL, Ib }, 0 },
2596   { "adcS",             { eAX, Iv }, 0 },
2597   { X86_64_TABLE (X86_64_16) },
2598   { X86_64_TABLE (X86_64_17) },
2599   /* 18 */
2600   { "sbbB",             { Ebh1, Gb }, 0 },
2601   { "sbbS",             { Evh1, Gv }, 0 },
2602   { "sbbB",             { Gb, EbS }, 0 },
2603   { "sbbS",             { Gv, EvS }, 0 },
2604   { "sbbB",             { AL, Ib }, 0 },
2605   { "sbbS",             { eAX, Iv }, 0 },
2606   { X86_64_TABLE (X86_64_1E) },
2607   { X86_64_TABLE (X86_64_1F) },
2608   /* 20 */
2609   { "andB",             { Ebh1, Gb }, 0 },
2610   { "andS",             { Evh1, Gv }, 0 },
2611   { "andB",             { Gb, EbS }, 0 },
2612   { "andS",             { Gv, EvS }, 0 },
2613   { "andB",             { AL, Ib }, 0 },
2614   { "andS",             { eAX, Iv }, 0 },
2615   { Bad_Opcode },       /* SEG ES prefix */
2616   { X86_64_TABLE (X86_64_27) },
2617   /* 28 */
2618   { "subB",             { Ebh1, Gb }, 0 },
2619   { "subS",             { Evh1, Gv }, 0 },
2620   { "subB",             { Gb, EbS }, 0 },
2621   { "subS",             { Gv, EvS }, 0 },
2622   { "subB",             { AL, Ib }, 0 },
2623   { "subS",             { eAX, Iv }, 0 },
2624   { Bad_Opcode },       /* SEG CS prefix */
2625   { X86_64_TABLE (X86_64_2F) },
2626   /* 30 */
2627   { "xorB",             { Ebh1, Gb }, 0 },
2628   { "xorS",             { Evh1, Gv }, 0 },
2629   { "xorB",             { Gb, EbS }, 0 },
2630   { "xorS",             { Gv, EvS }, 0 },
2631   { "xorB",             { AL, Ib }, 0 },
2632   { "xorS",             { eAX, Iv }, 0 },
2633   { Bad_Opcode },       /* SEG SS prefix */
2634   { X86_64_TABLE (X86_64_37) },
2635   /* 38 */
2636   { "cmpB",             { Eb, Gb }, 0 },
2637   { "cmpS",             { Ev, Gv }, 0 },
2638   { "cmpB",             { Gb, EbS }, 0 },
2639   { "cmpS",             { Gv, EvS }, 0 },
2640   { "cmpB",             { AL, Ib }, 0 },
2641   { "cmpS",             { eAX, Iv }, 0 },
2642   { Bad_Opcode },       /* SEG DS prefix */
2643   { X86_64_TABLE (X86_64_3F) },
2644   /* 40 */
2645   { "inc{S|}",          { RMeAX }, 0 },
2646   { "inc{S|}",          { RMeCX }, 0 },
2647   { "inc{S|}",          { RMeDX }, 0 },
2648   { "inc{S|}",          { RMeBX }, 0 },
2649   { "inc{S|}",          { RMeSP }, 0 },
2650   { "inc{S|}",          { RMeBP }, 0 },
2651   { "inc{S|}",          { RMeSI }, 0 },
2652   { "inc{S|}",          { RMeDI }, 0 },
2653   /* 48 */
2654   { "dec{S|}",          { RMeAX }, 0 },
2655   { "dec{S|}",          { RMeCX }, 0 },
2656   { "dec{S|}",          { RMeDX }, 0 },
2657   { "dec{S|}",          { RMeBX }, 0 },
2658   { "dec{S|}",          { RMeSP }, 0 },
2659   { "dec{S|}",          { RMeBP }, 0 },
2660   { "dec{S|}",          { RMeSI }, 0 },
2661   { "dec{S|}",          { RMeDI }, 0 },
2662   /* 50 */
2663   { "pushV",            { RMrAX }, 0 },
2664   { "pushV",            { RMrCX }, 0 },
2665   { "pushV",            { RMrDX }, 0 },
2666   { "pushV",            { RMrBX }, 0 },
2667   { "pushV",            { RMrSP }, 0 },
2668   { "pushV",            { RMrBP }, 0 },
2669   { "pushV",            { RMrSI }, 0 },
2670   { "pushV",            { RMrDI }, 0 },
2671   /* 58 */
2672   { "popV",             { RMrAX }, 0 },
2673   { "popV",             { RMrCX }, 0 },
2674   { "popV",             { RMrDX }, 0 },
2675   { "popV",             { RMrBX }, 0 },
2676   { "popV",             { RMrSP }, 0 },
2677   { "popV",             { RMrBP }, 0 },
2678   { "popV",             { RMrSI }, 0 },
2679   { "popV",             { RMrDI }, 0 },
2680   /* 60 */
2681   { X86_64_TABLE (X86_64_60) },
2682   { X86_64_TABLE (X86_64_61) },
2683   { X86_64_TABLE (X86_64_62) },
2684   { X86_64_TABLE (X86_64_63) },
2685   { Bad_Opcode },       /* seg fs */
2686   { Bad_Opcode },       /* seg gs */
2687   { Bad_Opcode },       /* op size prefix */
2688   { Bad_Opcode },       /* adr size prefix */
2689   /* 68 */
2690   { "pushT",            { sIv }, 0 },
2691   { "imulS",            { Gv, Ev, Iv }, 0 },
2692   { "pushT",            { sIbT }, 0 },
2693   { "imulS",            { Gv, Ev, sIb }, 0 },
2694   { "ins{b|}",          { Ybr, indirDX }, 0 },
2695   { X86_64_TABLE (X86_64_6D) },
2696   { "outs{b|}",         { indirDXr, Xb }, 0 },
2697   { X86_64_TABLE (X86_64_6F) },
2698   /* 70 */
2699   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2700   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2701   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2702   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2703   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2704   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2705   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2706   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2707   /* 78 */
2708   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2709   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2710   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2711   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2712   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2713   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2714   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2715   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2716   /* 80 */
2717   { REG_TABLE (REG_80) },
2718   { REG_TABLE (REG_81) },
2719   { X86_64_TABLE (X86_64_82) },
2720   { REG_TABLE (REG_83) },
2721   { "testB",            { Eb, Gb }, 0 },
2722   { "testS",            { Ev, Gv }, 0 },
2723   { "xchgB",            { Ebh2, Gb }, 0 },
2724   { "xchgS",            { Evh2, Gv }, 0 },
2725   /* 88 */
2726   { "movB",             { Ebh3, Gb }, 0 },
2727   { "movS",             { Evh3, Gv }, 0 },
2728   { "movB",             { Gb, EbS }, 0 },
2729   { "movS",             { Gv, EvS }, 0 },
2730   { "movD",             { Sv, Sw }, 0 },
2731   { MOD_TABLE (MOD_8D) },
2732   { "movD",             { Sw, Sv }, 0 },
2733   { REG_TABLE (REG_8F) },
2734   /* 90 */
2735   { PREFIX_TABLE (PREFIX_90) },
2736   { "xchgS",            { RMeCX, eAX }, 0 },
2737   { "xchgS",            { RMeDX, eAX }, 0 },
2738   { "xchgS",            { RMeBX, eAX }, 0 },
2739   { "xchgS",            { RMeSP, eAX }, 0 },
2740   { "xchgS",            { RMeBP, eAX }, 0 },
2741   { "xchgS",            { RMeSI, eAX }, 0 },
2742   { "xchgS",            { RMeDI, eAX }, 0 },
2743   /* 98 */
2744   { "cW{t|}R",          { XX }, 0 },
2745   { "cR{t|}O",          { XX }, 0 },
2746   { X86_64_TABLE (X86_64_9A) },
2747   { Bad_Opcode },       /* fwait */
2748   { "pushfT",           { XX }, 0 },
2749   { "popfT",            { XX }, 0 },
2750   { "sahf",             { XX }, 0 },
2751   { "lahf",             { XX }, 0 },
2752   /* a0 */
2753   { "mov%LB",           { AL, Ob }, 0 },
2754   { "mov%LS",           { eAX, Ov }, 0 },
2755   { "mov%LB",           { Ob, AL }, 0 },
2756   { "mov%LS",           { Ov, eAX }, 0 },
2757   { "movs{b|}",         { Ybr, Xb }, 0 },
2758   { "movs{R|}",         { Yvr, Xv }, 0 },
2759   { "cmps{b|}",         { Xb, Yb }, 0 },
2760   { "cmps{R|}",         { Xv, Yv }, 0 },
2761   /* a8 */
2762   { "testB",            { AL, Ib }, 0 },
2763   { "testS",            { eAX, Iv }, 0 },
2764   { "stosB",            { Ybr, AL }, 0 },
2765   { "stosS",            { Yvr, eAX }, 0 },
2766   { "lodsB",            { ALr, Xb }, 0 },
2767   { "lodsS",            { eAXr, Xv }, 0 },
2768   { "scasB",            { AL, Yb }, 0 },
2769   { "scasS",            { eAX, Yv }, 0 },
2770   /* b0 */
2771   { "movB",             { RMAL, Ib }, 0 },
2772   { "movB",             { RMCL, Ib }, 0 },
2773   { "movB",             { RMDL, Ib }, 0 },
2774   { "movB",             { RMBL, Ib }, 0 },
2775   { "movB",             { RMAH, Ib }, 0 },
2776   { "movB",             { RMCH, Ib }, 0 },
2777   { "movB",             { RMDH, Ib }, 0 },
2778   { "movB",             { RMBH, Ib }, 0 },
2779   /* b8 */
2780   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2781   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2782   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2783   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2784   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2785   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2786   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2787   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2788   /* c0 */
2789   { REG_TABLE (REG_C0) },
2790   { REG_TABLE (REG_C1) },
2791   { "retT",             { Iw, BND }, 0 },
2792   { "retT",             { BND }, 0 },
2793   { X86_64_TABLE (X86_64_C4) },
2794   { X86_64_TABLE (X86_64_C5) },
2795   { REG_TABLE (REG_C6) },
2796   { REG_TABLE (REG_C7) },
2797   /* c8 */
2798   { "enterT",           { Iw, Ib }, 0 },
2799   { "leaveT",           { XX }, 0 },
2800   { "Jret{|f}P",        { Iw }, 0 },
2801   { "Jret{|f}P",        { XX }, 0 },
2802   { "int3",             { XX }, 0 },
2803   { "int",              { Ib }, 0 },
2804   { X86_64_TABLE (X86_64_CE) },
2805   { "iret%LP",          { XX }, 0 },
2806   /* d0 */
2807   { REG_TABLE (REG_D0) },
2808   { REG_TABLE (REG_D1) },
2809   { REG_TABLE (REG_D2) },
2810   { REG_TABLE (REG_D3) },
2811   { X86_64_TABLE (X86_64_D4) },
2812   { X86_64_TABLE (X86_64_D5) },
2813   { Bad_Opcode },
2814   { "xlat",             { DSBX }, 0 },
2815   /* d8 */
2816   { FLOAT },
2817   { FLOAT },
2818   { FLOAT },
2819   { FLOAT },
2820   { FLOAT },
2821   { FLOAT },
2822   { FLOAT },
2823   { FLOAT },
2824   /* e0 */
2825   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2826   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2827   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2828   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2829   { "inB",              { AL, Ib }, 0 },
2830   { "inG",              { zAX, Ib }, 0 },
2831   { "outB",             { Ib, AL }, 0 },
2832   { "outG",             { Ib, zAX }, 0 },
2833   /* e8 */
2834   { X86_64_TABLE (X86_64_E8) },
2835   { X86_64_TABLE (X86_64_E9) },
2836   { X86_64_TABLE (X86_64_EA) },
2837   { "jmp",              { Jb, BND }, 0 },
2838   { "inB",              { AL, indirDX }, 0 },
2839   { "inG",              { zAX, indirDX }, 0 },
2840   { "outB",             { indirDX, AL }, 0 },
2841   { "outG",             { indirDX, zAX }, 0 },
2842   /* f0 */
2843   { Bad_Opcode },       /* lock prefix */
2844   { "icebp",            { XX }, 0 },
2845   { Bad_Opcode },       /* repne */
2846   { Bad_Opcode },       /* repz */
2847   { "hlt",              { XX }, 0 },
2848   { "cmc",              { XX }, 0 },
2849   { REG_TABLE (REG_F6) },
2850   { REG_TABLE (REG_F7) },
2851   /* f8 */
2852   { "clc",              { XX }, 0 },
2853   { "stc",              { XX }, 0 },
2854   { "cli",              { XX }, 0 },
2855   { "sti",              { XX }, 0 },
2856   { "cld",              { XX }, 0 },
2857   { "std",              { XX }, 0 },
2858   { REG_TABLE (REG_FE) },
2859   { REG_TABLE (REG_FF) },
2860 };
2861
2862 static const struct dis386 dis386_twobyte[] = {
2863   /* 00 */
2864   { REG_TABLE (REG_0F00 ) },
2865   { REG_TABLE (REG_0F01 ) },
2866   { "larS",             { Gv, Ew }, 0 },
2867   { "lslS",             { Gv, Ew }, 0 },
2868   { Bad_Opcode },
2869   { "syscall",          { XX }, 0 },
2870   { "clts",             { XX }, 0 },
2871   { "sysret%LP",                { XX }, 0 },
2872   /* 08 */
2873   { "invd",             { XX }, 0 },
2874   { "wbinvd",           { XX }, 0 },
2875   { Bad_Opcode },
2876   { "ud2",              { XX }, 0 },
2877   { Bad_Opcode },
2878   { REG_TABLE (REG_0F0D) },
2879   { "femms",            { XX }, 0 },
2880   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2881   /* 10 */
2882   { PREFIX_TABLE (PREFIX_0F10) },
2883   { PREFIX_TABLE (PREFIX_0F11) },
2884   { PREFIX_TABLE (PREFIX_0F12) },
2885   { MOD_TABLE (MOD_0F13) },
2886   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2887   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2888   { PREFIX_TABLE (PREFIX_0F16) },
2889   { MOD_TABLE (MOD_0F17) },
2890   /* 18 */
2891   { REG_TABLE (REG_0F18) },
2892   { "nopQ",             { Ev }, 0 },
2893   { PREFIX_TABLE (PREFIX_0F1A) },
2894   { PREFIX_TABLE (PREFIX_0F1B) },
2895   { "nopQ",             { Ev }, 0 },
2896   { "nopQ",             { Ev }, 0 },
2897   { PREFIX_TABLE (PREFIX_0F1E) },
2898   { "nopQ",             { Ev }, 0 },
2899   /* 20 */
2900   { "movZ",             { Rm, Cm }, 0 },
2901   { "movZ",             { Rm, Dm }, 0 },
2902   { "movZ",             { Cm, Rm }, 0 },
2903   { "movZ",             { Dm, Rm }, 0 },
2904   { MOD_TABLE (MOD_0F24) },
2905   { Bad_Opcode },
2906   { MOD_TABLE (MOD_0F26) },
2907   { Bad_Opcode },
2908   /* 28 */
2909   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2910   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2911   { PREFIX_TABLE (PREFIX_0F2A) },
2912   { PREFIX_TABLE (PREFIX_0F2B) },
2913   { PREFIX_TABLE (PREFIX_0F2C) },
2914   { PREFIX_TABLE (PREFIX_0F2D) },
2915   { PREFIX_TABLE (PREFIX_0F2E) },
2916   { PREFIX_TABLE (PREFIX_0F2F) },
2917   /* 30 */
2918   { "wrmsr",            { XX }, 0 },
2919   { "rdtsc",            { XX }, 0 },
2920   { "rdmsr",            { XX }, 0 },
2921   { "rdpmc",            { XX }, 0 },
2922   { "sysenter",         { XX }, 0 },
2923   { "sysexit",          { XX }, 0 },
2924   { Bad_Opcode },
2925   { "getsec",           { XX }, 0 },
2926   /* 38 */
2927   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2928   { Bad_Opcode },
2929   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2930   { Bad_Opcode },
2931   { Bad_Opcode },
2932   { Bad_Opcode },
2933   { Bad_Opcode },
2934   { Bad_Opcode },
2935   /* 40 */
2936   { "cmovoS",           { Gv, Ev }, 0 },
2937   { "cmovnoS",          { Gv, Ev }, 0 },
2938   { "cmovbS",           { Gv, Ev }, 0 },
2939   { "cmovaeS",          { Gv, Ev }, 0 },
2940   { "cmoveS",           { Gv, Ev }, 0 },
2941   { "cmovneS",          { Gv, Ev }, 0 },
2942   { "cmovbeS",          { Gv, Ev }, 0 },
2943   { "cmovaS",           { Gv, Ev }, 0 },
2944   /* 48 */
2945   { "cmovsS",           { Gv, Ev }, 0 },
2946   { "cmovnsS",          { Gv, Ev }, 0 },
2947   { "cmovpS",           { Gv, Ev }, 0 },
2948   { "cmovnpS",          { Gv, Ev }, 0 },
2949   { "cmovlS",           { Gv, Ev }, 0 },
2950   { "cmovgeS",          { Gv, Ev }, 0 },
2951   { "cmovleS",          { Gv, Ev }, 0 },
2952   { "cmovgS",           { Gv, Ev }, 0 },
2953   /* 50 */
2954   { MOD_TABLE (MOD_0F51) },
2955   { PREFIX_TABLE (PREFIX_0F51) },
2956   { PREFIX_TABLE (PREFIX_0F52) },
2957   { PREFIX_TABLE (PREFIX_0F53) },
2958   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2959   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2960   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2961   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2962   /* 58 */
2963   { PREFIX_TABLE (PREFIX_0F58) },
2964   { PREFIX_TABLE (PREFIX_0F59) },
2965   { PREFIX_TABLE (PREFIX_0F5A) },
2966   { PREFIX_TABLE (PREFIX_0F5B) },
2967   { PREFIX_TABLE (PREFIX_0F5C) },
2968   { PREFIX_TABLE (PREFIX_0F5D) },
2969   { PREFIX_TABLE (PREFIX_0F5E) },
2970   { PREFIX_TABLE (PREFIX_0F5F) },
2971   /* 60 */
2972   { PREFIX_TABLE (PREFIX_0F60) },
2973   { PREFIX_TABLE (PREFIX_0F61) },
2974   { PREFIX_TABLE (PREFIX_0F62) },
2975   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2976   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2977   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2978   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2979   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2980   /* 68 */
2981   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2982   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2983   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2984   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2985   { PREFIX_TABLE (PREFIX_0F6C) },
2986   { PREFIX_TABLE (PREFIX_0F6D) },
2987   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2988   { PREFIX_TABLE (PREFIX_0F6F) },
2989   /* 70 */
2990   { PREFIX_TABLE (PREFIX_0F70) },
2991   { REG_TABLE (REG_0F71) },
2992   { REG_TABLE (REG_0F72) },
2993   { REG_TABLE (REG_0F73) },
2994   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2995   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2996   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2997   { "emms",             { XX }, PREFIX_OPCODE },
2998   /* 78 */
2999   { PREFIX_TABLE (PREFIX_0F78) },
3000   { PREFIX_TABLE (PREFIX_0F79) },
3001   { Bad_Opcode },
3002   { Bad_Opcode },
3003   { PREFIX_TABLE (PREFIX_0F7C) },
3004   { PREFIX_TABLE (PREFIX_0F7D) },
3005   { PREFIX_TABLE (PREFIX_0F7E) },
3006   { PREFIX_TABLE (PREFIX_0F7F) },
3007   /* 80 */
3008   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3009   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3010   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3011   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3012   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3013   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3014   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3015   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3016   /* 88 */
3017   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3018   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3019   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3020   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3021   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3022   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3023   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3024   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3025   /* 90 */
3026   { "seto",             { Eb }, 0 },
3027   { "setno",            { Eb }, 0 },
3028   { "setb",             { Eb }, 0 },
3029   { "setae",            { Eb }, 0 },
3030   { "sete",             { Eb }, 0 },
3031   { "setne",            { Eb }, 0 },
3032   { "setbe",            { Eb }, 0 },
3033   { "seta",             { Eb }, 0 },
3034   /* 98 */
3035   { "sets",             { Eb }, 0 },
3036   { "setns",            { Eb }, 0 },
3037   { "setp",             { Eb }, 0 },
3038   { "setnp",            { Eb }, 0 },
3039   { "setl",             { Eb }, 0 },
3040   { "setge",            { Eb }, 0 },
3041   { "setle",            { Eb }, 0 },
3042   { "setg",             { Eb }, 0 },
3043   /* a0 */
3044   { "pushT",            { fs }, 0 },
3045   { "popT",             { fs }, 0 },
3046   { "cpuid",            { XX }, 0 },
3047   { "btS",              { Ev, Gv }, 0 },
3048   { "shldS",            { Ev, Gv, Ib }, 0 },
3049   { "shldS",            { Ev, Gv, CL }, 0 },
3050   { REG_TABLE (REG_0FA6) },
3051   { REG_TABLE (REG_0FA7) },
3052   /* a8 */
3053   { "pushT",            { gs }, 0 },
3054   { "popT",             { gs }, 0 },
3055   { "rsm",              { XX }, 0 },
3056   { "btsS",             { Evh1, Gv }, 0 },
3057   { "shrdS",            { Ev, Gv, Ib }, 0 },
3058   { "shrdS",            { Ev, Gv, CL }, 0 },
3059   { REG_TABLE (REG_0FAE) },
3060   { "imulS",            { Gv, Ev }, 0 },
3061   /* b0 */
3062   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3063   { "cmpxchgS",         { Evh1, Gv }, 0 },
3064   { MOD_TABLE (MOD_0FB2) },
3065   { "btrS",             { Evh1, Gv }, 0 },
3066   { MOD_TABLE (MOD_0FB4) },
3067   { MOD_TABLE (MOD_0FB5) },
3068   { "movz{bR|x}",       { Gv, Eb }, 0 },
3069   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3070   /* b8 */
3071   { PREFIX_TABLE (PREFIX_0FB8) },
3072   { "ud1",              { XX }, 0 },
3073   { REG_TABLE (REG_0FBA) },
3074   { "btcS",             { Evh1, Gv }, 0 },
3075   { PREFIX_TABLE (PREFIX_0FBC) },
3076   { PREFIX_TABLE (PREFIX_0FBD) },
3077   { "movs{bR|x}",       { Gv, Eb }, 0 },
3078   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3079   /* c0 */
3080   { "xaddB",            { Ebh1, Gb }, 0 },
3081   { "xaddS",            { Evh1, Gv }, 0 },
3082   { PREFIX_TABLE (PREFIX_0FC2) },
3083   { MOD_TABLE (MOD_0FC3) },
3084   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3085   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3086   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3087   { REG_TABLE (REG_0FC7) },
3088   /* c8 */
3089   { "bswap",            { RMeAX }, 0 },
3090   { "bswap",            { RMeCX }, 0 },
3091   { "bswap",            { RMeDX }, 0 },
3092   { "bswap",            { RMeBX }, 0 },
3093   { "bswap",            { RMeSP }, 0 },
3094   { "bswap",            { RMeBP }, 0 },
3095   { "bswap",            { RMeSI }, 0 },
3096   { "bswap",            { RMeDI }, 0 },
3097   /* d0 */
3098   { PREFIX_TABLE (PREFIX_0FD0) },
3099   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3100   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3101   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3102   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3103   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3104   { PREFIX_TABLE (PREFIX_0FD6) },
3105   { MOD_TABLE (MOD_0FD7) },
3106   /* d8 */
3107   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3108   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3109   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3110   { "pand",             { MX, EM }, PREFIX_OPCODE },
3111   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3112   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3113   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3114   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3115   /* e0 */
3116   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3117   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3118   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3119   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3120   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3121   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3122   { PREFIX_TABLE (PREFIX_0FE6) },
3123   { PREFIX_TABLE (PREFIX_0FE7) },
3124   /* e8 */
3125   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3126   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3127   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3128   { "por",              { MX, EM }, PREFIX_OPCODE },
3129   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3130   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3131   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3132   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3133   /* f0 */
3134   { PREFIX_TABLE (PREFIX_0FF0) },
3135   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3136   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3137   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3138   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3139   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3140   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3141   { PREFIX_TABLE (PREFIX_0FF7) },
3142   /* f8 */
3143   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3144   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3145   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3146   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3147   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3148   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3149   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3150   { Bad_Opcode },
3151 };
3152
3153 static const unsigned char onebyte_has_modrm[256] = {
3154   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3155   /*       -------------------------------        */
3156   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3157   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3158   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3159   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3160   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3161   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3162   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3163   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3164   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3165   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3166   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3167   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3168   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3169   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3170   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3171   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3172   /*       -------------------------------        */
3173   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3174 };
3175
3176 static const unsigned char twobyte_has_modrm[256] = {
3177   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3178   /*       -------------------------------        */
3179   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3180   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3181   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3182   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3183   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3184   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3185   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3186   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3187   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3188   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3189   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3190   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3191   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3192   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3193   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3194   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3195   /*       -------------------------------        */
3196   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3197 };
3198
3199 static char obuf[100];
3200 static char *obufp;
3201 static char *mnemonicendp;
3202 static char scratchbuf[100];
3203 static unsigned char *start_codep;
3204 static unsigned char *insn_codep;
3205 static unsigned char *codep;
3206 static unsigned char *end_codep;
3207 static int last_lock_prefix;
3208 static int last_repz_prefix;
3209 static int last_repnz_prefix;
3210 static int last_data_prefix;
3211 static int last_addr_prefix;
3212 static int last_rex_prefix;
3213 static int last_seg_prefix;
3214 static int fwait_prefix;
3215 /* The active segment register prefix.  */
3216 static int active_seg_prefix;
3217 #define MAX_CODE_LENGTH 15
3218 /* We can up to 14 prefixes since the maximum instruction length is
3219    15bytes.  */
3220 static int all_prefixes[MAX_CODE_LENGTH - 1];
3221 static disassemble_info *the_info;
3222 static struct
3223   {
3224     int mod;
3225     int reg;
3226     int rm;
3227   }
3228 modrm;
3229 static unsigned char need_modrm;
3230 static struct
3231   {
3232     int scale;
3233     int index;
3234     int base;
3235   }
3236 sib;
3237 static struct
3238   {
3239     int register_specifier;
3240     int length;
3241     int prefix;
3242     int w;
3243     int evex;
3244     int r;
3245     int v;
3246     int mask_register_specifier;
3247     int zeroing;
3248     int ll;
3249     int b;
3250   }
3251 vex;
3252 static unsigned char need_vex;
3253 static unsigned char need_vex_reg;
3254 static unsigned char vex_w_done;
3255
3256 struct op
3257   {
3258     const char *name;
3259     unsigned int len;
3260   };
3261
3262 /* If we are accessing mod/rm/reg without need_modrm set, then the
3263    values are stale.  Hitting this abort likely indicates that you
3264    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3265 #define MODRM_CHECK  if (!need_modrm) abort ()
3266
3267 static const char **names64;
3268 static const char **names32;
3269 static const char **names16;
3270 static const char **names8;
3271 static const char **names8rex;
3272 static const char **names_seg;
3273 static const char *index64;
3274 static const char *index32;
3275 static const char **index16;
3276 static const char **names_bnd;
3277
3278 static const char *intel_names64[] = {
3279   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3280   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3281 };
3282 static const char *intel_names32[] = {
3283   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3284   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3285 };
3286 static const char *intel_names16[] = {
3287   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3288   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3289 };
3290 static const char *intel_names8[] = {
3291   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3292 };
3293 static const char *intel_names8rex[] = {
3294   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3295   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3296 };
3297 static const char *intel_names_seg[] = {
3298   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3299 };
3300 static const char *intel_index64 = "riz";
3301 static const char *intel_index32 = "eiz";
3302 static const char *intel_index16[] = {
3303   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3304 };
3305
3306 static const char *att_names64[] = {
3307   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3308   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3309 };
3310 static const char *att_names32[] = {
3311   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3312   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3313 };
3314 static const char *att_names16[] = {
3315   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3316   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3317 };
3318 static const char *att_names8[] = {
3319   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3320 };
3321 static const char *att_names8rex[] = {
3322   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3323   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3324 };
3325 static const char *att_names_seg[] = {
3326   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3327 };
3328 static const char *att_index64 = "%riz";
3329 static const char *att_index32 = "%eiz";
3330 static const char *att_index16[] = {
3331   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3332 };
3333
3334 static const char **names_mm;
3335 static const char *intel_names_mm[] = {
3336   "mm0", "mm1", "mm2", "mm3",
3337   "mm4", "mm5", "mm6", "mm7"
3338 };
3339 static const char *att_names_mm[] = {
3340   "%mm0", "%mm1", "%mm2", "%mm3",
3341   "%mm4", "%mm5", "%mm6", "%mm7"
3342 };
3343
3344 static const char *intel_names_bnd[] = {
3345   "bnd0", "bnd1", "bnd2", "bnd3"
3346 };
3347
3348 static const char *att_names_bnd[] = {
3349   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3350 };
3351
3352 static const char **names_xmm;
3353 static const char *intel_names_xmm[] = {
3354   "xmm0", "xmm1", "xmm2", "xmm3",
3355   "xmm4", "xmm5", "xmm6", "xmm7",
3356   "xmm8", "xmm9", "xmm10", "xmm11",
3357   "xmm12", "xmm13", "xmm14", "xmm15",
3358   "xmm16", "xmm17", "xmm18", "xmm19",
3359   "xmm20", "xmm21", "xmm22", "xmm23",
3360   "xmm24", "xmm25", "xmm26", "xmm27",
3361   "xmm28", "xmm29", "xmm30", "xmm31"
3362 };
3363 static const char *att_names_xmm[] = {
3364   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3365   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3366   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3367   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3368   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3369   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3370   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3371   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3372 };
3373
3374 static const char **names_ymm;
3375 static const char *intel_names_ymm[] = {
3376   "ymm0", "ymm1", "ymm2", "ymm3",
3377   "ymm4", "ymm5", "ymm6", "ymm7",
3378   "ymm8", "ymm9", "ymm10", "ymm11",
3379   "ymm12", "ymm13", "ymm14", "ymm15",
3380   "ymm16", "ymm17", "ymm18", "ymm19",
3381   "ymm20", "ymm21", "ymm22", "ymm23",
3382   "ymm24", "ymm25", "ymm26", "ymm27",
3383   "ymm28", "ymm29", "ymm30", "ymm31"
3384 };
3385 static const char *att_names_ymm[] = {
3386   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3387   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3388   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3389   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3390   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3391   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3392   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3393   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3394 };
3395
3396 static const char **names_zmm;
3397 static const char *intel_names_zmm[] = {
3398   "zmm0", "zmm1", "zmm2", "zmm3",
3399   "zmm4", "zmm5", "zmm6", "zmm7",
3400   "zmm8", "zmm9", "zmm10", "zmm11",
3401   "zmm12", "zmm13", "zmm14", "zmm15",
3402   "zmm16", "zmm17", "zmm18", "zmm19",
3403   "zmm20", "zmm21", "zmm22", "zmm23",
3404   "zmm24", "zmm25", "zmm26", "zmm27",
3405   "zmm28", "zmm29", "zmm30", "zmm31"
3406 };
3407 static const char *att_names_zmm[] = {
3408   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3409   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3410   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3411   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3412   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3413   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3414   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3415   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3416 };
3417
3418 static const char **names_mask;
3419 static const char *intel_names_mask[] = {
3420   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3421 };
3422 static const char *att_names_mask[] = {
3423   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3424 };
3425
3426 static const char *names_rounding[] =
3427 {
3428   "{rn-sae}",
3429   "{rd-sae}",
3430   "{ru-sae}",
3431   "{rz-sae}"
3432 };
3433
3434 static const struct dis386 reg_table[][8] = {
3435   /* REG_80 */
3436   {
3437     { "addA",   { Ebh1, Ib }, 0 },
3438     { "orA",    { Ebh1, Ib }, 0 },
3439     { "adcA",   { Ebh1, Ib }, 0 },
3440     { "sbbA",   { Ebh1, Ib }, 0 },
3441     { "andA",   { Ebh1, Ib }, 0 },
3442     { "subA",   { Ebh1, Ib }, 0 },
3443     { "xorA",   { Ebh1, Ib }, 0 },
3444     { "cmpA",   { Eb, Ib }, 0 },
3445   },
3446   /* REG_81 */
3447   {
3448     { "addQ",   { Evh1, Iv }, 0 },
3449     { "orQ",    { Evh1, Iv }, 0 },
3450     { "adcQ",   { Evh1, Iv }, 0 },
3451     { "sbbQ",   { Evh1, Iv }, 0 },
3452     { "andQ",   { Evh1, Iv }, 0 },
3453     { "subQ",   { Evh1, Iv }, 0 },
3454     { "xorQ",   { Evh1, Iv }, 0 },
3455     { "cmpQ",   { Ev, Iv }, 0 },
3456   },
3457   /* REG_83 */
3458   {
3459     { "addQ",   { Evh1, sIb }, 0 },
3460     { "orQ",    { Evh1, sIb }, 0 },
3461     { "adcQ",   { Evh1, sIb }, 0 },
3462     { "sbbQ",   { Evh1, sIb }, 0 },
3463     { "andQ",   { Evh1, sIb }, 0 },
3464     { "subQ",   { Evh1, sIb }, 0 },
3465     { "xorQ",   { Evh1, sIb }, 0 },
3466     { "cmpQ",   { Ev, sIb }, 0 },
3467   },
3468   /* REG_8F */
3469   {
3470     { "popU",   { stackEv }, 0 },
3471     { XOP_8F_TABLE (XOP_09) },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { XOP_8F_TABLE (XOP_09) },
3476   },
3477   /* REG_C0 */
3478   {
3479     { "rolA",   { Eb, Ib }, 0 },
3480     { "rorA",   { Eb, Ib }, 0 },
3481     { "rclA",   { Eb, Ib }, 0 },
3482     { "rcrA",   { Eb, Ib }, 0 },
3483     { "shlA",   { Eb, Ib }, 0 },
3484     { "shrA",   { Eb, Ib }, 0 },
3485     { "shlA",   { Eb, Ib }, 0 },
3486     { "sarA",   { Eb, Ib }, 0 },
3487   },
3488   /* REG_C1 */
3489   {
3490     { "rolQ",   { Ev, Ib }, 0 },
3491     { "rorQ",   { Ev, Ib }, 0 },
3492     { "rclQ",   { Ev, Ib }, 0 },
3493     { "rcrQ",   { Ev, Ib }, 0 },
3494     { "shlQ",   { Ev, Ib }, 0 },
3495     { "shrQ",   { Ev, Ib }, 0 },
3496     { "shlQ",   { Ev, Ib }, 0 },
3497     { "sarQ",   { Ev, Ib }, 0 },
3498   },
3499   /* REG_C6 */
3500   {
3501     { "movA",   { Ebh3, Ib }, 0 },
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { Bad_Opcode },
3508     { MOD_TABLE (MOD_C6_REG_7) },
3509   },
3510   /* REG_C7 */
3511   {
3512     { "movQ",   { Evh3, Iv }, 0 },
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { MOD_TABLE (MOD_C7_REG_7) },
3520   },
3521   /* REG_D0 */
3522   {
3523     { "rolA",   { Eb, I1 }, 0 },
3524     { "rorA",   { Eb, I1 }, 0 },
3525     { "rclA",   { Eb, I1 }, 0 },
3526     { "rcrA",   { Eb, I1 }, 0 },
3527     { "shlA",   { Eb, I1 }, 0 },
3528     { "shrA",   { Eb, I1 }, 0 },
3529     { "shlA",   { Eb, I1 }, 0 },
3530     { "sarA",   { Eb, I1 }, 0 },
3531   },
3532   /* REG_D1 */
3533   {
3534     { "rolQ",   { Ev, I1 }, 0 },
3535     { "rorQ",   { Ev, I1 }, 0 },
3536     { "rclQ",   { Ev, I1 }, 0 },
3537     { "rcrQ",   { Ev, I1 }, 0 },
3538     { "shlQ",   { Ev, I1 }, 0 },
3539     { "shrQ",   { Ev, I1 }, 0 },
3540     { "shlQ",   { Ev, I1 }, 0 },
3541     { "sarQ",   { Ev, I1 }, 0 },
3542   },
3543   /* REG_D2 */
3544   {
3545     { "rolA",   { Eb, CL }, 0 },
3546     { "rorA",   { Eb, CL }, 0 },
3547     { "rclA",   { Eb, CL }, 0 },
3548     { "rcrA",   { Eb, CL }, 0 },
3549     { "shlA",   { Eb, CL }, 0 },
3550     { "shrA",   { Eb, CL }, 0 },
3551     { "shlA",   { Eb, CL }, 0 },
3552     { "sarA",   { Eb, CL }, 0 },
3553   },
3554   /* REG_D3 */
3555   {
3556     { "rolQ",   { Ev, CL }, 0 },
3557     { "rorQ",   { Ev, CL }, 0 },
3558     { "rclQ",   { Ev, CL }, 0 },
3559     { "rcrQ",   { Ev, CL }, 0 },
3560     { "shlQ",   { Ev, CL }, 0 },
3561     { "shrQ",   { Ev, CL }, 0 },
3562     { "shlQ",   { Ev, CL }, 0 },
3563     { "sarQ",   { Ev, CL }, 0 },
3564   },
3565   /* REG_F6 */
3566   {
3567     { "testA",  { Eb, Ib }, 0 },
3568     { "testA",  { Eb, Ib }, 0 },
3569     { "notA",   { Ebh1 }, 0 },
3570     { "negA",   { Ebh1 }, 0 },
3571     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3572     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3573     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3574     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3575   },
3576   /* REG_F7 */
3577   {
3578     { "testQ",  { Ev, Iv }, 0 },
3579     { "testQ",  { Ev, Iv }, 0 },
3580     { "notQ",   { Evh1 }, 0 },
3581     { "negQ",   { Evh1 }, 0 },
3582     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3583     { "imulQ",  { Ev }, 0 },
3584     { "divQ",   { Ev }, 0 },
3585     { "idivQ",  { Ev }, 0 },
3586   },
3587   /* REG_FE */
3588   {
3589     { "incA",   { Ebh1 }, 0 },
3590     { "decA",   { Ebh1 }, 0 },
3591   },
3592   /* REG_FF */
3593   {
3594     { "incQ",   { Evh1 }, 0 },
3595     { "decQ",   { Evh1 }, 0 },
3596     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3597     { MOD_TABLE (MOD_FF_REG_3) },
3598     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3599     { MOD_TABLE (MOD_FF_REG_5) },
3600     { "pushU",  { stackEv }, 0 },
3601     { Bad_Opcode },
3602   },
3603   /* REG_0F00 */
3604   {
3605     { "sldtD",  { Sv }, 0 },
3606     { "strD",   { Sv }, 0 },
3607     { "lldt",   { Ew }, 0 },
3608     { "ltr",    { Ew }, 0 },
3609     { "verr",   { Ew }, 0 },
3610     { "verw",   { Ew }, 0 },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613   },
3614   /* REG_0F01 */
3615   {
3616     { MOD_TABLE (MOD_0F01_REG_0) },
3617     { MOD_TABLE (MOD_0F01_REG_1) },
3618     { MOD_TABLE (MOD_0F01_REG_2) },
3619     { MOD_TABLE (MOD_0F01_REG_3) },
3620     { "smswD",  { Sv }, 0 },
3621     { MOD_TABLE (MOD_0F01_REG_5) },
3622     { "lmsw",   { Ew }, 0 },
3623     { MOD_TABLE (MOD_0F01_REG_7) },
3624   },
3625   /* REG_0F0D */
3626   {
3627     { "prefetch",       { Mb }, 0 },
3628     { "prefetchw",      { Mb }, 0 },
3629     { "prefetchwt1",    { Mb }, 0 },
3630     { "prefetch",       { Mb }, 0 },
3631     { "prefetch",       { Mb }, 0 },
3632     { "prefetch",       { Mb }, 0 },
3633     { "prefetch",       { Mb }, 0 },
3634     { "prefetch",       { Mb }, 0 },
3635   },
3636   /* REG_0F18 */
3637   {
3638     { MOD_TABLE (MOD_0F18_REG_0) },
3639     { MOD_TABLE (MOD_0F18_REG_1) },
3640     { MOD_TABLE (MOD_0F18_REG_2) },
3641     { MOD_TABLE (MOD_0F18_REG_3) },
3642     { MOD_TABLE (MOD_0F18_REG_4) },
3643     { MOD_TABLE (MOD_0F18_REG_5) },
3644     { MOD_TABLE (MOD_0F18_REG_6) },
3645     { MOD_TABLE (MOD_0F18_REG_7) },
3646   },
3647   /* REG_0F1E_MOD_3 */
3648   {
3649     { "nopQ",           { Ev }, 0 },
3650     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3651     { "nopQ",           { Ev }, 0 },
3652     { "nopQ",           { Ev }, 0 },
3653     { "nopQ",           { Ev }, 0 },
3654     { "nopQ",           { Ev }, 0 },
3655     { "nopQ",           { Ev }, 0 },
3656     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3657   },
3658   /* REG_0F71 */
3659   {
3660     { Bad_Opcode },
3661     { Bad_Opcode },
3662     { MOD_TABLE (MOD_0F71_REG_2) },
3663     { Bad_Opcode },
3664     { MOD_TABLE (MOD_0F71_REG_4) },
3665     { Bad_Opcode },
3666     { MOD_TABLE (MOD_0F71_REG_6) },
3667   },
3668   /* REG_0F72 */
3669   {
3670     { Bad_Opcode },
3671     { Bad_Opcode },
3672     { MOD_TABLE (MOD_0F72_REG_2) },
3673     { Bad_Opcode },
3674     { MOD_TABLE (MOD_0F72_REG_4) },
3675     { Bad_Opcode },
3676     { MOD_TABLE (MOD_0F72_REG_6) },
3677   },
3678   /* REG_0F73 */
3679   {
3680     { Bad_Opcode },
3681     { Bad_Opcode },
3682     { MOD_TABLE (MOD_0F73_REG_2) },
3683     { MOD_TABLE (MOD_0F73_REG_3) },
3684     { Bad_Opcode },
3685     { Bad_Opcode },
3686     { MOD_TABLE (MOD_0F73_REG_6) },
3687     { MOD_TABLE (MOD_0F73_REG_7) },
3688   },
3689   /* REG_0FA6 */
3690   {
3691     { "montmul",        { { OP_0f07, 0 } }, 0 },
3692     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3693     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3694   },
3695   /* REG_0FA7 */
3696   {
3697     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3698     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3699     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3700     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3701     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3702     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3703   },
3704   /* REG_0FAE */
3705   {
3706     { MOD_TABLE (MOD_0FAE_REG_0) },
3707     { MOD_TABLE (MOD_0FAE_REG_1) },
3708     { MOD_TABLE (MOD_0FAE_REG_2) },
3709     { MOD_TABLE (MOD_0FAE_REG_3) },
3710     { MOD_TABLE (MOD_0FAE_REG_4) },
3711     { MOD_TABLE (MOD_0FAE_REG_5) },
3712     { MOD_TABLE (MOD_0FAE_REG_6) },
3713     { MOD_TABLE (MOD_0FAE_REG_7) },
3714   },
3715   /* REG_0FBA */
3716   {
3717     { Bad_Opcode },
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { Bad_Opcode },
3721     { "btQ",    { Ev, Ib }, 0 },
3722     { "btsQ",   { Evh1, Ib }, 0 },
3723     { "btrQ",   { Evh1, Ib }, 0 },
3724     { "btcQ",   { Evh1, Ib }, 0 },
3725   },
3726   /* REG_0FC7 */
3727   {
3728     { Bad_Opcode },
3729     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3730     { Bad_Opcode },
3731     { MOD_TABLE (MOD_0FC7_REG_3) },
3732     { MOD_TABLE (MOD_0FC7_REG_4) },
3733     { MOD_TABLE (MOD_0FC7_REG_5) },
3734     { MOD_TABLE (MOD_0FC7_REG_6) },
3735     { MOD_TABLE (MOD_0FC7_REG_7) },
3736   },
3737   /* REG_VEX_0F71 */
3738   {
3739     { Bad_Opcode },
3740     { Bad_Opcode },
3741     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3742     { Bad_Opcode },
3743     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3744     { Bad_Opcode },
3745     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3746   },
3747   /* REG_VEX_0F72 */
3748   {
3749     { Bad_Opcode },
3750     { Bad_Opcode },
3751     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3752     { Bad_Opcode },
3753     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3754     { Bad_Opcode },
3755     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3756   },
3757   /* REG_VEX_0F73 */
3758   {
3759     { Bad_Opcode },
3760     { Bad_Opcode },
3761     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3762     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3763     { Bad_Opcode },
3764     { Bad_Opcode },
3765     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3766     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3767   },
3768   /* REG_VEX_0FAE */
3769   {
3770     { Bad_Opcode },
3771     { Bad_Opcode },
3772     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3773     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3774   },
3775   /* REG_VEX_0F38F3 */
3776   {
3777     { Bad_Opcode },
3778     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3779     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3780     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3781   },
3782   /* REG_XOP_LWPCB */
3783   {
3784     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3785     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3786   },
3787   /* REG_XOP_LWP */
3788   {
3789     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3790     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3791   },
3792   /* REG_XOP_TBM_01 */
3793   {
3794     { Bad_Opcode },
3795     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3796     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3797     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3798     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3799     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3800     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3801     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3802   },
3803   /* REG_XOP_TBM_02 */
3804   {
3805     { Bad_Opcode },
3806     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3807     { Bad_Opcode },
3808     { Bad_Opcode },
3809     { Bad_Opcode },
3810     { Bad_Opcode },
3811     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3812   },
3813 #define NEED_REG_TABLE
3814 #include "i386-dis-evex.h"
3815 #undef NEED_REG_TABLE
3816 };
3817
3818 static const struct dis386 prefix_table[][4] = {
3819   /* PREFIX_90 */
3820   {
3821     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3822     { "pause", { XX }, 0 },
3823     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3824     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3825   },
3826
3827   /* PREFIX_MOD_0_0F01_REG_5 */
3828   {
3829     { Bad_Opcode },
3830     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3834   {
3835     { Bad_Opcode },
3836     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3837   },
3838
3839   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3840   {
3841     { Bad_Opcode },
3842     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0F10 */
3846   {
3847     { "movups", { XM, EXx }, PREFIX_OPCODE },
3848     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3849     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3850     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F11 */
3854   {
3855     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3856     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3857     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3858     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F12 */
3862   {
3863     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3864     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3865     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3866     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F16 */
3870   {
3871     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3872     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3873     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F1A */
3877   {
3878     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3879     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3880     { "bndmov", { Gbnd, Ebnd }, 0 },
3881     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3882   },
3883
3884   /* PREFIX_0F1B */
3885   {
3886     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3887     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3888     { "bndmov", { Ebnd, Gbnd }, 0 },
3889     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3890   },
3891
3892   /* PREFIX_0F1E */
3893   {
3894     { "nopQ",   { Ev }, PREFIX_OPCODE },
3895     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3896     { "nopQ",   { Ev }, PREFIX_OPCODE },
3897     { "nopQ",   { Ev }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F2A */
3901   {
3902     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3903     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3904     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3905     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3906   },
3907
3908   /* PREFIX_0F2B */
3909   {
3910     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3911     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3912     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3913     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3914   },
3915
3916   /* PREFIX_0F2C */
3917   {
3918     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3919     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3920     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3921     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0F2D */
3925   {
3926     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3927     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3928     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3929     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3930   },
3931
3932   /* PREFIX_0F2E */
3933   {
3934     { "ucomiss",{ XM, EXd }, 0 },
3935     { Bad_Opcode },
3936     { "ucomisd",{ XM, EXq }, 0 },
3937   },
3938
3939   /* PREFIX_0F2F */
3940   {
3941     { "comiss", { XM, EXd }, 0 },
3942     { Bad_Opcode },
3943     { "comisd", { XM, EXq }, 0 },
3944   },
3945
3946   /* PREFIX_0F51 */
3947   {
3948     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3949     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3950     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3951     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0F52 */
3955   {
3956     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3957     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0F53 */
3961   {
3962     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3963     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0F58 */
3967   {
3968     { "addps", { XM, EXx }, PREFIX_OPCODE },
3969     { "addss", { XM, EXd }, PREFIX_OPCODE },
3970     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3971     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0F59 */
3975   {
3976     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3977     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3978     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3979     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3980   },
3981
3982   /* PREFIX_0F5A */
3983   {
3984     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3985     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3986     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3987     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3988   },
3989
3990   /* PREFIX_0F5B */
3991   {
3992     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3993     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3994     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3995   },
3996
3997   /* PREFIX_0F5C */
3998   {
3999     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4000     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4001     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4002     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4003   },
4004
4005   /* PREFIX_0F5D */
4006   {
4007     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4008     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4009     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4010     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4011   },
4012
4013   /* PREFIX_0F5E */
4014   {
4015     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4016     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4017     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4018     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4019   },
4020
4021   /* PREFIX_0F5F */
4022   {
4023     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4024     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4025     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4026     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0F60 */
4030   {
4031     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4032     { Bad_Opcode },
4033     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4034   },
4035
4036   /* PREFIX_0F61 */
4037   {
4038     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4039     { Bad_Opcode },
4040     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4041   },
4042
4043   /* PREFIX_0F62 */
4044   {
4045     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4046     { Bad_Opcode },
4047     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4048   },
4049
4050   /* PREFIX_0F6C */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4055   },
4056
4057   /* PREFIX_0F6D */
4058   {
4059     { Bad_Opcode },
4060     { Bad_Opcode },
4061     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4062   },
4063
4064   /* PREFIX_0F6F */
4065   {
4066     { "movq",   { MX, EM }, PREFIX_OPCODE },
4067     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4068     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4069   },
4070
4071   /* PREFIX_0F70 */
4072   {
4073     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4074     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4075     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4076     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4077   },
4078
4079   /* PREFIX_0F73_REG_3 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { "psrldq", { XS, Ib }, 0 },
4084   },
4085
4086   /* PREFIX_0F73_REG_7 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { "pslldq", { XS, Ib }, 0 },
4091   },
4092
4093   /* PREFIX_0F78 */
4094   {
4095     {"vmread",  { Em, Gm }, 0 },
4096     { Bad_Opcode },
4097     {"extrq",   { XS, Ib, Ib }, 0 },
4098     {"insertq", { XM, XS, Ib, Ib }, 0 },
4099   },
4100
4101   /* PREFIX_0F79 */
4102   {
4103     {"vmwrite", { Gm, Em }, 0 },
4104     { Bad_Opcode },
4105     {"extrq",   { XM, XS }, 0 },
4106     {"insertq", { XM, XS }, 0 },
4107   },
4108
4109   /* PREFIX_0F7C */
4110   {
4111     { Bad_Opcode },
4112     { Bad_Opcode },
4113     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4114     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4115   },
4116
4117   /* PREFIX_0F7D */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4122     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4123   },
4124
4125   /* PREFIX_0F7E */
4126   {
4127     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4128     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4129     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4130   },
4131
4132   /* PREFIX_0F7F */
4133   {
4134     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4135     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4136     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4137   },
4138
4139   /* PREFIX_0FAE_REG_0 */
4140   {
4141     { Bad_Opcode },
4142     { "rdfsbase", { Ev }, 0 },
4143   },
4144
4145   /* PREFIX_0FAE_REG_1 */
4146   {
4147     { Bad_Opcode },
4148     { "rdgsbase", { Ev }, 0 },
4149   },
4150
4151   /* PREFIX_0FAE_REG_2 */
4152   {
4153     { Bad_Opcode },
4154     { "wrfsbase", { Ev }, 0 },
4155   },
4156
4157   /* PREFIX_0FAE_REG_3 */
4158   {
4159     { Bad_Opcode },
4160     { "wrgsbase", { Ev }, 0 },
4161   },
4162
4163   /* PREFIX_MOD_0_0FAE_REG_4 */
4164   {
4165     { "xsave",  { FXSAVE }, 0 },
4166     { "ptwrite%LQ", { Edq }, 0 },
4167   },
4168
4169   /* PREFIX_MOD_3_0FAE_REG_4 */
4170   {
4171     { Bad_Opcode },
4172     { "ptwrite%LQ", { Edq }, 0 },
4173   },
4174
4175   /* PREFIX_MOD_0_0FAE_REG_5 */
4176   {
4177     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_MOD_3_0FAE_REG_5 */
4181   {
4182     { "lfence",         { Skip_MODRM }, 0 },
4183     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_0FAE_REG_6 */
4187   {
4188     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4189     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4190     { "clwb",   { Mb }, PREFIX_OPCODE },
4191   },
4192
4193   /* PREFIX_0FAE_REG_7 */
4194   {
4195     { "clflush",        { Mb }, 0 },
4196     { Bad_Opcode },
4197     { "clflushopt",     { Mb }, 0 },
4198   },
4199
4200   /* PREFIX_0FB8 */
4201   {
4202     { Bad_Opcode },
4203     { "popcntS", { Gv, Ev }, 0 },
4204   },
4205
4206   /* PREFIX_0FBC */
4207   {
4208     { "bsfS",   { Gv, Ev }, 0 },
4209     { "tzcntS", { Gv, Ev }, 0 },
4210     { "bsfS",   { Gv, Ev }, 0 },
4211   },
4212
4213   /* PREFIX_0FBD */
4214   {
4215     { "bsrS",   { Gv, Ev }, 0 },
4216     { "lzcntS", { Gv, Ev }, 0 },
4217     { "bsrS",   { Gv, Ev }, 0 },
4218   },
4219
4220   /* PREFIX_0FC2 */
4221   {
4222     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4223     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4224     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4225     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4226   },
4227
4228   /* PREFIX_MOD_0_0FC3 */
4229   {
4230     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_MOD_0_0FC7_REG_6 */
4234   {
4235     { "vmptrld",{ Mq }, 0 },
4236     { "vmxon",  { Mq }, 0 },
4237     { "vmclear",{ Mq }, 0 },
4238   },
4239
4240   /* PREFIX_MOD_3_0FC7_REG_6 */
4241   {
4242     { "rdrand", { Ev }, 0 },
4243     { Bad_Opcode },
4244     { "rdrand", { Ev }, 0 }
4245   },
4246
4247   /* PREFIX_MOD_3_0FC7_REG_7 */
4248   {
4249     { "rdseed", { Ev }, 0 },
4250     { "rdpid",  { Em }, 0 },
4251     { "rdseed", { Ev }, 0 },
4252   },
4253
4254   /* PREFIX_0FD0 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "addsubpd", { XM, EXx }, 0 },
4259     { "addsubps", { XM, EXx }, 0 },
4260   },
4261
4262   /* PREFIX_0FD6 */
4263   {
4264     { Bad_Opcode },
4265     { "movq2dq",{ XM, MS }, 0 },
4266     { "movq",   { EXqS, XM }, 0 },
4267     { "movdq2q",{ MX, XS }, 0 },
4268   },
4269
4270   /* PREFIX_0FE6 */
4271   {
4272     { Bad_Opcode },
4273     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4274     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4275     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0FE7 */
4279   {
4280     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4281     { Bad_Opcode },
4282     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4283   },
4284
4285   /* PREFIX_0FF0 */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4291   },
4292
4293   /* PREFIX_0FF7 */
4294   {
4295     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4296     { Bad_Opcode },
4297     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F3810 */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F3814 */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F3815 */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F3817 */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F3820 */
4329   {
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F3821 */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F3822 */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F3823 */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3824 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F3825 */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F3828 */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F3829 */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F382A */
4385   {
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4389   },
4390
4391   /* PREFIX_0F382B */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F3830 */
4399   {
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F3831 */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F3832 */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F3833 */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F3834 */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F3835 */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F3837 */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F3838 */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F3839 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F383A */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F383B */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F383C */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F383D */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F383E */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F383F */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3840 */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3841 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3880 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3881 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3882 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F38C8 */
4539   {
4540     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F38C9 */
4544   {
4545     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4546   },
4547
4548   /* PREFIX_0F38CA */
4549   {
4550     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F38CB */
4554   {
4555     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F38CC */
4559   {
4560     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F38CD */
4564   {
4565     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F38CF */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F38DB */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F38DC */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F38DD */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F38DE */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F38DF */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F38F0 */
4611   {
4612     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4613     { Bad_Opcode },
4614     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4615     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F38F1 */
4619   {
4620     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4621     { Bad_Opcode },
4622     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4623     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F38F5 */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4631   },
4632
4633   /* PREFIX_0F38F6 */
4634   {
4635     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4636     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4637     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4638     { Bad_Opcode },
4639   },
4640
4641   /* PREFIX_0F3A08 */
4642   {
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4646   },
4647
4648   /* PREFIX_0F3A09 */
4649   {
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4653   },
4654
4655   /* PREFIX_0F3A0A */
4656   {
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4660   },
4661
4662   /* PREFIX_0F3A0B */
4663   {
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4667   },
4668
4669   /* PREFIX_0F3A0C */
4670   {
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4674   },
4675
4676   /* PREFIX_0F3A0D */
4677   {
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4681   },
4682
4683   /* PREFIX_0F3A0E */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_0F3A14 */
4691   {
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4695   },
4696
4697   /* PREFIX_0F3A15 */
4698   {
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4702   },
4703
4704   /* PREFIX_0F3A16 */
4705   {
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4709   },
4710
4711   /* PREFIX_0F3A17 */
4712   {
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4716   },
4717
4718   /* PREFIX_0F3A20 */
4719   {
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4723   },
4724
4725   /* PREFIX_0F3A21 */
4726   {
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4730   },
4731
4732   /* PREFIX_0F3A22 */
4733   {
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4737   },
4738
4739   /* PREFIX_0F3A40 */
4740   {
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4744   },
4745
4746   /* PREFIX_0F3A41 */
4747   {
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4751   },
4752
4753   /* PREFIX_0F3A42 */
4754   {
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4758   },
4759
4760   /* PREFIX_0F3A44 */
4761   {
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4765   },
4766
4767   /* PREFIX_0F3A60 */
4768   {
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4772   },
4773
4774   /* PREFIX_0F3A61 */
4775   {
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4779   },
4780
4781   /* PREFIX_0F3A62 */
4782   {
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4786   },
4787
4788   /* PREFIX_0F3A63 */
4789   {
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4793   },
4794
4795   /* PREFIX_0F3ACC */
4796   {
4797     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4798   },
4799
4800   /* PREFIX_0F3ACE */
4801   {
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4805   },
4806
4807   /* PREFIX_0F3ACF */
4808   {
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4812   },
4813
4814   /* PREFIX_0F3ADF */
4815   {
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4819   },
4820
4821   /* PREFIX_VEX_0F10 */
4822   {
4823     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4824     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4825     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4826     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4827   },
4828
4829   /* PREFIX_VEX_0F11 */
4830   {
4831     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4832     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4833     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4834     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4835   },
4836
4837   /* PREFIX_VEX_0F12 */
4838   {
4839     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4840     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4841     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4842     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4843   },
4844
4845   /* PREFIX_VEX_0F16 */
4846   {
4847     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4848     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4849     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4850   },
4851
4852   /* PREFIX_VEX_0F2A */
4853   {
4854     { Bad_Opcode },
4855     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4856     { Bad_Opcode },
4857     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4858   },
4859
4860   /* PREFIX_VEX_0F2C */
4861   {
4862     { Bad_Opcode },
4863     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4864     { Bad_Opcode },
4865     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4866   },
4867
4868   /* PREFIX_VEX_0F2D */
4869   {
4870     { Bad_Opcode },
4871     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4872     { Bad_Opcode },
4873     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4874   },
4875
4876   /* PREFIX_VEX_0F2E */
4877   {
4878     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4879     { Bad_Opcode },
4880     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4881   },
4882
4883   /* PREFIX_VEX_0F2F */
4884   {
4885     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4886     { Bad_Opcode },
4887     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4888   },
4889
4890   /* PREFIX_VEX_0F41 */
4891   {
4892     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4893     { Bad_Opcode },
4894     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4895   },
4896
4897   /* PREFIX_VEX_0F42 */
4898   {
4899     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4900     { Bad_Opcode },
4901     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4902   },
4903
4904   /* PREFIX_VEX_0F44 */
4905   {
4906     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4907     { Bad_Opcode },
4908     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4909   },
4910
4911   /* PREFIX_VEX_0F45 */
4912   {
4913     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4914     { Bad_Opcode },
4915     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4916   },
4917
4918   /* PREFIX_VEX_0F46 */
4919   {
4920     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4921     { Bad_Opcode },
4922     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4923   },
4924
4925   /* PREFIX_VEX_0F47 */
4926   {
4927     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4928     { Bad_Opcode },
4929     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4930   },
4931
4932   /* PREFIX_VEX_0F4A */
4933   {
4934     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4935     { Bad_Opcode },
4936     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4937   },
4938
4939   /* PREFIX_VEX_0F4B */
4940   {
4941     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4942     { Bad_Opcode },
4943     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F51 */
4947   {
4948     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4949     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4950     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4951     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4952   },
4953
4954   /* PREFIX_VEX_0F52 */
4955   {
4956     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4957     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4958   },
4959
4960   /* PREFIX_VEX_0F53 */
4961   {
4962     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4963     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4964   },
4965
4966   /* PREFIX_VEX_0F58 */
4967   {
4968     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4969     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4970     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4971     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4972   },
4973
4974   /* PREFIX_VEX_0F59 */
4975   {
4976     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4977     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4978     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4979     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4980   },
4981
4982   /* PREFIX_VEX_0F5A */
4983   {
4984     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4985     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4986     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4987     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4988   },
4989
4990   /* PREFIX_VEX_0F5B */
4991   {
4992     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4993     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4994     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_0F5C */
4998   {
4999     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5000     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5001     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5002     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5003   },
5004
5005   /* PREFIX_VEX_0F5D */
5006   {
5007     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5008     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5009     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5010     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5011   },
5012
5013   /* PREFIX_VEX_0F5E */
5014   {
5015     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5016     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5017     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5018     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5019   },
5020
5021   /* PREFIX_VEX_0F5F */
5022   {
5023     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5024     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5025     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5026     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5027   },
5028
5029   /* PREFIX_VEX_0F60 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5034   },
5035
5036   /* PREFIX_VEX_0F61 */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0F62 */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0F63 */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0F64 */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0F65 */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0F66 */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0F67 */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0F68 */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5090   },
5091
5092   /* PREFIX_VEX_0F69 */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5097   },
5098
5099   /* PREFIX_VEX_0F6A */
5100   {
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5104   },
5105
5106   /* PREFIX_VEX_0F6B */
5107   {
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5111   },
5112
5113   /* PREFIX_VEX_0F6C */
5114   {
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5118   },
5119
5120   /* PREFIX_VEX_0F6D */
5121   {
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0F6E */
5128   {
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0F6F */
5135   {
5136     { Bad_Opcode },
5137     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5138     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0F70 */
5142   {
5143     { Bad_Opcode },
5144     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5145     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5146     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5147   },
5148
5149   /* PREFIX_VEX_0F71_REG_2 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0F71_REG_4 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0F71_REG_6 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0F72_REG_2 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0F72_REG_4 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0F72_REG_6 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0F73_REG_2 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0F73_REG_3 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0F73_REG_6 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F73_REG_7 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F74 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F75 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0F76 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0F77 */
5241   {
5242     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5243   },
5244
5245   /* PREFIX_VEX_0F7C */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5250     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5251   },
5252
5253   /* PREFIX_VEX_0F7D */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5258     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5259   },
5260
5261   /* PREFIX_VEX_0F7E */
5262   {
5263     { Bad_Opcode },
5264     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5265     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5266   },
5267
5268   /* PREFIX_VEX_0F7F */
5269   {
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5272     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0F90 */
5276   {
5277     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5278     { Bad_Opcode },
5279     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0F91 */
5283   {
5284     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5285     { Bad_Opcode },
5286     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5287   },
5288
5289   /* PREFIX_VEX_0F92 */
5290   {
5291     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5292     { Bad_Opcode },
5293     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5294     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5295   },
5296
5297   /* PREFIX_VEX_0F93 */
5298   {
5299     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5300     { Bad_Opcode },
5301     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5302     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5303   },
5304
5305   /* PREFIX_VEX_0F98 */
5306   {
5307     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5308     { Bad_Opcode },
5309     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5310   },
5311
5312   /* PREFIX_VEX_0F99 */
5313   {
5314     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5315     { Bad_Opcode },
5316     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5317   },
5318
5319   /* PREFIX_VEX_0FC2 */
5320   {
5321     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5322     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5323     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5324     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5325   },
5326
5327   /* PREFIX_VEX_0FC4 */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5332   },
5333
5334   /* PREFIX_VEX_0FC5 */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5339   },
5340
5341   /* PREFIX_VEX_0FD0 */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5346     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5347   },
5348
5349   /* PREFIX_VEX_0FD1 */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5354   },
5355
5356   /* PREFIX_VEX_0FD2 */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5361   },
5362
5363   /* PREFIX_VEX_0FD3 */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5368   },
5369
5370   /* PREFIX_VEX_0FD4 */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5375   },
5376
5377   /* PREFIX_VEX_0FD5 */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5382   },
5383
5384   /* PREFIX_VEX_0FD6 */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5389   },
5390
5391   /* PREFIX_VEX_0FD7 */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5396   },
5397
5398   /* PREFIX_VEX_0FD8 */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5403   },
5404
5405   /* PREFIX_VEX_0FD9 */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5410   },
5411
5412   /* PREFIX_VEX_0FDA */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5417   },
5418
5419   /* PREFIX_VEX_0FDB */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5424   },
5425
5426   /* PREFIX_VEX_0FDC */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5431   },
5432
5433   /* PREFIX_VEX_0FDD */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5438   },
5439
5440   /* PREFIX_VEX_0FDE */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5445   },
5446
5447   /* PREFIX_VEX_0FDF */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5452   },
5453
5454   /* PREFIX_VEX_0FE0 */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5459   },
5460
5461   /* PREFIX_VEX_0FE1 */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5466   },
5467
5468   /* PREFIX_VEX_0FE2 */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5473   },
5474
5475   /* PREFIX_VEX_0FE3 */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5480   },
5481
5482   /* PREFIX_VEX_0FE4 */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5487   },
5488
5489   /* PREFIX_VEX_0FE5 */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5494   },
5495
5496   /* PREFIX_VEX_0FE6 */
5497   {
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5500     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5501     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5502   },
5503
5504   /* PREFIX_VEX_0FE7 */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5509   },
5510
5511   /* PREFIX_VEX_0FE8 */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5516   },
5517
5518   /* PREFIX_VEX_0FE9 */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5523   },
5524
5525   /* PREFIX_VEX_0FEA */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5530   },
5531
5532   /* PREFIX_VEX_0FEB */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5537   },
5538
5539   /* PREFIX_VEX_0FEC */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5544   },
5545
5546   /* PREFIX_VEX_0FED */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5551   },
5552
5553   /* PREFIX_VEX_0FEE */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5558   },
5559
5560   /* PREFIX_VEX_0FEF */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5565   },
5566
5567   /* PREFIX_VEX_0FF0 */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5573   },
5574
5575   /* PREFIX_VEX_0FF1 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0FF2 */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0FF3 */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0FF4 */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0FF5 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0FF6 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0FF7 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0FF8 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0FF9 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0FFA */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5643   },
5644
5645   /* PREFIX_VEX_0FFB */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5650   },
5651
5652   /* PREFIX_VEX_0FFC */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5657   },
5658
5659   /* PREFIX_VEX_0FFD */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5664   },
5665
5666   /* PREFIX_VEX_0FFE */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5671   },
5672
5673   /* PREFIX_VEX_0F3800 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5678   },
5679
5680   /* PREFIX_VEX_0F3801 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5685   },
5686
5687   /* PREFIX_VEX_0F3802 */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5692   },
5693
5694   /* PREFIX_VEX_0F3803 */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5699   },
5700
5701   /* PREFIX_VEX_0F3804 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5706   },
5707
5708   /* PREFIX_VEX_0F3805 */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5713   },
5714
5715   /* PREFIX_VEX_0F3806 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5720   },
5721
5722   /* PREFIX_VEX_0F3807 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F3808 */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F3809 */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F380A */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F380B */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F380C */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F380D */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5769   },
5770
5771   /* PREFIX_VEX_0F380E */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5776   },
5777
5778   /* PREFIX_VEX_0F380F */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5783   },
5784
5785   /* PREFIX_VEX_0F3813 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5790   },
5791
5792   /* PREFIX_VEX_0F3816 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F3817 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5804   },
5805
5806   /* PREFIX_VEX_0F3818 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F3819 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5818   },
5819
5820   /* PREFIX_VEX_0F381A */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5825   },
5826
5827   /* PREFIX_VEX_0F381C */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5832   },
5833
5834   /* PREFIX_VEX_0F381D */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5839   },
5840
5841   /* PREFIX_VEX_0F381E */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F3820 */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5853   },
5854
5855   /* PREFIX_VEX_0F3821 */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5860   },
5861
5862   /* PREFIX_VEX_0F3822 */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5867   },
5868
5869   /* PREFIX_VEX_0F3823 */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5874   },
5875
5876   /* PREFIX_VEX_0F3824 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5881   },
5882
5883   /* PREFIX_VEX_0F3825 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F3828 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5895   },
5896
5897   /* PREFIX_VEX_0F3829 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5902   },
5903
5904   /* PREFIX_VEX_0F382A */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5909   },
5910
5911   /* PREFIX_VEX_0F382B */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5916   },
5917
5918   /* PREFIX_VEX_0F382C */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F382D */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5930   },
5931
5932   /* PREFIX_VEX_0F382E */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5937   },
5938
5939   /* PREFIX_VEX_0F382F */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5944   },
5945
5946   /* PREFIX_VEX_0F3830 */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5951   },
5952
5953   /* PREFIX_VEX_0F3831 */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F3832 */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5965   },
5966
5967   /* PREFIX_VEX_0F3833 */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5972   },
5973
5974   /* PREFIX_VEX_0F3834 */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5979   },
5980
5981   /* PREFIX_VEX_0F3835 */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5986   },
5987
5988   /* PREFIX_VEX_0F3836 */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5993   },
5994
5995   /* PREFIX_VEX_0F3837 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6000   },
6001
6002   /* PREFIX_VEX_0F3838 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6007   },
6008
6009   /* PREFIX_VEX_0F3839 */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6014   },
6015
6016   /* PREFIX_VEX_0F383A */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6021   },
6022
6023   /* PREFIX_VEX_0F383B */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6028   },
6029
6030   /* PREFIX_VEX_0F383C */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6035   },
6036
6037   /* PREFIX_VEX_0F383D */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6042   },
6043
6044   /* PREFIX_VEX_0F383E */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6049   },
6050
6051   /* PREFIX_VEX_0F383F */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6056   },
6057
6058   /* PREFIX_VEX_0F3840 */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6063   },
6064
6065   /* PREFIX_VEX_0F3841 */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6070   },
6071
6072   /* PREFIX_VEX_0F3845 */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6077   },
6078
6079   /* PREFIX_VEX_0F3846 */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6084   },
6085
6086   /* PREFIX_VEX_0F3847 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F3858 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6098   },
6099
6100   /* PREFIX_VEX_0F3859 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6105   },
6106
6107   /* PREFIX_VEX_0F385A */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6112   },
6113
6114   /* PREFIX_VEX_0F3878 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6119   },
6120
6121   /* PREFIX_VEX_0F3879 */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6126   },
6127
6128   /* PREFIX_VEX_0F388C */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6133   },
6134
6135   /* PREFIX_VEX_0F388E */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6140   },
6141
6142   /* PREFIX_VEX_0F3890 */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F3891 */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F3892 */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F3893 */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F3896 */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F3897 */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6182   },
6183
6184   /* PREFIX_VEX_0F3898 */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6189   },
6190
6191   /* PREFIX_VEX_0F3899 */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6196   },
6197
6198   /* PREFIX_VEX_0F389A */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6203   },
6204
6205   /* PREFIX_VEX_0F389B */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6210   },
6211
6212   /* PREFIX_VEX_0F389C */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6217   },
6218
6219   /* PREFIX_VEX_0F389D */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6224   },
6225
6226   /* PREFIX_VEX_0F389E */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6231   },
6232
6233   /* PREFIX_VEX_0F389F */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6238   },
6239
6240   /* PREFIX_VEX_0F38A6 */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6245     { Bad_Opcode },
6246   },
6247
6248   /* PREFIX_VEX_0F38A7 */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6253   },
6254
6255   /* PREFIX_VEX_0F38A8 */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6260   },
6261
6262   /* PREFIX_VEX_0F38A9 */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6267   },
6268
6269   /* PREFIX_VEX_0F38AA */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6274   },
6275
6276   /* PREFIX_VEX_0F38AB */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6281   },
6282
6283   /* PREFIX_VEX_0F38AC */
6284   {
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6288   },
6289
6290   /* PREFIX_VEX_0F38AD */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6295   },
6296
6297   /* PREFIX_VEX_0F38AE */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6302   },
6303
6304   /* PREFIX_VEX_0F38AF */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6309   },
6310
6311   /* PREFIX_VEX_0F38B6 */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6316   },
6317
6318   /* PREFIX_VEX_0F38B7 */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6323   },
6324
6325   /* PREFIX_VEX_0F38B8 */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6330   },
6331
6332   /* PREFIX_VEX_0F38B9 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6337   },
6338
6339   /* PREFIX_VEX_0F38BA */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6344   },
6345
6346   /* PREFIX_VEX_0F38BB */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6351   },
6352
6353   /* PREFIX_VEX_0F38BC */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6358   },
6359
6360   /* PREFIX_VEX_0F38BD */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6365   },
6366
6367   /* PREFIX_VEX_0F38BE */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6372   },
6373
6374   /* PREFIX_VEX_0F38BF */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6379   },
6380
6381   /* PREFIX_VEX_0F38CF */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6386   },
6387
6388   /* PREFIX_VEX_0F38DB */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6393   },
6394
6395   /* PREFIX_VEX_0F38DC */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { "vaesenc",        { XM, Vex, EXx }, 0 },
6400   },
6401
6402   /* PREFIX_VEX_0F38DD */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6407   },
6408
6409   /* PREFIX_VEX_0F38DE */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { "vaesdec",        { XM, Vex, EXx }, 0 },
6414   },
6415
6416   /* PREFIX_VEX_0F38DF */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6421   },
6422
6423   /* PREFIX_VEX_0F38F2 */
6424   {
6425     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6426   },
6427
6428   /* PREFIX_VEX_0F38F3_REG_1 */
6429   {
6430     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6431   },
6432
6433   /* PREFIX_VEX_0F38F3_REG_2 */
6434   {
6435     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6436   },
6437
6438   /* PREFIX_VEX_0F38F3_REG_3 */
6439   {
6440     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6441   },
6442
6443   /* PREFIX_VEX_0F38F5 */
6444   {
6445     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6446     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6447     { Bad_Opcode },
6448     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6449   },
6450
6451   /* PREFIX_VEX_0F38F6 */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6457   },
6458
6459   /* PREFIX_VEX_0F38F7 */
6460   {
6461     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6462     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6463     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6464     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6465   },
6466
6467   /* PREFIX_VEX_0F3A00 */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A01 */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6479   },
6480
6481   /* PREFIX_VEX_0F3A02 */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6486   },
6487
6488   /* PREFIX_VEX_0F3A04 */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6493   },
6494
6495   /* PREFIX_VEX_0F3A05 */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6500   },
6501
6502   /* PREFIX_VEX_0F3A06 */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6507   },
6508
6509   /* PREFIX_VEX_0F3A08 */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6514   },
6515
6516   /* PREFIX_VEX_0F3A09 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6521   },
6522
6523   /* PREFIX_VEX_0F3A0A */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6528   },
6529
6530   /* PREFIX_VEX_0F3A0B */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6535   },
6536
6537   /* PREFIX_VEX_0F3A0C */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6542   },
6543
6544   /* PREFIX_VEX_0F3A0D */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6549   },
6550
6551   /* PREFIX_VEX_0F3A0E */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6556   },
6557
6558   /* PREFIX_VEX_0F3A0F */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A14 */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A15 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A16 */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A17 */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6591   },
6592
6593   /* PREFIX_VEX_0F3A18 */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6598   },
6599
6600   /* PREFIX_VEX_0F3A19 */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6605   },
6606
6607   /* PREFIX_VEX_0F3A1D */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6612   },
6613
6614   /* PREFIX_VEX_0F3A20 */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3A21 */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3A22 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A30 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A31 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A32 */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6654   },
6655
6656   /* PREFIX_VEX_0F3A33 */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6661   },
6662
6663   /* PREFIX_VEX_0F3A38 */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A39 */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6675   },
6676
6677   /* PREFIX_VEX_0F3A40 */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6682   },
6683
6684   /* PREFIX_VEX_0F3A41 */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6689   },
6690
6691   /* PREFIX_VEX_0F3A42 */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6696   },
6697
6698   /* PREFIX_VEX_0F3A44 */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6703   },
6704
6705   /* PREFIX_VEX_0F3A46 */
6706   {
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6710   },
6711
6712   /* PREFIX_VEX_0F3A48 */
6713   {
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6717   },
6718
6719   /* PREFIX_VEX_0F3A49 */
6720   {
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6724   },
6725
6726   /* PREFIX_VEX_0F3A4A */
6727   {
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6731   },
6732
6733   /* PREFIX_VEX_0F3A4B */
6734   {
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6738   },
6739
6740   /* PREFIX_VEX_0F3A4C */
6741   {
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6745   },
6746
6747   /* PREFIX_VEX_0F3A5C */
6748   {
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6752   },
6753
6754   /* PREFIX_VEX_0F3A5D */
6755   {
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6759   },
6760
6761   /* PREFIX_VEX_0F3A5E */
6762   {
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6766   },
6767
6768   /* PREFIX_VEX_0F3A5F */
6769   {
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6773   },
6774
6775   /* PREFIX_VEX_0F3A60 */
6776   {
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6780     { Bad_Opcode },
6781   },
6782
6783   /* PREFIX_VEX_0F3A61 */
6784   {
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6788   },
6789
6790   /* PREFIX_VEX_0F3A62 */
6791   {
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6795   },
6796
6797   /* PREFIX_VEX_0F3A63 */
6798   {
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6802   },
6803
6804   /* PREFIX_VEX_0F3A68 */
6805   {
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6809   },
6810
6811   /* PREFIX_VEX_0F3A69 */
6812   {
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6816   },
6817
6818   /* PREFIX_VEX_0F3A6A */
6819   {
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6823   },
6824
6825   /* PREFIX_VEX_0F3A6B */
6826   {
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6830   },
6831
6832   /* PREFIX_VEX_0F3A6C */
6833   {
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6837   },
6838
6839   /* PREFIX_VEX_0F3A6D */
6840   {
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6844   },
6845
6846   /* PREFIX_VEX_0F3A6E */
6847   {
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6851   },
6852
6853   /* PREFIX_VEX_0F3A6F */
6854   {
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6858   },
6859
6860   /* PREFIX_VEX_0F3A78 */
6861   {
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6865   },
6866
6867   /* PREFIX_VEX_0F3A79 */
6868   {
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6872   },
6873
6874   /* PREFIX_VEX_0F3A7A */
6875   {
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6879   },
6880
6881   /* PREFIX_VEX_0F3A7B */
6882   {
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6886   },
6887
6888   /* PREFIX_VEX_0F3A7C */
6889   {
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6893     { Bad_Opcode },
6894   },
6895
6896   /* PREFIX_VEX_0F3A7D */
6897   {
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6901   },
6902
6903   /* PREFIX_VEX_0F3A7E */
6904   {
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6908   },
6909
6910   /* PREFIX_VEX_0F3A7F */
6911   {
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6915   },
6916
6917   /* PREFIX_VEX_0F3ACE */
6918   {
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6922   },
6923
6924   /* PREFIX_VEX_0F3ACF */
6925   {
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6929   },
6930
6931   /* PREFIX_VEX_0F3ADF */
6932   {
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6936   },
6937
6938   /* PREFIX_VEX_0F3AF0 */
6939   {
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6944   },
6945
6946 #define NEED_PREFIX_TABLE
6947 #include "i386-dis-evex.h"
6948 #undef NEED_PREFIX_TABLE
6949 };
6950
6951 static const struct dis386 x86_64_table[][2] = {
6952   /* X86_64_06 */
6953   {
6954     { "pushP", { es }, 0 },
6955   },
6956
6957   /* X86_64_07 */
6958   {
6959     { "popP", { es }, 0 },
6960   },
6961
6962   /* X86_64_0D */
6963   {
6964     { "pushP", { cs }, 0 },
6965   },
6966
6967   /* X86_64_16 */
6968   {
6969     { "pushP", { ss }, 0 },
6970   },
6971
6972   /* X86_64_17 */
6973   {
6974     { "popP", { ss }, 0 },
6975   },
6976
6977   /* X86_64_1E */
6978   {
6979     { "pushP", { ds }, 0 },
6980   },
6981
6982   /* X86_64_1F */
6983   {
6984     { "popP", { ds }, 0 },
6985   },
6986
6987   /* X86_64_27 */
6988   {
6989     { "daa", { XX }, 0 },
6990   },
6991
6992   /* X86_64_2F */
6993   {
6994     { "das", { XX }, 0 },
6995   },
6996
6997   /* X86_64_37 */
6998   {
6999     { "aaa", { XX }, 0 },
7000   },
7001
7002   /* X86_64_3F */
7003   {
7004     { "aas", { XX }, 0 },
7005   },
7006
7007   /* X86_64_60 */
7008   {
7009     { "pushaP", { XX }, 0 },
7010   },
7011
7012   /* X86_64_61 */
7013   {
7014     { "popaP", { XX }, 0 },
7015   },
7016
7017   /* X86_64_62 */
7018   {
7019     { MOD_TABLE (MOD_62_32BIT) },
7020     { EVEX_TABLE (EVEX_0F) },
7021   },
7022
7023   /* X86_64_63 */
7024   {
7025     { "arpl", { Ew, Gw }, 0 },
7026     { "movs{lq|xd}", { Gv, Ed }, 0 },
7027   },
7028
7029   /* X86_64_6D */
7030   {
7031     { "ins{R|}", { Yzr, indirDX }, 0 },
7032     { "ins{G|}", { Yzr, indirDX }, 0 },
7033   },
7034
7035   /* X86_64_6F */
7036   {
7037     { "outs{R|}", { indirDXr, Xz }, 0 },
7038     { "outs{G|}", { indirDXr, Xz }, 0 },
7039   },
7040
7041   /* X86_64_82 */
7042   {
7043     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7044     { REG_TABLE (REG_80) },
7045   },
7046
7047   /* X86_64_9A */
7048   {
7049     { "Jcall{T|}", { Ap }, 0 },
7050   },
7051
7052   /* X86_64_C4 */
7053   {
7054     { MOD_TABLE (MOD_C4_32BIT) },
7055     { VEX_C4_TABLE (VEX_0F) },
7056   },
7057
7058   /* X86_64_C5 */
7059   {
7060     { MOD_TABLE (MOD_C5_32BIT) },
7061     { VEX_C5_TABLE (VEX_0F) },
7062   },
7063
7064   /* X86_64_CE */
7065   {
7066     { "into", { XX }, 0 },
7067   },
7068
7069   /* X86_64_D4 */
7070   {
7071     { "aam", { Ib }, 0 },
7072   },
7073
7074   /* X86_64_D5 */
7075   {
7076     { "aad", { Ib }, 0 },
7077   },
7078
7079   /* X86_64_E8 */
7080   {
7081     { "callP",          { Jv, BND }, 0 },
7082     { "call@",          { Jv, BND }, 0 }
7083   },
7084
7085   /* X86_64_E9 */
7086   {
7087     { "jmpP",           { Jv, BND }, 0 },
7088     { "jmp@",           { Jv, BND }, 0 }
7089   },
7090
7091   /* X86_64_EA */
7092   {
7093     { "Jjmp{T|}", { Ap }, 0 },
7094   },
7095
7096   /* X86_64_0F01_REG_0 */
7097   {
7098     { "sgdt{Q|IQ}", { M }, 0 },
7099     { "sgdt", { M }, 0 },
7100   },
7101
7102   /* X86_64_0F01_REG_1 */
7103   {
7104     { "sidt{Q|IQ}", { M }, 0 },
7105     { "sidt", { M }, 0 },
7106   },
7107
7108   /* X86_64_0F01_REG_2 */
7109   {
7110     { "lgdt{Q|Q}", { M }, 0 },
7111     { "lgdt", { M }, 0 },
7112   },
7113
7114   /* X86_64_0F01_REG_3 */
7115   {
7116     { "lidt{Q|Q}", { M }, 0 },
7117     { "lidt", { M }, 0 },
7118   },
7119 };
7120
7121 static const struct dis386 three_byte_table[][256] = {
7122
7123   /* THREE_BYTE_0F38 */
7124   {
7125     /* 00 */
7126     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7127     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7128     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7129     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7130     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7131     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7132     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7133     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7134     /* 08 */
7135     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7136     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7137     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7138     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* 10 */
7144     { PREFIX_TABLE (PREFIX_0F3810) },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { PREFIX_TABLE (PREFIX_0F3814) },
7149     { PREFIX_TABLE (PREFIX_0F3815) },
7150     { Bad_Opcode },
7151     { PREFIX_TABLE (PREFIX_0F3817) },
7152     /* 18 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7158     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7159     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7160     { Bad_Opcode },
7161     /* 20 */
7162     { PREFIX_TABLE (PREFIX_0F3820) },
7163     { PREFIX_TABLE (PREFIX_0F3821) },
7164     { PREFIX_TABLE (PREFIX_0F3822) },
7165     { PREFIX_TABLE (PREFIX_0F3823) },
7166     { PREFIX_TABLE (PREFIX_0F3824) },
7167     { PREFIX_TABLE (PREFIX_0F3825) },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* 28 */
7171     { PREFIX_TABLE (PREFIX_0F3828) },
7172     { PREFIX_TABLE (PREFIX_0F3829) },
7173     { PREFIX_TABLE (PREFIX_0F382A) },
7174     { PREFIX_TABLE (PREFIX_0F382B) },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* 30 */
7180     { PREFIX_TABLE (PREFIX_0F3830) },
7181     { PREFIX_TABLE (PREFIX_0F3831) },
7182     { PREFIX_TABLE (PREFIX_0F3832) },
7183     { PREFIX_TABLE (PREFIX_0F3833) },
7184     { PREFIX_TABLE (PREFIX_0F3834) },
7185     { PREFIX_TABLE (PREFIX_0F3835) },
7186     { Bad_Opcode },
7187     { PREFIX_TABLE (PREFIX_0F3837) },
7188     /* 38 */
7189     { PREFIX_TABLE (PREFIX_0F3838) },
7190     { PREFIX_TABLE (PREFIX_0F3839) },
7191     { PREFIX_TABLE (PREFIX_0F383A) },
7192     { PREFIX_TABLE (PREFIX_0F383B) },
7193     { PREFIX_TABLE (PREFIX_0F383C) },
7194     { PREFIX_TABLE (PREFIX_0F383D) },
7195     { PREFIX_TABLE (PREFIX_0F383E) },
7196     { PREFIX_TABLE (PREFIX_0F383F) },
7197     /* 40 */
7198     { PREFIX_TABLE (PREFIX_0F3840) },
7199     { PREFIX_TABLE (PREFIX_0F3841) },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* 48 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* 50 */
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     /* 58 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* 60 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* 68 */
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     /* 70 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     /* 78 */
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     /* 80 */
7270     { PREFIX_TABLE (PREFIX_0F3880) },
7271     { PREFIX_TABLE (PREFIX_0F3881) },
7272     { PREFIX_TABLE (PREFIX_0F3882) },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     /* 88 */
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     /* 90 */
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     /* 98 */
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     /* a0 */
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     /* a8 */
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     /* b0 */
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     /* b8 */
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     /* c0 */
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     /* c8 */
7351     { PREFIX_TABLE (PREFIX_0F38C8) },
7352     { PREFIX_TABLE (PREFIX_0F38C9) },
7353     { PREFIX_TABLE (PREFIX_0F38CA) },
7354     { PREFIX_TABLE (PREFIX_0F38CB) },
7355     { PREFIX_TABLE (PREFIX_0F38CC) },
7356     { PREFIX_TABLE (PREFIX_0F38CD) },
7357     { Bad_Opcode },
7358     { PREFIX_TABLE (PREFIX_0F38CF) },
7359     /* d0 */
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     /* d8 */
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { PREFIX_TABLE (PREFIX_0F38DB) },
7373     { PREFIX_TABLE (PREFIX_0F38DC) },
7374     { PREFIX_TABLE (PREFIX_0F38DD) },
7375     { PREFIX_TABLE (PREFIX_0F38DE) },
7376     { PREFIX_TABLE (PREFIX_0F38DF) },
7377     /* e0 */
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     /* e8 */
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     /* f0 */
7396     { PREFIX_TABLE (PREFIX_0F38F0) },
7397     { PREFIX_TABLE (PREFIX_0F38F1) },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { PREFIX_TABLE (PREFIX_0F38F5) },
7402     { PREFIX_TABLE (PREFIX_0F38F6) },
7403     { Bad_Opcode },
7404     /* f8 */
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413   },
7414   /* THREE_BYTE_0F3A */
7415   {
7416     /* 00 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* 08 */
7426     { PREFIX_TABLE (PREFIX_0F3A08) },
7427     { PREFIX_TABLE (PREFIX_0F3A09) },
7428     { PREFIX_TABLE (PREFIX_0F3A0A) },
7429     { PREFIX_TABLE (PREFIX_0F3A0B) },
7430     { PREFIX_TABLE (PREFIX_0F3A0C) },
7431     { PREFIX_TABLE (PREFIX_0F3A0D) },
7432     { PREFIX_TABLE (PREFIX_0F3A0E) },
7433     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7434     /* 10 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { PREFIX_TABLE (PREFIX_0F3A14) },
7440     { PREFIX_TABLE (PREFIX_0F3A15) },
7441     { PREFIX_TABLE (PREFIX_0F3A16) },
7442     { PREFIX_TABLE (PREFIX_0F3A17) },
7443     /* 18 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* 20 */
7453     { PREFIX_TABLE (PREFIX_0F3A20) },
7454     { PREFIX_TABLE (PREFIX_0F3A21) },
7455     { PREFIX_TABLE (PREFIX_0F3A22) },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* 28 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* 30 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* 38 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* 40 */
7489     { PREFIX_TABLE (PREFIX_0F3A40) },
7490     { PREFIX_TABLE (PREFIX_0F3A41) },
7491     { PREFIX_TABLE (PREFIX_0F3A42) },
7492     { Bad_Opcode },
7493     { PREFIX_TABLE (PREFIX_0F3A44) },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* 48 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* 50 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     /* 58 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* 60 */
7525     { PREFIX_TABLE (PREFIX_0F3A60) },
7526     { PREFIX_TABLE (PREFIX_0F3A61) },
7527     { PREFIX_TABLE (PREFIX_0F3A62) },
7528     { PREFIX_TABLE (PREFIX_0F3A63) },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     /* 68 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* 70 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     /* 78 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* 80 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 88 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 90 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 98 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* a0 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* a8 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* b0 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* b8 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* c0 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* c8 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { PREFIX_TABLE (PREFIX_0F3ACC) },
7647     { Bad_Opcode },
7648     { PREFIX_TABLE (PREFIX_0F3ACE) },
7649     { PREFIX_TABLE (PREFIX_0F3ACF) },
7650     /* d0 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* d8 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { PREFIX_TABLE (PREFIX_0F3ADF) },
7668     /* e0 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* e8 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* f0 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* f8 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704   },
7705 };
7706
7707 static const struct dis386 xop_table[][256] = {
7708   /* XOP_08 */
7709   {
7710     /* 00 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* 08 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* 10 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* 18 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* 20 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* 28 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     /* 30 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* 38 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* 40 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* 48 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* 50 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* 58 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* 60 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* 68 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* 70 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* 78 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* 80 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7861     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7862     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7863     /* 88 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7871     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7872     /* 90 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7879     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7880     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7881     /* 98 */
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7889     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7890     /* a0 */
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7894     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7898     { Bad_Opcode },
7899     /* a8 */
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     /* b0 */
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7916     { Bad_Opcode },
7917     /* b8 */
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     /* c0 */
7927     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7928     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7929     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7930     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     /* c8 */
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7941     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7942     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7943     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7944     /* d0 */
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     /* d8 */
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     /* e0 */
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     /* e8 */
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7977     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7978     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7979     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7980     /* f0 */
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     /* f8 */
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998   },
7999   /* XOP_09 */
8000   {
8001     /* 00 */
8002     { Bad_Opcode },
8003     { REG_TABLE (REG_XOP_TBM_01) },
8004     { REG_TABLE (REG_XOP_TBM_02) },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* 08 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* 10 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { REG_TABLE (REG_XOP_LWPCB) },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* 18 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* 20 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* 28 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* 30 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* 38 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* 40 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* 48 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* 50 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* 58 */
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* 60 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* 68 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* 70 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     /* 78 */
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* 80 */
8146     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8147     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8148     { "vfrczss",        { XM, EXd }, 0 },
8149     { "vfrczsd",        { XM, EXq }, 0 },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     /* 88 */
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     /* 90 */
8164     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8165     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8166     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8167     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8168     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8169     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8170     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8171     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8172     /* 98 */
8173     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8176     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     /* a0 */
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     /* a8 */
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     /* b0 */
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     /* b8 */
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     /* c0 */
8218     { Bad_Opcode },
8219     { "vphaddbw",       { XM, EXxmm }, 0 },
8220     { "vphaddbd",       { XM, EXxmm }, 0 },
8221     { "vphaddbq",       { XM, EXxmm }, 0 },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { "vphaddwd",       { XM, EXxmm }, 0 },
8225     { "vphaddwq",       { XM, EXxmm }, 0 },
8226     /* c8 */
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { "vphadddq",       { XM, EXxmm }, 0 },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     /* d0 */
8236     { Bad_Opcode },
8237     { "vphaddubw",      { XM, EXxmm }, 0 },
8238     { "vphaddubd",      { XM, EXxmm }, 0 },
8239     { "vphaddubq",      { XM, EXxmm }, 0 },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { "vphadduwd",      { XM, EXxmm }, 0 },
8243     { "vphadduwq",      { XM, EXxmm }, 0 },
8244     /* d8 */
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { "vphaddudq",      { XM, EXxmm }, 0 },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     /* e0 */
8254     { Bad_Opcode },
8255     { "vphsubbw",       { XM, EXxmm }, 0 },
8256     { "vphsubwd",       { XM, EXxmm }, 0 },
8257     { "vphsubdq",       { XM, EXxmm }, 0 },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     /* e8 */
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     /* f0 */
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     /* f8 */
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289   },
8290   /* XOP_0A */
8291   {
8292     /* 00 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* 08 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* 10 */
8311     { "bextr",  { Gv, Ev, Iq }, 0 },
8312     { Bad_Opcode },
8313     { REG_TABLE (REG_XOP_LWP) },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* 18 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* 20 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* 28 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* 30 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* 38 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* 40 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* 48 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* 50 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* 58 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* 60 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* 68 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* 70 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     /* 78 */
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     /* 80 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* 88 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* 90 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* 98 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* a0 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* a8 */
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     /* b0 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* b8 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     /* c0 */
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     /* c8 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* d0 */
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     /* d8 */
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     /* e0 */
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     /* e8 */
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     /* f0 */
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     /* f8 */
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580   },
8581 };
8582
8583 static const struct dis386 vex_table[][256] = {
8584   /* VEX_0F */
8585   {
8586     /* 00 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* 08 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* 10 */
8605     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8608     { MOD_TABLE (MOD_VEX_0F13) },
8609     { VEX_W_TABLE (VEX_W_0F14) },
8610     { VEX_W_TABLE (VEX_W_0F15) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8612     { MOD_TABLE (MOD_VEX_0F17) },
8613     /* 18 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* 20 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* 28 */
8632     { VEX_W_TABLE (VEX_W_0F28) },
8633     { VEX_W_TABLE (VEX_W_0F29) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8635     { MOD_TABLE (MOD_VEX_0F2B) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8640     /* 30 */
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     /* 38 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* 40 */
8659     { Bad_Opcode },
8660     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8662     { Bad_Opcode },
8663     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8667     /* 48 */
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     /* 50 */
8677     { MOD_TABLE (MOD_VEX_0F50) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8681     { "vandpX",         { XM, Vex, EXx }, 0 },
8682     { "vandnpX",        { XM, Vex, EXx }, 0 },
8683     { "vorpX",          { XM, Vex, EXx }, 0 },
8684     { "vxorpX",         { XM, Vex, EXx }, 0 },
8685     /* 58 */
8686     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8694     /* 60 */
8695     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8703     /* 68 */
8704     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8712     /* 70 */
8713     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8714     { REG_TABLE (REG_VEX_0F71) },
8715     { REG_TABLE (REG_VEX_0F72) },
8716     { REG_TABLE (REG_VEX_0F73) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8721     /* 78 */
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8730     /* 80 */
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     /* 88 */
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     /* 90 */
8749     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     /* 98 */
8758     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     /* a0 */
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     /* a8 */
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { REG_TABLE (REG_VEX_0FAE) },
8783     { Bad_Opcode },
8784     /* b0 */
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     /* b8 */
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     /* c0 */
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8806     { Bad_Opcode },
8807     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8808     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8809     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8810     { Bad_Opcode },
8811     /* c8 */
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     /* d0 */
8821     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8822     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8823     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8824     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8825     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8826     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8829     /* d8 */
8830     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8832     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8838     /* e0 */
8839     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8847     /* e8 */
8848     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8856     /* f0 */
8857     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8865     /* f8 */
8866     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8873     { Bad_Opcode },
8874   },
8875   /* VEX_0F38 */
8876   {
8877     /* 00 */
8878     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8886     /* 08 */
8887     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8895     /* 10 */
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8904     /* 18 */
8905     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8908     { Bad_Opcode },
8909     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8912     { Bad_Opcode },
8913     /* 20 */
8914     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     /* 28 */
8923     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8931     /* 30 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8940     /* 38 */
8941     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8949     /* 40 */
8950     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8958     /* 48 */
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     /* 50 */
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     /* 58 */
8977     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     /* 60 */
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     /* 68 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     /* 70 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     /* 78 */
9013     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     /* 80 */
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     /* 88 */
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9036     { Bad_Opcode },
9037     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9038     { Bad_Opcode },
9039     /* 90 */
9040     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9048     /* 98 */
9049     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9057     /* a0 */
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9066     /* a8 */
9067     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9075     /* b0 */
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9084     /* b8 */
9085     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9093     /* c0 */
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     /* c8 */
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9111     /* d0 */
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     /* d8 */
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9129     /* e0 */
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     /* e8 */
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     /* f0 */
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9151     { REG_TABLE (REG_VEX_0F38F3) },
9152     { Bad_Opcode },
9153     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9156     /* f8 */
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165   },
9166   /* VEX_0F3A */
9167   {
9168     /* 00 */
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9172     { Bad_Opcode },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9176     { Bad_Opcode },
9177     /* 08 */
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9186     /* 10 */
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9195     /* 18 */
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     /* 20 */
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9207     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* 28 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* 30 */
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* 38 */
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* 40 */
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9244     { Bad_Opcode },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9246     { Bad_Opcode },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9248     { Bad_Opcode },
9249     /* 48 */
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* 50 */
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     /* 58 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9276     /* 60 */
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9279     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     /* 68 */
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9294     /* 70 */
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     /* 78 */
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9305     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9312     /* 80 */
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     /* 88 */
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     /* 90 */
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     /* 98 */
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     /* a0 */
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     /* a8 */
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     /* b0 */
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     /* b8 */
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     /* c0 */
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     /* c8 */
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9401     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9402     /* d0 */
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     /* d8 */
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9420     /* e0 */
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     /* e8 */
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     /* f0 */
9439     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     /* f8 */
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456   },
9457 };
9458
9459 #define NEED_OPCODE_TABLE
9460 #include "i386-dis-evex.h"
9461 #undef NEED_OPCODE_TABLE
9462 static const struct dis386 vex_len_table[][2] = {
9463   /* VEX_LEN_0F10_P_1 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9466     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9467   },
9468
9469   /* VEX_LEN_0F10_P_3 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9472     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9473   },
9474
9475   /* VEX_LEN_0F11_P_1 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9478     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9479   },
9480
9481   /* VEX_LEN_0F11_P_3 */
9482   {
9483     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9484     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9485   },
9486
9487   /* VEX_LEN_0F12_P_0_M_0 */
9488   {
9489     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9490   },
9491
9492   /* VEX_LEN_0F12_P_0_M_1 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9495   },
9496
9497   /* VEX_LEN_0F12_P_2 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9500   },
9501
9502   /* VEX_LEN_0F13_M_0 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9505   },
9506
9507   /* VEX_LEN_0F16_P_0_M_0 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9510   },
9511
9512   /* VEX_LEN_0F16_P_0_M_1 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9515   },
9516
9517   /* VEX_LEN_0F16_P_2 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9520   },
9521
9522   /* VEX_LEN_0F17_M_0 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9525   },
9526
9527   /* VEX_LEN_0F2A_P_1 */
9528   {
9529     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9530     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9531   },
9532
9533   /* VEX_LEN_0F2A_P_3 */
9534   {
9535     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9536     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9537   },
9538
9539   /* VEX_LEN_0F2C_P_1 */
9540   {
9541     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9542     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9543   },
9544
9545   /* VEX_LEN_0F2C_P_3 */
9546   {
9547     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9548     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9549   },
9550
9551   /* VEX_LEN_0F2D_P_1 */
9552   {
9553     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9554     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9555   },
9556
9557   /* VEX_LEN_0F2D_P_3 */
9558   {
9559     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9560     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9561   },
9562
9563   /* VEX_LEN_0F2E_P_0 */
9564   {
9565     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9566     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9567   },
9568
9569   /* VEX_LEN_0F2E_P_2 */
9570   {
9571     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9572     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9573   },
9574
9575   /* VEX_LEN_0F2F_P_0 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9578     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9579   },
9580
9581   /* VEX_LEN_0F2F_P_2 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9584     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9585   },
9586
9587   /* VEX_LEN_0F41_P_0 */
9588   {
9589     { Bad_Opcode },
9590     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9591   },
9592   /* VEX_LEN_0F41_P_2 */
9593   {
9594     { Bad_Opcode },
9595     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9596   },
9597   /* VEX_LEN_0F42_P_0 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9601   },
9602   /* VEX_LEN_0F42_P_2 */
9603   {
9604     { Bad_Opcode },
9605     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9606   },
9607   /* VEX_LEN_0F44_P_0 */
9608   {
9609     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9610   },
9611   /* VEX_LEN_0F44_P_2 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9614   },
9615   /* VEX_LEN_0F45_P_0 */
9616   {
9617     { Bad_Opcode },
9618     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9619   },
9620   /* VEX_LEN_0F45_P_2 */
9621   {
9622     { Bad_Opcode },
9623     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9624   },
9625   /* VEX_LEN_0F46_P_0 */
9626   {
9627     { Bad_Opcode },
9628     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9629   },
9630   /* VEX_LEN_0F46_P_2 */
9631   {
9632     { Bad_Opcode },
9633     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9634   },
9635   /* VEX_LEN_0F47_P_0 */
9636   {
9637     { Bad_Opcode },
9638     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9639   },
9640   /* VEX_LEN_0F47_P_2 */
9641   {
9642     { Bad_Opcode },
9643     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9644   },
9645   /* VEX_LEN_0F4A_P_0 */
9646   {
9647     { Bad_Opcode },
9648     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9649   },
9650   /* VEX_LEN_0F4A_P_2 */
9651   {
9652     { Bad_Opcode },
9653     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9654   },
9655   /* VEX_LEN_0F4B_P_0 */
9656   {
9657     { Bad_Opcode },
9658     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9659   },
9660   /* VEX_LEN_0F4B_P_2 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9664   },
9665
9666   /* VEX_LEN_0F51_P_1 */
9667   {
9668     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9669     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9670   },
9671
9672   /* VEX_LEN_0F51_P_3 */
9673   {
9674     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9675     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9676   },
9677
9678   /* VEX_LEN_0F52_P_1 */
9679   {
9680     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9681     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9682   },
9683
9684   /* VEX_LEN_0F53_P_1 */
9685   {
9686     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9687     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9688   },
9689
9690   /* VEX_LEN_0F58_P_1 */
9691   {
9692     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9693     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9694   },
9695
9696   /* VEX_LEN_0F58_P_3 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9699     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9700   },
9701
9702   /* VEX_LEN_0F59_P_1 */
9703   {
9704     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9705     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9706   },
9707
9708   /* VEX_LEN_0F59_P_3 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9711     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9712   },
9713
9714   /* VEX_LEN_0F5A_P_1 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9717     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9718   },
9719
9720   /* VEX_LEN_0F5A_P_3 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9723     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9724   },
9725
9726   /* VEX_LEN_0F5C_P_1 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9729     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9730   },
9731
9732   /* VEX_LEN_0F5C_P_3 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9735     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9736   },
9737
9738   /* VEX_LEN_0F5D_P_1 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9741     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9742   },
9743
9744   /* VEX_LEN_0F5D_P_3 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9747     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9748   },
9749
9750   /* VEX_LEN_0F5E_P_1 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9753     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9754   },
9755
9756   /* VEX_LEN_0F5E_P_3 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9759     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9760   },
9761
9762   /* VEX_LEN_0F5F_P_1 */
9763   {
9764     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9765     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9766   },
9767
9768   /* VEX_LEN_0F5F_P_3 */
9769   {
9770     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9771     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9772   },
9773
9774   /* VEX_LEN_0F6E_P_2 */
9775   {
9776     { "vmovK",          { XMScalar, Edq }, 0 },
9777     { "vmovK",          { XMScalar, Edq }, 0 },
9778   },
9779
9780   /* VEX_LEN_0F7E_P_1 */
9781   {
9782     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9783     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9784   },
9785
9786   /* VEX_LEN_0F7E_P_2 */
9787   {
9788     { "vmovK",          { Edq, XMScalar }, 0 },
9789     { "vmovK",          { Edq, XMScalar }, 0 },
9790   },
9791
9792   /* VEX_LEN_0F90_P_0 */
9793   {
9794     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9795   },
9796
9797   /* VEX_LEN_0F90_P_2 */
9798   {
9799     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9800   },
9801
9802   /* VEX_LEN_0F91_P_0 */
9803   {
9804     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9805   },
9806
9807   /* VEX_LEN_0F91_P_2 */
9808   {
9809     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9810   },
9811
9812   /* VEX_LEN_0F92_P_0 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9815   },
9816
9817   /* VEX_LEN_0F92_P_2 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9820   },
9821
9822   /* VEX_LEN_0F92_P_3 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9825   },
9826
9827   /* VEX_LEN_0F93_P_0 */
9828   {
9829     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9830   },
9831
9832   /* VEX_LEN_0F93_P_2 */
9833   {
9834     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9835   },
9836
9837   /* VEX_LEN_0F93_P_3 */
9838   {
9839     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9840   },
9841
9842   /* VEX_LEN_0F98_P_0 */
9843   {
9844     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9845   },
9846
9847   /* VEX_LEN_0F98_P_2 */
9848   {
9849     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9850   },
9851
9852   /* VEX_LEN_0F99_P_0 */
9853   {
9854     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9855   },
9856
9857   /* VEX_LEN_0F99_P_2 */
9858   {
9859     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9860   },
9861
9862   /* VEX_LEN_0FAE_R_2_M_0 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9865   },
9866
9867   /* VEX_LEN_0FAE_R_3_M_0 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9870   },
9871
9872   /* VEX_LEN_0FC2_P_1 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9875     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9876   },
9877
9878   /* VEX_LEN_0FC2_P_3 */
9879   {
9880     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9881     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9882   },
9883
9884   /* VEX_LEN_0FC4_P_2 */
9885   {
9886     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9887   },
9888
9889   /* VEX_LEN_0FC5_P_2 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9892   },
9893
9894   /* VEX_LEN_0FD6_P_2 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9897     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9898   },
9899
9900   /* VEX_LEN_0FF7_P_2 */
9901   {
9902     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9903   },
9904
9905   /* VEX_LEN_0F3816_P_2 */
9906   {
9907     { Bad_Opcode },
9908     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9909   },
9910
9911   /* VEX_LEN_0F3819_P_2 */
9912   {
9913     { Bad_Opcode },
9914     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9915   },
9916
9917   /* VEX_LEN_0F381A_P_2_M_0 */
9918   {
9919     { Bad_Opcode },
9920     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9921   },
9922
9923   /* VEX_LEN_0F3836_P_2 */
9924   {
9925     { Bad_Opcode },
9926     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9927   },
9928
9929   /* VEX_LEN_0F3841_P_2 */
9930   {
9931     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9932   },
9933
9934   /* VEX_LEN_0F385A_P_2_M_0 */
9935   {
9936     { Bad_Opcode },
9937     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9938   },
9939
9940   /* VEX_LEN_0F38DB_P_2 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9943   },
9944
9945   /* VEX_LEN_0F38F2_P_0 */
9946   {
9947     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9948   },
9949
9950   /* VEX_LEN_0F38F3_R_1_P_0 */
9951   {
9952     { "blsrS",          { VexGdq, Edq }, 0 },
9953   },
9954
9955   /* VEX_LEN_0F38F3_R_2_P_0 */
9956   {
9957     { "blsmskS",        { VexGdq, Edq }, 0 },
9958   },
9959
9960   /* VEX_LEN_0F38F3_R_3_P_0 */
9961   {
9962     { "blsiS",          { VexGdq, Edq }, 0 },
9963   },
9964
9965   /* VEX_LEN_0F38F5_P_0 */
9966   {
9967     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9968   },
9969
9970   /* VEX_LEN_0F38F5_P_1 */
9971   {
9972     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9973   },
9974
9975   /* VEX_LEN_0F38F5_P_3 */
9976   {
9977     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9978   },
9979
9980   /* VEX_LEN_0F38F6_P_3 */
9981   {
9982     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9983   },
9984
9985   /* VEX_LEN_0F38F7_P_0 */
9986   {
9987     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9988   },
9989
9990   /* VEX_LEN_0F38F7_P_1 */
9991   {
9992     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9993   },
9994
9995   /* VEX_LEN_0F38F7_P_2 */
9996   {
9997     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9998   },
9999
10000   /* VEX_LEN_0F38F7_P_3 */
10001   {
10002     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10003   },
10004
10005   /* VEX_LEN_0F3A00_P_2 */
10006   {
10007     { Bad_Opcode },
10008     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10009   },
10010
10011   /* VEX_LEN_0F3A01_P_2 */
10012   {
10013     { Bad_Opcode },
10014     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10015   },
10016
10017   /* VEX_LEN_0F3A06_P_2 */
10018   {
10019     { Bad_Opcode },
10020     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10021   },
10022
10023   /* VEX_LEN_0F3A0A_P_2 */
10024   {
10025     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10026     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10027   },
10028
10029   /* VEX_LEN_0F3A0B_P_2 */
10030   {
10031     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10032     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10033   },
10034
10035   /* VEX_LEN_0F3A14_P_2 */
10036   {
10037     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10038   },
10039
10040   /* VEX_LEN_0F3A15_P_2 */
10041   {
10042     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10043   },
10044
10045   /* VEX_LEN_0F3A16_P_2  */
10046   {
10047     { "vpextrK",        { Edq, XM, Ib }, 0 },
10048   },
10049
10050   /* VEX_LEN_0F3A17_P_2 */
10051   {
10052     { "vextractps",     { Edqd, XM, Ib }, 0 },
10053   },
10054
10055   /* VEX_LEN_0F3A18_P_2 */
10056   {
10057     { Bad_Opcode },
10058     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10059   },
10060
10061   /* VEX_LEN_0F3A19_P_2 */
10062   {
10063     { Bad_Opcode },
10064     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10065   },
10066
10067   /* VEX_LEN_0F3A20_P_2 */
10068   {
10069     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10070   },
10071
10072   /* VEX_LEN_0F3A21_P_2 */
10073   {
10074     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10075   },
10076
10077   /* VEX_LEN_0F3A22_P_2 */
10078   {
10079     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10080   },
10081
10082   /* VEX_LEN_0F3A30_P_2 */
10083   {
10084     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10085   },
10086
10087   /* VEX_LEN_0F3A31_P_2 */
10088   {
10089     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10090   },
10091
10092   /* VEX_LEN_0F3A32_P_2 */
10093   {
10094     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10095   },
10096
10097   /* VEX_LEN_0F3A33_P_2 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10100   },
10101
10102   /* VEX_LEN_0F3A38_P_2 */
10103   {
10104     { Bad_Opcode },
10105     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10106   },
10107
10108   /* VEX_LEN_0F3A39_P_2 */
10109   {
10110     { Bad_Opcode },
10111     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10112   },
10113
10114   /* VEX_LEN_0F3A41_P_2 */
10115   {
10116     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10117   },
10118
10119   /* VEX_LEN_0F3A46_P_2 */
10120   {
10121     { Bad_Opcode },
10122     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10123   },
10124
10125   /* VEX_LEN_0F3A60_P_2 */
10126   {
10127     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10128   },
10129
10130   /* VEX_LEN_0F3A61_P_2 */
10131   {
10132     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10133   },
10134
10135   /* VEX_LEN_0F3A62_P_2 */
10136   {
10137     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10138   },
10139
10140   /* VEX_LEN_0F3A63_P_2 */
10141   {
10142     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10143   },
10144
10145   /* VEX_LEN_0F3A6A_P_2 */
10146   {
10147     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10148   },
10149
10150   /* VEX_LEN_0F3A6B_P_2 */
10151   {
10152     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10153   },
10154
10155   /* VEX_LEN_0F3A6E_P_2 */
10156   {
10157     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10158   },
10159
10160   /* VEX_LEN_0F3A6F_P_2 */
10161   {
10162     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10163   },
10164
10165   /* VEX_LEN_0F3A7A_P_2 */
10166   {
10167     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10168   },
10169
10170   /* VEX_LEN_0F3A7B_P_2 */
10171   {
10172     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10173   },
10174
10175   /* VEX_LEN_0F3A7E_P_2 */
10176   {
10177     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10178   },
10179
10180   /* VEX_LEN_0F3A7F_P_2 */
10181   {
10182     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10183   },
10184
10185   /* VEX_LEN_0F3ADF_P_2 */
10186   {
10187     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10188   },
10189
10190   /* VEX_LEN_0F3AF0_P_3 */
10191   {
10192     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10193   },
10194
10195   /* VEX_LEN_0FXOP_08_CC */
10196   {
10197      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10198   },
10199
10200   /* VEX_LEN_0FXOP_08_CD */
10201   {
10202      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10203   },
10204
10205   /* VEX_LEN_0FXOP_08_CE */
10206   {
10207      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10208   },
10209
10210   /* VEX_LEN_0FXOP_08_CF */
10211   {
10212      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10213   },
10214
10215   /* VEX_LEN_0FXOP_08_EC */
10216   {
10217      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10218   },
10219
10220   /* VEX_LEN_0FXOP_08_ED */
10221   {
10222      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10223   },
10224
10225   /* VEX_LEN_0FXOP_08_EE */
10226   {
10227      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10228   },
10229
10230   /* VEX_LEN_0FXOP_08_EF */
10231   {
10232      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10233   },
10234
10235   /* VEX_LEN_0FXOP_09_80 */
10236   {
10237     { "vfrczps",        { XM, EXxmm }, 0 },
10238     { "vfrczps",        { XM, EXymmq }, 0 },
10239   },
10240
10241   /* VEX_LEN_0FXOP_09_81 */
10242   {
10243     { "vfrczpd",        { XM, EXxmm }, 0 },
10244     { "vfrczpd",        { XM, EXymmq }, 0 },
10245   },
10246 };
10247
10248 static const struct dis386 vex_w_table[][2] = {
10249   {
10250     /* VEX_W_0F10_P_0 */
10251     { "vmovups",        { XM, EXx }, 0 },
10252   },
10253   {
10254     /* VEX_W_0F10_P_1 */
10255     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10256   },
10257   {
10258     /* VEX_W_0F10_P_2 */
10259     { "vmovupd",        { XM, EXx }, 0 },
10260   },
10261   {
10262     /* VEX_W_0F10_P_3 */
10263     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10264   },
10265   {
10266     /* VEX_W_0F11_P_0 */
10267     { "vmovups",        { EXxS, XM }, 0 },
10268   },
10269   {
10270     /* VEX_W_0F11_P_1 */
10271     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10272   },
10273   {
10274     /* VEX_W_0F11_P_2 */
10275     { "vmovupd",        { EXxS, XM }, 0 },
10276   },
10277   {
10278     /* VEX_W_0F11_P_3 */
10279     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10280   },
10281   {
10282     /* VEX_W_0F12_P_0_M_0 */
10283     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10284   },
10285   {
10286     /* VEX_W_0F12_P_0_M_1 */
10287     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10288   },
10289   {
10290     /* VEX_W_0F12_P_1 */
10291     { "vmovsldup",      { XM, EXx }, 0 },
10292   },
10293   {
10294     /* VEX_W_0F12_P_2 */
10295     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10296   },
10297   {
10298     /* VEX_W_0F12_P_3 */
10299     { "vmovddup",       { XM, EXymmq }, 0 },
10300   },
10301   {
10302     /* VEX_W_0F13_M_0 */
10303     { "vmovlpX",        { EXq, XM }, 0 },
10304   },
10305   {
10306     /* VEX_W_0F14 */
10307     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10308   },
10309   {
10310     /* VEX_W_0F15 */
10311     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10312   },
10313   {
10314     /* VEX_W_0F16_P_0_M_0 */
10315     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10316   },
10317   {
10318     /* VEX_W_0F16_P_0_M_1 */
10319     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10320   },
10321   {
10322     /* VEX_W_0F16_P_1 */
10323     { "vmovshdup",      { XM, EXx }, 0 },
10324   },
10325   {
10326     /* VEX_W_0F16_P_2 */
10327     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10328   },
10329   {
10330     /* VEX_W_0F17_M_0 */
10331     { "vmovhpX",        { EXq, XM }, 0 },
10332   },
10333   {
10334     /* VEX_W_0F28 */
10335     { "vmovapX",        { XM, EXx }, 0 },
10336   },
10337   {
10338     /* VEX_W_0F29 */
10339     { "vmovapX",        { EXxS, XM }, 0 },
10340   },
10341   {
10342     /* VEX_W_0F2B_M_0 */
10343     { "vmovntpX",       { Mx, XM }, 0 },
10344   },
10345   {
10346     /* VEX_W_0F2E_P_0 */
10347     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10348   },
10349   {
10350     /* VEX_W_0F2E_P_2 */
10351     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10352   },
10353   {
10354     /* VEX_W_0F2F_P_0 */
10355     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10356   },
10357   {
10358     /* VEX_W_0F2F_P_2 */
10359     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10360   },
10361   {
10362     /* VEX_W_0F41_P_0_LEN_1 */
10363     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10364     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10365   },
10366   {
10367     /* VEX_W_0F41_P_2_LEN_1 */
10368     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10369     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10370   },
10371   {
10372     /* VEX_W_0F42_P_0_LEN_1 */
10373     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10374     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10375   },
10376   {
10377     /* VEX_W_0F42_P_2_LEN_1 */
10378     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10379     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10380   },
10381   {
10382     /* VEX_W_0F44_P_0_LEN_0 */
10383     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10384     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10385   },
10386   {
10387     /* VEX_W_0F44_P_2_LEN_0 */
10388     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10389     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10390   },
10391   {
10392     /* VEX_W_0F45_P_0_LEN_1 */
10393     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10394     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10395   },
10396   {
10397     /* VEX_W_0F45_P_2_LEN_1 */
10398     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10399     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10400   },
10401   {
10402     /* VEX_W_0F46_P_0_LEN_1 */
10403     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10404     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10405   },
10406   {
10407     /* VEX_W_0F46_P_2_LEN_1 */
10408     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10409     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10410   },
10411   {
10412     /* VEX_W_0F47_P_0_LEN_1 */
10413     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10414     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10415   },
10416   {
10417     /* VEX_W_0F47_P_2_LEN_1 */
10418     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10419     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10420   },
10421   {
10422     /* VEX_W_0F4A_P_0_LEN_1 */
10423     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10424     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10425   },
10426   {
10427     /* VEX_W_0F4A_P_2_LEN_1 */
10428     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10429     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10430   },
10431   {
10432     /* VEX_W_0F4B_P_0_LEN_1 */
10433     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10434     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10435   },
10436   {
10437     /* VEX_W_0F4B_P_2_LEN_1 */
10438     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10439   },
10440   {
10441     /* VEX_W_0F50_M_0 */
10442     { "vmovmskpX",      { Gdq, XS }, 0 },
10443   },
10444   {
10445     /* VEX_W_0F51_P_0 */
10446     { "vsqrtps",        { XM, EXx }, 0 },
10447   },
10448   {
10449     /* VEX_W_0F51_P_1 */
10450     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F51_P_2  */
10454     { "vsqrtpd",        { XM, EXx }, 0 },
10455   },
10456   {
10457     /* VEX_W_0F51_P_3 */
10458     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F52_P_0 */
10462     { "vrsqrtps",       { XM, EXx }, 0 },
10463   },
10464   {
10465     /* VEX_W_0F52_P_1 */
10466     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F53_P_0  */
10470     { "vrcpps",         { XM, EXx }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F53_P_1  */
10474     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10475   },
10476   {
10477     /* VEX_W_0F58_P_0  */
10478     { "vaddps",         { XM, Vex, EXx }, 0 },
10479   },
10480   {
10481     /* VEX_W_0F58_P_1  */
10482     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10483   },
10484   {
10485     /* VEX_W_0F58_P_2  */
10486     { "vaddpd",         { XM, Vex, EXx }, 0 },
10487   },
10488   {
10489     /* VEX_W_0F58_P_3  */
10490     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10491   },
10492   {
10493     /* VEX_W_0F59_P_0  */
10494     { "vmulps",         { XM, Vex, EXx }, 0 },
10495   },
10496   {
10497     /* VEX_W_0F59_P_1  */
10498     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F59_P_2  */
10502     { "vmulpd",         { XM, Vex, EXx }, 0 },
10503   },
10504   {
10505     /* VEX_W_0F59_P_3  */
10506     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10507   },
10508   {
10509     /* VEX_W_0F5A_P_0  */
10510     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10511   },
10512   {
10513     /* VEX_W_0F5A_P_1  */
10514     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10515   },
10516   {
10517     /* VEX_W_0F5A_P_3  */
10518     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10519   },
10520   {
10521     /* VEX_W_0F5B_P_0  */
10522     { "vcvtdq2ps",      { XM, EXx }, 0 },
10523   },
10524   {
10525     /* VEX_W_0F5B_P_1  */
10526     { "vcvttps2dq",     { XM, EXx }, 0 },
10527   },
10528   {
10529     /* VEX_W_0F5B_P_2  */
10530     { "vcvtps2dq",      { XM, EXx }, 0 },
10531   },
10532   {
10533     /* VEX_W_0F5C_P_0  */
10534     { "vsubps",         { XM, Vex, EXx }, 0 },
10535   },
10536   {
10537     /* VEX_W_0F5C_P_1  */
10538     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10539   },
10540   {
10541     /* VEX_W_0F5C_P_2  */
10542     { "vsubpd",         { XM, Vex, EXx }, 0 },
10543   },
10544   {
10545     /* VEX_W_0F5C_P_3  */
10546     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10547   },
10548   {
10549     /* VEX_W_0F5D_P_0  */
10550     { "vminps",         { XM, Vex, EXx }, 0 },
10551   },
10552   {
10553     /* VEX_W_0F5D_P_1  */
10554     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10555   },
10556   {
10557     /* VEX_W_0F5D_P_2  */
10558     { "vminpd",         { XM, Vex, EXx }, 0 },
10559   },
10560   {
10561     /* VEX_W_0F5D_P_3  */
10562     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10563   },
10564   {
10565     /* VEX_W_0F5E_P_0  */
10566     { "vdivps",         { XM, Vex, EXx }, 0 },
10567   },
10568   {
10569     /* VEX_W_0F5E_P_1  */
10570     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10571   },
10572   {
10573     /* VEX_W_0F5E_P_2  */
10574     { "vdivpd",         { XM, Vex, EXx }, 0 },
10575   },
10576   {
10577     /* VEX_W_0F5E_P_3  */
10578     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10579   },
10580   {
10581     /* VEX_W_0F5F_P_0  */
10582     { "vmaxps",         { XM, Vex, EXx }, 0 },
10583   },
10584   {
10585     /* VEX_W_0F5F_P_1  */
10586     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10587   },
10588   {
10589     /* VEX_W_0F5F_P_2  */
10590     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10591   },
10592   {
10593     /* VEX_W_0F5F_P_3  */
10594     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10595   },
10596   {
10597     /* VEX_W_0F60_P_2  */
10598     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10599   },
10600   {
10601     /* VEX_W_0F61_P_2  */
10602     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10603   },
10604   {
10605     /* VEX_W_0F62_P_2  */
10606     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10607   },
10608   {
10609     /* VEX_W_0F63_P_2  */
10610     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10611   },
10612   {
10613     /* VEX_W_0F64_P_2  */
10614     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10615   },
10616   {
10617     /* VEX_W_0F65_P_2  */
10618     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10619   },
10620   {
10621     /* VEX_W_0F66_P_2  */
10622     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10623   },
10624   {
10625     /* VEX_W_0F67_P_2  */
10626     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10627   },
10628   {
10629     /* VEX_W_0F68_P_2  */
10630     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10631   },
10632   {
10633     /* VEX_W_0F69_P_2  */
10634     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10635   },
10636   {
10637     /* VEX_W_0F6A_P_2  */
10638     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10639   },
10640   {
10641     /* VEX_W_0F6B_P_2  */
10642     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10643   },
10644   {
10645     /* VEX_W_0F6C_P_2  */
10646     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10647   },
10648   {
10649     /* VEX_W_0F6D_P_2  */
10650     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10651   },
10652   {
10653     /* VEX_W_0F6F_P_1  */
10654     { "vmovdqu",        { XM, EXx }, 0 },
10655   },
10656   {
10657     /* VEX_W_0F6F_P_2  */
10658     { "vmovdqa",        { XM, EXx }, 0 },
10659   },
10660   {
10661     /* VEX_W_0F70_P_1 */
10662     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10663   },
10664   {
10665     /* VEX_W_0F70_P_2 */
10666     { "vpshufd",        { XM, EXx, Ib }, 0 },
10667   },
10668   {
10669     /* VEX_W_0F70_P_3 */
10670     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10671   },
10672   {
10673     /* VEX_W_0F71_R_2_P_2  */
10674     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10675   },
10676   {
10677     /* VEX_W_0F71_R_4_P_2  */
10678     { "vpsraw",         { Vex, XS, Ib }, 0 },
10679   },
10680   {
10681     /* VEX_W_0F71_R_6_P_2  */
10682     { "vpsllw",         { Vex, XS, Ib }, 0 },
10683   },
10684   {
10685     /* VEX_W_0F72_R_2_P_2  */
10686     { "vpsrld",         { Vex, XS, Ib }, 0 },
10687   },
10688   {
10689     /* VEX_W_0F72_R_4_P_2  */
10690     { "vpsrad",         { Vex, XS, Ib }, 0 },
10691   },
10692   {
10693     /* VEX_W_0F72_R_6_P_2  */
10694     { "vpslld",         { Vex, XS, Ib }, 0 },
10695   },
10696   {
10697     /* VEX_W_0F73_R_2_P_2  */
10698     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10699   },
10700   {
10701     /* VEX_W_0F73_R_3_P_2  */
10702     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10703   },
10704   {
10705     /* VEX_W_0F73_R_6_P_2  */
10706     { "vpsllq",         { Vex, XS, Ib }, 0 },
10707   },
10708   {
10709     /* VEX_W_0F73_R_7_P_2  */
10710     { "vpslldq",        { Vex, XS, Ib }, 0 },
10711   },
10712   {
10713     /* VEX_W_0F74_P_2 */
10714     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10715   },
10716   {
10717     /* VEX_W_0F75_P_2 */
10718     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10719   },
10720   {
10721     /* VEX_W_0F76_P_2 */
10722     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10723   },
10724   {
10725     /* VEX_W_0F77_P_0 */
10726     { "",               { VZERO }, 0 },
10727   },
10728   {
10729     /* VEX_W_0F7C_P_2 */
10730     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10731   },
10732   {
10733     /* VEX_W_0F7C_P_3 */
10734     { "vhaddps",        { XM, Vex, EXx }, 0 },
10735   },
10736   {
10737     /* VEX_W_0F7D_P_2 */
10738     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10739   },
10740   {
10741     /* VEX_W_0F7D_P_3 */
10742     { "vhsubps",        { XM, Vex, EXx }, 0 },
10743   },
10744   {
10745     /* VEX_W_0F7E_P_1 */
10746     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10747   },
10748   {
10749     /* VEX_W_0F7F_P_1 */
10750     { "vmovdqu",        { EXxS, XM }, 0 },
10751   },
10752   {
10753     /* VEX_W_0F7F_P_2 */
10754     { "vmovdqa",        { EXxS, XM }, 0 },
10755   },
10756   {
10757     /* VEX_W_0F90_P_0_LEN_0 */
10758     { "kmovw",          { MaskG, MaskE }, 0 },
10759     { "kmovq",          { MaskG, MaskE }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F90_P_2_LEN_0 */
10763     { "kmovb",          { MaskG, MaskBDE }, 0 },
10764     { "kmovd",          { MaskG, MaskBDE }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F91_P_0_LEN_0 */
10768     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10769     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10770   },
10771   {
10772     /* VEX_W_0F91_P_2_LEN_0 */
10773     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10774     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10775   },
10776   {
10777     /* VEX_W_0F92_P_0_LEN_0 */
10778     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10779   },
10780   {
10781     /* VEX_W_0F92_P_2_LEN_0 */
10782     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10783   },
10784   {
10785     /* VEX_W_0F92_P_3_LEN_0 */
10786     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10787     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10788   },
10789   {
10790     /* VEX_W_0F93_P_0_LEN_0 */
10791     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10792   },
10793   {
10794     /* VEX_W_0F93_P_2_LEN_0 */
10795     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10796   },
10797   {
10798     /* VEX_W_0F93_P_3_LEN_0 */
10799     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10800     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10801   },
10802   {
10803     /* VEX_W_0F98_P_0_LEN_0 */
10804     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10805     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10806   },
10807   {
10808     /* VEX_W_0F98_P_2_LEN_0 */
10809     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10810     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10811   },
10812   {
10813     /* VEX_W_0F99_P_0_LEN_0 */
10814     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10815     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10816   },
10817   {
10818     /* VEX_W_0F99_P_2_LEN_0 */
10819     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10820     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10821   },
10822   {
10823     /* VEX_W_0FAE_R_2_M_0 */
10824     { "vldmxcsr",       { Md }, 0 },
10825   },
10826   {
10827     /* VEX_W_0FAE_R_3_M_0 */
10828     { "vstmxcsr",       { Md }, 0 },
10829   },
10830   {
10831     /* VEX_W_0FC2_P_0 */
10832     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10833   },
10834   {
10835     /* VEX_W_0FC2_P_1 */
10836     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10837   },
10838   {
10839     /* VEX_W_0FC2_P_2 */
10840     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10841   },
10842   {
10843     /* VEX_W_0FC2_P_3 */
10844     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10845   },
10846   {
10847     /* VEX_W_0FC4_P_2 */
10848     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10849   },
10850   {
10851     /* VEX_W_0FC5_P_2 */
10852     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10853   },
10854   {
10855     /* VEX_W_0FD0_P_2 */
10856     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10857   },
10858   {
10859     /* VEX_W_0FD0_P_3 */
10860     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10861   },
10862   {
10863     /* VEX_W_0FD1_P_2 */
10864     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10865   },
10866   {
10867     /* VEX_W_0FD2_P_2 */
10868     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10869   },
10870   {
10871     /* VEX_W_0FD3_P_2 */
10872     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10873   },
10874   {
10875     /* VEX_W_0FD4_P_2 */
10876     { "vpaddq",         { XM, Vex, EXx }, 0 },
10877   },
10878   {
10879     /* VEX_W_0FD5_P_2 */
10880     { "vpmullw",        { XM, Vex, EXx }, 0 },
10881   },
10882   {
10883     /* VEX_W_0FD6_P_2 */
10884     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10885   },
10886   {
10887     /* VEX_W_0FD7_P_2_M_1 */
10888     { "vpmovmskb",      { Gdq, XS }, 0 },
10889   },
10890   {
10891     /* VEX_W_0FD8_P_2 */
10892     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10893   },
10894   {
10895     /* VEX_W_0FD9_P_2 */
10896     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10897   },
10898   {
10899     /* VEX_W_0FDA_P_2 */
10900     { "vpminub",        { XM, Vex, EXx }, 0 },
10901   },
10902   {
10903     /* VEX_W_0FDB_P_2 */
10904     { "vpand",          { XM, Vex, EXx }, 0 },
10905   },
10906   {
10907     /* VEX_W_0FDC_P_2 */
10908     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10909   },
10910   {
10911     /* VEX_W_0FDD_P_2 */
10912     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10913   },
10914   {
10915     /* VEX_W_0FDE_P_2 */
10916     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10917   },
10918   {
10919     /* VEX_W_0FDF_P_2 */
10920     { "vpandn",         { XM, Vex, EXx }, 0 },
10921   },
10922   {
10923     /* VEX_W_0FE0_P_2  */
10924     { "vpavgb",         { XM, Vex, EXx }, 0 },
10925   },
10926   {
10927     /* VEX_W_0FE1_P_2  */
10928     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10929   },
10930   {
10931     /* VEX_W_0FE2_P_2  */
10932     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10933   },
10934   {
10935     /* VEX_W_0FE3_P_2  */
10936     { "vpavgw",         { XM, Vex, EXx }, 0 },
10937   },
10938   {
10939     /* VEX_W_0FE4_P_2  */
10940     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10941   },
10942   {
10943     /* VEX_W_0FE5_P_2  */
10944     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10945   },
10946   {
10947     /* VEX_W_0FE6_P_1  */
10948     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10949   },
10950   {
10951     /* VEX_W_0FE6_P_2  */
10952     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10953   },
10954   {
10955     /* VEX_W_0FE6_P_3  */
10956     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10957   },
10958   {
10959     /* VEX_W_0FE7_P_2_M_0 */
10960     { "vmovntdq",       { Mx, XM }, 0 },
10961   },
10962   {
10963     /* VEX_W_0FE8_P_2  */
10964     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10965   },
10966   {
10967     /* VEX_W_0FE9_P_2  */
10968     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10969   },
10970   {
10971     /* VEX_W_0FEA_P_2  */
10972     { "vpminsw",        { XM, Vex, EXx }, 0 },
10973   },
10974   {
10975     /* VEX_W_0FEB_P_2  */
10976     { "vpor",           { XM, Vex, EXx }, 0 },
10977   },
10978   {
10979     /* VEX_W_0FEC_P_2  */
10980     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10981   },
10982   {
10983     /* VEX_W_0FED_P_2  */
10984     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10985   },
10986   {
10987     /* VEX_W_0FEE_P_2  */
10988     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10989   },
10990   {
10991     /* VEX_W_0FEF_P_2  */
10992     { "vpxor",          { XM, Vex, EXx }, 0 },
10993   },
10994   {
10995     /* VEX_W_0FF0_P_3_M_0 */
10996     { "vlddqu",         { XM, M }, 0 },
10997   },
10998   {
10999     /* VEX_W_0FF1_P_2 */
11000     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11001   },
11002   {
11003     /* VEX_W_0FF2_P_2 */
11004     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11005   },
11006   {
11007     /* VEX_W_0FF3_P_2 */
11008     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11009   },
11010   {
11011     /* VEX_W_0FF4_P_2 */
11012     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11013   },
11014   {
11015     /* VEX_W_0FF5_P_2 */
11016     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11017   },
11018   {
11019     /* VEX_W_0FF6_P_2 */
11020     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11021   },
11022   {
11023     /* VEX_W_0FF7_P_2 */
11024     { "vmaskmovdqu",    { XM, XS }, 0 },
11025   },
11026   {
11027     /* VEX_W_0FF8_P_2 */
11028     { "vpsubb",         { XM, Vex, EXx }, 0 },
11029   },
11030   {
11031     /* VEX_W_0FF9_P_2 */
11032     { "vpsubw",         { XM, Vex, EXx }, 0 },
11033   },
11034   {
11035     /* VEX_W_0FFA_P_2 */
11036     { "vpsubd",         { XM, Vex, EXx }, 0 },
11037   },
11038   {
11039     /* VEX_W_0FFB_P_2 */
11040     { "vpsubq",         { XM, Vex, EXx }, 0 },
11041   },
11042   {
11043     /* VEX_W_0FFC_P_2 */
11044     { "vpaddb",         { XM, Vex, EXx }, 0 },
11045   },
11046   {
11047     /* VEX_W_0FFD_P_2 */
11048     { "vpaddw",         { XM, Vex, EXx }, 0 },
11049   },
11050   {
11051     /* VEX_W_0FFE_P_2 */
11052     { "vpaddd",         { XM, Vex, EXx }, 0 },
11053   },
11054   {
11055     /* VEX_W_0F3800_P_2  */
11056     { "vpshufb",        { XM, Vex, EXx }, 0 },
11057   },
11058   {
11059     /* VEX_W_0F3801_P_2  */
11060     { "vphaddw",        { XM, Vex, EXx }, 0 },
11061   },
11062   {
11063     /* VEX_W_0F3802_P_2  */
11064     { "vphaddd",        { XM, Vex, EXx }, 0 },
11065   },
11066   {
11067     /* VEX_W_0F3803_P_2  */
11068     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11069   },
11070   {
11071     /* VEX_W_0F3804_P_2  */
11072     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11073   },
11074   {
11075     /* VEX_W_0F3805_P_2  */
11076     { "vphsubw",        { XM, Vex, EXx }, 0 },
11077   },
11078   {
11079     /* VEX_W_0F3806_P_2  */
11080     { "vphsubd",        { XM, Vex, EXx }, 0 },
11081   },
11082   {
11083     /* VEX_W_0F3807_P_2  */
11084     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11085   },
11086   {
11087     /* VEX_W_0F3808_P_2  */
11088     { "vpsignb",        { XM, Vex, EXx }, 0 },
11089   },
11090   {
11091     /* VEX_W_0F3809_P_2  */
11092     { "vpsignw",        { XM, Vex, EXx }, 0 },
11093   },
11094   {
11095     /* VEX_W_0F380A_P_2  */
11096     { "vpsignd",        { XM, Vex, EXx }, 0 },
11097   },
11098   {
11099     /* VEX_W_0F380B_P_2  */
11100     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11101   },
11102   {
11103     /* VEX_W_0F380C_P_2  */
11104     { "vpermilps",      { XM, Vex, EXx }, 0 },
11105   },
11106   {
11107     /* VEX_W_0F380D_P_2  */
11108     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11109   },
11110   {
11111     /* VEX_W_0F380E_P_2  */
11112     { "vtestps",        { XM, EXx }, 0 },
11113   },
11114   {
11115     /* VEX_W_0F380F_P_2  */
11116     { "vtestpd",        { XM, EXx }, 0 },
11117   },
11118   {
11119     /* VEX_W_0F3816_P_2  */
11120     { "vpermps",        { XM, Vex, EXx }, 0 },
11121   },
11122   {
11123     /* VEX_W_0F3817_P_2 */
11124     { "vptest",         { XM, EXx }, 0 },
11125   },
11126   {
11127     /* VEX_W_0F3818_P_2 */
11128     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11129   },
11130   {
11131     /* VEX_W_0F3819_P_2 */
11132     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11133   },
11134   {
11135     /* VEX_W_0F381A_P_2_M_0 */
11136     { "vbroadcastf128", { XM, Mxmm }, 0 },
11137   },
11138   {
11139     /* VEX_W_0F381C_P_2 */
11140     { "vpabsb",         { XM, EXx }, 0 },
11141   },
11142   {
11143     /* VEX_W_0F381D_P_2 */
11144     { "vpabsw",         { XM, EXx }, 0 },
11145   },
11146   {
11147     /* VEX_W_0F381E_P_2 */
11148     { "vpabsd",         { XM, EXx }, 0 },
11149   },
11150   {
11151     /* VEX_W_0F3820_P_2 */
11152     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11153   },
11154   {
11155     /* VEX_W_0F3821_P_2 */
11156     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11157   },
11158   {
11159     /* VEX_W_0F3822_P_2 */
11160     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11161   },
11162   {
11163     /* VEX_W_0F3823_P_2 */
11164     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11165   },
11166   {
11167     /* VEX_W_0F3824_P_2 */
11168     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11169   },
11170   {
11171     /* VEX_W_0F3825_P_2 */
11172     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11173   },
11174   {
11175     /* VEX_W_0F3828_P_2 */
11176     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11177   },
11178   {
11179     /* VEX_W_0F3829_P_2 */
11180     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11181   },
11182   {
11183     /* VEX_W_0F382A_P_2_M_0 */
11184     { "vmovntdqa",      { XM, Mx }, 0 },
11185   },
11186   {
11187     /* VEX_W_0F382B_P_2 */
11188     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11189   },
11190   {
11191     /* VEX_W_0F382C_P_2_M_0 */
11192     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11193   },
11194   {
11195     /* VEX_W_0F382D_P_2_M_0 */
11196     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11197   },
11198   {
11199     /* VEX_W_0F382E_P_2_M_0 */
11200     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11201   },
11202   {
11203     /* VEX_W_0F382F_P_2_M_0 */
11204     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11205   },
11206   {
11207     /* VEX_W_0F3830_P_2 */
11208     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11209   },
11210   {
11211     /* VEX_W_0F3831_P_2 */
11212     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11213   },
11214   {
11215     /* VEX_W_0F3832_P_2 */
11216     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11217   },
11218   {
11219     /* VEX_W_0F3833_P_2 */
11220     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11221   },
11222   {
11223     /* VEX_W_0F3834_P_2 */
11224     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11225   },
11226   {
11227     /* VEX_W_0F3835_P_2 */
11228     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11229   },
11230   {
11231     /* VEX_W_0F3836_P_2  */
11232     { "vpermd",         { XM, Vex, EXx }, 0 },
11233   },
11234   {
11235     /* VEX_W_0F3837_P_2 */
11236     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11237   },
11238   {
11239     /* VEX_W_0F3838_P_2 */
11240     { "vpminsb",        { XM, Vex, EXx }, 0 },
11241   },
11242   {
11243     /* VEX_W_0F3839_P_2 */
11244     { "vpminsd",        { XM, Vex, EXx }, 0 },
11245   },
11246   {
11247     /* VEX_W_0F383A_P_2 */
11248     { "vpminuw",        { XM, Vex, EXx }, 0 },
11249   },
11250   {
11251     /* VEX_W_0F383B_P_2 */
11252     { "vpminud",        { XM, Vex, EXx }, 0 },
11253   },
11254   {
11255     /* VEX_W_0F383C_P_2 */
11256     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11257   },
11258   {
11259     /* VEX_W_0F383D_P_2 */
11260     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11261   },
11262   {
11263     /* VEX_W_0F383E_P_2 */
11264     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11265   },
11266   {
11267     /* VEX_W_0F383F_P_2 */
11268     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11269   },
11270   {
11271     /* VEX_W_0F3840_P_2 */
11272     { "vpmulld",        { XM, Vex, EXx }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F3841_P_2 */
11276     { "vphminposuw",    { XM, EXx }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F3846_P_2 */
11280     { "vpsravd",        { XM, Vex, EXx }, 0 },
11281   },
11282   {
11283     /* VEX_W_0F3858_P_2 */
11284     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11285   },
11286   {
11287     /* VEX_W_0F3859_P_2 */
11288     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11289   },
11290   {
11291     /* VEX_W_0F385A_P_2_M_0 */
11292     { "vbroadcasti128", { XM, Mxmm }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3878_P_2 */
11296     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11297   },
11298   {
11299     /* VEX_W_0F3879_P_2 */
11300     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F38CF_P_2 */
11304     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F38DB_P_2 */
11308     { "vaesimc",        { XM, EXx }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F3A00_P_2 */
11312     { Bad_Opcode },
11313     { "vpermq",         { XM, EXx, Ib }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F3A01_P_2 */
11317     { Bad_Opcode },
11318     { "vpermpd",        { XM, EXx, Ib }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3A02_P_2 */
11322     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3A04_P_2 */
11326     { "vpermilps",      { XM, EXx, Ib }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F3A05_P_2 */
11330     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F3A06_P_2 */
11334     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F3A08_P_2 */
11338     { "vroundps",       { XM, EXx, Ib }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F3A09_P_2 */
11342     { "vroundpd",       { XM, EXx, Ib }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F3A0A_P_2 */
11346     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F3A0B_P_2 */
11350     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F3A0C_P_2 */
11354     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F3A0D_P_2 */
11358     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F3A0E_P_2 */
11362     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F3A0F_P_2 */
11366     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11367   },
11368   {
11369     /* VEX_W_0F3A14_P_2 */
11370     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F3A15_P_2 */
11374     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11375   },
11376   {
11377     /* VEX_W_0F3A18_P_2 */
11378     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11379   },
11380   {
11381     /* VEX_W_0F3A19_P_2 */
11382     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11383   },
11384   {
11385     /* VEX_W_0F3A20_P_2 */
11386     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F3A21_P_2 */
11390     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11391   },
11392   {
11393     /* VEX_W_0F3A30_P_2_LEN_0 */
11394     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11395     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11396   },
11397   {
11398     /* VEX_W_0F3A31_P_2_LEN_0 */
11399     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11400     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11401   },
11402   {
11403     /* VEX_W_0F3A32_P_2_LEN_0 */
11404     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11405     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11406   },
11407   {
11408     /* VEX_W_0F3A33_P_2_LEN_0 */
11409     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11410     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11411   },
11412   {
11413     /* VEX_W_0F3A38_P_2 */
11414     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11415   },
11416   {
11417     /* VEX_W_0F3A39_P_2 */
11418     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11419   },
11420   {
11421     /* VEX_W_0F3A40_P_2 */
11422     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F3A41_P_2 */
11426     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11427   },
11428   {
11429     /* VEX_W_0F3A42_P_2 */
11430     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11431   },
11432   {
11433     /* VEX_W_0F3A46_P_2 */
11434     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11435   },
11436   {
11437     /* VEX_W_0F3A48_P_2 */
11438     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11439     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A49_P_2 */
11443     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11444     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11445   },
11446   {
11447     /* VEX_W_0F3A4A_P_2 */
11448     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11449   },
11450   {
11451     /* VEX_W_0F3A4B_P_2 */
11452     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11453   },
11454   {
11455     /* VEX_W_0F3A4C_P_2 */
11456     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11457   },
11458   {
11459     /* VEX_W_0F3A62_P_2 */
11460     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11461   },
11462   {
11463     /* VEX_W_0F3A63_P_2 */
11464     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11465   },
11466   {
11467     /* VEX_W_0F3ACE_P_2 */
11468     { Bad_Opcode },
11469     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11470   },
11471   {
11472     /* VEX_W_0F3ACF_P_2 */
11473     { Bad_Opcode },
11474     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11475   },
11476   {
11477     /* VEX_W_0F3ADF_P_2 */
11478     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11479   },
11480 #define NEED_VEX_W_TABLE
11481 #include "i386-dis-evex.h"
11482 #undef NEED_VEX_W_TABLE
11483 };
11484
11485 static const struct dis386 mod_table[][2] = {
11486   {
11487     /* MOD_8D */
11488     { "leaS",           { Gv, M }, 0 },
11489   },
11490   {
11491     /* MOD_C6_REG_7 */
11492     { Bad_Opcode },
11493     { RM_TABLE (RM_C6_REG_7) },
11494   },
11495   {
11496     /* MOD_C7_REG_7 */
11497     { Bad_Opcode },
11498     { RM_TABLE (RM_C7_REG_7) },
11499   },
11500   {
11501     /* MOD_FF_REG_3 */
11502     { "Jcall^", { indirEp }, 0 },
11503   },
11504   {
11505     /* MOD_FF_REG_5 */
11506     { "Jjmp^", { indirEp }, 0 },
11507   },
11508   {
11509     /* MOD_0F01_REG_0 */
11510     { X86_64_TABLE (X86_64_0F01_REG_0) },
11511     { RM_TABLE (RM_0F01_REG_0) },
11512   },
11513   {
11514     /* MOD_0F01_REG_1 */
11515     { X86_64_TABLE (X86_64_0F01_REG_1) },
11516     { RM_TABLE (RM_0F01_REG_1) },
11517   },
11518   {
11519     /* MOD_0F01_REG_2 */
11520     { X86_64_TABLE (X86_64_0F01_REG_2) },
11521     { RM_TABLE (RM_0F01_REG_2) },
11522   },
11523   {
11524     /* MOD_0F01_REG_3 */
11525     { X86_64_TABLE (X86_64_0F01_REG_3) },
11526     { RM_TABLE (RM_0F01_REG_3) },
11527   },
11528   {
11529     /* MOD_0F01_REG_5 */
11530     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11531     { RM_TABLE (RM_0F01_REG_5) },
11532   },
11533   {
11534     /* MOD_0F01_REG_7 */
11535     { "invlpg",         { Mb }, 0 },
11536     { RM_TABLE (RM_0F01_REG_7) },
11537   },
11538   {
11539     /* MOD_0F12_PREFIX_0 */
11540     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11541     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11542   },
11543   {
11544     /* MOD_0F13 */
11545     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11546   },
11547   {
11548     /* MOD_0F16_PREFIX_0 */
11549     { "movhps",         { XM, EXq }, 0 },
11550     { "movlhps",        { XM, EXq }, 0 },
11551   },
11552   {
11553     /* MOD_0F17 */
11554     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11555   },
11556   {
11557     /* MOD_0F18_REG_0 */
11558     { "prefetchnta",    { Mb }, 0 },
11559   },
11560   {
11561     /* MOD_0F18_REG_1 */
11562     { "prefetcht0",     { Mb }, 0 },
11563   },
11564   {
11565     /* MOD_0F18_REG_2 */
11566     { "prefetcht1",     { Mb }, 0 },
11567   },
11568   {
11569     /* MOD_0F18_REG_3 */
11570     { "prefetcht2",     { Mb }, 0 },
11571   },
11572   {
11573     /* MOD_0F18_REG_4 */
11574     { "nop/reserved",   { Mb }, 0 },
11575   },
11576   {
11577     /* MOD_0F18_REG_5 */
11578     { "nop/reserved",   { Mb }, 0 },
11579   },
11580   {
11581     /* MOD_0F18_REG_6 */
11582     { "nop/reserved",   { Mb }, 0 },
11583   },
11584   {
11585     /* MOD_0F18_REG_7 */
11586     { "nop/reserved",   { Mb }, 0 },
11587   },
11588   {
11589     /* MOD_0F1A_PREFIX_0 */
11590     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11591     { "nopQ",           { Ev }, 0 },
11592   },
11593   {
11594     /* MOD_0F1B_PREFIX_0 */
11595     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11596     { "nopQ",           { Ev }, 0 },
11597   },
11598   {
11599     /* MOD_0F1B_PREFIX_1 */
11600     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11601     { "nopQ",           { Ev }, 0 },
11602   },
11603   {
11604     /* MOD_0F1E_PREFIX_1 */
11605     { "nopQ",           { Ev }, 0 },
11606     { REG_TABLE (REG_0F1E_MOD_3) },
11607   },
11608   {
11609     /* MOD_0F24 */
11610     { Bad_Opcode },
11611     { "movL",           { Rd, Td }, 0 },
11612   },
11613   {
11614     /* MOD_0F26 */
11615     { Bad_Opcode },
11616     { "movL",           { Td, Rd }, 0 },
11617   },
11618   {
11619     /* MOD_0F2B_PREFIX_0 */
11620     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11621   },
11622   {
11623     /* MOD_0F2B_PREFIX_1 */
11624     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11625   },
11626   {
11627     /* MOD_0F2B_PREFIX_2 */
11628     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11629   },
11630   {
11631     /* MOD_0F2B_PREFIX_3 */
11632     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11633   },
11634   {
11635     /* MOD_0F51 */
11636     { Bad_Opcode },
11637     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11638   },
11639   {
11640     /* MOD_0F71_REG_2 */
11641     { Bad_Opcode },
11642     { "psrlw",          { MS, Ib }, 0 },
11643   },
11644   {
11645     /* MOD_0F71_REG_4 */
11646     { Bad_Opcode },
11647     { "psraw",          { MS, Ib }, 0 },
11648   },
11649   {
11650     /* MOD_0F71_REG_6 */
11651     { Bad_Opcode },
11652     { "psllw",          { MS, Ib }, 0 },
11653   },
11654   {
11655     /* MOD_0F72_REG_2 */
11656     { Bad_Opcode },
11657     { "psrld",          { MS, Ib }, 0 },
11658   },
11659   {
11660     /* MOD_0F72_REG_4 */
11661     { Bad_Opcode },
11662     { "psrad",          { MS, Ib }, 0 },
11663   },
11664   {
11665     /* MOD_0F72_REG_6 */
11666     { Bad_Opcode },
11667     { "pslld",          { MS, Ib }, 0 },
11668   },
11669   {
11670     /* MOD_0F73_REG_2 */
11671     { Bad_Opcode },
11672     { "psrlq",          { MS, Ib }, 0 },
11673   },
11674   {
11675     /* MOD_0F73_REG_3 */
11676     { Bad_Opcode },
11677     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11678   },
11679   {
11680     /* MOD_0F73_REG_6 */
11681     { Bad_Opcode },
11682     { "psllq",          { MS, Ib }, 0 },
11683   },
11684   {
11685     /* MOD_0F73_REG_7 */
11686     { Bad_Opcode },
11687     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11688   },
11689   {
11690     /* MOD_0FAE_REG_0 */
11691     { "fxsave",         { FXSAVE }, 0 },
11692     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11693   },
11694   {
11695     /* MOD_0FAE_REG_1 */
11696     { "fxrstor",        { FXSAVE }, 0 },
11697     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11698   },
11699   {
11700     /* MOD_0FAE_REG_2 */
11701     { "ldmxcsr",        { Md }, 0 },
11702     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11703   },
11704   {
11705     /* MOD_0FAE_REG_3 */
11706     { "stmxcsr",        { Md }, 0 },
11707     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11708   },
11709   {
11710     /* MOD_0FAE_REG_4 */
11711     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11712     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11713   },
11714   {
11715     /* MOD_0FAE_REG_5 */
11716     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11717     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11718   },
11719   {
11720     /* MOD_0FAE_REG_6 */
11721     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11722     { RM_TABLE (RM_0FAE_REG_6) },
11723   },
11724   {
11725     /* MOD_0FAE_REG_7 */
11726     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11727     { RM_TABLE (RM_0FAE_REG_7) },
11728   },
11729   {
11730     /* MOD_0FB2 */
11731     { "lssS",           { Gv, Mp }, 0 },
11732   },
11733   {
11734     /* MOD_0FB4 */
11735     { "lfsS",           { Gv, Mp }, 0 },
11736   },
11737   {
11738     /* MOD_0FB5 */
11739     { "lgsS",           { Gv, Mp }, 0 },
11740   },
11741   {
11742     /* MOD_0FC3 */
11743     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11744   },
11745   {
11746     /* MOD_0FC7_REG_3 */
11747     { "xrstors",        { FXSAVE }, 0 },
11748   },
11749   {
11750     /* MOD_0FC7_REG_4 */
11751     { "xsavec",         { FXSAVE }, 0 },
11752   },
11753   {
11754     /* MOD_0FC7_REG_5 */
11755     { "xsaves",         { FXSAVE }, 0 },
11756   },
11757   {
11758     /* MOD_0FC7_REG_6 */
11759     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11760     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11761   },
11762   {
11763     /* MOD_0FC7_REG_7 */
11764     { "vmptrst",        { Mq }, 0 },
11765     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11766   },
11767   {
11768     /* MOD_0FD7 */
11769     { Bad_Opcode },
11770     { "pmovmskb",       { Gdq, MS }, 0 },
11771   },
11772   {
11773     /* MOD_0FE7_PREFIX_2 */
11774     { "movntdq",        { Mx, XM }, 0 },
11775   },
11776   {
11777     /* MOD_0FF0_PREFIX_3 */
11778     { "lddqu",          { XM, M }, 0 },
11779   },
11780   {
11781     /* MOD_0F382A_PREFIX_2 */
11782     { "movntdqa",       { XM, Mx }, 0 },
11783   },
11784   {
11785     /* MOD_0F38F5_PREFIX_2 */
11786     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11787   },
11788   {
11789     /* MOD_0F38F6_PREFIX_0 */
11790     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11791   },
11792   {
11793     /* MOD_62_32BIT */
11794     { "bound{S|}",      { Gv, Ma }, 0 },
11795     { EVEX_TABLE (EVEX_0F) },
11796   },
11797   {
11798     /* MOD_C4_32BIT */
11799     { "lesS",           { Gv, Mp }, 0 },
11800     { VEX_C4_TABLE (VEX_0F) },
11801   },
11802   {
11803     /* MOD_C5_32BIT */
11804     { "ldsS",           { Gv, Mp }, 0 },
11805     { VEX_C5_TABLE (VEX_0F) },
11806   },
11807   {
11808     /* MOD_VEX_0F12_PREFIX_0 */
11809     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11810     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11811   },
11812   {
11813     /* MOD_VEX_0F13 */
11814     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11815   },
11816   {
11817     /* MOD_VEX_0F16_PREFIX_0 */
11818     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11819     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11820   },
11821   {
11822     /* MOD_VEX_0F17 */
11823     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11824   },
11825   {
11826     /* MOD_VEX_0F2B */
11827     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11828   },
11829   {
11830     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11831     { Bad_Opcode },
11832     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11833   },
11834   {
11835     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11836     { Bad_Opcode },
11837     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11838   },
11839   {
11840     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11841     { Bad_Opcode },
11842     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11843   },
11844   {
11845     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11846     { Bad_Opcode },
11847     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11848   },
11849   {
11850     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11851     { Bad_Opcode },
11852     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11853   },
11854   {
11855     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11856     { Bad_Opcode },
11857     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11858   },
11859   {
11860     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11861     { Bad_Opcode },
11862     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11863   },
11864   {
11865     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11866     { Bad_Opcode },
11867     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11868   },
11869   {
11870     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11871     { Bad_Opcode },
11872     { "knotw",          { MaskG, MaskR }, 0 },
11873   },
11874   {
11875     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11876     { Bad_Opcode },
11877     { "knotq",          { MaskG, MaskR }, 0 },
11878   },
11879   {
11880     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11881     { Bad_Opcode },
11882     { "knotb",          { MaskG, MaskR }, 0 },
11883   },
11884   {
11885     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11886     { Bad_Opcode },
11887     { "knotd",          { MaskG, MaskR }, 0 },
11888   },
11889   {
11890     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11891     { Bad_Opcode },
11892     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11893   },
11894   {
11895     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11896     { Bad_Opcode },
11897     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11898   },
11899   {
11900     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11901     { Bad_Opcode },
11902     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11903   },
11904   {
11905     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11906     { Bad_Opcode },
11907     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11908   },
11909  {
11910     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11911     { Bad_Opcode },
11912     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11913   },
11914   {
11915     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11916     { Bad_Opcode },
11917     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11918   },
11919   {
11920     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11921     { Bad_Opcode },
11922     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11923   },
11924   {
11925     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11926     { Bad_Opcode },
11927     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11928   },
11929   {
11930     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11931     { Bad_Opcode },
11932     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11933   },
11934   {
11935     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11936     { Bad_Opcode },
11937     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11938   },
11939   {
11940     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11941     { Bad_Opcode },
11942     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11943   },
11944   {
11945     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11946     { Bad_Opcode },
11947     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11948   },
11949   {
11950     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11951     { Bad_Opcode },
11952     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11953   },
11954   {
11955     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11956     { Bad_Opcode },
11957     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11958   },
11959   {
11960     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11961     { Bad_Opcode },
11962     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11963   },
11964   {
11965     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11966     { Bad_Opcode },
11967     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11968   },
11969   {
11970     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11971     { Bad_Opcode },
11972     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11973   },
11974   {
11975     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11976     { Bad_Opcode },
11977     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11978   },
11979   {
11980     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11981     { Bad_Opcode },
11982     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11983   },
11984   {
11985     /* MOD_VEX_0F50 */
11986     { Bad_Opcode },
11987     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11988   },
11989   {
11990     /* MOD_VEX_0F71_REG_2 */
11991     { Bad_Opcode },
11992     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11993   },
11994   {
11995     /* MOD_VEX_0F71_REG_4 */
11996     { Bad_Opcode },
11997     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11998   },
11999   {
12000     /* MOD_VEX_0F71_REG_6 */
12001     { Bad_Opcode },
12002     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12003   },
12004   {
12005     /* MOD_VEX_0F72_REG_2 */
12006     { Bad_Opcode },
12007     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12008   },
12009   {
12010     /* MOD_VEX_0F72_REG_4 */
12011     { Bad_Opcode },
12012     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12013   },
12014   {
12015     /* MOD_VEX_0F72_REG_6 */
12016     { Bad_Opcode },
12017     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12018   },
12019   {
12020     /* MOD_VEX_0F73_REG_2 */
12021     { Bad_Opcode },
12022     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12023   },
12024   {
12025     /* MOD_VEX_0F73_REG_3 */
12026     { Bad_Opcode },
12027     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12028   },
12029   {
12030     /* MOD_VEX_0F73_REG_6 */
12031     { Bad_Opcode },
12032     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12033   },
12034   {
12035     /* MOD_VEX_0F73_REG_7 */
12036     { Bad_Opcode },
12037     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12038   },
12039   {
12040     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12041     { "kmovw",          { Ew, MaskG }, 0 },
12042     { Bad_Opcode },
12043   },
12044   {
12045     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12046     { "kmovq",          { Eq, MaskG }, 0 },
12047     { Bad_Opcode },
12048   },
12049   {
12050     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12051     { "kmovb",          { Eb, MaskG }, 0 },
12052     { Bad_Opcode },
12053   },
12054   {
12055     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12056     { "kmovd",          { Ed, MaskG }, 0 },
12057     { Bad_Opcode },
12058   },
12059   {
12060     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12061     { Bad_Opcode },
12062     { "kmovw",          { MaskG, Rdq }, 0 },
12063   },
12064   {
12065     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12066     { Bad_Opcode },
12067     { "kmovb",          { MaskG, Rdq }, 0 },
12068   },
12069   {
12070     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12071     { Bad_Opcode },
12072     { "kmovd",          { MaskG, Rdq }, 0 },
12073   },
12074   {
12075     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12076     { Bad_Opcode },
12077     { "kmovq",          { MaskG, Rdq }, 0 },
12078   },
12079   {
12080     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12081     { Bad_Opcode },
12082     { "kmovw",          { Gdq, MaskR }, 0 },
12083   },
12084   {
12085     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12086     { Bad_Opcode },
12087     { "kmovb",          { Gdq, MaskR }, 0 },
12088   },
12089   {
12090     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12091     { Bad_Opcode },
12092     { "kmovd",          { Gdq, MaskR }, 0 },
12093   },
12094   {
12095     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12096     { Bad_Opcode },
12097     { "kmovq",          { Gdq, MaskR }, 0 },
12098   },
12099   {
12100     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12101     { Bad_Opcode },
12102     { "kortestw", { MaskG, MaskR }, 0 },
12103   },
12104   {
12105     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12106     { Bad_Opcode },
12107     { "kortestq", { MaskG, MaskR }, 0 },
12108   },
12109   {
12110     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12111     { Bad_Opcode },
12112     { "kortestb", { MaskG, MaskR }, 0 },
12113   },
12114   {
12115     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12116     { Bad_Opcode },
12117     { "kortestd", { MaskG, MaskR }, 0 },
12118   },
12119   {
12120     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12121     { Bad_Opcode },
12122     { "ktestw", { MaskG, MaskR }, 0 },
12123   },
12124   {
12125     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12126     { Bad_Opcode },
12127     { "ktestq", { MaskG, MaskR }, 0 },
12128   },
12129   {
12130     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12131     { Bad_Opcode },
12132     { "ktestb", { MaskG, MaskR }, 0 },
12133   },
12134   {
12135     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12136     { Bad_Opcode },
12137     { "ktestd", { MaskG, MaskR }, 0 },
12138   },
12139   {
12140     /* MOD_VEX_0FAE_REG_2 */
12141     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12142   },
12143   {
12144     /* MOD_VEX_0FAE_REG_3 */
12145     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12146   },
12147   {
12148     /* MOD_VEX_0FD7_PREFIX_2 */
12149     { Bad_Opcode },
12150     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12151   },
12152   {
12153     /* MOD_VEX_0FE7_PREFIX_2 */
12154     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12155   },
12156   {
12157     /* MOD_VEX_0FF0_PREFIX_3 */
12158     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12159   },
12160   {
12161     /* MOD_VEX_0F381A_PREFIX_2 */
12162     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12163   },
12164   {
12165     /* MOD_VEX_0F382A_PREFIX_2 */
12166     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12167   },
12168   {
12169     /* MOD_VEX_0F382C_PREFIX_2 */
12170     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12171   },
12172   {
12173     /* MOD_VEX_0F382D_PREFIX_2 */
12174     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12175   },
12176   {
12177     /* MOD_VEX_0F382E_PREFIX_2 */
12178     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12179   },
12180   {
12181     /* MOD_VEX_0F382F_PREFIX_2 */
12182     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12183   },
12184   {
12185     /* MOD_VEX_0F385A_PREFIX_2 */
12186     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12187   },
12188   {
12189     /* MOD_VEX_0F388C_PREFIX_2 */
12190     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12191   },
12192   {
12193     /* MOD_VEX_0F388E_PREFIX_2 */
12194     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12195   },
12196   {
12197     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12198     { Bad_Opcode },
12199     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12200   },
12201   {
12202     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12203     { Bad_Opcode },
12204     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12205   },
12206   {
12207     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12208     { Bad_Opcode },
12209     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12210   },
12211   {
12212     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12213     { Bad_Opcode },
12214     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12215   },
12216   {
12217     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12218     { Bad_Opcode },
12219     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12220   },
12221   {
12222     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12223     { Bad_Opcode },
12224     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12225   },
12226   {
12227     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12228     { Bad_Opcode },
12229     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12230   },
12231   {
12232     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12233     { Bad_Opcode },
12234     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12235   },
12236 #define NEED_MOD_TABLE
12237 #include "i386-dis-evex.h"
12238 #undef NEED_MOD_TABLE
12239 };
12240
12241 static const struct dis386 rm_table[][8] = {
12242   {
12243     /* RM_C6_REG_7 */
12244     { "xabort",         { Skip_MODRM, Ib }, 0 },
12245   },
12246   {
12247     /* RM_C7_REG_7 */
12248     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12249   },
12250   {
12251     /* RM_0F01_REG_0 */
12252     { Bad_Opcode },
12253     { "vmcall",         { Skip_MODRM }, 0 },
12254     { "vmlaunch",       { Skip_MODRM }, 0 },
12255     { "vmresume",       { Skip_MODRM }, 0 },
12256     { "vmxoff",         { Skip_MODRM }, 0 },
12257   },
12258   {
12259     /* RM_0F01_REG_1 */
12260     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12261     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12262     { "clac",           { Skip_MODRM }, 0 },
12263     { "stac",           { Skip_MODRM }, 0 },
12264     { Bad_Opcode },
12265     { Bad_Opcode },
12266     { Bad_Opcode },
12267     { "encls",          { Skip_MODRM }, 0 },
12268   },
12269   {
12270     /* RM_0F01_REG_2 */
12271     { "xgetbv",         { Skip_MODRM }, 0 },
12272     { "xsetbv",         { Skip_MODRM }, 0 },
12273     { Bad_Opcode },
12274     { Bad_Opcode },
12275     { "vmfunc",         { Skip_MODRM }, 0 },
12276     { "xend",           { Skip_MODRM }, 0 },
12277     { "xtest",          { Skip_MODRM }, 0 },
12278     { "enclu",          { Skip_MODRM }, 0 },
12279   },
12280   {
12281     /* RM_0F01_REG_3 */
12282     { "vmrun",          { Skip_MODRM }, 0 },
12283     { "vmmcall",        { Skip_MODRM }, 0 },
12284     { "vmload",         { Skip_MODRM }, 0 },
12285     { "vmsave",         { Skip_MODRM }, 0 },
12286     { "stgi",           { Skip_MODRM }, 0 },
12287     { "clgi",           { Skip_MODRM }, 0 },
12288     { "skinit",         { Skip_MODRM }, 0 },
12289     { "invlpga",        { Skip_MODRM }, 0 },
12290   },
12291   {
12292     /* RM_0F01_REG_5 */
12293     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12294     { Bad_Opcode },
12295     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12296     { Bad_Opcode },
12297     { Bad_Opcode },
12298     { Bad_Opcode },
12299     { "rdpkru",         { Skip_MODRM }, 0 },
12300     { "wrpkru",         { Skip_MODRM }, 0 },
12301   },
12302   {
12303     /* RM_0F01_REG_7 */
12304     { "swapgs",         { Skip_MODRM }, 0  },
12305     { "rdtscp",         { Skip_MODRM }, 0  },
12306     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12307     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12308     { "clzero",         { Skip_MODRM }, 0  },
12309   },
12310   {
12311     /* RM_0F1E_MOD_3_REG_7 */
12312     { "nopQ",           { Ev }, 0 },
12313     { "nopQ",           { Ev }, 0 },
12314     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12315     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12316     { "nopQ",           { Ev }, 0 },
12317     { "nopQ",           { Ev }, 0 },
12318     { "nopQ",           { Ev }, 0 },
12319     { "nopQ",           { Ev }, 0 },
12320   },
12321   {
12322     /* RM_0FAE_REG_6 */
12323     { "mfence",         { Skip_MODRM }, 0 },
12324   },
12325   {
12326     /* RM_0FAE_REG_7 */
12327     { "sfence",         { Skip_MODRM }, 0 },
12328
12329   },
12330 };
12331
12332 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12333
12334 /* We use the high bit to indicate different name for the same
12335    prefix.  */
12336 #define REP_PREFIX      (0xf3 | 0x100)
12337 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12338 #define XRELEASE_PREFIX (0xf3 | 0x400)
12339 #define BND_PREFIX      (0xf2 | 0x400)
12340 #define NOTRACK_PREFIX  (0x3e | 0x100)
12341
12342 static int
12343 ckprefix (void)
12344 {
12345   int newrex, i, length;
12346   rex = 0;
12347   rex_ignored = 0;
12348   prefixes = 0;
12349   used_prefixes = 0;
12350   rex_used = 0;
12351   last_lock_prefix = -1;
12352   last_repz_prefix = -1;
12353   last_repnz_prefix = -1;
12354   last_data_prefix = -1;
12355   last_addr_prefix = -1;
12356   last_rex_prefix = -1;
12357   last_seg_prefix = -1;
12358   fwait_prefix = -1;
12359   active_seg_prefix = 0;
12360   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12361     all_prefixes[i] = 0;
12362   i = 0;
12363   length = 0;
12364   /* The maximum instruction length is 15bytes.  */
12365   while (length < MAX_CODE_LENGTH - 1)
12366     {
12367       FETCH_DATA (the_info, codep + 1);
12368       newrex = 0;
12369       switch (*codep)
12370         {
12371         /* REX prefixes family.  */
12372         case 0x40:
12373         case 0x41:
12374         case 0x42:
12375         case 0x43:
12376         case 0x44:
12377         case 0x45:
12378         case 0x46:
12379         case 0x47:
12380         case 0x48:
12381         case 0x49:
12382         case 0x4a:
12383         case 0x4b:
12384         case 0x4c:
12385         case 0x4d:
12386         case 0x4e:
12387         case 0x4f:
12388           if (address_mode == mode_64bit)
12389             newrex = *codep;
12390           else
12391             return 1;
12392           last_rex_prefix = i;
12393           break;
12394         case 0xf3:
12395           prefixes |= PREFIX_REPZ;
12396           last_repz_prefix = i;
12397           break;
12398         case 0xf2:
12399           prefixes |= PREFIX_REPNZ;
12400           last_repnz_prefix = i;
12401           break;
12402         case 0xf0:
12403           prefixes |= PREFIX_LOCK;
12404           last_lock_prefix = i;
12405           break;
12406         case 0x2e:
12407           prefixes |= PREFIX_CS;
12408           last_seg_prefix = i;
12409           active_seg_prefix = PREFIX_CS;
12410           break;
12411         case 0x36:
12412           prefixes |= PREFIX_SS;
12413           last_seg_prefix = i;
12414           active_seg_prefix = PREFIX_SS;
12415           break;
12416         case 0x3e:
12417           prefixes |= PREFIX_DS;
12418           last_seg_prefix = i;
12419           active_seg_prefix = PREFIX_DS;
12420           break;
12421         case 0x26:
12422           prefixes |= PREFIX_ES;
12423           last_seg_prefix = i;
12424           active_seg_prefix = PREFIX_ES;
12425           break;
12426         case 0x64:
12427           prefixes |= PREFIX_FS;
12428           last_seg_prefix = i;
12429           active_seg_prefix = PREFIX_FS;
12430           break;
12431         case 0x65:
12432           prefixes |= PREFIX_GS;
12433           last_seg_prefix = i;
12434           active_seg_prefix = PREFIX_GS;
12435           break;
12436         case 0x66:
12437           prefixes |= PREFIX_DATA;
12438           last_data_prefix = i;
12439           break;
12440         case 0x67:
12441           prefixes |= PREFIX_ADDR;
12442           last_addr_prefix = i;
12443           break;
12444         case FWAIT_OPCODE:
12445           /* fwait is really an instruction.  If there are prefixes
12446              before the fwait, they belong to the fwait, *not* to the
12447              following instruction.  */
12448           fwait_prefix = i;
12449           if (prefixes || rex)
12450             {
12451               prefixes |= PREFIX_FWAIT;
12452               codep++;
12453               /* This ensures that the previous REX prefixes are noticed
12454                  as unused prefixes, as in the return case below.  */
12455               rex_used = rex;
12456               return 1;
12457             }
12458           prefixes = PREFIX_FWAIT;
12459           break;
12460         default:
12461           return 1;
12462         }
12463       /* Rex is ignored when followed by another prefix.  */
12464       if (rex)
12465         {
12466           rex_used = rex;
12467           return 1;
12468         }
12469       if (*codep != FWAIT_OPCODE)
12470         all_prefixes[i++] = *codep;
12471       rex = newrex;
12472       codep++;
12473       length++;
12474     }
12475   return 0;
12476 }
12477
12478 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12479    prefix byte.  */
12480
12481 static const char *
12482 prefix_name (int pref, int sizeflag)
12483 {
12484   static const char *rexes [16] =
12485     {
12486       "rex",            /* 0x40 */
12487       "rex.B",          /* 0x41 */
12488       "rex.X",          /* 0x42 */
12489       "rex.XB",         /* 0x43 */
12490       "rex.R",          /* 0x44 */
12491       "rex.RB",         /* 0x45 */
12492       "rex.RX",         /* 0x46 */
12493       "rex.RXB",        /* 0x47 */
12494       "rex.W",          /* 0x48 */
12495       "rex.WB",         /* 0x49 */
12496       "rex.WX",         /* 0x4a */
12497       "rex.WXB",        /* 0x4b */
12498       "rex.WR",         /* 0x4c */
12499       "rex.WRB",        /* 0x4d */
12500       "rex.WRX",        /* 0x4e */
12501       "rex.WRXB",       /* 0x4f */
12502     };
12503
12504   switch (pref)
12505     {
12506     /* REX prefixes family.  */
12507     case 0x40:
12508     case 0x41:
12509     case 0x42:
12510     case 0x43:
12511     case 0x44:
12512     case 0x45:
12513     case 0x46:
12514     case 0x47:
12515     case 0x48:
12516     case 0x49:
12517     case 0x4a:
12518     case 0x4b:
12519     case 0x4c:
12520     case 0x4d:
12521     case 0x4e:
12522     case 0x4f:
12523       return rexes [pref - 0x40];
12524     case 0xf3:
12525       return "repz";
12526     case 0xf2:
12527       return "repnz";
12528     case 0xf0:
12529       return "lock";
12530     case 0x2e:
12531       return "cs";
12532     case 0x36:
12533       return "ss";
12534     case 0x3e:
12535       return "ds";
12536     case 0x26:
12537       return "es";
12538     case 0x64:
12539       return "fs";
12540     case 0x65:
12541       return "gs";
12542     case 0x66:
12543       return (sizeflag & DFLAG) ? "data16" : "data32";
12544     case 0x67:
12545       if (address_mode == mode_64bit)
12546         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12547       else
12548         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12549     case FWAIT_OPCODE:
12550       return "fwait";
12551     case REP_PREFIX:
12552       return "rep";
12553     case XACQUIRE_PREFIX:
12554       return "xacquire";
12555     case XRELEASE_PREFIX:
12556       return "xrelease";
12557     case BND_PREFIX:
12558       return "bnd";
12559     case NOTRACK_PREFIX:
12560       return "notrack";
12561     default:
12562       return NULL;
12563     }
12564 }
12565
12566 static char op_out[MAX_OPERANDS][100];
12567 static int op_ad, op_index[MAX_OPERANDS];
12568 static int two_source_ops;
12569 static bfd_vma op_address[MAX_OPERANDS];
12570 static bfd_vma op_riprel[MAX_OPERANDS];
12571 static bfd_vma start_pc;
12572
12573 /*
12574  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12575  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12576  *   section of the "Virtual 8086 Mode" chapter.)
12577  * 'pc' should be the address of this instruction, it will
12578  *   be used to print the target address if this is a relative jump or call
12579  * The function returns the length of this instruction in bytes.
12580  */
12581
12582 static char intel_syntax;
12583 static char intel_mnemonic = !SYSV386_COMPAT;
12584 static char open_char;
12585 static char close_char;
12586 static char separator_char;
12587 static char scale_char;
12588
12589 enum x86_64_isa
12590 {
12591   amd64 = 0,
12592   intel64
12593 };
12594
12595 static enum x86_64_isa isa64;
12596
12597 /* Here for backwards compatibility.  When gdb stops using
12598    print_insn_i386_att and print_insn_i386_intel these functions can
12599    disappear, and print_insn_i386 be merged into print_insn.  */
12600 int
12601 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12602 {
12603   intel_syntax = 0;
12604
12605   return print_insn (pc, info);
12606 }
12607
12608 int
12609 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12610 {
12611   intel_syntax = 1;
12612
12613   return print_insn (pc, info);
12614 }
12615
12616 int
12617 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12618 {
12619   intel_syntax = -1;
12620
12621   return print_insn (pc, info);
12622 }
12623
12624 void
12625 print_i386_disassembler_options (FILE *stream)
12626 {
12627   fprintf (stream, _("\n\
12628 The following i386/x86-64 specific disassembler options are supported for use\n\
12629 with the -M switch (multiple options should be separated by commas):\n"));
12630
12631   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12632   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12633   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12634   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12635   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12636   fprintf (stream, _("  att-mnemonic\n"
12637                      "              Display instruction in AT&T mnemonic\n"));
12638   fprintf (stream, _("  intel-mnemonic\n"
12639                      "              Display instruction in Intel mnemonic\n"));
12640   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12641   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12642   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12643   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12644   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12645   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12646   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12647   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12648 }
12649
12650 /* Bad opcode.  */
12651 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12652
12653 /* Get a pointer to struct dis386 with a valid name.  */
12654
12655 static const struct dis386 *
12656 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12657 {
12658   int vindex, vex_table_index;
12659
12660   if (dp->name != NULL)
12661     return dp;
12662
12663   switch (dp->op[0].bytemode)
12664     {
12665     case USE_REG_TABLE:
12666       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12667       break;
12668
12669     case USE_MOD_TABLE:
12670       vindex = modrm.mod == 0x3 ? 1 : 0;
12671       dp = &mod_table[dp->op[1].bytemode][vindex];
12672       break;
12673
12674     case USE_RM_TABLE:
12675       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12676       break;
12677
12678     case USE_PREFIX_TABLE:
12679       if (need_vex)
12680         {
12681           /* The prefix in VEX is implicit.  */
12682           switch (vex.prefix)
12683             {
12684             case 0:
12685               vindex = 0;
12686               break;
12687             case REPE_PREFIX_OPCODE:
12688               vindex = 1;
12689               break;
12690             case DATA_PREFIX_OPCODE:
12691               vindex = 2;
12692               break;
12693             case REPNE_PREFIX_OPCODE:
12694               vindex = 3;
12695               break;
12696             default:
12697               abort ();
12698               break;
12699             }
12700         }
12701       else
12702         {
12703           int last_prefix = -1;
12704           int prefix = 0;
12705           vindex = 0;
12706           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12707              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12708              last one wins.  */
12709           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12710             {
12711               if (last_repz_prefix > last_repnz_prefix)
12712                 {
12713                   vindex = 1;
12714                   prefix = PREFIX_REPZ;
12715                   last_prefix = last_repz_prefix;
12716                 }
12717               else
12718                 {
12719                   vindex = 3;
12720                   prefix = PREFIX_REPNZ;
12721                   last_prefix = last_repnz_prefix;
12722                 }
12723
12724               /* Check if prefix should be ignored.  */
12725               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12726                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12727                    & prefix) != 0)
12728                 vindex = 0;
12729             }
12730
12731           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12732             {
12733               vindex = 2;
12734               prefix = PREFIX_DATA;
12735               last_prefix = last_data_prefix;
12736             }
12737
12738           if (vindex != 0)
12739             {
12740               used_prefixes |= prefix;
12741               all_prefixes[last_prefix] = 0;
12742             }
12743         }
12744       dp = &prefix_table[dp->op[1].bytemode][vindex];
12745       break;
12746
12747     case USE_X86_64_TABLE:
12748       vindex = address_mode == mode_64bit ? 1 : 0;
12749       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12750       break;
12751
12752     case USE_3BYTE_TABLE:
12753       FETCH_DATA (info, codep + 2);
12754       vindex = *codep++;
12755       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12756       end_codep = codep;
12757       modrm.mod = (*codep >> 6) & 3;
12758       modrm.reg = (*codep >> 3) & 7;
12759       modrm.rm = *codep & 7;
12760       break;
12761
12762     case USE_VEX_LEN_TABLE:
12763       if (!need_vex)
12764         abort ();
12765
12766       switch (vex.length)
12767         {
12768         case 128:
12769           vindex = 0;
12770           break;
12771         case 256:
12772           vindex = 1;
12773           break;
12774         default:
12775           abort ();
12776           break;
12777         }
12778
12779       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12780       break;
12781
12782     case USE_XOP_8F_TABLE:
12783       FETCH_DATA (info, codep + 3);
12784       /* All bits in the REX prefix are ignored.  */
12785       rex_ignored = rex;
12786       rex = ~(*codep >> 5) & 0x7;
12787
12788       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12789       switch ((*codep & 0x1f))
12790         {
12791         default:
12792           dp = &bad_opcode;
12793           return dp;
12794         case 0x8:
12795           vex_table_index = XOP_08;
12796           break;
12797         case 0x9:
12798           vex_table_index = XOP_09;
12799           break;
12800         case 0xa:
12801           vex_table_index = XOP_0A;
12802           break;
12803         }
12804       codep++;
12805       vex.w = *codep & 0x80;
12806       if (vex.w && address_mode == mode_64bit)
12807         rex |= REX_W;
12808
12809       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12810       if (address_mode != mode_64bit)
12811         {
12812           /* In 16/32-bit mode REX_B is silently ignored.  */
12813           rex &= ~REX_B;
12814           if (vex.register_specifier > 0x7)
12815             {
12816               dp = &bad_opcode;
12817               return dp;
12818             }
12819         }
12820
12821       vex.length = (*codep & 0x4) ? 256 : 128;
12822       switch ((*codep & 0x3))
12823         {
12824         case 0:
12825           vex.prefix = 0;
12826           break;
12827         case 1:
12828           vex.prefix = DATA_PREFIX_OPCODE;
12829           break;
12830         case 2:
12831           vex.prefix = REPE_PREFIX_OPCODE;
12832           break;
12833         case 3:
12834           vex.prefix = REPNE_PREFIX_OPCODE;
12835           break;
12836         }
12837       need_vex = 1;
12838       need_vex_reg = 1;
12839       codep++;
12840       vindex = *codep++;
12841       dp = &xop_table[vex_table_index][vindex];
12842
12843       end_codep = codep;
12844       FETCH_DATA (info, codep + 1);
12845       modrm.mod = (*codep >> 6) & 3;
12846       modrm.reg = (*codep >> 3) & 7;
12847       modrm.rm = *codep & 7;
12848       break;
12849
12850     case USE_VEX_C4_TABLE:
12851       /* VEX prefix.  */
12852       FETCH_DATA (info, codep + 3);
12853       /* All bits in the REX prefix are ignored.  */
12854       rex_ignored = rex;
12855       rex = ~(*codep >> 5) & 0x7;
12856       switch ((*codep & 0x1f))
12857         {
12858         default:
12859           dp = &bad_opcode;
12860           return dp;
12861         case 0x1:
12862           vex_table_index = VEX_0F;
12863           break;
12864         case 0x2:
12865           vex_table_index = VEX_0F38;
12866           break;
12867         case 0x3:
12868           vex_table_index = VEX_0F3A;
12869           break;
12870         }
12871       codep++;
12872       vex.w = *codep & 0x80;
12873       if (address_mode == mode_64bit)
12874         {
12875           if (vex.w)
12876             rex |= REX_W;
12877           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12878         }
12879       else
12880         {
12881           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12882              is ignored, other REX bits are 0 and the highest bit in
12883              VEX.vvvv is also ignored.  */
12884           rex = 0;
12885           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12886         }
12887       vex.length = (*codep & 0x4) ? 256 : 128;
12888       switch ((*codep & 0x3))
12889         {
12890         case 0:
12891           vex.prefix = 0;
12892           break;
12893         case 1:
12894           vex.prefix = DATA_PREFIX_OPCODE;
12895           break;
12896         case 2:
12897           vex.prefix = REPE_PREFIX_OPCODE;
12898           break;
12899         case 3:
12900           vex.prefix = REPNE_PREFIX_OPCODE;
12901           break;
12902         }
12903       need_vex = 1;
12904       need_vex_reg = 1;
12905       codep++;
12906       vindex = *codep++;
12907       dp = &vex_table[vex_table_index][vindex];
12908       end_codep = codep;
12909       /* There is no MODRM byte for VEX0F 77.  */
12910       if (vex_table_index != VEX_0F || vindex != 0x77)
12911         {
12912           FETCH_DATA (info, codep + 1);
12913           modrm.mod = (*codep >> 6) & 3;
12914           modrm.reg = (*codep >> 3) & 7;
12915           modrm.rm = *codep & 7;
12916         }
12917       break;
12918
12919     case USE_VEX_C5_TABLE:
12920       /* VEX prefix.  */
12921       FETCH_DATA (info, codep + 2);
12922       /* All bits in the REX prefix are ignored.  */
12923       rex_ignored = rex;
12924       rex = (*codep & 0x80) ? 0 : REX_R;
12925
12926       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12927          VEX.vvvv is 1.  */
12928       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12929       vex.w = 0;
12930       vex.length = (*codep & 0x4) ? 256 : 128;
12931       switch ((*codep & 0x3))
12932         {
12933         case 0:
12934           vex.prefix = 0;
12935           break;
12936         case 1:
12937           vex.prefix = DATA_PREFIX_OPCODE;
12938           break;
12939         case 2:
12940           vex.prefix = REPE_PREFIX_OPCODE;
12941           break;
12942         case 3:
12943           vex.prefix = REPNE_PREFIX_OPCODE;
12944           break;
12945         }
12946       need_vex = 1;
12947       need_vex_reg = 1;
12948       codep++;
12949       vindex = *codep++;
12950       dp = &vex_table[dp->op[1].bytemode][vindex];
12951       end_codep = codep;
12952       /* There is no MODRM byte for VEX 77.  */
12953       if (vindex != 0x77)
12954         {
12955           FETCH_DATA (info, codep + 1);
12956           modrm.mod = (*codep >> 6) & 3;
12957           modrm.reg = (*codep >> 3) & 7;
12958           modrm.rm = *codep & 7;
12959         }
12960       break;
12961
12962     case USE_VEX_W_TABLE:
12963       if (!need_vex)
12964         abort ();
12965
12966       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12967       break;
12968
12969     case USE_EVEX_TABLE:
12970       two_source_ops = 0;
12971       /* EVEX prefix.  */
12972       vex.evex = 1;
12973       FETCH_DATA (info, codep + 4);
12974       /* All bits in the REX prefix are ignored.  */
12975       rex_ignored = rex;
12976       /* The first byte after 0x62.  */
12977       rex = ~(*codep >> 5) & 0x7;
12978       vex.r = *codep & 0x10;
12979       switch ((*codep & 0xf))
12980         {
12981         default:
12982           return &bad_opcode;
12983         case 0x1:
12984           vex_table_index = EVEX_0F;
12985           break;
12986         case 0x2:
12987           vex_table_index = EVEX_0F38;
12988           break;
12989         case 0x3:
12990           vex_table_index = EVEX_0F3A;
12991           break;
12992         }
12993
12994       /* The second byte after 0x62.  */
12995       codep++;
12996       vex.w = *codep & 0x80;
12997       if (vex.w && address_mode == mode_64bit)
12998         rex |= REX_W;
12999
13000       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13001       if (address_mode != mode_64bit)
13002         {
13003           /* In 16/32-bit mode silently ignore following bits.  */
13004           rex &= ~REX_B;
13005           vex.r = 1;
13006           vex.v = 1;
13007           vex.register_specifier &= 0x7;
13008         }
13009
13010       /* The U bit.  */
13011       if (!(*codep & 0x4))
13012         return &bad_opcode;
13013
13014       switch ((*codep & 0x3))
13015         {
13016         case 0:
13017           vex.prefix = 0;
13018           break;
13019         case 1:
13020           vex.prefix = DATA_PREFIX_OPCODE;
13021           break;
13022         case 2:
13023           vex.prefix = REPE_PREFIX_OPCODE;
13024           break;
13025         case 3:
13026           vex.prefix = REPNE_PREFIX_OPCODE;
13027           break;
13028         }
13029
13030       /* The third byte after 0x62.  */
13031       codep++;
13032
13033       /* Remember the static rounding bits.  */
13034       vex.ll = (*codep >> 5) & 3;
13035       vex.b = (*codep & 0x10) != 0;
13036
13037       vex.v = *codep & 0x8;
13038       vex.mask_register_specifier = *codep & 0x7;
13039       vex.zeroing = *codep & 0x80;
13040
13041       need_vex = 1;
13042       need_vex_reg = 1;
13043       codep++;
13044       vindex = *codep++;
13045       dp = &evex_table[vex_table_index][vindex];
13046       end_codep = codep;
13047       FETCH_DATA (info, codep + 1);
13048       modrm.mod = (*codep >> 6) & 3;
13049       modrm.reg = (*codep >> 3) & 7;
13050       modrm.rm = *codep & 7;
13051
13052       /* Set vector length.  */
13053       if (modrm.mod == 3 && vex.b)
13054         vex.length = 512;
13055       else
13056         {
13057           switch (vex.ll)
13058             {
13059             case 0x0:
13060               vex.length = 128;
13061               break;
13062             case 0x1:
13063               vex.length = 256;
13064               break;
13065             case 0x2:
13066               vex.length = 512;
13067               break;
13068             default:
13069               return &bad_opcode;
13070             }
13071         }
13072       break;
13073
13074     case 0:
13075       dp = &bad_opcode;
13076       break;
13077
13078     default:
13079       abort ();
13080     }
13081
13082   if (dp->name != NULL)
13083     return dp;
13084   else
13085     return get_valid_dis386 (dp, info);
13086 }
13087
13088 static void
13089 get_sib (disassemble_info *info, int sizeflag)
13090 {
13091   /* If modrm.mod == 3, operand must be register.  */
13092   if (need_modrm
13093       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13094       && modrm.mod != 3
13095       && modrm.rm == 4)
13096     {
13097       FETCH_DATA (info, codep + 2);
13098       sib.index = (codep [1] >> 3) & 7;
13099       sib.scale = (codep [1] >> 6) & 3;
13100       sib.base = codep [1] & 7;
13101     }
13102 }
13103
13104 static int
13105 print_insn (bfd_vma pc, disassemble_info *info)
13106 {
13107   const struct dis386 *dp;
13108   int i;
13109   char *op_txt[MAX_OPERANDS];
13110   int needcomma;
13111   int sizeflag, orig_sizeflag;
13112   const char *p;
13113   struct dis_private priv;
13114   int prefix_length;
13115
13116   priv.orig_sizeflag = AFLAG | DFLAG;
13117   if ((info->mach & bfd_mach_i386_i386) != 0)
13118     address_mode = mode_32bit;
13119   else if (info->mach == bfd_mach_i386_i8086)
13120     {
13121       address_mode = mode_16bit;
13122       priv.orig_sizeflag = 0;
13123     }
13124   else
13125     address_mode = mode_64bit;
13126
13127   if (intel_syntax == (char) -1)
13128     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13129
13130   for (p = info->disassembler_options; p != NULL; )
13131     {
13132       if (CONST_STRNEQ (p, "amd64"))
13133         isa64 = amd64;
13134       else if (CONST_STRNEQ (p, "intel64"))
13135         isa64 = intel64;
13136       else if (CONST_STRNEQ (p, "x86-64"))
13137         {
13138           address_mode = mode_64bit;
13139           priv.orig_sizeflag = AFLAG | DFLAG;
13140         }
13141       else if (CONST_STRNEQ (p, "i386"))
13142         {
13143           address_mode = mode_32bit;
13144           priv.orig_sizeflag = AFLAG | DFLAG;
13145         }
13146       else if (CONST_STRNEQ (p, "i8086"))
13147         {
13148           address_mode = mode_16bit;
13149           priv.orig_sizeflag = 0;
13150         }
13151       else if (CONST_STRNEQ (p, "intel"))
13152         {
13153           intel_syntax = 1;
13154           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13155             intel_mnemonic = 1;
13156         }
13157       else if (CONST_STRNEQ (p, "att"))
13158         {
13159           intel_syntax = 0;
13160           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13161             intel_mnemonic = 0;
13162         }
13163       else if (CONST_STRNEQ (p, "addr"))
13164         {
13165           if (address_mode == mode_64bit)
13166             {
13167               if (p[4] == '3' && p[5] == '2')
13168                 priv.orig_sizeflag &= ~AFLAG;
13169               else if (p[4] == '6' && p[5] == '4')
13170                 priv.orig_sizeflag |= AFLAG;
13171             }
13172           else
13173             {
13174               if (p[4] == '1' && p[5] == '6')
13175                 priv.orig_sizeflag &= ~AFLAG;
13176               else if (p[4] == '3' && p[5] == '2')
13177                 priv.orig_sizeflag |= AFLAG;
13178             }
13179         }
13180       else if (CONST_STRNEQ (p, "data"))
13181         {
13182           if (p[4] == '1' && p[5] == '6')
13183             priv.orig_sizeflag &= ~DFLAG;
13184           else if (p[4] == '3' && p[5] == '2')
13185             priv.orig_sizeflag |= DFLAG;
13186         }
13187       else if (CONST_STRNEQ (p, "suffix"))
13188         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13189
13190       p = strchr (p, ',');
13191       if (p != NULL)
13192         p++;
13193     }
13194
13195   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13196     {
13197       (*info->fprintf_func) (info->stream,
13198                              _("64-bit address is disabled"));
13199       return -1;
13200     }
13201
13202   if (intel_syntax)
13203     {
13204       names64 = intel_names64;
13205       names32 = intel_names32;
13206       names16 = intel_names16;
13207       names8 = intel_names8;
13208       names8rex = intel_names8rex;
13209       names_seg = intel_names_seg;
13210       names_mm = intel_names_mm;
13211       names_bnd = intel_names_bnd;
13212       names_xmm = intel_names_xmm;
13213       names_ymm = intel_names_ymm;
13214       names_zmm = intel_names_zmm;
13215       index64 = intel_index64;
13216       index32 = intel_index32;
13217       names_mask = intel_names_mask;
13218       index16 = intel_index16;
13219       open_char = '[';
13220       close_char = ']';
13221       separator_char = '+';
13222       scale_char = '*';
13223     }
13224   else
13225     {
13226       names64 = att_names64;
13227       names32 = att_names32;
13228       names16 = att_names16;
13229       names8 = att_names8;
13230       names8rex = att_names8rex;
13231       names_seg = att_names_seg;
13232       names_mm = att_names_mm;
13233       names_bnd = att_names_bnd;
13234       names_xmm = att_names_xmm;
13235       names_ymm = att_names_ymm;
13236       names_zmm = att_names_zmm;
13237       index64 = att_index64;
13238       index32 = att_index32;
13239       names_mask = att_names_mask;
13240       index16 = att_index16;
13241       open_char = '(';
13242       close_char =  ')';
13243       separator_char = ',';
13244       scale_char = ',';
13245     }
13246
13247   /* The output looks better if we put 7 bytes on a line, since that
13248      puts most long word instructions on a single line.  Use 8 bytes
13249      for Intel L1OM.  */
13250   if ((info->mach & bfd_mach_l1om) != 0)
13251     info->bytes_per_line = 8;
13252   else
13253     info->bytes_per_line = 7;
13254
13255   info->private_data = &priv;
13256   priv.max_fetched = priv.the_buffer;
13257   priv.insn_start = pc;
13258
13259   obuf[0] = 0;
13260   for (i = 0; i < MAX_OPERANDS; ++i)
13261     {
13262       op_out[i][0] = 0;
13263       op_index[i] = -1;
13264     }
13265
13266   the_info = info;
13267   start_pc = pc;
13268   start_codep = priv.the_buffer;
13269   codep = priv.the_buffer;
13270
13271   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13272     {
13273       const char *name;
13274
13275       /* Getting here means we tried for data but didn't get it.  That
13276          means we have an incomplete instruction of some sort.  Just
13277          print the first byte as a prefix or a .byte pseudo-op.  */
13278       if (codep > priv.the_buffer)
13279         {
13280           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13281           if (name != NULL)
13282             (*info->fprintf_func) (info->stream, "%s", name);
13283           else
13284             {
13285               /* Just print the first byte as a .byte instruction.  */
13286               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13287                                      (unsigned int) priv.the_buffer[0]);
13288             }
13289
13290           return 1;
13291         }
13292
13293       return -1;
13294     }
13295
13296   obufp = obuf;
13297   sizeflag = priv.orig_sizeflag;
13298
13299   if (!ckprefix () || rex_used)
13300     {
13301       /* Too many prefixes or unused REX prefixes.  */
13302       for (i = 0;
13303            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13304            i++)
13305         (*info->fprintf_func) (info->stream, "%s%s",
13306                                i == 0 ? "" : " ",
13307                                prefix_name (all_prefixes[i], sizeflag));
13308       return i;
13309     }
13310
13311   insn_codep = codep;
13312
13313   FETCH_DATA (info, codep + 1);
13314   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13315
13316   if (((prefixes & PREFIX_FWAIT)
13317        && ((*codep < 0xd8) || (*codep > 0xdf))))
13318     {
13319       /* Handle prefixes before fwait.  */
13320       for (i = 0; i < fwait_prefix && all_prefixes[i];
13321            i++)
13322         (*info->fprintf_func) (info->stream, "%s ",
13323                                prefix_name (all_prefixes[i], sizeflag));
13324       (*info->fprintf_func) (info->stream, "fwait");
13325       return i + 1;
13326     }
13327
13328   if (*codep == 0x0f)
13329     {
13330       unsigned char threebyte;
13331
13332       codep++;
13333       FETCH_DATA (info, codep + 1);
13334       threebyte = *codep;
13335       dp = &dis386_twobyte[threebyte];
13336       need_modrm = twobyte_has_modrm[*codep];
13337       codep++;
13338     }
13339   else
13340     {
13341       dp = &dis386[*codep];
13342       need_modrm = onebyte_has_modrm[*codep];
13343       codep++;
13344     }
13345
13346   /* Save sizeflag for printing the extra prefixes later before updating
13347      it for mnemonic and operand processing.  The prefix names depend
13348      only on the address mode.  */
13349   orig_sizeflag = sizeflag;
13350   if (prefixes & PREFIX_ADDR)
13351     sizeflag ^= AFLAG;
13352   if ((prefixes & PREFIX_DATA))
13353     sizeflag ^= DFLAG;
13354
13355   end_codep = codep;
13356   if (need_modrm)
13357     {
13358       FETCH_DATA (info, codep + 1);
13359       modrm.mod = (*codep >> 6) & 3;
13360       modrm.reg = (*codep >> 3) & 7;
13361       modrm.rm = *codep & 7;
13362     }
13363
13364   need_vex = 0;
13365   need_vex_reg = 0;
13366   vex_w_done = 0;
13367   vex.evex = 0;
13368
13369   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13370     {
13371       get_sib (info, sizeflag);
13372       dofloat (sizeflag);
13373     }
13374   else
13375     {
13376       dp = get_valid_dis386 (dp, info);
13377       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13378         {
13379           get_sib (info, sizeflag);
13380           for (i = 0; i < MAX_OPERANDS; ++i)
13381             {
13382               obufp = op_out[i];
13383               op_ad = MAX_OPERANDS - 1 - i;
13384               if (dp->op[i].rtn)
13385                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13386               /* For EVEX instruction after the last operand masking
13387                  should be printed.  */
13388               if (i == 0 && vex.evex)
13389                 {
13390                   /* Don't print {%k0}.  */
13391                   if (vex.mask_register_specifier)
13392                     {
13393                       oappend ("{");
13394                       oappend (names_mask[vex.mask_register_specifier]);
13395                       oappend ("}");
13396                     }
13397                   if (vex.zeroing)
13398                     oappend ("{z}");
13399                 }
13400             }
13401         }
13402     }
13403
13404   /* Check if the REX prefix is used.  */
13405   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13406     all_prefixes[last_rex_prefix] = 0;
13407
13408   /* Check if the SEG prefix is used.  */
13409   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13410                    | PREFIX_FS | PREFIX_GS)) != 0
13411       && (used_prefixes & active_seg_prefix) != 0)
13412     all_prefixes[last_seg_prefix] = 0;
13413
13414   /* Check if the ADDR prefix is used.  */
13415   if ((prefixes & PREFIX_ADDR) != 0
13416       && (used_prefixes & PREFIX_ADDR) != 0)
13417     all_prefixes[last_addr_prefix] = 0;
13418
13419   /* Check if the DATA prefix is used.  */
13420   if ((prefixes & PREFIX_DATA) != 0
13421       && (used_prefixes & PREFIX_DATA) != 0)
13422     all_prefixes[last_data_prefix] = 0;
13423
13424   /* Print the extra prefixes.  */
13425   prefix_length = 0;
13426   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13427     if (all_prefixes[i])
13428       {
13429         const char *name;
13430         name = prefix_name (all_prefixes[i], orig_sizeflag);
13431         if (name == NULL)
13432           abort ();
13433         prefix_length += strlen (name) + 1;
13434         (*info->fprintf_func) (info->stream, "%s ", name);
13435       }
13436
13437   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13438      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13439      used by putop and MMX/SSE operand and may be overriden by the
13440      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13441      separately.  */
13442   if (dp->prefix_requirement == PREFIX_OPCODE
13443       && dp != &bad_opcode
13444       && (((prefixes
13445             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13446            && (used_prefixes
13447                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13448           || ((((prefixes
13449                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13450                 == PREFIX_DATA)
13451                && (used_prefixes & PREFIX_DATA) == 0))))
13452     {
13453       (*info->fprintf_func) (info->stream, "(bad)");
13454       return end_codep - priv.the_buffer;
13455     }
13456
13457   /* Check maximum code length.  */
13458   if ((codep - start_codep) > MAX_CODE_LENGTH)
13459     {
13460       (*info->fprintf_func) (info->stream, "(bad)");
13461       return MAX_CODE_LENGTH;
13462     }
13463
13464   obufp = mnemonicendp;
13465   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13466     oappend (" ");
13467   oappend (" ");
13468   (*info->fprintf_func) (info->stream, "%s", obuf);
13469
13470   /* The enter and bound instructions are printed with operands in the same
13471      order as the intel book; everything else is printed in reverse order.  */
13472   if (intel_syntax || two_source_ops)
13473     {
13474       bfd_vma riprel;
13475
13476       for (i = 0; i < MAX_OPERANDS; ++i)
13477         op_txt[i] = op_out[i];
13478
13479       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13480           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13481         {
13482           op_txt[2] = op_out[3];
13483           op_txt[3] = op_out[2];
13484         }
13485
13486       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13487         {
13488           op_ad = op_index[i];
13489           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13490           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13491           riprel = op_riprel[i];
13492           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13493           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13494         }
13495     }
13496   else
13497     {
13498       for (i = 0; i < MAX_OPERANDS; ++i)
13499         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13500     }
13501
13502   needcomma = 0;
13503   for (i = 0; i < MAX_OPERANDS; ++i)
13504     if (*op_txt[i])
13505       {
13506         if (needcomma)
13507           (*info->fprintf_func) (info->stream, ",");
13508         if (op_index[i] != -1 && !op_riprel[i])
13509           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13510         else
13511           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13512         needcomma = 1;
13513       }
13514
13515   for (i = 0; i < MAX_OPERANDS; i++)
13516     if (op_index[i] != -1 && op_riprel[i])
13517       {
13518         (*info->fprintf_func) (info->stream, "        # ");
13519         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13520                                                 + op_address[op_index[i]]), info);
13521         break;
13522       }
13523   return codep - priv.the_buffer;
13524 }
13525
13526 static const char *float_mem[] = {
13527   /* d8 */
13528   "fadd{s|}",
13529   "fmul{s|}",
13530   "fcom{s|}",
13531   "fcomp{s|}",
13532   "fsub{s|}",
13533   "fsubr{s|}",
13534   "fdiv{s|}",
13535   "fdivr{s|}",
13536   /* d9 */
13537   "fld{s|}",
13538   "(bad)",
13539   "fst{s|}",
13540   "fstp{s|}",
13541   "fldenvIC",
13542   "fldcw",
13543   "fNstenvIC",
13544   "fNstcw",
13545   /* da */
13546   "fiadd{l|}",
13547   "fimul{l|}",
13548   "ficom{l|}",
13549   "ficomp{l|}",
13550   "fisub{l|}",
13551   "fisubr{l|}",
13552   "fidiv{l|}",
13553   "fidivr{l|}",
13554   /* db */
13555   "fild{l|}",
13556   "fisttp{l|}",
13557   "fist{l|}",
13558   "fistp{l|}",
13559   "(bad)",
13560   "fld{t||t|}",
13561   "(bad)",
13562   "fstp{t||t|}",
13563   /* dc */
13564   "fadd{l|}",
13565   "fmul{l|}",
13566   "fcom{l|}",
13567   "fcomp{l|}",
13568   "fsub{l|}",
13569   "fsubr{l|}",
13570   "fdiv{l|}",
13571   "fdivr{l|}",
13572   /* dd */
13573   "fld{l|}",
13574   "fisttp{ll|}",
13575   "fst{l||}",
13576   "fstp{l|}",
13577   "frstorIC",
13578   "(bad)",
13579   "fNsaveIC",
13580   "fNstsw",
13581   /* de */
13582   "fiadd",
13583   "fimul",
13584   "ficom",
13585   "ficomp",
13586   "fisub",
13587   "fisubr",
13588   "fidiv",
13589   "fidivr",
13590   /* df */
13591   "fild",
13592   "fisttp",
13593   "fist",
13594   "fistp",
13595   "fbld",
13596   "fild{ll|}",
13597   "fbstp",
13598   "fistp{ll|}",
13599 };
13600
13601 static const unsigned char float_mem_mode[] = {
13602   /* d8 */
13603   d_mode,
13604   d_mode,
13605   d_mode,
13606   d_mode,
13607   d_mode,
13608   d_mode,
13609   d_mode,
13610   d_mode,
13611   /* d9 */
13612   d_mode,
13613   0,
13614   d_mode,
13615   d_mode,
13616   0,
13617   w_mode,
13618   0,
13619   w_mode,
13620   /* da */
13621   d_mode,
13622   d_mode,
13623   d_mode,
13624   d_mode,
13625   d_mode,
13626   d_mode,
13627   d_mode,
13628   d_mode,
13629   /* db */
13630   d_mode,
13631   d_mode,
13632   d_mode,
13633   d_mode,
13634   0,
13635   t_mode,
13636   0,
13637   t_mode,
13638   /* dc */
13639   q_mode,
13640   q_mode,
13641   q_mode,
13642   q_mode,
13643   q_mode,
13644   q_mode,
13645   q_mode,
13646   q_mode,
13647   /* dd */
13648   q_mode,
13649   q_mode,
13650   q_mode,
13651   q_mode,
13652   0,
13653   0,
13654   0,
13655   w_mode,
13656   /* de */
13657   w_mode,
13658   w_mode,
13659   w_mode,
13660   w_mode,
13661   w_mode,
13662   w_mode,
13663   w_mode,
13664   w_mode,
13665   /* df */
13666   w_mode,
13667   w_mode,
13668   w_mode,
13669   w_mode,
13670   t_mode,
13671   q_mode,
13672   t_mode,
13673   q_mode
13674 };
13675
13676 #define ST { OP_ST, 0 }
13677 #define STi { OP_STi, 0 }
13678
13679 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13680 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13681 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13682 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13683 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13684 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13685 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13686 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13687 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13688
13689 static const struct dis386 float_reg[][8] = {
13690   /* d8 */
13691   {
13692     { "fadd",   { ST, STi }, 0 },
13693     { "fmul",   { ST, STi }, 0 },
13694     { "fcom",   { STi }, 0 },
13695     { "fcomp",  { STi }, 0 },
13696     { "fsub",   { ST, STi }, 0 },
13697     { "fsubr",  { ST, STi }, 0 },
13698     { "fdiv",   { ST, STi }, 0 },
13699     { "fdivr",  { ST, STi }, 0 },
13700   },
13701   /* d9 */
13702   {
13703     { "fld",    { STi }, 0 },
13704     { "fxch",   { STi }, 0 },
13705     { FGRPd9_2 },
13706     { Bad_Opcode },
13707     { FGRPd9_4 },
13708     { FGRPd9_5 },
13709     { FGRPd9_6 },
13710     { FGRPd9_7 },
13711   },
13712   /* da */
13713   {
13714     { "fcmovb", { ST, STi }, 0 },
13715     { "fcmove", { ST, STi }, 0 },
13716     { "fcmovbe",{ ST, STi }, 0 },
13717     { "fcmovu", { ST, STi }, 0 },
13718     { Bad_Opcode },
13719     { FGRPda_5 },
13720     { Bad_Opcode },
13721     { Bad_Opcode },
13722   },
13723   /* db */
13724   {
13725     { "fcmovnb",{ ST, STi }, 0 },
13726     { "fcmovne",{ ST, STi }, 0 },
13727     { "fcmovnbe",{ ST, STi }, 0 },
13728     { "fcmovnu",{ ST, STi }, 0 },
13729     { FGRPdb_4 },
13730     { "fucomi", { ST, STi }, 0 },
13731     { "fcomi",  { ST, STi }, 0 },
13732     { Bad_Opcode },
13733   },
13734   /* dc */
13735   {
13736     { "fadd",   { STi, ST }, 0 },
13737     { "fmul",   { STi, ST }, 0 },
13738     { Bad_Opcode },
13739     { Bad_Opcode },
13740     { "fsub!M", { STi, ST }, 0 },
13741     { "fsubM",  { STi, ST }, 0 },
13742     { "fdiv!M", { STi, ST }, 0 },
13743     { "fdivM",  { STi, ST }, 0 },
13744   },
13745   /* dd */
13746   {
13747     { "ffree",  { STi }, 0 },
13748     { Bad_Opcode },
13749     { "fst",    { STi }, 0 },
13750     { "fstp",   { STi }, 0 },
13751     { "fucom",  { STi }, 0 },
13752     { "fucomp", { STi }, 0 },
13753     { Bad_Opcode },
13754     { Bad_Opcode },
13755   },
13756   /* de */
13757   {
13758     { "faddp",  { STi, ST }, 0 },
13759     { "fmulp",  { STi, ST }, 0 },
13760     { Bad_Opcode },
13761     { FGRPde_3 },
13762     { "fsub!Mp", { STi, ST }, 0 },
13763     { "fsubMp", { STi, ST }, 0 },
13764     { "fdiv!Mp", { STi, ST }, 0 },
13765     { "fdivMp", { STi, ST }, 0 },
13766   },
13767   /* df */
13768   {
13769     { "ffreep", { STi }, 0 },
13770     { Bad_Opcode },
13771     { Bad_Opcode },
13772     { Bad_Opcode },
13773     { FGRPdf_4 },
13774     { "fucomip", { ST, STi }, 0 },
13775     { "fcomip", { ST, STi }, 0 },
13776     { Bad_Opcode },
13777   },
13778 };
13779
13780 static char *fgrps[][8] = {
13781   /* Bad opcode 0 */
13782   {
13783     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13784   },
13785
13786   /* d9_2  1 */
13787   {
13788     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13789   },
13790
13791   /* d9_4  2 */
13792   {
13793     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13794   },
13795
13796   /* d9_5  3 */
13797   {
13798     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13799   },
13800
13801   /* d9_6  4 */
13802   {
13803     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13804   },
13805
13806   /* d9_7  5 */
13807   {
13808     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13809   },
13810
13811   /* da_5  6 */
13812   {
13813     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13814   },
13815
13816   /* db_4  7 */
13817   {
13818     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13819     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13820   },
13821
13822   /* de_3  8 */
13823   {
13824     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13825   },
13826
13827   /* df_4  9 */
13828   {
13829     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13830   },
13831 };
13832
13833 static void
13834 swap_operand (void)
13835 {
13836   mnemonicendp[0] = '.';
13837   mnemonicendp[1] = 's';
13838   mnemonicendp += 2;
13839 }
13840
13841 static void
13842 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13843                int sizeflag ATTRIBUTE_UNUSED)
13844 {
13845   /* Skip mod/rm byte.  */
13846   MODRM_CHECK;
13847   codep++;
13848 }
13849
13850 static void
13851 dofloat (int sizeflag)
13852 {
13853   const struct dis386 *dp;
13854   unsigned char floatop;
13855
13856   floatop = codep[-1];
13857
13858   if (modrm.mod != 3)
13859     {
13860       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13861
13862       putop (float_mem[fp_indx], sizeflag);
13863       obufp = op_out[0];
13864       op_ad = 2;
13865       OP_E (float_mem_mode[fp_indx], sizeflag);
13866       return;
13867     }
13868   /* Skip mod/rm byte.  */
13869   MODRM_CHECK;
13870   codep++;
13871
13872   dp = &float_reg[floatop - 0xd8][modrm.reg];
13873   if (dp->name == NULL)
13874     {
13875       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13876
13877       /* Instruction fnstsw is only one with strange arg.  */
13878       if (floatop == 0xdf && codep[-1] == 0xe0)
13879         strcpy (op_out[0], names16[0]);
13880     }
13881   else
13882     {
13883       putop (dp->name, sizeflag);
13884
13885       obufp = op_out[0];
13886       op_ad = 2;
13887       if (dp->op[0].rtn)
13888         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13889
13890       obufp = op_out[1];
13891       op_ad = 1;
13892       if (dp->op[1].rtn)
13893         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13894     }
13895 }
13896
13897 /* Like oappend (below), but S is a string starting with '%'.
13898    In Intel syntax, the '%' is elided.  */
13899 static void
13900 oappend_maybe_intel (const char *s)
13901 {
13902   oappend (s + intel_syntax);
13903 }
13904
13905 static void
13906 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13907 {
13908   oappend_maybe_intel ("%st");
13909 }
13910
13911 static void
13912 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13913 {
13914   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13915   oappend_maybe_intel (scratchbuf);
13916 }
13917
13918 /* Capital letters in template are macros.  */
13919 static int
13920 putop (const char *in_template, int sizeflag)
13921 {
13922   const char *p;
13923   int alt = 0;
13924   int cond = 1;
13925   unsigned int l = 0, len = 1;
13926   char last[4];
13927
13928 #define SAVE_LAST(c)                    \
13929   if (l < len && l < sizeof (last))     \
13930     last[l++] = c;                      \
13931   else                                  \
13932     abort ();
13933
13934   for (p = in_template; *p; p++)
13935     {
13936       switch (*p)
13937         {
13938         default:
13939           *obufp++ = *p;
13940           break;
13941         case '%':
13942           len++;
13943           break;
13944         case '!':
13945           cond = 0;
13946           break;
13947         case '{':
13948           if (intel_syntax)
13949             {
13950               while (*++p != '|')
13951                 if (*p == '}' || *p == '\0')
13952                   abort ();
13953             }
13954           /* Fall through.  */
13955         case 'I':
13956           alt = 1;
13957           continue;
13958         case '|':
13959           while (*++p != '}')
13960             {
13961               if (*p == '\0')
13962                 abort ();
13963             }
13964           break;
13965         case '}':
13966           break;
13967         case 'A':
13968           if (intel_syntax)
13969             break;
13970           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13971             *obufp++ = 'b';
13972           break;
13973         case 'B':
13974           if (l == 0 && len == 1)
13975             {
13976 case_B:
13977               if (intel_syntax)
13978                 break;
13979               if (sizeflag & SUFFIX_ALWAYS)
13980                 *obufp++ = 'b';
13981             }
13982           else
13983             {
13984               if (l != 1
13985                   || len != 2
13986                   || last[0] != 'L')
13987                 {
13988                   SAVE_LAST (*p);
13989                   break;
13990                 }
13991
13992               if (address_mode == mode_64bit
13993                   && !(prefixes & PREFIX_ADDR))
13994                 {
13995                   *obufp++ = 'a';
13996                   *obufp++ = 'b';
13997                   *obufp++ = 's';
13998                 }
13999
14000               goto case_B;
14001             }
14002           break;
14003         case 'C':
14004           if (intel_syntax && !alt)
14005             break;
14006           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14007             {
14008               if (sizeflag & DFLAG)
14009                 *obufp++ = intel_syntax ? 'd' : 'l';
14010               else
14011                 *obufp++ = intel_syntax ? 'w' : 's';
14012               used_prefixes |= (prefixes & PREFIX_DATA);
14013             }
14014           break;
14015         case 'D':
14016           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14017             break;
14018           USED_REX (REX_W);
14019           if (modrm.mod == 3)
14020             {
14021               if (rex & REX_W)
14022                 *obufp++ = 'q';
14023               else
14024                 {
14025                   if (sizeflag & DFLAG)
14026                     *obufp++ = intel_syntax ? 'd' : 'l';
14027                   else
14028                     *obufp++ = 'w';
14029                   used_prefixes |= (prefixes & PREFIX_DATA);
14030                 }
14031             }
14032           else
14033             *obufp++ = 'w';
14034           break;
14035         case 'E':               /* For jcxz/jecxz */
14036           if (address_mode == mode_64bit)
14037             {
14038               if (sizeflag & AFLAG)
14039                 *obufp++ = 'r';
14040               else
14041                 *obufp++ = 'e';
14042             }
14043           else
14044             if (sizeflag & AFLAG)
14045               *obufp++ = 'e';
14046           used_prefixes |= (prefixes & PREFIX_ADDR);
14047           break;
14048         case 'F':
14049           if (intel_syntax)
14050             break;
14051           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14052             {
14053               if (sizeflag & AFLAG)
14054                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14055               else
14056                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14057               used_prefixes |= (prefixes & PREFIX_ADDR);
14058             }
14059           break;
14060         case 'G':
14061           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14062             break;
14063           if ((rex & REX_W) || (sizeflag & DFLAG))
14064             *obufp++ = 'l';
14065           else
14066             *obufp++ = 'w';
14067           if (!(rex & REX_W))
14068             used_prefixes |= (prefixes & PREFIX_DATA);
14069           break;
14070         case 'H':
14071           if (intel_syntax)
14072             break;
14073           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14074               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14075             {
14076               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14077               *obufp++ = ',';
14078               *obufp++ = 'p';
14079               if (prefixes & PREFIX_DS)
14080                 *obufp++ = 't';
14081               else
14082                 *obufp++ = 'n';
14083             }
14084           break;
14085         case 'J':
14086           if (intel_syntax)
14087             break;
14088           *obufp++ = 'l';
14089           break;
14090         case 'K':
14091           USED_REX (REX_W);
14092           if (rex & REX_W)
14093             *obufp++ = 'q';
14094           else
14095             *obufp++ = 'd';
14096           break;
14097         case 'Z':
14098           if (l != 0 || len != 1)
14099             {
14100               if (l != 1 || len != 2 || last[0] != 'X')
14101                 {
14102                   SAVE_LAST (*p);
14103                   break;
14104                 }
14105               if (!need_vex || !vex.evex)
14106                 abort ();
14107               if (intel_syntax
14108                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14109                 break;
14110               switch (vex.length)
14111                 {
14112                 case 128:
14113                   *obufp++ = 'x';
14114                   break;
14115                 case 256:
14116                   *obufp++ = 'y';
14117                   break;
14118                 case 512:
14119                   *obufp++ = 'z';
14120                   break;
14121                 default:
14122                   abort ();
14123                 }
14124               break;
14125             }
14126           if (intel_syntax)
14127             break;
14128           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14129             {
14130               *obufp++ = 'q';
14131               break;
14132             }
14133           /* Fall through.  */
14134           goto case_L;
14135         case 'L':
14136           if (l != 0 || len != 1)
14137             {
14138               SAVE_LAST (*p);
14139               break;
14140             }
14141 case_L:
14142           if (intel_syntax)
14143             break;
14144           if (sizeflag & SUFFIX_ALWAYS)
14145             *obufp++ = 'l';
14146           break;
14147         case 'M':
14148           if (intel_mnemonic != cond)
14149             *obufp++ = 'r';
14150           break;
14151         case 'N':
14152           if ((prefixes & PREFIX_FWAIT) == 0)
14153             *obufp++ = 'n';
14154           else
14155             used_prefixes |= PREFIX_FWAIT;
14156           break;
14157         case 'O':
14158           USED_REX (REX_W);
14159           if (rex & REX_W)
14160             *obufp++ = 'o';
14161           else if (intel_syntax && (sizeflag & DFLAG))
14162             *obufp++ = 'q';
14163           else
14164             *obufp++ = 'd';
14165           if (!(rex & REX_W))
14166             used_prefixes |= (prefixes & PREFIX_DATA);
14167           break;
14168         case '&':
14169           if (!intel_syntax
14170               && address_mode == mode_64bit
14171               && isa64 == intel64)
14172             {
14173               *obufp++ = 'q';
14174               break;
14175             }
14176           /* Fall through.  */
14177         case 'T':
14178           if (!intel_syntax
14179               && address_mode == mode_64bit
14180               && ((sizeflag & DFLAG) || (rex & REX_W)))
14181             {
14182               *obufp++ = 'q';
14183               break;
14184             }
14185           /* Fall through.  */
14186           goto case_P;
14187         case 'P':
14188           if (l == 0 && len == 1)
14189             {
14190 case_P:
14191               if (intel_syntax)
14192                 {
14193                   if ((rex & REX_W) == 0
14194                       && (prefixes & PREFIX_DATA))
14195                     {
14196                       if ((sizeflag & DFLAG) == 0)
14197                         *obufp++ = 'w';
14198                       used_prefixes |= (prefixes & PREFIX_DATA);
14199                     }
14200                   break;
14201                 }
14202               if ((prefixes & PREFIX_DATA)
14203                   || (rex & REX_W)
14204                   || (sizeflag & SUFFIX_ALWAYS))
14205                 {
14206                   USED_REX (REX_W);
14207                   if (rex & REX_W)
14208                     *obufp++ = 'q';
14209                   else
14210                     {
14211                       if (sizeflag & DFLAG)
14212                         *obufp++ = 'l';
14213                       else
14214                         *obufp++ = 'w';
14215                       used_prefixes |= (prefixes & PREFIX_DATA);
14216                     }
14217                 }
14218             }
14219           else
14220             {
14221               if (l != 1 || len != 2 || last[0] != 'L')
14222                 {
14223                   SAVE_LAST (*p);
14224                   break;
14225                 }
14226
14227               if ((prefixes & PREFIX_DATA)
14228                   || (rex & REX_W)
14229                   || (sizeflag & SUFFIX_ALWAYS))
14230                 {
14231                   USED_REX (REX_W);
14232                   if (rex & REX_W)
14233                     *obufp++ = 'q';
14234                   else
14235                     {
14236                       if (sizeflag & DFLAG)
14237                         *obufp++ = intel_syntax ? 'd' : 'l';
14238                       else
14239                         *obufp++ = 'w';
14240                       used_prefixes |= (prefixes & PREFIX_DATA);
14241                     }
14242                 }
14243             }
14244           break;
14245         case 'U':
14246           if (intel_syntax)
14247             break;
14248           if (address_mode == mode_64bit
14249               && ((sizeflag & DFLAG) || (rex & REX_W)))
14250             {
14251               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14252                 *obufp++ = 'q';
14253               break;
14254             }
14255           /* Fall through.  */
14256           goto case_Q;
14257         case 'Q':
14258           if (l == 0 && len == 1)
14259             {
14260 case_Q:
14261               if (intel_syntax && !alt)
14262                 break;
14263               USED_REX (REX_W);
14264               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14265                 {
14266                   if (rex & REX_W)
14267                     *obufp++ = 'q';
14268                   else
14269                     {
14270                       if (sizeflag & DFLAG)
14271                         *obufp++ = intel_syntax ? 'd' : 'l';
14272                       else
14273                         *obufp++ = 'w';
14274                       used_prefixes |= (prefixes & PREFIX_DATA);
14275                     }
14276                 }
14277             }
14278           else
14279             {
14280               if (l != 1 || len != 2 || last[0] != 'L')
14281                 {
14282                   SAVE_LAST (*p);
14283                   break;
14284                 }
14285               if (intel_syntax
14286                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14287                 break;
14288               if ((rex & REX_W))
14289                 {
14290                   USED_REX (REX_W);
14291                   *obufp++ = 'q';
14292                 }
14293               else
14294                 *obufp++ = 'l';
14295             }
14296           break;
14297         case 'R':
14298           USED_REX (REX_W);
14299           if (rex & REX_W)
14300             *obufp++ = 'q';
14301           else if (sizeflag & DFLAG)
14302             {
14303               if (intel_syntax)
14304                   *obufp++ = 'd';
14305               else
14306                   *obufp++ = 'l';
14307             }
14308           else
14309             *obufp++ = 'w';
14310           if (intel_syntax && !p[1]
14311               && ((rex & REX_W) || (sizeflag & DFLAG)))
14312             *obufp++ = 'e';
14313           if (!(rex & REX_W))
14314             used_prefixes |= (prefixes & PREFIX_DATA);
14315           break;
14316         case 'V':
14317           if (l == 0 && len == 1)
14318             {
14319               if (intel_syntax)
14320                 break;
14321               if (address_mode == mode_64bit
14322                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14323                 {
14324                   if (sizeflag & SUFFIX_ALWAYS)
14325                     *obufp++ = 'q';
14326                   break;
14327                 }
14328             }
14329           else
14330             {
14331               if (l != 1
14332                   || len != 2
14333                   || last[0] != 'L')
14334                 {
14335                   SAVE_LAST (*p);
14336                   break;
14337                 }
14338
14339               if (rex & REX_W)
14340                 {
14341                   *obufp++ = 'a';
14342                   *obufp++ = 'b';
14343                   *obufp++ = 's';
14344                 }
14345             }
14346           /* Fall through.  */
14347           goto case_S;
14348         case 'S':
14349           if (l == 0 && len == 1)
14350             {
14351 case_S:
14352               if (intel_syntax)
14353                 break;
14354               if (sizeflag & SUFFIX_ALWAYS)
14355                 {
14356                   if (rex & REX_W)
14357                     *obufp++ = 'q';
14358                   else
14359                     {
14360                       if (sizeflag & DFLAG)
14361                         *obufp++ = 'l';
14362                       else
14363                         *obufp++ = 'w';
14364                       used_prefixes |= (prefixes & PREFIX_DATA);
14365                     }
14366                 }
14367             }
14368           else
14369             {
14370               if (l != 1
14371                   || len != 2
14372                   || last[0] != 'L')
14373                 {
14374                   SAVE_LAST (*p);
14375                   break;
14376                 }
14377
14378               if (address_mode == mode_64bit
14379                   && !(prefixes & PREFIX_ADDR))
14380                 {
14381                   *obufp++ = 'a';
14382                   *obufp++ = 'b';
14383                   *obufp++ = 's';
14384                 }
14385
14386               goto case_S;
14387             }
14388           break;
14389         case 'X':
14390           if (l != 0 || len != 1)
14391             {
14392               SAVE_LAST (*p);
14393               break;
14394             }
14395           if (need_vex && vex.prefix)
14396             {
14397               if (vex.prefix == DATA_PREFIX_OPCODE)
14398                 *obufp++ = 'd';
14399               else
14400                 *obufp++ = 's';
14401             }
14402           else
14403             {
14404               if (prefixes & PREFIX_DATA)
14405                 *obufp++ = 'd';
14406               else
14407                 *obufp++ = 's';
14408               used_prefixes |= (prefixes & PREFIX_DATA);
14409             }
14410           break;
14411         case 'Y':
14412           if (l == 0 && len == 1)
14413             {
14414               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14415                 break;
14416               if (rex & REX_W)
14417                 {
14418                   USED_REX (REX_W);
14419                   *obufp++ = 'q';
14420                 }
14421               break;
14422             }
14423           else
14424             {
14425               if (l != 1 || len != 2 || last[0] != 'X')
14426                 {
14427                   SAVE_LAST (*p);
14428                   break;
14429                 }
14430               if (!need_vex)
14431                 abort ();
14432               if (intel_syntax
14433                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14434                 break;
14435               switch (vex.length)
14436                 {
14437                 case 128:
14438                   *obufp++ = 'x';
14439                   break;
14440                 case 256:
14441                   *obufp++ = 'y';
14442                   break;
14443                 case 512:
14444                   if (!vex.evex)
14445                 default:
14446                     abort ();
14447                 }
14448             }
14449           break;
14450         case 'W':
14451           if (l == 0 && len == 1)
14452             {
14453               /* operand size flag for cwtl, cbtw */
14454               USED_REX (REX_W);
14455               if (rex & REX_W)
14456                 {
14457                   if (intel_syntax)
14458                     *obufp++ = 'd';
14459                   else
14460                     *obufp++ = 'l';
14461                 }
14462               else if (sizeflag & DFLAG)
14463                 *obufp++ = 'w';
14464               else
14465                 *obufp++ = 'b';
14466               if (!(rex & REX_W))
14467                 used_prefixes |= (prefixes & PREFIX_DATA);
14468             }
14469           else
14470             {
14471               if (l != 1
14472                   || len != 2
14473                   || (last[0] != 'X'
14474                       && last[0] != 'L'))
14475                 {
14476                   SAVE_LAST (*p);
14477                   break;
14478                 }
14479               if (!need_vex)
14480                 abort ();
14481               if (last[0] == 'X')
14482                 *obufp++ = vex.w ? 'd': 's';
14483               else
14484                 *obufp++ = vex.w ? 'q': 'd';
14485             }
14486           break;
14487         case '^':
14488           if (intel_syntax)
14489             break;
14490           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14491             {
14492               if (sizeflag & DFLAG)
14493                 *obufp++ = 'l';
14494               else
14495                 *obufp++ = 'w';
14496               used_prefixes |= (prefixes & PREFIX_DATA);
14497             }
14498           break;
14499         case '@':
14500           if (intel_syntax)
14501             break;
14502           if (address_mode == mode_64bit
14503               && (isa64 == intel64
14504                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14505               *obufp++ = 'q';
14506           else if ((prefixes & PREFIX_DATA))
14507             {
14508               if (!(sizeflag & DFLAG))
14509                 *obufp++ = 'w';
14510               used_prefixes |= (prefixes & PREFIX_DATA);
14511             }
14512           break;
14513         }
14514       alt = 0;
14515     }
14516   *obufp = 0;
14517   mnemonicendp = obufp;
14518   return 0;
14519 }
14520
14521 static void
14522 oappend (const char *s)
14523 {
14524   obufp = stpcpy (obufp, s);
14525 }
14526
14527 static void
14528 append_seg (void)
14529 {
14530   /* Only print the active segment register.  */
14531   if (!active_seg_prefix)
14532     return;
14533
14534   used_prefixes |= active_seg_prefix;
14535   switch (active_seg_prefix)
14536     {
14537     case PREFIX_CS:
14538       oappend_maybe_intel ("%cs:");
14539       break;
14540     case PREFIX_DS:
14541       oappend_maybe_intel ("%ds:");
14542       break;
14543     case PREFIX_SS:
14544       oappend_maybe_intel ("%ss:");
14545       break;
14546     case PREFIX_ES:
14547       oappend_maybe_intel ("%es:");
14548       break;
14549     case PREFIX_FS:
14550       oappend_maybe_intel ("%fs:");
14551       break;
14552     case PREFIX_GS:
14553       oappend_maybe_intel ("%gs:");
14554       break;
14555     default:
14556       break;
14557     }
14558 }
14559
14560 static void
14561 OP_indirE (int bytemode, int sizeflag)
14562 {
14563   if (!intel_syntax)
14564     oappend ("*");
14565   OP_E (bytemode, sizeflag);
14566 }
14567
14568 static void
14569 print_operand_value (char *buf, int hex, bfd_vma disp)
14570 {
14571   if (address_mode == mode_64bit)
14572     {
14573       if (hex)
14574         {
14575           char tmp[30];
14576           int i;
14577           buf[0] = '0';
14578           buf[1] = 'x';
14579           sprintf_vma (tmp, disp);
14580           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14581           strcpy (buf + 2, tmp + i);
14582         }
14583       else
14584         {
14585           bfd_signed_vma v = disp;
14586           char tmp[30];
14587           int i;
14588           if (v < 0)
14589             {
14590               *(buf++) = '-';
14591               v = -disp;
14592               /* Check for possible overflow on 0x8000000000000000.  */
14593               if (v < 0)
14594                 {
14595                   strcpy (buf, "9223372036854775808");
14596                   return;
14597                 }
14598             }
14599           if (!v)
14600             {
14601               strcpy (buf, "0");
14602               return;
14603             }
14604
14605           i = 0;
14606           tmp[29] = 0;
14607           while (v)
14608             {
14609               tmp[28 - i] = (v % 10) + '0';
14610               v /= 10;
14611               i++;
14612             }
14613           strcpy (buf, tmp + 29 - i);
14614         }
14615     }
14616   else
14617     {
14618       if (hex)
14619         sprintf (buf, "0x%x", (unsigned int) disp);
14620       else
14621         sprintf (buf, "%d", (int) disp);
14622     }
14623 }
14624
14625 /* Put DISP in BUF as signed hex number.  */
14626
14627 static void
14628 print_displacement (char *buf, bfd_vma disp)
14629 {
14630   bfd_signed_vma val = disp;
14631   char tmp[30];
14632   int i, j = 0;
14633
14634   if (val < 0)
14635     {
14636       buf[j++] = '-';
14637       val = -disp;
14638
14639       /* Check for possible overflow.  */
14640       if (val < 0)
14641         {
14642           switch (address_mode)
14643             {
14644             case mode_64bit:
14645               strcpy (buf + j, "0x8000000000000000");
14646               break;
14647             case mode_32bit:
14648               strcpy (buf + j, "0x80000000");
14649               break;
14650             case mode_16bit:
14651               strcpy (buf + j, "0x8000");
14652               break;
14653             }
14654           return;
14655         }
14656     }
14657
14658   buf[j++] = '0';
14659   buf[j++] = 'x';
14660
14661   sprintf_vma (tmp, (bfd_vma) val);
14662   for (i = 0; tmp[i] == '0'; i++)
14663     continue;
14664   if (tmp[i] == '\0')
14665     i--;
14666   strcpy (buf + j, tmp + i);
14667 }
14668
14669 static void
14670 intel_operand_size (int bytemode, int sizeflag)
14671 {
14672   if (vex.evex
14673       && vex.b
14674       && (bytemode == x_mode
14675           || bytemode == evex_half_bcst_xmmq_mode))
14676     {
14677       if (vex.w)
14678         oappend ("QWORD PTR ");
14679       else
14680         oappend ("DWORD PTR ");
14681       return;
14682     }
14683   switch (bytemode)
14684     {
14685     case b_mode:
14686     case b_swap_mode:
14687     case dqb_mode:
14688     case db_mode:
14689       oappend ("BYTE PTR ");
14690       break;
14691     case w_mode:
14692     case dw_mode:
14693     case dqw_mode:
14694       oappend ("WORD PTR ");
14695       break;
14696     case indir_v_mode:
14697       if (address_mode == mode_64bit && isa64 == intel64)
14698         {
14699           oappend ("QWORD PTR ");
14700           break;
14701         }
14702       /* Fall through.  */
14703     case stack_v_mode:
14704       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14705         {
14706           oappend ("QWORD PTR ");
14707           break;
14708         }
14709       /* Fall through.  */
14710     case v_mode:
14711     case v_swap_mode:
14712     case dq_mode:
14713       USED_REX (REX_W);
14714       if (rex & REX_W)
14715         oappend ("QWORD PTR ");
14716       else
14717         {
14718           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14719             oappend ("DWORD PTR ");
14720           else
14721             oappend ("WORD PTR ");
14722           used_prefixes |= (prefixes & PREFIX_DATA);
14723         }
14724       break;
14725     case z_mode:
14726       if ((rex & REX_W) || (sizeflag & DFLAG))
14727         *obufp++ = 'D';
14728       oappend ("WORD PTR ");
14729       if (!(rex & REX_W))
14730         used_prefixes |= (prefixes & PREFIX_DATA);
14731       break;
14732     case a_mode:
14733       if (sizeflag & DFLAG)
14734         oappend ("QWORD PTR ");
14735       else
14736         oappend ("DWORD PTR ");
14737       used_prefixes |= (prefixes & PREFIX_DATA);
14738       break;
14739     case d_mode:
14740     case d_scalar_mode:
14741     case d_scalar_swap_mode:
14742     case d_swap_mode:
14743     case dqd_mode:
14744       oappend ("DWORD PTR ");
14745       break;
14746     case q_mode:
14747     case q_scalar_mode:
14748     case q_scalar_swap_mode:
14749     case q_swap_mode:
14750       oappend ("QWORD PTR ");
14751       break;
14752     case m_mode:
14753       if (address_mode == mode_64bit)
14754         oappend ("QWORD PTR ");
14755       else
14756         oappend ("DWORD PTR ");
14757       break;
14758     case f_mode:
14759       if (sizeflag & DFLAG)
14760         oappend ("FWORD PTR ");
14761       else
14762         oappend ("DWORD PTR ");
14763       used_prefixes |= (prefixes & PREFIX_DATA);
14764       break;
14765     case t_mode:
14766       oappend ("TBYTE PTR ");
14767       break;
14768     case x_mode:
14769     case x_swap_mode:
14770     case evex_x_gscat_mode:
14771     case evex_x_nobcst_mode:
14772     case b_scalar_mode:
14773     case w_scalar_mode:
14774       if (need_vex)
14775         {
14776           switch (vex.length)
14777             {
14778             case 128:
14779               oappend ("XMMWORD PTR ");
14780               break;
14781             case 256:
14782               oappend ("YMMWORD PTR ");
14783               break;
14784             case 512:
14785               oappend ("ZMMWORD PTR ");
14786               break;
14787             default:
14788               abort ();
14789             }
14790         }
14791       else
14792         oappend ("XMMWORD PTR ");
14793       break;
14794     case xmm_mode:
14795       oappend ("XMMWORD PTR ");
14796       break;
14797     case ymm_mode:
14798       oappend ("YMMWORD PTR ");
14799       break;
14800     case xmmq_mode:
14801     case evex_half_bcst_xmmq_mode:
14802       if (!need_vex)
14803         abort ();
14804
14805       switch (vex.length)
14806         {
14807         case 128:
14808           oappend ("QWORD PTR ");
14809           break;
14810         case 256:
14811           oappend ("XMMWORD PTR ");
14812           break;
14813         case 512:
14814           oappend ("YMMWORD PTR ");
14815           break;
14816         default:
14817           abort ();
14818         }
14819       break;
14820     case xmm_mb_mode:
14821       if (!need_vex)
14822         abort ();
14823
14824       switch (vex.length)
14825         {
14826         case 128:
14827         case 256:
14828         case 512:
14829           oappend ("BYTE PTR ");
14830           break;
14831         default:
14832           abort ();
14833         }
14834       break;
14835     case xmm_mw_mode:
14836       if (!need_vex)
14837         abort ();
14838
14839       switch (vex.length)
14840         {
14841         case 128:
14842         case 256:
14843         case 512:
14844           oappend ("WORD PTR ");
14845           break;
14846         default:
14847           abort ();
14848         }
14849       break;
14850     case xmm_md_mode:
14851       if (!need_vex)
14852         abort ();
14853
14854       switch (vex.length)
14855         {
14856         case 128:
14857         case 256:
14858         case 512:
14859           oappend ("DWORD PTR ");
14860           break;
14861         default:
14862           abort ();
14863         }
14864       break;
14865     case xmm_mq_mode:
14866       if (!need_vex)
14867         abort ();
14868
14869       switch (vex.length)
14870         {
14871         case 128:
14872         case 256:
14873         case 512:
14874           oappend ("QWORD PTR ");
14875           break;
14876         default:
14877           abort ();
14878         }
14879       break;
14880     case xmmdw_mode:
14881       if (!need_vex)
14882         abort ();
14883
14884       switch (vex.length)
14885         {
14886         case 128:
14887           oappend ("WORD PTR ");
14888           break;
14889         case 256:
14890           oappend ("DWORD PTR ");
14891           break;
14892         case 512:
14893           oappend ("QWORD PTR ");
14894           break;
14895         default:
14896           abort ();
14897         }
14898       break;
14899     case xmmqd_mode:
14900       if (!need_vex)
14901         abort ();
14902
14903       switch (vex.length)
14904         {
14905         case 128:
14906           oappend ("DWORD PTR ");
14907           break;
14908         case 256:
14909           oappend ("QWORD PTR ");
14910           break;
14911         case 512:
14912           oappend ("XMMWORD PTR ");
14913           break;
14914         default:
14915           abort ();
14916         }
14917       break;
14918     case ymmq_mode:
14919       if (!need_vex)
14920         abort ();
14921
14922       switch (vex.length)
14923         {
14924         case 128:
14925           oappend ("QWORD PTR ");
14926           break;
14927         case 256:
14928           oappend ("YMMWORD PTR ");
14929           break;
14930         case 512:
14931           oappend ("ZMMWORD PTR ");
14932           break;
14933         default:
14934           abort ();
14935         }
14936       break;
14937     case ymmxmm_mode:
14938       if (!need_vex)
14939         abort ();
14940
14941       switch (vex.length)
14942         {
14943         case 128:
14944         case 256:
14945           oappend ("XMMWORD PTR ");
14946           break;
14947         default:
14948           abort ();
14949         }
14950       break;
14951     case o_mode:
14952       oappend ("OWORD PTR ");
14953       break;
14954     case xmm_mdq_mode:
14955     case vex_w_dq_mode:
14956     case vex_scalar_w_dq_mode:
14957       if (!need_vex)
14958         abort ();
14959
14960       if (vex.w)
14961         oappend ("QWORD PTR ");
14962       else
14963         oappend ("DWORD PTR ");
14964       break;
14965     case vex_vsib_d_w_dq_mode:
14966     case vex_vsib_q_w_dq_mode:
14967       if (!need_vex)
14968         abort ();
14969
14970       if (!vex.evex)
14971         {
14972           if (vex.w)
14973             oappend ("QWORD PTR ");
14974           else
14975             oappend ("DWORD PTR ");
14976         }
14977       else
14978         {
14979           switch (vex.length)
14980             {
14981             case 128:
14982               oappend ("XMMWORD PTR ");
14983               break;
14984             case 256:
14985               oappend ("YMMWORD PTR ");
14986               break;
14987             case 512:
14988               oappend ("ZMMWORD PTR ");
14989               break;
14990             default:
14991               abort ();
14992             }
14993         }
14994       break;
14995     case vex_vsib_q_w_d_mode:
14996     case vex_vsib_d_w_d_mode:
14997       if (!need_vex || !vex.evex)
14998         abort ();
14999
15000       switch (vex.length)
15001         {
15002         case 128:
15003           oappend ("QWORD PTR ");
15004           break;
15005         case 256:
15006           oappend ("XMMWORD PTR ");
15007           break;
15008         case 512:
15009           oappend ("YMMWORD PTR ");
15010           break;
15011         default:
15012           abort ();
15013         }
15014
15015       break;
15016     case mask_bd_mode:
15017       if (!need_vex || vex.length != 128)
15018         abort ();
15019       if (vex.w)
15020         oappend ("DWORD PTR ");
15021       else
15022         oappend ("BYTE PTR ");
15023       break;
15024     case mask_mode:
15025       if (!need_vex)
15026         abort ();
15027       if (vex.w)
15028         oappend ("QWORD PTR ");
15029       else
15030         oappend ("WORD PTR ");
15031       break;
15032     case v_bnd_mode:
15033     default:
15034       break;
15035     }
15036 }
15037
15038 static void
15039 OP_E_register (int bytemode, int sizeflag)
15040 {
15041   int reg = modrm.rm;
15042   const char **names;
15043
15044   USED_REX (REX_B);
15045   if ((rex & REX_B))
15046     reg += 8;
15047
15048   if ((sizeflag & SUFFIX_ALWAYS)
15049       && (bytemode == b_swap_mode
15050           || bytemode == v_swap_mode))
15051     swap_operand ();
15052
15053   switch (bytemode)
15054     {
15055     case b_mode:
15056     case b_swap_mode:
15057       USED_REX (0);
15058       if (rex)
15059         names = names8rex;
15060       else
15061         names = names8;
15062       break;
15063     case w_mode:
15064       names = names16;
15065       break;
15066     case d_mode:
15067     case dw_mode:
15068     case db_mode:
15069       names = names32;
15070       break;
15071     case q_mode:
15072       names = names64;
15073       break;
15074     case m_mode:
15075     case v_bnd_mode:
15076       names = address_mode == mode_64bit ? names64 : names32;
15077       break;
15078     case bnd_mode:
15079       if (reg > 0x3)
15080         {
15081           oappend ("(bad)");
15082           return;
15083         }
15084       names = names_bnd;
15085       break;
15086     case indir_v_mode:
15087       if (address_mode == mode_64bit && isa64 == intel64)
15088         {
15089           names = names64;
15090           break;
15091         }
15092       /* Fall through.  */
15093     case stack_v_mode:
15094       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15095         {
15096           names = names64;
15097           break;
15098         }
15099       bytemode = v_mode;
15100       /* Fall through.  */
15101     case v_mode:
15102     case v_swap_mode:
15103     case dq_mode:
15104     case dqb_mode:
15105     case dqd_mode:
15106     case dqw_mode:
15107       USED_REX (REX_W);
15108       if (rex & REX_W)
15109         names = names64;
15110       else
15111         {
15112           if ((sizeflag & DFLAG)
15113               || (bytemode != v_mode
15114                   && bytemode != v_swap_mode))
15115             names = names32;
15116           else
15117             names = names16;
15118           used_prefixes |= (prefixes & PREFIX_DATA);
15119         }
15120       break;
15121     case mask_bd_mode:
15122     case mask_mode:
15123       if (reg > 0x7)
15124         {
15125           oappend ("(bad)");
15126           return;
15127         }
15128       names = names_mask;
15129       break;
15130     case 0:
15131       return;
15132     default:
15133       oappend (INTERNAL_DISASSEMBLER_ERROR);
15134       return;
15135     }
15136   oappend (names[reg]);
15137 }
15138
15139 static void
15140 OP_E_memory (int bytemode, int sizeflag)
15141 {
15142   bfd_vma disp = 0;
15143   int add = (rex & REX_B) ? 8 : 0;
15144   int riprel = 0;
15145   int shift;
15146
15147   if (vex.evex)
15148     {
15149       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15150       if (vex.b
15151           && bytemode != x_mode
15152           && bytemode != xmmq_mode
15153           && bytemode != evex_half_bcst_xmmq_mode)
15154         {
15155           BadOp ();
15156           return;
15157         }
15158       switch (bytemode)
15159         {
15160         case dqw_mode:
15161         case dw_mode:
15162           shift = 1;
15163           break;
15164         case dqb_mode:
15165         case db_mode:
15166           shift = 0;
15167           break;
15168         case vex_vsib_d_w_dq_mode:
15169         case vex_vsib_d_w_d_mode:
15170         case vex_vsib_q_w_dq_mode:
15171         case vex_vsib_q_w_d_mode:
15172         case evex_x_gscat_mode:
15173         case xmm_mdq_mode:
15174           shift = vex.w ? 3 : 2;
15175           break;
15176         case x_mode:
15177         case evex_half_bcst_xmmq_mode:
15178         case xmmq_mode:
15179           if (vex.b)
15180             {
15181               shift = vex.w ? 3 : 2;
15182               break;
15183             }
15184           /* Fall through.  */
15185         case xmmqd_mode:
15186         case xmmdw_mode:
15187         case ymmq_mode:
15188         case evex_x_nobcst_mode:
15189         case x_swap_mode:
15190           switch (vex.length)
15191             {
15192             case 128:
15193               shift = 4;
15194               break;
15195             case 256:
15196               shift = 5;
15197               break;
15198             case 512:
15199               shift = 6;
15200               break;
15201             default:
15202               abort ();
15203             }
15204           break;
15205         case ymm_mode:
15206           shift = 5;
15207           break;
15208         case xmm_mode:
15209           shift = 4;
15210           break;
15211         case xmm_mq_mode:
15212         case q_mode:
15213         case q_scalar_mode:
15214         case q_swap_mode:
15215         case q_scalar_swap_mode:
15216           shift = 3;
15217           break;
15218         case dqd_mode:
15219         case xmm_md_mode:
15220         case d_mode:
15221         case d_scalar_mode:
15222         case d_swap_mode:
15223         case d_scalar_swap_mode:
15224           shift = 2;
15225           break;
15226     case w_scalar_mode:
15227         case xmm_mw_mode:
15228           shift = 1;
15229           break;
15230     case b_scalar_mode:
15231         case xmm_mb_mode:
15232           shift = 0;
15233           break;
15234         default:
15235           abort ();
15236         }
15237       /* Make necessary corrections to shift for modes that need it.
15238          For these modes we currently have shift 4, 5 or 6 depending on
15239          vex.length (it corresponds to xmmword, ymmword or zmmword
15240          operand).  We might want to make it 3, 4 or 5 (e.g. for
15241          xmmq_mode).  In case of broadcast enabled the corrections
15242          aren't needed, as element size is always 32 or 64 bits.  */
15243       if (!vex.b
15244           && (bytemode == xmmq_mode
15245               || bytemode == evex_half_bcst_xmmq_mode))
15246         shift -= 1;
15247       else if (bytemode == xmmqd_mode)
15248         shift -= 2;
15249       else if (bytemode == xmmdw_mode)
15250         shift -= 3;
15251       else if (bytemode == ymmq_mode && vex.length == 128)
15252         shift -= 1;
15253     }
15254   else
15255     shift = 0;
15256
15257   USED_REX (REX_B);
15258   if (intel_syntax)
15259     intel_operand_size (bytemode, sizeflag);
15260   append_seg ();
15261
15262   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15263     {
15264       /* 32/64 bit address mode */
15265       int havedisp;
15266       int havesib;
15267       int havebase;
15268       int haveindex;
15269       int needindex;
15270       int base, rbase;
15271       int vindex = 0;
15272       int scale = 0;
15273       int addr32flag = !((sizeflag & AFLAG)
15274                          || bytemode == v_bnd_mode
15275                          || bytemode == bnd_mode);
15276       const char **indexes64 = names64;
15277       const char **indexes32 = names32;
15278
15279       havesib = 0;
15280       havebase = 1;
15281       haveindex = 0;
15282       base = modrm.rm;
15283
15284       if (base == 4)
15285         {
15286           havesib = 1;
15287           vindex = sib.index;
15288           USED_REX (REX_X);
15289           if (rex & REX_X)
15290             vindex += 8;
15291           switch (bytemode)
15292             {
15293             case vex_vsib_d_w_dq_mode:
15294             case vex_vsib_d_w_d_mode:
15295             case vex_vsib_q_w_dq_mode:
15296             case vex_vsib_q_w_d_mode:
15297               if (!need_vex)
15298                 abort ();
15299               if (vex.evex)
15300                 {
15301                   if (!vex.v)
15302                     vindex += 16;
15303                 }
15304
15305               haveindex = 1;
15306               switch (vex.length)
15307                 {
15308                 case 128:
15309                   indexes64 = indexes32 = names_xmm;
15310                   break;
15311                 case 256:
15312                   if (!vex.w
15313                       || bytemode == vex_vsib_q_w_dq_mode
15314                       || bytemode == vex_vsib_q_w_d_mode)
15315                     indexes64 = indexes32 = names_ymm;
15316                   else
15317                     indexes64 = indexes32 = names_xmm;
15318                   break;
15319                 case 512:
15320                   if (!vex.w
15321                       || bytemode == vex_vsib_q_w_dq_mode
15322                       || bytemode == vex_vsib_q_w_d_mode)
15323                     indexes64 = indexes32 = names_zmm;
15324                   else
15325                     indexes64 = indexes32 = names_ymm;
15326                   break;
15327                 default:
15328                   abort ();
15329                 }
15330               break;
15331             default:
15332               haveindex = vindex != 4;
15333               break;
15334             }
15335           scale = sib.scale;
15336           base = sib.base;
15337           codep++;
15338         }
15339       rbase = base + add;
15340
15341       switch (modrm.mod)
15342         {
15343         case 0:
15344           if (base == 5)
15345             {
15346               havebase = 0;
15347               if (address_mode == mode_64bit && !havesib)
15348                 riprel = 1;
15349               disp = get32s ();
15350             }
15351           break;
15352         case 1:
15353           FETCH_DATA (the_info, codep + 1);
15354           disp = *codep++;
15355           if ((disp & 0x80) != 0)
15356             disp -= 0x100;
15357           if (vex.evex && shift > 0)
15358             disp <<= shift;
15359           break;
15360         case 2:
15361           disp = get32s ();
15362           break;
15363         }
15364
15365       /* In 32bit mode, we need index register to tell [offset] from
15366          [eiz*1 + offset].  */
15367       needindex = (havesib
15368                    && !havebase
15369                    && !haveindex
15370                    && address_mode == mode_32bit);
15371       havedisp = (havebase
15372                   || needindex
15373                   || (havesib && (haveindex || scale != 0)));
15374
15375       if (!intel_syntax)
15376         if (modrm.mod != 0 || base == 5)
15377           {
15378             if (havedisp || riprel)
15379               print_displacement (scratchbuf, disp);
15380             else
15381               print_operand_value (scratchbuf, 1, disp);
15382             oappend (scratchbuf);
15383             if (riprel)
15384               {
15385                 set_op (disp, 1);
15386                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15387               }
15388           }
15389
15390       if ((havebase || haveindex || riprel)
15391           && (bytemode != v_bnd_mode)
15392           && (bytemode != bnd_mode))
15393         used_prefixes |= PREFIX_ADDR;
15394
15395       if (havedisp || (intel_syntax && riprel))
15396         {
15397           *obufp++ = open_char;
15398           if (intel_syntax && riprel)
15399             {
15400               set_op (disp, 1);
15401               oappend (!addr32flag ? "rip" : "eip");
15402             }
15403           *obufp = '\0';
15404           if (havebase)
15405             oappend (address_mode == mode_64bit && !addr32flag
15406                      ? names64[rbase] : names32[rbase]);
15407           if (havesib)
15408             {
15409               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15410                  print index to tell base + index from base.  */
15411               if (scale != 0
15412                   || needindex
15413                   || haveindex
15414                   || (havebase && base != ESP_REG_NUM))
15415                 {
15416                   if (!intel_syntax || havebase)
15417                     {
15418                       *obufp++ = separator_char;
15419                       *obufp = '\0';
15420                     }
15421                   if (haveindex)
15422                     oappend (address_mode == mode_64bit && !addr32flag
15423                              ? indexes64[vindex] : indexes32[vindex]);
15424                   else
15425                     oappend (address_mode == mode_64bit && !addr32flag
15426                              ? index64 : index32);
15427
15428                   *obufp++ = scale_char;
15429                   *obufp = '\0';
15430                   sprintf (scratchbuf, "%d", 1 << scale);
15431                   oappend (scratchbuf);
15432                 }
15433             }
15434           if (intel_syntax
15435               && (disp || modrm.mod != 0 || base == 5))
15436             {
15437               if (!havedisp || (bfd_signed_vma) disp >= 0)
15438                 {
15439                   *obufp++ = '+';
15440                   *obufp = '\0';
15441                 }
15442               else if (modrm.mod != 1 && disp != -disp)
15443                 {
15444                   *obufp++ = '-';
15445                   *obufp = '\0';
15446                   disp = - (bfd_signed_vma) disp;
15447                 }
15448
15449               if (havedisp)
15450                 print_displacement (scratchbuf, disp);
15451               else
15452                 print_operand_value (scratchbuf, 1, disp);
15453               oappend (scratchbuf);
15454             }
15455
15456           *obufp++ = close_char;
15457           *obufp = '\0';
15458         }
15459       else if (intel_syntax)
15460         {
15461           if (modrm.mod != 0 || base == 5)
15462             {
15463               if (!active_seg_prefix)
15464                 {
15465                   oappend (names_seg[ds_reg - es_reg]);
15466                   oappend (":");
15467                 }
15468               print_operand_value (scratchbuf, 1, disp);
15469               oappend (scratchbuf);
15470             }
15471         }
15472     }
15473   else
15474     {
15475       /* 16 bit address mode */
15476       used_prefixes |= prefixes & PREFIX_ADDR;
15477       switch (modrm.mod)
15478         {
15479         case 0:
15480           if (modrm.rm == 6)
15481             {
15482               disp = get16 ();
15483               if ((disp & 0x8000) != 0)
15484                 disp -= 0x10000;
15485             }
15486           break;
15487         case 1:
15488           FETCH_DATA (the_info, codep + 1);
15489           disp = *codep++;
15490           if ((disp & 0x80) != 0)
15491             disp -= 0x100;
15492           break;
15493         case 2:
15494           disp = get16 ();
15495           if ((disp & 0x8000) != 0)
15496             disp -= 0x10000;
15497           break;
15498         }
15499
15500       if (!intel_syntax)
15501         if (modrm.mod != 0 || modrm.rm == 6)
15502           {
15503             print_displacement (scratchbuf, disp);
15504             oappend (scratchbuf);
15505           }
15506
15507       if (modrm.mod != 0 || modrm.rm != 6)
15508         {
15509           *obufp++ = open_char;
15510           *obufp = '\0';
15511           oappend (index16[modrm.rm]);
15512           if (intel_syntax
15513               && (disp || modrm.mod != 0 || modrm.rm == 6))
15514             {
15515               if ((bfd_signed_vma) disp >= 0)
15516                 {
15517                   *obufp++ = '+';
15518                   *obufp = '\0';
15519                 }
15520               else if (modrm.mod != 1)
15521                 {
15522                   *obufp++ = '-';
15523                   *obufp = '\0';
15524                   disp = - (bfd_signed_vma) disp;
15525                 }
15526
15527               print_displacement (scratchbuf, disp);
15528               oappend (scratchbuf);
15529             }
15530
15531           *obufp++ = close_char;
15532           *obufp = '\0';
15533         }
15534       else if (intel_syntax)
15535         {
15536           if (!active_seg_prefix)
15537             {
15538               oappend (names_seg[ds_reg - es_reg]);
15539               oappend (":");
15540             }
15541           print_operand_value (scratchbuf, 1, disp & 0xffff);
15542           oappend (scratchbuf);
15543         }
15544     }
15545   if (vex.evex && vex.b
15546       && (bytemode == x_mode
15547           || bytemode == xmmq_mode
15548           || bytemode == evex_half_bcst_xmmq_mode))
15549     {
15550       if (vex.w
15551           || bytemode == xmmq_mode
15552           || bytemode == evex_half_bcst_xmmq_mode)
15553         {
15554           switch (vex.length)
15555             {
15556             case 128:
15557               oappend ("{1to2}");
15558               break;
15559             case 256:
15560               oappend ("{1to4}");
15561               break;
15562             case 512:
15563               oappend ("{1to8}");
15564               break;
15565             default:
15566               abort ();
15567             }
15568         }
15569       else
15570         {
15571           switch (vex.length)
15572             {
15573             case 128:
15574               oappend ("{1to4}");
15575               break;
15576             case 256:
15577               oappend ("{1to8}");
15578               break;
15579             case 512:
15580               oappend ("{1to16}");
15581               break;
15582             default:
15583               abort ();
15584             }
15585         }
15586     }
15587 }
15588
15589 static void
15590 OP_E (int bytemode, int sizeflag)
15591 {
15592   /* Skip mod/rm byte.  */
15593   MODRM_CHECK;
15594   codep++;
15595
15596   if (modrm.mod == 3)
15597     OP_E_register (bytemode, sizeflag);
15598   else
15599     OP_E_memory (bytemode, sizeflag);
15600 }
15601
15602 static void
15603 OP_G (int bytemode, int sizeflag)
15604 {
15605   int add = 0;
15606   USED_REX (REX_R);
15607   if (rex & REX_R)
15608     add += 8;
15609   switch (bytemode)
15610     {
15611     case b_mode:
15612       USED_REX (0);
15613       if (rex)
15614         oappend (names8rex[modrm.reg + add]);
15615       else
15616         oappend (names8[modrm.reg + add]);
15617       break;
15618     case w_mode:
15619       oappend (names16[modrm.reg + add]);
15620       break;
15621     case d_mode:
15622     case db_mode:
15623     case dw_mode:
15624       oappend (names32[modrm.reg + add]);
15625       break;
15626     case q_mode:
15627       oappend (names64[modrm.reg + add]);
15628       break;
15629     case bnd_mode:
15630       if (modrm.reg > 0x3)
15631         {
15632           oappend ("(bad)");
15633           return;
15634         }
15635       oappend (names_bnd[modrm.reg]);
15636       break;
15637     case v_mode:
15638     case dq_mode:
15639     case dqb_mode:
15640     case dqd_mode:
15641     case dqw_mode:
15642       USED_REX (REX_W);
15643       if (rex & REX_W)
15644         oappend (names64[modrm.reg + add]);
15645       else
15646         {
15647           if ((sizeflag & DFLAG) || bytemode != v_mode)
15648             oappend (names32[modrm.reg + add]);
15649           else
15650             oappend (names16[modrm.reg + add]);
15651           used_prefixes |= (prefixes & PREFIX_DATA);
15652         }
15653       break;
15654     case m_mode:
15655       if (address_mode == mode_64bit)
15656         oappend (names64[modrm.reg + add]);
15657       else
15658         oappend (names32[modrm.reg + add]);
15659       break;
15660     case mask_bd_mode:
15661     case mask_mode:
15662       if ((modrm.reg + add) > 0x7)
15663         {
15664           oappend ("(bad)");
15665           return;
15666         }
15667       oappend (names_mask[modrm.reg + add]);
15668       break;
15669     default:
15670       oappend (INTERNAL_DISASSEMBLER_ERROR);
15671       break;
15672     }
15673 }
15674
15675 static bfd_vma
15676 get64 (void)
15677 {
15678   bfd_vma x;
15679 #ifdef BFD64
15680   unsigned int a;
15681   unsigned int b;
15682
15683   FETCH_DATA (the_info, codep + 8);
15684   a = *codep++ & 0xff;
15685   a |= (*codep++ & 0xff) << 8;
15686   a |= (*codep++ & 0xff) << 16;
15687   a |= (*codep++ & 0xffu) << 24;
15688   b = *codep++ & 0xff;
15689   b |= (*codep++ & 0xff) << 8;
15690   b |= (*codep++ & 0xff) << 16;
15691   b |= (*codep++ & 0xffu) << 24;
15692   x = a + ((bfd_vma) b << 32);
15693 #else
15694   abort ();
15695   x = 0;
15696 #endif
15697   return x;
15698 }
15699
15700 static bfd_signed_vma
15701 get32 (void)
15702 {
15703   bfd_signed_vma x = 0;
15704
15705   FETCH_DATA (the_info, codep + 4);
15706   x = *codep++ & (bfd_signed_vma) 0xff;
15707   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15708   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15709   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15710   return x;
15711 }
15712
15713 static bfd_signed_vma
15714 get32s (void)
15715 {
15716   bfd_signed_vma x = 0;
15717
15718   FETCH_DATA (the_info, codep + 4);
15719   x = *codep++ & (bfd_signed_vma) 0xff;
15720   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15721   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15722   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15723
15724   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15725
15726   return x;
15727 }
15728
15729 static int
15730 get16 (void)
15731 {
15732   int x = 0;
15733
15734   FETCH_DATA (the_info, codep + 2);
15735   x = *codep++ & 0xff;
15736   x |= (*codep++ & 0xff) << 8;
15737   return x;
15738 }
15739
15740 static void
15741 set_op (bfd_vma op, int riprel)
15742 {
15743   op_index[op_ad] = op_ad;
15744   if (address_mode == mode_64bit)
15745     {
15746       op_address[op_ad] = op;
15747       op_riprel[op_ad] = riprel;
15748     }
15749   else
15750     {
15751       /* Mask to get a 32-bit address.  */
15752       op_address[op_ad] = op & 0xffffffff;
15753       op_riprel[op_ad] = riprel & 0xffffffff;
15754     }
15755 }
15756
15757 static void
15758 OP_REG (int code, int sizeflag)
15759 {
15760   const char *s;
15761   int add;
15762
15763   switch (code)
15764     {
15765     case es_reg: case ss_reg: case cs_reg:
15766     case ds_reg: case fs_reg: case gs_reg:
15767       oappend (names_seg[code - es_reg]);
15768       return;
15769     }
15770
15771   USED_REX (REX_B);
15772   if (rex & REX_B)
15773     add = 8;
15774   else
15775     add = 0;
15776
15777   switch (code)
15778     {
15779     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15780     case sp_reg: case bp_reg: case si_reg: case di_reg:
15781       s = names16[code - ax_reg + add];
15782       break;
15783     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15784     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15785       USED_REX (0);
15786       if (rex)
15787         s = names8rex[code - al_reg + add];
15788       else
15789         s = names8[code - al_reg];
15790       break;
15791     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15792     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15793       if (address_mode == mode_64bit
15794           && ((sizeflag & DFLAG) || (rex & REX_W)))
15795         {
15796           s = names64[code - rAX_reg + add];
15797           break;
15798         }
15799       code += eAX_reg - rAX_reg;
15800       /* Fall through.  */
15801     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15802     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15803       USED_REX (REX_W);
15804       if (rex & REX_W)
15805         s = names64[code - eAX_reg + add];
15806       else
15807         {
15808           if (sizeflag & DFLAG)
15809             s = names32[code - eAX_reg + add];
15810           else
15811             s = names16[code - eAX_reg + add];
15812           used_prefixes |= (prefixes & PREFIX_DATA);
15813         }
15814       break;
15815     default:
15816       s = INTERNAL_DISASSEMBLER_ERROR;
15817       break;
15818     }
15819   oappend (s);
15820 }
15821
15822 static void
15823 OP_IMREG (int code, int sizeflag)
15824 {
15825   const char *s;
15826
15827   switch (code)
15828     {
15829     case indir_dx_reg:
15830       if (intel_syntax)
15831         s = "dx";
15832       else
15833         s = "(%dx)";
15834       break;
15835     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15836     case sp_reg: case bp_reg: case si_reg: case di_reg:
15837       s = names16[code - ax_reg];
15838       break;
15839     case es_reg: case ss_reg: case cs_reg:
15840     case ds_reg: case fs_reg: case gs_reg:
15841       s = names_seg[code - es_reg];
15842       break;
15843     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15844     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15845       USED_REX (0);
15846       if (rex)
15847         s = names8rex[code - al_reg];
15848       else
15849         s = names8[code - al_reg];
15850       break;
15851     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15852     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15853       USED_REX (REX_W);
15854       if (rex & REX_W)
15855         s = names64[code - eAX_reg];
15856       else
15857         {
15858           if (sizeflag & DFLAG)
15859             s = names32[code - eAX_reg];
15860           else
15861             s = names16[code - eAX_reg];
15862           used_prefixes |= (prefixes & PREFIX_DATA);
15863         }
15864       break;
15865     case z_mode_ax_reg:
15866       if ((rex & REX_W) || (sizeflag & DFLAG))
15867         s = *names32;
15868       else
15869         s = *names16;
15870       if (!(rex & REX_W))
15871         used_prefixes |= (prefixes & PREFIX_DATA);
15872       break;
15873     default:
15874       s = INTERNAL_DISASSEMBLER_ERROR;
15875       break;
15876     }
15877   oappend (s);
15878 }
15879
15880 static void
15881 OP_I (int bytemode, int sizeflag)
15882 {
15883   bfd_signed_vma op;
15884   bfd_signed_vma mask = -1;
15885
15886   switch (bytemode)
15887     {
15888     case b_mode:
15889       FETCH_DATA (the_info, codep + 1);
15890       op = *codep++;
15891       mask = 0xff;
15892       break;
15893     case q_mode:
15894       if (address_mode == mode_64bit)
15895         {
15896           op = get32s ();
15897           break;
15898         }
15899       /* Fall through.  */
15900     case v_mode:
15901       USED_REX (REX_W);
15902       if (rex & REX_W)
15903         op = get32s ();
15904       else
15905         {
15906           if (sizeflag & DFLAG)
15907             {
15908               op = get32 ();
15909               mask = 0xffffffff;
15910             }
15911           else
15912             {
15913               op = get16 ();
15914               mask = 0xfffff;
15915             }
15916           used_prefixes |= (prefixes & PREFIX_DATA);
15917         }
15918       break;
15919     case w_mode:
15920       mask = 0xfffff;
15921       op = get16 ();
15922       break;
15923     case const_1_mode:
15924       if (intel_syntax)
15925         oappend ("1");
15926       return;
15927     default:
15928       oappend (INTERNAL_DISASSEMBLER_ERROR);
15929       return;
15930     }
15931
15932   op &= mask;
15933   scratchbuf[0] = '$';
15934   print_operand_value (scratchbuf + 1, 1, op);
15935   oappend_maybe_intel (scratchbuf);
15936   scratchbuf[0] = '\0';
15937 }
15938
15939 static void
15940 OP_I64 (int bytemode, int sizeflag)
15941 {
15942   bfd_signed_vma op;
15943   bfd_signed_vma mask = -1;
15944
15945   if (address_mode != mode_64bit)
15946     {
15947       OP_I (bytemode, sizeflag);
15948       return;
15949     }
15950
15951   switch (bytemode)
15952     {
15953     case b_mode:
15954       FETCH_DATA (the_info, codep + 1);
15955       op = *codep++;
15956       mask = 0xff;
15957       break;
15958     case v_mode:
15959       USED_REX (REX_W);
15960       if (rex & REX_W)
15961         op = get64 ();
15962       else
15963         {
15964           if (sizeflag & DFLAG)
15965             {
15966               op = get32 ();
15967               mask = 0xffffffff;
15968             }
15969           else
15970             {
15971               op = get16 ();
15972               mask = 0xfffff;
15973             }
15974           used_prefixes |= (prefixes & PREFIX_DATA);
15975         }
15976       break;
15977     case w_mode:
15978       mask = 0xfffff;
15979       op = get16 ();
15980       break;
15981     default:
15982       oappend (INTERNAL_DISASSEMBLER_ERROR);
15983       return;
15984     }
15985
15986   op &= mask;
15987   scratchbuf[0] = '$';
15988   print_operand_value (scratchbuf + 1, 1, op);
15989   oappend_maybe_intel (scratchbuf);
15990   scratchbuf[0] = '\0';
15991 }
15992
15993 static void
15994 OP_sI (int bytemode, int sizeflag)
15995 {
15996   bfd_signed_vma op;
15997
15998   switch (bytemode)
15999     {
16000     case b_mode:
16001     case b_T_mode:
16002       FETCH_DATA (the_info, codep + 1);
16003       op = *codep++;
16004       if ((op & 0x80) != 0)
16005         op -= 0x100;
16006       if (bytemode == b_T_mode)
16007         {
16008           if (address_mode != mode_64bit
16009               || !((sizeflag & DFLAG) || (rex & REX_W)))
16010             {
16011               /* The operand-size prefix is overridden by a REX prefix.  */
16012               if ((sizeflag & DFLAG) || (rex & REX_W))
16013                 op &= 0xffffffff;
16014               else
16015                 op &= 0xffff;
16016           }
16017         }
16018       else
16019         {
16020           if (!(rex & REX_W))
16021             {
16022               if (sizeflag & DFLAG)
16023                 op &= 0xffffffff;
16024               else
16025                 op &= 0xffff;
16026             }
16027         }
16028       break;
16029     case v_mode:
16030       /* The operand-size prefix is overridden by a REX prefix.  */
16031       if ((sizeflag & DFLAG) || (rex & REX_W))
16032         op = get32s ();
16033       else
16034         op = get16 ();
16035       break;
16036     default:
16037       oappend (INTERNAL_DISASSEMBLER_ERROR);
16038       return;
16039     }
16040
16041   scratchbuf[0] = '$';
16042   print_operand_value (scratchbuf + 1, 1, op);
16043   oappend_maybe_intel (scratchbuf);
16044 }
16045
16046 static void
16047 OP_J (int bytemode, int sizeflag)
16048 {
16049   bfd_vma disp;
16050   bfd_vma mask = -1;
16051   bfd_vma segment = 0;
16052
16053   switch (bytemode)
16054     {
16055     case b_mode:
16056       FETCH_DATA (the_info, codep + 1);
16057       disp = *codep++;
16058       if ((disp & 0x80) != 0)
16059         disp -= 0x100;
16060       break;
16061     case v_mode:
16062       if (isa64 == amd64)
16063         USED_REX (REX_W);
16064       if ((sizeflag & DFLAG)
16065           || (address_mode == mode_64bit
16066               && (isa64 != amd64 || (rex & REX_W))))
16067         disp = get32s ();
16068       else
16069         {
16070           disp = get16 ();
16071           if ((disp & 0x8000) != 0)
16072             disp -= 0x10000;
16073           /* In 16bit mode, address is wrapped around at 64k within
16074              the same segment.  Otherwise, a data16 prefix on a jump
16075              instruction means that the pc is masked to 16 bits after
16076              the displacement is added!  */
16077           mask = 0xffff;
16078           if ((prefixes & PREFIX_DATA) == 0)
16079             segment = ((start_pc + (codep - start_codep))
16080                        & ~((bfd_vma) 0xffff));
16081         }
16082       if (address_mode != mode_64bit
16083           || (isa64 == amd64 && !(rex & REX_W)))
16084         used_prefixes |= (prefixes & PREFIX_DATA);
16085       break;
16086     default:
16087       oappend (INTERNAL_DISASSEMBLER_ERROR);
16088       return;
16089     }
16090   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16091   set_op (disp, 0);
16092   print_operand_value (scratchbuf, 1, disp);
16093   oappend (scratchbuf);
16094 }
16095
16096 static void
16097 OP_SEG (int bytemode, int sizeflag)
16098 {
16099   if (bytemode == w_mode)
16100     oappend (names_seg[modrm.reg]);
16101   else
16102     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16103 }
16104
16105 static void
16106 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16107 {
16108   int seg, offset;
16109
16110   if (sizeflag & DFLAG)
16111     {
16112       offset = get32 ();
16113       seg = get16 ();
16114     }
16115   else
16116     {
16117       offset = get16 ();
16118       seg = get16 ();
16119     }
16120   used_prefixes |= (prefixes & PREFIX_DATA);
16121   if (intel_syntax)
16122     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16123   else
16124     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16125   oappend (scratchbuf);
16126 }
16127
16128 static void
16129 OP_OFF (int bytemode, int sizeflag)
16130 {
16131   bfd_vma off;
16132
16133   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16134     intel_operand_size (bytemode, sizeflag);
16135   append_seg ();
16136
16137   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16138     off = get32 ();
16139   else
16140     off = get16 ();
16141
16142   if (intel_syntax)
16143     {
16144       if (!active_seg_prefix)
16145         {
16146           oappend (names_seg[ds_reg - es_reg]);
16147           oappend (":");
16148         }
16149     }
16150   print_operand_value (scratchbuf, 1, off);
16151   oappend (scratchbuf);
16152 }
16153
16154 static void
16155 OP_OFF64 (int bytemode, int sizeflag)
16156 {
16157   bfd_vma off;
16158
16159   if (address_mode != mode_64bit
16160       || (prefixes & PREFIX_ADDR))
16161     {
16162       OP_OFF (bytemode, sizeflag);
16163       return;
16164     }
16165
16166   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16167     intel_operand_size (bytemode, sizeflag);
16168   append_seg ();
16169
16170   off = get64 ();
16171
16172   if (intel_syntax)
16173     {
16174       if (!active_seg_prefix)
16175         {
16176           oappend (names_seg[ds_reg - es_reg]);
16177           oappend (":");
16178         }
16179     }
16180   print_operand_value (scratchbuf, 1, off);
16181   oappend (scratchbuf);
16182 }
16183
16184 static void
16185 ptr_reg (int code, int sizeflag)
16186 {
16187   const char *s;
16188
16189   *obufp++ = open_char;
16190   used_prefixes |= (prefixes & PREFIX_ADDR);
16191   if (address_mode == mode_64bit)
16192     {
16193       if (!(sizeflag & AFLAG))
16194         s = names32[code - eAX_reg];
16195       else
16196         s = names64[code - eAX_reg];
16197     }
16198   else if (sizeflag & AFLAG)
16199     s = names32[code - eAX_reg];
16200   else
16201     s = names16[code - eAX_reg];
16202   oappend (s);
16203   *obufp++ = close_char;
16204   *obufp = 0;
16205 }
16206
16207 static void
16208 OP_ESreg (int code, int sizeflag)
16209 {
16210   if (intel_syntax)
16211     {
16212       switch (codep[-1])
16213         {
16214         case 0x6d:      /* insw/insl */
16215           intel_operand_size (z_mode, sizeflag);
16216           break;
16217         case 0xa5:      /* movsw/movsl/movsq */
16218         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16219         case 0xab:      /* stosw/stosl */
16220         case 0xaf:      /* scasw/scasl */
16221           intel_operand_size (v_mode, sizeflag);
16222           break;
16223         default:
16224           intel_operand_size (b_mode, sizeflag);
16225         }
16226     }
16227   oappend_maybe_intel ("%es:");
16228   ptr_reg (code, sizeflag);
16229 }
16230
16231 static void
16232 OP_DSreg (int code, int sizeflag)
16233 {
16234   if (intel_syntax)
16235     {
16236       switch (codep[-1])
16237         {
16238         case 0x6f:      /* outsw/outsl */
16239           intel_operand_size (z_mode, sizeflag);
16240           break;
16241         case 0xa5:      /* movsw/movsl/movsq */
16242         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16243         case 0xad:      /* lodsw/lodsl/lodsq */
16244           intel_operand_size (v_mode, sizeflag);
16245           break;
16246         default:
16247           intel_operand_size (b_mode, sizeflag);
16248         }
16249     }
16250   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16251      default segment register DS is printed.  */
16252   if (!active_seg_prefix)
16253     active_seg_prefix = PREFIX_DS;
16254   append_seg ();
16255   ptr_reg (code, sizeflag);
16256 }
16257
16258 static void
16259 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16260 {
16261   int add;
16262   if (rex & REX_R)
16263     {
16264       USED_REX (REX_R);
16265       add = 8;
16266     }
16267   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16268     {
16269       all_prefixes[last_lock_prefix] = 0;
16270       used_prefixes |= PREFIX_LOCK;
16271       add = 8;
16272     }
16273   else
16274     add = 0;
16275   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16276   oappend_maybe_intel (scratchbuf);
16277 }
16278
16279 static void
16280 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16281 {
16282   int add;
16283   USED_REX (REX_R);
16284   if (rex & REX_R)
16285     add = 8;
16286   else
16287     add = 0;
16288   if (intel_syntax)
16289     sprintf (scratchbuf, "db%d", modrm.reg + add);
16290   else
16291     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16292   oappend (scratchbuf);
16293 }
16294
16295 static void
16296 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16297 {
16298   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16299   oappend_maybe_intel (scratchbuf);
16300 }
16301
16302 static void
16303 OP_R (int bytemode, int sizeflag)
16304 {
16305   /* Skip mod/rm byte.  */
16306   MODRM_CHECK;
16307   codep++;
16308   OP_E_register (bytemode, sizeflag);
16309 }
16310
16311 static void
16312 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16313 {
16314   int reg = modrm.reg;
16315   const char **names;
16316
16317   used_prefixes |= (prefixes & PREFIX_DATA);
16318   if (prefixes & PREFIX_DATA)
16319     {
16320       names = names_xmm;
16321       USED_REX (REX_R);
16322       if (rex & REX_R)
16323         reg += 8;
16324     }
16325   else
16326     names = names_mm;
16327   oappend (names[reg]);
16328 }
16329
16330 static void
16331 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16332 {
16333   int reg = modrm.reg;
16334   const char **names;
16335
16336   USED_REX (REX_R);
16337   if (rex & REX_R)
16338     reg += 8;
16339   if (vex.evex)
16340     {
16341       if (!vex.r)
16342         reg += 16;
16343     }
16344
16345   if (need_vex
16346       && bytemode != xmm_mode
16347       && bytemode != xmmq_mode
16348       && bytemode != evex_half_bcst_xmmq_mode
16349       && bytemode != ymm_mode
16350       && bytemode != scalar_mode)
16351     {
16352       switch (vex.length)
16353         {
16354         case 128:
16355           names = names_xmm;
16356           break;
16357         case 256:
16358           if (vex.w
16359               || (bytemode != vex_vsib_q_w_dq_mode
16360                   && bytemode != vex_vsib_q_w_d_mode))
16361             names = names_ymm;
16362           else
16363             names = names_xmm;
16364           break;
16365         case 512:
16366           names = names_zmm;
16367           break;
16368         default:
16369           abort ();
16370         }
16371     }
16372   else if (bytemode == xmmq_mode
16373            || bytemode == evex_half_bcst_xmmq_mode)
16374     {
16375       switch (vex.length)
16376         {
16377         case 128:
16378         case 256:
16379           names = names_xmm;
16380           break;
16381         case 512:
16382           names = names_ymm;
16383           break;
16384         default:
16385           abort ();
16386         }
16387     }
16388   else if (bytemode == ymm_mode)
16389     names = names_ymm;
16390   else
16391     names = names_xmm;
16392   oappend (names[reg]);
16393 }
16394
16395 static void
16396 OP_EM (int bytemode, int sizeflag)
16397 {
16398   int reg;
16399   const char **names;
16400
16401   if (modrm.mod != 3)
16402     {
16403       if (intel_syntax
16404           && (bytemode == v_mode || bytemode == v_swap_mode))
16405         {
16406           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16407           used_prefixes |= (prefixes & PREFIX_DATA);
16408         }
16409       OP_E (bytemode, sizeflag);
16410       return;
16411     }
16412
16413   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16414     swap_operand ();
16415
16416   /* Skip mod/rm byte.  */
16417   MODRM_CHECK;
16418   codep++;
16419   used_prefixes |= (prefixes & PREFIX_DATA);
16420   reg = modrm.rm;
16421   if (prefixes & PREFIX_DATA)
16422     {
16423       names = names_xmm;
16424       USED_REX (REX_B);
16425       if (rex & REX_B)
16426         reg += 8;
16427     }
16428   else
16429     names = names_mm;
16430   oappend (names[reg]);
16431 }
16432
16433 /* cvt* are the only instructions in sse2 which have
16434    both SSE and MMX operands and also have 0x66 prefix
16435    in their opcode. 0x66 was originally used to differentiate
16436    between SSE and MMX instruction(operands). So we have to handle the
16437    cvt* separately using OP_EMC and OP_MXC */
16438 static void
16439 OP_EMC (int bytemode, int sizeflag)
16440 {
16441   if (modrm.mod != 3)
16442     {
16443       if (intel_syntax && bytemode == v_mode)
16444         {
16445           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16446           used_prefixes |= (prefixes & PREFIX_DATA);
16447         }
16448       OP_E (bytemode, sizeflag);
16449       return;
16450     }
16451
16452   /* Skip mod/rm byte.  */
16453   MODRM_CHECK;
16454   codep++;
16455   used_prefixes |= (prefixes & PREFIX_DATA);
16456   oappend (names_mm[modrm.rm]);
16457 }
16458
16459 static void
16460 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16461 {
16462   used_prefixes |= (prefixes & PREFIX_DATA);
16463   oappend (names_mm[modrm.reg]);
16464 }
16465
16466 static void
16467 OP_EX (int bytemode, int sizeflag)
16468 {
16469   int reg;
16470   const char **names;
16471
16472   /* Skip mod/rm byte.  */
16473   MODRM_CHECK;
16474   codep++;
16475
16476   if (modrm.mod != 3)
16477     {
16478       OP_E_memory (bytemode, sizeflag);
16479       return;
16480     }
16481
16482   reg = modrm.rm;
16483   USED_REX (REX_B);
16484   if (rex & REX_B)
16485     reg += 8;
16486   if (vex.evex)
16487     {
16488       USED_REX (REX_X);
16489       if ((rex & REX_X))
16490         reg += 16;
16491     }
16492
16493   if ((sizeflag & SUFFIX_ALWAYS)
16494       && (bytemode == x_swap_mode
16495           || bytemode == d_swap_mode
16496           || bytemode == d_scalar_swap_mode
16497           || bytemode == q_swap_mode
16498           || bytemode == q_scalar_swap_mode))
16499     swap_operand ();
16500
16501   if (need_vex
16502       && bytemode != xmm_mode
16503       && bytemode != xmmdw_mode
16504       && bytemode != xmmqd_mode
16505       && bytemode != xmm_mb_mode
16506       && bytemode != xmm_mw_mode
16507       && bytemode != xmm_md_mode
16508       && bytemode != xmm_mq_mode
16509       && bytemode != xmm_mdq_mode
16510       && bytemode != xmmq_mode
16511       && bytemode != evex_half_bcst_xmmq_mode
16512       && bytemode != ymm_mode
16513       && bytemode != d_scalar_mode
16514       && bytemode != d_scalar_swap_mode
16515       && bytemode != q_scalar_mode
16516       && bytemode != q_scalar_swap_mode
16517       && bytemode != vex_scalar_w_dq_mode)
16518     {
16519       switch (vex.length)
16520         {
16521         case 128:
16522           names = names_xmm;
16523           break;
16524         case 256:
16525           names = names_ymm;
16526           break;
16527         case 512:
16528           names = names_zmm;
16529           break;
16530         default:
16531           abort ();
16532         }
16533     }
16534   else if (bytemode == xmmq_mode
16535            || bytemode == evex_half_bcst_xmmq_mode)
16536     {
16537       switch (vex.length)
16538         {
16539         case 128:
16540         case 256:
16541           names = names_xmm;
16542           break;
16543         case 512:
16544           names = names_ymm;
16545           break;
16546         default:
16547           abort ();
16548         }
16549     }
16550   else if (bytemode == ymm_mode)
16551     names = names_ymm;
16552   else
16553     names = names_xmm;
16554   oappend (names[reg]);
16555 }
16556
16557 static void
16558 OP_MS (int bytemode, int sizeflag)
16559 {
16560   if (modrm.mod == 3)
16561     OP_EM (bytemode, sizeflag);
16562   else
16563     BadOp ();
16564 }
16565
16566 static void
16567 OP_XS (int bytemode, int sizeflag)
16568 {
16569   if (modrm.mod == 3)
16570     OP_EX (bytemode, sizeflag);
16571   else
16572     BadOp ();
16573 }
16574
16575 static void
16576 OP_M (int bytemode, int sizeflag)
16577 {
16578   if (modrm.mod == 3)
16579     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16580     BadOp ();
16581   else
16582     OP_E (bytemode, sizeflag);
16583 }
16584
16585 static void
16586 OP_0f07 (int bytemode, int sizeflag)
16587 {
16588   if (modrm.mod != 3 || modrm.rm != 0)
16589     BadOp ();
16590   else
16591     OP_E (bytemode, sizeflag);
16592 }
16593
16594 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16595    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16596
16597 static void
16598 NOP_Fixup1 (int bytemode, int sizeflag)
16599 {
16600   if ((prefixes & PREFIX_DATA) != 0
16601       || (rex != 0
16602           && rex != 0x48
16603           && address_mode == mode_64bit))
16604     OP_REG (bytemode, sizeflag);
16605   else
16606     strcpy (obuf, "nop");
16607 }
16608
16609 static void
16610 NOP_Fixup2 (int bytemode, int sizeflag)
16611 {
16612   if ((prefixes & PREFIX_DATA) != 0
16613       || (rex != 0
16614           && rex != 0x48
16615           && address_mode == mode_64bit))
16616     OP_IMREG (bytemode, sizeflag);
16617 }
16618
16619 static const char *const Suffix3DNow[] = {
16620 /* 00 */        NULL,           NULL,           NULL,           NULL,
16621 /* 04 */        NULL,           NULL,           NULL,           NULL,
16622 /* 08 */        NULL,           NULL,           NULL,           NULL,
16623 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16624 /* 10 */        NULL,           NULL,           NULL,           NULL,
16625 /* 14 */        NULL,           NULL,           NULL,           NULL,
16626 /* 18 */        NULL,           NULL,           NULL,           NULL,
16627 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16628 /* 20 */        NULL,           NULL,           NULL,           NULL,
16629 /* 24 */        NULL,           NULL,           NULL,           NULL,
16630 /* 28 */        NULL,           NULL,           NULL,           NULL,
16631 /* 2C */        NULL,           NULL,           NULL,           NULL,
16632 /* 30 */        NULL,           NULL,           NULL,           NULL,
16633 /* 34 */        NULL,           NULL,           NULL,           NULL,
16634 /* 38 */        NULL,           NULL,           NULL,           NULL,
16635 /* 3C */        NULL,           NULL,           NULL,           NULL,
16636 /* 40 */        NULL,           NULL,           NULL,           NULL,
16637 /* 44 */        NULL,           NULL,           NULL,           NULL,
16638 /* 48 */        NULL,           NULL,           NULL,           NULL,
16639 /* 4C */        NULL,           NULL,           NULL,           NULL,
16640 /* 50 */        NULL,           NULL,           NULL,           NULL,
16641 /* 54 */        NULL,           NULL,           NULL,           NULL,
16642 /* 58 */        NULL,           NULL,           NULL,           NULL,
16643 /* 5C */        NULL,           NULL,           NULL,           NULL,
16644 /* 60 */        NULL,           NULL,           NULL,           NULL,
16645 /* 64 */        NULL,           NULL,           NULL,           NULL,
16646 /* 68 */        NULL,           NULL,           NULL,           NULL,
16647 /* 6C */        NULL,           NULL,           NULL,           NULL,
16648 /* 70 */        NULL,           NULL,           NULL,           NULL,
16649 /* 74 */        NULL,           NULL,           NULL,           NULL,
16650 /* 78 */        NULL,           NULL,           NULL,           NULL,
16651 /* 7C */        NULL,           NULL,           NULL,           NULL,
16652 /* 80 */        NULL,           NULL,           NULL,           NULL,
16653 /* 84 */        NULL,           NULL,           NULL,           NULL,
16654 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16655 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16656 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16657 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16658 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16659 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16660 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16661 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16662 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16663 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16664 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16665 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16666 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16667 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16668 /* C0 */        NULL,           NULL,           NULL,           NULL,
16669 /* C4 */        NULL,           NULL,           NULL,           NULL,
16670 /* C8 */        NULL,           NULL,           NULL,           NULL,
16671 /* CC */        NULL,           NULL,           NULL,           NULL,
16672 /* D0 */        NULL,           NULL,           NULL,           NULL,
16673 /* D4 */        NULL,           NULL,           NULL,           NULL,
16674 /* D8 */        NULL,           NULL,           NULL,           NULL,
16675 /* DC */        NULL,           NULL,           NULL,           NULL,
16676 /* E0 */        NULL,           NULL,           NULL,           NULL,
16677 /* E4 */        NULL,           NULL,           NULL,           NULL,
16678 /* E8 */        NULL,           NULL,           NULL,           NULL,
16679 /* EC */        NULL,           NULL,           NULL,           NULL,
16680 /* F0 */        NULL,           NULL,           NULL,           NULL,
16681 /* F4 */        NULL,           NULL,           NULL,           NULL,
16682 /* F8 */        NULL,           NULL,           NULL,           NULL,
16683 /* FC */        NULL,           NULL,           NULL,           NULL,
16684 };
16685
16686 static void
16687 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16688 {
16689   const char *mnemonic;
16690
16691   FETCH_DATA (the_info, codep + 1);
16692   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16693      place where an 8-bit immediate would normally go.  ie. the last
16694      byte of the instruction.  */
16695   obufp = mnemonicendp;
16696   mnemonic = Suffix3DNow[*codep++ & 0xff];
16697   if (mnemonic)
16698     oappend (mnemonic);
16699   else
16700     {
16701       /* Since a variable sized modrm/sib chunk is between the start
16702          of the opcode (0x0f0f) and the opcode suffix, we need to do
16703          all the modrm processing first, and don't know until now that
16704          we have a bad opcode.  This necessitates some cleaning up.  */
16705       op_out[0][0] = '\0';
16706       op_out[1][0] = '\0';
16707       BadOp ();
16708     }
16709   mnemonicendp = obufp;
16710 }
16711
16712 static struct op simd_cmp_op[] =
16713 {
16714   { STRING_COMMA_LEN ("eq") },
16715   { STRING_COMMA_LEN ("lt") },
16716   { STRING_COMMA_LEN ("le") },
16717   { STRING_COMMA_LEN ("unord") },
16718   { STRING_COMMA_LEN ("neq") },
16719   { STRING_COMMA_LEN ("nlt") },
16720   { STRING_COMMA_LEN ("nle") },
16721   { STRING_COMMA_LEN ("ord") }
16722 };
16723
16724 static void
16725 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16726 {
16727   unsigned int cmp_type;
16728
16729   FETCH_DATA (the_info, codep + 1);
16730   cmp_type = *codep++ & 0xff;
16731   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16732     {
16733       char suffix [3];
16734       char *p = mnemonicendp - 2;
16735       suffix[0] = p[0];
16736       suffix[1] = p[1];
16737       suffix[2] = '\0';
16738       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16739       mnemonicendp += simd_cmp_op[cmp_type].len;
16740     }
16741   else
16742     {
16743       /* We have a reserved extension byte.  Output it directly.  */
16744       scratchbuf[0] = '$';
16745       print_operand_value (scratchbuf + 1, 1, cmp_type);
16746       oappend_maybe_intel (scratchbuf);
16747       scratchbuf[0] = '\0';
16748     }
16749 }
16750
16751 static void
16752 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16753           int sizeflag ATTRIBUTE_UNUSED)
16754 {
16755   /* mwaitx %eax,%ecx,%ebx */
16756   if (!intel_syntax)
16757     {
16758       const char **names = (address_mode == mode_64bit
16759                             ? names64 : names32);
16760       strcpy (op_out[0], names[0]);
16761       strcpy (op_out[1], names[1]);
16762       strcpy (op_out[2], names[3]);
16763       two_source_ops = 1;
16764     }
16765   /* Skip mod/rm byte.  */
16766   MODRM_CHECK;
16767   codep++;
16768 }
16769
16770 static void
16771 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16772           int sizeflag ATTRIBUTE_UNUSED)
16773 {
16774   /* mwait %eax,%ecx  */
16775   if (!intel_syntax)
16776     {
16777       const char **names = (address_mode == mode_64bit
16778                             ? names64 : names32);
16779       strcpy (op_out[0], names[0]);
16780       strcpy (op_out[1], names[1]);
16781       two_source_ops = 1;
16782     }
16783   /* Skip mod/rm byte.  */
16784   MODRM_CHECK;
16785   codep++;
16786 }
16787
16788 static void
16789 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16790             int sizeflag ATTRIBUTE_UNUSED)
16791 {
16792   /* monitor %eax,%ecx,%edx"  */
16793   if (!intel_syntax)
16794     {
16795       const char **op1_names;
16796       const char **names = (address_mode == mode_64bit
16797                             ? names64 : names32);
16798
16799       if (!(prefixes & PREFIX_ADDR))
16800         op1_names = (address_mode == mode_16bit
16801                      ? names16 : names);
16802       else
16803         {
16804           /* Remove "addr16/addr32".  */
16805           all_prefixes[last_addr_prefix] = 0;
16806           op1_names = (address_mode != mode_32bit
16807                        ? names32 : names16);
16808           used_prefixes |= PREFIX_ADDR;
16809         }
16810       strcpy (op_out[0], op1_names[0]);
16811       strcpy (op_out[1], names[1]);
16812       strcpy (op_out[2], names[2]);
16813       two_source_ops = 1;
16814     }
16815   /* Skip mod/rm byte.  */
16816   MODRM_CHECK;
16817   codep++;
16818 }
16819
16820 static void
16821 BadOp (void)
16822 {
16823   /* Throw away prefixes and 1st. opcode byte.  */
16824   codep = insn_codep + 1;
16825   oappend ("(bad)");
16826 }
16827
16828 static void
16829 REP_Fixup (int bytemode, int sizeflag)
16830 {
16831   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16832      lods and stos.  */
16833   if (prefixes & PREFIX_REPZ)
16834     all_prefixes[last_repz_prefix] = REP_PREFIX;
16835
16836   switch (bytemode)
16837     {
16838     case al_reg:
16839     case eAX_reg:
16840     case indir_dx_reg:
16841       OP_IMREG (bytemode, sizeflag);
16842       break;
16843     case eDI_reg:
16844       OP_ESreg (bytemode, sizeflag);
16845       break;
16846     case eSI_reg:
16847       OP_DSreg (bytemode, sizeflag);
16848       break;
16849     default:
16850       abort ();
16851       break;
16852     }
16853 }
16854
16855 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16856    "bnd".  */
16857
16858 static void
16859 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16860 {
16861   if (prefixes & PREFIX_REPNZ)
16862     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16863 }
16864
16865 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16866    "notrack".  */
16867
16868 static void
16869 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16870                int sizeflag ATTRIBUTE_UNUSED)
16871 {
16872   if (active_seg_prefix == PREFIX_DS
16873       && (address_mode != mode_64bit || last_data_prefix < 0))
16874     {
16875       /* NOTRACK prefix is only valid on indirect branch instructions.
16876          NB: DATA prefix is unsupported for Intel64.  */
16877       active_seg_prefix = 0;
16878       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16879     }
16880 }
16881
16882 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16883    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16884  */
16885
16886 static void
16887 HLE_Fixup1 (int bytemode, int sizeflag)
16888 {
16889   if (modrm.mod != 3
16890       && (prefixes & PREFIX_LOCK) != 0)
16891     {
16892       if (prefixes & PREFIX_REPZ)
16893         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16894       if (prefixes & PREFIX_REPNZ)
16895         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16896     }
16897
16898   OP_E (bytemode, sizeflag);
16899 }
16900
16901 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16902    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16903  */
16904
16905 static void
16906 HLE_Fixup2 (int bytemode, int sizeflag)
16907 {
16908   if (modrm.mod != 3)
16909     {
16910       if (prefixes & PREFIX_REPZ)
16911         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16912       if (prefixes & PREFIX_REPNZ)
16913         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16914     }
16915
16916   OP_E (bytemode, sizeflag);
16917 }
16918
16919 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16920    "xrelease" for memory operand.  No check for LOCK prefix.   */
16921
16922 static void
16923 HLE_Fixup3 (int bytemode, int sizeflag)
16924 {
16925   if (modrm.mod != 3
16926       && last_repz_prefix > last_repnz_prefix
16927       && (prefixes & PREFIX_REPZ) != 0)
16928     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16929
16930   OP_E (bytemode, sizeflag);
16931 }
16932
16933 static void
16934 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16935 {
16936   USED_REX (REX_W);
16937   if (rex & REX_W)
16938     {
16939       /* Change cmpxchg8b to cmpxchg16b.  */
16940       char *p = mnemonicendp - 2;
16941       mnemonicendp = stpcpy (p, "16b");
16942       bytemode = o_mode;
16943     }
16944   else if ((prefixes & PREFIX_LOCK) != 0)
16945     {
16946       if (prefixes & PREFIX_REPZ)
16947         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16948       if (prefixes & PREFIX_REPNZ)
16949         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16950     }
16951
16952   OP_M (bytemode, sizeflag);
16953 }
16954
16955 static void
16956 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16957 {
16958   const char **names;
16959
16960   if (need_vex)
16961     {
16962       switch (vex.length)
16963         {
16964         case 128:
16965           names = names_xmm;
16966           break;
16967         case 256:
16968           names = names_ymm;
16969           break;
16970         default:
16971           abort ();
16972         }
16973     }
16974   else
16975     names = names_xmm;
16976   oappend (names[reg]);
16977 }
16978
16979 static void
16980 CRC32_Fixup (int bytemode, int sizeflag)
16981 {
16982   /* Add proper suffix to "crc32".  */
16983   char *p = mnemonicendp;
16984
16985   switch (bytemode)
16986     {
16987     case b_mode:
16988       if (intel_syntax)
16989         goto skip;
16990
16991       *p++ = 'b';
16992       break;
16993     case v_mode:
16994       if (intel_syntax)
16995         goto skip;
16996
16997       USED_REX (REX_W);
16998       if (rex & REX_W)
16999         *p++ = 'q';
17000       else
17001         {
17002           if (sizeflag & DFLAG)
17003             *p++ = 'l';
17004           else
17005             *p++ = 'w';
17006           used_prefixes |= (prefixes & PREFIX_DATA);
17007         }
17008       break;
17009     default:
17010       oappend (INTERNAL_DISASSEMBLER_ERROR);
17011       break;
17012     }
17013   mnemonicendp = p;
17014   *p = '\0';
17015
17016 skip:
17017   if (modrm.mod == 3)
17018     {
17019       int add;
17020
17021       /* Skip mod/rm byte.  */
17022       MODRM_CHECK;
17023       codep++;
17024
17025       USED_REX (REX_B);
17026       add = (rex & REX_B) ? 8 : 0;
17027       if (bytemode == b_mode)
17028         {
17029           USED_REX (0);
17030           if (rex)
17031             oappend (names8rex[modrm.rm + add]);
17032           else
17033             oappend (names8[modrm.rm + add]);
17034         }
17035       else
17036         {
17037           USED_REX (REX_W);
17038           if (rex & REX_W)
17039             oappend (names64[modrm.rm + add]);
17040           else if ((prefixes & PREFIX_DATA))
17041             oappend (names16[modrm.rm + add]);
17042           else
17043             oappend (names32[modrm.rm + add]);
17044         }
17045     }
17046   else
17047     OP_E (bytemode, sizeflag);
17048 }
17049
17050 static void
17051 FXSAVE_Fixup (int bytemode, int sizeflag)
17052 {
17053   /* Add proper suffix to "fxsave" and "fxrstor".  */
17054   USED_REX (REX_W);
17055   if (rex & REX_W)
17056     {
17057       char *p = mnemonicendp;
17058       *p++ = '6';
17059       *p++ = '4';
17060       *p = '\0';
17061       mnemonicendp = p;
17062     }
17063   OP_M (bytemode, sizeflag);
17064 }
17065
17066 static void
17067 PCMPESTR_Fixup (int bytemode, int sizeflag)
17068 {
17069   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17070   if (!intel_syntax)
17071     {
17072       char *p = mnemonicendp;
17073
17074       USED_REX (REX_W);
17075       if (rex & REX_W)
17076         *p++ = 'q';
17077       else if (sizeflag & SUFFIX_ALWAYS)
17078         *p++ = 'l';
17079
17080       *p = '\0';
17081       mnemonicendp = p;
17082     }
17083
17084   OP_EX (bytemode, sizeflag);
17085 }
17086
17087 /* Display the destination register operand for instructions with
17088    VEX. */
17089
17090 static void
17091 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17092 {
17093   int reg;
17094   const char **names;
17095
17096   if (!need_vex)
17097     abort ();
17098
17099   if (!need_vex_reg)
17100     return;
17101
17102   reg = vex.register_specifier;
17103   if (vex.evex)
17104     {
17105       if (!vex.v)
17106         reg += 16;
17107     }
17108
17109   if (bytemode == vex_scalar_mode)
17110     {
17111       oappend (names_xmm[reg]);
17112       return;
17113     }
17114
17115   switch (vex.length)
17116     {
17117     case 128:
17118       switch (bytemode)
17119         {
17120         case vex_mode:
17121         case vex128_mode:
17122         case vex_vsib_q_w_dq_mode:
17123         case vex_vsib_q_w_d_mode:
17124           names = names_xmm;
17125           break;
17126         case dq_mode:
17127           if (vex.w)
17128             names = names64;
17129           else
17130             names = names32;
17131           break;
17132         case mask_bd_mode:
17133         case mask_mode:
17134           if (reg > 0x7)
17135             {
17136               oappend ("(bad)");
17137               return;
17138             }
17139           names = names_mask;
17140           break;
17141         default:
17142           abort ();
17143           return;
17144         }
17145       break;
17146     case 256:
17147       switch (bytemode)
17148         {
17149         case vex_mode:
17150         case vex256_mode:
17151           names = names_ymm;
17152           break;
17153         case vex_vsib_q_w_dq_mode:
17154         case vex_vsib_q_w_d_mode:
17155           names = vex.w ? names_ymm : names_xmm;
17156           break;
17157         case mask_bd_mode:
17158         case mask_mode:
17159           if (reg > 0x7)
17160             {
17161               oappend ("(bad)");
17162               return;
17163             }
17164           names = names_mask;
17165           break;
17166         default:
17167           /* See PR binutils/20893 for a reproducer.  */
17168           oappend ("(bad)");
17169           return;
17170         }
17171       break;
17172     case 512:
17173       names = names_zmm;
17174       break;
17175     default:
17176       abort ();
17177       break;
17178     }
17179   oappend (names[reg]);
17180 }
17181
17182 /* Get the VEX immediate byte without moving codep.  */
17183
17184 static unsigned char
17185 get_vex_imm8 (int sizeflag, int opnum)
17186 {
17187   int bytes_before_imm = 0;
17188
17189   if (modrm.mod != 3)
17190     {
17191       /* There are SIB/displacement bytes.  */
17192       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17193         {
17194           /* 32/64 bit address mode */
17195           int base = modrm.rm;
17196
17197           /* Check SIB byte.  */
17198           if (base == 4)
17199             {
17200               FETCH_DATA (the_info, codep + 1);
17201               base = *codep & 7;
17202               /* When decoding the third source, don't increase
17203                  bytes_before_imm as this has already been incremented
17204                  by one in OP_E_memory while decoding the second
17205                  source operand.  */
17206               if (opnum == 0)
17207                 bytes_before_imm++;
17208             }
17209
17210           /* Don't increase bytes_before_imm when decoding the third source,
17211              it has already been incremented by OP_E_memory while decoding
17212              the second source operand.  */
17213           if (opnum == 0)
17214             {
17215               switch (modrm.mod)
17216                 {
17217                   case 0:
17218                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17219                        SIB == 5, there is a 4 byte displacement.  */
17220                     if (base != 5)
17221                       /* No displacement. */
17222                       break;
17223                     /* Fall through.  */
17224                   case 2:
17225                     /* 4 byte displacement.  */
17226                     bytes_before_imm += 4;
17227                     break;
17228                   case 1:
17229                     /* 1 byte displacement.  */
17230                     bytes_before_imm++;
17231                     break;
17232                 }
17233             }
17234         }
17235       else
17236         {
17237           /* 16 bit address mode */
17238           /* Don't increase bytes_before_imm when decoding the third source,
17239              it has already been incremented by OP_E_memory while decoding
17240              the second source operand.  */
17241           if (opnum == 0)
17242             {
17243               switch (modrm.mod)
17244                 {
17245                 case 0:
17246                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17247                   if (modrm.rm != 6)
17248                     /* No displacement. */
17249                     break;
17250                   /* Fall through.  */
17251                 case 2:
17252                   /* 2 byte displacement.  */
17253                   bytes_before_imm += 2;
17254                   break;
17255                 case 1:
17256                   /* 1 byte displacement: when decoding the third source,
17257                      don't increase bytes_before_imm as this has already
17258                      been incremented by one in OP_E_memory while decoding
17259                      the second source operand.  */
17260                   if (opnum == 0)
17261                     bytes_before_imm++;
17262
17263                   break;
17264                 }
17265             }
17266         }
17267     }
17268
17269   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17270   return codep [bytes_before_imm];
17271 }
17272
17273 static void
17274 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17275 {
17276   const char **names;
17277
17278   if (reg == -1 && modrm.mod != 3)
17279     {
17280       OP_E_memory (bytemode, sizeflag);
17281       return;
17282     }
17283   else
17284     {
17285       if (reg == -1)
17286         {
17287           reg = modrm.rm;
17288           USED_REX (REX_B);
17289           if (rex & REX_B)
17290             reg += 8;
17291         }
17292       else if (reg > 7 && address_mode != mode_64bit)
17293         BadOp ();
17294     }
17295
17296   switch (vex.length)
17297     {
17298     case 128:
17299       names = names_xmm;
17300       break;
17301     case 256:
17302       names = names_ymm;
17303       break;
17304     default:
17305       abort ();
17306     }
17307   oappend (names[reg]);
17308 }
17309
17310 static void
17311 OP_EX_VexImmW (int bytemode, int sizeflag)
17312 {
17313   int reg = -1;
17314   static unsigned char vex_imm8;
17315
17316   if (vex_w_done == 0)
17317     {
17318       vex_w_done = 1;
17319
17320       /* Skip mod/rm byte.  */
17321       MODRM_CHECK;
17322       codep++;
17323
17324       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17325
17326       if (vex.w)
17327           reg = vex_imm8 >> 4;
17328
17329       OP_EX_VexReg (bytemode, sizeflag, reg);
17330     }
17331   else if (vex_w_done == 1)
17332     {
17333       vex_w_done = 2;
17334
17335       if (!vex.w)
17336           reg = vex_imm8 >> 4;
17337
17338       OP_EX_VexReg (bytemode, sizeflag, reg);
17339     }
17340   else
17341     {
17342       /* Output the imm8 directly.  */
17343       scratchbuf[0] = '$';
17344       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17345       oappend_maybe_intel (scratchbuf);
17346       scratchbuf[0] = '\0';
17347       codep++;
17348     }
17349 }
17350
17351 static void
17352 OP_Vex_2src (int bytemode, int sizeflag)
17353 {
17354   if (modrm.mod == 3)
17355     {
17356       int reg = modrm.rm;
17357       USED_REX (REX_B);
17358       if (rex & REX_B)
17359         reg += 8;
17360       oappend (names_xmm[reg]);
17361     }
17362   else
17363     {
17364       if (intel_syntax
17365           && (bytemode == v_mode || bytemode == v_swap_mode))
17366         {
17367           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17368           used_prefixes |= (prefixes & PREFIX_DATA);
17369         }
17370       OP_E (bytemode, sizeflag);
17371     }
17372 }
17373
17374 static void
17375 OP_Vex_2src_1 (int bytemode, int sizeflag)
17376 {
17377   if (modrm.mod == 3)
17378     {
17379       /* Skip mod/rm byte.   */
17380       MODRM_CHECK;
17381       codep++;
17382     }
17383
17384   if (vex.w)
17385     oappend (names_xmm[vex.register_specifier]);
17386   else
17387     OP_Vex_2src (bytemode, sizeflag);
17388 }
17389
17390 static void
17391 OP_Vex_2src_2 (int bytemode, int sizeflag)
17392 {
17393   if (vex.w)
17394     OP_Vex_2src (bytemode, sizeflag);
17395   else
17396     oappend (names_xmm[vex.register_specifier]);
17397 }
17398
17399 static void
17400 OP_EX_VexW (int bytemode, int sizeflag)
17401 {
17402   int reg = -1;
17403
17404   if (!vex_w_done)
17405     {
17406       vex_w_done = 1;
17407
17408       /* Skip mod/rm byte.  */
17409       MODRM_CHECK;
17410       codep++;
17411
17412       if (vex.w)
17413         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17414     }
17415   else
17416     {
17417       if (!vex.w)
17418         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17419     }
17420
17421   OP_EX_VexReg (bytemode, sizeflag, reg);
17422 }
17423
17424 static void
17425 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17426              int sizeflag ATTRIBUTE_UNUSED)
17427 {
17428   /* Skip the immediate byte and check for invalid bits.  */
17429   FETCH_DATA (the_info, codep + 1);
17430   if (*codep++ & 0xf)
17431     BadOp ();
17432 }
17433
17434 static void
17435 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17436 {
17437   int reg;
17438   const char **names;
17439
17440   FETCH_DATA (the_info, codep + 1);
17441   reg = *codep++;
17442
17443   if (bytemode != x_mode)
17444     abort ();
17445
17446   if (reg & 0xf)
17447       BadOp ();
17448
17449   reg >>= 4;
17450   if (reg > 7 && address_mode != mode_64bit)
17451     BadOp ();
17452
17453   switch (vex.length)
17454     {
17455     case 128:
17456       names = names_xmm;
17457       break;
17458     case 256:
17459       names = names_ymm;
17460       break;
17461     default:
17462       abort ();
17463     }
17464   oappend (names[reg]);
17465 }
17466
17467 static void
17468 OP_XMM_VexW (int bytemode, int sizeflag)
17469 {
17470   /* Turn off the REX.W bit since it is used for swapping operands
17471      now.  */
17472   rex &= ~REX_W;
17473   OP_XMM (bytemode, sizeflag);
17474 }
17475
17476 static void
17477 OP_EX_Vex (int bytemode, int sizeflag)
17478 {
17479   if (modrm.mod != 3)
17480     {
17481       if (vex.register_specifier != 0)
17482         BadOp ();
17483       need_vex_reg = 0;
17484     }
17485   OP_EX (bytemode, sizeflag);
17486 }
17487
17488 static void
17489 OP_XMM_Vex (int bytemode, int sizeflag)
17490 {
17491   if (modrm.mod != 3)
17492     {
17493       if (vex.register_specifier != 0)
17494         BadOp ();
17495       need_vex_reg = 0;
17496     }
17497   OP_XMM (bytemode, sizeflag);
17498 }
17499
17500 static void
17501 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17502 {
17503   switch (vex.length)
17504     {
17505     case 128:
17506       mnemonicendp = stpcpy (obuf, "vzeroupper");
17507       break;
17508     case 256:
17509       mnemonicendp = stpcpy (obuf, "vzeroall");
17510       break;
17511     default:
17512       abort ();
17513     }
17514 }
17515
17516 static struct op vex_cmp_op[] =
17517 {
17518   { STRING_COMMA_LEN ("eq") },
17519   { STRING_COMMA_LEN ("lt") },
17520   { STRING_COMMA_LEN ("le") },
17521   { STRING_COMMA_LEN ("unord") },
17522   { STRING_COMMA_LEN ("neq") },
17523   { STRING_COMMA_LEN ("nlt") },
17524   { STRING_COMMA_LEN ("nle") },
17525   { STRING_COMMA_LEN ("ord") },
17526   { STRING_COMMA_LEN ("eq_uq") },
17527   { STRING_COMMA_LEN ("nge") },
17528   { STRING_COMMA_LEN ("ngt") },
17529   { STRING_COMMA_LEN ("false") },
17530   { STRING_COMMA_LEN ("neq_oq") },
17531   { STRING_COMMA_LEN ("ge") },
17532   { STRING_COMMA_LEN ("gt") },
17533   { STRING_COMMA_LEN ("true") },
17534   { STRING_COMMA_LEN ("eq_os") },
17535   { STRING_COMMA_LEN ("lt_oq") },
17536   { STRING_COMMA_LEN ("le_oq") },
17537   { STRING_COMMA_LEN ("unord_s") },
17538   { STRING_COMMA_LEN ("neq_us") },
17539   { STRING_COMMA_LEN ("nlt_uq") },
17540   { STRING_COMMA_LEN ("nle_uq") },
17541   { STRING_COMMA_LEN ("ord_s") },
17542   { STRING_COMMA_LEN ("eq_us") },
17543   { STRING_COMMA_LEN ("nge_uq") },
17544   { STRING_COMMA_LEN ("ngt_uq") },
17545   { STRING_COMMA_LEN ("false_os") },
17546   { STRING_COMMA_LEN ("neq_os") },
17547   { STRING_COMMA_LEN ("ge_oq") },
17548   { STRING_COMMA_LEN ("gt_oq") },
17549   { STRING_COMMA_LEN ("true_us") },
17550 };
17551
17552 static void
17553 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17554 {
17555   unsigned int cmp_type;
17556
17557   FETCH_DATA (the_info, codep + 1);
17558   cmp_type = *codep++ & 0xff;
17559   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17560     {
17561       char suffix [3];
17562       char *p = mnemonicendp - 2;
17563       suffix[0] = p[0];
17564       suffix[1] = p[1];
17565       suffix[2] = '\0';
17566       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17567       mnemonicendp += vex_cmp_op[cmp_type].len;
17568     }
17569   else
17570     {
17571       /* We have a reserved extension byte.  Output it directly.  */
17572       scratchbuf[0] = '$';
17573       print_operand_value (scratchbuf + 1, 1, cmp_type);
17574       oappend_maybe_intel (scratchbuf);
17575       scratchbuf[0] = '\0';
17576     }
17577 }
17578
17579 static void
17580 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17581              int sizeflag ATTRIBUTE_UNUSED)
17582 {
17583   unsigned int cmp_type;
17584
17585   if (!vex.evex)
17586     abort ();
17587
17588   FETCH_DATA (the_info, codep + 1);
17589   cmp_type = *codep++ & 0xff;
17590   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17591      If it's the case, print suffix, otherwise - print the immediate.  */
17592   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17593       && cmp_type != 3
17594       && cmp_type != 7)
17595     {
17596       char suffix [3];
17597       char *p = mnemonicendp - 2;
17598
17599       /* vpcmp* can have both one- and two-lettered suffix.  */
17600       if (p[0] == 'p')
17601         {
17602           p++;
17603           suffix[0] = p[0];
17604           suffix[1] = '\0';
17605         }
17606       else
17607         {
17608           suffix[0] = p[0];
17609           suffix[1] = p[1];
17610           suffix[2] = '\0';
17611         }
17612
17613       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17614       mnemonicendp += simd_cmp_op[cmp_type].len;
17615     }
17616   else
17617     {
17618       /* We have a reserved extension byte.  Output it directly.  */
17619       scratchbuf[0] = '$';
17620       print_operand_value (scratchbuf + 1, 1, cmp_type);
17621       oappend_maybe_intel (scratchbuf);
17622       scratchbuf[0] = '\0';
17623     }
17624 }
17625
17626 static const struct op xop_cmp_op[] =
17627 {
17628   { STRING_COMMA_LEN ("lt") },
17629   { STRING_COMMA_LEN ("le") },
17630   { STRING_COMMA_LEN ("gt") },
17631   { STRING_COMMA_LEN ("ge") },
17632   { STRING_COMMA_LEN ("eq") },
17633   { STRING_COMMA_LEN ("neq") },
17634   { STRING_COMMA_LEN ("false") },
17635   { STRING_COMMA_LEN ("true") }
17636 };
17637
17638 static void
17639 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17640              int sizeflag ATTRIBUTE_UNUSED)
17641 {
17642   unsigned int cmp_type;
17643
17644   FETCH_DATA (the_info, codep + 1);
17645   cmp_type = *codep++ & 0xff;
17646   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17647     {
17648       char suffix[3];
17649       char *p = mnemonicendp - 2;
17650
17651       /* vpcom* can have both one- and two-lettered suffix.  */
17652       if (p[0] == 'm')
17653         {
17654           p++;
17655           suffix[0] = p[0];
17656           suffix[1] = '\0';
17657         }
17658       else
17659         {
17660           suffix[0] = p[0];
17661           suffix[1] = p[1];
17662           suffix[2] = '\0';
17663         }
17664
17665       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17666       mnemonicendp += xop_cmp_op[cmp_type].len;
17667     }
17668   else
17669     {
17670       /* We have a reserved extension byte.  Output it directly.  */
17671       scratchbuf[0] = '$';
17672       print_operand_value (scratchbuf + 1, 1, cmp_type);
17673       oappend_maybe_intel (scratchbuf);
17674       scratchbuf[0] = '\0';
17675     }
17676 }
17677
17678 static const struct op pclmul_op[] =
17679 {
17680   { STRING_COMMA_LEN ("lql") },
17681   { STRING_COMMA_LEN ("hql") },
17682   { STRING_COMMA_LEN ("lqh") },
17683   { STRING_COMMA_LEN ("hqh") }
17684 };
17685
17686 static void
17687 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17688               int sizeflag ATTRIBUTE_UNUSED)
17689 {
17690   unsigned int pclmul_type;
17691
17692   FETCH_DATA (the_info, codep + 1);
17693   pclmul_type = *codep++ & 0xff;
17694   switch (pclmul_type)
17695     {
17696     case 0x10:
17697       pclmul_type = 2;
17698       break;
17699     case 0x11:
17700       pclmul_type = 3;
17701       break;
17702     default:
17703       break;
17704     }
17705   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17706     {
17707       char suffix [4];
17708       char *p = mnemonicendp - 3;
17709       suffix[0] = p[0];
17710       suffix[1] = p[1];
17711       suffix[2] = p[2];
17712       suffix[3] = '\0';
17713       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17714       mnemonicendp += pclmul_op[pclmul_type].len;
17715     }
17716   else
17717     {
17718       /* We have a reserved extension byte.  Output it directly.  */
17719       scratchbuf[0] = '$';
17720       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17721       oappend_maybe_intel (scratchbuf);
17722       scratchbuf[0] = '\0';
17723     }
17724 }
17725
17726 static void
17727 MOVBE_Fixup (int bytemode, int sizeflag)
17728 {
17729   /* Add proper suffix to "movbe".  */
17730   char *p = mnemonicendp;
17731
17732   switch (bytemode)
17733     {
17734     case v_mode:
17735       if (intel_syntax)
17736         goto skip;
17737
17738       USED_REX (REX_W);
17739       if (sizeflag & SUFFIX_ALWAYS)
17740         {
17741           if (rex & REX_W)
17742             *p++ = 'q';
17743           else
17744             {
17745               if (sizeflag & DFLAG)
17746                 *p++ = 'l';
17747               else
17748                 *p++ = 'w';
17749               used_prefixes |= (prefixes & PREFIX_DATA);
17750             }
17751         }
17752       break;
17753     default:
17754       oappend (INTERNAL_DISASSEMBLER_ERROR);
17755       break;
17756     }
17757   mnemonicendp = p;
17758   *p = '\0';
17759
17760 skip:
17761   OP_M (bytemode, sizeflag);
17762 }
17763
17764 static void
17765 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17766 {
17767   int reg;
17768   const char **names;
17769
17770   /* Skip mod/rm byte.  */
17771   MODRM_CHECK;
17772   codep++;
17773
17774   if (vex.w)
17775     names = names64;
17776   else
17777     names = names32;
17778
17779   reg = modrm.rm;
17780   USED_REX (REX_B);
17781   if (rex & REX_B)
17782     reg += 8;
17783
17784   oappend (names[reg]);
17785 }
17786
17787 static void
17788 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17789 {
17790   const char **names;
17791
17792   if (vex.w)
17793     names = names64;
17794   else
17795     names = names32;
17796
17797   oappend (names[vex.register_specifier]);
17798 }
17799
17800 static void
17801 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17802 {
17803   if (!vex.evex
17804       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17805     abort ();
17806
17807   USED_REX (REX_R);
17808   if ((rex & REX_R) != 0 || !vex.r)
17809     {
17810       BadOp ();
17811       return;
17812     }
17813
17814   oappend (names_mask [modrm.reg]);
17815 }
17816
17817 static void
17818 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17819 {
17820   if (!vex.evex
17821       || (bytemode != evex_rounding_mode
17822           && bytemode != evex_sae_mode))
17823     abort ();
17824   if (modrm.mod == 3 && vex.b)
17825     switch (bytemode)
17826       {
17827       case evex_rounding_mode:
17828         oappend (names_rounding[vex.ll]);
17829         break;
17830       case evex_sae_mode:
17831         oappend ("{sae}");
17832         break;
17833       default:
17834         break;
17835       }
17836 }