opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXbScalar { OP_EX, b_scalar_mode }
 380 #define EXw { OP_EX, w_mode }
 381 #define EXwScalar { OP_EX, w_scalar_mode }
 382 #define EXd { OP_EX, d_mode }
 383 #define EXdScalar { OP_EX, d_scalar_mode }
 384 #define EXdS { OP_EX, d_swap_mode }
 385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 386 #define EXq { OP_EX, q_mode }
 387 #define EXqScalar { OP_EX, q_scalar_mode }
 388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 401 #define EXxmmdw { OP_EX, xmmdw_mode }
 402 #define EXxmmqd { OP_EX, xmmqd_mode }
 403 #define EXymmq { OP_EX, ymmq_mode }
 404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 408 #define MS { OP_MS, v_mode }
 409 #define XS { OP_XS, v_mode }
 410 #define EMCq { OP_EMC, q_mode }
 411 #define MXC { OP_MXC, 0 }
 412 #define OPSUF { OP_3DNowSuffix, 0 }
 413 #define CMP { CMP_Fixup, 0 }
 414 #define XMM0 { XMM_Fixup, 0 }
 415 #define FXSAVE { FXSAVE_Fixup, 0 }
 416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 418
 419 #define Vex { OP_VEX, vex_mode }
 420 #define VexScalar { OP_VEX, vex_scalar_mode }
 421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 422 #define Vex128 { OP_VEX, vex128_mode }
 423 #define Vex256 { OP_VEX, vex256_mode }
 424 #define VexGdq { OP_VEX, dq_mode }
 425 #define EXdVex { OP_EX_Vex, d_mode }
 426 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 428 #define EXqVex { OP_EX_Vex, q_mode }
 429 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 430 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 431 #define EXVexW { OP_EX_VexW, x_mode }
 432 #define EXdVexW { OP_EX_VexW, d_mode }
 433 #define EXqVexW { OP_EX_VexW, q_mode }
 434 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 435 #define XMVex { OP_XMM_Vex, 0 }
 436 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 437 #define XMVexW { OP_XMM_VexW, 0 }
 438 #define XMVexI4 { OP_REG_VexI4, x_mode }
 439 #define PCLMUL { PCLMUL_Fixup, 0 }
 440 #define VZERO { VZERO_Fixup, 0 }
 441 #define VCMP { VCMP_Fixup, 0 }
 442 #define VPCMP { VPCMP_Fixup, 0 }
 443 #define VPCOM { VPCOM_Fixup, 0 }
 444
 445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 447
 448 #define XMask { OP_Mask, mask_mode }
 449 #define MaskG { OP_G, mask_mode }
 450 #define MaskE { OP_E, mask_mode }
 451 #define MaskBDE { OP_E, mask_bd_mode }
 452 #define MaskR { OP_R, mask_mode }
 453 #define MaskVex { OP_VEX, mask_mode }
 454
 455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 459
 460 /* Used handle "rep" prefix for string instructions.  */
 461 #define Xbr { REP_Fixup, eSI_reg }
 462 #define Xvr { REP_Fixup, eSI_reg }
 463 #define Ybr { REP_Fixup, eDI_reg }
 464 #define Yvr { REP_Fixup, eDI_reg }
 465 #define Yzr { REP_Fixup, eDI_reg }
 466 #define indirDXr { REP_Fixup, indir_dx_reg }
 467 #define ALr { REP_Fixup, al_reg }
 468 #define eAXr { REP_Fixup, eAX_reg }
 469
 470 /* Used handle HLE prefix for lockable instructions.  */
 471 #define Ebh1 { HLE_Fixup1, b_mode }
 472 #define Evh1 { HLE_Fixup1, v_mode }
 473 #define Ebh2 { HLE_Fixup2, b_mode }
 474 #define Evh2 { HLE_Fixup2, v_mode }
 475 #define Ebh3 { HLE_Fixup3, b_mode }
 476 #define Evh3 { HLE_Fixup3, v_mode }
 477
 478 #define BND { BND_Fixup, 0 }
 479 #define NOTRACK { NOTRACK_Fixup, 0 }
 480
 481 #define cond_jump_flag { NULL, cond_jump_mode }
 482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 483
 484 /* bits in sizeflag */
 485 #define SUFFIX_ALWAYS 4
 486 #define AFLAG 2
 487 #define DFLAG 1
 488
 489 enum
 490 {
 491   /* byte operand */
 492   b_mode = 1,
 493   /* byte operand with operand swapped */
 494   b_swap_mode,
 495   /* byte operand, sign extend like 'T' suffix */
 496   b_T_mode,
 497   /* operand size depends on prefixes */
 498   v_mode,
 499   /* operand size depends on prefixes with operand swapped */
 500   v_swap_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* XMM register or double/quad word memory operand, depending on
 540      VEX.W.  */
 541   xmm_mdq_mode,
 542   /* 16-byte XMM, word, double word or quad word operand.  */
 543   xmmdw_mode,
 544   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 545   xmmqd_mode,
 546   /* 32-byte YMM operand */
 547   ymm_mode,
 548   /* quad word, ymmword or zmmword memory operand.  */
 549   ymmq_mode,
 550   /* 32-byte YMM or 16-byte word operand */
 551   ymmxmm_mode,
 552   /* d_mode in 32bit, q_mode in 64bit mode.  */
 553   m_mode,
 554   /* pair of v_mode operands */
 555   a_mode,
 556   cond_jump_mode,
 557   loop_jcxz_mode,
 558   v_bnd_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode.  */
 562   dqw_mode,
 563   bnd_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589   /* operand size depends on the VEX.W bit.  */
 590   vex_w_dq_mode,
 591
 592   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like b_mode, ignore vector length.  */
 604   b_scalar_mode,
 605   /* like w_mode, ignore vector length.  */
 606   w_scalar_mode,
 607   /* like d_mode, ignore vector length.  */
 608   d_scalar_mode,
 609   /* like d_swap_mode, ignore vector length.  */
 610   d_scalar_swap_mode,
 611   /* like q_mode, ignore vector length.  */
 612   q_scalar_mode,
 613   /* like q_swap_mode, ignore vector length.  */
 614   q_scalar_swap_mode,
 615   /* like vex_mode, ignore vector length.  */
 616   vex_scalar_mode,
 617   /* like vex_w_dq_mode, ignore vector length.  */
 618   vex_scalar_w_dq_mode,
 619
 620   /* Static rounding.  */
 621   evex_rounding_mode,
 622   /* Supress all exceptions.  */
 623   evex_sae_mode,
 624
 625   /* Mask register operand.  */
 626   mask_mode,
 627   /* Mask register operand.  */
 628   mask_bd_mode,
 629
 630   es_reg,
 631   cs_reg,
 632   ss_reg,
 633   ds_reg,
 634   fs_reg,
 635   gs_reg,
 636
 637   eAX_reg,
 638   eCX_reg,
 639   eDX_reg,
 640   eBX_reg,
 641   eSP_reg,
 642   eBP_reg,
 643   eSI_reg,
 644   eDI_reg,
 645
 646   al_reg,
 647   cl_reg,
 648   dl_reg,
 649   bl_reg,
 650   ah_reg,
 651   ch_reg,
 652   dh_reg,
 653   bh_reg,
 654
 655   ax_reg,
 656   cx_reg,
 657   dx_reg,
 658   bx_reg,
 659   sp_reg,
 660   bp_reg,
 661   si_reg,
 662   di_reg,
 663
 664   rAX_reg,
 665   rCX_reg,
 666   rDX_reg,
 667   rBX_reg,
 668   rSP_reg,
 669   rBP_reg,
 670   rSI_reg,
 671   rDI_reg,
 672
 673   z_mode_ax_reg,
 674   indir_dx_reg
 675 };
 676
 677 enum
 678 {
 679   FLOATCODE = 1,
 680   USE_REG_TABLE,
 681   USE_MOD_TABLE,
 682   USE_RM_TABLE,
 683   USE_PREFIX_TABLE,
 684   USE_X86_64_TABLE,
 685   USE_3BYTE_TABLE,
 686   USE_XOP_8F_TABLE,
 687   USE_VEX_C4_TABLE,
 688   USE_VEX_C5_TABLE,
 689   USE_VEX_LEN_TABLE,
 690   USE_VEX_W_TABLE,
 691   USE_EVEX_TABLE
 692 };
 693
 694 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 695
 696 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 697 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 698 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 699 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 700 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 701 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 702 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 703 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 704 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 705 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 706 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 707 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 708 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 709 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 710 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 711
 712 enum
 713 {
 714   REG_80 = 0,
 715   REG_81,
 716   REG_83,
 717   REG_8F,
 718   REG_C0,
 719   REG_C1,
 720   REG_C6,
 721   REG_C7,
 722   REG_D0,
 723   REG_D1,
 724   REG_D2,
 725   REG_D3,
 726   REG_F6,
 727   REG_F7,
 728   REG_FE,
 729   REG_FF,
 730   REG_0F00,
 731   REG_0F01,
 732   REG_0F0D,
 733   REG_0F18,
 734   REG_0F1E_MOD_3,
 735   REG_0F71,
 736   REG_0F72,
 737   REG_0F73,
 738   REG_0FA6,
 739   REG_0FA7,
 740   REG_0FAE,
 741   REG_0FBA,
 742   REG_0FC7,
 743   REG_VEX_0F71,
 744   REG_VEX_0F72,
 745   REG_VEX_0F73,
 746   REG_VEX_0FAE,
 747   REG_VEX_0F38F3,
 748   REG_XOP_LWPCB,
 749   REG_XOP_LWP,
 750   REG_XOP_TBM_01,
 751   REG_XOP_TBM_02,
 752
 753   REG_EVEX_0F71,
 754   REG_EVEX_0F72,
 755   REG_EVEX_0F73,
 756   REG_EVEX_0F38C6,
 757   REG_EVEX_0F38C7
 758 };
 759
 760 enum
 761 {
 762   MOD_8D = 0,
 763   MOD_C6_REG_7,
 764   MOD_C7_REG_7,
 765   MOD_FF_REG_3,
 766   MOD_FF_REG_5,
 767   MOD_0F01_REG_0,
 768   MOD_0F01_REG_1,
 769   MOD_0F01_REG_2,
 770   MOD_0F01_REG_3,
 771   MOD_0F01_REG_5,
 772   MOD_0F01_REG_7,
 773   MOD_0F12_PREFIX_0,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F17,
 777   MOD_0F18_REG_0,
 778   MOD_0F18_REG_1,
 779   MOD_0F18_REG_2,
 780   MOD_0F18_REG_3,
 781   MOD_0F18_REG_4,
 782   MOD_0F18_REG_5,
 783   MOD_0F18_REG_6,
 784   MOD_0F18_REG_7,
 785   MOD_0F1A_PREFIX_0,
 786   MOD_0F1B_PREFIX_0,
 787   MOD_0F1B_PREFIX_1,
 788   MOD_0F1E_PREFIX_1,
 789   MOD_0F24,
 790   MOD_0F26,
 791   MOD_0F2B_PREFIX_0,
 792   MOD_0F2B_PREFIX_1,
 793   MOD_0F2B_PREFIX_2,
 794   MOD_0F2B_PREFIX_3,
 795   MOD_0F51,
 796   MOD_0F71_REG_2,
 797   MOD_0F71_REG_4,
 798   MOD_0F71_REG_6,
 799   MOD_0F72_REG_2,
 800   MOD_0F72_REG_4,
 801   MOD_0F72_REG_6,
 802   MOD_0F73_REG_2,
 803   MOD_0F73_REG_3,
 804   MOD_0F73_REG_6,
 805   MOD_0F73_REG_7,
 806   MOD_0FAE_REG_0,
 807   MOD_0FAE_REG_1,
 808   MOD_0FAE_REG_2,
 809   MOD_0FAE_REG_3,
 810   MOD_0FAE_REG_4,
 811   MOD_0FAE_REG_5,
 812   MOD_0FAE_REG_6,
 813   MOD_0FAE_REG_7,
 814   MOD_0FB2,
 815   MOD_0FB4,
 816   MOD_0FB5,
 817   MOD_0FC3,
 818   MOD_0FC7_REG_3,
 819   MOD_0FC7_REG_4,
 820   MOD_0FC7_REG_5,
 821   MOD_0FC7_REG_6,
 822   MOD_0FC7_REG_7,
 823   MOD_0FD7,
 824   MOD_0FE7_PREFIX_2,
 825   MOD_0FF0_PREFIX_3,
 826   MOD_0F382A_PREFIX_2,
 827   MOD_0F38F5_PREFIX_2,
 828   MOD_0F38F6_PREFIX_0,
 829   MOD_62_32BIT,
 830   MOD_C4_32BIT,
 831   MOD_C5_32BIT,
 832   MOD_VEX_0F12_PREFIX_0,
 833   MOD_VEX_0F13,
 834   MOD_VEX_0F16_PREFIX_0,
 835   MOD_VEX_0F17,
 836   MOD_VEX_0F2B,
 837   MOD_VEX_W_0_0F41_P_0_LEN_1,
 838   MOD_VEX_W_1_0F41_P_0_LEN_1,
 839   MOD_VEX_W_0_0F41_P_2_LEN_1,
 840   MOD_VEX_W_1_0F41_P_2_LEN_1,
 841   MOD_VEX_W_0_0F42_P_0_LEN_1,
 842   MOD_VEX_W_1_0F42_P_0_LEN_1,
 843   MOD_VEX_W_0_0F42_P_2_LEN_1,
 844   MOD_VEX_W_1_0F42_P_2_LEN_1,
 845   MOD_VEX_W_0_0F44_P_0_LEN_1,
 846   MOD_VEX_W_1_0F44_P_0_LEN_1,
 847   MOD_VEX_W_0_0F44_P_2_LEN_1,
 848   MOD_VEX_W_1_0F44_P_2_LEN_1,
 849   MOD_VEX_W_0_0F45_P_0_LEN_1,
 850   MOD_VEX_W_1_0F45_P_0_LEN_1,
 851   MOD_VEX_W_0_0F45_P_2_LEN_1,
 852   MOD_VEX_W_1_0F45_P_2_LEN_1,
 853   MOD_VEX_W_0_0F46_P_0_LEN_1,
 854   MOD_VEX_W_1_0F46_P_0_LEN_1,
 855   MOD_VEX_W_0_0F46_P_2_LEN_1,
 856   MOD_VEX_W_1_0F46_P_2_LEN_1,
 857   MOD_VEX_W_0_0F47_P_0_LEN_1,
 858   MOD_VEX_W_1_0F47_P_0_LEN_1,
 859   MOD_VEX_W_0_0F47_P_2_LEN_1,
 860   MOD_VEX_W_1_0F47_P_2_LEN_1,
 861   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 868   MOD_VEX_0F50,
 869   MOD_VEX_0F71_REG_2,
 870   MOD_VEX_0F71_REG_4,
 871   MOD_VEX_0F71_REG_6,
 872   MOD_VEX_0F72_REG_2,
 873   MOD_VEX_0F72_REG_4,
 874   MOD_VEX_0F72_REG_6,
 875   MOD_VEX_0F73_REG_2,
 876   MOD_VEX_0F73_REG_3,
 877   MOD_VEX_0F73_REG_6,
 878   MOD_VEX_0F73_REG_7,
 879   MOD_VEX_W_0_0F91_P_0_LEN_0,
 880   MOD_VEX_W_1_0F91_P_0_LEN_0,
 881   MOD_VEX_W_0_0F91_P_2_LEN_0,
 882   MOD_VEX_W_1_0F91_P_2_LEN_0,
 883   MOD_VEX_W_0_0F92_P_0_LEN_0,
 884   MOD_VEX_W_0_0F92_P_2_LEN_0,
 885   MOD_VEX_W_0_0F92_P_3_LEN_0,
 886   MOD_VEX_W_1_0F92_P_3_LEN_0,
 887   MOD_VEX_W_0_0F93_P_0_LEN_0,
 888   MOD_VEX_W_0_0F93_P_2_LEN_0,
 889   MOD_VEX_W_0_0F93_P_3_LEN_0,
 890   MOD_VEX_W_1_0F93_P_3_LEN_0,
 891   MOD_VEX_W_0_0F98_P_0_LEN_0,
 892   MOD_VEX_W_1_0F98_P_0_LEN_0,
 893   MOD_VEX_W_0_0F98_P_2_LEN_0,
 894   MOD_VEX_W_1_0F98_P_2_LEN_0,
 895   MOD_VEX_W_0_0F99_P_0_LEN_0,
 896   MOD_VEX_W_1_0F99_P_0_LEN_0,
 897   MOD_VEX_W_0_0F99_P_2_LEN_0,
 898   MOD_VEX_W_1_0F99_P_2_LEN_0,
 899   MOD_VEX_0FAE_REG_2,
 900   MOD_VEX_0FAE_REG_3,
 901   MOD_VEX_0FD7_PREFIX_2,
 902   MOD_VEX_0FE7_PREFIX_2,
 903   MOD_VEX_0FF0_PREFIX_3,
 904   MOD_VEX_0F381A_PREFIX_2,
 905   MOD_VEX_0F382A_PREFIX_2,
 906   MOD_VEX_0F382C_PREFIX_2,
 907   MOD_VEX_0F382D_PREFIX_2,
 908   MOD_VEX_0F382E_PREFIX_2,
 909   MOD_VEX_0F382F_PREFIX_2,
 910   MOD_VEX_0F385A_PREFIX_2,
 911   MOD_VEX_0F388C_PREFIX_2,
 912   MOD_VEX_0F388E_PREFIX_2,
 913   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 921
 922   MOD_EVEX_0F10_PREFIX_1,
 923   MOD_EVEX_0F10_PREFIX_3,
 924   MOD_EVEX_0F11_PREFIX_1,
 925   MOD_EVEX_0F11_PREFIX_3,
 926   MOD_EVEX_0F12_PREFIX_0,
 927   MOD_EVEX_0F16_PREFIX_0,
 928   MOD_EVEX_0F38C6_REG_1,
 929   MOD_EVEX_0F38C6_REG_2,
 930   MOD_EVEX_0F38C6_REG_5,
 931   MOD_EVEX_0F38C6_REG_6,
 932   MOD_EVEX_0F38C7_REG_1,
 933   MOD_EVEX_0F38C7_REG_2,
 934   MOD_EVEX_0F38C7_REG_5,
 935   MOD_EVEX_0F38C7_REG_6
 936 };
 937
 938 enum
 939 {
 940   RM_C6_REG_7 = 0,
 941   RM_C7_REG_7,
 942   RM_0F01_REG_0,
 943   RM_0F01_REG_1,
 944   RM_0F01_REG_2,
 945   RM_0F01_REG_3,
 946   RM_0F01_REG_5,
 947   RM_0F01_REG_7,
 948   RM_0F1E_MOD_3_REG_7,
 949   RM_0FAE_REG_6,
 950   RM_0FAE_REG_7
 951 };
 952
 953 enum
 954 {
 955   PREFIX_90 = 0,
 956   PREFIX_MOD_0_0F01_REG_5,
 957   PREFIX_MOD_3_0F01_REG_5_RM_0,
 958   PREFIX_MOD_3_0F01_REG_5_RM_2,
 959   PREFIX_0F09,
 960   PREFIX_0F10,
 961   PREFIX_0F11,
 962   PREFIX_0F12,
 963   PREFIX_0F16,
 964   PREFIX_0F1A,
 965   PREFIX_0F1B,
 966   PREFIX_0F1E,
 967   PREFIX_0F2A,
 968   PREFIX_0F2B,
 969   PREFIX_0F2C,
 970   PREFIX_0F2D,
 971   PREFIX_0F2E,
 972   PREFIX_0F2F,
 973   PREFIX_0F51,
 974   PREFIX_0F52,
 975   PREFIX_0F53,
 976   PREFIX_0F58,
 977   PREFIX_0F59,
 978   PREFIX_0F5A,
 979   PREFIX_0F5B,
 980   PREFIX_0F5C,
 981   PREFIX_0F5D,
 982   PREFIX_0F5E,
 983   PREFIX_0F5F,
 984   PREFIX_0F60,
 985   PREFIX_0F61,
 986   PREFIX_0F62,
 987   PREFIX_0F6C,
 988   PREFIX_0F6D,
 989   PREFIX_0F6F,
 990   PREFIX_0F70,
 991   PREFIX_0F73_REG_3,
 992   PREFIX_0F73_REG_7,
 993   PREFIX_0F78,
 994   PREFIX_0F79,
 995   PREFIX_0F7C,
 996   PREFIX_0F7D,
 997   PREFIX_0F7E,
 998   PREFIX_0F7F,
 999   PREFIX_0FAE_REG_0,
1000   PREFIX_0FAE_REG_1,
1001   PREFIX_0FAE_REG_2,
1002   PREFIX_0FAE_REG_3,
1003   PREFIX_MOD_0_0FAE_REG_4,
1004   PREFIX_MOD_3_0FAE_REG_4,
1005   PREFIX_MOD_0_0FAE_REG_5,
1006   PREFIX_MOD_3_0FAE_REG_5,
1007   PREFIX_0FAE_REG_6,
1008   PREFIX_0FAE_REG_7,
1009   PREFIX_0FB8,
1010   PREFIX_0FBC,
1011   PREFIX_0FBD,
1012   PREFIX_0FC2,
1013   PREFIX_MOD_0_0FC3,
1014   PREFIX_MOD_0_0FC7_REG_6,
1015   PREFIX_MOD_3_0FC7_REG_6,
1016   PREFIX_MOD_3_0FC7_REG_7,
1017   PREFIX_0FD0,
1018   PREFIX_0FD6,
1019   PREFIX_0FE6,
1020   PREFIX_0FE7,
1021   PREFIX_0FF0,
1022   PREFIX_0FF7,
1023   PREFIX_0F3810,
1024   PREFIX_0F3814,
1025   PREFIX_0F3815,
1026   PREFIX_0F3817,
1027   PREFIX_0F3820,
1028   PREFIX_0F3821,
1029   PREFIX_0F3822,
1030   PREFIX_0F3823,
1031   PREFIX_0F3824,
1032   PREFIX_0F3825,
1033   PREFIX_0F3828,
1034   PREFIX_0F3829,
1035   PREFIX_0F382A,
1036   PREFIX_0F382B,
1037   PREFIX_0F3830,
1038   PREFIX_0F3831,
1039   PREFIX_0F3832,
1040   PREFIX_0F3833,
1041   PREFIX_0F3834,
1042   PREFIX_0F3835,
1043   PREFIX_0F3837,
1044   PREFIX_0F3838,
1045   PREFIX_0F3839,
1046   PREFIX_0F383A,
1047   PREFIX_0F383B,
1048   PREFIX_0F383C,
1049   PREFIX_0F383D,
1050   PREFIX_0F383E,
1051   PREFIX_0F383F,
1052   PREFIX_0F3840,
1053   PREFIX_0F3841,
1054   PREFIX_0F3880,
1055   PREFIX_0F3881,
1056   PREFIX_0F3882,
1057   PREFIX_0F38C8,
1058   PREFIX_0F38C9,
1059   PREFIX_0F38CA,
1060   PREFIX_0F38CB,
1061   PREFIX_0F38CC,
1062   PREFIX_0F38CD,
1063   PREFIX_0F38CF,
1064   PREFIX_0F38DB,
1065   PREFIX_0F38DC,
1066   PREFIX_0F38DD,
1067   PREFIX_0F38DE,
1068   PREFIX_0F38DF,
1069   PREFIX_0F38F0,
1070   PREFIX_0F38F1,
1071   PREFIX_0F38F5,
1072   PREFIX_0F38F6,
1073   PREFIX_0F3A08,
1074   PREFIX_0F3A09,
1075   PREFIX_0F3A0A,
1076   PREFIX_0F3A0B,
1077   PREFIX_0F3A0C,
1078   PREFIX_0F3A0D,
1079   PREFIX_0F3A0E,
1080   PREFIX_0F3A14,
1081   PREFIX_0F3A15,
1082   PREFIX_0F3A16,
1083   PREFIX_0F3A17,
1084   PREFIX_0F3A20,
1085   PREFIX_0F3A21,
1086   PREFIX_0F3A22,
1087   PREFIX_0F3A40,
1088   PREFIX_0F3A41,
1089   PREFIX_0F3A42,
1090   PREFIX_0F3A44,
1091   PREFIX_0F3A60,
1092   PREFIX_0F3A61,
1093   PREFIX_0F3A62,
1094   PREFIX_0F3A63,
1095   PREFIX_0F3ACC,
1096   PREFIX_0F3ACE,
1097   PREFIX_0F3ACF,
1098   PREFIX_0F3ADF,
1099   PREFIX_VEX_0F10,
1100   PREFIX_VEX_0F11,
1101   PREFIX_VEX_0F12,
1102   PREFIX_VEX_0F16,
1103   PREFIX_VEX_0F2A,
1104   PREFIX_VEX_0F2C,
1105   PREFIX_VEX_0F2D,
1106   PREFIX_VEX_0F2E,
1107   PREFIX_VEX_0F2F,
1108   PREFIX_VEX_0F41,
1109   PREFIX_VEX_0F42,
1110   PREFIX_VEX_0F44,
1111   PREFIX_VEX_0F45,
1112   PREFIX_VEX_0F46,
1113   PREFIX_VEX_0F47,
1114   PREFIX_VEX_0F4A,
1115   PREFIX_VEX_0F4B,
1116   PREFIX_VEX_0F51,
1117   PREFIX_VEX_0F52,
1118   PREFIX_VEX_0F53,
1119   PREFIX_VEX_0F58,
1120   PREFIX_VEX_0F59,
1121   PREFIX_VEX_0F5A,
1122   PREFIX_VEX_0F5B,
1123   PREFIX_VEX_0F5C,
1124   PREFIX_VEX_0F5D,
1125   PREFIX_VEX_0F5E,
1126   PREFIX_VEX_0F5F,
1127   PREFIX_VEX_0F60,
1128   PREFIX_VEX_0F61,
1129   PREFIX_VEX_0F62,
1130   PREFIX_VEX_0F63,
1131   PREFIX_VEX_0F64,
1132   PREFIX_VEX_0F65,
1133   PREFIX_VEX_0F66,
1134   PREFIX_VEX_0F67,
1135   PREFIX_VEX_0F68,
1136   PREFIX_VEX_0F69,
1137   PREFIX_VEX_0F6A,
1138   PREFIX_VEX_0F6B,
1139   PREFIX_VEX_0F6C,
1140   PREFIX_VEX_0F6D,
1141   PREFIX_VEX_0F6E,
1142   PREFIX_VEX_0F6F,
1143   PREFIX_VEX_0F70,
1144   PREFIX_VEX_0F71_REG_2,
1145   PREFIX_VEX_0F71_REG_4,
1146   PREFIX_VEX_0F71_REG_6,
1147   PREFIX_VEX_0F72_REG_2,
1148   PREFIX_VEX_0F72_REG_4,
1149   PREFIX_VEX_0F72_REG_6,
1150   PREFIX_VEX_0F73_REG_2,
1151   PREFIX_VEX_0F73_REG_3,
1152   PREFIX_VEX_0F73_REG_6,
1153   PREFIX_VEX_0F73_REG_7,
1154   PREFIX_VEX_0F74,
1155   PREFIX_VEX_0F75,
1156   PREFIX_VEX_0F76,
1157   PREFIX_VEX_0F77,
1158   PREFIX_VEX_0F7C,
1159   PREFIX_VEX_0F7D,
1160   PREFIX_VEX_0F7E,
1161   PREFIX_VEX_0F7F,
1162   PREFIX_VEX_0F90,
1163   PREFIX_VEX_0F91,
1164   PREFIX_VEX_0F92,
1165   PREFIX_VEX_0F93,
1166   PREFIX_VEX_0F98,
1167   PREFIX_VEX_0F99,
1168   PREFIX_VEX_0FC2,
1169   PREFIX_VEX_0FC4,
1170   PREFIX_VEX_0FC5,
1171   PREFIX_VEX_0FD0,
1172   PREFIX_VEX_0FD1,
1173   PREFIX_VEX_0FD2,
1174   PREFIX_VEX_0FD3,
1175   PREFIX_VEX_0FD4,
1176   PREFIX_VEX_0FD5,
1177   PREFIX_VEX_0FD6,
1178   PREFIX_VEX_0FD7,
1179   PREFIX_VEX_0FD8,
1180   PREFIX_VEX_0FD9,
1181   PREFIX_VEX_0FDA,
1182   PREFIX_VEX_0FDB,
1183   PREFIX_VEX_0FDC,
1184   PREFIX_VEX_0FDD,
1185   PREFIX_VEX_0FDE,
1186   PREFIX_VEX_0FDF,
1187   PREFIX_VEX_0FE0,
1188   PREFIX_VEX_0FE1,
1189   PREFIX_VEX_0FE2,
1190   PREFIX_VEX_0FE3,
1191   PREFIX_VEX_0FE4,
1192   PREFIX_VEX_0FE5,
1193   PREFIX_VEX_0FE6,
1194   PREFIX_VEX_0FE7,
1195   PREFIX_VEX_0FE8,
1196   PREFIX_VEX_0FE9,
1197   PREFIX_VEX_0FEA,
1198   PREFIX_VEX_0FEB,
1199   PREFIX_VEX_0FEC,
1200   PREFIX_VEX_0FED,
1201   PREFIX_VEX_0FEE,
1202   PREFIX_VEX_0FEF,
1203   PREFIX_VEX_0FF0,
1204   PREFIX_VEX_0FF1,
1205   PREFIX_VEX_0FF2,
1206   PREFIX_VEX_0FF3,
1207   PREFIX_VEX_0FF4,
1208   PREFIX_VEX_0FF5,
1209   PREFIX_VEX_0FF6,
1210   PREFIX_VEX_0FF7,
1211   PREFIX_VEX_0FF8,
1212   PREFIX_VEX_0FF9,
1213   PREFIX_VEX_0FFA,
1214   PREFIX_VEX_0FFB,
1215   PREFIX_VEX_0FFC,
1216   PREFIX_VEX_0FFD,
1217   PREFIX_VEX_0FFE,
1218   PREFIX_VEX_0F3800,
1219   PREFIX_VEX_0F3801,
1220   PREFIX_VEX_0F3802,
1221   PREFIX_VEX_0F3803,
1222   PREFIX_VEX_0F3804,
1223   PREFIX_VEX_0F3805,
1224   PREFIX_VEX_0F3806,
1225   PREFIX_VEX_0F3807,
1226   PREFIX_VEX_0F3808,
1227   PREFIX_VEX_0F3809,
1228   PREFIX_VEX_0F380A,
1229   PREFIX_VEX_0F380B,
1230   PREFIX_VEX_0F380C,
1231   PREFIX_VEX_0F380D,
1232   PREFIX_VEX_0F380E,
1233   PREFIX_VEX_0F380F,
1234   PREFIX_VEX_0F3813,
1235   PREFIX_VEX_0F3816,
1236   PREFIX_VEX_0F3817,
1237   PREFIX_VEX_0F3818,
1238   PREFIX_VEX_0F3819,
1239   PREFIX_VEX_0F381A,
1240   PREFIX_VEX_0F381C,
1241   PREFIX_VEX_0F381D,
1242   PREFIX_VEX_0F381E,
1243   PREFIX_VEX_0F3820,
1244   PREFIX_VEX_0F3821,
1245   PREFIX_VEX_0F3822,
1246   PREFIX_VEX_0F3823,
1247   PREFIX_VEX_0F3824,
1248   PREFIX_VEX_0F3825,
1249   PREFIX_VEX_0F3828,
1250   PREFIX_VEX_0F3829,
1251   PREFIX_VEX_0F382A,
1252   PREFIX_VEX_0F382B,
1253   PREFIX_VEX_0F382C,
1254   PREFIX_VEX_0F382D,
1255   PREFIX_VEX_0F382E,
1256   PREFIX_VEX_0F382F,
1257   PREFIX_VEX_0F3830,
1258   PREFIX_VEX_0F3831,
1259   PREFIX_VEX_0F3832,
1260   PREFIX_VEX_0F3833,
1261   PREFIX_VEX_0F3834,
1262   PREFIX_VEX_0F3835,
1263   PREFIX_VEX_0F3836,
1264   PREFIX_VEX_0F3837,
1265   PREFIX_VEX_0F3838,
1266   PREFIX_VEX_0F3839,
1267   PREFIX_VEX_0F383A,
1268   PREFIX_VEX_0F383B,
1269   PREFIX_VEX_0F383C,
1270   PREFIX_VEX_0F383D,
1271   PREFIX_VEX_0F383E,
1272   PREFIX_VEX_0F383F,
1273   PREFIX_VEX_0F3840,
1274   PREFIX_VEX_0F3841,
1275   PREFIX_VEX_0F3845,
1276   PREFIX_VEX_0F3846,
1277   PREFIX_VEX_0F3847,
1278   PREFIX_VEX_0F3858,
1279   PREFIX_VEX_0F3859,
1280   PREFIX_VEX_0F385A,
1281   PREFIX_VEX_0F3878,
1282   PREFIX_VEX_0F3879,
1283   PREFIX_VEX_0F388C,
1284   PREFIX_VEX_0F388E,
1285   PREFIX_VEX_0F3890,
1286   PREFIX_VEX_0F3891,
1287   PREFIX_VEX_0F3892,
1288   PREFIX_VEX_0F3893,
1289   PREFIX_VEX_0F3896,
1290   PREFIX_VEX_0F3897,
1291   PREFIX_VEX_0F3898,
1292   PREFIX_VEX_0F3899,
1293   PREFIX_VEX_0F389A,
1294   PREFIX_VEX_0F389B,
1295   PREFIX_VEX_0F389C,
1296   PREFIX_VEX_0F389D,
1297   PREFIX_VEX_0F389E,
1298   PREFIX_VEX_0F389F,
1299   PREFIX_VEX_0F38A6,
1300   PREFIX_VEX_0F38A7,
1301   PREFIX_VEX_0F38A8,
1302   PREFIX_VEX_0F38A9,
1303   PREFIX_VEX_0F38AA,
1304   PREFIX_VEX_0F38AB,
1305   PREFIX_VEX_0F38AC,
1306   PREFIX_VEX_0F38AD,
1307   PREFIX_VEX_0F38AE,
1308   PREFIX_VEX_0F38AF,
1309   PREFIX_VEX_0F38B6,
1310   PREFIX_VEX_0F38B7,
1311   PREFIX_VEX_0F38B8,
1312   PREFIX_VEX_0F38B9,
1313   PREFIX_VEX_0F38BA,
1314   PREFIX_VEX_0F38BB,
1315   PREFIX_VEX_0F38BC,
1316   PREFIX_VEX_0F38BD,
1317   PREFIX_VEX_0F38BE,
1318   PREFIX_VEX_0F38BF,
1319   PREFIX_VEX_0F38CF,
1320   PREFIX_VEX_0F38DB,
1321   PREFIX_VEX_0F38DC,
1322   PREFIX_VEX_0F38DD,
1323   PREFIX_VEX_0F38DE,
1324   PREFIX_VEX_0F38DF,
1325   PREFIX_VEX_0F38F2,
1326   PREFIX_VEX_0F38F3_REG_1,
1327   PREFIX_VEX_0F38F3_REG_2,
1328   PREFIX_VEX_0F38F3_REG_3,
1329   PREFIX_VEX_0F38F5,
1330   PREFIX_VEX_0F38F6,
1331   PREFIX_VEX_0F38F7,
1332   PREFIX_VEX_0F3A00,
1333   PREFIX_VEX_0F3A01,
1334   PREFIX_VEX_0F3A02,
1335   PREFIX_VEX_0F3A04,
1336   PREFIX_VEX_0F3A05,
1337   PREFIX_VEX_0F3A06,
1338   PREFIX_VEX_0F3A08,
1339   PREFIX_VEX_0F3A09,
1340   PREFIX_VEX_0F3A0A,
1341   PREFIX_VEX_0F3A0B,
1342   PREFIX_VEX_0F3A0C,
1343   PREFIX_VEX_0F3A0D,
1344   PREFIX_VEX_0F3A0E,
1345   PREFIX_VEX_0F3A0F,
1346   PREFIX_VEX_0F3A14,
1347   PREFIX_VEX_0F3A15,
1348   PREFIX_VEX_0F3A16,
1349   PREFIX_VEX_0F3A17,
1350   PREFIX_VEX_0F3A18,
1351   PREFIX_VEX_0F3A19,
1352   PREFIX_VEX_0F3A1D,
1353   PREFIX_VEX_0F3A20,
1354   PREFIX_VEX_0F3A21,
1355   PREFIX_VEX_0F3A22,
1356   PREFIX_VEX_0F3A30,
1357   PREFIX_VEX_0F3A31,
1358   PREFIX_VEX_0F3A32,
1359   PREFIX_VEX_0F3A33,
1360   PREFIX_VEX_0F3A38,
1361   PREFIX_VEX_0F3A39,
1362   PREFIX_VEX_0F3A40,
1363   PREFIX_VEX_0F3A41,
1364   PREFIX_VEX_0F3A42,
1365   PREFIX_VEX_0F3A44,
1366   PREFIX_VEX_0F3A46,
1367   PREFIX_VEX_0F3A48,
1368   PREFIX_VEX_0F3A49,
1369   PREFIX_VEX_0F3A4A,
1370   PREFIX_VEX_0F3A4B,
1371   PREFIX_VEX_0F3A4C,
1372   PREFIX_VEX_0F3A5C,
1373   PREFIX_VEX_0F3A5D,
1374   PREFIX_VEX_0F3A5E,
1375   PREFIX_VEX_0F3A5F,
1376   PREFIX_VEX_0F3A60,
1377   PREFIX_VEX_0F3A61,
1378   PREFIX_VEX_0F3A62,
1379   PREFIX_VEX_0F3A63,
1380   PREFIX_VEX_0F3A68,
1381   PREFIX_VEX_0F3A69,
1382   PREFIX_VEX_0F3A6A,
1383   PREFIX_VEX_0F3A6B,
1384   PREFIX_VEX_0F3A6C,
1385   PREFIX_VEX_0F3A6D,
1386   PREFIX_VEX_0F3A6E,
1387   PREFIX_VEX_0F3A6F,
1388   PREFIX_VEX_0F3A78,
1389   PREFIX_VEX_0F3A79,
1390   PREFIX_VEX_0F3A7A,
1391   PREFIX_VEX_0F3A7B,
1392   PREFIX_VEX_0F3A7C,
1393   PREFIX_VEX_0F3A7D,
1394   PREFIX_VEX_0F3A7E,
1395   PREFIX_VEX_0F3A7F,
1396   PREFIX_VEX_0F3ACE,
1397   PREFIX_VEX_0F3ACF,
1398   PREFIX_VEX_0F3ADF,
1399   PREFIX_VEX_0F3AF0,
1400
1401   PREFIX_EVEX_0F10,
1402   PREFIX_EVEX_0F11,
1403   PREFIX_EVEX_0F12,
1404   PREFIX_EVEX_0F13,
1405   PREFIX_EVEX_0F14,
1406   PREFIX_EVEX_0F15,
1407   PREFIX_EVEX_0F16,
1408   PREFIX_EVEX_0F17,
1409   PREFIX_EVEX_0F28,
1410   PREFIX_EVEX_0F29,
1411   PREFIX_EVEX_0F2A,
1412   PREFIX_EVEX_0F2B,
1413   PREFIX_EVEX_0F2C,
1414   PREFIX_EVEX_0F2D,
1415   PREFIX_EVEX_0F2E,
1416   PREFIX_EVEX_0F2F,
1417   PREFIX_EVEX_0F51,
1418   PREFIX_EVEX_0F54,
1419   PREFIX_EVEX_0F55,
1420   PREFIX_EVEX_0F56,
1421   PREFIX_EVEX_0F57,
1422   PREFIX_EVEX_0F58,
1423   PREFIX_EVEX_0F59,
1424   PREFIX_EVEX_0F5A,
1425   PREFIX_EVEX_0F5B,
1426   PREFIX_EVEX_0F5C,
1427   PREFIX_EVEX_0F5D,
1428   PREFIX_EVEX_0F5E,
1429   PREFIX_EVEX_0F5F,
1430   PREFIX_EVEX_0F60,
1431   PREFIX_EVEX_0F61,
1432   PREFIX_EVEX_0F62,
1433   PREFIX_EVEX_0F63,
1434   PREFIX_EVEX_0F64,
1435   PREFIX_EVEX_0F65,
1436   PREFIX_EVEX_0F66,
1437   PREFIX_EVEX_0F67,
1438   PREFIX_EVEX_0F68,
1439   PREFIX_EVEX_0F69,
1440   PREFIX_EVEX_0F6A,
1441   PREFIX_EVEX_0F6B,
1442   PREFIX_EVEX_0F6C,
1443   PREFIX_EVEX_0F6D,
1444   PREFIX_EVEX_0F6E,
1445   PREFIX_EVEX_0F6F,
1446   PREFIX_EVEX_0F70,
1447   PREFIX_EVEX_0F71_REG_2,
1448   PREFIX_EVEX_0F71_REG_4,
1449   PREFIX_EVEX_0F71_REG_6,
1450   PREFIX_EVEX_0F72_REG_0,
1451   PREFIX_EVEX_0F72_REG_1,
1452   PREFIX_EVEX_0F72_REG_2,
1453   PREFIX_EVEX_0F72_REG_4,
1454   PREFIX_EVEX_0F72_REG_6,
1455   PREFIX_EVEX_0F73_REG_2,
1456   PREFIX_EVEX_0F73_REG_3,
1457   PREFIX_EVEX_0F73_REG_6,
1458   PREFIX_EVEX_0F73_REG_7,
1459   PREFIX_EVEX_0F74,
1460   PREFIX_EVEX_0F75,
1461   PREFIX_EVEX_0F76,
1462   PREFIX_EVEX_0F78,
1463   PREFIX_EVEX_0F79,
1464   PREFIX_EVEX_0F7A,
1465   PREFIX_EVEX_0F7B,
1466   PREFIX_EVEX_0F7E,
1467   PREFIX_EVEX_0F7F,
1468   PREFIX_EVEX_0FC2,
1469   PREFIX_EVEX_0FC4,
1470   PREFIX_EVEX_0FC5,
1471   PREFIX_EVEX_0FC6,
1472   PREFIX_EVEX_0FD1,
1473   PREFIX_EVEX_0FD2,
1474   PREFIX_EVEX_0FD3,
1475   PREFIX_EVEX_0FD4,
1476   PREFIX_EVEX_0FD5,
1477   PREFIX_EVEX_0FD6,
1478   PREFIX_EVEX_0FD8,
1479   PREFIX_EVEX_0FD9,
1480   PREFIX_EVEX_0FDA,
1481   PREFIX_EVEX_0FDB,
1482   PREFIX_EVEX_0FDC,
1483   PREFIX_EVEX_0FDD,
1484   PREFIX_EVEX_0FDE,
1485   PREFIX_EVEX_0FDF,
1486   PREFIX_EVEX_0FE0,
1487   PREFIX_EVEX_0FE1,
1488   PREFIX_EVEX_0FE2,
1489   PREFIX_EVEX_0FE3,
1490   PREFIX_EVEX_0FE4,
1491   PREFIX_EVEX_0FE5,
1492   PREFIX_EVEX_0FE6,
1493   PREFIX_EVEX_0FE7,
1494   PREFIX_EVEX_0FE8,
1495   PREFIX_EVEX_0FE9,
1496   PREFIX_EVEX_0FEA,
1497   PREFIX_EVEX_0FEB,
1498   PREFIX_EVEX_0FEC,
1499   PREFIX_EVEX_0FED,
1500   PREFIX_EVEX_0FEE,
1501   PREFIX_EVEX_0FEF,
1502   PREFIX_EVEX_0FF1,
1503   PREFIX_EVEX_0FF2,
1504   PREFIX_EVEX_0FF3,
1505   PREFIX_EVEX_0FF4,
1506   PREFIX_EVEX_0FF5,
1507   PREFIX_EVEX_0FF6,
1508   PREFIX_EVEX_0FF8,
1509   PREFIX_EVEX_0FF9,
1510   PREFIX_EVEX_0FFA,
1511   PREFIX_EVEX_0FFB,
1512   PREFIX_EVEX_0FFC,
1513   PREFIX_EVEX_0FFD,
1514   PREFIX_EVEX_0FFE,
1515   PREFIX_EVEX_0F3800,
1516   PREFIX_EVEX_0F3804,
1517   PREFIX_EVEX_0F380B,
1518   PREFIX_EVEX_0F380C,
1519   PREFIX_EVEX_0F380D,
1520   PREFIX_EVEX_0F3810,
1521   PREFIX_EVEX_0F3811,
1522   PREFIX_EVEX_0F3812,
1523   PREFIX_EVEX_0F3813,
1524   PREFIX_EVEX_0F3814,
1525   PREFIX_EVEX_0F3815,
1526   PREFIX_EVEX_0F3816,
1527   PREFIX_EVEX_0F3818,
1528   PREFIX_EVEX_0F3819,
1529   PREFIX_EVEX_0F381A,
1530   PREFIX_EVEX_0F381B,
1531   PREFIX_EVEX_0F381C,
1532   PREFIX_EVEX_0F381D,
1533   PREFIX_EVEX_0F381E,
1534   PREFIX_EVEX_0F381F,
1535   PREFIX_EVEX_0F3820,
1536   PREFIX_EVEX_0F3821,
1537   PREFIX_EVEX_0F3822,
1538   PREFIX_EVEX_0F3823,
1539   PREFIX_EVEX_0F3824,
1540   PREFIX_EVEX_0F3825,
1541   PREFIX_EVEX_0F3826,
1542   PREFIX_EVEX_0F3827,
1543   PREFIX_EVEX_0F3828,
1544   PREFIX_EVEX_0F3829,
1545   PREFIX_EVEX_0F382A,
1546   PREFIX_EVEX_0F382B,
1547   PREFIX_EVEX_0F382C,
1548   PREFIX_EVEX_0F382D,
1549   PREFIX_EVEX_0F3830,
1550   PREFIX_EVEX_0F3831,
1551   PREFIX_EVEX_0F3832,
1552   PREFIX_EVEX_0F3833,
1553   PREFIX_EVEX_0F3834,
1554   PREFIX_EVEX_0F3835,
1555   PREFIX_EVEX_0F3836,
1556   PREFIX_EVEX_0F3837,
1557   PREFIX_EVEX_0F3838,
1558   PREFIX_EVEX_0F3839,
1559   PREFIX_EVEX_0F383A,
1560   PREFIX_EVEX_0F383B,
1561   PREFIX_EVEX_0F383C,
1562   PREFIX_EVEX_0F383D,
1563   PREFIX_EVEX_0F383E,
1564   PREFIX_EVEX_0F383F,
1565   PREFIX_EVEX_0F3840,
1566   PREFIX_EVEX_0F3842,
1567   PREFIX_EVEX_0F3843,
1568   PREFIX_EVEX_0F3844,
1569   PREFIX_EVEX_0F3845,
1570   PREFIX_EVEX_0F3846,
1571   PREFIX_EVEX_0F3847,
1572   PREFIX_EVEX_0F384C,
1573   PREFIX_EVEX_0F384D,
1574   PREFIX_EVEX_0F384E,
1575   PREFIX_EVEX_0F384F,
1576   PREFIX_EVEX_0F3850,
1577   PREFIX_EVEX_0F3851,
1578   PREFIX_EVEX_0F3852,
1579   PREFIX_EVEX_0F3853,
1580   PREFIX_EVEX_0F3854,
1581   PREFIX_EVEX_0F3855,
1582   PREFIX_EVEX_0F3858,
1583   PREFIX_EVEX_0F3859,
1584   PREFIX_EVEX_0F385A,
1585   PREFIX_EVEX_0F385B,
1586   PREFIX_EVEX_0F3862,
1587   PREFIX_EVEX_0F3863,
1588   PREFIX_EVEX_0F3864,
1589   PREFIX_EVEX_0F3865,
1590   PREFIX_EVEX_0F3866,
1591   PREFIX_EVEX_0F3870,
1592   PREFIX_EVEX_0F3871,
1593   PREFIX_EVEX_0F3872,
1594   PREFIX_EVEX_0F3873,
1595   PREFIX_EVEX_0F3875,
1596   PREFIX_EVEX_0F3876,
1597   PREFIX_EVEX_0F3877,
1598   PREFIX_EVEX_0F3878,
1599   PREFIX_EVEX_0F3879,
1600   PREFIX_EVEX_0F387A,
1601   PREFIX_EVEX_0F387B,
1602   PREFIX_EVEX_0F387C,
1603   PREFIX_EVEX_0F387D,
1604   PREFIX_EVEX_0F387E,
1605   PREFIX_EVEX_0F387F,
1606   PREFIX_EVEX_0F3883,
1607   PREFIX_EVEX_0F3888,
1608   PREFIX_EVEX_0F3889,
1609   PREFIX_EVEX_0F388A,
1610   PREFIX_EVEX_0F388B,
1611   PREFIX_EVEX_0F388D,
1612   PREFIX_EVEX_0F388F,
1613   PREFIX_EVEX_0F3890,
1614   PREFIX_EVEX_0F3891,
1615   PREFIX_EVEX_0F3892,
1616   PREFIX_EVEX_0F3893,
1617   PREFIX_EVEX_0F3896,
1618   PREFIX_EVEX_0F3897,
1619   PREFIX_EVEX_0F3898,
1620   PREFIX_EVEX_0F3899,
1621   PREFIX_EVEX_0F389A,
1622   PREFIX_EVEX_0F389B,
1623   PREFIX_EVEX_0F389C,
1624   PREFIX_EVEX_0F389D,
1625   PREFIX_EVEX_0F389E,
1626   PREFIX_EVEX_0F389F,
1627   PREFIX_EVEX_0F38A0,
1628   PREFIX_EVEX_0F38A1,
1629   PREFIX_EVEX_0F38A2,
1630   PREFIX_EVEX_0F38A3,
1631   PREFIX_EVEX_0F38A6,
1632   PREFIX_EVEX_0F38A7,
1633   PREFIX_EVEX_0F38A8,
1634   PREFIX_EVEX_0F38A9,
1635   PREFIX_EVEX_0F38AA,
1636   PREFIX_EVEX_0F38AB,
1637   PREFIX_EVEX_0F38AC,
1638   PREFIX_EVEX_0F38AD,
1639   PREFIX_EVEX_0F38AE,
1640   PREFIX_EVEX_0F38AF,
1641   PREFIX_EVEX_0F38B4,
1642   PREFIX_EVEX_0F38B5,
1643   PREFIX_EVEX_0F38B6,
1644   PREFIX_EVEX_0F38B7,
1645   PREFIX_EVEX_0F38B8,
1646   PREFIX_EVEX_0F38B9,
1647   PREFIX_EVEX_0F38BA,
1648   PREFIX_EVEX_0F38BB,
1649   PREFIX_EVEX_0F38BC,
1650   PREFIX_EVEX_0F38BD,
1651   PREFIX_EVEX_0F38BE,
1652   PREFIX_EVEX_0F38BF,
1653   PREFIX_EVEX_0F38C4,
1654   PREFIX_EVEX_0F38C6_REG_1,
1655   PREFIX_EVEX_0F38C6_REG_2,
1656   PREFIX_EVEX_0F38C6_REG_5,
1657   PREFIX_EVEX_0F38C6_REG_6,
1658   PREFIX_EVEX_0F38C7_REG_1,
1659   PREFIX_EVEX_0F38C7_REG_2,
1660   PREFIX_EVEX_0F38C7_REG_5,
1661   PREFIX_EVEX_0F38C7_REG_6,
1662   PREFIX_EVEX_0F38C8,
1663   PREFIX_EVEX_0F38CA,
1664   PREFIX_EVEX_0F38CB,
1665   PREFIX_EVEX_0F38CC,
1666   PREFIX_EVEX_0F38CD,
1667   PREFIX_EVEX_0F38CF,
1668   PREFIX_EVEX_0F38DC,
1669   PREFIX_EVEX_0F38DD,
1670   PREFIX_EVEX_0F38DE,
1671   PREFIX_EVEX_0F38DF,
1672
1673   PREFIX_EVEX_0F3A00,
1674   PREFIX_EVEX_0F3A01,
1675   PREFIX_EVEX_0F3A03,
1676   PREFIX_EVEX_0F3A04,
1677   PREFIX_EVEX_0F3A05,
1678   PREFIX_EVEX_0F3A08,
1679   PREFIX_EVEX_0F3A09,
1680   PREFIX_EVEX_0F3A0A,
1681   PREFIX_EVEX_0F3A0B,
1682   PREFIX_EVEX_0F3A0F,
1683   PREFIX_EVEX_0F3A14,
1684   PREFIX_EVEX_0F3A15,
1685   PREFIX_EVEX_0F3A16,
1686   PREFIX_EVEX_0F3A17,
1687   PREFIX_EVEX_0F3A18,
1688   PREFIX_EVEX_0F3A19,
1689   PREFIX_EVEX_0F3A1A,
1690   PREFIX_EVEX_0F3A1B,
1691   PREFIX_EVEX_0F3A1D,
1692   PREFIX_EVEX_0F3A1E,
1693   PREFIX_EVEX_0F3A1F,
1694   PREFIX_EVEX_0F3A20,
1695   PREFIX_EVEX_0F3A21,
1696   PREFIX_EVEX_0F3A22,
1697   PREFIX_EVEX_0F3A23,
1698   PREFIX_EVEX_0F3A25,
1699   PREFIX_EVEX_0F3A26,
1700   PREFIX_EVEX_0F3A27,
1701   PREFIX_EVEX_0F3A38,
1702   PREFIX_EVEX_0F3A39,
1703   PREFIX_EVEX_0F3A3A,
1704   PREFIX_EVEX_0F3A3B,
1705   PREFIX_EVEX_0F3A3E,
1706   PREFIX_EVEX_0F3A3F,
1707   PREFIX_EVEX_0F3A42,
1708   PREFIX_EVEX_0F3A43,
1709   PREFIX_EVEX_0F3A44,
1710   PREFIX_EVEX_0F3A50,
1711   PREFIX_EVEX_0F3A51,
1712   PREFIX_EVEX_0F3A54,
1713   PREFIX_EVEX_0F3A55,
1714   PREFIX_EVEX_0F3A56,
1715   PREFIX_EVEX_0F3A57,
1716   PREFIX_EVEX_0F3A66,
1717   PREFIX_EVEX_0F3A67,
1718   PREFIX_EVEX_0F3A70,
1719   PREFIX_EVEX_0F3A71,
1720   PREFIX_EVEX_0F3A72,
1721   PREFIX_EVEX_0F3A73,
1722   PREFIX_EVEX_0F3ACE,
1723   PREFIX_EVEX_0F3ACF
1724 };
1725
1726 enum
1727 {
1728   X86_64_06 = 0,
1729   X86_64_07,
1730   X86_64_0D,
1731   X86_64_16,
1732   X86_64_17,
1733   X86_64_1E,
1734   X86_64_1F,
1735   X86_64_27,
1736   X86_64_2F,
1737   X86_64_37,
1738   X86_64_3F,
1739   X86_64_60,
1740   X86_64_61,
1741   X86_64_62,
1742   X86_64_63,
1743   X86_64_6D,
1744   X86_64_6F,
1745   X86_64_82,
1746   X86_64_9A,
1747   X86_64_C4,
1748   X86_64_C5,
1749   X86_64_CE,
1750   X86_64_D4,
1751   X86_64_D5,
1752   X86_64_E8,
1753   X86_64_E9,
1754   X86_64_EA,
1755   X86_64_0F01_REG_0,
1756   X86_64_0F01_REG_1,
1757   X86_64_0F01_REG_2,
1758   X86_64_0F01_REG_3
1759 };
1760
1761 enum
1762 {
1763   THREE_BYTE_0F38 = 0,
1764   THREE_BYTE_0F3A
1765 };
1766
1767 enum
1768 {
1769   XOP_08 = 0,
1770   XOP_09,
1771   XOP_0A
1772 };
1773
1774 enum
1775 {
1776   VEX_0F = 0,
1777   VEX_0F38,
1778   VEX_0F3A
1779 };
1780
1781 enum
1782 {
1783   EVEX_0F = 0,
1784   EVEX_0F38,
1785   EVEX_0F3A
1786 };
1787
1788 enum
1789 {
1790   VEX_LEN_0F10_P_1 = 0,
1791   VEX_LEN_0F10_P_3,
1792   VEX_LEN_0F11_P_1,
1793   VEX_LEN_0F11_P_3,
1794   VEX_LEN_0F12_P_0_M_0,
1795   VEX_LEN_0F12_P_0_M_1,
1796   VEX_LEN_0F12_P_2,
1797   VEX_LEN_0F13_M_0,
1798   VEX_LEN_0F16_P_0_M_0,
1799   VEX_LEN_0F16_P_0_M_1,
1800   VEX_LEN_0F16_P_2,
1801   VEX_LEN_0F17_M_0,
1802   VEX_LEN_0F2A_P_1,
1803   VEX_LEN_0F2A_P_3,
1804   VEX_LEN_0F2C_P_1,
1805   VEX_LEN_0F2C_P_3,
1806   VEX_LEN_0F2D_P_1,
1807   VEX_LEN_0F2D_P_3,
1808   VEX_LEN_0F2E_P_0,
1809   VEX_LEN_0F2E_P_2,
1810   VEX_LEN_0F2F_P_0,
1811   VEX_LEN_0F2F_P_2,
1812   VEX_LEN_0F41_P_0,
1813   VEX_LEN_0F41_P_2,
1814   VEX_LEN_0F42_P_0,
1815   VEX_LEN_0F42_P_2,
1816   VEX_LEN_0F44_P_0,
1817   VEX_LEN_0F44_P_2,
1818   VEX_LEN_0F45_P_0,
1819   VEX_LEN_0F45_P_2,
1820   VEX_LEN_0F46_P_0,
1821   VEX_LEN_0F46_P_2,
1822   VEX_LEN_0F47_P_0,
1823   VEX_LEN_0F47_P_2,
1824   VEX_LEN_0F4A_P_0,
1825   VEX_LEN_0F4A_P_2,
1826   VEX_LEN_0F4B_P_0,
1827   VEX_LEN_0F4B_P_2,
1828   VEX_LEN_0F51_P_1,
1829   VEX_LEN_0F51_P_3,
1830   VEX_LEN_0F52_P_1,
1831   VEX_LEN_0F53_P_1,
1832   VEX_LEN_0F58_P_1,
1833   VEX_LEN_0F58_P_3,
1834   VEX_LEN_0F59_P_1,
1835   VEX_LEN_0F59_P_3,
1836   VEX_LEN_0F5A_P_1,
1837   VEX_LEN_0F5A_P_3,
1838   VEX_LEN_0F5C_P_1,
1839   VEX_LEN_0F5C_P_3,
1840   VEX_LEN_0F5D_P_1,
1841   VEX_LEN_0F5D_P_3,
1842   VEX_LEN_0F5E_P_1,
1843   VEX_LEN_0F5E_P_3,
1844   VEX_LEN_0F5F_P_1,
1845   VEX_LEN_0F5F_P_3,
1846   VEX_LEN_0F6E_P_2,
1847   VEX_LEN_0F7E_P_1,
1848   VEX_LEN_0F7E_P_2,
1849   VEX_LEN_0F90_P_0,
1850   VEX_LEN_0F90_P_2,
1851   VEX_LEN_0F91_P_0,
1852   VEX_LEN_0F91_P_2,
1853   VEX_LEN_0F92_P_0,
1854   VEX_LEN_0F92_P_2,
1855   VEX_LEN_0F92_P_3,
1856   VEX_LEN_0F93_P_0,
1857   VEX_LEN_0F93_P_2,
1858   VEX_LEN_0F93_P_3,
1859   VEX_LEN_0F98_P_0,
1860   VEX_LEN_0F98_P_2,
1861   VEX_LEN_0F99_P_0,
1862   VEX_LEN_0F99_P_2,
1863   VEX_LEN_0FAE_R_2_M_0,
1864   VEX_LEN_0FAE_R_3_M_0,
1865   VEX_LEN_0FC2_P_1,
1866   VEX_LEN_0FC2_P_3,
1867   VEX_LEN_0FC4_P_2,
1868   VEX_LEN_0FC5_P_2,
1869   VEX_LEN_0FD6_P_2,
1870   VEX_LEN_0FF7_P_2,
1871   VEX_LEN_0F3816_P_2,
1872   VEX_LEN_0F3819_P_2,
1873   VEX_LEN_0F381A_P_2_M_0,
1874   VEX_LEN_0F3836_P_2,
1875   VEX_LEN_0F3841_P_2,
1876   VEX_LEN_0F385A_P_2_M_0,
1877   VEX_LEN_0F38DB_P_2,
1878   VEX_LEN_0F38F2_P_0,
1879   VEX_LEN_0F38F3_R_1_P_0,
1880   VEX_LEN_0F38F3_R_2_P_0,
1881   VEX_LEN_0F38F3_R_3_P_0,
1882   VEX_LEN_0F38F5_P_0,
1883   VEX_LEN_0F38F5_P_1,
1884   VEX_LEN_0F38F5_P_3,
1885   VEX_LEN_0F38F6_P_3,
1886   VEX_LEN_0F38F7_P_0,
1887   VEX_LEN_0F38F7_P_1,
1888   VEX_LEN_0F38F7_P_2,
1889   VEX_LEN_0F38F7_P_3,
1890   VEX_LEN_0F3A00_P_2,
1891   VEX_LEN_0F3A01_P_2,
1892   VEX_LEN_0F3A06_P_2,
1893   VEX_LEN_0F3A0A_P_2,
1894   VEX_LEN_0F3A0B_P_2,
1895   VEX_LEN_0F3A14_P_2,
1896   VEX_LEN_0F3A15_P_2,
1897   VEX_LEN_0F3A16_P_2,
1898   VEX_LEN_0F3A17_P_2,
1899   VEX_LEN_0F3A18_P_2,
1900   VEX_LEN_0F3A19_P_2,
1901   VEX_LEN_0F3A20_P_2,
1902   VEX_LEN_0F3A21_P_2,
1903   VEX_LEN_0F3A22_P_2,
1904   VEX_LEN_0F3A30_P_2,
1905   VEX_LEN_0F3A31_P_2,
1906   VEX_LEN_0F3A32_P_2,
1907   VEX_LEN_0F3A33_P_2,
1908   VEX_LEN_0F3A38_P_2,
1909   VEX_LEN_0F3A39_P_2,
1910   VEX_LEN_0F3A41_P_2,
1911   VEX_LEN_0F3A46_P_2,
1912   VEX_LEN_0F3A60_P_2,
1913   VEX_LEN_0F3A61_P_2,
1914   VEX_LEN_0F3A62_P_2,
1915   VEX_LEN_0F3A63_P_2,
1916   VEX_LEN_0F3A6A_P_2,
1917   VEX_LEN_0F3A6B_P_2,
1918   VEX_LEN_0F3A6E_P_2,
1919   VEX_LEN_0F3A6F_P_2,
1920   VEX_LEN_0F3A7A_P_2,
1921   VEX_LEN_0F3A7B_P_2,
1922   VEX_LEN_0F3A7E_P_2,
1923   VEX_LEN_0F3A7F_P_2,
1924   VEX_LEN_0F3ADF_P_2,
1925   VEX_LEN_0F3AF0_P_3,
1926   VEX_LEN_0FXOP_08_CC,
1927   VEX_LEN_0FXOP_08_CD,
1928   VEX_LEN_0FXOP_08_CE,
1929   VEX_LEN_0FXOP_08_CF,
1930   VEX_LEN_0FXOP_08_EC,
1931   VEX_LEN_0FXOP_08_ED,
1932   VEX_LEN_0FXOP_08_EE,
1933   VEX_LEN_0FXOP_08_EF,
1934   VEX_LEN_0FXOP_09_80,
1935   VEX_LEN_0FXOP_09_81
1936 };
1937
1938 enum
1939 {
1940   VEX_W_0F10_P_0 = 0,
1941   VEX_W_0F10_P_1,
1942   VEX_W_0F10_P_2,
1943   VEX_W_0F10_P_3,
1944   VEX_W_0F11_P_0,
1945   VEX_W_0F11_P_1,
1946   VEX_W_0F11_P_2,
1947   VEX_W_0F11_P_3,
1948   VEX_W_0F12_P_0_M_0,
1949   VEX_W_0F12_P_0_M_1,
1950   VEX_W_0F12_P_1,
1951   VEX_W_0F12_P_2,
1952   VEX_W_0F12_P_3,
1953   VEX_W_0F13_M_0,
1954   VEX_W_0F14,
1955   VEX_W_0F15,
1956   VEX_W_0F16_P_0_M_0,
1957   VEX_W_0F16_P_0_M_1,
1958   VEX_W_0F16_P_1,
1959   VEX_W_0F16_P_2,
1960   VEX_W_0F17_M_0,
1961   VEX_W_0F28,
1962   VEX_W_0F29,
1963   VEX_W_0F2B_M_0,
1964   VEX_W_0F2E_P_0,
1965   VEX_W_0F2E_P_2,
1966   VEX_W_0F2F_P_0,
1967   VEX_W_0F2F_P_2,
1968   VEX_W_0F41_P_0_LEN_1,
1969   VEX_W_0F41_P_2_LEN_1,
1970   VEX_W_0F42_P_0_LEN_1,
1971   VEX_W_0F42_P_2_LEN_1,
1972   VEX_W_0F44_P_0_LEN_0,
1973   VEX_W_0F44_P_2_LEN_0,
1974   VEX_W_0F45_P_0_LEN_1,
1975   VEX_W_0F45_P_2_LEN_1,
1976   VEX_W_0F46_P_0_LEN_1,
1977   VEX_W_0F46_P_2_LEN_1,
1978   VEX_W_0F47_P_0_LEN_1,
1979   VEX_W_0F47_P_2_LEN_1,
1980   VEX_W_0F4A_P_0_LEN_1,
1981   VEX_W_0F4A_P_2_LEN_1,
1982   VEX_W_0F4B_P_0_LEN_1,
1983   VEX_W_0F4B_P_2_LEN_1,
1984   VEX_W_0F50_M_0,
1985   VEX_W_0F51_P_0,
1986   VEX_W_0F51_P_1,
1987   VEX_W_0F51_P_2,
1988   VEX_W_0F51_P_3,
1989   VEX_W_0F52_P_0,
1990   VEX_W_0F52_P_1,
1991   VEX_W_0F53_P_0,
1992   VEX_W_0F53_P_1,
1993   VEX_W_0F58_P_0,
1994   VEX_W_0F58_P_1,
1995   VEX_W_0F58_P_2,
1996   VEX_W_0F58_P_3,
1997   VEX_W_0F59_P_0,
1998   VEX_W_0F59_P_1,
1999   VEX_W_0F59_P_2,
2000   VEX_W_0F59_P_3,
2001   VEX_W_0F5A_P_0,
2002   VEX_W_0F5A_P_1,
2003   VEX_W_0F5A_P_3,
2004   VEX_W_0F5B_P_0,
2005   VEX_W_0F5B_P_1,
2006   VEX_W_0F5B_P_2,
2007   VEX_W_0F5C_P_0,
2008   VEX_W_0F5C_P_1,
2009   VEX_W_0F5C_P_2,
2010   VEX_W_0F5C_P_3,
2011   VEX_W_0F5D_P_0,
2012   VEX_W_0F5D_P_1,
2013   VEX_W_0F5D_P_2,
2014   VEX_W_0F5D_P_3,
2015   VEX_W_0F5E_P_0,
2016   VEX_W_0F5E_P_1,
2017   VEX_W_0F5E_P_2,
2018   VEX_W_0F5E_P_3,
2019   VEX_W_0F5F_P_0,
2020   VEX_W_0F5F_P_1,
2021   VEX_W_0F5F_P_2,
2022   VEX_W_0F5F_P_3,
2023   VEX_W_0F60_P_2,
2024   VEX_W_0F61_P_2,
2025   VEX_W_0F62_P_2,
2026   VEX_W_0F63_P_2,
2027   VEX_W_0F64_P_2,
2028   VEX_W_0F65_P_2,
2029   VEX_W_0F66_P_2,
2030   VEX_W_0F67_P_2,
2031   VEX_W_0F68_P_2,
2032   VEX_W_0F69_P_2,
2033   VEX_W_0F6A_P_2,
2034   VEX_W_0F6B_P_2,
2035   VEX_W_0F6C_P_2,
2036   VEX_W_0F6D_P_2,
2037   VEX_W_0F6F_P_1,
2038   VEX_W_0F6F_P_2,
2039   VEX_W_0F70_P_1,
2040   VEX_W_0F70_P_2,
2041   VEX_W_0F70_P_3,
2042   VEX_W_0F71_R_2_P_2,
2043   VEX_W_0F71_R_4_P_2,
2044   VEX_W_0F71_R_6_P_2,
2045   VEX_W_0F72_R_2_P_2,
2046   VEX_W_0F72_R_4_P_2,
2047   VEX_W_0F72_R_6_P_2,
2048   VEX_W_0F73_R_2_P_2,
2049   VEX_W_0F73_R_3_P_2,
2050   VEX_W_0F73_R_6_P_2,
2051   VEX_W_0F73_R_7_P_2,
2052   VEX_W_0F74_P_2,
2053   VEX_W_0F75_P_2,
2054   VEX_W_0F76_P_2,
2055   VEX_W_0F77_P_0,
2056   VEX_W_0F7C_P_2,
2057   VEX_W_0F7C_P_3,
2058   VEX_W_0F7D_P_2,
2059   VEX_W_0F7D_P_3,
2060   VEX_W_0F7E_P_1,
2061   VEX_W_0F7F_P_1,
2062   VEX_W_0F7F_P_2,
2063   VEX_W_0F90_P_0_LEN_0,
2064   VEX_W_0F90_P_2_LEN_0,
2065   VEX_W_0F91_P_0_LEN_0,
2066   VEX_W_0F91_P_2_LEN_0,
2067   VEX_W_0F92_P_0_LEN_0,
2068   VEX_W_0F92_P_2_LEN_0,
2069   VEX_W_0F92_P_3_LEN_0,
2070   VEX_W_0F93_P_0_LEN_0,
2071   VEX_W_0F93_P_2_LEN_0,
2072   VEX_W_0F93_P_3_LEN_0,
2073   VEX_W_0F98_P_0_LEN_0,
2074   VEX_W_0F98_P_2_LEN_0,
2075   VEX_W_0F99_P_0_LEN_0,
2076   VEX_W_0F99_P_2_LEN_0,
2077   VEX_W_0FAE_R_2_M_0,
2078   VEX_W_0FAE_R_3_M_0,
2079   VEX_W_0FC2_P_0,
2080   VEX_W_0FC2_P_1,
2081   VEX_W_0FC2_P_2,
2082   VEX_W_0FC2_P_3,
2083   VEX_W_0FC4_P_2,
2084   VEX_W_0FC5_P_2,
2085   VEX_W_0FD0_P_2,
2086   VEX_W_0FD0_P_3,
2087   VEX_W_0FD1_P_2,
2088   VEX_W_0FD2_P_2,
2089   VEX_W_0FD3_P_2,
2090   VEX_W_0FD4_P_2,
2091   VEX_W_0FD5_P_2,
2092   VEX_W_0FD6_P_2,
2093   VEX_W_0FD7_P_2_M_1,
2094   VEX_W_0FD8_P_2,
2095   VEX_W_0FD9_P_2,
2096   VEX_W_0FDA_P_2,
2097   VEX_W_0FDB_P_2,
2098   VEX_W_0FDC_P_2,
2099   VEX_W_0FDD_P_2,
2100   VEX_W_0FDE_P_2,
2101   VEX_W_0FDF_P_2,
2102   VEX_W_0FE0_P_2,
2103   VEX_W_0FE1_P_2,
2104   VEX_W_0FE2_P_2,
2105   VEX_W_0FE3_P_2,
2106   VEX_W_0FE4_P_2,
2107   VEX_W_0FE5_P_2,
2108   VEX_W_0FE6_P_1,
2109   VEX_W_0FE6_P_2,
2110   VEX_W_0FE6_P_3,
2111   VEX_W_0FE7_P_2_M_0,
2112   VEX_W_0FE8_P_2,
2113   VEX_W_0FE9_P_2,
2114   VEX_W_0FEA_P_2,
2115   VEX_W_0FEB_P_2,
2116   VEX_W_0FEC_P_2,
2117   VEX_W_0FED_P_2,
2118   VEX_W_0FEE_P_2,
2119   VEX_W_0FEF_P_2,
2120   VEX_W_0FF0_P_3_M_0,
2121   VEX_W_0FF1_P_2,
2122   VEX_W_0FF2_P_2,
2123   VEX_W_0FF3_P_2,
2124   VEX_W_0FF4_P_2,
2125   VEX_W_0FF5_P_2,
2126   VEX_W_0FF6_P_2,
2127   VEX_W_0FF7_P_2,
2128   VEX_W_0FF8_P_2,
2129   VEX_W_0FF9_P_2,
2130   VEX_W_0FFA_P_2,
2131   VEX_W_0FFB_P_2,
2132   VEX_W_0FFC_P_2,
2133   VEX_W_0FFD_P_2,
2134   VEX_W_0FFE_P_2,
2135   VEX_W_0F3800_P_2,
2136   VEX_W_0F3801_P_2,
2137   VEX_W_0F3802_P_2,
2138   VEX_W_0F3803_P_2,
2139   VEX_W_0F3804_P_2,
2140   VEX_W_0F3805_P_2,
2141   VEX_W_0F3806_P_2,
2142   VEX_W_0F3807_P_2,
2143   VEX_W_0F3808_P_2,
2144   VEX_W_0F3809_P_2,
2145   VEX_W_0F380A_P_2,
2146   VEX_W_0F380B_P_2,
2147   VEX_W_0F380C_P_2,
2148   VEX_W_0F380D_P_2,
2149   VEX_W_0F380E_P_2,
2150   VEX_W_0F380F_P_2,
2151   VEX_W_0F3816_P_2,
2152   VEX_W_0F3817_P_2,
2153   VEX_W_0F3818_P_2,
2154   VEX_W_0F3819_P_2,
2155   VEX_W_0F381A_P_2_M_0,
2156   VEX_W_0F381C_P_2,
2157   VEX_W_0F381D_P_2,
2158   VEX_W_0F381E_P_2,
2159   VEX_W_0F3820_P_2,
2160   VEX_W_0F3821_P_2,
2161   VEX_W_0F3822_P_2,
2162   VEX_W_0F3823_P_2,
2163   VEX_W_0F3824_P_2,
2164   VEX_W_0F3825_P_2,
2165   VEX_W_0F3828_P_2,
2166   VEX_W_0F3829_P_2,
2167   VEX_W_0F382A_P_2_M_0,
2168   VEX_W_0F382B_P_2,
2169   VEX_W_0F382C_P_2_M_0,
2170   VEX_W_0F382D_P_2_M_0,
2171   VEX_W_0F382E_P_2_M_0,
2172   VEX_W_0F382F_P_2_M_0,
2173   VEX_W_0F3830_P_2,
2174   VEX_W_0F3831_P_2,
2175   VEX_W_0F3832_P_2,
2176   VEX_W_0F3833_P_2,
2177   VEX_W_0F3834_P_2,
2178   VEX_W_0F3835_P_2,
2179   VEX_W_0F3836_P_2,
2180   VEX_W_0F3837_P_2,
2181   VEX_W_0F3838_P_2,
2182   VEX_W_0F3839_P_2,
2183   VEX_W_0F383A_P_2,
2184   VEX_W_0F383B_P_2,
2185   VEX_W_0F383C_P_2,
2186   VEX_W_0F383D_P_2,
2187   VEX_W_0F383E_P_2,
2188   VEX_W_0F383F_P_2,
2189   VEX_W_0F3840_P_2,
2190   VEX_W_0F3841_P_2,
2191   VEX_W_0F3846_P_2,
2192   VEX_W_0F3858_P_2,
2193   VEX_W_0F3859_P_2,
2194   VEX_W_0F385A_P_2_M_0,
2195   VEX_W_0F3878_P_2,
2196   VEX_W_0F3879_P_2,
2197   VEX_W_0F38CF_P_2,
2198   VEX_W_0F38DB_P_2,
2199   VEX_W_0F3A00_P_2,
2200   VEX_W_0F3A01_P_2,
2201   VEX_W_0F3A02_P_2,
2202   VEX_W_0F3A04_P_2,
2203   VEX_W_0F3A05_P_2,
2204   VEX_W_0F3A06_P_2,
2205   VEX_W_0F3A08_P_2,
2206   VEX_W_0F3A09_P_2,
2207   VEX_W_0F3A0A_P_2,
2208   VEX_W_0F3A0B_P_2,
2209   VEX_W_0F3A0C_P_2,
2210   VEX_W_0F3A0D_P_2,
2211   VEX_W_0F3A0E_P_2,
2212   VEX_W_0F3A0F_P_2,
2213   VEX_W_0F3A14_P_2,
2214   VEX_W_0F3A15_P_2,
2215   VEX_W_0F3A18_P_2,
2216   VEX_W_0F3A19_P_2,
2217   VEX_W_0F3A20_P_2,
2218   VEX_W_0F3A21_P_2,
2219   VEX_W_0F3A30_P_2_LEN_0,
2220   VEX_W_0F3A31_P_2_LEN_0,
2221   VEX_W_0F3A32_P_2_LEN_0,
2222   VEX_W_0F3A33_P_2_LEN_0,
2223   VEX_W_0F3A38_P_2,
2224   VEX_W_0F3A39_P_2,
2225   VEX_W_0F3A40_P_2,
2226   VEX_W_0F3A41_P_2,
2227   VEX_W_0F3A42_P_2,
2228   VEX_W_0F3A46_P_2,
2229   VEX_W_0F3A48_P_2,
2230   VEX_W_0F3A49_P_2,
2231   VEX_W_0F3A4A_P_2,
2232   VEX_W_0F3A4B_P_2,
2233   VEX_W_0F3A4C_P_2,
2234   VEX_W_0F3A62_P_2,
2235   VEX_W_0F3A63_P_2,
2236   VEX_W_0F3ACE_P_2,
2237   VEX_W_0F3ACF_P_2,
2238   VEX_W_0F3ADF_P_2,
2239
2240   EVEX_W_0F10_P_0,
2241   EVEX_W_0F10_P_1_M_0,
2242   EVEX_W_0F10_P_1_M_1,
2243   EVEX_W_0F10_P_2,
2244   EVEX_W_0F10_P_3_M_0,
2245   EVEX_W_0F10_P_3_M_1,
2246   EVEX_W_0F11_P_0,
2247   EVEX_W_0F11_P_1_M_0,
2248   EVEX_W_0F11_P_1_M_1,
2249   EVEX_W_0F11_P_2,
2250   EVEX_W_0F11_P_3_M_0,
2251   EVEX_W_0F11_P_3_M_1,
2252   EVEX_W_0F12_P_0_M_0,
2253   EVEX_W_0F12_P_0_M_1,
2254   EVEX_W_0F12_P_1,
2255   EVEX_W_0F12_P_2,
2256   EVEX_W_0F12_P_3,
2257   EVEX_W_0F13_P_0,
2258   EVEX_W_0F13_P_2,
2259   EVEX_W_0F14_P_0,
2260   EVEX_W_0F14_P_2,
2261   EVEX_W_0F15_P_0,
2262   EVEX_W_0F15_P_2,
2263   EVEX_W_0F16_P_0_M_0,
2264   EVEX_W_0F16_P_0_M_1,
2265   EVEX_W_0F16_P_1,
2266   EVEX_W_0F16_P_2,
2267   EVEX_W_0F17_P_0,
2268   EVEX_W_0F17_P_2,
2269   EVEX_W_0F28_P_0,
2270   EVEX_W_0F28_P_2,
2271   EVEX_W_0F29_P_0,
2272   EVEX_W_0F29_P_2,
2273   EVEX_W_0F2A_P_1,
2274   EVEX_W_0F2A_P_3,
2275   EVEX_W_0F2B_P_0,
2276   EVEX_W_0F2B_P_2,
2277   EVEX_W_0F2E_P_0,
2278   EVEX_W_0F2E_P_2,
2279   EVEX_W_0F2F_P_0,
2280   EVEX_W_0F2F_P_2,
2281   EVEX_W_0F51_P_0,
2282   EVEX_W_0F51_P_1,
2283   EVEX_W_0F51_P_2,
2284   EVEX_W_0F51_P_3,
2285   EVEX_W_0F54_P_0,
2286   EVEX_W_0F54_P_2,
2287   EVEX_W_0F55_P_0,
2288   EVEX_W_0F55_P_2,
2289   EVEX_W_0F56_P_0,
2290   EVEX_W_0F56_P_2,
2291   EVEX_W_0F57_P_0,
2292   EVEX_W_0F57_P_2,
2293   EVEX_W_0F58_P_0,
2294   EVEX_W_0F58_P_1,
2295   EVEX_W_0F58_P_2,
2296   EVEX_W_0F58_P_3,
2297   EVEX_W_0F59_P_0,
2298   EVEX_W_0F59_P_1,
2299   EVEX_W_0F59_P_2,
2300   EVEX_W_0F59_P_3,
2301   EVEX_W_0F5A_P_0,
2302   EVEX_W_0F5A_P_1,
2303   EVEX_W_0F5A_P_2,
2304   EVEX_W_0F5A_P_3,
2305   EVEX_W_0F5B_P_0,
2306   EVEX_W_0F5B_P_1,
2307   EVEX_W_0F5B_P_2,
2308   EVEX_W_0F5C_P_0,
2309   EVEX_W_0F5C_P_1,
2310   EVEX_W_0F5C_P_2,
2311   EVEX_W_0F5C_P_3,
2312   EVEX_W_0F5D_P_0,
2313   EVEX_W_0F5D_P_1,
2314   EVEX_W_0F5D_P_2,
2315   EVEX_W_0F5D_P_3,
2316   EVEX_W_0F5E_P_0,
2317   EVEX_W_0F5E_P_1,
2318   EVEX_W_0F5E_P_2,
2319   EVEX_W_0F5E_P_3,
2320   EVEX_W_0F5F_P_0,
2321   EVEX_W_0F5F_P_1,
2322   EVEX_W_0F5F_P_2,
2323   EVEX_W_0F5F_P_3,
2324   EVEX_W_0F62_P_2,
2325   EVEX_W_0F66_P_2,
2326   EVEX_W_0F6A_P_2,
2327   EVEX_W_0F6B_P_2,
2328   EVEX_W_0F6C_P_2,
2329   EVEX_W_0F6D_P_2,
2330   EVEX_W_0F6E_P_2,
2331   EVEX_W_0F6F_P_1,
2332   EVEX_W_0F6F_P_2,
2333   EVEX_W_0F6F_P_3,
2334   EVEX_W_0F70_P_2,
2335   EVEX_W_0F72_R_2_P_2,
2336   EVEX_W_0F72_R_6_P_2,
2337   EVEX_W_0F73_R_2_P_2,
2338   EVEX_W_0F73_R_6_P_2,
2339   EVEX_W_0F76_P_2,
2340   EVEX_W_0F78_P_0,
2341   EVEX_W_0F78_P_2,
2342   EVEX_W_0F79_P_0,
2343   EVEX_W_0F79_P_2,
2344   EVEX_W_0F7A_P_1,
2345   EVEX_W_0F7A_P_2,
2346   EVEX_W_0F7A_P_3,
2347   EVEX_W_0F7B_P_1,
2348   EVEX_W_0F7B_P_2,
2349   EVEX_W_0F7B_P_3,
2350   EVEX_W_0F7E_P_1,
2351   EVEX_W_0F7E_P_2,
2352   EVEX_W_0F7F_P_1,
2353   EVEX_W_0F7F_P_2,
2354   EVEX_W_0F7F_P_3,
2355   EVEX_W_0FC2_P_0,
2356   EVEX_W_0FC2_P_1,
2357   EVEX_W_0FC2_P_2,
2358   EVEX_W_0FC2_P_3,
2359   EVEX_W_0FC6_P_0,
2360   EVEX_W_0FC6_P_2,
2361   EVEX_W_0FD2_P_2,
2362   EVEX_W_0FD3_P_2,
2363   EVEX_W_0FD4_P_2,
2364   EVEX_W_0FD6_P_2,
2365   EVEX_W_0FE6_P_1,
2366   EVEX_W_0FE6_P_2,
2367   EVEX_W_0FE6_P_3,
2368   EVEX_W_0FE7_P_2,
2369   EVEX_W_0FF2_P_2,
2370   EVEX_W_0FF3_P_2,
2371   EVEX_W_0FF4_P_2,
2372   EVEX_W_0FFA_P_2,
2373   EVEX_W_0FFB_P_2,
2374   EVEX_W_0FFE_P_2,
2375   EVEX_W_0F380C_P_2,
2376   EVEX_W_0F380D_P_2,
2377   EVEX_W_0F3810_P_1,
2378   EVEX_W_0F3810_P_2,
2379   EVEX_W_0F3811_P_1,
2380   EVEX_W_0F3811_P_2,
2381   EVEX_W_0F3812_P_1,
2382   EVEX_W_0F3812_P_2,
2383   EVEX_W_0F3813_P_1,
2384   EVEX_W_0F3813_P_2,
2385   EVEX_W_0F3814_P_1,
2386   EVEX_W_0F3815_P_1,
2387   EVEX_W_0F3818_P_2,
2388   EVEX_W_0F3819_P_2,
2389   EVEX_W_0F381A_P_2,
2390   EVEX_W_0F381B_P_2,
2391   EVEX_W_0F381E_P_2,
2392   EVEX_W_0F381F_P_2,
2393   EVEX_W_0F3820_P_1,
2394   EVEX_W_0F3821_P_1,
2395   EVEX_W_0F3822_P_1,
2396   EVEX_W_0F3823_P_1,
2397   EVEX_W_0F3824_P_1,
2398   EVEX_W_0F3825_P_1,
2399   EVEX_W_0F3825_P_2,
2400   EVEX_W_0F3826_P_1,
2401   EVEX_W_0F3826_P_2,
2402   EVEX_W_0F3828_P_1,
2403   EVEX_W_0F3828_P_2,
2404   EVEX_W_0F3829_P_1,
2405   EVEX_W_0F3829_P_2,
2406   EVEX_W_0F382A_P_1,
2407   EVEX_W_0F382A_P_2,
2408   EVEX_W_0F382B_P_2,
2409   EVEX_W_0F3830_P_1,
2410   EVEX_W_0F3831_P_1,
2411   EVEX_W_0F3832_P_1,
2412   EVEX_W_0F3833_P_1,
2413   EVEX_W_0F3834_P_1,
2414   EVEX_W_0F3835_P_1,
2415   EVEX_W_0F3835_P_2,
2416   EVEX_W_0F3837_P_2,
2417   EVEX_W_0F3838_P_1,
2418   EVEX_W_0F3839_P_1,
2419   EVEX_W_0F383A_P_1,
2420   EVEX_W_0F3840_P_2,
2421   EVEX_W_0F3854_P_2,
2422   EVEX_W_0F3855_P_2,
2423   EVEX_W_0F3858_P_2,
2424   EVEX_W_0F3859_P_2,
2425   EVEX_W_0F385A_P_2,
2426   EVEX_W_0F385B_P_2,
2427   EVEX_W_0F3862_P_2,
2428   EVEX_W_0F3863_P_2,
2429   EVEX_W_0F3866_P_2,
2430   EVEX_W_0F3870_P_2,
2431   EVEX_W_0F3871_P_2,
2432   EVEX_W_0F3872_P_2,
2433   EVEX_W_0F3873_P_2,
2434   EVEX_W_0F3875_P_2,
2435   EVEX_W_0F3878_P_2,
2436   EVEX_W_0F3879_P_2,
2437   EVEX_W_0F387A_P_2,
2438   EVEX_W_0F387B_P_2,
2439   EVEX_W_0F387D_P_2,
2440   EVEX_W_0F3883_P_2,
2441   EVEX_W_0F388D_P_2,
2442   EVEX_W_0F3891_P_2,
2443   EVEX_W_0F3893_P_2,
2444   EVEX_W_0F38A1_P_2,
2445   EVEX_W_0F38A3_P_2,
2446   EVEX_W_0F38C7_R_1_P_2,
2447   EVEX_W_0F38C7_R_2_P_2,
2448   EVEX_W_0F38C7_R_5_P_2,
2449   EVEX_W_0F38C7_R_6_P_2,
2450
2451   EVEX_W_0F3A00_P_2,
2452   EVEX_W_0F3A01_P_2,
2453   EVEX_W_0F3A04_P_2,
2454   EVEX_W_0F3A05_P_2,
2455   EVEX_W_0F3A08_P_2,
2456   EVEX_W_0F3A09_P_2,
2457   EVEX_W_0F3A0A_P_2,
2458   EVEX_W_0F3A0B_P_2,
2459   EVEX_W_0F3A16_P_2,
2460   EVEX_W_0F3A18_P_2,
2461   EVEX_W_0F3A19_P_2,
2462   EVEX_W_0F3A1A_P_2,
2463   EVEX_W_0F3A1B_P_2,
2464   EVEX_W_0F3A1D_P_2,
2465   EVEX_W_0F3A21_P_2,
2466   EVEX_W_0F3A22_P_2,
2467   EVEX_W_0F3A23_P_2,
2468   EVEX_W_0F3A38_P_2,
2469   EVEX_W_0F3A39_P_2,
2470   EVEX_W_0F3A3A_P_2,
2471   EVEX_W_0F3A3B_P_2,
2472   EVEX_W_0F3A3E_P_2,
2473   EVEX_W_0F3A3F_P_2,
2474   EVEX_W_0F3A42_P_2,
2475   EVEX_W_0F3A43_P_2,
2476   EVEX_W_0F3A50_P_2,
2477   EVEX_W_0F3A51_P_2,
2478   EVEX_W_0F3A56_P_2,
2479   EVEX_W_0F3A57_P_2,
2480   EVEX_W_0F3A66_P_2,
2481   EVEX_W_0F3A67_P_2,
2482   EVEX_W_0F3A70_P_2,
2483   EVEX_W_0F3A71_P_2,
2484   EVEX_W_0F3A72_P_2,
2485   EVEX_W_0F3A73_P_2,
2486   EVEX_W_0F3ACE_P_2,
2487   EVEX_W_0F3ACF_P_2
2488 };
2489
2490 typedef void (*op_rtn) (int bytemode, int sizeflag);
2491
2492 struct dis386 {
2493   const char *name;
2494   struct
2495     {
2496       op_rtn rtn;
2497       int bytemode;
2498     } op[MAX_OPERANDS];
2499   unsigned int prefix_requirement;
2500 };
2501
2502 /* Upper case letters in the instruction names here are macros.
2503    'A' => print 'b' if no register operands or suffix_always is true
2504    'B' => print 'b' if suffix_always is true
2505    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2506           size prefix
2507    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2508           suffix_always is true
2509    'E' => print 'e' if 32-bit form of jcxz
2510    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2511    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2512    'H' => print ",pt" or ",pn" branch hint
2513    'I' => honor following macro letter even in Intel mode (implemented only
2514           for some of the macro letters)
2515    'J' => print 'l'
2516    'K' => print 'd' or 'q' if rex prefix is present.
2517    'L' => print 'l' if suffix_always is true
2518    'M' => print 'r' if intel_mnemonic is false.
2519    'N' => print 'n' if instruction has no wait "prefix"
2520    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2521    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2522           or suffix_always is true.  print 'q' if rex prefix is present.
2523    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2524           is true
2525    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2526    'S' => print 'w', 'l' or 'q' if suffix_always is true
2527    'T' => print 'q' in 64bit mode if instruction has no operand size
2528           prefix and behave as 'P' otherwise
2529    'U' => print 'q' in 64bit mode if instruction has no operand size
2530           prefix and behave as 'Q' otherwise
2531    'V' => print 'q' in 64bit mode if instruction has no operand size
2532           prefix and behave as 'S' otherwise
2533    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2534    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2535    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2536           suffix_always is true.
2537    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2538    '!' => change condition from true to false or from false to true.
2539    '%' => add 1 upper case letter to the macro.
2540    '^' => print 'w' or 'l' depending on operand size prefix or
2541           suffix_always is true (lcall/ljmp).
2542    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2543           on operand size prefix.
2544    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2545           has no operand size prefix for AMD64 ISA, behave as 'P'
2546           otherwise
2547
2548    2 upper case letter macros:
2549    "XY" => print 'x' or 'y' if suffix_always is true or no register
2550            operands and no broadcast.
2551    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2552            register operands and no broadcast.
2553    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2554    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2555            or suffix_always is true
2556    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2557    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2558    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2559    "LW" => print 'd', 'q' depending on the VEX.W bit
2560    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2561            an operand size prefix, or suffix_always is true.  print
2562            'q' if rex prefix is present.
2563
2564    Many of the above letters print nothing in Intel mode.  See "putop"
2565    for the details.
2566
2567    Braces '{' and '}', and vertical bars '|', indicate alternative
2568    mnemonic strings for AT&T and Intel.  */
2569
2570 static const struct dis386 dis386[] = {
2571   /* 00 */
2572   { "addB",             { Ebh1, Gb }, 0 },
2573   { "addS",             { Evh1, Gv }, 0 },
2574   { "addB",             { Gb, EbS }, 0 },
2575   { "addS",             { Gv, EvS }, 0 },
2576   { "addB",             { AL, Ib }, 0 },
2577   { "addS",             { eAX, Iv }, 0 },
2578   { X86_64_TABLE (X86_64_06) },
2579   { X86_64_TABLE (X86_64_07) },
2580   /* 08 */
2581   { "orB",              { Ebh1, Gb }, 0 },
2582   { "orS",              { Evh1, Gv }, 0 },
2583   { "orB",              { Gb, EbS }, 0 },
2584   { "orS",              { Gv, EvS }, 0 },
2585   { "orB",              { AL, Ib }, 0 },
2586   { "orS",              { eAX, Iv }, 0 },
2587   { X86_64_TABLE (X86_64_0D) },
2588   { Bad_Opcode },       /* 0x0f extended opcode escape */
2589   /* 10 */
2590   { "adcB",             { Ebh1, Gb }, 0 },
2591   { "adcS",             { Evh1, Gv }, 0 },
2592   { "adcB",             { Gb, EbS }, 0 },
2593   { "adcS",             { Gv, EvS }, 0 },
2594   { "adcB",             { AL, Ib }, 0 },
2595   { "adcS",             { eAX, Iv }, 0 },
2596   { X86_64_TABLE (X86_64_16) },
2597   { X86_64_TABLE (X86_64_17) },
2598   /* 18 */
2599   { "sbbB",             { Ebh1, Gb }, 0 },
2600   { "sbbS",             { Evh1, Gv }, 0 },
2601   { "sbbB",             { Gb, EbS }, 0 },
2602   { "sbbS",             { Gv, EvS }, 0 },
2603   { "sbbB",             { AL, Ib }, 0 },
2604   { "sbbS",             { eAX, Iv }, 0 },
2605   { X86_64_TABLE (X86_64_1E) },
2606   { X86_64_TABLE (X86_64_1F) },
2607   /* 20 */
2608   { "andB",             { Ebh1, Gb }, 0 },
2609   { "andS",             { Evh1, Gv }, 0 },
2610   { "andB",             { Gb, EbS }, 0 },
2611   { "andS",             { Gv, EvS }, 0 },
2612   { "andB",             { AL, Ib }, 0 },
2613   { "andS",             { eAX, Iv }, 0 },
2614   { Bad_Opcode },       /* SEG ES prefix */
2615   { X86_64_TABLE (X86_64_27) },
2616   /* 28 */
2617   { "subB",             { Ebh1, Gb }, 0 },
2618   { "subS",             { Evh1, Gv }, 0 },
2619   { "subB",             { Gb, EbS }, 0 },
2620   { "subS",             { Gv, EvS }, 0 },
2621   { "subB",             { AL, Ib }, 0 },
2622   { "subS",             { eAX, Iv }, 0 },
2623   { Bad_Opcode },       /* SEG CS prefix */
2624   { X86_64_TABLE (X86_64_2F) },
2625   /* 30 */
2626   { "xorB",             { Ebh1, Gb }, 0 },
2627   { "xorS",             { Evh1, Gv }, 0 },
2628   { "xorB",             { Gb, EbS }, 0 },
2629   { "xorS",             { Gv, EvS }, 0 },
2630   { "xorB",             { AL, Ib }, 0 },
2631   { "xorS",             { eAX, Iv }, 0 },
2632   { Bad_Opcode },       /* SEG SS prefix */
2633   { X86_64_TABLE (X86_64_37) },
2634   /* 38 */
2635   { "cmpB",             { Eb, Gb }, 0 },
2636   { "cmpS",             { Ev, Gv }, 0 },
2637   { "cmpB",             { Gb, EbS }, 0 },
2638   { "cmpS",             { Gv, EvS }, 0 },
2639   { "cmpB",             { AL, Ib }, 0 },
2640   { "cmpS",             { eAX, Iv }, 0 },
2641   { Bad_Opcode },       /* SEG DS prefix */
2642   { X86_64_TABLE (X86_64_3F) },
2643   /* 40 */
2644   { "inc{S|}",          { RMeAX }, 0 },
2645   { "inc{S|}",          { RMeCX }, 0 },
2646   { "inc{S|}",          { RMeDX }, 0 },
2647   { "inc{S|}",          { RMeBX }, 0 },
2648   { "inc{S|}",          { RMeSP }, 0 },
2649   { "inc{S|}",          { RMeBP }, 0 },
2650   { "inc{S|}",          { RMeSI }, 0 },
2651   { "inc{S|}",          { RMeDI }, 0 },
2652   /* 48 */
2653   { "dec{S|}",          { RMeAX }, 0 },
2654   { "dec{S|}",          { RMeCX }, 0 },
2655   { "dec{S|}",          { RMeDX }, 0 },
2656   { "dec{S|}",          { RMeBX }, 0 },
2657   { "dec{S|}",          { RMeSP }, 0 },
2658   { "dec{S|}",          { RMeBP }, 0 },
2659   { "dec{S|}",          { RMeSI }, 0 },
2660   { "dec{S|}",          { RMeDI }, 0 },
2661   /* 50 */
2662   { "pushV",            { RMrAX }, 0 },
2663   { "pushV",            { RMrCX }, 0 },
2664   { "pushV",            { RMrDX }, 0 },
2665   { "pushV",            { RMrBX }, 0 },
2666   { "pushV",            { RMrSP }, 0 },
2667   { "pushV",            { RMrBP }, 0 },
2668   { "pushV",            { RMrSI }, 0 },
2669   { "pushV",            { RMrDI }, 0 },
2670   /* 58 */
2671   { "popV",             { RMrAX }, 0 },
2672   { "popV",             { RMrCX }, 0 },
2673   { "popV",             { RMrDX }, 0 },
2674   { "popV",             { RMrBX }, 0 },
2675   { "popV",             { RMrSP }, 0 },
2676   { "popV",             { RMrBP }, 0 },
2677   { "popV",             { RMrSI }, 0 },
2678   { "popV",             { RMrDI }, 0 },
2679   /* 60 */
2680   { X86_64_TABLE (X86_64_60) },
2681   { X86_64_TABLE (X86_64_61) },
2682   { X86_64_TABLE (X86_64_62) },
2683   { X86_64_TABLE (X86_64_63) },
2684   { Bad_Opcode },       /* seg fs */
2685   { Bad_Opcode },       /* seg gs */
2686   { Bad_Opcode },       /* op size prefix */
2687   { Bad_Opcode },       /* adr size prefix */
2688   /* 68 */
2689   { "pushT",            { sIv }, 0 },
2690   { "imulS",            { Gv, Ev, Iv }, 0 },
2691   { "pushT",            { sIbT }, 0 },
2692   { "imulS",            { Gv, Ev, sIb }, 0 },
2693   { "ins{b|}",          { Ybr, indirDX }, 0 },
2694   { X86_64_TABLE (X86_64_6D) },
2695   { "outs{b|}",         { indirDXr, Xb }, 0 },
2696   { X86_64_TABLE (X86_64_6F) },
2697   /* 70 */
2698   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2699   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2700   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2701   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2702   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2703   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2704   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2705   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2706   /* 78 */
2707   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2708   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2709   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2710   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2711   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2712   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2713   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2714   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2715   /* 80 */
2716   { REG_TABLE (REG_80) },
2717   { REG_TABLE (REG_81) },
2718   { X86_64_TABLE (X86_64_82) },
2719   { REG_TABLE (REG_83) },
2720   { "testB",            { Eb, Gb }, 0 },
2721   { "testS",            { Ev, Gv }, 0 },
2722   { "xchgB",            { Ebh2, Gb }, 0 },
2723   { "xchgS",            { Evh2, Gv }, 0 },
2724   /* 88 */
2725   { "movB",             { Ebh3, Gb }, 0 },
2726   { "movS",             { Evh3, Gv }, 0 },
2727   { "movB",             { Gb, EbS }, 0 },
2728   { "movS",             { Gv, EvS }, 0 },
2729   { "movD",             { Sv, Sw }, 0 },
2730   { MOD_TABLE (MOD_8D) },
2731   { "movD",             { Sw, Sv }, 0 },
2732   { REG_TABLE (REG_8F) },
2733   /* 90 */
2734   { PREFIX_TABLE (PREFIX_90) },
2735   { "xchgS",            { RMeCX, eAX }, 0 },
2736   { "xchgS",            { RMeDX, eAX }, 0 },
2737   { "xchgS",            { RMeBX, eAX }, 0 },
2738   { "xchgS",            { RMeSP, eAX }, 0 },
2739   { "xchgS",            { RMeBP, eAX }, 0 },
2740   { "xchgS",            { RMeSI, eAX }, 0 },
2741   { "xchgS",            { RMeDI, eAX }, 0 },
2742   /* 98 */
2743   { "cW{t|}R",          { XX }, 0 },
2744   { "cR{t|}O",          { XX }, 0 },
2745   { X86_64_TABLE (X86_64_9A) },
2746   { Bad_Opcode },       /* fwait */
2747   { "pushfT",           { XX }, 0 },
2748   { "popfT",            { XX }, 0 },
2749   { "sahf",             { XX }, 0 },
2750   { "lahf",             { XX }, 0 },
2751   /* a0 */
2752   { "mov%LB",           { AL, Ob }, 0 },
2753   { "mov%LS",           { eAX, Ov }, 0 },
2754   { "mov%LB",           { Ob, AL }, 0 },
2755   { "mov%LS",           { Ov, eAX }, 0 },
2756   { "movs{b|}",         { Ybr, Xb }, 0 },
2757   { "movs{R|}",         { Yvr, Xv }, 0 },
2758   { "cmps{b|}",         { Xb, Yb }, 0 },
2759   { "cmps{R|}",         { Xv, Yv }, 0 },
2760   /* a8 */
2761   { "testB",            { AL, Ib }, 0 },
2762   { "testS",            { eAX, Iv }, 0 },
2763   { "stosB",            { Ybr, AL }, 0 },
2764   { "stosS",            { Yvr, eAX }, 0 },
2765   { "lodsB",            { ALr, Xb }, 0 },
2766   { "lodsS",            { eAXr, Xv }, 0 },
2767   { "scasB",            { AL, Yb }, 0 },
2768   { "scasS",            { eAX, Yv }, 0 },
2769   /* b0 */
2770   { "movB",             { RMAL, Ib }, 0 },
2771   { "movB",             { RMCL, Ib }, 0 },
2772   { "movB",             { RMDL, Ib }, 0 },
2773   { "movB",             { RMBL, Ib }, 0 },
2774   { "movB",             { RMAH, Ib }, 0 },
2775   { "movB",             { RMCH, Ib }, 0 },
2776   { "movB",             { RMDH, Ib }, 0 },
2777   { "movB",             { RMBH, Ib }, 0 },
2778   /* b8 */
2779   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2780   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2781   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2782   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2783   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2784   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2785   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2786   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2787   /* c0 */
2788   { REG_TABLE (REG_C0) },
2789   { REG_TABLE (REG_C1) },
2790   { "retT",             { Iw, BND }, 0 },
2791   { "retT",             { BND }, 0 },
2792   { X86_64_TABLE (X86_64_C4) },
2793   { X86_64_TABLE (X86_64_C5) },
2794   { REG_TABLE (REG_C6) },
2795   { REG_TABLE (REG_C7) },
2796   /* c8 */
2797   { "enterT",           { Iw, Ib }, 0 },
2798   { "leaveT",           { XX }, 0 },
2799   { "Jret{|f}P",        { Iw }, 0 },
2800   { "Jret{|f}P",        { XX }, 0 },
2801   { "int3",             { XX }, 0 },
2802   { "int",              { Ib }, 0 },
2803   { X86_64_TABLE (X86_64_CE) },
2804   { "iret%LP",          { XX }, 0 },
2805   /* d0 */
2806   { REG_TABLE (REG_D0) },
2807   { REG_TABLE (REG_D1) },
2808   { REG_TABLE (REG_D2) },
2809   { REG_TABLE (REG_D3) },
2810   { X86_64_TABLE (X86_64_D4) },
2811   { X86_64_TABLE (X86_64_D5) },
2812   { Bad_Opcode },
2813   { "xlat",             { DSBX }, 0 },
2814   /* d8 */
2815   { FLOAT },
2816   { FLOAT },
2817   { FLOAT },
2818   { FLOAT },
2819   { FLOAT },
2820   { FLOAT },
2821   { FLOAT },
2822   { FLOAT },
2823   /* e0 */
2824   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2825   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2826   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2827   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2828   { "inB",              { AL, Ib }, 0 },
2829   { "inG",              { zAX, Ib }, 0 },
2830   { "outB",             { Ib, AL }, 0 },
2831   { "outG",             { Ib, zAX }, 0 },
2832   /* e8 */
2833   { X86_64_TABLE (X86_64_E8) },
2834   { X86_64_TABLE (X86_64_E9) },
2835   { X86_64_TABLE (X86_64_EA) },
2836   { "jmp",              { Jb, BND }, 0 },
2837   { "inB",              { AL, indirDX }, 0 },
2838   { "inG",              { zAX, indirDX }, 0 },
2839   { "outB",             { indirDX, AL }, 0 },
2840   { "outG",             { indirDX, zAX }, 0 },
2841   /* f0 */
2842   { Bad_Opcode },       /* lock prefix */
2843   { "icebp",            { XX }, 0 },
2844   { Bad_Opcode },       /* repne */
2845   { Bad_Opcode },       /* repz */
2846   { "hlt",              { XX }, 0 },
2847   { "cmc",              { XX }, 0 },
2848   { REG_TABLE (REG_F6) },
2849   { REG_TABLE (REG_F7) },
2850   /* f8 */
2851   { "clc",              { XX }, 0 },
2852   { "stc",              { XX }, 0 },
2853   { "cli",              { XX }, 0 },
2854   { "sti",              { XX }, 0 },
2855   { "cld",              { XX }, 0 },
2856   { "std",              { XX }, 0 },
2857   { REG_TABLE (REG_FE) },
2858   { REG_TABLE (REG_FF) },
2859 };
2860
2861 static const struct dis386 dis386_twobyte[] = {
2862   /* 00 */
2863   { REG_TABLE (REG_0F00 ) },
2864   { REG_TABLE (REG_0F01 ) },
2865   { "larS",             { Gv, Ew }, 0 },
2866   { "lslS",             { Gv, Ew }, 0 },
2867   { Bad_Opcode },
2868   { "syscall",          { XX }, 0 },
2869   { "clts",             { XX }, 0 },
2870   { "sysret%LP",                { XX }, 0 },
2871   /* 08 */
2872   { "invd",             { XX }, 0 },
2873   { PREFIX_TABLE (PREFIX_0F09) },
2874   { Bad_Opcode },
2875   { "ud2",              { XX }, 0 },
2876   { Bad_Opcode },
2877   { REG_TABLE (REG_0F0D) },
2878   { "femms",            { XX }, 0 },
2879   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2880   /* 10 */
2881   { PREFIX_TABLE (PREFIX_0F10) },
2882   { PREFIX_TABLE (PREFIX_0F11) },
2883   { PREFIX_TABLE (PREFIX_0F12) },
2884   { MOD_TABLE (MOD_0F13) },
2885   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2886   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2887   { PREFIX_TABLE (PREFIX_0F16) },
2888   { MOD_TABLE (MOD_0F17) },
2889   /* 18 */
2890   { REG_TABLE (REG_0F18) },
2891   { "nopQ",             { Ev }, 0 },
2892   { PREFIX_TABLE (PREFIX_0F1A) },
2893   { PREFIX_TABLE (PREFIX_0F1B) },
2894   { "nopQ",             { Ev }, 0 },
2895   { "nopQ",             { Ev }, 0 },
2896   { PREFIX_TABLE (PREFIX_0F1E) },
2897   { "nopQ",             { Ev }, 0 },
2898   /* 20 */
2899   { "movZ",             { Rm, Cm }, 0 },
2900   { "movZ",             { Rm, Dm }, 0 },
2901   { "movZ",             { Cm, Rm }, 0 },
2902   { "movZ",             { Dm, Rm }, 0 },
2903   { MOD_TABLE (MOD_0F24) },
2904   { Bad_Opcode },
2905   { MOD_TABLE (MOD_0F26) },
2906   { Bad_Opcode },
2907   /* 28 */
2908   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2909   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2910   { PREFIX_TABLE (PREFIX_0F2A) },
2911   { PREFIX_TABLE (PREFIX_0F2B) },
2912   { PREFIX_TABLE (PREFIX_0F2C) },
2913   { PREFIX_TABLE (PREFIX_0F2D) },
2914   { PREFIX_TABLE (PREFIX_0F2E) },
2915   { PREFIX_TABLE (PREFIX_0F2F) },
2916   /* 30 */
2917   { "wrmsr",            { XX }, 0 },
2918   { "rdtsc",            { XX }, 0 },
2919   { "rdmsr",            { XX }, 0 },
2920   { "rdpmc",            { XX }, 0 },
2921   { "sysenter",         { XX }, 0 },
2922   { "sysexit",          { XX }, 0 },
2923   { Bad_Opcode },
2924   { "getsec",           { XX }, 0 },
2925   /* 38 */
2926   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2927   { Bad_Opcode },
2928   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2929   { Bad_Opcode },
2930   { Bad_Opcode },
2931   { Bad_Opcode },
2932   { Bad_Opcode },
2933   { Bad_Opcode },
2934   /* 40 */
2935   { "cmovoS",           { Gv, Ev }, 0 },
2936   { "cmovnoS",          { Gv, Ev }, 0 },
2937   { "cmovbS",           { Gv, Ev }, 0 },
2938   { "cmovaeS",          { Gv, Ev }, 0 },
2939   { "cmoveS",           { Gv, Ev }, 0 },
2940   { "cmovneS",          { Gv, Ev }, 0 },
2941   { "cmovbeS",          { Gv, Ev }, 0 },
2942   { "cmovaS",           { Gv, Ev }, 0 },
2943   /* 48 */
2944   { "cmovsS",           { Gv, Ev }, 0 },
2945   { "cmovnsS",          { Gv, Ev }, 0 },
2946   { "cmovpS",           { Gv, Ev }, 0 },
2947   { "cmovnpS",          { Gv, Ev }, 0 },
2948   { "cmovlS",           { Gv, Ev }, 0 },
2949   { "cmovgeS",          { Gv, Ev }, 0 },
2950   { "cmovleS",          { Gv, Ev }, 0 },
2951   { "cmovgS",           { Gv, Ev }, 0 },
2952   /* 50 */
2953   { MOD_TABLE (MOD_0F51) },
2954   { PREFIX_TABLE (PREFIX_0F51) },
2955   { PREFIX_TABLE (PREFIX_0F52) },
2956   { PREFIX_TABLE (PREFIX_0F53) },
2957   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2958   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2959   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2960   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2961   /* 58 */
2962   { PREFIX_TABLE (PREFIX_0F58) },
2963   { PREFIX_TABLE (PREFIX_0F59) },
2964   { PREFIX_TABLE (PREFIX_0F5A) },
2965   { PREFIX_TABLE (PREFIX_0F5B) },
2966   { PREFIX_TABLE (PREFIX_0F5C) },
2967   { PREFIX_TABLE (PREFIX_0F5D) },
2968   { PREFIX_TABLE (PREFIX_0F5E) },
2969   { PREFIX_TABLE (PREFIX_0F5F) },
2970   /* 60 */
2971   { PREFIX_TABLE (PREFIX_0F60) },
2972   { PREFIX_TABLE (PREFIX_0F61) },
2973   { PREFIX_TABLE (PREFIX_0F62) },
2974   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2975   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2976   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2977   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2978   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2979   /* 68 */
2980   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2981   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2982   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2983   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2984   { PREFIX_TABLE (PREFIX_0F6C) },
2985   { PREFIX_TABLE (PREFIX_0F6D) },
2986   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2987   { PREFIX_TABLE (PREFIX_0F6F) },
2988   /* 70 */
2989   { PREFIX_TABLE (PREFIX_0F70) },
2990   { REG_TABLE (REG_0F71) },
2991   { REG_TABLE (REG_0F72) },
2992   { REG_TABLE (REG_0F73) },
2993   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2994   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2995   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2996   { "emms",             { XX }, PREFIX_OPCODE },
2997   /* 78 */
2998   { PREFIX_TABLE (PREFIX_0F78) },
2999   { PREFIX_TABLE (PREFIX_0F79) },
3000   { Bad_Opcode },
3001   { Bad_Opcode },
3002   { PREFIX_TABLE (PREFIX_0F7C) },
3003   { PREFIX_TABLE (PREFIX_0F7D) },
3004   { PREFIX_TABLE (PREFIX_0F7E) },
3005   { PREFIX_TABLE (PREFIX_0F7F) },
3006   /* 80 */
3007   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3008   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3009   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3010   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3011   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3012   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3013   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3014   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3015   /* 88 */
3016   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3017   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3018   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3019   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3020   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3021   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3022   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3023   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3024   /* 90 */
3025   { "seto",             { Eb }, 0 },
3026   { "setno",            { Eb }, 0 },
3027   { "setb",             { Eb }, 0 },
3028   { "setae",            { Eb }, 0 },
3029   { "sete",             { Eb }, 0 },
3030   { "setne",            { Eb }, 0 },
3031   { "setbe",            { Eb }, 0 },
3032   { "seta",             { Eb }, 0 },
3033   /* 98 */
3034   { "sets",             { Eb }, 0 },
3035   { "setns",            { Eb }, 0 },
3036   { "setp",             { Eb }, 0 },
3037   { "setnp",            { Eb }, 0 },
3038   { "setl",             { Eb }, 0 },
3039   { "setge",            { Eb }, 0 },
3040   { "setle",            { Eb }, 0 },
3041   { "setg",             { Eb }, 0 },
3042   /* a0 */
3043   { "pushT",            { fs }, 0 },
3044   { "popT",             { fs }, 0 },
3045   { "cpuid",            { XX }, 0 },
3046   { "btS",              { Ev, Gv }, 0 },
3047   { "shldS",            { Ev, Gv, Ib }, 0 },
3048   { "shldS",            { Ev, Gv, CL }, 0 },
3049   { REG_TABLE (REG_0FA6) },
3050   { REG_TABLE (REG_0FA7) },
3051   /* a8 */
3052   { "pushT",            { gs }, 0 },
3053   { "popT",             { gs }, 0 },
3054   { "rsm",              { XX }, 0 },
3055   { "btsS",             { Evh1, Gv }, 0 },
3056   { "shrdS",            { Ev, Gv, Ib }, 0 },
3057   { "shrdS",            { Ev, Gv, CL }, 0 },
3058   { REG_TABLE (REG_0FAE) },
3059   { "imulS",            { Gv, Ev }, 0 },
3060   /* b0 */
3061   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3062   { "cmpxchgS",         { Evh1, Gv }, 0 },
3063   { MOD_TABLE (MOD_0FB2) },
3064   { "btrS",             { Evh1, Gv }, 0 },
3065   { MOD_TABLE (MOD_0FB4) },
3066   { MOD_TABLE (MOD_0FB5) },
3067   { "movz{bR|x}",       { Gv, Eb }, 0 },
3068   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3069   /* b8 */
3070   { PREFIX_TABLE (PREFIX_0FB8) },
3071   { "ud1S",             { Gv, Ev }, 0 },
3072   { REG_TABLE (REG_0FBA) },
3073   { "btcS",             { Evh1, Gv }, 0 },
3074   { PREFIX_TABLE (PREFIX_0FBC) },
3075   { PREFIX_TABLE (PREFIX_0FBD) },
3076   { "movs{bR|x}",       { Gv, Eb }, 0 },
3077   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3078   /* c0 */
3079   { "xaddB",            { Ebh1, Gb }, 0 },
3080   { "xaddS",            { Evh1, Gv }, 0 },
3081   { PREFIX_TABLE (PREFIX_0FC2) },
3082   { MOD_TABLE (MOD_0FC3) },
3083   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3084   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3085   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3086   { REG_TABLE (REG_0FC7) },
3087   /* c8 */
3088   { "bswap",            { RMeAX }, 0 },
3089   { "bswap",            { RMeCX }, 0 },
3090   { "bswap",            { RMeDX }, 0 },
3091   { "bswap",            { RMeBX }, 0 },
3092   { "bswap",            { RMeSP }, 0 },
3093   { "bswap",            { RMeBP }, 0 },
3094   { "bswap",            { RMeSI }, 0 },
3095   { "bswap",            { RMeDI }, 0 },
3096   /* d0 */
3097   { PREFIX_TABLE (PREFIX_0FD0) },
3098   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3099   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3100   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3101   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3102   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3103   { PREFIX_TABLE (PREFIX_0FD6) },
3104   { MOD_TABLE (MOD_0FD7) },
3105   /* d8 */
3106   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3107   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3108   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3109   { "pand",             { MX, EM }, PREFIX_OPCODE },
3110   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3111   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3112   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3113   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3114   /* e0 */
3115   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3116   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3117   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3118   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3119   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3120   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3121   { PREFIX_TABLE (PREFIX_0FE6) },
3122   { PREFIX_TABLE (PREFIX_0FE7) },
3123   /* e8 */
3124   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3125   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3126   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3127   { "por",              { MX, EM }, PREFIX_OPCODE },
3128   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3129   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3130   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3131   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3132   /* f0 */
3133   { PREFIX_TABLE (PREFIX_0FF0) },
3134   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3135   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3136   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3137   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3138   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3139   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3140   { PREFIX_TABLE (PREFIX_0FF7) },
3141   /* f8 */
3142   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3143   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3144   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3145   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3146   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3147   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3148   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3149   { "ud0S",             { Gv, Ev }, 0 },
3150 };
3151
3152 static const unsigned char onebyte_has_modrm[256] = {
3153   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3154   /*       -------------------------------        */
3155   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3156   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3157   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3158   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3159   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3160   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3161   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3162   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3163   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3164   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3165   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3166   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3167   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3168   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3169   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3170   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3171   /*       -------------------------------        */
3172   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3173 };
3174
3175 static const unsigned char twobyte_has_modrm[256] = {
3176   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3177   /*       -------------------------------        */
3178   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3179   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3180   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3181   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3182   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3183   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3184   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3185   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3186   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3187   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3188   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3189   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3190   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3191   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3192   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3193   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3194   /*       -------------------------------        */
3195   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3196 };
3197
3198 static char obuf[100];
3199 static char *obufp;
3200 static char *mnemonicendp;
3201 static char scratchbuf[100];
3202 static unsigned char *start_codep;
3203 static unsigned char *insn_codep;
3204 static unsigned char *codep;
3205 static unsigned char *end_codep;
3206 static int last_lock_prefix;
3207 static int last_repz_prefix;
3208 static int last_repnz_prefix;
3209 static int last_data_prefix;
3210 static int last_addr_prefix;
3211 static int last_rex_prefix;
3212 static int last_seg_prefix;
3213 static int fwait_prefix;
3214 /* The active segment register prefix.  */
3215 static int active_seg_prefix;
3216 #define MAX_CODE_LENGTH 15
3217 /* We can up to 14 prefixes since the maximum instruction length is
3218    15bytes.  */
3219 static int all_prefixes[MAX_CODE_LENGTH - 1];
3220 static disassemble_info *the_info;
3221 static struct
3222   {
3223     int mod;
3224     int reg;
3225     int rm;
3226   }
3227 modrm;
3228 static unsigned char need_modrm;
3229 static struct
3230   {
3231     int scale;
3232     int index;
3233     int base;
3234   }
3235 sib;
3236 static struct
3237   {
3238     int register_specifier;
3239     int length;
3240     int prefix;
3241     int w;
3242     int evex;
3243     int r;
3244     int v;
3245     int mask_register_specifier;
3246     int zeroing;
3247     int ll;
3248     int b;
3249   }
3250 vex;
3251 static unsigned char need_vex;
3252 static unsigned char need_vex_reg;
3253 static unsigned char vex_w_done;
3254
3255 struct op
3256   {
3257     const char *name;
3258     unsigned int len;
3259   };
3260
3261 /* If we are accessing mod/rm/reg without need_modrm set, then the
3262    values are stale.  Hitting this abort likely indicates that you
3263    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3264 #define MODRM_CHECK  if (!need_modrm) abort ()
3265
3266 static const char **names64;
3267 static const char **names32;
3268 static const char **names16;
3269 static const char **names8;
3270 static const char **names8rex;
3271 static const char **names_seg;
3272 static const char *index64;
3273 static const char *index32;
3274 static const char **index16;
3275 static const char **names_bnd;
3276
3277 static const char *intel_names64[] = {
3278   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3279   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3280 };
3281 static const char *intel_names32[] = {
3282   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3283   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3284 };
3285 static const char *intel_names16[] = {
3286   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3287   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3288 };
3289 static const char *intel_names8[] = {
3290   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3291 };
3292 static const char *intel_names8rex[] = {
3293   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3294   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3295 };
3296 static const char *intel_names_seg[] = {
3297   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3298 };
3299 static const char *intel_index64 = "riz";
3300 static const char *intel_index32 = "eiz";
3301 static const char *intel_index16[] = {
3302   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3303 };
3304
3305 static const char *att_names64[] = {
3306   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3307   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3308 };
3309 static const char *att_names32[] = {
3310   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3311   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3312 };
3313 static const char *att_names16[] = {
3314   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3315   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3316 };
3317 static const char *att_names8[] = {
3318   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3319 };
3320 static const char *att_names8rex[] = {
3321   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3322   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3323 };
3324 static const char *att_names_seg[] = {
3325   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3326 };
3327 static const char *att_index64 = "%riz";
3328 static const char *att_index32 = "%eiz";
3329 static const char *att_index16[] = {
3330   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3331 };
3332
3333 static const char **names_mm;
3334 static const char *intel_names_mm[] = {
3335   "mm0", "mm1", "mm2", "mm3",
3336   "mm4", "mm5", "mm6", "mm7"
3337 };
3338 static const char *att_names_mm[] = {
3339   "%mm0", "%mm1", "%mm2", "%mm3",
3340   "%mm4", "%mm5", "%mm6", "%mm7"
3341 };
3342
3343 static const char *intel_names_bnd[] = {
3344   "bnd0", "bnd1", "bnd2", "bnd3"
3345 };
3346
3347 static const char *att_names_bnd[] = {
3348   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3349 };
3350
3351 static const char **names_xmm;
3352 static const char *intel_names_xmm[] = {
3353   "xmm0", "xmm1", "xmm2", "xmm3",
3354   "xmm4", "xmm5", "xmm6", "xmm7",
3355   "xmm8", "xmm9", "xmm10", "xmm11",
3356   "xmm12", "xmm13", "xmm14", "xmm15",
3357   "xmm16", "xmm17", "xmm18", "xmm19",
3358   "xmm20", "xmm21", "xmm22", "xmm23",
3359   "xmm24", "xmm25", "xmm26", "xmm27",
3360   "xmm28", "xmm29", "xmm30", "xmm31"
3361 };
3362 static const char *att_names_xmm[] = {
3363   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3364   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3365   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3366   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3367   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3368   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3369   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3370   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3371 };
3372
3373 static const char **names_ymm;
3374 static const char *intel_names_ymm[] = {
3375   "ymm0", "ymm1", "ymm2", "ymm3",
3376   "ymm4", "ymm5", "ymm6", "ymm7",
3377   "ymm8", "ymm9", "ymm10", "ymm11",
3378   "ymm12", "ymm13", "ymm14", "ymm15",
3379   "ymm16", "ymm17", "ymm18", "ymm19",
3380   "ymm20", "ymm21", "ymm22", "ymm23",
3381   "ymm24", "ymm25", "ymm26", "ymm27",
3382   "ymm28", "ymm29", "ymm30", "ymm31"
3383 };
3384 static const char *att_names_ymm[] = {
3385   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3386   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3387   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3388   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3389   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3390   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3391   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3392   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3393 };
3394
3395 static const char **names_zmm;
3396 static const char *intel_names_zmm[] = {
3397   "zmm0", "zmm1", "zmm2", "zmm3",
3398   "zmm4", "zmm5", "zmm6", "zmm7",
3399   "zmm8", "zmm9", "zmm10", "zmm11",
3400   "zmm12", "zmm13", "zmm14", "zmm15",
3401   "zmm16", "zmm17", "zmm18", "zmm19",
3402   "zmm20", "zmm21", "zmm22", "zmm23",
3403   "zmm24", "zmm25", "zmm26", "zmm27",
3404   "zmm28", "zmm29", "zmm30", "zmm31"
3405 };
3406 static const char *att_names_zmm[] = {
3407   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3408   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3409   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3410   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3411   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3412   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3413   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3414   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3415 };
3416
3417 static const char **names_mask;
3418 static const char *intel_names_mask[] = {
3419   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3420 };
3421 static const char *att_names_mask[] = {
3422   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3423 };
3424
3425 static const char *names_rounding[] =
3426 {
3427   "{rn-sae}",
3428   "{rd-sae}",
3429   "{ru-sae}",
3430   "{rz-sae}"
3431 };
3432
3433 static const struct dis386 reg_table[][8] = {
3434   /* REG_80 */
3435   {
3436     { "addA",   { Ebh1, Ib }, 0 },
3437     { "orA",    { Ebh1, Ib }, 0 },
3438     { "adcA",   { Ebh1, Ib }, 0 },
3439     { "sbbA",   { Ebh1, Ib }, 0 },
3440     { "andA",   { Ebh1, Ib }, 0 },
3441     { "subA",   { Ebh1, Ib }, 0 },
3442     { "xorA",   { Ebh1, Ib }, 0 },
3443     { "cmpA",   { Eb, Ib }, 0 },
3444   },
3445   /* REG_81 */
3446   {
3447     { "addQ",   { Evh1, Iv }, 0 },
3448     { "orQ",    { Evh1, Iv }, 0 },
3449     { "adcQ",   { Evh1, Iv }, 0 },
3450     { "sbbQ",   { Evh1, Iv }, 0 },
3451     { "andQ",   { Evh1, Iv }, 0 },
3452     { "subQ",   { Evh1, Iv }, 0 },
3453     { "xorQ",   { Evh1, Iv }, 0 },
3454     { "cmpQ",   { Ev, Iv }, 0 },
3455   },
3456   /* REG_83 */
3457   {
3458     { "addQ",   { Evh1, sIb }, 0 },
3459     { "orQ",    { Evh1, sIb }, 0 },
3460     { "adcQ",   { Evh1, sIb }, 0 },
3461     { "sbbQ",   { Evh1, sIb }, 0 },
3462     { "andQ",   { Evh1, sIb }, 0 },
3463     { "subQ",   { Evh1, sIb }, 0 },
3464     { "xorQ",   { Evh1, sIb }, 0 },
3465     { "cmpQ",   { Ev, sIb }, 0 },
3466   },
3467   /* REG_8F */
3468   {
3469     { "popU",   { stackEv }, 0 },
3470     { XOP_8F_TABLE (XOP_09) },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { XOP_8F_TABLE (XOP_09) },
3475   },
3476   /* REG_C0 */
3477   {
3478     { "rolA",   { Eb, Ib }, 0 },
3479     { "rorA",   { Eb, Ib }, 0 },
3480     { "rclA",   { Eb, Ib }, 0 },
3481     { "rcrA",   { Eb, Ib }, 0 },
3482     { "shlA",   { Eb, Ib }, 0 },
3483     { "shrA",   { Eb, Ib }, 0 },
3484     { "shlA",   { Eb, Ib }, 0 },
3485     { "sarA",   { Eb, Ib }, 0 },
3486   },
3487   /* REG_C1 */
3488   {
3489     { "rolQ",   { Ev, Ib }, 0 },
3490     { "rorQ",   { Ev, Ib }, 0 },
3491     { "rclQ",   { Ev, Ib }, 0 },
3492     { "rcrQ",   { Ev, Ib }, 0 },
3493     { "shlQ",   { Ev, Ib }, 0 },
3494     { "shrQ",   { Ev, Ib }, 0 },
3495     { "shlQ",   { Ev, Ib }, 0 },
3496     { "sarQ",   { Ev, Ib }, 0 },
3497   },
3498   /* REG_C6 */
3499   {
3500     { "movA",   { Ebh3, Ib }, 0 },
3501     { Bad_Opcode },
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { Bad_Opcode },
3507     { MOD_TABLE (MOD_C6_REG_7) },
3508   },
3509   /* REG_C7 */
3510   {
3511     { "movQ",   { Evh3, Iv }, 0 },
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { Bad_Opcode },
3518     { MOD_TABLE (MOD_C7_REG_7) },
3519   },
3520   /* REG_D0 */
3521   {
3522     { "rolA",   { Eb, I1 }, 0 },
3523     { "rorA",   { Eb, I1 }, 0 },
3524     { "rclA",   { Eb, I1 }, 0 },
3525     { "rcrA",   { Eb, I1 }, 0 },
3526     { "shlA",   { Eb, I1 }, 0 },
3527     { "shrA",   { Eb, I1 }, 0 },
3528     { "shlA",   { Eb, I1 }, 0 },
3529     { "sarA",   { Eb, I1 }, 0 },
3530   },
3531   /* REG_D1 */
3532   {
3533     { "rolQ",   { Ev, I1 }, 0 },
3534     { "rorQ",   { Ev, I1 }, 0 },
3535     { "rclQ",   { Ev, I1 }, 0 },
3536     { "rcrQ",   { Ev, I1 }, 0 },
3537     { "shlQ",   { Ev, I1 }, 0 },
3538     { "shrQ",   { Ev, I1 }, 0 },
3539     { "shlQ",   { Ev, I1 }, 0 },
3540     { "sarQ",   { Ev, I1 }, 0 },
3541   },
3542   /* REG_D2 */
3543   {
3544     { "rolA",   { Eb, CL }, 0 },
3545     { "rorA",   { Eb, CL }, 0 },
3546     { "rclA",   { Eb, CL }, 0 },
3547     { "rcrA",   { Eb, CL }, 0 },
3548     { "shlA",   { Eb, CL }, 0 },
3549     { "shrA",   { Eb, CL }, 0 },
3550     { "shlA",   { Eb, CL }, 0 },
3551     { "sarA",   { Eb, CL }, 0 },
3552   },
3553   /* REG_D3 */
3554   {
3555     { "rolQ",   { Ev, CL }, 0 },
3556     { "rorQ",   { Ev, CL }, 0 },
3557     { "rclQ",   { Ev, CL }, 0 },
3558     { "rcrQ",   { Ev, CL }, 0 },
3559     { "shlQ",   { Ev, CL }, 0 },
3560     { "shrQ",   { Ev, CL }, 0 },
3561     { "shlQ",   { Ev, CL }, 0 },
3562     { "sarQ",   { Ev, CL }, 0 },
3563   },
3564   /* REG_F6 */
3565   {
3566     { "testA",  { Eb, Ib }, 0 },
3567     { "testA",  { Eb, Ib }, 0 },
3568     { "notA",   { Ebh1 }, 0 },
3569     { "negA",   { Ebh1 }, 0 },
3570     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3571     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3572     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3573     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3574   },
3575   /* REG_F7 */
3576   {
3577     { "testQ",  { Ev, Iv }, 0 },
3578     { "testQ",  { Ev, Iv }, 0 },
3579     { "notQ",   { Evh1 }, 0 },
3580     { "negQ",   { Evh1 }, 0 },
3581     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3582     { "imulQ",  { Ev }, 0 },
3583     { "divQ",   { Ev }, 0 },
3584     { "idivQ",  { Ev }, 0 },
3585   },
3586   /* REG_FE */
3587   {
3588     { "incA",   { Ebh1 }, 0 },
3589     { "decA",   { Ebh1 }, 0 },
3590   },
3591   /* REG_FF */
3592   {
3593     { "incQ",   { Evh1 }, 0 },
3594     { "decQ",   { Evh1 }, 0 },
3595     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3596     { MOD_TABLE (MOD_FF_REG_3) },
3597     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3598     { MOD_TABLE (MOD_FF_REG_5) },
3599     { "pushU",  { stackEv }, 0 },
3600     { Bad_Opcode },
3601   },
3602   /* REG_0F00 */
3603   {
3604     { "sldtD",  { Sv }, 0 },
3605     { "strD",   { Sv }, 0 },
3606     { "lldt",   { Ew }, 0 },
3607     { "ltr",    { Ew }, 0 },
3608     { "verr",   { Ew }, 0 },
3609     { "verw",   { Ew }, 0 },
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612   },
3613   /* REG_0F01 */
3614   {
3615     { MOD_TABLE (MOD_0F01_REG_0) },
3616     { MOD_TABLE (MOD_0F01_REG_1) },
3617     { MOD_TABLE (MOD_0F01_REG_2) },
3618     { MOD_TABLE (MOD_0F01_REG_3) },
3619     { "smswD",  { Sv }, 0 },
3620     { MOD_TABLE (MOD_0F01_REG_5) },
3621     { "lmsw",   { Ew }, 0 },
3622     { MOD_TABLE (MOD_0F01_REG_7) },
3623   },
3624   /* REG_0F0D */
3625   {
3626     { "prefetch",       { Mb }, 0 },
3627     { "prefetchw",      { Mb }, 0 },
3628     { "prefetchwt1",    { Mb }, 0 },
3629     { "prefetch",       { Mb }, 0 },
3630     { "prefetch",       { Mb }, 0 },
3631     { "prefetch",       { Mb }, 0 },
3632     { "prefetch",       { Mb }, 0 },
3633     { "prefetch",       { Mb }, 0 },
3634   },
3635   /* REG_0F18 */
3636   {
3637     { MOD_TABLE (MOD_0F18_REG_0) },
3638     { MOD_TABLE (MOD_0F18_REG_1) },
3639     { MOD_TABLE (MOD_0F18_REG_2) },
3640     { MOD_TABLE (MOD_0F18_REG_3) },
3641     { MOD_TABLE (MOD_0F18_REG_4) },
3642     { MOD_TABLE (MOD_0F18_REG_5) },
3643     { MOD_TABLE (MOD_0F18_REG_6) },
3644     { MOD_TABLE (MOD_0F18_REG_7) },
3645   },
3646   /* REG_0F1E_MOD_3 */
3647   {
3648     { "nopQ",           { Ev }, 0 },
3649     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3650     { "nopQ",           { Ev }, 0 },
3651     { "nopQ",           { Ev }, 0 },
3652     { "nopQ",           { Ev }, 0 },
3653     { "nopQ",           { Ev }, 0 },
3654     { "nopQ",           { Ev }, 0 },
3655     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3656   },
3657   /* REG_0F71 */
3658   {
3659     { Bad_Opcode },
3660     { Bad_Opcode },
3661     { MOD_TABLE (MOD_0F71_REG_2) },
3662     { Bad_Opcode },
3663     { MOD_TABLE (MOD_0F71_REG_4) },
3664     { Bad_Opcode },
3665     { MOD_TABLE (MOD_0F71_REG_6) },
3666   },
3667   /* REG_0F72 */
3668   {
3669     { Bad_Opcode },
3670     { Bad_Opcode },
3671     { MOD_TABLE (MOD_0F72_REG_2) },
3672     { Bad_Opcode },
3673     { MOD_TABLE (MOD_0F72_REG_4) },
3674     { Bad_Opcode },
3675     { MOD_TABLE (MOD_0F72_REG_6) },
3676   },
3677   /* REG_0F73 */
3678   {
3679     { Bad_Opcode },
3680     { Bad_Opcode },
3681     { MOD_TABLE (MOD_0F73_REG_2) },
3682     { MOD_TABLE (MOD_0F73_REG_3) },
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { MOD_TABLE (MOD_0F73_REG_6) },
3686     { MOD_TABLE (MOD_0F73_REG_7) },
3687   },
3688   /* REG_0FA6 */
3689   {
3690     { "montmul",        { { OP_0f07, 0 } }, 0 },
3691     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3692     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3693   },
3694   /* REG_0FA7 */
3695   {
3696     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3697     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3698     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3699     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3700     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3701     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3702   },
3703   /* REG_0FAE */
3704   {
3705     { MOD_TABLE (MOD_0FAE_REG_0) },
3706     { MOD_TABLE (MOD_0FAE_REG_1) },
3707     { MOD_TABLE (MOD_0FAE_REG_2) },
3708     { MOD_TABLE (MOD_0FAE_REG_3) },
3709     { MOD_TABLE (MOD_0FAE_REG_4) },
3710     { MOD_TABLE (MOD_0FAE_REG_5) },
3711     { MOD_TABLE (MOD_0FAE_REG_6) },
3712     { MOD_TABLE (MOD_0FAE_REG_7) },
3713   },
3714   /* REG_0FBA */
3715   {
3716     { Bad_Opcode },
3717     { Bad_Opcode },
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { "btQ",    { Ev, Ib }, 0 },
3721     { "btsQ",   { Evh1, Ib }, 0 },
3722     { "btrQ",   { Evh1, Ib }, 0 },
3723     { "btcQ",   { Evh1, Ib }, 0 },
3724   },
3725   /* REG_0FC7 */
3726   {
3727     { Bad_Opcode },
3728     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3729     { Bad_Opcode },
3730     { MOD_TABLE (MOD_0FC7_REG_3) },
3731     { MOD_TABLE (MOD_0FC7_REG_4) },
3732     { MOD_TABLE (MOD_0FC7_REG_5) },
3733     { MOD_TABLE (MOD_0FC7_REG_6) },
3734     { MOD_TABLE (MOD_0FC7_REG_7) },
3735   },
3736   /* REG_VEX_0F71 */
3737   {
3738     { Bad_Opcode },
3739     { Bad_Opcode },
3740     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3741     { Bad_Opcode },
3742     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3743     { Bad_Opcode },
3744     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3745   },
3746   /* REG_VEX_0F72 */
3747   {
3748     { Bad_Opcode },
3749     { Bad_Opcode },
3750     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3751     { Bad_Opcode },
3752     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3753     { Bad_Opcode },
3754     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3755   },
3756   /* REG_VEX_0F73 */
3757   {
3758     { Bad_Opcode },
3759     { Bad_Opcode },
3760     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3761     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3762     { Bad_Opcode },
3763     { Bad_Opcode },
3764     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3765     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3766   },
3767   /* REG_VEX_0FAE */
3768   {
3769     { Bad_Opcode },
3770     { Bad_Opcode },
3771     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3772     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3773   },
3774   /* REG_VEX_0F38F3 */
3775   {
3776     { Bad_Opcode },
3777     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3778     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3779     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3780   },
3781   /* REG_XOP_LWPCB */
3782   {
3783     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3784     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3785   },
3786   /* REG_XOP_LWP */
3787   {
3788     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3789     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3790   },
3791   /* REG_XOP_TBM_01 */
3792   {
3793     { Bad_Opcode },
3794     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3795     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3796     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3797     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3798     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3799     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3800     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3801   },
3802   /* REG_XOP_TBM_02 */
3803   {
3804     { Bad_Opcode },
3805     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3806     { Bad_Opcode },
3807     { Bad_Opcode },
3808     { Bad_Opcode },
3809     { Bad_Opcode },
3810     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3811   },
3812 #define NEED_REG_TABLE
3813 #include "i386-dis-evex.h"
3814 #undef NEED_REG_TABLE
3815 };
3816
3817 static const struct dis386 prefix_table[][4] = {
3818   /* PREFIX_90 */
3819   {
3820     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3821     { "pause", { XX }, 0 },
3822     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3823     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3824   },
3825
3826   /* PREFIX_MOD_0_0F01_REG_5 */
3827   {
3828     { Bad_Opcode },
3829     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3833   {
3834     { Bad_Opcode },
3835     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3836   },
3837
3838   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3839   {
3840     { Bad_Opcode },
3841     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3842   },
3843
3844   /* PREFIX_0F09 */
3845   {
3846     { "wbinvd",   { XX }, 0 },
3847     { "wbnoinvd", { XX }, 0 },
3848   },
3849
3850   /* PREFIX_0F10 */
3851   {
3852     { "movups", { XM, EXx }, PREFIX_OPCODE },
3853     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3854     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3855     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F11 */
3859   {
3860     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3861     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3862     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3863     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3864   },
3865
3866   /* PREFIX_0F12 */
3867   {
3868     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3869     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3870     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3871     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F16 */
3875   {
3876     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3877     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3878     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F1A */
3882   {
3883     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3884     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3885     { "bndmov", { Gbnd, Ebnd }, 0 },
3886     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3887   },
3888
3889   /* PREFIX_0F1B */
3890   {
3891     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3892     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3893     { "bndmov", { Ebnd, Gbnd }, 0 },
3894     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3895   },
3896
3897   /* PREFIX_0F1E */
3898   {
3899     { "nopQ",   { Ev }, PREFIX_OPCODE },
3900     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3901     { "nopQ",   { Ev }, PREFIX_OPCODE },
3902     { "nopQ",   { Ev }, PREFIX_OPCODE },
3903   },
3904
3905   /* PREFIX_0F2A */
3906   {
3907     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3908     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3909     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3910     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3911   },
3912
3913   /* PREFIX_0F2B */
3914   {
3915     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3916     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3917     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3918     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3919   },
3920
3921   /* PREFIX_0F2C */
3922   {
3923     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3924     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3925     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3926     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3927   },
3928
3929   /* PREFIX_0F2D */
3930   {
3931     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3932     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3933     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3934     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F2E */
3938   {
3939     { "ucomiss",{ XM, EXd }, 0 },
3940     { Bad_Opcode },
3941     { "ucomisd",{ XM, EXq }, 0 },
3942   },
3943
3944   /* PREFIX_0F2F */
3945   {
3946     { "comiss", { XM, EXd }, 0 },
3947     { Bad_Opcode },
3948     { "comisd", { XM, EXq }, 0 },
3949   },
3950
3951   /* PREFIX_0F51 */
3952   {
3953     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3954     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3955     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3956     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3957   },
3958
3959   /* PREFIX_0F52 */
3960   {
3961     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3962     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F53 */
3966   {
3967     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3968     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0F58 */
3972   {
3973     { "addps", { XM, EXx }, PREFIX_OPCODE },
3974     { "addss", { XM, EXd }, PREFIX_OPCODE },
3975     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3976     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0F59 */
3980   {
3981     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3982     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3983     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3984     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0F5A */
3988   {
3989     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3990     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3991     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3992     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0F5B */
3996   {
3997     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3998     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3999     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4000   },
4001
4002   /* PREFIX_0F5C */
4003   {
4004     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4005     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4006     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4007     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4008   },
4009
4010   /* PREFIX_0F5D */
4011   {
4012     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4013     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4014     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4015     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4016   },
4017
4018   /* PREFIX_0F5E */
4019   {
4020     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4021     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4022     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4023     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4024   },
4025
4026   /* PREFIX_0F5F */
4027   {
4028     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4029     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4030     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4031     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_0F60 */
4035   {
4036     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4037     { Bad_Opcode },
4038     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0F61 */
4042   {
4043     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4044     { Bad_Opcode },
4045     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4046   },
4047
4048   /* PREFIX_0F62 */
4049   {
4050     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4051     { Bad_Opcode },
4052     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4053   },
4054
4055   /* PREFIX_0F6C */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4060   },
4061
4062   /* PREFIX_0F6D */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_0F6F */
4070   {
4071     { "movq",   { MX, EM }, PREFIX_OPCODE },
4072     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4073     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4074   },
4075
4076   /* PREFIX_0F70 */
4077   {
4078     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4079     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4080     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4081     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0F73_REG_3 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { "psrldq", { XS, Ib }, 0 },
4089   },
4090
4091   /* PREFIX_0F73_REG_7 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "pslldq", { XS, Ib }, 0 },
4096   },
4097
4098   /* PREFIX_0F78 */
4099   {
4100     {"vmread",  { Em, Gm }, 0 },
4101     { Bad_Opcode },
4102     {"extrq",   { XS, Ib, Ib }, 0 },
4103     {"insertq", { XM, XS, Ib, Ib }, 0 },
4104   },
4105
4106   /* PREFIX_0F79 */
4107   {
4108     {"vmwrite", { Gm, Em }, 0 },
4109     { Bad_Opcode },
4110     {"extrq",   { XM, XS }, 0 },
4111     {"insertq", { XM, XS }, 0 },
4112   },
4113
4114   /* PREFIX_0F7C */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4119     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F7D */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4127     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4128   },
4129
4130   /* PREFIX_0F7E */
4131   {
4132     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4133     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4134     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F7F */
4138   {
4139     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4140     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4141     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0FAE_REG_0 */
4145   {
4146     { Bad_Opcode },
4147     { "rdfsbase", { Ev }, 0 },
4148   },
4149
4150   /* PREFIX_0FAE_REG_1 */
4151   {
4152     { Bad_Opcode },
4153     { "rdgsbase", { Ev }, 0 },
4154   },
4155
4156   /* PREFIX_0FAE_REG_2 */
4157   {
4158     { Bad_Opcode },
4159     { "wrfsbase", { Ev }, 0 },
4160   },
4161
4162   /* PREFIX_0FAE_REG_3 */
4163   {
4164     { Bad_Opcode },
4165     { "wrgsbase", { Ev }, 0 },
4166   },
4167
4168   /* PREFIX_MOD_0_0FAE_REG_4 */
4169   {
4170     { "xsave",  { FXSAVE }, 0 },
4171     { "ptwrite%LQ", { Edq }, 0 },
4172   },
4173
4174   /* PREFIX_MOD_3_0FAE_REG_4 */
4175   {
4176     { Bad_Opcode },
4177     { "ptwrite%LQ", { Edq }, 0 },
4178   },
4179
4180   /* PREFIX_MOD_0_0FAE_REG_5 */
4181   {
4182     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_MOD_3_0FAE_REG_5 */
4186   {
4187     { "lfence",         { Skip_MODRM }, 0 },
4188     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0FAE_REG_6 */
4192   {
4193     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4194     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4195     { "clwb",   { Mb }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0FAE_REG_7 */
4199   {
4200     { "clflush",        { Mb }, 0 },
4201     { Bad_Opcode },
4202     { "clflushopt",     { Mb }, 0 },
4203   },
4204
4205   /* PREFIX_0FB8 */
4206   {
4207     { Bad_Opcode },
4208     { "popcntS", { Gv, Ev }, 0 },
4209   },
4210
4211   /* PREFIX_0FBC */
4212   {
4213     { "bsfS",   { Gv, Ev }, 0 },
4214     { "tzcntS", { Gv, Ev }, 0 },
4215     { "bsfS",   { Gv, Ev }, 0 },
4216   },
4217
4218   /* PREFIX_0FBD */
4219   {
4220     { "bsrS",   { Gv, Ev }, 0 },
4221     { "lzcntS", { Gv, Ev }, 0 },
4222     { "bsrS",   { Gv, Ev }, 0 },
4223   },
4224
4225   /* PREFIX_0FC2 */
4226   {
4227     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4228     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4229     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4230     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_MOD_0_0FC3 */
4234   {
4235     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_MOD_0_0FC7_REG_6 */
4239   {
4240     { "vmptrld",{ Mq }, 0 },
4241     { "vmxon",  { Mq }, 0 },
4242     { "vmclear",{ Mq }, 0 },
4243   },
4244
4245   /* PREFIX_MOD_3_0FC7_REG_6 */
4246   {
4247     { "rdrand", { Ev }, 0 },
4248     { Bad_Opcode },
4249     { "rdrand", { Ev }, 0 }
4250   },
4251
4252   /* PREFIX_MOD_3_0FC7_REG_7 */
4253   {
4254     { "rdseed", { Ev }, 0 },
4255     { "rdpid",  { Em }, 0 },
4256     { "rdseed", { Ev }, 0 },
4257   },
4258
4259   /* PREFIX_0FD0 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "addsubpd", { XM, EXx }, 0 },
4264     { "addsubps", { XM, EXx }, 0 },
4265   },
4266
4267   /* PREFIX_0FD6 */
4268   {
4269     { Bad_Opcode },
4270     { "movq2dq",{ XM, MS }, 0 },
4271     { "movq",   { EXqS, XM }, 0 },
4272     { "movdq2q",{ MX, XS }, 0 },
4273   },
4274
4275   /* PREFIX_0FE6 */
4276   {
4277     { Bad_Opcode },
4278     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4279     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4280     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0FE7 */
4284   {
4285     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4286     { Bad_Opcode },
4287     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4288   },
4289
4290   /* PREFIX_0FF0 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4296   },
4297
4298   /* PREFIX_0FF7 */
4299   {
4300     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4301     { Bad_Opcode },
4302     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F3810 */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F3814 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F3815 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F3817 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F3820 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3821 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3822 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3823 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F3824 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F3825 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F3828 */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F3829 */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F382A */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4394   },
4395
4396   /* PREFIX_0F382B */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F3830 */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F3831 */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F3832 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F3833 */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F3834 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F3835 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F3837 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F3838 */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F3839 */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F383A */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F383B */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F383C */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F383D */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F383E */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F383F */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3840 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3841 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3880 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3881 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3882 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F38C8 */
4544   {
4545     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4546   },
4547
4548   /* PREFIX_0F38C9 */
4549   {
4550     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F38CA */
4554   {
4555     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F38CB */
4559   {
4560     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F38CC */
4564   {
4565     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F38CD */
4569   {
4570     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F38CF */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F38DB */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F38DC */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F38DD */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F38DE */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F38DF */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F38F0 */
4616   {
4617     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4618     { Bad_Opcode },
4619     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4620     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F38F1 */
4624   {
4625     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4626     { Bad_Opcode },
4627     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4628     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F38F5 */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4636   },
4637
4638   /* PREFIX_0F38F6 */
4639   {
4640     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4641     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4642     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4643     { Bad_Opcode },
4644   },
4645
4646   /* PREFIX_0F3A08 */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4651   },
4652
4653   /* PREFIX_0F3A09 */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4658   },
4659
4660   /* PREFIX_0F3A0A */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4665   },
4666
4667   /* PREFIX_0F3A0B */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4672   },
4673
4674   /* PREFIX_0F3A0C */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4679   },
4680
4681   /* PREFIX_0F3A0D */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4686   },
4687
4688   /* PREFIX_0F3A0E */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4693   },
4694
4695   /* PREFIX_0F3A14 */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4700   },
4701
4702   /* PREFIX_0F3A15 */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4707   },
4708
4709   /* PREFIX_0F3A16 */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4714   },
4715
4716   /* PREFIX_0F3A17 */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4721   },
4722
4723   /* PREFIX_0F3A20 */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4728   },
4729
4730   /* PREFIX_0F3A21 */
4731   {
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4735   },
4736
4737   /* PREFIX_0F3A22 */
4738   {
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4742   },
4743
4744   /* PREFIX_0F3A40 */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4749   },
4750
4751   /* PREFIX_0F3A41 */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4756   },
4757
4758   /* PREFIX_0F3A42 */
4759   {
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4763   },
4764
4765   /* PREFIX_0F3A44 */
4766   {
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4770   },
4771
4772   /* PREFIX_0F3A60 */
4773   {
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4777   },
4778
4779   /* PREFIX_0F3A61 */
4780   {
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4784   },
4785
4786   /* PREFIX_0F3A62 */
4787   {
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4791   },
4792
4793   /* PREFIX_0F3A63 */
4794   {
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4798   },
4799
4800   /* PREFIX_0F3ACC */
4801   {
4802     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4803   },
4804
4805   /* PREFIX_0F3ACE */
4806   {
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4810   },
4811
4812   /* PREFIX_0F3ACF */
4813   {
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4817   },
4818
4819   /* PREFIX_0F3ADF */
4820   {
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4824   },
4825
4826   /* PREFIX_VEX_0F10 */
4827   {
4828     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4829     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4830     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4831     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4832   },
4833
4834   /* PREFIX_VEX_0F11 */
4835   {
4836     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4837     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4838     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4840   },
4841
4842   /* PREFIX_VEX_0F12 */
4843   {
4844     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4845     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4846     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4847     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4848   },
4849
4850   /* PREFIX_VEX_0F16 */
4851   {
4852     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4853     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4854     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4855   },
4856
4857   /* PREFIX_VEX_0F2A */
4858   {
4859     { Bad_Opcode },
4860     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4861     { Bad_Opcode },
4862     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4863   },
4864
4865   /* PREFIX_VEX_0F2C */
4866   {
4867     { Bad_Opcode },
4868     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4869     { Bad_Opcode },
4870     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4871   },
4872
4873   /* PREFIX_VEX_0F2D */
4874   {
4875     { Bad_Opcode },
4876     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4877     { Bad_Opcode },
4878     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4879   },
4880
4881   /* PREFIX_VEX_0F2E */
4882   {
4883     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4884     { Bad_Opcode },
4885     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0F2F */
4889   {
4890     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4891     { Bad_Opcode },
4892     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0F41 */
4896   {
4897     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4898     { Bad_Opcode },
4899     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0F42 */
4903   {
4904     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4905     { Bad_Opcode },
4906     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F44 */
4910   {
4911     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4912     { Bad_Opcode },
4913     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4914   },
4915
4916   /* PREFIX_VEX_0F45 */
4917   {
4918     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4919     { Bad_Opcode },
4920     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4921   },
4922
4923   /* PREFIX_VEX_0F46 */
4924   {
4925     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4926     { Bad_Opcode },
4927     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0F47 */
4931   {
4932     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4933     { Bad_Opcode },
4934     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4935   },
4936
4937   /* PREFIX_VEX_0F4A */
4938   {
4939     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4940     { Bad_Opcode },
4941     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4942   },
4943
4944   /* PREFIX_VEX_0F4B */
4945   {
4946     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4947     { Bad_Opcode },
4948     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4949   },
4950
4951   /* PREFIX_VEX_0F51 */
4952   {
4953     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4954     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4955     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4956     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4957   },
4958
4959   /* PREFIX_VEX_0F52 */
4960   {
4961     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4962     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4963   },
4964
4965   /* PREFIX_VEX_0F53 */
4966   {
4967     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4968     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4969   },
4970
4971   /* PREFIX_VEX_0F58 */
4972   {
4973     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4974     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4975     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4976     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4977   },
4978
4979   /* PREFIX_VEX_0F59 */
4980   {
4981     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4982     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4983     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4984     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4985   },
4986
4987   /* PREFIX_VEX_0F5A */
4988   {
4989     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4990     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4991     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4992     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4993   },
4994
4995   /* PREFIX_VEX_0F5B */
4996   {
4997     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4998     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4999     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5000   },
5001
5002   /* PREFIX_VEX_0F5C */
5003   {
5004     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5005     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5006     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5007     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5008   },
5009
5010   /* PREFIX_VEX_0F5D */
5011   {
5012     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5013     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5014     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5015     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5016   },
5017
5018   /* PREFIX_VEX_0F5E */
5019   {
5020     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5021     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5022     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5023     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5024   },
5025
5026   /* PREFIX_VEX_0F5F */
5027   {
5028     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5029     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5030     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5031     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5032   },
5033
5034   /* PREFIX_VEX_0F60 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5039   },
5040
5041   /* PREFIX_VEX_0F61 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0F62 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0F63 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F64 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0F65 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0F66 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F67 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0F68 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F69 */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F6A */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5109   },
5110
5111   /* PREFIX_VEX_0F6B */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F6C */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F6D */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F6E */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F6F */
5140   {
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5143     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0F70 */
5147   {
5148     { Bad_Opcode },
5149     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5150     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5151     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5152   },
5153
5154   /* PREFIX_VEX_0F71_REG_2 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F71_REG_4 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F71_REG_6 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0F72_REG_2 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0F72_REG_4 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0F72_REG_6 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5194   },
5195
5196   /* PREFIX_VEX_0F73_REG_2 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0F73_REG_3 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5208   },
5209
5210   /* PREFIX_VEX_0F73_REG_6 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5215   },
5216
5217   /* PREFIX_VEX_0F73_REG_7 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0F74 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0F75 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0F76 */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0F77 */
5246   {
5247     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5248   },
5249
5250   /* PREFIX_VEX_0F7C */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5255     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5256   },
5257
5258   /* PREFIX_VEX_0F7D */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5263     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5264   },
5265
5266   /* PREFIX_VEX_0F7E */
5267   {
5268     { Bad_Opcode },
5269     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5270     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0F7F */
5274   {
5275     { Bad_Opcode },
5276     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5277     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0F90 */
5281   {
5282     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5283     { Bad_Opcode },
5284     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5285   },
5286
5287   /* PREFIX_VEX_0F91 */
5288   {
5289     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5290     { Bad_Opcode },
5291     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5292   },
5293
5294   /* PREFIX_VEX_0F92 */
5295   {
5296     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5297     { Bad_Opcode },
5298     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5299     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5300   },
5301
5302   /* PREFIX_VEX_0F93 */
5303   {
5304     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5305     { Bad_Opcode },
5306     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5307     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5308   },
5309
5310   /* PREFIX_VEX_0F98 */
5311   {
5312     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5313     { Bad_Opcode },
5314     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0F99 */
5318   {
5319     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5320     { Bad_Opcode },
5321     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0FC2 */
5325   {
5326     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5327     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5328     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5329     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5330   },
5331
5332   /* PREFIX_VEX_0FC4 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0FC5 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0FD0 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5351     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5352   },
5353
5354   /* PREFIX_VEX_0FD1 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FD2 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5366   },
5367
5368   /* PREFIX_VEX_0FD3 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5373   },
5374
5375   /* PREFIX_VEX_0FD4 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FD5 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FD6 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FD7 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FD8 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FD9 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FDA */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FDB */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0FDC */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FDD */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5443   },
5444
5445   /* PREFIX_VEX_0FDE */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0FDF */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0FE0 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5464   },
5465
5466   /* PREFIX_VEX_0FE1 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0FE2 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0FE3 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0FE4 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0FE5 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5499   },
5500
5501   /* PREFIX_VEX_0FE6 */
5502   {
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5505     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5506     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5507   },
5508
5509   /* PREFIX_VEX_0FE7 */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5514   },
5515
5516   /* PREFIX_VEX_0FE8 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0FE9 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0FEA */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0FEB */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0FEC */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0FED */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0FEE */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0FEF */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5570   },
5571
5572   /* PREFIX_VEX_0FF0 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5578   },
5579
5580   /* PREFIX_VEX_0FF1 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0FF2 */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5592   },
5593
5594   /* PREFIX_VEX_0FF3 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5599   },
5600
5601   /* PREFIX_VEX_0FF4 */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0FF5 */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0FF6 */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0FF7 */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0FF8 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5634   },
5635
5636   /* PREFIX_VEX_0FF9 */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0FFA */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5648   },
5649
5650   /* PREFIX_VEX_0FFB */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0FFC */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5662   },
5663
5664   /* PREFIX_VEX_0FFD */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5669   },
5670
5671   /* PREFIX_VEX_0FFE */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5676   },
5677
5678   /* PREFIX_VEX_0F3800 */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5683   },
5684
5685   /* PREFIX_VEX_0F3801 */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5690   },
5691
5692   /* PREFIX_VEX_0F3802 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5697   },
5698
5699   /* PREFIX_VEX_0F3803 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5704   },
5705
5706   /* PREFIX_VEX_0F3804 */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5711   },
5712
5713   /* PREFIX_VEX_0F3805 */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5718   },
5719
5720   /* PREFIX_VEX_0F3806 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5725   },
5726
5727   /* PREFIX_VEX_0F3807 */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5732   },
5733
5734   /* PREFIX_VEX_0F3808 */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5739   },
5740
5741   /* PREFIX_VEX_0F3809 */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5746   },
5747
5748   /* PREFIX_VEX_0F380A */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5753   },
5754
5755   /* PREFIX_VEX_0F380B */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5760   },
5761
5762   /* PREFIX_VEX_0F380C */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F380D */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F380E */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F380F */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F3813 */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5795   },
5796
5797   /* PREFIX_VEX_0F3816 */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F3817 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5809   },
5810
5811   /* PREFIX_VEX_0F3818 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F3819 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F381A */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F381C */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F381D */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5844   },
5845
5846   /* PREFIX_VEX_0F381E */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F3820 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5858   },
5859
5860   /* PREFIX_VEX_0F3821 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5865   },
5866
5867   /* PREFIX_VEX_0F3822 */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5872   },
5873
5874   /* PREFIX_VEX_0F3823 */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5879   },
5880
5881   /* PREFIX_VEX_0F3824 */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5886   },
5887
5888   /* PREFIX_VEX_0F3825 */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5893   },
5894
5895   /* PREFIX_VEX_0F3828 */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5900   },
5901
5902   /* PREFIX_VEX_0F3829 */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5907   },
5908
5909   /* PREFIX_VEX_0F382A */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5914   },
5915
5916   /* PREFIX_VEX_0F382B */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5921   },
5922
5923   /* PREFIX_VEX_0F382C */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F382D */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5935   },
5936
5937   /* PREFIX_VEX_0F382E */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5942   },
5943
5944   /* PREFIX_VEX_0F382F */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5949   },
5950
5951   /* PREFIX_VEX_0F3830 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3831 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F3832 */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F3833 */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F3834 */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F3835 */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F3836 */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F3837 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6005   },
6006
6007   /* PREFIX_VEX_0F3838 */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6012   },
6013
6014   /* PREFIX_VEX_0F3839 */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6019   },
6020
6021   /* PREFIX_VEX_0F383A */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6026   },
6027
6028   /* PREFIX_VEX_0F383B */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6033   },
6034
6035   /* PREFIX_VEX_0F383C */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6040   },
6041
6042   /* PREFIX_VEX_0F383D */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6047   },
6048
6049   /* PREFIX_VEX_0F383E */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6054   },
6055
6056   /* PREFIX_VEX_0F383F */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6061   },
6062
6063   /* PREFIX_VEX_0F3840 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6068   },
6069
6070   /* PREFIX_VEX_0F3841 */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6075   },
6076
6077   /* PREFIX_VEX_0F3845 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6082   },
6083
6084   /* PREFIX_VEX_0F3846 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6089   },
6090
6091   /* PREFIX_VEX_0F3847 */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F3858 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6103   },
6104
6105   /* PREFIX_VEX_0F3859 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6110   },
6111
6112   /* PREFIX_VEX_0F385A */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6117   },
6118
6119   /* PREFIX_VEX_0F3878 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6124   },
6125
6126   /* PREFIX_VEX_0F3879 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6131   },
6132
6133   /* PREFIX_VEX_0F388C */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6138   },
6139
6140   /* PREFIX_VEX_0F388E */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6145   },
6146
6147   /* PREFIX_VEX_0F3890 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F3891 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F3892 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F3893 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F3896 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F3897 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F3898 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F3899 */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F389A */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F389B */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F389C */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F389D */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F389E */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F389F */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6243   },
6244
6245   /* PREFIX_VEX_0F38A6 */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6250     { Bad_Opcode },
6251   },
6252
6253   /* PREFIX_VEX_0F38A7 */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F38A8 */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F38A9 */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F38AA */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6279   },
6280
6281   /* PREFIX_VEX_0F38AB */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6286   },
6287
6288   /* PREFIX_VEX_0F38AC */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6293   },
6294
6295   /* PREFIX_VEX_0F38AD */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6300   },
6301
6302   /* PREFIX_VEX_0F38AE */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6307   },
6308
6309   /* PREFIX_VEX_0F38AF */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6314   },
6315
6316   /* PREFIX_VEX_0F38B6 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6321   },
6322
6323   /* PREFIX_VEX_0F38B7 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F38B8 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F38B9 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F38BA */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F38BB */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F38BC */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F38BD */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F38BE */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F38BF */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F38CF */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F38DB */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F38DC */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vaesenc",        { XM, Vex, EXx }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F38DD */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F38DE */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vaesdec",        { XM, Vex, EXx }, 0 },
6419   },
6420
6421   /* PREFIX_VEX_0F38DF */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6426   },
6427
6428   /* PREFIX_VEX_0F38F2 */
6429   {
6430     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6431   },
6432
6433   /* PREFIX_VEX_0F38F3_REG_1 */
6434   {
6435     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6436   },
6437
6438   /* PREFIX_VEX_0F38F3_REG_2 */
6439   {
6440     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6441   },
6442
6443   /* PREFIX_VEX_0F38F3_REG_3 */
6444   {
6445     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6446   },
6447
6448   /* PREFIX_VEX_0F38F5 */
6449   {
6450     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6451     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6454   },
6455
6456   /* PREFIX_VEX_0F38F6 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6462   },
6463
6464   /* PREFIX_VEX_0F38F7 */
6465   {
6466     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6467     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6468     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6469     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6470   },
6471
6472   /* PREFIX_VEX_0F3A00 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A01 */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A02 */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A04 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A05 */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A06 */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6512   },
6513
6514   /* PREFIX_VEX_0F3A08 */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A09 */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6526   },
6527
6528   /* PREFIX_VEX_0F3A0A */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A0B */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6540   },
6541
6542   /* PREFIX_VEX_0F3A0C */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A0D */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A0E */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A0F */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6568   },
6569
6570   /* PREFIX_VEX_0F3A14 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A15 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A16 */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A17 */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6596   },
6597
6598   /* PREFIX_VEX_0F3A18 */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A19 */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A1D */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6617   },
6618
6619   /* PREFIX_VEX_0F3A20 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3A21 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3A22 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A30 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A31 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A32 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A33 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A38 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A39 */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A40 */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6687   },
6688
6689   /* PREFIX_VEX_0F3A41 */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A42 */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A44 */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A46 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6715   },
6716
6717   /* PREFIX_VEX_0F3A48 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A49 */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A4A */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A4B */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3A4C */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6750   },
6751
6752   /* PREFIX_VEX_0F3A5C */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6757   },
6758
6759   /* PREFIX_VEX_0F3A5D */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6764   },
6765
6766   /* PREFIX_VEX_0F3A5E */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6771   },
6772
6773   /* PREFIX_VEX_0F3A5F */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6778   },
6779
6780   /* PREFIX_VEX_0F3A60 */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6785     { Bad_Opcode },
6786   },
6787
6788   /* PREFIX_VEX_0F3A61 */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6793   },
6794
6795   /* PREFIX_VEX_0F3A62 */
6796   {
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6800   },
6801
6802   /* PREFIX_VEX_0F3A63 */
6803   {
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6807   },
6808
6809   /* PREFIX_VEX_0F3A68 */
6810   {
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6814   },
6815
6816   /* PREFIX_VEX_0F3A69 */
6817   {
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6821   },
6822
6823   /* PREFIX_VEX_0F3A6A */
6824   {
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6828   },
6829
6830   /* PREFIX_VEX_0F3A6B */
6831   {
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6835   },
6836
6837   /* PREFIX_VEX_0F3A6C */
6838   {
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6842   },
6843
6844   /* PREFIX_VEX_0F3A6D */
6845   {
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6849   },
6850
6851   /* PREFIX_VEX_0F3A6E */
6852   {
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6856   },
6857
6858   /* PREFIX_VEX_0F3A6F */
6859   {
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6863   },
6864
6865   /* PREFIX_VEX_0F3A78 */
6866   {
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6870   },
6871
6872   /* PREFIX_VEX_0F3A79 */
6873   {
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6877   },
6878
6879   /* PREFIX_VEX_0F3A7A */
6880   {
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6884   },
6885
6886   /* PREFIX_VEX_0F3A7B */
6887   {
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6891   },
6892
6893   /* PREFIX_VEX_0F3A7C */
6894   {
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6898     { Bad_Opcode },
6899   },
6900
6901   /* PREFIX_VEX_0F3A7D */
6902   {
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6906   },
6907
6908   /* PREFIX_VEX_0F3A7E */
6909   {
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6913   },
6914
6915   /* PREFIX_VEX_0F3A7F */
6916   {
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6920   },
6921
6922   /* PREFIX_VEX_0F3ACE */
6923   {
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6927   },
6928
6929   /* PREFIX_VEX_0F3ACF */
6930   {
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6934   },
6935
6936   /* PREFIX_VEX_0F3ADF */
6937   {
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6941   },
6942
6943   /* PREFIX_VEX_0F3AF0 */
6944   {
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6949   },
6950
6951 #define NEED_PREFIX_TABLE
6952 #include "i386-dis-evex.h"
6953 #undef NEED_PREFIX_TABLE
6954 };
6955
6956 static const struct dis386 x86_64_table[][2] = {
6957   /* X86_64_06 */
6958   {
6959     { "pushP", { es }, 0 },
6960   },
6961
6962   /* X86_64_07 */
6963   {
6964     { "popP", { es }, 0 },
6965   },
6966
6967   /* X86_64_0D */
6968   {
6969     { "pushP", { cs }, 0 },
6970   },
6971
6972   /* X86_64_16 */
6973   {
6974     { "pushP", { ss }, 0 },
6975   },
6976
6977   /* X86_64_17 */
6978   {
6979     { "popP", { ss }, 0 },
6980   },
6981
6982   /* X86_64_1E */
6983   {
6984     { "pushP", { ds }, 0 },
6985   },
6986
6987   /* X86_64_1F */
6988   {
6989     { "popP", { ds }, 0 },
6990   },
6991
6992   /* X86_64_27 */
6993   {
6994     { "daa", { XX }, 0 },
6995   },
6996
6997   /* X86_64_2F */
6998   {
6999     { "das", { XX }, 0 },
7000   },
7001
7002   /* X86_64_37 */
7003   {
7004     { "aaa", { XX }, 0 },
7005   },
7006
7007   /* X86_64_3F */
7008   {
7009     { "aas", { XX }, 0 },
7010   },
7011
7012   /* X86_64_60 */
7013   {
7014     { "pushaP", { XX }, 0 },
7015   },
7016
7017   /* X86_64_61 */
7018   {
7019     { "popaP", { XX }, 0 },
7020   },
7021
7022   /* X86_64_62 */
7023   {
7024     { MOD_TABLE (MOD_62_32BIT) },
7025     { EVEX_TABLE (EVEX_0F) },
7026   },
7027
7028   /* X86_64_63 */
7029   {
7030     { "arpl", { Ew, Gw }, 0 },
7031     { "movs{lq|xd}", { Gv, Ed }, 0 },
7032   },
7033
7034   /* X86_64_6D */
7035   {
7036     { "ins{R|}", { Yzr, indirDX }, 0 },
7037     { "ins{G|}", { Yzr, indirDX }, 0 },
7038   },
7039
7040   /* X86_64_6F */
7041   {
7042     { "outs{R|}", { indirDXr, Xz }, 0 },
7043     { "outs{G|}", { indirDXr, Xz }, 0 },
7044   },
7045
7046   /* X86_64_82 */
7047   {
7048     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7049     { REG_TABLE (REG_80) },
7050   },
7051
7052   /* X86_64_9A */
7053   {
7054     { "Jcall{T|}", { Ap }, 0 },
7055   },
7056
7057   /* X86_64_C4 */
7058   {
7059     { MOD_TABLE (MOD_C4_32BIT) },
7060     { VEX_C4_TABLE (VEX_0F) },
7061   },
7062
7063   /* X86_64_C5 */
7064   {
7065     { MOD_TABLE (MOD_C5_32BIT) },
7066     { VEX_C5_TABLE (VEX_0F) },
7067   },
7068
7069   /* X86_64_CE */
7070   {
7071     { "into", { XX }, 0 },
7072   },
7073
7074   /* X86_64_D4 */
7075   {
7076     { "aam", { Ib }, 0 },
7077   },
7078
7079   /* X86_64_D5 */
7080   {
7081     { "aad", { Ib }, 0 },
7082   },
7083
7084   /* X86_64_E8 */
7085   {
7086     { "callP",          { Jv, BND }, 0 },
7087     { "call@",          { Jv, BND }, 0 }
7088   },
7089
7090   /* X86_64_E9 */
7091   {
7092     { "jmpP",           { Jv, BND }, 0 },
7093     { "jmp@",           { Jv, BND }, 0 }
7094   },
7095
7096   /* X86_64_EA */
7097   {
7098     { "Jjmp{T|}", { Ap }, 0 },
7099   },
7100
7101   /* X86_64_0F01_REG_0 */
7102   {
7103     { "sgdt{Q|IQ}", { M }, 0 },
7104     { "sgdt", { M }, 0 },
7105   },
7106
7107   /* X86_64_0F01_REG_1 */
7108   {
7109     { "sidt{Q|IQ}", { M }, 0 },
7110     { "sidt", { M }, 0 },
7111   },
7112
7113   /* X86_64_0F01_REG_2 */
7114   {
7115     { "lgdt{Q|Q}", { M }, 0 },
7116     { "lgdt", { M }, 0 },
7117   },
7118
7119   /* X86_64_0F01_REG_3 */
7120   {
7121     { "lidt{Q|Q}", { M }, 0 },
7122     { "lidt", { M }, 0 },
7123   },
7124 };
7125
7126 static const struct dis386 three_byte_table[][256] = {
7127
7128   /* THREE_BYTE_0F38 */
7129   {
7130     /* 00 */
7131     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7132     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7133     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7134     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7135     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7136     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7137     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7138     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7139     /* 08 */
7140     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7141     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7142     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7143     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* 10 */
7149     { PREFIX_TABLE (PREFIX_0F3810) },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { PREFIX_TABLE (PREFIX_0F3814) },
7154     { PREFIX_TABLE (PREFIX_0F3815) },
7155     { Bad_Opcode },
7156     { PREFIX_TABLE (PREFIX_0F3817) },
7157     /* 18 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7163     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7164     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7165     { Bad_Opcode },
7166     /* 20 */
7167     { PREFIX_TABLE (PREFIX_0F3820) },
7168     { PREFIX_TABLE (PREFIX_0F3821) },
7169     { PREFIX_TABLE (PREFIX_0F3822) },
7170     { PREFIX_TABLE (PREFIX_0F3823) },
7171     { PREFIX_TABLE (PREFIX_0F3824) },
7172     { PREFIX_TABLE (PREFIX_0F3825) },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 28 */
7176     { PREFIX_TABLE (PREFIX_0F3828) },
7177     { PREFIX_TABLE (PREFIX_0F3829) },
7178     { PREFIX_TABLE (PREFIX_0F382A) },
7179     { PREFIX_TABLE (PREFIX_0F382B) },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 30 */
7185     { PREFIX_TABLE (PREFIX_0F3830) },
7186     { PREFIX_TABLE (PREFIX_0F3831) },
7187     { PREFIX_TABLE (PREFIX_0F3832) },
7188     { PREFIX_TABLE (PREFIX_0F3833) },
7189     { PREFIX_TABLE (PREFIX_0F3834) },
7190     { PREFIX_TABLE (PREFIX_0F3835) },
7191     { Bad_Opcode },
7192     { PREFIX_TABLE (PREFIX_0F3837) },
7193     /* 38 */
7194     { PREFIX_TABLE (PREFIX_0F3838) },
7195     { PREFIX_TABLE (PREFIX_0F3839) },
7196     { PREFIX_TABLE (PREFIX_0F383A) },
7197     { PREFIX_TABLE (PREFIX_0F383B) },
7198     { PREFIX_TABLE (PREFIX_0F383C) },
7199     { PREFIX_TABLE (PREFIX_0F383D) },
7200     { PREFIX_TABLE (PREFIX_0F383E) },
7201     { PREFIX_TABLE (PREFIX_0F383F) },
7202     /* 40 */
7203     { PREFIX_TABLE (PREFIX_0F3840) },
7204     { PREFIX_TABLE (PREFIX_0F3841) },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 48 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 50 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 58 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 60 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 68 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 70 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 78 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 80 */
7275     { PREFIX_TABLE (PREFIX_0F3880) },
7276     { PREFIX_TABLE (PREFIX_0F3881) },
7277     { PREFIX_TABLE (PREFIX_0F3882) },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 88 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 90 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 98 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* a0 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* a8 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* b0 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* b8 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* c0 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* c8 */
7356     { PREFIX_TABLE (PREFIX_0F38C8) },
7357     { PREFIX_TABLE (PREFIX_0F38C9) },
7358     { PREFIX_TABLE (PREFIX_0F38CA) },
7359     { PREFIX_TABLE (PREFIX_0F38CB) },
7360     { PREFIX_TABLE (PREFIX_0F38CC) },
7361     { PREFIX_TABLE (PREFIX_0F38CD) },
7362     { Bad_Opcode },
7363     { PREFIX_TABLE (PREFIX_0F38CF) },
7364     /* d0 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* d8 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { PREFIX_TABLE (PREFIX_0F38DB) },
7378     { PREFIX_TABLE (PREFIX_0F38DC) },
7379     { PREFIX_TABLE (PREFIX_0F38DD) },
7380     { PREFIX_TABLE (PREFIX_0F38DE) },
7381     { PREFIX_TABLE (PREFIX_0F38DF) },
7382     /* e0 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* e8 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* f0 */
7401     { PREFIX_TABLE (PREFIX_0F38F0) },
7402     { PREFIX_TABLE (PREFIX_0F38F1) },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { PREFIX_TABLE (PREFIX_0F38F5) },
7407     { PREFIX_TABLE (PREFIX_0F38F6) },
7408     { Bad_Opcode },
7409     /* f8 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418   },
7419   /* THREE_BYTE_0F3A */
7420   {
7421     /* 00 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* 08 */
7431     { PREFIX_TABLE (PREFIX_0F3A08) },
7432     { PREFIX_TABLE (PREFIX_0F3A09) },
7433     { PREFIX_TABLE (PREFIX_0F3A0A) },
7434     { PREFIX_TABLE (PREFIX_0F3A0B) },
7435     { PREFIX_TABLE (PREFIX_0F3A0C) },
7436     { PREFIX_TABLE (PREFIX_0F3A0D) },
7437     { PREFIX_TABLE (PREFIX_0F3A0E) },
7438     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7439     /* 10 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { PREFIX_TABLE (PREFIX_0F3A14) },
7445     { PREFIX_TABLE (PREFIX_0F3A15) },
7446     { PREFIX_TABLE (PREFIX_0F3A16) },
7447     { PREFIX_TABLE (PREFIX_0F3A17) },
7448     /* 18 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* 20 */
7458     { PREFIX_TABLE (PREFIX_0F3A20) },
7459     { PREFIX_TABLE (PREFIX_0F3A21) },
7460     { PREFIX_TABLE (PREFIX_0F3A22) },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     /* 28 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* 30 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* 38 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* 40 */
7494     { PREFIX_TABLE (PREFIX_0F3A40) },
7495     { PREFIX_TABLE (PREFIX_0F3A41) },
7496     { PREFIX_TABLE (PREFIX_0F3A42) },
7497     { Bad_Opcode },
7498     { PREFIX_TABLE (PREFIX_0F3A44) },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* 48 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* 50 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* 58 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* 60 */
7530     { PREFIX_TABLE (PREFIX_0F3A60) },
7531     { PREFIX_TABLE (PREFIX_0F3A61) },
7532     { PREFIX_TABLE (PREFIX_0F3A62) },
7533     { PREFIX_TABLE (PREFIX_0F3A63) },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* 68 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 70 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* 78 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 80 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 88 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 90 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 98 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* a0 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* a8 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* b0 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* b8 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* c0 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* c8 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { PREFIX_TABLE (PREFIX_0F3ACC) },
7652     { Bad_Opcode },
7653     { PREFIX_TABLE (PREFIX_0F3ACE) },
7654     { PREFIX_TABLE (PREFIX_0F3ACF) },
7655     /* d0 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* d8 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { PREFIX_TABLE (PREFIX_0F3ADF) },
7673     /* e0 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* e8 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* f0 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* f8 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709   },
7710 };
7711
7712 static const struct dis386 xop_table[][256] = {
7713   /* XOP_08 */
7714   {
7715     /* 00 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* 08 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* 10 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* 18 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 20 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 28 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 30 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 38 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 40 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 48 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 50 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 58 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 60 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 68 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 70 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 78 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 80 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7866     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7867     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7868     /* 88 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7876     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7877     /* 90 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7884     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7885     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7886     /* 98 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7894     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7895     /* a0 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7899     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7903     { Bad_Opcode },
7904     /* a8 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* b0 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7921     { Bad_Opcode },
7922     /* b8 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* c0 */
7932     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7933     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7934     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7935     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* c8 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7946     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7947     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7948     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7949     /* d0 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* d8 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* e0 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* e8 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7983     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7984     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7985     /* f0 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* f8 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003   },
8004   /* XOP_09 */
8005   {
8006     /* 00 */
8007     { Bad_Opcode },
8008     { REG_TABLE (REG_XOP_TBM_01) },
8009     { REG_TABLE (REG_XOP_TBM_02) },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* 08 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* 10 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { REG_TABLE (REG_XOP_LWPCB) },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 18 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 20 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 28 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 30 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 38 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 40 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 48 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 50 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 58 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 60 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 68 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 70 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 78 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 80 */
8151     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8152     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8153     { "vfrczss",        { XM, EXd }, 0 },
8154     { "vfrczsd",        { XM, EXq }, 0 },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 88 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 90 */
8169     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8170     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8171     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8172     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8173     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8174     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8175     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8176     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8177     /* 98 */
8178     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8179     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8180     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8181     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* a0 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* a8 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* b0 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* b8 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* c0 */
8223     { Bad_Opcode },
8224     { "vphaddbw",       { XM, EXxmm }, 0 },
8225     { "vphaddbd",       { XM, EXxmm }, 0 },
8226     { "vphaddbq",       { XM, EXxmm }, 0 },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { "vphaddwd",       { XM, EXxmm }, 0 },
8230     { "vphaddwq",       { XM, EXxmm }, 0 },
8231     /* c8 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { "vphadddq",       { XM, EXxmm }, 0 },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* d0 */
8241     { Bad_Opcode },
8242     { "vphaddubw",      { XM, EXxmm }, 0 },
8243     { "vphaddubd",      { XM, EXxmm }, 0 },
8244     { "vphaddubq",      { XM, EXxmm }, 0 },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { "vphadduwd",      { XM, EXxmm }, 0 },
8248     { "vphadduwq",      { XM, EXxmm }, 0 },
8249     /* d8 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { "vphaddudq",      { XM, EXxmm }, 0 },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* e0 */
8259     { Bad_Opcode },
8260     { "vphsubbw",       { XM, EXxmm }, 0 },
8261     { "vphsubwd",       { XM, EXxmm }, 0 },
8262     { "vphsubdq",       { XM, EXxmm }, 0 },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* e8 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* f0 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* f8 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294   },
8295   /* XOP_0A */
8296   {
8297     /* 00 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* 08 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* 10 */
8316     { "bextr",  { Gv, Ev, Iq }, 0 },
8317     { Bad_Opcode },
8318     { REG_TABLE (REG_XOP_LWP) },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* 18 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* 20 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* 28 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* 30 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* 38 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* 40 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* 48 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* 50 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* 58 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* 60 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* 68 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* 70 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* 78 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 80 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 88 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     /* 90 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* 98 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* a0 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* a8 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* b0 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* b8 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* c0 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* c8 */
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     /* d0 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* d8 */
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     /* e0 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     /* e8 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* f0 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     /* f8 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585   },
8586 };
8587
8588 static const struct dis386 vex_table[][256] = {
8589   /* VEX_0F */
8590   {
8591     /* 00 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* 08 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     /* 10 */
8610     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8613     { MOD_TABLE (MOD_VEX_0F13) },
8614     { VEX_W_TABLE (VEX_W_0F14) },
8615     { VEX_W_TABLE (VEX_W_0F15) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8617     { MOD_TABLE (MOD_VEX_0F17) },
8618     /* 18 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     /* 20 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* 28 */
8637     { VEX_W_TABLE (VEX_W_0F28) },
8638     { VEX_W_TABLE (VEX_W_0F29) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8640     { MOD_TABLE (MOD_VEX_0F2B) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8645     /* 30 */
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     /* 38 */
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     /* 40 */
8664     { Bad_Opcode },
8665     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8667     { Bad_Opcode },
8668     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8672     /* 48 */
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* 50 */
8682     { MOD_TABLE (MOD_VEX_0F50) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8686     { "vandpX",         { XM, Vex, EXx }, 0 },
8687     { "vandnpX",        { XM, Vex, EXx }, 0 },
8688     { "vorpX",          { XM, Vex, EXx }, 0 },
8689     { "vxorpX",         { XM, Vex, EXx }, 0 },
8690     /* 58 */
8691     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8699     /* 60 */
8700     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8708     /* 68 */
8709     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8717     /* 70 */
8718     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8719     { REG_TABLE (REG_VEX_0F71) },
8720     { REG_TABLE (REG_VEX_0F72) },
8721     { REG_TABLE (REG_VEX_0F73) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8726     /* 78 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8735     /* 80 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* 88 */
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     /* 90 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     /* 98 */
8763     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     /* a0 */
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     /* a8 */
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { REG_TABLE (REG_VEX_0FAE) },
8788     { Bad_Opcode },
8789     /* b0 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     /* b8 */
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     /* c0 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8811     { Bad_Opcode },
8812     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8813     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8814     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8815     { Bad_Opcode },
8816     /* c8 */
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     /* d0 */
8826     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8827     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8828     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8830     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8831     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8832     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8834     /* d8 */
8835     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8840     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8841     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8843     /* e0 */
8844     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8852     /* e8 */
8853     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8861     /* f0 */
8862     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8870     /* f8 */
8871     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8878     { Bad_Opcode },
8879   },
8880   /* VEX_0F38 */
8881   {
8882     /* 00 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8891     /* 08 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8900     /* 10 */
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8909     /* 18 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8917     { Bad_Opcode },
8918     /* 20 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     /* 28 */
8928     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8936     /* 30 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8945     /* 38 */
8946     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8954     /* 40 */
8955     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8963     /* 48 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* 50 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* 58 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     /* 60 */
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     /* 68 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     /* 70 */
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     /* 78 */
9018     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     /* 80 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 88 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9041     { Bad_Opcode },
9042     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9043     { Bad_Opcode },
9044     /* 90 */
9045     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9053     /* 98 */
9054     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9062     /* a0 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9071     /* a8 */
9072     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9080     /* b0 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9089     /* b8 */
9090     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9098     /* c0 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* c8 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9116     /* d0 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* d8 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9134     /* e0 */
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* e8 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* f0 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9156     { REG_TABLE (REG_VEX_0F38F3) },
9157     { Bad_Opcode },
9158     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9161     /* f8 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170   },
9171   /* VEX_0F3A */
9172   {
9173     /* 00 */
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9177     { Bad_Opcode },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9181     { Bad_Opcode },
9182     /* 08 */
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9191     /* 10 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9200     /* 18 */
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* 20 */
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     /* 28 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     /* 30 */
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     /* 38 */
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     /* 40 */
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9249     { Bad_Opcode },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9251     { Bad_Opcode },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9253     { Bad_Opcode },
9254     /* 48 */
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9257     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* 50 */
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* 58 */
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9279     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9280     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9281     /* 60 */
9282     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     /* 68 */
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9299     /* 70 */
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     /* 78 */
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9317     /* 80 */
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     /* 88 */
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     /* 90 */
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     /* 98 */
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     /* a0 */
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     /* a8 */
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     /* b0 */
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     /* b8 */
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     /* c0 */
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     /* c8 */
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9406     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9407     /* d0 */
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     /* d8 */
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9425     /* e0 */
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     /* e8 */
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     /* f0 */
9444     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     /* f8 */
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461   },
9462 };
9463
9464 #define NEED_OPCODE_TABLE
9465 #include "i386-dis-evex.h"
9466 #undef NEED_OPCODE_TABLE
9467 static const struct dis386 vex_len_table[][2] = {
9468   /* VEX_LEN_0F10_P_1 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9471     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9472   },
9473
9474   /* VEX_LEN_0F10_P_3 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9477     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9478   },
9479
9480   /* VEX_LEN_0F11_P_1 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9483     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9484   },
9485
9486   /* VEX_LEN_0F11_P_3 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9489     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9490   },
9491
9492   /* VEX_LEN_0F12_P_0_M_0 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9495   },
9496
9497   /* VEX_LEN_0F12_P_0_M_1 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9500   },
9501
9502   /* VEX_LEN_0F12_P_2 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9505   },
9506
9507   /* VEX_LEN_0F13_M_0 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9510   },
9511
9512   /* VEX_LEN_0F16_P_0_M_0 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9515   },
9516
9517   /* VEX_LEN_0F16_P_0_M_1 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9520   },
9521
9522   /* VEX_LEN_0F16_P_2 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9525   },
9526
9527   /* VEX_LEN_0F17_M_0 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9530   },
9531
9532   /* VEX_LEN_0F2A_P_1 */
9533   {
9534     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9535     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9536   },
9537
9538   /* VEX_LEN_0F2A_P_3 */
9539   {
9540     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9541     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9542   },
9543
9544   /* VEX_LEN_0F2C_P_1 */
9545   {
9546     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9547     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9548   },
9549
9550   /* VEX_LEN_0F2C_P_3 */
9551   {
9552     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9553     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9554   },
9555
9556   /* VEX_LEN_0F2D_P_1 */
9557   {
9558     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9559     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9560   },
9561
9562   /* VEX_LEN_0F2D_P_3 */
9563   {
9564     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9565     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9566   },
9567
9568   /* VEX_LEN_0F2E_P_0 */
9569   {
9570     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9571     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9572   },
9573
9574   /* VEX_LEN_0F2E_P_2 */
9575   {
9576     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9577     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9578   },
9579
9580   /* VEX_LEN_0F2F_P_0 */
9581   {
9582     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9583     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9584   },
9585
9586   /* VEX_LEN_0F2F_P_2 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9589     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F41_P_0 */
9593   {
9594     { Bad_Opcode },
9595     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9596   },
9597   /* VEX_LEN_0F41_P_2 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9601   },
9602   /* VEX_LEN_0F42_P_0 */
9603   {
9604     { Bad_Opcode },
9605     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9606   },
9607   /* VEX_LEN_0F42_P_2 */
9608   {
9609     { Bad_Opcode },
9610     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9611   },
9612   /* VEX_LEN_0F44_P_0 */
9613   {
9614     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9615   },
9616   /* VEX_LEN_0F44_P_2 */
9617   {
9618     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9619   },
9620   /* VEX_LEN_0F45_P_0 */
9621   {
9622     { Bad_Opcode },
9623     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9624   },
9625   /* VEX_LEN_0F45_P_2 */
9626   {
9627     { Bad_Opcode },
9628     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9629   },
9630   /* VEX_LEN_0F46_P_0 */
9631   {
9632     { Bad_Opcode },
9633     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9634   },
9635   /* VEX_LEN_0F46_P_2 */
9636   {
9637     { Bad_Opcode },
9638     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9639   },
9640   /* VEX_LEN_0F47_P_0 */
9641   {
9642     { Bad_Opcode },
9643     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9644   },
9645   /* VEX_LEN_0F47_P_2 */
9646   {
9647     { Bad_Opcode },
9648     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9649   },
9650   /* VEX_LEN_0F4A_P_0 */
9651   {
9652     { Bad_Opcode },
9653     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9654   },
9655   /* VEX_LEN_0F4A_P_2 */
9656   {
9657     { Bad_Opcode },
9658     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9659   },
9660   /* VEX_LEN_0F4B_P_0 */
9661   {
9662     { Bad_Opcode },
9663     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9664   },
9665   /* VEX_LEN_0F4B_P_2 */
9666   {
9667     { Bad_Opcode },
9668     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9669   },
9670
9671   /* VEX_LEN_0F51_P_1 */
9672   {
9673     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9674     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9675   },
9676
9677   /* VEX_LEN_0F51_P_3 */
9678   {
9679     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9680     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9681   },
9682
9683   /* VEX_LEN_0F52_P_1 */
9684   {
9685     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9686     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9687   },
9688
9689   /* VEX_LEN_0F53_P_1 */
9690   {
9691     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9692     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9693   },
9694
9695   /* VEX_LEN_0F58_P_1 */
9696   {
9697     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9698     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9699   },
9700
9701   /* VEX_LEN_0F58_P_3 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9704     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9705   },
9706
9707   /* VEX_LEN_0F59_P_1 */
9708   {
9709     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9710     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9711   },
9712
9713   /* VEX_LEN_0F59_P_3 */
9714   {
9715     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9716     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9717   },
9718
9719   /* VEX_LEN_0F5A_P_1 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9722     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9723   },
9724
9725   /* VEX_LEN_0F5A_P_3 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9728     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9729   },
9730
9731   /* VEX_LEN_0F5C_P_1 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9734     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9735   },
9736
9737   /* VEX_LEN_0F5C_P_3 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9740     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9741   },
9742
9743   /* VEX_LEN_0F5D_P_1 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9746     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9747   },
9748
9749   /* VEX_LEN_0F5D_P_3 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9752     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9753   },
9754
9755   /* VEX_LEN_0F5E_P_1 */
9756   {
9757     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9758     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9759   },
9760
9761   /* VEX_LEN_0F5E_P_3 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9764     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9765   },
9766
9767   /* VEX_LEN_0F5F_P_1 */
9768   {
9769     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9770     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9771   },
9772
9773   /* VEX_LEN_0F5F_P_3 */
9774   {
9775     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9776     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9777   },
9778
9779   /* VEX_LEN_0F6E_P_2 */
9780   {
9781     { "vmovK",          { XMScalar, Edq }, 0 },
9782     { "vmovK",          { XMScalar, Edq }, 0 },
9783   },
9784
9785   /* VEX_LEN_0F7E_P_1 */
9786   {
9787     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9788     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9789   },
9790
9791   /* VEX_LEN_0F7E_P_2 */
9792   {
9793     { "vmovK",          { Edq, XMScalar }, 0 },
9794     { "vmovK",          { Edq, XMScalar }, 0 },
9795   },
9796
9797   /* VEX_LEN_0F90_P_0 */
9798   {
9799     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9800   },
9801
9802   /* VEX_LEN_0F90_P_2 */
9803   {
9804     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9805   },
9806
9807   /* VEX_LEN_0F91_P_0 */
9808   {
9809     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9810   },
9811
9812   /* VEX_LEN_0F91_P_2 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9815   },
9816
9817   /* VEX_LEN_0F92_P_0 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9820   },
9821
9822   /* VEX_LEN_0F92_P_2 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9825   },
9826
9827   /* VEX_LEN_0F92_P_3 */
9828   {
9829     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9830   },
9831
9832   /* VEX_LEN_0F93_P_0 */
9833   {
9834     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9835   },
9836
9837   /* VEX_LEN_0F93_P_2 */
9838   {
9839     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9840   },
9841
9842   /* VEX_LEN_0F93_P_3 */
9843   {
9844     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9845   },
9846
9847   /* VEX_LEN_0F98_P_0 */
9848   {
9849     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9850   },
9851
9852   /* VEX_LEN_0F98_P_2 */
9853   {
9854     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9855   },
9856
9857   /* VEX_LEN_0F99_P_0 */
9858   {
9859     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9860   },
9861
9862   /* VEX_LEN_0F99_P_2 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9865   },
9866
9867   /* VEX_LEN_0FAE_R_2_M_0 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9870   },
9871
9872   /* VEX_LEN_0FAE_R_3_M_0 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9875   },
9876
9877   /* VEX_LEN_0FC2_P_1 */
9878   {
9879     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9880     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9881   },
9882
9883   /* VEX_LEN_0FC2_P_3 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9886     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9887   },
9888
9889   /* VEX_LEN_0FC4_P_2 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9892   },
9893
9894   /* VEX_LEN_0FC5_P_2 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9897   },
9898
9899   /* VEX_LEN_0FD6_P_2 */
9900   {
9901     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9902     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9903   },
9904
9905   /* VEX_LEN_0FF7_P_2 */
9906   {
9907     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9908   },
9909
9910   /* VEX_LEN_0F3816_P_2 */
9911   {
9912     { Bad_Opcode },
9913     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9914   },
9915
9916   /* VEX_LEN_0F3819_P_2 */
9917   {
9918     { Bad_Opcode },
9919     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9920   },
9921
9922   /* VEX_LEN_0F381A_P_2_M_0 */
9923   {
9924     { Bad_Opcode },
9925     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9926   },
9927
9928   /* VEX_LEN_0F3836_P_2 */
9929   {
9930     { Bad_Opcode },
9931     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9932   },
9933
9934   /* VEX_LEN_0F3841_P_2 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9937   },
9938
9939   /* VEX_LEN_0F385A_P_2_M_0 */
9940   {
9941     { Bad_Opcode },
9942     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9943   },
9944
9945   /* VEX_LEN_0F38DB_P_2 */
9946   {
9947     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9948   },
9949
9950   /* VEX_LEN_0F38F2_P_0 */
9951   {
9952     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9953   },
9954
9955   /* VEX_LEN_0F38F3_R_1_P_0 */
9956   {
9957     { "blsrS",          { VexGdq, Edq }, 0 },
9958   },
9959
9960   /* VEX_LEN_0F38F3_R_2_P_0 */
9961   {
9962     { "blsmskS",        { VexGdq, Edq }, 0 },
9963   },
9964
9965   /* VEX_LEN_0F38F3_R_3_P_0 */
9966   {
9967     { "blsiS",          { VexGdq, Edq }, 0 },
9968   },
9969
9970   /* VEX_LEN_0F38F5_P_0 */
9971   {
9972     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9973   },
9974
9975   /* VEX_LEN_0F38F5_P_1 */
9976   {
9977     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9978   },
9979
9980   /* VEX_LEN_0F38F5_P_3 */
9981   {
9982     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9983   },
9984
9985   /* VEX_LEN_0F38F6_P_3 */
9986   {
9987     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9988   },
9989
9990   /* VEX_LEN_0F38F7_P_0 */
9991   {
9992     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9993   },
9994
9995   /* VEX_LEN_0F38F7_P_1 */
9996   {
9997     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9998   },
9999
10000   /* VEX_LEN_0F38F7_P_2 */
10001   {
10002     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10003   },
10004
10005   /* VEX_LEN_0F38F7_P_3 */
10006   {
10007     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10008   },
10009
10010   /* VEX_LEN_0F3A00_P_2 */
10011   {
10012     { Bad_Opcode },
10013     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10014   },
10015
10016   /* VEX_LEN_0F3A01_P_2 */
10017   {
10018     { Bad_Opcode },
10019     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10020   },
10021
10022   /* VEX_LEN_0F3A06_P_2 */
10023   {
10024     { Bad_Opcode },
10025     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10026   },
10027
10028   /* VEX_LEN_0F3A0A_P_2 */
10029   {
10030     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10031     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10032   },
10033
10034   /* VEX_LEN_0F3A0B_P_2 */
10035   {
10036     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10037     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10038   },
10039
10040   /* VEX_LEN_0F3A14_P_2 */
10041   {
10042     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10043   },
10044
10045   /* VEX_LEN_0F3A15_P_2 */
10046   {
10047     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10048   },
10049
10050   /* VEX_LEN_0F3A16_P_2  */
10051   {
10052     { "vpextrK",        { Edq, XM, Ib }, 0 },
10053   },
10054
10055   /* VEX_LEN_0F3A17_P_2 */
10056   {
10057     { "vextractps",     { Edqd, XM, Ib }, 0 },
10058   },
10059
10060   /* VEX_LEN_0F3A18_P_2 */
10061   {
10062     { Bad_Opcode },
10063     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10064   },
10065
10066   /* VEX_LEN_0F3A19_P_2 */
10067   {
10068     { Bad_Opcode },
10069     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10070   },
10071
10072   /* VEX_LEN_0F3A20_P_2 */
10073   {
10074     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10075   },
10076
10077   /* VEX_LEN_0F3A21_P_2 */
10078   {
10079     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10080   },
10081
10082   /* VEX_LEN_0F3A22_P_2 */
10083   {
10084     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10085   },
10086
10087   /* VEX_LEN_0F3A30_P_2 */
10088   {
10089     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10090   },
10091
10092   /* VEX_LEN_0F3A31_P_2 */
10093   {
10094     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10095   },
10096
10097   /* VEX_LEN_0F3A32_P_2 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10100   },
10101
10102   /* VEX_LEN_0F3A33_P_2 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10105   },
10106
10107   /* VEX_LEN_0F3A38_P_2 */
10108   {
10109     { Bad_Opcode },
10110     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10111   },
10112
10113   /* VEX_LEN_0F3A39_P_2 */
10114   {
10115     { Bad_Opcode },
10116     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10117   },
10118
10119   /* VEX_LEN_0F3A41_P_2 */
10120   {
10121     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10122   },
10123
10124   /* VEX_LEN_0F3A46_P_2 */
10125   {
10126     { Bad_Opcode },
10127     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10128   },
10129
10130   /* VEX_LEN_0F3A60_P_2 */
10131   {
10132     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10133   },
10134
10135   /* VEX_LEN_0F3A61_P_2 */
10136   {
10137     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10138   },
10139
10140   /* VEX_LEN_0F3A62_P_2 */
10141   {
10142     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10143   },
10144
10145   /* VEX_LEN_0F3A63_P_2 */
10146   {
10147     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10148   },
10149
10150   /* VEX_LEN_0F3A6A_P_2 */
10151   {
10152     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10153   },
10154
10155   /* VEX_LEN_0F3A6B_P_2 */
10156   {
10157     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10158   },
10159
10160   /* VEX_LEN_0F3A6E_P_2 */
10161   {
10162     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10163   },
10164
10165   /* VEX_LEN_0F3A6F_P_2 */
10166   {
10167     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10168   },
10169
10170   /* VEX_LEN_0F3A7A_P_2 */
10171   {
10172     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10173   },
10174
10175   /* VEX_LEN_0F3A7B_P_2 */
10176   {
10177     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10178   },
10179
10180   /* VEX_LEN_0F3A7E_P_2 */
10181   {
10182     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10183   },
10184
10185   /* VEX_LEN_0F3A7F_P_2 */
10186   {
10187     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10188   },
10189
10190   /* VEX_LEN_0F3ADF_P_2 */
10191   {
10192     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10193   },
10194
10195   /* VEX_LEN_0F3AF0_P_3 */
10196   {
10197     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10198   },
10199
10200   /* VEX_LEN_0FXOP_08_CC */
10201   {
10202      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10203   },
10204
10205   /* VEX_LEN_0FXOP_08_CD */
10206   {
10207      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10208   },
10209
10210   /* VEX_LEN_0FXOP_08_CE */
10211   {
10212      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10213   },
10214
10215   /* VEX_LEN_0FXOP_08_CF */
10216   {
10217      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10218   },
10219
10220   /* VEX_LEN_0FXOP_08_EC */
10221   {
10222      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10223   },
10224
10225   /* VEX_LEN_0FXOP_08_ED */
10226   {
10227      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10228   },
10229
10230   /* VEX_LEN_0FXOP_08_EE */
10231   {
10232      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10233   },
10234
10235   /* VEX_LEN_0FXOP_08_EF */
10236   {
10237      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10238   },
10239
10240   /* VEX_LEN_0FXOP_09_80 */
10241   {
10242     { "vfrczps",        { XM, EXxmm }, 0 },
10243     { "vfrczps",        { XM, EXymmq }, 0 },
10244   },
10245
10246   /* VEX_LEN_0FXOP_09_81 */
10247   {
10248     { "vfrczpd",        { XM, EXxmm }, 0 },
10249     { "vfrczpd",        { XM, EXymmq }, 0 },
10250   },
10251 };
10252
10253 static const struct dis386 vex_w_table[][2] = {
10254   {
10255     /* VEX_W_0F10_P_0 */
10256     { "vmovups",        { XM, EXx }, 0 },
10257   },
10258   {
10259     /* VEX_W_0F10_P_1 */
10260     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10261   },
10262   {
10263     /* VEX_W_0F10_P_2 */
10264     { "vmovupd",        { XM, EXx }, 0 },
10265   },
10266   {
10267     /* VEX_W_0F10_P_3 */
10268     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10269   },
10270   {
10271     /* VEX_W_0F11_P_0 */
10272     { "vmovups",        { EXxS, XM }, 0 },
10273   },
10274   {
10275     /* VEX_W_0F11_P_1 */
10276     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10277   },
10278   {
10279     /* VEX_W_0F11_P_2 */
10280     { "vmovupd",        { EXxS, XM }, 0 },
10281   },
10282   {
10283     /* VEX_W_0F11_P_3 */
10284     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10285   },
10286   {
10287     /* VEX_W_0F12_P_0_M_0 */
10288     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10289   },
10290   {
10291     /* VEX_W_0F12_P_0_M_1 */
10292     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10293   },
10294   {
10295     /* VEX_W_0F12_P_1 */
10296     { "vmovsldup",      { XM, EXx }, 0 },
10297   },
10298   {
10299     /* VEX_W_0F12_P_2 */
10300     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10301   },
10302   {
10303     /* VEX_W_0F12_P_3 */
10304     { "vmovddup",       { XM, EXymmq }, 0 },
10305   },
10306   {
10307     /* VEX_W_0F13_M_0 */
10308     { "vmovlpX",        { EXq, XM }, 0 },
10309   },
10310   {
10311     /* VEX_W_0F14 */
10312     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10313   },
10314   {
10315     /* VEX_W_0F15 */
10316     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F16_P_0_M_0 */
10320     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F16_P_0_M_1 */
10324     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F16_P_1 */
10328     { "vmovshdup",      { XM, EXx }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F16_P_2 */
10332     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F17_M_0 */
10336     { "vmovhpX",        { EXq, XM }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F28 */
10340     { "vmovapX",        { XM, EXx }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F29 */
10344     { "vmovapX",        { EXxS, XM }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F2B_M_0 */
10348     { "vmovntpX",       { Mx, XM }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F2E_P_0 */
10352     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F2E_P_2 */
10356     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F2F_P_0 */
10360     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F2F_P_2 */
10364     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F41_P_0_LEN_1 */
10368     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10369     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10370   },
10371   {
10372     /* VEX_W_0F41_P_2_LEN_1 */
10373     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10374     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10375   },
10376   {
10377     /* VEX_W_0F42_P_0_LEN_1 */
10378     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10379     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10380   },
10381   {
10382     /* VEX_W_0F42_P_2_LEN_1 */
10383     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10384     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10385   },
10386   {
10387     /* VEX_W_0F44_P_0_LEN_0 */
10388     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10389     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10390   },
10391   {
10392     /* VEX_W_0F44_P_2_LEN_0 */
10393     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10394     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10395   },
10396   {
10397     /* VEX_W_0F45_P_0_LEN_1 */
10398     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10399     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10400   },
10401   {
10402     /* VEX_W_0F45_P_2_LEN_1 */
10403     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10404     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10405   },
10406   {
10407     /* VEX_W_0F46_P_0_LEN_1 */
10408     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10409     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10410   },
10411   {
10412     /* VEX_W_0F46_P_2_LEN_1 */
10413     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10414     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10415   },
10416   {
10417     /* VEX_W_0F47_P_0_LEN_1 */
10418     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10419     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10420   },
10421   {
10422     /* VEX_W_0F47_P_2_LEN_1 */
10423     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10424     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10425   },
10426   {
10427     /* VEX_W_0F4A_P_0_LEN_1 */
10428     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10429     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10430   },
10431   {
10432     /* VEX_W_0F4A_P_2_LEN_1 */
10433     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10434     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10435   },
10436   {
10437     /* VEX_W_0F4B_P_0_LEN_1 */
10438     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10439     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10440   },
10441   {
10442     /* VEX_W_0F4B_P_2_LEN_1 */
10443     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10444   },
10445   {
10446     /* VEX_W_0F50_M_0 */
10447     { "vmovmskpX",      { Gdq, XS }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F51_P_0 */
10451     { "vsqrtps",        { XM, EXx }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F51_P_1 */
10455     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F51_P_2  */
10459     { "vsqrtpd",        { XM, EXx }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F51_P_3 */
10463     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F52_P_0 */
10467     { "vrsqrtps",       { XM, EXx }, 0 },
10468   },
10469   {
10470     /* VEX_W_0F52_P_1 */
10471     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F53_P_0  */
10475     { "vrcpps",         { XM, EXx }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F53_P_1  */
10479     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F58_P_0  */
10483     { "vaddps",         { XM, Vex, EXx }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F58_P_1  */
10487     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F58_P_2  */
10491     { "vaddpd",         { XM, Vex, EXx }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F58_P_3  */
10495     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F59_P_0  */
10499     { "vmulps",         { XM, Vex, EXx }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F59_P_1  */
10503     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F59_P_2  */
10507     { "vmulpd",         { XM, Vex, EXx }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F59_P_3  */
10511     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F5A_P_0  */
10515     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F5A_P_1  */
10519     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F5A_P_3  */
10523     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F5B_P_0  */
10527     { "vcvtdq2ps",      { XM, EXx }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F5B_P_1  */
10531     { "vcvttps2dq",     { XM, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F5B_P_2  */
10535     { "vcvtps2dq",      { XM, EXx }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F5C_P_0  */
10539     { "vsubps",         { XM, Vex, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F5C_P_1  */
10543     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F5C_P_2  */
10547     { "vsubpd",         { XM, Vex, EXx }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F5C_P_3  */
10551     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F5D_P_0  */
10555     { "vminps",         { XM, Vex, EXx }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F5D_P_1  */
10559     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F5D_P_2  */
10563     { "vminpd",         { XM, Vex, EXx }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F5D_P_3  */
10567     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F5E_P_0  */
10571     { "vdivps",         { XM, Vex, EXx }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F5E_P_1  */
10575     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F5E_P_2  */
10579     { "vdivpd",         { XM, Vex, EXx }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F5E_P_3  */
10583     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F5F_P_0  */
10587     { "vmaxps",         { XM, Vex, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F5F_P_1  */
10591     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F5F_P_2  */
10595     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F5F_P_3  */
10599     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F60_P_2  */
10603     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F61_P_2  */
10607     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F62_P_2  */
10611     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F63_P_2  */
10615     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F64_P_2  */
10619     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F65_P_2  */
10623     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F66_P_2  */
10627     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F67_P_2  */
10631     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F68_P_2  */
10635     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F69_P_2  */
10639     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F6A_P_2  */
10643     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F6B_P_2  */
10647     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F6C_P_2  */
10651     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F6D_P_2  */
10655     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F6F_P_1  */
10659     { "vmovdqu",        { XM, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F6F_P_2  */
10663     { "vmovdqa",        { XM, EXx }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F70_P_1 */
10667     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F70_P_2 */
10671     { "vpshufd",        { XM, EXx, Ib }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F70_P_3 */
10675     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F71_R_2_P_2  */
10679     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F71_R_4_P_2  */
10683     { "vpsraw",         { Vex, XS, Ib }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F71_R_6_P_2  */
10687     { "vpsllw",         { Vex, XS, Ib }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F72_R_2_P_2  */
10691     { "vpsrld",         { Vex, XS, Ib }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F72_R_4_P_2  */
10695     { "vpsrad",         { Vex, XS, Ib }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F72_R_6_P_2  */
10699     { "vpslld",         { Vex, XS, Ib }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F73_R_2_P_2  */
10703     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F73_R_3_P_2  */
10707     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F73_R_6_P_2  */
10711     { "vpsllq",         { Vex, XS, Ib }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F73_R_7_P_2  */
10715     { "vpslldq",        { Vex, XS, Ib }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F74_P_2 */
10719     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F75_P_2 */
10723     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F76_P_2 */
10727     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F77_P_0 */
10731     { "",               { VZERO }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F7C_P_2 */
10735     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F7C_P_3 */
10739     { "vhaddps",        { XM, Vex, EXx }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F7D_P_2 */
10743     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F7D_P_3 */
10747     { "vhsubps",        { XM, Vex, EXx }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F7E_P_1 */
10751     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F7F_P_1 */
10755     { "vmovdqu",        { EXxS, XM }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F7F_P_2 */
10759     { "vmovdqa",        { EXxS, XM }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F90_P_0_LEN_0 */
10763     { "kmovw",          { MaskG, MaskE }, 0 },
10764     { "kmovq",          { MaskG, MaskE }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F90_P_2_LEN_0 */
10768     { "kmovb",          { MaskG, MaskBDE }, 0 },
10769     { "kmovd",          { MaskG, MaskBDE }, 0 },
10770   },
10771   {
10772     /* VEX_W_0F91_P_0_LEN_0 */
10773     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10774     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10775   },
10776   {
10777     /* VEX_W_0F91_P_2_LEN_0 */
10778     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10779     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10780   },
10781   {
10782     /* VEX_W_0F92_P_0_LEN_0 */
10783     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10784   },
10785   {
10786     /* VEX_W_0F92_P_2_LEN_0 */
10787     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10788   },
10789   {
10790     /* VEX_W_0F92_P_3_LEN_0 */
10791     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10792     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10793   },
10794   {
10795     /* VEX_W_0F93_P_0_LEN_0 */
10796     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10797   },
10798   {
10799     /* VEX_W_0F93_P_2_LEN_0 */
10800     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10801   },
10802   {
10803     /* VEX_W_0F93_P_3_LEN_0 */
10804     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10805     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10806   },
10807   {
10808     /* VEX_W_0F98_P_0_LEN_0 */
10809     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10810     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10811   },
10812   {
10813     /* VEX_W_0F98_P_2_LEN_0 */
10814     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10815     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10816   },
10817   {
10818     /* VEX_W_0F99_P_0_LEN_0 */
10819     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10820     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10821   },
10822   {
10823     /* VEX_W_0F99_P_2_LEN_0 */
10824     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10825     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10826   },
10827   {
10828     /* VEX_W_0FAE_R_2_M_0 */
10829     { "vldmxcsr",       { Md }, 0 },
10830   },
10831   {
10832     /* VEX_W_0FAE_R_3_M_0 */
10833     { "vstmxcsr",       { Md }, 0 },
10834   },
10835   {
10836     /* VEX_W_0FC2_P_0 */
10837     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10838   },
10839   {
10840     /* VEX_W_0FC2_P_1 */
10841     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10842   },
10843   {
10844     /* VEX_W_0FC2_P_2 */
10845     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10846   },
10847   {
10848     /* VEX_W_0FC2_P_3 */
10849     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10850   },
10851   {
10852     /* VEX_W_0FC4_P_2 */
10853     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10854   },
10855   {
10856     /* VEX_W_0FC5_P_2 */
10857     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10858   },
10859   {
10860     /* VEX_W_0FD0_P_2 */
10861     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10862   },
10863   {
10864     /* VEX_W_0FD0_P_3 */
10865     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10866   },
10867   {
10868     /* VEX_W_0FD1_P_2 */
10869     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10870   },
10871   {
10872     /* VEX_W_0FD2_P_2 */
10873     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10874   },
10875   {
10876     /* VEX_W_0FD3_P_2 */
10877     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10878   },
10879   {
10880     /* VEX_W_0FD4_P_2 */
10881     { "vpaddq",         { XM, Vex, EXx }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FD5_P_2 */
10885     { "vpmullw",        { XM, Vex, EXx }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FD6_P_2 */
10889     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FD7_P_2_M_1 */
10893     { "vpmovmskb",      { Gdq, XS }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FD8_P_2 */
10897     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FD9_P_2 */
10901     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FDA_P_2 */
10905     { "vpminub",        { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FDB_P_2 */
10909     { "vpand",          { XM, Vex, EXx }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FDC_P_2 */
10913     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FDD_P_2 */
10917     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FDE_P_2 */
10921     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FDF_P_2 */
10925     { "vpandn",         { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FE0_P_2  */
10929     { "vpavgb",         { XM, Vex, EXx }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FE1_P_2  */
10933     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FE2_P_2  */
10937     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FE3_P_2  */
10941     { "vpavgw",         { XM, Vex, EXx }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FE4_P_2  */
10945     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FE5_P_2  */
10949     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FE6_P_1  */
10953     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FE6_P_2  */
10957     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FE6_P_3  */
10961     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FE7_P_2_M_0 */
10965     { "vmovntdq",       { Mx, XM }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FE8_P_2  */
10969     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FE9_P_2  */
10973     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FEA_P_2  */
10977     { "vpminsw",        { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FEB_P_2  */
10981     { "vpor",           { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FEC_P_2  */
10985     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FED_P_2  */
10989     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FEE_P_2  */
10993     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FEF_P_2  */
10997     { "vpxor",          { XM, Vex, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FF0_P_3_M_0 */
11001     { "vlddqu",         { XM, M }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FF1_P_2 */
11005     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FF2_P_2 */
11009     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FF3_P_2 */
11013     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FF4_P_2 */
11017     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FF5_P_2 */
11021     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FF6_P_2 */
11025     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FF7_P_2 */
11029     { "vmaskmovdqu",    { XM, XS }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FF8_P_2 */
11033     { "vpsubb",         { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FF9_P_2 */
11037     { "vpsubw",         { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FFA_P_2 */
11041     { "vpsubd",         { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FFB_P_2 */
11045     { "vpsubq",         { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FFC_P_2 */
11049     { "vpaddb",         { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FFD_P_2 */
11053     { "vpaddw",         { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FFE_P_2 */
11057     { "vpaddd",         { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0F3800_P_2  */
11061     { "vpshufb",        { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0F3801_P_2  */
11065     { "vphaddw",        { XM, Vex, EXx }, 0 },
11066   },
11067   {
11068     /* VEX_W_0F3802_P_2  */
11069     { "vphaddd",        { XM, Vex, EXx }, 0 },
11070   },
11071   {
11072     /* VEX_W_0F3803_P_2  */
11073     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11074   },
11075   {
11076     /* VEX_W_0F3804_P_2  */
11077     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11078   },
11079   {
11080     /* VEX_W_0F3805_P_2  */
11081     { "vphsubw",        { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0F3806_P_2  */
11085     { "vphsubd",        { XM, Vex, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0F3807_P_2  */
11089     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0F3808_P_2  */
11093     { "vpsignb",        { XM, Vex, EXx }, 0 },
11094   },
11095   {
11096     /* VEX_W_0F3809_P_2  */
11097     { "vpsignw",        { XM, Vex, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0F380A_P_2  */
11101     { "vpsignd",        { XM, Vex, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0F380B_P_2  */
11105     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0F380C_P_2  */
11109     { "vpermilps",      { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0F380D_P_2  */
11113     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F380E_P_2  */
11117     { "vtestps",        { XM, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F380F_P_2  */
11121     { "vtestpd",        { XM, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F3816_P_2  */
11125     { "vpermps",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F3817_P_2 */
11129     { "vptest",         { XM, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F3818_P_2 */
11133     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F3819_P_2 */
11137     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F381A_P_2_M_0 */
11141     { "vbroadcastf128", { XM, Mxmm }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F381C_P_2 */
11145     { "vpabsb",         { XM, EXx }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F381D_P_2 */
11149     { "vpabsw",         { XM, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F381E_P_2 */
11153     { "vpabsd",         { XM, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F3820_P_2 */
11157     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F3821_P_2 */
11161     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F3822_P_2 */
11165     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F3823_P_2 */
11169     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F3824_P_2 */
11173     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F3825_P_2 */
11177     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F3828_P_2 */
11181     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F3829_P_2 */
11185     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F382A_P_2_M_0 */
11189     { "vmovntdqa",      { XM, Mx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F382B_P_2 */
11193     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F382C_P_2_M_0 */
11197     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F382D_P_2_M_0 */
11201     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F382E_P_2_M_0 */
11205     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F382F_P_2_M_0 */
11209     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F3830_P_2 */
11213     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3831_P_2 */
11217     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3832_P_2 */
11221     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3833_P_2 */
11225     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3834_P_2 */
11229     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3835_P_2 */
11233     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3836_P_2  */
11237     { "vpermd",         { XM, Vex, EXx }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F3837_P_2 */
11241     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F3838_P_2 */
11245     { "vpminsb",        { XM, Vex, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F3839_P_2 */
11249     { "vpminsd",        { XM, Vex, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F383A_P_2 */
11253     { "vpminuw",        { XM, Vex, EXx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F383B_P_2 */
11257     { "vpminud",        { XM, Vex, EXx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F383C_P_2 */
11261     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F383D_P_2 */
11265     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F383E_P_2 */
11269     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F383F_P_2 */
11273     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F3840_P_2 */
11277     { "vpmulld",        { XM, Vex, EXx }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F3841_P_2 */
11281     { "vphminposuw",    { XM, EXx }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F3846_P_2 */
11285     { "vpsravd",        { XM, Vex, EXx }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F3858_P_2 */
11289     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F3859_P_2 */
11293     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F385A_P_2_M_0 */
11297     { "vbroadcasti128", { XM, Mxmm }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F3878_P_2 */
11301     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3879_P_2 */
11305     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F38CF_P_2 */
11309     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F38DB_P_2 */
11313     { "vaesimc",        { XM, EXx }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F3A00_P_2 */
11317     { Bad_Opcode },
11318     { "vpermq",         { XM, EXx, Ib }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3A01_P_2 */
11322     { Bad_Opcode },
11323     { "vpermpd",        { XM, EXx, Ib }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F3A02_P_2 */
11327     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F3A04_P_2 */
11331     { "vpermilps",      { XM, EXx, Ib }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F3A05_P_2 */
11335     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3A06_P_2 */
11339     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3A08_P_2 */
11343     { "vroundps",       { XM, EXx, Ib }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F3A09_P_2 */
11347     { "vroundpd",       { XM, EXx, Ib }, 0 },
11348   },
11349   {
11350     /* VEX_W_0F3A0A_P_2 */
11351     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11352   },
11353   {
11354     /* VEX_W_0F3A0B_P_2 */
11355     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F3A0C_P_2 */
11359     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11360   },
11361   {
11362     /* VEX_W_0F3A0D_P_2 */
11363     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F3A0E_P_2 */
11367     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F3A0F_P_2 */
11371     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F3A14_P_2 */
11375     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3A15_P_2 */
11379     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3A18_P_2 */
11383     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A19_P_2 */
11387     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A20_P_2 */
11391     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3A21_P_2 */
11395     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F3A30_P_2_LEN_0 */
11399     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11400     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11401   },
11402   {
11403     /* VEX_W_0F3A31_P_2_LEN_0 */
11404     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11405     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11406   },
11407   {
11408     /* VEX_W_0F3A32_P_2_LEN_0 */
11409     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11410     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11411   },
11412   {
11413     /* VEX_W_0F3A33_P_2_LEN_0 */
11414     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11415     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11416   },
11417   {
11418     /* VEX_W_0F3A38_P_2 */
11419     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F3A39_P_2 */
11423     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3A40_P_2 */
11427     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A41_P_2 */
11431     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A42_P_2 */
11435     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A46_P_2 */
11439     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A48_P_2 */
11443     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11444     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11445   },
11446   {
11447     /* VEX_W_0F3A49_P_2 */
11448     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11449     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11450   },
11451   {
11452     /* VEX_W_0F3A4A_P_2 */
11453     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11454   },
11455   {
11456     /* VEX_W_0F3A4B_P_2 */
11457     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11458   },
11459   {
11460     /* VEX_W_0F3A4C_P_2 */
11461     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11462   },
11463   {
11464     /* VEX_W_0F3A62_P_2 */
11465     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11466   },
11467   {
11468     /* VEX_W_0F3A63_P_2 */
11469     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11470   },
11471   {
11472     /* VEX_W_0F3ACE_P_2 */
11473     { Bad_Opcode },
11474     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11475   },
11476   {
11477     /* VEX_W_0F3ACF_P_2 */
11478     { Bad_Opcode },
11479     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11480   },
11481   {
11482     /* VEX_W_0F3ADF_P_2 */
11483     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11484   },
11485 #define NEED_VEX_W_TABLE
11486 #include "i386-dis-evex.h"
11487 #undef NEED_VEX_W_TABLE
11488 };
11489
11490 static const struct dis386 mod_table[][2] = {
11491   {
11492     /* MOD_8D */
11493     { "leaS",           { Gv, M }, 0 },
11494   },
11495   {
11496     /* MOD_C6_REG_7 */
11497     { Bad_Opcode },
11498     { RM_TABLE (RM_C6_REG_7) },
11499   },
11500   {
11501     /* MOD_C7_REG_7 */
11502     { Bad_Opcode },
11503     { RM_TABLE (RM_C7_REG_7) },
11504   },
11505   {
11506     /* MOD_FF_REG_3 */
11507     { "Jcall^", { indirEp }, 0 },
11508   },
11509   {
11510     /* MOD_FF_REG_5 */
11511     { "Jjmp^", { indirEp }, 0 },
11512   },
11513   {
11514     /* MOD_0F01_REG_0 */
11515     { X86_64_TABLE (X86_64_0F01_REG_0) },
11516     { RM_TABLE (RM_0F01_REG_0) },
11517   },
11518   {
11519     /* MOD_0F01_REG_1 */
11520     { X86_64_TABLE (X86_64_0F01_REG_1) },
11521     { RM_TABLE (RM_0F01_REG_1) },
11522   },
11523   {
11524     /* MOD_0F01_REG_2 */
11525     { X86_64_TABLE (X86_64_0F01_REG_2) },
11526     { RM_TABLE (RM_0F01_REG_2) },
11527   },
11528   {
11529     /* MOD_0F01_REG_3 */
11530     { X86_64_TABLE (X86_64_0F01_REG_3) },
11531     { RM_TABLE (RM_0F01_REG_3) },
11532   },
11533   {
11534     /* MOD_0F01_REG_5 */
11535     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11536     { RM_TABLE (RM_0F01_REG_5) },
11537   },
11538   {
11539     /* MOD_0F01_REG_7 */
11540     { "invlpg",         { Mb }, 0 },
11541     { RM_TABLE (RM_0F01_REG_7) },
11542   },
11543   {
11544     /* MOD_0F12_PREFIX_0 */
11545     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11546     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11547   },
11548   {
11549     /* MOD_0F13 */
11550     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11551   },
11552   {
11553     /* MOD_0F16_PREFIX_0 */
11554     { "movhps",         { XM, EXq }, 0 },
11555     { "movlhps",        { XM, EXq }, 0 },
11556   },
11557   {
11558     /* MOD_0F17 */
11559     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11560   },
11561   {
11562     /* MOD_0F18_REG_0 */
11563     { "prefetchnta",    { Mb }, 0 },
11564   },
11565   {
11566     /* MOD_0F18_REG_1 */
11567     { "prefetcht0",     { Mb }, 0 },
11568   },
11569   {
11570     /* MOD_0F18_REG_2 */
11571     { "prefetcht1",     { Mb }, 0 },
11572   },
11573   {
11574     /* MOD_0F18_REG_3 */
11575     { "prefetcht2",     { Mb }, 0 },
11576   },
11577   {
11578     /* MOD_0F18_REG_4 */
11579     { "nop/reserved",   { Mb }, 0 },
11580   },
11581   {
11582     /* MOD_0F18_REG_5 */
11583     { "nop/reserved",   { Mb }, 0 },
11584   },
11585   {
11586     /* MOD_0F18_REG_6 */
11587     { "nop/reserved",   { Mb }, 0 },
11588   },
11589   {
11590     /* MOD_0F18_REG_7 */
11591     { "nop/reserved",   { Mb }, 0 },
11592   },
11593   {
11594     /* MOD_0F1A_PREFIX_0 */
11595     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11596     { "nopQ",           { Ev }, 0 },
11597   },
11598   {
11599     /* MOD_0F1B_PREFIX_0 */
11600     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11601     { "nopQ",           { Ev }, 0 },
11602   },
11603   {
11604     /* MOD_0F1B_PREFIX_1 */
11605     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11606     { "nopQ",           { Ev }, 0 },
11607   },
11608   {
11609     /* MOD_0F1E_PREFIX_1 */
11610     { "nopQ",           { Ev }, 0 },
11611     { REG_TABLE (REG_0F1E_MOD_3) },
11612   },
11613   {
11614     /* MOD_0F24 */
11615     { Bad_Opcode },
11616     { "movL",           { Rd, Td }, 0 },
11617   },
11618   {
11619     /* MOD_0F26 */
11620     { Bad_Opcode },
11621     { "movL",           { Td, Rd }, 0 },
11622   },
11623   {
11624     /* MOD_0F2B_PREFIX_0 */
11625     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11626   },
11627   {
11628     /* MOD_0F2B_PREFIX_1 */
11629     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11630   },
11631   {
11632     /* MOD_0F2B_PREFIX_2 */
11633     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11634   },
11635   {
11636     /* MOD_0F2B_PREFIX_3 */
11637     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11638   },
11639   {
11640     /* MOD_0F51 */
11641     { Bad_Opcode },
11642     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11643   },
11644   {
11645     /* MOD_0F71_REG_2 */
11646     { Bad_Opcode },
11647     { "psrlw",          { MS, Ib }, 0 },
11648   },
11649   {
11650     /* MOD_0F71_REG_4 */
11651     { Bad_Opcode },
11652     { "psraw",          { MS, Ib }, 0 },
11653   },
11654   {
11655     /* MOD_0F71_REG_6 */
11656     { Bad_Opcode },
11657     { "psllw",          { MS, Ib }, 0 },
11658   },
11659   {
11660     /* MOD_0F72_REG_2 */
11661     { Bad_Opcode },
11662     { "psrld",          { MS, Ib }, 0 },
11663   },
11664   {
11665     /* MOD_0F72_REG_4 */
11666     { Bad_Opcode },
11667     { "psrad",          { MS, Ib }, 0 },
11668   },
11669   {
11670     /* MOD_0F72_REG_6 */
11671     { Bad_Opcode },
11672     { "pslld",          { MS, Ib }, 0 },
11673   },
11674   {
11675     /* MOD_0F73_REG_2 */
11676     { Bad_Opcode },
11677     { "psrlq",          { MS, Ib }, 0 },
11678   },
11679   {
11680     /* MOD_0F73_REG_3 */
11681     { Bad_Opcode },
11682     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11683   },
11684   {
11685     /* MOD_0F73_REG_6 */
11686     { Bad_Opcode },
11687     { "psllq",          { MS, Ib }, 0 },
11688   },
11689   {
11690     /* MOD_0F73_REG_7 */
11691     { Bad_Opcode },
11692     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11693   },
11694   {
11695     /* MOD_0FAE_REG_0 */
11696     { "fxsave",         { FXSAVE }, 0 },
11697     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11698   },
11699   {
11700     /* MOD_0FAE_REG_1 */
11701     { "fxrstor",        { FXSAVE }, 0 },
11702     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11703   },
11704   {
11705     /* MOD_0FAE_REG_2 */
11706     { "ldmxcsr",        { Md }, 0 },
11707     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11708   },
11709   {
11710     /* MOD_0FAE_REG_3 */
11711     { "stmxcsr",        { Md }, 0 },
11712     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11713   },
11714   {
11715     /* MOD_0FAE_REG_4 */
11716     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11717     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11718   },
11719   {
11720     /* MOD_0FAE_REG_5 */
11721     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11722     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11723   },
11724   {
11725     /* MOD_0FAE_REG_6 */
11726     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11727     { RM_TABLE (RM_0FAE_REG_6) },
11728   },
11729   {
11730     /* MOD_0FAE_REG_7 */
11731     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11732     { RM_TABLE (RM_0FAE_REG_7) },
11733   },
11734   {
11735     /* MOD_0FB2 */
11736     { "lssS",           { Gv, Mp }, 0 },
11737   },
11738   {
11739     /* MOD_0FB4 */
11740     { "lfsS",           { Gv, Mp }, 0 },
11741   },
11742   {
11743     /* MOD_0FB5 */
11744     { "lgsS",           { Gv, Mp }, 0 },
11745   },
11746   {
11747     /* MOD_0FC3 */
11748     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11749   },
11750   {
11751     /* MOD_0FC7_REG_3 */
11752     { "xrstors",        { FXSAVE }, 0 },
11753   },
11754   {
11755     /* MOD_0FC7_REG_4 */
11756     { "xsavec",         { FXSAVE }, 0 },
11757   },
11758   {
11759     /* MOD_0FC7_REG_5 */
11760     { "xsaves",         { FXSAVE }, 0 },
11761   },
11762   {
11763     /* MOD_0FC7_REG_6 */
11764     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11765     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11766   },
11767   {
11768     /* MOD_0FC7_REG_7 */
11769     { "vmptrst",        { Mq }, 0 },
11770     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11771   },
11772   {
11773     /* MOD_0FD7 */
11774     { Bad_Opcode },
11775     { "pmovmskb",       { Gdq, MS }, 0 },
11776   },
11777   {
11778     /* MOD_0FE7_PREFIX_2 */
11779     { "movntdq",        { Mx, XM }, 0 },
11780   },
11781   {
11782     /* MOD_0FF0_PREFIX_3 */
11783     { "lddqu",          { XM, M }, 0 },
11784   },
11785   {
11786     /* MOD_0F382A_PREFIX_2 */
11787     { "movntdqa",       { XM, Mx }, 0 },
11788   },
11789   {
11790     /* MOD_0F38F5_PREFIX_2 */
11791     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11792   },
11793   {
11794     /* MOD_0F38F6_PREFIX_0 */
11795     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11796   },
11797   {
11798     /* MOD_62_32BIT */
11799     { "bound{S|}",      { Gv, Ma }, 0 },
11800     { EVEX_TABLE (EVEX_0F) },
11801   },
11802   {
11803     /* MOD_C4_32BIT */
11804     { "lesS",           { Gv, Mp }, 0 },
11805     { VEX_C4_TABLE (VEX_0F) },
11806   },
11807   {
11808     /* MOD_C5_32BIT */
11809     { "ldsS",           { Gv, Mp }, 0 },
11810     { VEX_C5_TABLE (VEX_0F) },
11811   },
11812   {
11813     /* MOD_VEX_0F12_PREFIX_0 */
11814     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11815     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11816   },
11817   {
11818     /* MOD_VEX_0F13 */
11819     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11820   },
11821   {
11822     /* MOD_VEX_0F16_PREFIX_0 */
11823     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11824     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11825   },
11826   {
11827     /* MOD_VEX_0F17 */
11828     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11829   },
11830   {
11831     /* MOD_VEX_0F2B */
11832     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11833   },
11834   {
11835     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11836     { Bad_Opcode },
11837     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11838   },
11839   {
11840     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11841     { Bad_Opcode },
11842     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11843   },
11844   {
11845     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11846     { Bad_Opcode },
11847     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11848   },
11849   {
11850     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11851     { Bad_Opcode },
11852     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11853   },
11854   {
11855     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11856     { Bad_Opcode },
11857     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11858   },
11859   {
11860     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11861     { Bad_Opcode },
11862     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11863   },
11864   {
11865     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11866     { Bad_Opcode },
11867     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11868   },
11869   {
11870     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11871     { Bad_Opcode },
11872     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11873   },
11874   {
11875     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11876     { Bad_Opcode },
11877     { "knotw",          { MaskG, MaskR }, 0 },
11878   },
11879   {
11880     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11881     { Bad_Opcode },
11882     { "knotq",          { MaskG, MaskR }, 0 },
11883   },
11884   {
11885     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11886     { Bad_Opcode },
11887     { "knotb",          { MaskG, MaskR }, 0 },
11888   },
11889   {
11890     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11891     { Bad_Opcode },
11892     { "knotd",          { MaskG, MaskR }, 0 },
11893   },
11894   {
11895     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11896     { Bad_Opcode },
11897     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11898   },
11899   {
11900     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11901     { Bad_Opcode },
11902     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11903   },
11904   {
11905     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11906     { Bad_Opcode },
11907     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11908   },
11909   {
11910     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11911     { Bad_Opcode },
11912     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11913   },
11914  {
11915     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11916     { Bad_Opcode },
11917     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11918   },
11919   {
11920     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11921     { Bad_Opcode },
11922     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11923   },
11924   {
11925     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11926     { Bad_Opcode },
11927     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11928   },
11929   {
11930     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11931     { Bad_Opcode },
11932     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11933   },
11934   {
11935     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11936     { Bad_Opcode },
11937     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11938   },
11939   {
11940     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11941     { Bad_Opcode },
11942     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11943   },
11944   {
11945     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11946     { Bad_Opcode },
11947     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11948   },
11949   {
11950     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11951     { Bad_Opcode },
11952     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11953   },
11954   {
11955     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11956     { Bad_Opcode },
11957     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11958   },
11959   {
11960     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11961     { Bad_Opcode },
11962     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11963   },
11964   {
11965     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11966     { Bad_Opcode },
11967     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11968   },
11969   {
11970     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11971     { Bad_Opcode },
11972     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11973   },
11974   {
11975     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11976     { Bad_Opcode },
11977     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11978   },
11979   {
11980     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11981     { Bad_Opcode },
11982     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11983   },
11984   {
11985     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11986     { Bad_Opcode },
11987     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11988   },
11989   {
11990     /* MOD_VEX_0F50 */
11991     { Bad_Opcode },
11992     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11993   },
11994   {
11995     /* MOD_VEX_0F71_REG_2 */
11996     { Bad_Opcode },
11997     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11998   },
11999   {
12000     /* MOD_VEX_0F71_REG_4 */
12001     { Bad_Opcode },
12002     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12003   },
12004   {
12005     /* MOD_VEX_0F71_REG_6 */
12006     { Bad_Opcode },
12007     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12008   },
12009   {
12010     /* MOD_VEX_0F72_REG_2 */
12011     { Bad_Opcode },
12012     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12013   },
12014   {
12015     /* MOD_VEX_0F72_REG_4 */
12016     { Bad_Opcode },
12017     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12018   },
12019   {
12020     /* MOD_VEX_0F72_REG_6 */
12021     { Bad_Opcode },
12022     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12023   },
12024   {
12025     /* MOD_VEX_0F73_REG_2 */
12026     { Bad_Opcode },
12027     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12028   },
12029   {
12030     /* MOD_VEX_0F73_REG_3 */
12031     { Bad_Opcode },
12032     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12033   },
12034   {
12035     /* MOD_VEX_0F73_REG_6 */
12036     { Bad_Opcode },
12037     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12038   },
12039   {
12040     /* MOD_VEX_0F73_REG_7 */
12041     { Bad_Opcode },
12042     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12043   },
12044   {
12045     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12046     { "kmovw",          { Ew, MaskG }, 0 },
12047     { Bad_Opcode },
12048   },
12049   {
12050     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12051     { "kmovq",          { Eq, MaskG }, 0 },
12052     { Bad_Opcode },
12053   },
12054   {
12055     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12056     { "kmovb",          { Eb, MaskG }, 0 },
12057     { Bad_Opcode },
12058   },
12059   {
12060     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12061     { "kmovd",          { Ed, MaskG }, 0 },
12062     { Bad_Opcode },
12063   },
12064   {
12065     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12066     { Bad_Opcode },
12067     { "kmovw",          { MaskG, Rdq }, 0 },
12068   },
12069   {
12070     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12071     { Bad_Opcode },
12072     { "kmovb",          { MaskG, Rdq }, 0 },
12073   },
12074   {
12075     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12076     { Bad_Opcode },
12077     { "kmovd",          { MaskG, Rdq }, 0 },
12078   },
12079   {
12080     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12081     { Bad_Opcode },
12082     { "kmovq",          { MaskG, Rdq }, 0 },
12083   },
12084   {
12085     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12086     { Bad_Opcode },
12087     { "kmovw",          { Gdq, MaskR }, 0 },
12088   },
12089   {
12090     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12091     { Bad_Opcode },
12092     { "kmovb",          { Gdq, MaskR }, 0 },
12093   },
12094   {
12095     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12096     { Bad_Opcode },
12097     { "kmovd",          { Gdq, MaskR }, 0 },
12098   },
12099   {
12100     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12101     { Bad_Opcode },
12102     { "kmovq",          { Gdq, MaskR }, 0 },
12103   },
12104   {
12105     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12106     { Bad_Opcode },
12107     { "kortestw", { MaskG, MaskR }, 0 },
12108   },
12109   {
12110     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12111     { Bad_Opcode },
12112     { "kortestq", { MaskG, MaskR }, 0 },
12113   },
12114   {
12115     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12116     { Bad_Opcode },
12117     { "kortestb", { MaskG, MaskR }, 0 },
12118   },
12119   {
12120     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12121     { Bad_Opcode },
12122     { "kortestd", { MaskG, MaskR }, 0 },
12123   },
12124   {
12125     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12126     { Bad_Opcode },
12127     { "ktestw", { MaskG, MaskR }, 0 },
12128   },
12129   {
12130     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12131     { Bad_Opcode },
12132     { "ktestq", { MaskG, MaskR }, 0 },
12133   },
12134   {
12135     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12136     { Bad_Opcode },
12137     { "ktestb", { MaskG, MaskR }, 0 },
12138   },
12139   {
12140     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12141     { Bad_Opcode },
12142     { "ktestd", { MaskG, MaskR }, 0 },
12143   },
12144   {
12145     /* MOD_VEX_0FAE_REG_2 */
12146     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12147   },
12148   {
12149     /* MOD_VEX_0FAE_REG_3 */
12150     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12151   },
12152   {
12153     /* MOD_VEX_0FD7_PREFIX_2 */
12154     { Bad_Opcode },
12155     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12156   },
12157   {
12158     /* MOD_VEX_0FE7_PREFIX_2 */
12159     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12160   },
12161   {
12162     /* MOD_VEX_0FF0_PREFIX_3 */
12163     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12164   },
12165   {
12166     /* MOD_VEX_0F381A_PREFIX_2 */
12167     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12168   },
12169   {
12170     /* MOD_VEX_0F382A_PREFIX_2 */
12171     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12172   },
12173   {
12174     /* MOD_VEX_0F382C_PREFIX_2 */
12175     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12176   },
12177   {
12178     /* MOD_VEX_0F382D_PREFIX_2 */
12179     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12180   },
12181   {
12182     /* MOD_VEX_0F382E_PREFIX_2 */
12183     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12184   },
12185   {
12186     /* MOD_VEX_0F382F_PREFIX_2 */
12187     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12188   },
12189   {
12190     /* MOD_VEX_0F385A_PREFIX_2 */
12191     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12192   },
12193   {
12194     /* MOD_VEX_0F388C_PREFIX_2 */
12195     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12196   },
12197   {
12198     /* MOD_VEX_0F388E_PREFIX_2 */
12199     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12200   },
12201   {
12202     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12203     { Bad_Opcode },
12204     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12205   },
12206   {
12207     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12208     { Bad_Opcode },
12209     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12210   },
12211   {
12212     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12213     { Bad_Opcode },
12214     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12215   },
12216   {
12217     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12218     { Bad_Opcode },
12219     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12220   },
12221   {
12222     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12223     { Bad_Opcode },
12224     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12225   },
12226   {
12227     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12228     { Bad_Opcode },
12229     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12230   },
12231   {
12232     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12233     { Bad_Opcode },
12234     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12235   },
12236   {
12237     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12238     { Bad_Opcode },
12239     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12240   },
12241 #define NEED_MOD_TABLE
12242 #include "i386-dis-evex.h"
12243 #undef NEED_MOD_TABLE
12244 };
12245
12246 static const struct dis386 rm_table[][8] = {
12247   {
12248     /* RM_C6_REG_7 */
12249     { "xabort",         { Skip_MODRM, Ib }, 0 },
12250   },
12251   {
12252     /* RM_C7_REG_7 */
12253     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12254   },
12255   {
12256     /* RM_0F01_REG_0 */
12257     { Bad_Opcode },
12258     { "vmcall",         { Skip_MODRM }, 0 },
12259     { "vmlaunch",       { Skip_MODRM }, 0 },
12260     { "vmresume",       { Skip_MODRM }, 0 },
12261     { "vmxoff",         { Skip_MODRM }, 0 },
12262     { "pconfig",        { Skip_MODRM }, 0 },
12263   },
12264   {
12265     /* RM_0F01_REG_1 */
12266     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12267     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12268     { "clac",           { Skip_MODRM }, 0 },
12269     { "stac",           { Skip_MODRM }, 0 },
12270     { Bad_Opcode },
12271     { Bad_Opcode },
12272     { Bad_Opcode },
12273     { "encls",          { Skip_MODRM }, 0 },
12274   },
12275   {
12276     /* RM_0F01_REG_2 */
12277     { "xgetbv",         { Skip_MODRM }, 0 },
12278     { "xsetbv",         { Skip_MODRM }, 0 },
12279     { Bad_Opcode },
12280     { Bad_Opcode },
12281     { "vmfunc",         { Skip_MODRM }, 0 },
12282     { "xend",           { Skip_MODRM }, 0 },
12283     { "xtest",          { Skip_MODRM }, 0 },
12284     { "enclu",          { Skip_MODRM }, 0 },
12285   },
12286   {
12287     /* RM_0F01_REG_3 */
12288     { "vmrun",          { Skip_MODRM }, 0 },
12289     { "vmmcall",        { Skip_MODRM }, 0 },
12290     { "vmload",         { Skip_MODRM }, 0 },
12291     { "vmsave",         { Skip_MODRM }, 0 },
12292     { "stgi",           { Skip_MODRM }, 0 },
12293     { "clgi",           { Skip_MODRM }, 0 },
12294     { "skinit",         { Skip_MODRM }, 0 },
12295     { "invlpga",        { Skip_MODRM }, 0 },
12296   },
12297   {
12298     /* RM_0F01_REG_5 */
12299     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12300     { Bad_Opcode },
12301     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12302     { Bad_Opcode },
12303     { Bad_Opcode },
12304     { Bad_Opcode },
12305     { "rdpkru",         { Skip_MODRM }, 0 },
12306     { "wrpkru",         { Skip_MODRM }, 0 },
12307   },
12308   {
12309     /* RM_0F01_REG_7 */
12310     { "swapgs",         { Skip_MODRM }, 0  },
12311     { "rdtscp",         { Skip_MODRM }, 0  },
12312     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12313     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12314     { "clzero",         { Skip_MODRM }, 0  },
12315   },
12316   {
12317     /* RM_0F1E_MOD_3_REG_7 */
12318     { "nopQ",           { Ev }, 0 },
12319     { "nopQ",           { Ev }, 0 },
12320     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12321     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12322     { "nopQ",           { Ev }, 0 },
12323     { "nopQ",           { Ev }, 0 },
12324     { "nopQ",           { Ev }, 0 },
12325     { "nopQ",           { Ev }, 0 },
12326   },
12327   {
12328     /* RM_0FAE_REG_6 */
12329     { "mfence",         { Skip_MODRM }, 0 },
12330   },
12331   {
12332     /* RM_0FAE_REG_7 */
12333     { "sfence",         { Skip_MODRM }, 0 },
12334
12335   },
12336 };
12337
12338 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12339
12340 /* We use the high bit to indicate different name for the same
12341    prefix.  */
12342 #define REP_PREFIX      (0xf3 | 0x100)
12343 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12344 #define XRELEASE_PREFIX (0xf3 | 0x400)
12345 #define BND_PREFIX      (0xf2 | 0x400)
12346 #define NOTRACK_PREFIX  (0x3e | 0x100)
12347
12348 static int
12349 ckprefix (void)
12350 {
12351   int newrex, i, length;
12352   rex = 0;
12353   rex_ignored = 0;
12354   prefixes = 0;
12355   used_prefixes = 0;
12356   rex_used = 0;
12357   last_lock_prefix = -1;
12358   last_repz_prefix = -1;
12359   last_repnz_prefix = -1;
12360   last_data_prefix = -1;
12361   last_addr_prefix = -1;
12362   last_rex_prefix = -1;
12363   last_seg_prefix = -1;
12364   fwait_prefix = -1;
12365   active_seg_prefix = 0;
12366   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12367     all_prefixes[i] = 0;
12368   i = 0;
12369   length = 0;
12370   /* The maximum instruction length is 15bytes.  */
12371   while (length < MAX_CODE_LENGTH - 1)
12372     {
12373       FETCH_DATA (the_info, codep + 1);
12374       newrex = 0;
12375       switch (*codep)
12376         {
12377         /* REX prefixes family.  */
12378         case 0x40:
12379         case 0x41:
12380         case 0x42:
12381         case 0x43:
12382         case 0x44:
12383         case 0x45:
12384         case 0x46:
12385         case 0x47:
12386         case 0x48:
12387         case 0x49:
12388         case 0x4a:
12389         case 0x4b:
12390         case 0x4c:
12391         case 0x4d:
12392         case 0x4e:
12393         case 0x4f:
12394           if (address_mode == mode_64bit)
12395             newrex = *codep;
12396           else
12397             return 1;
12398           last_rex_prefix = i;
12399           break;
12400         case 0xf3:
12401           prefixes |= PREFIX_REPZ;
12402           last_repz_prefix = i;
12403           break;
12404         case 0xf2:
12405           prefixes |= PREFIX_REPNZ;
12406           last_repnz_prefix = i;
12407           break;
12408         case 0xf0:
12409           prefixes |= PREFIX_LOCK;
12410           last_lock_prefix = i;
12411           break;
12412         case 0x2e:
12413           prefixes |= PREFIX_CS;
12414           last_seg_prefix = i;
12415           active_seg_prefix = PREFIX_CS;
12416           break;
12417         case 0x36:
12418           prefixes |= PREFIX_SS;
12419           last_seg_prefix = i;
12420           active_seg_prefix = PREFIX_SS;
12421           break;
12422         case 0x3e:
12423           prefixes |= PREFIX_DS;
12424           last_seg_prefix = i;
12425           active_seg_prefix = PREFIX_DS;
12426           break;
12427         case 0x26:
12428           prefixes |= PREFIX_ES;
12429           last_seg_prefix = i;
12430           active_seg_prefix = PREFIX_ES;
12431           break;
12432         case 0x64:
12433           prefixes |= PREFIX_FS;
12434           last_seg_prefix = i;
12435           active_seg_prefix = PREFIX_FS;
12436           break;
12437         case 0x65:
12438           prefixes |= PREFIX_GS;
12439           last_seg_prefix = i;
12440           active_seg_prefix = PREFIX_GS;
12441           break;
12442         case 0x66:
12443           prefixes |= PREFIX_DATA;
12444           last_data_prefix = i;
12445           break;
12446         case 0x67:
12447           prefixes |= PREFIX_ADDR;
12448           last_addr_prefix = i;
12449           break;
12450         case FWAIT_OPCODE:
12451           /* fwait is really an instruction.  If there are prefixes
12452              before the fwait, they belong to the fwait, *not* to the
12453              following instruction.  */
12454           fwait_prefix = i;
12455           if (prefixes || rex)
12456             {
12457               prefixes |= PREFIX_FWAIT;
12458               codep++;
12459               /* This ensures that the previous REX prefixes are noticed
12460                  as unused prefixes, as in the return case below.  */
12461               rex_used = rex;
12462               return 1;
12463             }
12464           prefixes = PREFIX_FWAIT;
12465           break;
12466         default:
12467           return 1;
12468         }
12469       /* Rex is ignored when followed by another prefix.  */
12470       if (rex)
12471         {
12472           rex_used = rex;
12473           return 1;
12474         }
12475       if (*codep != FWAIT_OPCODE)
12476         all_prefixes[i++] = *codep;
12477       rex = newrex;
12478       codep++;
12479       length++;
12480     }
12481   return 0;
12482 }
12483
12484 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12485    prefix byte.  */
12486
12487 static const char *
12488 prefix_name (int pref, int sizeflag)
12489 {
12490   static const char *rexes [16] =
12491     {
12492       "rex",            /* 0x40 */
12493       "rex.B",          /* 0x41 */
12494       "rex.X",          /* 0x42 */
12495       "rex.XB",         /* 0x43 */
12496       "rex.R",          /* 0x44 */
12497       "rex.RB",         /* 0x45 */
12498       "rex.RX",         /* 0x46 */
12499       "rex.RXB",        /* 0x47 */
12500       "rex.W",          /* 0x48 */
12501       "rex.WB",         /* 0x49 */
12502       "rex.WX",         /* 0x4a */
12503       "rex.WXB",        /* 0x4b */
12504       "rex.WR",         /* 0x4c */
12505       "rex.WRB",        /* 0x4d */
12506       "rex.WRX",        /* 0x4e */
12507       "rex.WRXB",       /* 0x4f */
12508     };
12509
12510   switch (pref)
12511     {
12512     /* REX prefixes family.  */
12513     case 0x40:
12514     case 0x41:
12515     case 0x42:
12516     case 0x43:
12517     case 0x44:
12518     case 0x45:
12519     case 0x46:
12520     case 0x47:
12521     case 0x48:
12522     case 0x49:
12523     case 0x4a:
12524     case 0x4b:
12525     case 0x4c:
12526     case 0x4d:
12527     case 0x4e:
12528     case 0x4f:
12529       return rexes [pref - 0x40];
12530     case 0xf3:
12531       return "repz";
12532     case 0xf2:
12533       return "repnz";
12534     case 0xf0:
12535       return "lock";
12536     case 0x2e:
12537       return "cs";
12538     case 0x36:
12539       return "ss";
12540     case 0x3e:
12541       return "ds";
12542     case 0x26:
12543       return "es";
12544     case 0x64:
12545       return "fs";
12546     case 0x65:
12547       return "gs";
12548     case 0x66:
12549       return (sizeflag & DFLAG) ? "data16" : "data32";
12550     case 0x67:
12551       if (address_mode == mode_64bit)
12552         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12553       else
12554         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12555     case FWAIT_OPCODE:
12556       return "fwait";
12557     case REP_PREFIX:
12558       return "rep";
12559     case XACQUIRE_PREFIX:
12560       return "xacquire";
12561     case XRELEASE_PREFIX:
12562       return "xrelease";
12563     case BND_PREFIX:
12564       return "bnd";
12565     case NOTRACK_PREFIX:
12566       return "notrack";
12567     default:
12568       return NULL;
12569     }
12570 }
12571
12572 static char op_out[MAX_OPERANDS][100];
12573 static int op_ad, op_index[MAX_OPERANDS];
12574 static int two_source_ops;
12575 static bfd_vma op_address[MAX_OPERANDS];
12576 static bfd_vma op_riprel[MAX_OPERANDS];
12577 static bfd_vma start_pc;
12578
12579 /*
12580  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12581  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12582  *   section of the "Virtual 8086 Mode" chapter.)
12583  * 'pc' should be the address of this instruction, it will
12584  *   be used to print the target address if this is a relative jump or call
12585  * The function returns the length of this instruction in bytes.
12586  */
12587
12588 static char intel_syntax;
12589 static char intel_mnemonic = !SYSV386_COMPAT;
12590 static char open_char;
12591 static char close_char;
12592 static char separator_char;
12593 static char scale_char;
12594
12595 enum x86_64_isa
12596 {
12597   amd64 = 0,
12598   intel64
12599 };
12600
12601 static enum x86_64_isa isa64;
12602
12603 /* Here for backwards compatibility.  When gdb stops using
12604    print_insn_i386_att and print_insn_i386_intel these functions can
12605    disappear, and print_insn_i386 be merged into print_insn.  */
12606 int
12607 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12608 {
12609   intel_syntax = 0;
12610
12611   return print_insn (pc, info);
12612 }
12613
12614 int
12615 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12616 {
12617   intel_syntax = 1;
12618
12619   return print_insn (pc, info);
12620 }
12621
12622 int
12623 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12624 {
12625   intel_syntax = -1;
12626
12627   return print_insn (pc, info);
12628 }
12629
12630 void
12631 print_i386_disassembler_options (FILE *stream)
12632 {
12633   fprintf (stream, _("\n\
12634 The following i386/x86-64 specific disassembler options are supported for use\n\
12635 with the -M switch (multiple options should be separated by commas):\n"));
12636
12637   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12638   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12639   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12640   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12641   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12642   fprintf (stream, _("  att-mnemonic\n"
12643                      "              Display instruction in AT&T mnemonic\n"));
12644   fprintf (stream, _("  intel-mnemonic\n"
12645                      "              Display instruction in Intel mnemonic\n"));
12646   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12647   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12648   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12649   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12650   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12651   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12652   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12653   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12654 }
12655
12656 /* Bad opcode.  */
12657 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12658
12659 /* Get a pointer to struct dis386 with a valid name.  */
12660
12661 static const struct dis386 *
12662 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12663 {
12664   int vindex, vex_table_index;
12665
12666   if (dp->name != NULL)
12667     return dp;
12668
12669   switch (dp->op[0].bytemode)
12670     {
12671     case USE_REG_TABLE:
12672       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12673       break;
12674
12675     case USE_MOD_TABLE:
12676       vindex = modrm.mod == 0x3 ? 1 : 0;
12677       dp = &mod_table[dp->op[1].bytemode][vindex];
12678       break;
12679
12680     case USE_RM_TABLE:
12681       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12682       break;
12683
12684     case USE_PREFIX_TABLE:
12685       if (need_vex)
12686         {
12687           /* The prefix in VEX is implicit.  */
12688           switch (vex.prefix)
12689             {
12690             case 0:
12691               vindex = 0;
12692               break;
12693             case REPE_PREFIX_OPCODE:
12694               vindex = 1;
12695               break;
12696             case DATA_PREFIX_OPCODE:
12697               vindex = 2;
12698               break;
12699             case REPNE_PREFIX_OPCODE:
12700               vindex = 3;
12701               break;
12702             default:
12703               abort ();
12704               break;
12705             }
12706         }
12707       else
12708         {
12709           int last_prefix = -1;
12710           int prefix = 0;
12711           vindex = 0;
12712           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12713              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12714              last one wins.  */
12715           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12716             {
12717               if (last_repz_prefix > last_repnz_prefix)
12718                 {
12719                   vindex = 1;
12720                   prefix = PREFIX_REPZ;
12721                   last_prefix = last_repz_prefix;
12722                 }
12723               else
12724                 {
12725                   vindex = 3;
12726                   prefix = PREFIX_REPNZ;
12727                   last_prefix = last_repnz_prefix;
12728                 }
12729
12730               /* Check if prefix should be ignored.  */
12731               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12732                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12733                    & prefix) != 0)
12734                 vindex = 0;
12735             }
12736
12737           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12738             {
12739               vindex = 2;
12740               prefix = PREFIX_DATA;
12741               last_prefix = last_data_prefix;
12742             }
12743
12744           if (vindex != 0)
12745             {
12746               used_prefixes |= prefix;
12747               all_prefixes[last_prefix] = 0;
12748             }
12749         }
12750       dp = &prefix_table[dp->op[1].bytemode][vindex];
12751       break;
12752
12753     case USE_X86_64_TABLE:
12754       vindex = address_mode == mode_64bit ? 1 : 0;
12755       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12756       break;
12757
12758     case USE_3BYTE_TABLE:
12759       FETCH_DATA (info, codep + 2);
12760       vindex = *codep++;
12761       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12762       end_codep = codep;
12763       modrm.mod = (*codep >> 6) & 3;
12764       modrm.reg = (*codep >> 3) & 7;
12765       modrm.rm = *codep & 7;
12766       break;
12767
12768     case USE_VEX_LEN_TABLE:
12769       if (!need_vex)
12770         abort ();
12771
12772       switch (vex.length)
12773         {
12774         case 128:
12775           vindex = 0;
12776           break;
12777         case 256:
12778           vindex = 1;
12779           break;
12780         default:
12781           abort ();
12782           break;
12783         }
12784
12785       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12786       break;
12787
12788     case USE_XOP_8F_TABLE:
12789       FETCH_DATA (info, codep + 3);
12790       /* All bits in the REX prefix are ignored.  */
12791       rex_ignored = rex;
12792       rex = ~(*codep >> 5) & 0x7;
12793
12794       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12795       switch ((*codep & 0x1f))
12796         {
12797         default:
12798           dp = &bad_opcode;
12799           return dp;
12800         case 0x8:
12801           vex_table_index = XOP_08;
12802           break;
12803         case 0x9:
12804           vex_table_index = XOP_09;
12805           break;
12806         case 0xa:
12807           vex_table_index = XOP_0A;
12808           break;
12809         }
12810       codep++;
12811       vex.w = *codep & 0x80;
12812       if (vex.w && address_mode == mode_64bit)
12813         rex |= REX_W;
12814
12815       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12816       if (address_mode != mode_64bit)
12817         {
12818           /* In 16/32-bit mode REX_B is silently ignored.  */
12819           rex &= ~REX_B;
12820         }
12821
12822       vex.length = (*codep & 0x4) ? 256 : 128;
12823       switch ((*codep & 0x3))
12824         {
12825         case 0:
12826           vex.prefix = 0;
12827           break;
12828         case 1:
12829           vex.prefix = DATA_PREFIX_OPCODE;
12830           break;
12831         case 2:
12832           vex.prefix = REPE_PREFIX_OPCODE;
12833           break;
12834         case 3:
12835           vex.prefix = REPNE_PREFIX_OPCODE;
12836           break;
12837         }
12838       need_vex = 1;
12839       need_vex_reg = 1;
12840       codep++;
12841       vindex = *codep++;
12842       dp = &xop_table[vex_table_index][vindex];
12843
12844       end_codep = codep;
12845       FETCH_DATA (info, codep + 1);
12846       modrm.mod = (*codep >> 6) & 3;
12847       modrm.reg = (*codep >> 3) & 7;
12848       modrm.rm = *codep & 7;
12849       break;
12850
12851     case USE_VEX_C4_TABLE:
12852       /* VEX prefix.  */
12853       FETCH_DATA (info, codep + 3);
12854       /* All bits in the REX prefix are ignored.  */
12855       rex_ignored = rex;
12856       rex = ~(*codep >> 5) & 0x7;
12857       switch ((*codep & 0x1f))
12858         {
12859         default:
12860           dp = &bad_opcode;
12861           return dp;
12862         case 0x1:
12863           vex_table_index = VEX_0F;
12864           break;
12865         case 0x2:
12866           vex_table_index = VEX_0F38;
12867           break;
12868         case 0x3:
12869           vex_table_index = VEX_0F3A;
12870           break;
12871         }
12872       codep++;
12873       vex.w = *codep & 0x80;
12874       if (address_mode == mode_64bit)
12875         {
12876           if (vex.w)
12877             rex |= REX_W;
12878         }
12879       else
12880         {
12881           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12882              is ignored, other REX bits are 0 and the highest bit in
12883              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12884           rex = 0;
12885         }
12886       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12887       vex.length = (*codep & 0x4) ? 256 : 128;
12888       switch ((*codep & 0x3))
12889         {
12890         case 0:
12891           vex.prefix = 0;
12892           break;
12893         case 1:
12894           vex.prefix = DATA_PREFIX_OPCODE;
12895           break;
12896         case 2:
12897           vex.prefix = REPE_PREFIX_OPCODE;
12898           break;
12899         case 3:
12900           vex.prefix = REPNE_PREFIX_OPCODE;
12901           break;
12902         }
12903       need_vex = 1;
12904       need_vex_reg = 1;
12905       codep++;
12906       vindex = *codep++;
12907       dp = &vex_table[vex_table_index][vindex];
12908       end_codep = codep;
12909       /* There is no MODRM byte for VEX0F 77.  */
12910       if (vex_table_index != VEX_0F || vindex != 0x77)
12911         {
12912           FETCH_DATA (info, codep + 1);
12913           modrm.mod = (*codep >> 6) & 3;
12914           modrm.reg = (*codep >> 3) & 7;
12915           modrm.rm = *codep & 7;
12916         }
12917       break;
12918
12919     case USE_VEX_C5_TABLE:
12920       /* VEX prefix.  */
12921       FETCH_DATA (info, codep + 2);
12922       /* All bits in the REX prefix are ignored.  */
12923       rex_ignored = rex;
12924       rex = (*codep & 0x80) ? 0 : REX_R;
12925
12926       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12927          VEX.vvvv is 1.  */
12928       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12929       vex.w = 0;
12930       vex.length = (*codep & 0x4) ? 256 : 128;
12931       switch ((*codep & 0x3))
12932         {
12933         case 0:
12934           vex.prefix = 0;
12935           break;
12936         case 1:
12937           vex.prefix = DATA_PREFIX_OPCODE;
12938           break;
12939         case 2:
12940           vex.prefix = REPE_PREFIX_OPCODE;
12941           break;
12942         case 3:
12943           vex.prefix = REPNE_PREFIX_OPCODE;
12944           break;
12945         }
12946       need_vex = 1;
12947       need_vex_reg = 1;
12948       codep++;
12949       vindex = *codep++;
12950       dp = &vex_table[dp->op[1].bytemode][vindex];
12951       end_codep = codep;
12952       /* There is no MODRM byte for VEX 77.  */
12953       if (vindex != 0x77)
12954         {
12955           FETCH_DATA (info, codep + 1);
12956           modrm.mod = (*codep >> 6) & 3;
12957           modrm.reg = (*codep >> 3) & 7;
12958           modrm.rm = *codep & 7;
12959         }
12960       break;
12961
12962     case USE_VEX_W_TABLE:
12963       if (!need_vex)
12964         abort ();
12965
12966       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12967       break;
12968
12969     case USE_EVEX_TABLE:
12970       two_source_ops = 0;
12971       /* EVEX prefix.  */
12972       vex.evex = 1;
12973       FETCH_DATA (info, codep + 4);
12974       /* All bits in the REX prefix are ignored.  */
12975       rex_ignored = rex;
12976       /* The first byte after 0x62.  */
12977       rex = ~(*codep >> 5) & 0x7;
12978       vex.r = *codep & 0x10;
12979       switch ((*codep & 0xf))
12980         {
12981         default:
12982           return &bad_opcode;
12983         case 0x1:
12984           vex_table_index = EVEX_0F;
12985           break;
12986         case 0x2:
12987           vex_table_index = EVEX_0F38;
12988           break;
12989         case 0x3:
12990           vex_table_index = EVEX_0F3A;
12991           break;
12992         }
12993
12994       /* The second byte after 0x62.  */
12995       codep++;
12996       vex.w = *codep & 0x80;
12997       if (vex.w && address_mode == mode_64bit)
12998         rex |= REX_W;
12999
13000       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13001
13002       /* The U bit.  */
13003       if (!(*codep & 0x4))
13004         return &bad_opcode;
13005
13006       switch ((*codep & 0x3))
13007         {
13008         case 0:
13009           vex.prefix = 0;
13010           break;
13011         case 1:
13012           vex.prefix = DATA_PREFIX_OPCODE;
13013           break;
13014         case 2:
13015           vex.prefix = REPE_PREFIX_OPCODE;
13016           break;
13017         case 3:
13018           vex.prefix = REPNE_PREFIX_OPCODE;
13019           break;
13020         }
13021
13022       /* The third byte after 0x62.  */
13023       codep++;
13024
13025       /* Remember the static rounding bits.  */
13026       vex.ll = (*codep >> 5) & 3;
13027       vex.b = (*codep & 0x10) != 0;
13028
13029       vex.v = *codep & 0x8;
13030       vex.mask_register_specifier = *codep & 0x7;
13031       vex.zeroing = *codep & 0x80;
13032
13033       if (address_mode != mode_64bit)
13034         {
13035           /* In 16/32-bit mode silently ignore following bits.  */
13036           rex &= ~REX_B;
13037           vex.r = 1;
13038           vex.v = 1;
13039         }
13040
13041       need_vex = 1;
13042       need_vex_reg = 1;
13043       codep++;
13044       vindex = *codep++;
13045       dp = &evex_table[vex_table_index][vindex];
13046       end_codep = codep;
13047       FETCH_DATA (info, codep + 1);
13048       modrm.mod = (*codep >> 6) & 3;
13049       modrm.reg = (*codep >> 3) & 7;
13050       modrm.rm = *codep & 7;
13051
13052       /* Set vector length.  */
13053       if (modrm.mod == 3 && vex.b)
13054         vex.length = 512;
13055       else
13056         {
13057           switch (vex.ll)
13058             {
13059             case 0x0:
13060               vex.length = 128;
13061               break;
13062             case 0x1:
13063               vex.length = 256;
13064               break;
13065             case 0x2:
13066               vex.length = 512;
13067               break;
13068             default:
13069               return &bad_opcode;
13070             }
13071         }
13072       break;
13073
13074     case 0:
13075       dp = &bad_opcode;
13076       break;
13077
13078     default:
13079       abort ();
13080     }
13081
13082   if (dp->name != NULL)
13083     return dp;
13084   else
13085     return get_valid_dis386 (dp, info);
13086 }
13087
13088 static void
13089 get_sib (disassemble_info *info, int sizeflag)
13090 {
13091   /* If modrm.mod == 3, operand must be register.  */
13092   if (need_modrm
13093       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13094       && modrm.mod != 3
13095       && modrm.rm == 4)
13096     {
13097       FETCH_DATA (info, codep + 2);
13098       sib.index = (codep [1] >> 3) & 7;
13099       sib.scale = (codep [1] >> 6) & 3;
13100       sib.base = codep [1] & 7;
13101     }
13102 }
13103
13104 static int
13105 print_insn (bfd_vma pc, disassemble_info *info)
13106 {
13107   const struct dis386 *dp;
13108   int i;
13109   char *op_txt[MAX_OPERANDS];
13110   int needcomma;
13111   int sizeflag, orig_sizeflag;
13112   const char *p;
13113   struct dis_private priv;
13114   int prefix_length;
13115
13116   priv.orig_sizeflag = AFLAG | DFLAG;
13117   if ((info->mach & bfd_mach_i386_i386) != 0)
13118     address_mode = mode_32bit;
13119   else if (info->mach == bfd_mach_i386_i8086)
13120     {
13121       address_mode = mode_16bit;
13122       priv.orig_sizeflag = 0;
13123     }
13124   else
13125     address_mode = mode_64bit;
13126
13127   if (intel_syntax == (char) -1)
13128     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13129
13130   for (p = info->disassembler_options; p != NULL; )
13131     {
13132       if (CONST_STRNEQ (p, "amd64"))
13133         isa64 = amd64;
13134       else if (CONST_STRNEQ (p, "intel64"))
13135         isa64 = intel64;
13136       else if (CONST_STRNEQ (p, "x86-64"))
13137         {
13138           address_mode = mode_64bit;
13139           priv.orig_sizeflag = AFLAG | DFLAG;
13140         }
13141       else if (CONST_STRNEQ (p, "i386"))
13142         {
13143           address_mode = mode_32bit;
13144           priv.orig_sizeflag = AFLAG | DFLAG;
13145         }
13146       else if (CONST_STRNEQ (p, "i8086"))
13147         {
13148           address_mode = mode_16bit;
13149           priv.orig_sizeflag = 0;
13150         }
13151       else if (CONST_STRNEQ (p, "intel"))
13152         {
13153           intel_syntax = 1;
13154           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13155             intel_mnemonic = 1;
13156         }
13157       else if (CONST_STRNEQ (p, "att"))
13158         {
13159           intel_syntax = 0;
13160           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13161             intel_mnemonic = 0;
13162         }
13163       else if (CONST_STRNEQ (p, "addr"))
13164         {
13165           if (address_mode == mode_64bit)
13166             {
13167               if (p[4] == '3' && p[5] == '2')
13168                 priv.orig_sizeflag &= ~AFLAG;
13169               else if (p[4] == '6' && p[5] == '4')
13170                 priv.orig_sizeflag |= AFLAG;
13171             }
13172           else
13173             {
13174               if (p[4] == '1' && p[5] == '6')
13175                 priv.orig_sizeflag &= ~AFLAG;
13176               else if (p[4] == '3' && p[5] == '2')
13177                 priv.orig_sizeflag |= AFLAG;
13178             }
13179         }
13180       else if (CONST_STRNEQ (p, "data"))
13181         {
13182           if (p[4] == '1' && p[5] == '6')
13183             priv.orig_sizeflag &= ~DFLAG;
13184           else if (p[4] == '3' && p[5] == '2')
13185             priv.orig_sizeflag |= DFLAG;
13186         }
13187       else if (CONST_STRNEQ (p, "suffix"))
13188         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13189
13190       p = strchr (p, ',');
13191       if (p != NULL)
13192         p++;
13193     }
13194
13195   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13196     {
13197       (*info->fprintf_func) (info->stream,
13198                              _("64-bit address is disabled"));
13199       return -1;
13200     }
13201
13202   if (intel_syntax)
13203     {
13204       names64 = intel_names64;
13205       names32 = intel_names32;
13206       names16 = intel_names16;
13207       names8 = intel_names8;
13208       names8rex = intel_names8rex;
13209       names_seg = intel_names_seg;
13210       names_mm = intel_names_mm;
13211       names_bnd = intel_names_bnd;
13212       names_xmm = intel_names_xmm;
13213       names_ymm = intel_names_ymm;
13214       names_zmm = intel_names_zmm;
13215       index64 = intel_index64;
13216       index32 = intel_index32;
13217       names_mask = intel_names_mask;
13218       index16 = intel_index16;
13219       open_char = '[';
13220       close_char = ']';
13221       separator_char = '+';
13222       scale_char = '*';
13223     }
13224   else
13225     {
13226       names64 = att_names64;
13227       names32 = att_names32;
13228       names16 = att_names16;
13229       names8 = att_names8;
13230       names8rex = att_names8rex;
13231       names_seg = att_names_seg;
13232       names_mm = att_names_mm;
13233       names_bnd = att_names_bnd;
13234       names_xmm = att_names_xmm;
13235       names_ymm = att_names_ymm;
13236       names_zmm = att_names_zmm;
13237       index64 = att_index64;
13238       index32 = att_index32;
13239       names_mask = att_names_mask;
13240       index16 = att_index16;
13241       open_char = '(';
13242       close_char =  ')';
13243       separator_char = ',';
13244       scale_char = ',';
13245     }
13246
13247   /* The output looks better if we put 7 bytes on a line, since that
13248      puts most long word instructions on a single line.  Use 8 bytes
13249      for Intel L1OM.  */
13250   if ((info->mach & bfd_mach_l1om) != 0)
13251     info->bytes_per_line = 8;
13252   else
13253     info->bytes_per_line = 7;
13254
13255   info->private_data = &priv;
13256   priv.max_fetched = priv.the_buffer;
13257   priv.insn_start = pc;
13258
13259   obuf[0] = 0;
13260   for (i = 0; i < MAX_OPERANDS; ++i)
13261     {
13262       op_out[i][0] = 0;
13263       op_index[i] = -1;
13264     }
13265
13266   the_info = info;
13267   start_pc = pc;
13268   start_codep = priv.the_buffer;
13269   codep = priv.the_buffer;
13270
13271   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13272     {
13273       const char *name;
13274
13275       /* Getting here means we tried for data but didn't get it.  That
13276          means we have an incomplete instruction of some sort.  Just
13277          print the first byte as a prefix or a .byte pseudo-op.  */
13278       if (codep > priv.the_buffer)
13279         {
13280           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13281           if (name != NULL)
13282             (*info->fprintf_func) (info->stream, "%s", name);
13283           else
13284             {
13285               /* Just print the first byte as a .byte instruction.  */
13286               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13287                                      (unsigned int) priv.the_buffer[0]);
13288             }
13289
13290           return 1;
13291         }
13292
13293       return -1;
13294     }
13295
13296   obufp = obuf;
13297   sizeflag = priv.orig_sizeflag;
13298
13299   if (!ckprefix () || rex_used)
13300     {
13301       /* Too many prefixes or unused REX prefixes.  */
13302       for (i = 0;
13303            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13304            i++)
13305         (*info->fprintf_func) (info->stream, "%s%s",
13306                                i == 0 ? "" : " ",
13307                                prefix_name (all_prefixes[i], sizeflag));
13308       return i;
13309     }
13310
13311   insn_codep = codep;
13312
13313   FETCH_DATA (info, codep + 1);
13314   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13315
13316   if (((prefixes & PREFIX_FWAIT)
13317        && ((*codep < 0xd8) || (*codep > 0xdf))))
13318     {
13319       /* Handle prefixes before fwait.  */
13320       for (i = 0; i < fwait_prefix && all_prefixes[i];
13321            i++)
13322         (*info->fprintf_func) (info->stream, "%s ",
13323                                prefix_name (all_prefixes[i], sizeflag));
13324       (*info->fprintf_func) (info->stream, "fwait");
13325       return i + 1;
13326     }
13327
13328   if (*codep == 0x0f)
13329     {
13330       unsigned char threebyte;
13331
13332       codep++;
13333       FETCH_DATA (info, codep + 1);
13334       threebyte = *codep;
13335       dp = &dis386_twobyte[threebyte];
13336       need_modrm = twobyte_has_modrm[*codep];
13337       codep++;
13338     }
13339   else
13340     {
13341       dp = &dis386[*codep];
13342       need_modrm = onebyte_has_modrm[*codep];
13343       codep++;
13344     }
13345
13346   /* Save sizeflag for printing the extra prefixes later before updating
13347      it for mnemonic and operand processing.  The prefix names depend
13348      only on the address mode.  */
13349   orig_sizeflag = sizeflag;
13350   if (prefixes & PREFIX_ADDR)
13351     sizeflag ^= AFLAG;
13352   if ((prefixes & PREFIX_DATA))
13353     sizeflag ^= DFLAG;
13354
13355   end_codep = codep;
13356   if (need_modrm)
13357     {
13358       FETCH_DATA (info, codep + 1);
13359       modrm.mod = (*codep >> 6) & 3;
13360       modrm.reg = (*codep >> 3) & 7;
13361       modrm.rm = *codep & 7;
13362     }
13363
13364   need_vex = 0;
13365   need_vex_reg = 0;
13366   vex_w_done = 0;
13367   vex.evex = 0;
13368
13369   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13370     {
13371       get_sib (info, sizeflag);
13372       dofloat (sizeflag);
13373     }
13374   else
13375     {
13376       dp = get_valid_dis386 (dp, info);
13377       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13378         {
13379           get_sib (info, sizeflag);
13380           for (i = 0; i < MAX_OPERANDS; ++i)
13381             {
13382               obufp = op_out[i];
13383               op_ad = MAX_OPERANDS - 1 - i;
13384               if (dp->op[i].rtn)
13385                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13386               /* For EVEX instruction after the last operand masking
13387                  should be printed.  */
13388               if (i == 0 && vex.evex)
13389                 {
13390                   /* Don't print {%k0}.  */
13391                   if (vex.mask_register_specifier)
13392                     {
13393                       oappend ("{");
13394                       oappend (names_mask[vex.mask_register_specifier]);
13395                       oappend ("}");
13396                     }
13397                   if (vex.zeroing)
13398                     oappend ("{z}");
13399                 }
13400             }
13401         }
13402     }
13403
13404   /* Check if the REX prefix is used.  */
13405   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13406     all_prefixes[last_rex_prefix] = 0;
13407
13408   /* Check if the SEG prefix is used.  */
13409   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13410                    | PREFIX_FS | PREFIX_GS)) != 0
13411       && (used_prefixes & active_seg_prefix) != 0)
13412     all_prefixes[last_seg_prefix] = 0;
13413
13414   /* Check if the ADDR prefix is used.  */
13415   if ((prefixes & PREFIX_ADDR) != 0
13416       && (used_prefixes & PREFIX_ADDR) != 0)
13417     all_prefixes[last_addr_prefix] = 0;
13418
13419   /* Check if the DATA prefix is used.  */
13420   if ((prefixes & PREFIX_DATA) != 0
13421       && (used_prefixes & PREFIX_DATA) != 0)
13422     all_prefixes[last_data_prefix] = 0;
13423
13424   /* Print the extra prefixes.  */
13425   prefix_length = 0;
13426   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13427     if (all_prefixes[i])
13428       {
13429         const char *name;
13430         name = prefix_name (all_prefixes[i], orig_sizeflag);
13431         if (name == NULL)
13432           abort ();
13433         prefix_length += strlen (name) + 1;
13434         (*info->fprintf_func) (info->stream, "%s ", name);
13435       }
13436
13437   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13438      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13439      used by putop and MMX/SSE operand and may be overriden by the
13440      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13441      separately.  */
13442   if (dp->prefix_requirement == PREFIX_OPCODE
13443       && dp != &bad_opcode
13444       && (((prefixes
13445             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13446            && (used_prefixes
13447                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13448           || ((((prefixes
13449                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13450                 == PREFIX_DATA)
13451                && (used_prefixes & PREFIX_DATA) == 0))))
13452     {
13453       (*info->fprintf_func) (info->stream, "(bad)");
13454       return end_codep - priv.the_buffer;
13455     }
13456
13457   /* Check maximum code length.  */
13458   if ((codep - start_codep) > MAX_CODE_LENGTH)
13459     {
13460       (*info->fprintf_func) (info->stream, "(bad)");
13461       return MAX_CODE_LENGTH;
13462     }
13463
13464   obufp = mnemonicendp;
13465   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13466     oappend (" ");
13467   oappend (" ");
13468   (*info->fprintf_func) (info->stream, "%s", obuf);
13469
13470   /* The enter and bound instructions are printed with operands in the same
13471      order as the intel book; everything else is printed in reverse order.  */
13472   if (intel_syntax || two_source_ops)
13473     {
13474       bfd_vma riprel;
13475
13476       for (i = 0; i < MAX_OPERANDS; ++i)
13477         op_txt[i] = op_out[i];
13478
13479       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13480           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13481         {
13482           op_txt[2] = op_out[3];
13483           op_txt[3] = op_out[2];
13484         }
13485
13486       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13487         {
13488           op_ad = op_index[i];
13489           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13490           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13491           riprel = op_riprel[i];
13492           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13493           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13494         }
13495     }
13496   else
13497     {
13498       for (i = 0; i < MAX_OPERANDS; ++i)
13499         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13500     }
13501
13502   needcomma = 0;
13503   for (i = 0; i < MAX_OPERANDS; ++i)
13504     if (*op_txt[i])
13505       {
13506         if (needcomma)
13507           (*info->fprintf_func) (info->stream, ",");
13508         if (op_index[i] != -1 && !op_riprel[i])
13509           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13510         else
13511           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13512         needcomma = 1;
13513       }
13514
13515   for (i = 0; i < MAX_OPERANDS; i++)
13516     if (op_index[i] != -1 && op_riprel[i])
13517       {
13518         (*info->fprintf_func) (info->stream, "        # ");
13519         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13520                                                 + op_address[op_index[i]]), info);
13521         break;
13522       }
13523   return codep - priv.the_buffer;
13524 }
13525
13526 static const char *float_mem[] = {
13527   /* d8 */
13528   "fadd{s|}",
13529   "fmul{s|}",
13530   "fcom{s|}",
13531   "fcomp{s|}",
13532   "fsub{s|}",
13533   "fsubr{s|}",
13534   "fdiv{s|}",
13535   "fdivr{s|}",
13536   /* d9 */
13537   "fld{s|}",
13538   "(bad)",
13539   "fst{s|}",
13540   "fstp{s|}",
13541   "fldenvIC",
13542   "fldcw",
13543   "fNstenvIC",
13544   "fNstcw",
13545   /* da */
13546   "fiadd{l|}",
13547   "fimul{l|}",
13548   "ficom{l|}",
13549   "ficomp{l|}",
13550   "fisub{l|}",
13551   "fisubr{l|}",
13552   "fidiv{l|}",
13553   "fidivr{l|}",
13554   /* db */
13555   "fild{l|}",
13556   "fisttp{l|}",
13557   "fist{l|}",
13558   "fistp{l|}",
13559   "(bad)",
13560   "fld{t||t|}",
13561   "(bad)",
13562   "fstp{t||t|}",
13563   /* dc */
13564   "fadd{l|}",
13565   "fmul{l|}",
13566   "fcom{l|}",
13567   "fcomp{l|}",
13568   "fsub{l|}",
13569   "fsubr{l|}",
13570   "fdiv{l|}",
13571   "fdivr{l|}",
13572   /* dd */
13573   "fld{l|}",
13574   "fisttp{ll|}",
13575   "fst{l||}",
13576   "fstp{l|}",
13577   "frstorIC",
13578   "(bad)",
13579   "fNsaveIC",
13580   "fNstsw",
13581   /* de */
13582   "fiadd{s|}",
13583   "fimul{s|}",
13584   "ficom{s|}",
13585   "ficomp{s|}",
13586   "fisub{s|}",
13587   "fisubr{s|}",
13588   "fidiv{s|}",
13589   "fidivr{s|}",
13590   /* df */
13591   "fild{s|}",
13592   "fisttp{s|}",
13593   "fist{s|}",
13594   "fistp{s|}",
13595   "fbld",
13596   "fild{ll|}",
13597   "fbstp",
13598   "fistp{ll|}",
13599 };
13600
13601 static const unsigned char float_mem_mode[] = {
13602   /* d8 */
13603   d_mode,
13604   d_mode,
13605   d_mode,
13606   d_mode,
13607   d_mode,
13608   d_mode,
13609   d_mode,
13610   d_mode,
13611   /* d9 */
13612   d_mode,
13613   0,
13614   d_mode,
13615   d_mode,
13616   0,
13617   w_mode,
13618   0,
13619   w_mode,
13620   /* da */
13621   d_mode,
13622   d_mode,
13623   d_mode,
13624   d_mode,
13625   d_mode,
13626   d_mode,
13627   d_mode,
13628   d_mode,
13629   /* db */
13630   d_mode,
13631   d_mode,
13632   d_mode,
13633   d_mode,
13634   0,
13635   t_mode,
13636   0,
13637   t_mode,
13638   /* dc */
13639   q_mode,
13640   q_mode,
13641   q_mode,
13642   q_mode,
13643   q_mode,
13644   q_mode,
13645   q_mode,
13646   q_mode,
13647   /* dd */
13648   q_mode,
13649   q_mode,
13650   q_mode,
13651   q_mode,
13652   0,
13653   0,
13654   0,
13655   w_mode,
13656   /* de */
13657   w_mode,
13658   w_mode,
13659   w_mode,
13660   w_mode,
13661   w_mode,
13662   w_mode,
13663   w_mode,
13664   w_mode,
13665   /* df */
13666   w_mode,
13667   w_mode,
13668   w_mode,
13669   w_mode,
13670   t_mode,
13671   q_mode,
13672   t_mode,
13673   q_mode
13674 };
13675
13676 #define ST { OP_ST, 0 }
13677 #define STi { OP_STi, 0 }
13678
13679 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13680 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13681 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13682 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13683 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13684 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13685 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13686 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13687 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13688
13689 static const struct dis386 float_reg[][8] = {
13690   /* d8 */
13691   {
13692     { "fadd",   { ST, STi }, 0 },
13693     { "fmul",   { ST, STi }, 0 },
13694     { "fcom",   { STi }, 0 },
13695     { "fcomp",  { STi }, 0 },
13696     { "fsub",   { ST, STi }, 0 },
13697     { "fsubr",  { ST, STi }, 0 },
13698     { "fdiv",   { ST, STi }, 0 },
13699     { "fdivr",  { ST, STi }, 0 },
13700   },
13701   /* d9 */
13702   {
13703     { "fld",    { STi }, 0 },
13704     { "fxch",   { STi }, 0 },
13705     { FGRPd9_2 },
13706     { Bad_Opcode },
13707     { FGRPd9_4 },
13708     { FGRPd9_5 },
13709     { FGRPd9_6 },
13710     { FGRPd9_7 },
13711   },
13712   /* da */
13713   {
13714     { "fcmovb", { ST, STi }, 0 },
13715     { "fcmove", { ST, STi }, 0 },
13716     { "fcmovbe",{ ST, STi }, 0 },
13717     { "fcmovu", { ST, STi }, 0 },
13718     { Bad_Opcode },
13719     { FGRPda_5 },
13720     { Bad_Opcode },
13721     { Bad_Opcode },
13722   },
13723   /* db */
13724   {
13725     { "fcmovnb",{ ST, STi }, 0 },
13726     { "fcmovne",{ ST, STi }, 0 },
13727     { "fcmovnbe",{ ST, STi }, 0 },
13728     { "fcmovnu",{ ST, STi }, 0 },
13729     { FGRPdb_4 },
13730     { "fucomi", { ST, STi }, 0 },
13731     { "fcomi",  { ST, STi }, 0 },
13732     { Bad_Opcode },
13733   },
13734   /* dc */
13735   {
13736     { "fadd",   { STi, ST }, 0 },
13737     { "fmul",   { STi, ST }, 0 },
13738     { Bad_Opcode },
13739     { Bad_Opcode },
13740     { "fsub{!M|r}",     { STi, ST }, 0 },
13741     { "fsub{M|}",       { STi, ST }, 0 },
13742     { "fdiv{!M|r}",     { STi, ST }, 0 },
13743     { "fdiv{M|}",       { STi, ST }, 0 },
13744   },
13745   /* dd */
13746   {
13747     { "ffree",  { STi }, 0 },
13748     { Bad_Opcode },
13749     { "fst",    { STi }, 0 },
13750     { "fstp",   { STi }, 0 },
13751     { "fucom",  { STi }, 0 },
13752     { "fucomp", { STi }, 0 },
13753     { Bad_Opcode },
13754     { Bad_Opcode },
13755   },
13756   /* de */
13757   {
13758     { "faddp",  { STi, ST }, 0 },
13759     { "fmulp",  { STi, ST }, 0 },
13760     { Bad_Opcode },
13761     { FGRPde_3 },
13762     { "fsub{!M|r}p",    { STi, ST }, 0 },
13763     { "fsub{M|}p",      { STi, ST }, 0 },
13764     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13765     { "fdiv{M|}p",      { STi, ST }, 0 },
13766   },
13767   /* df */
13768   {
13769     { "ffreep", { STi }, 0 },
13770     { Bad_Opcode },
13771     { Bad_Opcode },
13772     { Bad_Opcode },
13773     { FGRPdf_4 },
13774     { "fucomip", { ST, STi }, 0 },
13775     { "fcomip", { ST, STi }, 0 },
13776     { Bad_Opcode },
13777   },
13778 };
13779
13780 static char *fgrps[][8] = {
13781   /* Bad opcode 0 */
13782   {
13783     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13784   },
13785
13786   /* d9_2  1 */
13787   {
13788     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13789   },
13790
13791   /* d9_4  2 */
13792   {
13793     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13794   },
13795
13796   /* d9_5  3 */
13797   {
13798     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13799   },
13800
13801   /* d9_6  4 */
13802   {
13803     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13804   },
13805
13806   /* d9_7  5 */
13807   {
13808     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13809   },
13810
13811   /* da_5  6 */
13812   {
13813     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13814   },
13815
13816   /* db_4  7 */
13817   {
13818     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13819     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13820   },
13821
13822   /* de_3  8 */
13823   {
13824     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13825   },
13826
13827   /* df_4  9 */
13828   {
13829     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13830   },
13831 };
13832
13833 static void
13834 swap_operand (void)
13835 {
13836   mnemonicendp[0] = '.';
13837   mnemonicendp[1] = 's';
13838   mnemonicendp += 2;
13839 }
13840
13841 static void
13842 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13843                int sizeflag ATTRIBUTE_UNUSED)
13844 {
13845   /* Skip mod/rm byte.  */
13846   MODRM_CHECK;
13847   codep++;
13848 }
13849
13850 static void
13851 dofloat (int sizeflag)
13852 {
13853   const struct dis386 *dp;
13854   unsigned char floatop;
13855
13856   floatop = codep[-1];
13857
13858   if (modrm.mod != 3)
13859     {
13860       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13861
13862       putop (float_mem[fp_indx], sizeflag);
13863       obufp = op_out[0];
13864       op_ad = 2;
13865       OP_E (float_mem_mode[fp_indx], sizeflag);
13866       return;
13867     }
13868   /* Skip mod/rm byte.  */
13869   MODRM_CHECK;
13870   codep++;
13871
13872   dp = &float_reg[floatop - 0xd8][modrm.reg];
13873   if (dp->name == NULL)
13874     {
13875       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13876
13877       /* Instruction fnstsw is only one with strange arg.  */
13878       if (floatop == 0xdf && codep[-1] == 0xe0)
13879         strcpy (op_out[0], names16[0]);
13880     }
13881   else
13882     {
13883       putop (dp->name, sizeflag);
13884
13885       obufp = op_out[0];
13886       op_ad = 2;
13887       if (dp->op[0].rtn)
13888         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13889
13890       obufp = op_out[1];
13891       op_ad = 1;
13892       if (dp->op[1].rtn)
13893         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13894     }
13895 }
13896
13897 /* Like oappend (below), but S is a string starting with '%'.
13898    In Intel syntax, the '%' is elided.  */
13899 static void
13900 oappend_maybe_intel (const char *s)
13901 {
13902   oappend (s + intel_syntax);
13903 }
13904
13905 static void
13906 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13907 {
13908   oappend_maybe_intel ("%st");
13909 }
13910
13911 static void
13912 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13913 {
13914   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13915   oappend_maybe_intel (scratchbuf);
13916 }
13917
13918 /* Capital letters in template are macros.  */
13919 static int
13920 putop (const char *in_template, int sizeflag)
13921 {
13922   const char *p;
13923   int alt = 0;
13924   int cond = 1;
13925   unsigned int l = 0, len = 1;
13926   char last[4];
13927
13928 #define SAVE_LAST(c)                    \
13929   if (l < len && l < sizeof (last))     \
13930     last[l++] = c;                      \
13931   else                                  \
13932     abort ();
13933
13934   for (p = in_template; *p; p++)
13935     {
13936       switch (*p)
13937         {
13938         default:
13939           *obufp++ = *p;
13940           break;
13941         case '%':
13942           len++;
13943           break;
13944         case '!':
13945           cond = 0;
13946           break;
13947         case '{':
13948           if (intel_syntax)
13949             {
13950               while (*++p != '|')
13951                 if (*p == '}' || *p == '\0')
13952                   abort ();
13953             }
13954           /* Fall through.  */
13955         case 'I':
13956           alt = 1;
13957           continue;
13958         case '|':
13959           while (*++p != '}')
13960             {
13961               if (*p == '\0')
13962                 abort ();
13963             }
13964           break;
13965         case '}':
13966           break;
13967         case 'A':
13968           if (intel_syntax)
13969             break;
13970           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13971             *obufp++ = 'b';
13972           break;
13973         case 'B':
13974           if (l == 0 && len == 1)
13975             {
13976 case_B:
13977               if (intel_syntax)
13978                 break;
13979               if (sizeflag & SUFFIX_ALWAYS)
13980                 *obufp++ = 'b';
13981             }
13982           else
13983             {
13984               if (l != 1
13985                   || len != 2
13986                   || last[0] != 'L')
13987                 {
13988                   SAVE_LAST (*p);
13989                   break;
13990                 }
13991
13992               if (address_mode == mode_64bit
13993                   && !(prefixes & PREFIX_ADDR))
13994                 {
13995                   *obufp++ = 'a';
13996                   *obufp++ = 'b';
13997                   *obufp++ = 's';
13998                 }
13999
14000               goto case_B;
14001             }
14002           break;
14003         case 'C':
14004           if (intel_syntax && !alt)
14005             break;
14006           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14007             {
14008               if (sizeflag & DFLAG)
14009                 *obufp++ = intel_syntax ? 'd' : 'l';
14010               else
14011                 *obufp++ = intel_syntax ? 'w' : 's';
14012               used_prefixes |= (prefixes & PREFIX_DATA);
14013             }
14014           break;
14015         case 'D':
14016           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14017             break;
14018           USED_REX (REX_W);
14019           if (modrm.mod == 3)
14020             {
14021               if (rex & REX_W)
14022                 *obufp++ = 'q';
14023               else
14024                 {
14025                   if (sizeflag & DFLAG)
14026                     *obufp++ = intel_syntax ? 'd' : 'l';
14027                   else
14028                     *obufp++ = 'w';
14029                   used_prefixes |= (prefixes & PREFIX_DATA);
14030                 }
14031             }
14032           else
14033             *obufp++ = 'w';
14034           break;
14035         case 'E':               /* For jcxz/jecxz */
14036           if (address_mode == mode_64bit)
14037             {
14038               if (sizeflag & AFLAG)
14039                 *obufp++ = 'r';
14040               else
14041                 *obufp++ = 'e';
14042             }
14043           else
14044             if (sizeflag & AFLAG)
14045               *obufp++ = 'e';
14046           used_prefixes |= (prefixes & PREFIX_ADDR);
14047           break;
14048         case 'F':
14049           if (intel_syntax)
14050             break;
14051           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14052             {
14053               if (sizeflag & AFLAG)
14054                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14055               else
14056                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14057               used_prefixes |= (prefixes & PREFIX_ADDR);
14058             }
14059           break;
14060         case 'G':
14061           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14062             break;
14063           if ((rex & REX_W) || (sizeflag & DFLAG))
14064             *obufp++ = 'l';
14065           else
14066             *obufp++ = 'w';
14067           if (!(rex & REX_W))
14068             used_prefixes |= (prefixes & PREFIX_DATA);
14069           break;
14070         case 'H':
14071           if (intel_syntax)
14072             break;
14073           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14074               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14075             {
14076               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14077               *obufp++ = ',';
14078               *obufp++ = 'p';
14079               if (prefixes & PREFIX_DS)
14080                 *obufp++ = 't';
14081               else
14082                 *obufp++ = 'n';
14083             }
14084           break;
14085         case 'J':
14086           if (intel_syntax)
14087             break;
14088           *obufp++ = 'l';
14089           break;
14090         case 'K':
14091           USED_REX (REX_W);
14092           if (rex & REX_W)
14093             *obufp++ = 'q';
14094           else
14095             *obufp++ = 'd';
14096           break;
14097         case 'Z':
14098           if (l != 0 || len != 1)
14099             {
14100               if (l != 1 || len != 2 || last[0] != 'X')
14101                 {
14102                   SAVE_LAST (*p);
14103                   break;
14104                 }
14105               if (!need_vex || !vex.evex)
14106                 abort ();
14107               if (intel_syntax
14108                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14109                 break;
14110               switch (vex.length)
14111                 {
14112                 case 128:
14113                   *obufp++ = 'x';
14114                   break;
14115                 case 256:
14116                   *obufp++ = 'y';
14117                   break;
14118                 case 512:
14119                   *obufp++ = 'z';
14120                   break;
14121                 default:
14122                   abort ();
14123                 }
14124               break;
14125             }
14126           if (intel_syntax)
14127             break;
14128           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14129             {
14130               *obufp++ = 'q';
14131               break;
14132             }
14133           /* Fall through.  */
14134           goto case_L;
14135         case 'L':
14136           if (l != 0 || len != 1)
14137             {
14138               SAVE_LAST (*p);
14139               break;
14140             }
14141 case_L:
14142           if (intel_syntax)
14143             break;
14144           if (sizeflag & SUFFIX_ALWAYS)
14145             *obufp++ = 'l';
14146           break;
14147         case 'M':
14148           if (intel_mnemonic != cond)
14149             *obufp++ = 'r';
14150           break;
14151         case 'N':
14152           if ((prefixes & PREFIX_FWAIT) == 0)
14153             *obufp++ = 'n';
14154           else
14155             used_prefixes |= PREFIX_FWAIT;
14156           break;
14157         case 'O':
14158           USED_REX (REX_W);
14159           if (rex & REX_W)
14160             *obufp++ = 'o';
14161           else if (intel_syntax && (sizeflag & DFLAG))
14162             *obufp++ = 'q';
14163           else
14164             *obufp++ = 'd';
14165           if (!(rex & REX_W))
14166             used_prefixes |= (prefixes & PREFIX_DATA);
14167           break;
14168         case '&':
14169           if (!intel_syntax
14170               && address_mode == mode_64bit
14171               && isa64 == intel64)
14172             {
14173               *obufp++ = 'q';
14174               break;
14175             }
14176           /* Fall through.  */
14177         case 'T':
14178           if (!intel_syntax
14179               && address_mode == mode_64bit
14180               && ((sizeflag & DFLAG) || (rex & REX_W)))
14181             {
14182               *obufp++ = 'q';
14183               break;
14184             }
14185           /* Fall through.  */
14186           goto case_P;
14187         case 'P':
14188           if (l == 0 && len == 1)
14189             {
14190 case_P:
14191               if (intel_syntax)
14192                 {
14193                   if ((rex & REX_W) == 0
14194                       && (prefixes & PREFIX_DATA))
14195                     {
14196                       if ((sizeflag & DFLAG) == 0)
14197                         *obufp++ = 'w';
14198                       used_prefixes |= (prefixes & PREFIX_DATA);
14199                     }
14200                   break;
14201                 }
14202               if ((prefixes & PREFIX_DATA)
14203                   || (rex & REX_W)
14204                   || (sizeflag & SUFFIX_ALWAYS))
14205                 {
14206                   USED_REX (REX_W);
14207                   if (rex & REX_W)
14208                     *obufp++ = 'q';
14209                   else
14210                     {
14211                       if (sizeflag & DFLAG)
14212                         *obufp++ = 'l';
14213                       else
14214                         *obufp++ = 'w';
14215                       used_prefixes |= (prefixes & PREFIX_DATA);
14216                     }
14217                 }
14218             }
14219           else
14220             {
14221               if (l != 1 || len != 2 || last[0] != 'L')
14222                 {
14223                   SAVE_LAST (*p);
14224                   break;
14225                 }
14226
14227               if ((prefixes & PREFIX_DATA)
14228                   || (rex & REX_W)
14229                   || (sizeflag & SUFFIX_ALWAYS))
14230                 {
14231                   USED_REX (REX_W);
14232                   if (rex & REX_W)
14233                     *obufp++ = 'q';
14234                   else
14235                     {
14236                       if (sizeflag & DFLAG)
14237                         *obufp++ = intel_syntax ? 'd' : 'l';
14238                       else
14239                         *obufp++ = 'w';
14240                       used_prefixes |= (prefixes & PREFIX_DATA);
14241                     }
14242                 }
14243             }
14244           break;
14245         case 'U':
14246           if (intel_syntax)
14247             break;
14248           if (address_mode == mode_64bit
14249               && ((sizeflag & DFLAG) || (rex & REX_W)))
14250             {
14251               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14252                 *obufp++ = 'q';
14253               break;
14254             }
14255           /* Fall through.  */
14256           goto case_Q;
14257         case 'Q':
14258           if (l == 0 && len == 1)
14259             {
14260 case_Q:
14261               if (intel_syntax && !alt)
14262                 break;
14263               USED_REX (REX_W);
14264               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14265                 {
14266                   if (rex & REX_W)
14267                     *obufp++ = 'q';
14268                   else
14269                     {
14270                       if (sizeflag & DFLAG)
14271                         *obufp++ = intel_syntax ? 'd' : 'l';
14272                       else
14273                         *obufp++ = 'w';
14274                       used_prefixes |= (prefixes & PREFIX_DATA);
14275                     }
14276                 }
14277             }
14278           else
14279             {
14280               if (l != 1 || len != 2 || last[0] != 'L')
14281                 {
14282                   SAVE_LAST (*p);
14283                   break;
14284                 }
14285               if (intel_syntax
14286                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14287                 break;
14288               if ((rex & REX_W))
14289                 {
14290                   USED_REX (REX_W);
14291                   *obufp++ = 'q';
14292                 }
14293               else
14294                 *obufp++ = 'l';
14295             }
14296           break;
14297         case 'R':
14298           USED_REX (REX_W);
14299           if (rex & REX_W)
14300             *obufp++ = 'q';
14301           else if (sizeflag & DFLAG)
14302             {
14303               if (intel_syntax)
14304                   *obufp++ = 'd';
14305               else
14306                   *obufp++ = 'l';
14307             }
14308           else
14309             *obufp++ = 'w';
14310           if (intel_syntax && !p[1]
14311               && ((rex & REX_W) || (sizeflag & DFLAG)))
14312             *obufp++ = 'e';
14313           if (!(rex & REX_W))
14314             used_prefixes |= (prefixes & PREFIX_DATA);
14315           break;
14316         case 'V':
14317           if (l == 0 && len == 1)
14318             {
14319               if (intel_syntax)
14320                 break;
14321               if (address_mode == mode_64bit
14322                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14323                 {
14324                   if (sizeflag & SUFFIX_ALWAYS)
14325                     *obufp++ = 'q';
14326                   break;
14327                 }
14328             }
14329           else
14330             {
14331               if (l != 1
14332                   || len != 2
14333                   || last[0] != 'L')
14334                 {
14335                   SAVE_LAST (*p);
14336                   break;
14337                 }
14338
14339               if (rex & REX_W)
14340                 {
14341                   *obufp++ = 'a';
14342                   *obufp++ = 'b';
14343                   *obufp++ = 's';
14344                 }
14345             }
14346           /* Fall through.  */
14347           goto case_S;
14348         case 'S':
14349           if (l == 0 && len == 1)
14350             {
14351 case_S:
14352               if (intel_syntax)
14353                 break;
14354               if (sizeflag & SUFFIX_ALWAYS)
14355                 {
14356                   if (rex & REX_W)
14357                     *obufp++ = 'q';
14358                   else
14359                     {
14360                       if (sizeflag & DFLAG)
14361                         *obufp++ = 'l';
14362                       else
14363                         *obufp++ = 'w';
14364                       used_prefixes |= (prefixes & PREFIX_DATA);
14365                     }
14366                 }
14367             }
14368           else
14369             {
14370               if (l != 1
14371                   || len != 2
14372                   || last[0] != 'L')
14373                 {
14374                   SAVE_LAST (*p);
14375                   break;
14376                 }
14377
14378               if (address_mode == mode_64bit
14379                   && !(prefixes & PREFIX_ADDR))
14380                 {
14381                   *obufp++ = 'a';
14382                   *obufp++ = 'b';
14383                   *obufp++ = 's';
14384                 }
14385
14386               goto case_S;
14387             }
14388           break;
14389         case 'X':
14390           if (l != 0 || len != 1)
14391             {
14392               SAVE_LAST (*p);
14393               break;
14394             }
14395           if (need_vex && vex.prefix)
14396             {
14397               if (vex.prefix == DATA_PREFIX_OPCODE)
14398                 *obufp++ = 'd';
14399               else
14400                 *obufp++ = 's';
14401             }
14402           else
14403             {
14404               if (prefixes & PREFIX_DATA)
14405                 *obufp++ = 'd';
14406               else
14407                 *obufp++ = 's';
14408               used_prefixes |= (prefixes & PREFIX_DATA);
14409             }
14410           break;
14411         case 'Y':
14412           if (l == 0 && len == 1)
14413             {
14414               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14415                 break;
14416               if (rex & REX_W)
14417                 {
14418                   USED_REX (REX_W);
14419                   *obufp++ = 'q';
14420                 }
14421               break;
14422             }
14423           else
14424             {
14425               if (l != 1 || len != 2 || last[0] != 'X')
14426                 {
14427                   SAVE_LAST (*p);
14428                   break;
14429                 }
14430               if (!need_vex)
14431                 abort ();
14432               if (intel_syntax
14433                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14434                 break;
14435               switch (vex.length)
14436                 {
14437                 case 128:
14438                   *obufp++ = 'x';
14439                   break;
14440                 case 256:
14441                   *obufp++ = 'y';
14442                   break;
14443                 case 512:
14444                   if (!vex.evex)
14445                 default:
14446                     abort ();
14447                 }
14448             }
14449           break;
14450         case 'W':
14451           if (l == 0 && len == 1)
14452             {
14453               /* operand size flag for cwtl, cbtw */
14454               USED_REX (REX_W);
14455               if (rex & REX_W)
14456                 {
14457                   if (intel_syntax)
14458                     *obufp++ = 'd';
14459                   else
14460                     *obufp++ = 'l';
14461                 }
14462               else if (sizeflag & DFLAG)
14463                 *obufp++ = 'w';
14464               else
14465                 *obufp++ = 'b';
14466               if (!(rex & REX_W))
14467                 used_prefixes |= (prefixes & PREFIX_DATA);
14468             }
14469           else
14470             {
14471               if (l != 1
14472                   || len != 2
14473                   || (last[0] != 'X'
14474                       && last[0] != 'L'))
14475                 {
14476                   SAVE_LAST (*p);
14477                   break;
14478                 }
14479               if (!need_vex)
14480                 abort ();
14481               if (last[0] == 'X')
14482                 *obufp++ = vex.w ? 'd': 's';
14483               else
14484                 *obufp++ = vex.w ? 'q': 'd';
14485             }
14486           break;
14487         case '^':
14488           if (intel_syntax)
14489             break;
14490           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14491             {
14492               if (sizeflag & DFLAG)
14493                 *obufp++ = 'l';
14494               else
14495                 *obufp++ = 'w';
14496               used_prefixes |= (prefixes & PREFIX_DATA);
14497             }
14498           break;
14499         case '@':
14500           if (intel_syntax)
14501             break;
14502           if (address_mode == mode_64bit
14503               && (isa64 == intel64
14504                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14505               *obufp++ = 'q';
14506           else if ((prefixes & PREFIX_DATA))
14507             {
14508               if (!(sizeflag & DFLAG))
14509                 *obufp++ = 'w';
14510               used_prefixes |= (prefixes & PREFIX_DATA);
14511             }
14512           break;
14513         }
14514       alt = 0;
14515     }
14516   *obufp = 0;
14517   mnemonicendp = obufp;
14518   return 0;
14519 }
14520
14521 static void
14522 oappend (const char *s)
14523 {
14524   obufp = stpcpy (obufp, s);
14525 }
14526
14527 static void
14528 append_seg (void)
14529 {
14530   /* Only print the active segment register.  */
14531   if (!active_seg_prefix)
14532     return;
14533
14534   used_prefixes |= active_seg_prefix;
14535   switch (active_seg_prefix)
14536     {
14537     case PREFIX_CS:
14538       oappend_maybe_intel ("%cs:");
14539       break;
14540     case PREFIX_DS:
14541       oappend_maybe_intel ("%ds:");
14542       break;
14543     case PREFIX_SS:
14544       oappend_maybe_intel ("%ss:");
14545       break;
14546     case PREFIX_ES:
14547       oappend_maybe_intel ("%es:");
14548       break;
14549     case PREFIX_FS:
14550       oappend_maybe_intel ("%fs:");
14551       break;
14552     case PREFIX_GS:
14553       oappend_maybe_intel ("%gs:");
14554       break;
14555     default:
14556       break;
14557     }
14558 }
14559
14560 static void
14561 OP_indirE (int bytemode, int sizeflag)
14562 {
14563   if (!intel_syntax)
14564     oappend ("*");
14565   OP_E (bytemode, sizeflag);
14566 }
14567
14568 static void
14569 print_operand_value (char *buf, int hex, bfd_vma disp)
14570 {
14571   if (address_mode == mode_64bit)
14572     {
14573       if (hex)
14574         {
14575           char tmp[30];
14576           int i;
14577           buf[0] = '0';
14578           buf[1] = 'x';
14579           sprintf_vma (tmp, disp);
14580           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14581           strcpy (buf + 2, tmp + i);
14582         }
14583       else
14584         {
14585           bfd_signed_vma v = disp;
14586           char tmp[30];
14587           int i;
14588           if (v < 0)
14589             {
14590               *(buf++) = '-';
14591               v = -disp;
14592               /* Check for possible overflow on 0x8000000000000000.  */
14593               if (v < 0)
14594                 {
14595                   strcpy (buf, "9223372036854775808");
14596                   return;
14597                 }
14598             }
14599           if (!v)
14600             {
14601               strcpy (buf, "0");
14602               return;
14603             }
14604
14605           i = 0;
14606           tmp[29] = 0;
14607           while (v)
14608             {
14609               tmp[28 - i] = (v % 10) + '0';
14610               v /= 10;
14611               i++;
14612             }
14613           strcpy (buf, tmp + 29 - i);
14614         }
14615     }
14616   else
14617     {
14618       if (hex)
14619         sprintf (buf, "0x%x", (unsigned int) disp);
14620       else
14621         sprintf (buf, "%d", (int) disp);
14622     }
14623 }
14624
14625 /* Put DISP in BUF as signed hex number.  */
14626
14627 static void
14628 print_displacement (char *buf, bfd_vma disp)
14629 {
14630   bfd_signed_vma val = disp;
14631   char tmp[30];
14632   int i, j = 0;
14633
14634   if (val < 0)
14635     {
14636       buf[j++] = '-';
14637       val = -disp;
14638
14639       /* Check for possible overflow.  */
14640       if (val < 0)
14641         {
14642           switch (address_mode)
14643             {
14644             case mode_64bit:
14645               strcpy (buf + j, "0x8000000000000000");
14646               break;
14647             case mode_32bit:
14648               strcpy (buf + j, "0x80000000");
14649               break;
14650             case mode_16bit:
14651               strcpy (buf + j, "0x8000");
14652               break;
14653             }
14654           return;
14655         }
14656     }
14657
14658   buf[j++] = '0';
14659   buf[j++] = 'x';
14660
14661   sprintf_vma (tmp, (bfd_vma) val);
14662   for (i = 0; tmp[i] == '0'; i++)
14663     continue;
14664   if (tmp[i] == '\0')
14665     i--;
14666   strcpy (buf + j, tmp + i);
14667 }
14668
14669 static void
14670 intel_operand_size (int bytemode, int sizeflag)
14671 {
14672   if (vex.evex
14673       && vex.b
14674       && (bytemode == x_mode
14675           || bytemode == evex_half_bcst_xmmq_mode))
14676     {
14677       if (vex.w)
14678         oappend ("QWORD PTR ");
14679       else
14680         oappend ("DWORD PTR ");
14681       return;
14682     }
14683   switch (bytemode)
14684     {
14685     case b_mode:
14686     case b_swap_mode:
14687     case dqb_mode:
14688     case db_mode:
14689       oappend ("BYTE PTR ");
14690       break;
14691     case w_mode:
14692     case dw_mode:
14693     case dqw_mode:
14694       oappend ("WORD PTR ");
14695       break;
14696     case indir_v_mode:
14697       if (address_mode == mode_64bit && isa64 == intel64)
14698         {
14699           oappend ("QWORD PTR ");
14700           break;
14701         }
14702       /* Fall through.  */
14703     case stack_v_mode:
14704       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14705         {
14706           oappend ("QWORD PTR ");
14707           break;
14708         }
14709       /* Fall through.  */
14710     case v_mode:
14711     case v_swap_mode:
14712     case dq_mode:
14713       USED_REX (REX_W);
14714       if (rex & REX_W)
14715         oappend ("QWORD PTR ");
14716       else
14717         {
14718           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14719             oappend ("DWORD PTR ");
14720           else
14721             oappend ("WORD PTR ");
14722           used_prefixes |= (prefixes & PREFIX_DATA);
14723         }
14724       break;
14725     case z_mode:
14726       if ((rex & REX_W) || (sizeflag & DFLAG))
14727         *obufp++ = 'D';
14728       oappend ("WORD PTR ");
14729       if (!(rex & REX_W))
14730         used_prefixes |= (prefixes & PREFIX_DATA);
14731       break;
14732     case a_mode:
14733       if (sizeflag & DFLAG)
14734         oappend ("QWORD PTR ");
14735       else
14736         oappend ("DWORD PTR ");
14737       used_prefixes |= (prefixes & PREFIX_DATA);
14738       break;
14739     case d_mode:
14740     case d_scalar_mode:
14741     case d_scalar_swap_mode:
14742     case d_swap_mode:
14743     case dqd_mode:
14744       oappend ("DWORD PTR ");
14745       break;
14746     case q_mode:
14747     case q_scalar_mode:
14748     case q_scalar_swap_mode:
14749     case q_swap_mode:
14750       oappend ("QWORD PTR ");
14751       break;
14752     case m_mode:
14753       if (address_mode == mode_64bit)
14754         oappend ("QWORD PTR ");
14755       else
14756         oappend ("DWORD PTR ");
14757       break;
14758     case f_mode:
14759       if (sizeflag & DFLAG)
14760         oappend ("FWORD PTR ");
14761       else
14762         oappend ("DWORD PTR ");
14763       used_prefixes |= (prefixes & PREFIX_DATA);
14764       break;
14765     case t_mode:
14766       oappend ("TBYTE PTR ");
14767       break;
14768     case x_mode:
14769     case x_swap_mode:
14770     case evex_x_gscat_mode:
14771     case evex_x_nobcst_mode:
14772     case b_scalar_mode:
14773     case w_scalar_mode:
14774       if (need_vex)
14775         {
14776           switch (vex.length)
14777             {
14778             case 128:
14779               oappend ("XMMWORD PTR ");
14780               break;
14781             case 256:
14782               oappend ("YMMWORD PTR ");
14783               break;
14784             case 512:
14785               oappend ("ZMMWORD PTR ");
14786               break;
14787             default:
14788               abort ();
14789             }
14790         }
14791       else
14792         oappend ("XMMWORD PTR ");
14793       break;
14794     case xmm_mode:
14795       oappend ("XMMWORD PTR ");
14796       break;
14797     case ymm_mode:
14798       oappend ("YMMWORD PTR ");
14799       break;
14800     case xmmq_mode:
14801     case evex_half_bcst_xmmq_mode:
14802       if (!need_vex)
14803         abort ();
14804
14805       switch (vex.length)
14806         {
14807         case 128:
14808           oappend ("QWORD PTR ");
14809           break;
14810         case 256:
14811           oappend ("XMMWORD PTR ");
14812           break;
14813         case 512:
14814           oappend ("YMMWORD PTR ");
14815           break;
14816         default:
14817           abort ();
14818         }
14819       break;
14820     case xmm_mb_mode:
14821       if (!need_vex)
14822         abort ();
14823
14824       switch (vex.length)
14825         {
14826         case 128:
14827         case 256:
14828         case 512:
14829           oappend ("BYTE PTR ");
14830           break;
14831         default:
14832           abort ();
14833         }
14834       break;
14835     case xmm_mw_mode:
14836       if (!need_vex)
14837         abort ();
14838
14839       switch (vex.length)
14840         {
14841         case 128:
14842         case 256:
14843         case 512:
14844           oappend ("WORD PTR ");
14845           break;
14846         default:
14847           abort ();
14848         }
14849       break;
14850     case xmm_md_mode:
14851       if (!need_vex)
14852         abort ();
14853
14854       switch (vex.length)
14855         {
14856         case 128:
14857         case 256:
14858         case 512:
14859           oappend ("DWORD PTR ");
14860           break;
14861         default:
14862           abort ();
14863         }
14864       break;
14865     case xmm_mq_mode:
14866       if (!need_vex)
14867         abort ();
14868
14869       switch (vex.length)
14870         {
14871         case 128:
14872         case 256:
14873         case 512:
14874           oappend ("QWORD PTR ");
14875           break;
14876         default:
14877           abort ();
14878         }
14879       break;
14880     case xmmdw_mode:
14881       if (!need_vex)
14882         abort ();
14883
14884       switch (vex.length)
14885         {
14886         case 128:
14887           oappend ("WORD PTR ");
14888           break;
14889         case 256:
14890           oappend ("DWORD PTR ");
14891           break;
14892         case 512:
14893           oappend ("QWORD PTR ");
14894           break;
14895         default:
14896           abort ();
14897         }
14898       break;
14899     case xmmqd_mode:
14900       if (!need_vex)
14901         abort ();
14902
14903       switch (vex.length)
14904         {
14905         case 128:
14906           oappend ("DWORD PTR ");
14907           break;
14908         case 256:
14909           oappend ("QWORD PTR ");
14910           break;
14911         case 512:
14912           oappend ("XMMWORD PTR ");
14913           break;
14914         default:
14915           abort ();
14916         }
14917       break;
14918     case ymmq_mode:
14919       if (!need_vex)
14920         abort ();
14921
14922       switch (vex.length)
14923         {
14924         case 128:
14925           oappend ("QWORD PTR ");
14926           break;
14927         case 256:
14928           oappend ("YMMWORD PTR ");
14929           break;
14930         case 512:
14931           oappend ("ZMMWORD PTR ");
14932           break;
14933         default:
14934           abort ();
14935         }
14936       break;
14937     case ymmxmm_mode:
14938       if (!need_vex)
14939         abort ();
14940
14941       switch (vex.length)
14942         {
14943         case 128:
14944         case 256:
14945           oappend ("XMMWORD PTR ");
14946           break;
14947         default:
14948           abort ();
14949         }
14950       break;
14951     case o_mode:
14952       oappend ("OWORD PTR ");
14953       break;
14954     case xmm_mdq_mode:
14955     case vex_w_dq_mode:
14956     case vex_scalar_w_dq_mode:
14957       if (!need_vex)
14958         abort ();
14959
14960       if (vex.w)
14961         oappend ("QWORD PTR ");
14962       else
14963         oappend ("DWORD PTR ");
14964       break;
14965     case vex_vsib_d_w_dq_mode:
14966     case vex_vsib_q_w_dq_mode:
14967       if (!need_vex)
14968         abort ();
14969
14970       if (!vex.evex)
14971         {
14972           if (vex.w)
14973             oappend ("QWORD PTR ");
14974           else
14975             oappend ("DWORD PTR ");
14976         }
14977       else
14978         {
14979           switch (vex.length)
14980             {
14981             case 128:
14982               oappend ("XMMWORD PTR ");
14983               break;
14984             case 256:
14985               oappend ("YMMWORD PTR ");
14986               break;
14987             case 512:
14988               oappend ("ZMMWORD PTR ");
14989               break;
14990             default:
14991               abort ();
14992             }
14993         }
14994       break;
14995     case vex_vsib_q_w_d_mode:
14996     case vex_vsib_d_w_d_mode:
14997       if (!need_vex || !vex.evex)
14998         abort ();
14999
15000       switch (vex.length)
15001         {
15002         case 128:
15003           oappend ("QWORD PTR ");
15004           break;
15005         case 256:
15006           oappend ("XMMWORD PTR ");
15007           break;
15008         case 512:
15009           oappend ("YMMWORD PTR ");
15010           break;
15011         default:
15012           abort ();
15013         }
15014
15015       break;
15016     case mask_bd_mode:
15017       if (!need_vex || vex.length != 128)
15018         abort ();
15019       if (vex.w)
15020         oappend ("DWORD PTR ");
15021       else
15022         oappend ("BYTE PTR ");
15023       break;
15024     case mask_mode:
15025       if (!need_vex)
15026         abort ();
15027       if (vex.w)
15028         oappend ("QWORD PTR ");
15029       else
15030         oappend ("WORD PTR ");
15031       break;
15032     case v_bnd_mode:
15033     default:
15034       break;
15035     }
15036 }
15037
15038 static void
15039 OP_E_register (int bytemode, int sizeflag)
15040 {
15041   int reg = modrm.rm;
15042   const char **names;
15043
15044   USED_REX (REX_B);
15045   if ((rex & REX_B))
15046     reg += 8;
15047
15048   if ((sizeflag & SUFFIX_ALWAYS)
15049       && (bytemode == b_swap_mode
15050           || bytemode == v_swap_mode))
15051     swap_operand ();
15052
15053   switch (bytemode)
15054     {
15055     case b_mode:
15056     case b_swap_mode:
15057       USED_REX (0);
15058       if (rex)
15059         names = names8rex;
15060       else
15061         names = names8;
15062       break;
15063     case w_mode:
15064       names = names16;
15065       break;
15066     case d_mode:
15067     case dw_mode:
15068     case db_mode:
15069       names = names32;
15070       break;
15071     case q_mode:
15072       names = names64;
15073       break;
15074     case m_mode:
15075     case v_bnd_mode:
15076       names = address_mode == mode_64bit ? names64 : names32;
15077       break;
15078     case bnd_mode:
15079       if (reg > 0x3)
15080         {
15081           oappend ("(bad)");
15082           return;
15083         }
15084       names = names_bnd;
15085       break;
15086     case indir_v_mode:
15087       if (address_mode == mode_64bit && isa64 == intel64)
15088         {
15089           names = names64;
15090           break;
15091         }
15092       /* Fall through.  */
15093     case stack_v_mode:
15094       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15095         {
15096           names = names64;
15097           break;
15098         }
15099       bytemode = v_mode;
15100       /* Fall through.  */
15101     case v_mode:
15102     case v_swap_mode:
15103     case dq_mode:
15104     case dqb_mode:
15105     case dqd_mode:
15106     case dqw_mode:
15107       USED_REX (REX_W);
15108       if (rex & REX_W)
15109         names = names64;
15110       else
15111         {
15112           if ((sizeflag & DFLAG)
15113               || (bytemode != v_mode
15114                   && bytemode != v_swap_mode))
15115             names = names32;
15116           else
15117             names = names16;
15118           used_prefixes |= (prefixes & PREFIX_DATA);
15119         }
15120       break;
15121     case mask_bd_mode:
15122     case mask_mode:
15123       if (reg > 0x7)
15124         {
15125           oappend ("(bad)");
15126           return;
15127         }
15128       names = names_mask;
15129       break;
15130     case 0:
15131       return;
15132     default:
15133       oappend (INTERNAL_DISASSEMBLER_ERROR);
15134       return;
15135     }
15136   oappend (names[reg]);
15137 }
15138
15139 static void
15140 OP_E_memory (int bytemode, int sizeflag)
15141 {
15142   bfd_vma disp = 0;
15143   int add = (rex & REX_B) ? 8 : 0;
15144   int riprel = 0;
15145   int shift;
15146
15147   if (vex.evex)
15148     {
15149       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15150       if (vex.b
15151           && bytemode != x_mode
15152           && bytemode != xmmq_mode
15153           && bytemode != evex_half_bcst_xmmq_mode)
15154         {
15155           BadOp ();
15156           return;
15157         }
15158       switch (bytemode)
15159         {
15160         case dqw_mode:
15161         case dw_mode:
15162           shift = 1;
15163           break;
15164         case dqb_mode:
15165         case db_mode:
15166           shift = 0;
15167           break;
15168         case vex_vsib_d_w_dq_mode:
15169         case vex_vsib_d_w_d_mode:
15170         case vex_vsib_q_w_dq_mode:
15171         case vex_vsib_q_w_d_mode:
15172         case evex_x_gscat_mode:
15173         case xmm_mdq_mode:
15174           shift = vex.w ? 3 : 2;
15175           break;
15176         case x_mode:
15177         case evex_half_bcst_xmmq_mode:
15178         case xmmq_mode:
15179           if (vex.b)
15180             {
15181               shift = vex.w ? 3 : 2;
15182               break;
15183             }
15184           /* Fall through.  */
15185         case xmmqd_mode:
15186         case xmmdw_mode:
15187         case ymmq_mode:
15188         case evex_x_nobcst_mode:
15189         case x_swap_mode:
15190           switch (vex.length)
15191             {
15192             case 128:
15193               shift = 4;
15194               break;
15195             case 256:
15196               shift = 5;
15197               break;
15198             case 512:
15199               shift = 6;
15200               break;
15201             default:
15202               abort ();
15203             }
15204           break;
15205         case ymm_mode:
15206           shift = 5;
15207           break;
15208         case xmm_mode:
15209           shift = 4;
15210           break;
15211         case xmm_mq_mode:
15212         case q_mode:
15213         case q_scalar_mode:
15214         case q_swap_mode:
15215         case q_scalar_swap_mode:
15216           shift = 3;
15217           break;
15218         case dqd_mode:
15219         case xmm_md_mode:
15220         case d_mode:
15221         case d_scalar_mode:
15222         case d_swap_mode:
15223         case d_scalar_swap_mode:
15224           shift = 2;
15225           break;
15226     case w_scalar_mode:
15227         case xmm_mw_mode:
15228           shift = 1;
15229           break;
15230     case b_scalar_mode:
15231         case xmm_mb_mode:
15232           shift = 0;
15233           break;
15234         default:
15235           abort ();
15236         }
15237       /* Make necessary corrections to shift for modes that need it.
15238          For these modes we currently have shift 4, 5 or 6 depending on
15239          vex.length (it corresponds to xmmword, ymmword or zmmword
15240          operand).  We might want to make it 3, 4 or 5 (e.g. for
15241          xmmq_mode).  In case of broadcast enabled the corrections
15242          aren't needed, as element size is always 32 or 64 bits.  */
15243       if (!vex.b
15244           && (bytemode == xmmq_mode
15245               || bytemode == evex_half_bcst_xmmq_mode))
15246         shift -= 1;
15247       else if (bytemode == xmmqd_mode)
15248         shift -= 2;
15249       else if (bytemode == xmmdw_mode)
15250         shift -= 3;
15251       else if (bytemode == ymmq_mode && vex.length == 128)
15252         shift -= 1;
15253     }
15254   else
15255     shift = 0;
15256
15257   USED_REX (REX_B);
15258   if (intel_syntax)
15259     intel_operand_size (bytemode, sizeflag);
15260   append_seg ();
15261
15262   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15263     {
15264       /* 32/64 bit address mode */
15265       int havedisp;
15266       int havesib;
15267       int havebase;
15268       int haveindex;
15269       int needindex;
15270       int base, rbase;
15271       int vindex = 0;
15272       int scale = 0;
15273       int addr32flag = !((sizeflag & AFLAG)
15274                          || bytemode == v_bnd_mode
15275                          || bytemode == bnd_mode);
15276       const char **indexes64 = names64;
15277       const char **indexes32 = names32;
15278
15279       havesib = 0;
15280       havebase = 1;
15281       haveindex = 0;
15282       base = modrm.rm;
15283
15284       if (base == 4)
15285         {
15286           havesib = 1;
15287           vindex = sib.index;
15288           USED_REX (REX_X);
15289           if (rex & REX_X)
15290             vindex += 8;
15291           switch (bytemode)
15292             {
15293             case vex_vsib_d_w_dq_mode:
15294             case vex_vsib_d_w_d_mode:
15295             case vex_vsib_q_w_dq_mode:
15296             case vex_vsib_q_w_d_mode:
15297               if (!need_vex)
15298                 abort ();
15299               if (vex.evex)
15300                 {
15301                   if (!vex.v)
15302                     vindex += 16;
15303                 }
15304
15305               haveindex = 1;
15306               switch (vex.length)
15307                 {
15308                 case 128:
15309                   indexes64 = indexes32 = names_xmm;
15310                   break;
15311                 case 256:
15312                   if (!vex.w
15313                       || bytemode == vex_vsib_q_w_dq_mode
15314                       || bytemode == vex_vsib_q_w_d_mode)
15315                     indexes64 = indexes32 = names_ymm;
15316                   else
15317                     indexes64 = indexes32 = names_xmm;
15318                   break;
15319                 case 512:
15320                   if (!vex.w
15321                       || bytemode == vex_vsib_q_w_dq_mode
15322                       || bytemode == vex_vsib_q_w_d_mode)
15323                     indexes64 = indexes32 = names_zmm;
15324                   else
15325                     indexes64 = indexes32 = names_ymm;
15326                   break;
15327                 default:
15328                   abort ();
15329                 }
15330               break;
15331             default:
15332               haveindex = vindex != 4;
15333               break;
15334             }
15335           scale = sib.scale;
15336           base = sib.base;
15337           codep++;
15338         }
15339       rbase = base + add;
15340
15341       switch (modrm.mod)
15342         {
15343         case 0:
15344           if (base == 5)
15345             {
15346               havebase = 0;
15347               if (address_mode == mode_64bit && !havesib)
15348                 riprel = 1;
15349               disp = get32s ();
15350             }
15351           break;
15352         case 1:
15353           FETCH_DATA (the_info, codep + 1);
15354           disp = *codep++;
15355           if ((disp & 0x80) != 0)
15356             disp -= 0x100;
15357           if (vex.evex && shift > 0)
15358             disp <<= shift;
15359           break;
15360         case 2:
15361           disp = get32s ();
15362           break;
15363         }
15364
15365       /* In 32bit mode, we need index register to tell [offset] from
15366          [eiz*1 + offset].  */
15367       needindex = (havesib
15368                    && !havebase
15369                    && !haveindex
15370                    && address_mode == mode_32bit);
15371       havedisp = (havebase
15372                   || needindex
15373                   || (havesib && (haveindex || scale != 0)));
15374
15375       if (!intel_syntax)
15376         if (modrm.mod != 0 || base == 5)
15377           {
15378             if (havedisp || riprel)
15379               print_displacement (scratchbuf, disp);
15380             else
15381               print_operand_value (scratchbuf, 1, disp);
15382             oappend (scratchbuf);
15383             if (riprel)
15384               {
15385                 set_op (disp, 1);
15386                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15387               }
15388           }
15389
15390       if ((havebase || haveindex || riprel)
15391           && (bytemode != v_bnd_mode)
15392           && (bytemode != bnd_mode))
15393         used_prefixes |= PREFIX_ADDR;
15394
15395       if (havedisp || (intel_syntax && riprel))
15396         {
15397           *obufp++ = open_char;
15398           if (intel_syntax && riprel)
15399             {
15400               set_op (disp, 1);
15401               oappend (!addr32flag ? "rip" : "eip");
15402             }
15403           *obufp = '\0';
15404           if (havebase)
15405             oappend (address_mode == mode_64bit && !addr32flag
15406                      ? names64[rbase] : names32[rbase]);
15407           if (havesib)
15408             {
15409               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15410                  print index to tell base + index from base.  */
15411               if (scale != 0
15412                   || needindex
15413                   || haveindex
15414                   || (havebase && base != ESP_REG_NUM))
15415                 {
15416                   if (!intel_syntax || havebase)
15417                     {
15418                       *obufp++ = separator_char;
15419                       *obufp = '\0';
15420                     }
15421                   if (haveindex)
15422                     oappend (address_mode == mode_64bit && !addr32flag
15423                              ? indexes64[vindex] : indexes32[vindex]);
15424                   else
15425                     oappend (address_mode == mode_64bit && !addr32flag
15426                              ? index64 : index32);
15427
15428                   *obufp++ = scale_char;
15429                   *obufp = '\0';
15430                   sprintf (scratchbuf, "%d", 1 << scale);
15431                   oappend (scratchbuf);
15432                 }
15433             }
15434           if (intel_syntax
15435               && (disp || modrm.mod != 0 || base == 5))
15436             {
15437               if (!havedisp || (bfd_signed_vma) disp >= 0)
15438                 {
15439                   *obufp++ = '+';
15440                   *obufp = '\0';
15441                 }
15442               else if (modrm.mod != 1 && disp != -disp)
15443                 {
15444                   *obufp++ = '-';
15445                   *obufp = '\0';
15446                   disp = - (bfd_signed_vma) disp;
15447                 }
15448
15449               if (havedisp)
15450                 print_displacement (scratchbuf, disp);
15451               else
15452                 print_operand_value (scratchbuf, 1, disp);
15453               oappend (scratchbuf);
15454             }
15455
15456           *obufp++ = close_char;
15457           *obufp = '\0';
15458         }
15459       else if (intel_syntax)
15460         {
15461           if (modrm.mod != 0 || base == 5)
15462             {
15463               if (!active_seg_prefix)
15464                 {
15465                   oappend (names_seg[ds_reg - es_reg]);
15466                   oappend (":");
15467                 }
15468               print_operand_value (scratchbuf, 1, disp);
15469               oappend (scratchbuf);
15470             }
15471         }
15472     }
15473   else
15474     {
15475       /* 16 bit address mode */
15476       used_prefixes |= prefixes & PREFIX_ADDR;
15477       switch (modrm.mod)
15478         {
15479         case 0:
15480           if (modrm.rm == 6)
15481             {
15482               disp = get16 ();
15483               if ((disp & 0x8000) != 0)
15484                 disp -= 0x10000;
15485             }
15486           break;
15487         case 1:
15488           FETCH_DATA (the_info, codep + 1);
15489           disp = *codep++;
15490           if ((disp & 0x80) != 0)
15491             disp -= 0x100;
15492           if (vex.evex && shift > 0)
15493             disp <<= shift;
15494           break;
15495         case 2:
15496           disp = get16 ();
15497           if ((disp & 0x8000) != 0)
15498             disp -= 0x10000;
15499           break;
15500         }
15501
15502       if (!intel_syntax)
15503         if (modrm.mod != 0 || modrm.rm == 6)
15504           {
15505             print_displacement (scratchbuf, disp);
15506             oappend (scratchbuf);
15507           }
15508
15509       if (modrm.mod != 0 || modrm.rm != 6)
15510         {
15511           *obufp++ = open_char;
15512           *obufp = '\0';
15513           oappend (index16[modrm.rm]);
15514           if (intel_syntax
15515               && (disp || modrm.mod != 0 || modrm.rm == 6))
15516             {
15517               if ((bfd_signed_vma) disp >= 0)
15518                 {
15519                   *obufp++ = '+';
15520                   *obufp = '\0';
15521                 }
15522               else if (modrm.mod != 1)
15523                 {
15524                   *obufp++ = '-';
15525                   *obufp = '\0';
15526                   disp = - (bfd_signed_vma) disp;
15527                 }
15528
15529               print_displacement (scratchbuf, disp);
15530               oappend (scratchbuf);
15531             }
15532
15533           *obufp++ = close_char;
15534           *obufp = '\0';
15535         }
15536       else if (intel_syntax)
15537         {
15538           if (!active_seg_prefix)
15539             {
15540               oappend (names_seg[ds_reg - es_reg]);
15541               oappend (":");
15542             }
15543           print_operand_value (scratchbuf, 1, disp & 0xffff);
15544           oappend (scratchbuf);
15545         }
15546     }
15547   if (vex.evex && vex.b
15548       && (bytemode == x_mode
15549           || bytemode == xmmq_mode
15550           || bytemode == evex_half_bcst_xmmq_mode))
15551     {
15552       if (vex.w
15553           || bytemode == xmmq_mode
15554           || bytemode == evex_half_bcst_xmmq_mode)
15555         {
15556           switch (vex.length)
15557             {
15558             case 128:
15559               oappend ("{1to2}");
15560               break;
15561             case 256:
15562               oappend ("{1to4}");
15563               break;
15564             case 512:
15565               oappend ("{1to8}");
15566               break;
15567             default:
15568               abort ();
15569             }
15570         }
15571       else
15572         {
15573           switch (vex.length)
15574             {
15575             case 128:
15576               oappend ("{1to4}");
15577               break;
15578             case 256:
15579               oappend ("{1to8}");
15580               break;
15581             case 512:
15582               oappend ("{1to16}");
15583               break;
15584             default:
15585               abort ();
15586             }
15587         }
15588     }
15589 }
15590
15591 static void
15592 OP_E (int bytemode, int sizeflag)
15593 {
15594   /* Skip mod/rm byte.  */
15595   MODRM_CHECK;
15596   codep++;
15597
15598   if (modrm.mod == 3)
15599     OP_E_register (bytemode, sizeflag);
15600   else
15601     OP_E_memory (bytemode, sizeflag);
15602 }
15603
15604 static void
15605 OP_G (int bytemode, int sizeflag)
15606 {
15607   int add = 0;
15608   USED_REX (REX_R);
15609   if (rex & REX_R)
15610     add += 8;
15611   switch (bytemode)
15612     {
15613     case b_mode:
15614       USED_REX (0);
15615       if (rex)
15616         oappend (names8rex[modrm.reg + add]);
15617       else
15618         oappend (names8[modrm.reg + add]);
15619       break;
15620     case w_mode:
15621       oappend (names16[modrm.reg + add]);
15622       break;
15623     case d_mode:
15624     case db_mode:
15625     case dw_mode:
15626       oappend (names32[modrm.reg + add]);
15627       break;
15628     case q_mode:
15629       oappend (names64[modrm.reg + add]);
15630       break;
15631     case bnd_mode:
15632       if (modrm.reg > 0x3)
15633         {
15634           oappend ("(bad)");
15635           return;
15636         }
15637       oappend (names_bnd[modrm.reg]);
15638       break;
15639     case v_mode:
15640     case dq_mode:
15641     case dqb_mode:
15642     case dqd_mode:
15643     case dqw_mode:
15644       USED_REX (REX_W);
15645       if (rex & REX_W)
15646         oappend (names64[modrm.reg + add]);
15647       else
15648         {
15649           if ((sizeflag & DFLAG) || bytemode != v_mode)
15650             oappend (names32[modrm.reg + add]);
15651           else
15652             oappend (names16[modrm.reg + add]);
15653           used_prefixes |= (prefixes & PREFIX_DATA);
15654         }
15655       break;
15656     case m_mode:
15657       if (address_mode == mode_64bit)
15658         oappend (names64[modrm.reg + add]);
15659       else
15660         oappend (names32[modrm.reg + add]);
15661       break;
15662     case mask_bd_mode:
15663     case mask_mode:
15664       if ((modrm.reg + add) > 0x7)
15665         {
15666           oappend ("(bad)");
15667           return;
15668         }
15669       oappend (names_mask[modrm.reg + add]);
15670       break;
15671     default:
15672       oappend (INTERNAL_DISASSEMBLER_ERROR);
15673       break;
15674     }
15675 }
15676
15677 static bfd_vma
15678 get64 (void)
15679 {
15680   bfd_vma x;
15681 #ifdef BFD64
15682   unsigned int a;
15683   unsigned int b;
15684
15685   FETCH_DATA (the_info, codep + 8);
15686   a = *codep++ & 0xff;
15687   a |= (*codep++ & 0xff) << 8;
15688   a |= (*codep++ & 0xff) << 16;
15689   a |= (*codep++ & 0xffu) << 24;
15690   b = *codep++ & 0xff;
15691   b |= (*codep++ & 0xff) << 8;
15692   b |= (*codep++ & 0xff) << 16;
15693   b |= (*codep++ & 0xffu) << 24;
15694   x = a + ((bfd_vma) b << 32);
15695 #else
15696   abort ();
15697   x = 0;
15698 #endif
15699   return x;
15700 }
15701
15702 static bfd_signed_vma
15703 get32 (void)
15704 {
15705   bfd_signed_vma x = 0;
15706
15707   FETCH_DATA (the_info, codep + 4);
15708   x = *codep++ & (bfd_signed_vma) 0xff;
15709   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15710   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15711   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15712   return x;
15713 }
15714
15715 static bfd_signed_vma
15716 get32s (void)
15717 {
15718   bfd_signed_vma x = 0;
15719
15720   FETCH_DATA (the_info, codep + 4);
15721   x = *codep++ & (bfd_signed_vma) 0xff;
15722   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15723   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15724   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15725
15726   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15727
15728   return x;
15729 }
15730
15731 static int
15732 get16 (void)
15733 {
15734   int x = 0;
15735
15736   FETCH_DATA (the_info, codep + 2);
15737   x = *codep++ & 0xff;
15738   x |= (*codep++ & 0xff) << 8;
15739   return x;
15740 }
15741
15742 static void
15743 set_op (bfd_vma op, int riprel)
15744 {
15745   op_index[op_ad] = op_ad;
15746   if (address_mode == mode_64bit)
15747     {
15748       op_address[op_ad] = op;
15749       op_riprel[op_ad] = riprel;
15750     }
15751   else
15752     {
15753       /* Mask to get a 32-bit address.  */
15754       op_address[op_ad] = op & 0xffffffff;
15755       op_riprel[op_ad] = riprel & 0xffffffff;
15756     }
15757 }
15758
15759 static void
15760 OP_REG (int code, int sizeflag)
15761 {
15762   const char *s;
15763   int add;
15764
15765   switch (code)
15766     {
15767     case es_reg: case ss_reg: case cs_reg:
15768     case ds_reg: case fs_reg: case gs_reg:
15769       oappend (names_seg[code - es_reg]);
15770       return;
15771     }
15772
15773   USED_REX (REX_B);
15774   if (rex & REX_B)
15775     add = 8;
15776   else
15777     add = 0;
15778
15779   switch (code)
15780     {
15781     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15782     case sp_reg: case bp_reg: case si_reg: case di_reg:
15783       s = names16[code - ax_reg + add];
15784       break;
15785     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15786     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15787       USED_REX (0);
15788       if (rex)
15789         s = names8rex[code - al_reg + add];
15790       else
15791         s = names8[code - al_reg];
15792       break;
15793     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15794     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15795       if (address_mode == mode_64bit
15796           && ((sizeflag & DFLAG) || (rex & REX_W)))
15797         {
15798           s = names64[code - rAX_reg + add];
15799           break;
15800         }
15801       code += eAX_reg - rAX_reg;
15802       /* Fall through.  */
15803     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15804     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15805       USED_REX (REX_W);
15806       if (rex & REX_W)
15807         s = names64[code - eAX_reg + add];
15808       else
15809         {
15810           if (sizeflag & DFLAG)
15811             s = names32[code - eAX_reg + add];
15812           else
15813             s = names16[code - eAX_reg + add];
15814           used_prefixes |= (prefixes & PREFIX_DATA);
15815         }
15816       break;
15817     default:
15818       s = INTERNAL_DISASSEMBLER_ERROR;
15819       break;
15820     }
15821   oappend (s);
15822 }
15823
15824 static void
15825 OP_IMREG (int code, int sizeflag)
15826 {
15827   const char *s;
15828
15829   switch (code)
15830     {
15831     case indir_dx_reg:
15832       if (intel_syntax)
15833         s = "dx";
15834       else
15835         s = "(%dx)";
15836       break;
15837     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15838     case sp_reg: case bp_reg: case si_reg: case di_reg:
15839       s = names16[code - ax_reg];
15840       break;
15841     case es_reg: case ss_reg: case cs_reg:
15842     case ds_reg: case fs_reg: case gs_reg:
15843       s = names_seg[code - es_reg];
15844       break;
15845     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15846     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15847       USED_REX (0);
15848       if (rex)
15849         s = names8rex[code - al_reg];
15850       else
15851         s = names8[code - al_reg];
15852       break;
15853     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15854     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15855       USED_REX (REX_W);
15856       if (rex & REX_W)
15857         s = names64[code - eAX_reg];
15858       else
15859         {
15860           if (sizeflag & DFLAG)
15861             s = names32[code - eAX_reg];
15862           else
15863             s = names16[code - eAX_reg];
15864           used_prefixes |= (prefixes & PREFIX_DATA);
15865         }
15866       break;
15867     case z_mode_ax_reg:
15868       if ((rex & REX_W) || (sizeflag & DFLAG))
15869         s = *names32;
15870       else
15871         s = *names16;
15872       if (!(rex & REX_W))
15873         used_prefixes |= (prefixes & PREFIX_DATA);
15874       break;
15875     default:
15876       s = INTERNAL_DISASSEMBLER_ERROR;
15877       break;
15878     }
15879   oappend (s);
15880 }
15881
15882 static void
15883 OP_I (int bytemode, int sizeflag)
15884 {
15885   bfd_signed_vma op;
15886   bfd_signed_vma mask = -1;
15887
15888   switch (bytemode)
15889     {
15890     case b_mode:
15891       FETCH_DATA (the_info, codep + 1);
15892       op = *codep++;
15893       mask = 0xff;
15894       break;
15895     case q_mode:
15896       if (address_mode == mode_64bit)
15897         {
15898           op = get32s ();
15899           break;
15900         }
15901       /* Fall through.  */
15902     case v_mode:
15903       USED_REX (REX_W);
15904       if (rex & REX_W)
15905         op = get32s ();
15906       else
15907         {
15908           if (sizeflag & DFLAG)
15909             {
15910               op = get32 ();
15911               mask = 0xffffffff;
15912             }
15913           else
15914             {
15915               op = get16 ();
15916               mask = 0xfffff;
15917             }
15918           used_prefixes |= (prefixes & PREFIX_DATA);
15919         }
15920       break;
15921     case w_mode:
15922       mask = 0xfffff;
15923       op = get16 ();
15924       break;
15925     case const_1_mode:
15926       if (intel_syntax)
15927         oappend ("1");
15928       return;
15929     default:
15930       oappend (INTERNAL_DISASSEMBLER_ERROR);
15931       return;
15932     }
15933
15934   op &= mask;
15935   scratchbuf[0] = '$';
15936   print_operand_value (scratchbuf + 1, 1, op);
15937   oappend_maybe_intel (scratchbuf);
15938   scratchbuf[0] = '\0';
15939 }
15940
15941 static void
15942 OP_I64 (int bytemode, int sizeflag)
15943 {
15944   bfd_signed_vma op;
15945   bfd_signed_vma mask = -1;
15946
15947   if (address_mode != mode_64bit)
15948     {
15949       OP_I (bytemode, sizeflag);
15950       return;
15951     }
15952
15953   switch (bytemode)
15954     {
15955     case b_mode:
15956       FETCH_DATA (the_info, codep + 1);
15957       op = *codep++;
15958       mask = 0xff;
15959       break;
15960     case v_mode:
15961       USED_REX (REX_W);
15962       if (rex & REX_W)
15963         op = get64 ();
15964       else
15965         {
15966           if (sizeflag & DFLAG)
15967             {
15968               op = get32 ();
15969               mask = 0xffffffff;
15970             }
15971           else
15972             {
15973               op = get16 ();
15974               mask = 0xfffff;
15975             }
15976           used_prefixes |= (prefixes & PREFIX_DATA);
15977         }
15978       break;
15979     case w_mode:
15980       mask = 0xfffff;
15981       op = get16 ();
15982       break;
15983     default:
15984       oappend (INTERNAL_DISASSEMBLER_ERROR);
15985       return;
15986     }
15987
15988   op &= mask;
15989   scratchbuf[0] = '$';
15990   print_operand_value (scratchbuf + 1, 1, op);
15991   oappend_maybe_intel (scratchbuf);
15992   scratchbuf[0] = '\0';
15993 }
15994
15995 static void
15996 OP_sI (int bytemode, int sizeflag)
15997 {
15998   bfd_signed_vma op;
15999
16000   switch (bytemode)
16001     {
16002     case b_mode:
16003     case b_T_mode:
16004       FETCH_DATA (the_info, codep + 1);
16005       op = *codep++;
16006       if ((op & 0x80) != 0)
16007         op -= 0x100;
16008       if (bytemode == b_T_mode)
16009         {
16010           if (address_mode != mode_64bit
16011               || !((sizeflag & DFLAG) || (rex & REX_W)))
16012             {
16013               /* The operand-size prefix is overridden by a REX prefix.  */
16014               if ((sizeflag & DFLAG) || (rex & REX_W))
16015                 op &= 0xffffffff;
16016               else
16017                 op &= 0xffff;
16018           }
16019         }
16020       else
16021         {
16022           if (!(rex & REX_W))
16023             {
16024               if (sizeflag & DFLAG)
16025                 op &= 0xffffffff;
16026               else
16027                 op &= 0xffff;
16028             }
16029         }
16030       break;
16031     case v_mode:
16032       /* The operand-size prefix is overridden by a REX prefix.  */
16033       if ((sizeflag & DFLAG) || (rex & REX_W))
16034         op = get32s ();
16035       else
16036         op = get16 ();
16037       break;
16038     default:
16039       oappend (INTERNAL_DISASSEMBLER_ERROR);
16040       return;
16041     }
16042
16043   scratchbuf[0] = '$';
16044   print_operand_value (scratchbuf + 1, 1, op);
16045   oappend_maybe_intel (scratchbuf);
16046 }
16047
16048 static void
16049 OP_J (int bytemode, int sizeflag)
16050 {
16051   bfd_vma disp;
16052   bfd_vma mask = -1;
16053   bfd_vma segment = 0;
16054
16055   switch (bytemode)
16056     {
16057     case b_mode:
16058       FETCH_DATA (the_info, codep + 1);
16059       disp = *codep++;
16060       if ((disp & 0x80) != 0)
16061         disp -= 0x100;
16062       break;
16063     case v_mode:
16064       if (isa64 == amd64)
16065         USED_REX (REX_W);
16066       if ((sizeflag & DFLAG)
16067           || (address_mode == mode_64bit
16068               && (isa64 != amd64 || (rex & REX_W))))
16069         disp = get32s ();
16070       else
16071         {
16072           disp = get16 ();
16073           if ((disp & 0x8000) != 0)
16074             disp -= 0x10000;
16075           /* In 16bit mode, address is wrapped around at 64k within
16076              the same segment.  Otherwise, a data16 prefix on a jump
16077              instruction means that the pc is masked to 16 bits after
16078              the displacement is added!  */
16079           mask = 0xffff;
16080           if ((prefixes & PREFIX_DATA) == 0)
16081             segment = ((start_pc + (codep - start_codep))
16082                        & ~((bfd_vma) 0xffff));
16083         }
16084       if (address_mode != mode_64bit
16085           || (isa64 == amd64 && !(rex & REX_W)))
16086         used_prefixes |= (prefixes & PREFIX_DATA);
16087       break;
16088     default:
16089       oappend (INTERNAL_DISASSEMBLER_ERROR);
16090       return;
16091     }
16092   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16093   set_op (disp, 0);
16094   print_operand_value (scratchbuf, 1, disp);
16095   oappend (scratchbuf);
16096 }
16097
16098 static void
16099 OP_SEG (int bytemode, int sizeflag)
16100 {
16101   if (bytemode == w_mode)
16102     oappend (names_seg[modrm.reg]);
16103   else
16104     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16105 }
16106
16107 static void
16108 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16109 {
16110   int seg, offset;
16111
16112   if (sizeflag & DFLAG)
16113     {
16114       offset = get32 ();
16115       seg = get16 ();
16116     }
16117   else
16118     {
16119       offset = get16 ();
16120       seg = get16 ();
16121     }
16122   used_prefixes |= (prefixes & PREFIX_DATA);
16123   if (intel_syntax)
16124     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16125   else
16126     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16127   oappend (scratchbuf);
16128 }
16129
16130 static void
16131 OP_OFF (int bytemode, int sizeflag)
16132 {
16133   bfd_vma off;
16134
16135   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16136     intel_operand_size (bytemode, sizeflag);
16137   append_seg ();
16138
16139   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16140     off = get32 ();
16141   else
16142     off = get16 ();
16143
16144   if (intel_syntax)
16145     {
16146       if (!active_seg_prefix)
16147         {
16148           oappend (names_seg[ds_reg - es_reg]);
16149           oappend (":");
16150         }
16151     }
16152   print_operand_value (scratchbuf, 1, off);
16153   oappend (scratchbuf);
16154 }
16155
16156 static void
16157 OP_OFF64 (int bytemode, int sizeflag)
16158 {
16159   bfd_vma off;
16160
16161   if (address_mode != mode_64bit
16162       || (prefixes & PREFIX_ADDR))
16163     {
16164       OP_OFF (bytemode, sizeflag);
16165       return;
16166     }
16167
16168   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16169     intel_operand_size (bytemode, sizeflag);
16170   append_seg ();
16171
16172   off = get64 ();
16173
16174   if (intel_syntax)
16175     {
16176       if (!active_seg_prefix)
16177         {
16178           oappend (names_seg[ds_reg - es_reg]);
16179           oappend (":");
16180         }
16181     }
16182   print_operand_value (scratchbuf, 1, off);
16183   oappend (scratchbuf);
16184 }
16185
16186 static void
16187 ptr_reg (int code, int sizeflag)
16188 {
16189   const char *s;
16190
16191   *obufp++ = open_char;
16192   used_prefixes |= (prefixes & PREFIX_ADDR);
16193   if (address_mode == mode_64bit)
16194     {
16195       if (!(sizeflag & AFLAG))
16196         s = names32[code - eAX_reg];
16197       else
16198         s = names64[code - eAX_reg];
16199     }
16200   else if (sizeflag & AFLAG)
16201     s = names32[code - eAX_reg];
16202   else
16203     s = names16[code - eAX_reg];
16204   oappend (s);
16205   *obufp++ = close_char;
16206   *obufp = 0;
16207 }
16208
16209 static void
16210 OP_ESreg (int code, int sizeflag)
16211 {
16212   if (intel_syntax)
16213     {
16214       switch (codep[-1])
16215         {
16216         case 0x6d:      /* insw/insl */
16217           intel_operand_size (z_mode, sizeflag);
16218           break;
16219         case 0xa5:      /* movsw/movsl/movsq */
16220         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16221         case 0xab:      /* stosw/stosl */
16222         case 0xaf:      /* scasw/scasl */
16223           intel_operand_size (v_mode, sizeflag);
16224           break;
16225         default:
16226           intel_operand_size (b_mode, sizeflag);
16227         }
16228     }
16229   oappend_maybe_intel ("%es:");
16230   ptr_reg (code, sizeflag);
16231 }
16232
16233 static void
16234 OP_DSreg (int code, int sizeflag)
16235 {
16236   if (intel_syntax)
16237     {
16238       switch (codep[-1])
16239         {
16240         case 0x6f:      /* outsw/outsl */
16241           intel_operand_size (z_mode, sizeflag);
16242           break;
16243         case 0xa5:      /* movsw/movsl/movsq */
16244         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16245         case 0xad:      /* lodsw/lodsl/lodsq */
16246           intel_operand_size (v_mode, sizeflag);
16247           break;
16248         default:
16249           intel_operand_size (b_mode, sizeflag);
16250         }
16251     }
16252   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16253      default segment register DS is printed.  */
16254   if (!active_seg_prefix)
16255     active_seg_prefix = PREFIX_DS;
16256   append_seg ();
16257   ptr_reg (code, sizeflag);
16258 }
16259
16260 static void
16261 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16262 {
16263   int add;
16264   if (rex & REX_R)
16265     {
16266       USED_REX (REX_R);
16267       add = 8;
16268     }
16269   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16270     {
16271       all_prefixes[last_lock_prefix] = 0;
16272       used_prefixes |= PREFIX_LOCK;
16273       add = 8;
16274     }
16275   else
16276     add = 0;
16277   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16278   oappend_maybe_intel (scratchbuf);
16279 }
16280
16281 static void
16282 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16283 {
16284   int add;
16285   USED_REX (REX_R);
16286   if (rex & REX_R)
16287     add = 8;
16288   else
16289     add = 0;
16290   if (intel_syntax)
16291     sprintf (scratchbuf, "db%d", modrm.reg + add);
16292   else
16293     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16294   oappend (scratchbuf);
16295 }
16296
16297 static void
16298 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16299 {
16300   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16301   oappend_maybe_intel (scratchbuf);
16302 }
16303
16304 static void
16305 OP_R (int bytemode, int sizeflag)
16306 {
16307   /* Skip mod/rm byte.  */
16308   MODRM_CHECK;
16309   codep++;
16310   OP_E_register (bytemode, sizeflag);
16311 }
16312
16313 static void
16314 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16315 {
16316   int reg = modrm.reg;
16317   const char **names;
16318
16319   used_prefixes |= (prefixes & PREFIX_DATA);
16320   if (prefixes & PREFIX_DATA)
16321     {
16322       names = names_xmm;
16323       USED_REX (REX_R);
16324       if (rex & REX_R)
16325         reg += 8;
16326     }
16327   else
16328     names = names_mm;
16329   oappend (names[reg]);
16330 }
16331
16332 static void
16333 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16334 {
16335   int reg = modrm.reg;
16336   const char **names;
16337
16338   USED_REX (REX_R);
16339   if (rex & REX_R)
16340     reg += 8;
16341   if (vex.evex)
16342     {
16343       if (!vex.r)
16344         reg += 16;
16345     }
16346
16347   if (need_vex
16348       && bytemode != xmm_mode
16349       && bytemode != xmmq_mode
16350       && bytemode != evex_half_bcst_xmmq_mode
16351       && bytemode != ymm_mode
16352       && bytemode != scalar_mode)
16353     {
16354       switch (vex.length)
16355         {
16356         case 128:
16357           names = names_xmm;
16358           break;
16359         case 256:
16360           if (vex.w
16361               || (bytemode != vex_vsib_q_w_dq_mode
16362                   && bytemode != vex_vsib_q_w_d_mode))
16363             names = names_ymm;
16364           else
16365             names = names_xmm;
16366           break;
16367         case 512:
16368           names = names_zmm;
16369           break;
16370         default:
16371           abort ();
16372         }
16373     }
16374   else if (bytemode == xmmq_mode
16375            || bytemode == evex_half_bcst_xmmq_mode)
16376     {
16377       switch (vex.length)
16378         {
16379         case 128:
16380         case 256:
16381           names = names_xmm;
16382           break;
16383         case 512:
16384           names = names_ymm;
16385           break;
16386         default:
16387           abort ();
16388         }
16389     }
16390   else if (bytemode == ymm_mode)
16391     names = names_ymm;
16392   else
16393     names = names_xmm;
16394   oappend (names[reg]);
16395 }
16396
16397 static void
16398 OP_EM (int bytemode, int sizeflag)
16399 {
16400   int reg;
16401   const char **names;
16402
16403   if (modrm.mod != 3)
16404     {
16405       if (intel_syntax
16406           && (bytemode == v_mode || bytemode == v_swap_mode))
16407         {
16408           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16409           used_prefixes |= (prefixes & PREFIX_DATA);
16410         }
16411       OP_E (bytemode, sizeflag);
16412       return;
16413     }
16414
16415   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16416     swap_operand ();
16417
16418   /* Skip mod/rm byte.  */
16419   MODRM_CHECK;
16420   codep++;
16421   used_prefixes |= (prefixes & PREFIX_DATA);
16422   reg = modrm.rm;
16423   if (prefixes & PREFIX_DATA)
16424     {
16425       names = names_xmm;
16426       USED_REX (REX_B);
16427       if (rex & REX_B)
16428         reg += 8;
16429     }
16430   else
16431     names = names_mm;
16432   oappend (names[reg]);
16433 }
16434
16435 /* cvt* are the only instructions in sse2 which have
16436    both SSE and MMX operands and also have 0x66 prefix
16437    in their opcode. 0x66 was originally used to differentiate
16438    between SSE and MMX instruction(operands). So we have to handle the
16439    cvt* separately using OP_EMC and OP_MXC */
16440 static void
16441 OP_EMC (int bytemode, int sizeflag)
16442 {
16443   if (modrm.mod != 3)
16444     {
16445       if (intel_syntax && bytemode == v_mode)
16446         {
16447           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16448           used_prefixes |= (prefixes & PREFIX_DATA);
16449         }
16450       OP_E (bytemode, sizeflag);
16451       return;
16452     }
16453
16454   /* Skip mod/rm byte.  */
16455   MODRM_CHECK;
16456   codep++;
16457   used_prefixes |= (prefixes & PREFIX_DATA);
16458   oappend (names_mm[modrm.rm]);
16459 }
16460
16461 static void
16462 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16463 {
16464   used_prefixes |= (prefixes & PREFIX_DATA);
16465   oappend (names_mm[modrm.reg]);
16466 }
16467
16468 static void
16469 OP_EX (int bytemode, int sizeflag)
16470 {
16471   int reg;
16472   const char **names;
16473
16474   /* Skip mod/rm byte.  */
16475   MODRM_CHECK;
16476   codep++;
16477
16478   if (modrm.mod != 3)
16479     {
16480       OP_E_memory (bytemode, sizeflag);
16481       return;
16482     }
16483
16484   reg = modrm.rm;
16485   USED_REX (REX_B);
16486   if (rex & REX_B)
16487     reg += 8;
16488   if (vex.evex)
16489     {
16490       USED_REX (REX_X);
16491       if ((rex & REX_X))
16492         reg += 16;
16493     }
16494
16495   if ((sizeflag & SUFFIX_ALWAYS)
16496       && (bytemode == x_swap_mode
16497           || bytemode == d_swap_mode
16498           || bytemode == d_scalar_swap_mode
16499           || bytemode == q_swap_mode
16500           || bytemode == q_scalar_swap_mode))
16501     swap_operand ();
16502
16503   if (need_vex
16504       && bytemode != xmm_mode
16505       && bytemode != xmmdw_mode
16506       && bytemode != xmmqd_mode
16507       && bytemode != xmm_mb_mode
16508       && bytemode != xmm_mw_mode
16509       && bytemode != xmm_md_mode
16510       && bytemode != xmm_mq_mode
16511       && bytemode != xmm_mdq_mode
16512       && bytemode != xmmq_mode
16513       && bytemode != evex_half_bcst_xmmq_mode
16514       && bytemode != ymm_mode
16515       && bytemode != d_scalar_mode
16516       && bytemode != d_scalar_swap_mode
16517       && bytemode != q_scalar_mode
16518       && bytemode != q_scalar_swap_mode
16519       && bytemode != vex_scalar_w_dq_mode)
16520     {
16521       switch (vex.length)
16522         {
16523         case 128:
16524           names = names_xmm;
16525           break;
16526         case 256:
16527           names = names_ymm;
16528           break;
16529         case 512:
16530           names = names_zmm;
16531           break;
16532         default:
16533           abort ();
16534         }
16535     }
16536   else if (bytemode == xmmq_mode
16537            || bytemode == evex_half_bcst_xmmq_mode)
16538     {
16539       switch (vex.length)
16540         {
16541         case 128:
16542         case 256:
16543           names = names_xmm;
16544           break;
16545         case 512:
16546           names = names_ymm;
16547           break;
16548         default:
16549           abort ();
16550         }
16551     }
16552   else if (bytemode == ymm_mode)
16553     names = names_ymm;
16554   else
16555     names = names_xmm;
16556   oappend (names[reg]);
16557 }
16558
16559 static void
16560 OP_MS (int bytemode, int sizeflag)
16561 {
16562   if (modrm.mod == 3)
16563     OP_EM (bytemode, sizeflag);
16564   else
16565     BadOp ();
16566 }
16567
16568 static void
16569 OP_XS (int bytemode, int sizeflag)
16570 {
16571   if (modrm.mod == 3)
16572     OP_EX (bytemode, sizeflag);
16573   else
16574     BadOp ();
16575 }
16576
16577 static void
16578 OP_M (int bytemode, int sizeflag)
16579 {
16580   if (modrm.mod == 3)
16581     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16582     BadOp ();
16583   else
16584     OP_E (bytemode, sizeflag);
16585 }
16586
16587 static void
16588 OP_0f07 (int bytemode, int sizeflag)
16589 {
16590   if (modrm.mod != 3 || modrm.rm != 0)
16591     BadOp ();
16592   else
16593     OP_E (bytemode, sizeflag);
16594 }
16595
16596 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16597    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16598
16599 static void
16600 NOP_Fixup1 (int bytemode, int sizeflag)
16601 {
16602   if ((prefixes & PREFIX_DATA) != 0
16603       || (rex != 0
16604           && rex != 0x48
16605           && address_mode == mode_64bit))
16606     OP_REG (bytemode, sizeflag);
16607   else
16608     strcpy (obuf, "nop");
16609 }
16610
16611 static void
16612 NOP_Fixup2 (int bytemode, int sizeflag)
16613 {
16614   if ((prefixes & PREFIX_DATA) != 0
16615       || (rex != 0
16616           && rex != 0x48
16617           && address_mode == mode_64bit))
16618     OP_IMREG (bytemode, sizeflag);
16619 }
16620
16621 static const char *const Suffix3DNow[] = {
16622 /* 00 */        NULL,           NULL,           NULL,           NULL,
16623 /* 04 */        NULL,           NULL,           NULL,           NULL,
16624 /* 08 */        NULL,           NULL,           NULL,           NULL,
16625 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16626 /* 10 */        NULL,           NULL,           NULL,           NULL,
16627 /* 14 */        NULL,           NULL,           NULL,           NULL,
16628 /* 18 */        NULL,           NULL,           NULL,           NULL,
16629 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16630 /* 20 */        NULL,           NULL,           NULL,           NULL,
16631 /* 24 */        NULL,           NULL,           NULL,           NULL,
16632 /* 28 */        NULL,           NULL,           NULL,           NULL,
16633 /* 2C */        NULL,           NULL,           NULL,           NULL,
16634 /* 30 */        NULL,           NULL,           NULL,           NULL,
16635 /* 34 */        NULL,           NULL,           NULL,           NULL,
16636 /* 38 */        NULL,           NULL,           NULL,           NULL,
16637 /* 3C */        NULL,           NULL,           NULL,           NULL,
16638 /* 40 */        NULL,           NULL,           NULL,           NULL,
16639 /* 44 */        NULL,           NULL,           NULL,           NULL,
16640 /* 48 */        NULL,           NULL,           NULL,           NULL,
16641 /* 4C */        NULL,           NULL,           NULL,           NULL,
16642 /* 50 */        NULL,           NULL,           NULL,           NULL,
16643 /* 54 */        NULL,           NULL,           NULL,           NULL,
16644 /* 58 */        NULL,           NULL,           NULL,           NULL,
16645 /* 5C */        NULL,           NULL,           NULL,           NULL,
16646 /* 60 */        NULL,           NULL,           NULL,           NULL,
16647 /* 64 */        NULL,           NULL,           NULL,           NULL,
16648 /* 68 */        NULL,           NULL,           NULL,           NULL,
16649 /* 6C */        NULL,           NULL,           NULL,           NULL,
16650 /* 70 */        NULL,           NULL,           NULL,           NULL,
16651 /* 74 */        NULL,           NULL,           NULL,           NULL,
16652 /* 78 */        NULL,           NULL,           NULL,           NULL,
16653 /* 7C */        NULL,           NULL,           NULL,           NULL,
16654 /* 80 */        NULL,           NULL,           NULL,           NULL,
16655 /* 84 */        NULL,           NULL,           NULL,           NULL,
16656 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16657 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16658 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16659 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16660 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16661 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16662 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16663 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16664 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16665 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16666 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16667 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16668 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16669 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16670 /* C0 */        NULL,           NULL,           NULL,           NULL,
16671 /* C4 */        NULL,           NULL,           NULL,           NULL,
16672 /* C8 */        NULL,           NULL,           NULL,           NULL,
16673 /* CC */        NULL,           NULL,           NULL,           NULL,
16674 /* D0 */        NULL,           NULL,           NULL,           NULL,
16675 /* D4 */        NULL,           NULL,           NULL,           NULL,
16676 /* D8 */        NULL,           NULL,           NULL,           NULL,
16677 /* DC */        NULL,           NULL,           NULL,           NULL,
16678 /* E0 */        NULL,           NULL,           NULL,           NULL,
16679 /* E4 */        NULL,           NULL,           NULL,           NULL,
16680 /* E8 */        NULL,           NULL,           NULL,           NULL,
16681 /* EC */        NULL,           NULL,           NULL,           NULL,
16682 /* F0 */        NULL,           NULL,           NULL,           NULL,
16683 /* F4 */        NULL,           NULL,           NULL,           NULL,
16684 /* F8 */        NULL,           NULL,           NULL,           NULL,
16685 /* FC */        NULL,           NULL,           NULL,           NULL,
16686 };
16687
16688 static void
16689 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16690 {
16691   const char *mnemonic;
16692
16693   FETCH_DATA (the_info, codep + 1);
16694   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16695      place where an 8-bit immediate would normally go.  ie. the last
16696      byte of the instruction.  */
16697   obufp = mnemonicendp;
16698   mnemonic = Suffix3DNow[*codep++ & 0xff];
16699   if (mnemonic)
16700     oappend (mnemonic);
16701   else
16702     {
16703       /* Since a variable sized modrm/sib chunk is between the start
16704          of the opcode (0x0f0f) and the opcode suffix, we need to do
16705          all the modrm processing first, and don't know until now that
16706          we have a bad opcode.  This necessitates some cleaning up.  */
16707       op_out[0][0] = '\0';
16708       op_out[1][0] = '\0';
16709       BadOp ();
16710     }
16711   mnemonicendp = obufp;
16712 }
16713
16714 static struct op simd_cmp_op[] =
16715 {
16716   { STRING_COMMA_LEN ("eq") },
16717   { STRING_COMMA_LEN ("lt") },
16718   { STRING_COMMA_LEN ("le") },
16719   { STRING_COMMA_LEN ("unord") },
16720   { STRING_COMMA_LEN ("neq") },
16721   { STRING_COMMA_LEN ("nlt") },
16722   { STRING_COMMA_LEN ("nle") },
16723   { STRING_COMMA_LEN ("ord") }
16724 };
16725
16726 static void
16727 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16728 {
16729   unsigned int cmp_type;
16730
16731   FETCH_DATA (the_info, codep + 1);
16732   cmp_type = *codep++ & 0xff;
16733   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16734     {
16735       char suffix [3];
16736       char *p = mnemonicendp - 2;
16737       suffix[0] = p[0];
16738       suffix[1] = p[1];
16739       suffix[2] = '\0';
16740       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16741       mnemonicendp += simd_cmp_op[cmp_type].len;
16742     }
16743   else
16744     {
16745       /* We have a reserved extension byte.  Output it directly.  */
16746       scratchbuf[0] = '$';
16747       print_operand_value (scratchbuf + 1, 1, cmp_type);
16748       oappend_maybe_intel (scratchbuf);
16749       scratchbuf[0] = '\0';
16750     }
16751 }
16752
16753 static void
16754 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16755           int sizeflag ATTRIBUTE_UNUSED)
16756 {
16757   /* mwaitx %eax,%ecx,%ebx */
16758   if (!intel_syntax)
16759     {
16760       const char **names = (address_mode == mode_64bit
16761                             ? names64 : names32);
16762       strcpy (op_out[0], names[0]);
16763       strcpy (op_out[1], names[1]);
16764       strcpy (op_out[2], names[3]);
16765       two_source_ops = 1;
16766     }
16767   /* Skip mod/rm byte.  */
16768   MODRM_CHECK;
16769   codep++;
16770 }
16771
16772 static void
16773 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16774           int sizeflag ATTRIBUTE_UNUSED)
16775 {
16776   /* mwait %eax,%ecx  */
16777   if (!intel_syntax)
16778     {
16779       const char **names = (address_mode == mode_64bit
16780                             ? names64 : names32);
16781       strcpy (op_out[0], names[0]);
16782       strcpy (op_out[1], names[1]);
16783       two_source_ops = 1;
16784     }
16785   /* Skip mod/rm byte.  */
16786   MODRM_CHECK;
16787   codep++;
16788 }
16789
16790 static void
16791 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16792             int sizeflag ATTRIBUTE_UNUSED)
16793 {
16794   /* monitor %eax,%ecx,%edx"  */
16795   if (!intel_syntax)
16796     {
16797       const char **op1_names;
16798       const char **names = (address_mode == mode_64bit
16799                             ? names64 : names32);
16800
16801       if (!(prefixes & PREFIX_ADDR))
16802         op1_names = (address_mode == mode_16bit
16803                      ? names16 : names);
16804       else
16805         {
16806           /* Remove "addr16/addr32".  */
16807           all_prefixes[last_addr_prefix] = 0;
16808           op1_names = (address_mode != mode_32bit
16809                        ? names32 : names16);
16810           used_prefixes |= PREFIX_ADDR;
16811         }
16812       strcpy (op_out[0], op1_names[0]);
16813       strcpy (op_out[1], names[1]);
16814       strcpy (op_out[2], names[2]);
16815       two_source_ops = 1;
16816     }
16817   /* Skip mod/rm byte.  */
16818   MODRM_CHECK;
16819   codep++;
16820 }
16821
16822 static void
16823 BadOp (void)
16824 {
16825   /* Throw away prefixes and 1st. opcode byte.  */
16826   codep = insn_codep + 1;
16827   oappend ("(bad)");
16828 }
16829
16830 static void
16831 REP_Fixup (int bytemode, int sizeflag)
16832 {
16833   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16834      lods and stos.  */
16835   if (prefixes & PREFIX_REPZ)
16836     all_prefixes[last_repz_prefix] = REP_PREFIX;
16837
16838   switch (bytemode)
16839     {
16840     case al_reg:
16841     case eAX_reg:
16842     case indir_dx_reg:
16843       OP_IMREG (bytemode, sizeflag);
16844       break;
16845     case eDI_reg:
16846       OP_ESreg (bytemode, sizeflag);
16847       break;
16848     case eSI_reg:
16849       OP_DSreg (bytemode, sizeflag);
16850       break;
16851     default:
16852       abort ();
16853       break;
16854     }
16855 }
16856
16857 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16858    "bnd".  */
16859
16860 static void
16861 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16862 {
16863   if (prefixes & PREFIX_REPNZ)
16864     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16865 }
16866
16867 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16868    "notrack".  */
16869
16870 static void
16871 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16872                int sizeflag ATTRIBUTE_UNUSED)
16873 {
16874   if (active_seg_prefix == PREFIX_DS
16875       && (address_mode != mode_64bit || last_data_prefix < 0))
16876     {
16877       /* NOTRACK prefix is only valid on indirect branch instructions.
16878          NB: DATA prefix is unsupported for Intel64.  */
16879       active_seg_prefix = 0;
16880       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16881     }
16882 }
16883
16884 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16885    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16886  */
16887
16888 static void
16889 HLE_Fixup1 (int bytemode, int sizeflag)
16890 {
16891   if (modrm.mod != 3
16892       && (prefixes & PREFIX_LOCK) != 0)
16893     {
16894       if (prefixes & PREFIX_REPZ)
16895         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16896       if (prefixes & PREFIX_REPNZ)
16897         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16898     }
16899
16900   OP_E (bytemode, sizeflag);
16901 }
16902
16903 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16904    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16905  */
16906
16907 static void
16908 HLE_Fixup2 (int bytemode, int sizeflag)
16909 {
16910   if (modrm.mod != 3)
16911     {
16912       if (prefixes & PREFIX_REPZ)
16913         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16914       if (prefixes & PREFIX_REPNZ)
16915         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16916     }
16917
16918   OP_E (bytemode, sizeflag);
16919 }
16920
16921 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16922    "xrelease" for memory operand.  No check for LOCK prefix.   */
16923
16924 static void
16925 HLE_Fixup3 (int bytemode, int sizeflag)
16926 {
16927   if (modrm.mod != 3
16928       && last_repz_prefix > last_repnz_prefix
16929       && (prefixes & PREFIX_REPZ) != 0)
16930     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16931
16932   OP_E (bytemode, sizeflag);
16933 }
16934
16935 static void
16936 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16937 {
16938   USED_REX (REX_W);
16939   if (rex & REX_W)
16940     {
16941       /* Change cmpxchg8b to cmpxchg16b.  */
16942       char *p = mnemonicendp - 2;
16943       mnemonicendp = stpcpy (p, "16b");
16944       bytemode = o_mode;
16945     }
16946   else if ((prefixes & PREFIX_LOCK) != 0)
16947     {
16948       if (prefixes & PREFIX_REPZ)
16949         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16950       if (prefixes & PREFIX_REPNZ)
16951         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16952     }
16953
16954   OP_M (bytemode, sizeflag);
16955 }
16956
16957 static void
16958 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16959 {
16960   const char **names;
16961
16962   if (need_vex)
16963     {
16964       switch (vex.length)
16965         {
16966         case 128:
16967           names = names_xmm;
16968           break;
16969         case 256:
16970           names = names_ymm;
16971           break;
16972         default:
16973           abort ();
16974         }
16975     }
16976   else
16977     names = names_xmm;
16978   oappend (names[reg]);
16979 }
16980
16981 static void
16982 CRC32_Fixup (int bytemode, int sizeflag)
16983 {
16984   /* Add proper suffix to "crc32".  */
16985   char *p = mnemonicendp;
16986
16987   switch (bytemode)
16988     {
16989     case b_mode:
16990       if (intel_syntax)
16991         goto skip;
16992
16993       *p++ = 'b';
16994       break;
16995     case v_mode:
16996       if (intel_syntax)
16997         goto skip;
16998
16999       USED_REX (REX_W);
17000       if (rex & REX_W)
17001         *p++ = 'q';
17002       else
17003         {
17004           if (sizeflag & DFLAG)
17005             *p++ = 'l';
17006           else
17007             *p++ = 'w';
17008           used_prefixes |= (prefixes & PREFIX_DATA);
17009         }
17010       break;
17011     default:
17012       oappend (INTERNAL_DISASSEMBLER_ERROR);
17013       break;
17014     }
17015   mnemonicendp = p;
17016   *p = '\0';
17017
17018 skip:
17019   if (modrm.mod == 3)
17020     {
17021       int add;
17022
17023       /* Skip mod/rm byte.  */
17024       MODRM_CHECK;
17025       codep++;
17026
17027       USED_REX (REX_B);
17028       add = (rex & REX_B) ? 8 : 0;
17029       if (bytemode == b_mode)
17030         {
17031           USED_REX (0);
17032           if (rex)
17033             oappend (names8rex[modrm.rm + add]);
17034           else
17035             oappend (names8[modrm.rm + add]);
17036         }
17037       else
17038         {
17039           USED_REX (REX_W);
17040           if (rex & REX_W)
17041             oappend (names64[modrm.rm + add]);
17042           else if ((prefixes & PREFIX_DATA))
17043             oappend (names16[modrm.rm + add]);
17044           else
17045             oappend (names32[modrm.rm + add]);
17046         }
17047     }
17048   else
17049     OP_E (bytemode, sizeflag);
17050 }
17051
17052 static void
17053 FXSAVE_Fixup (int bytemode, int sizeflag)
17054 {
17055   /* Add proper suffix to "fxsave" and "fxrstor".  */
17056   USED_REX (REX_W);
17057   if (rex & REX_W)
17058     {
17059       char *p = mnemonicendp;
17060       *p++ = '6';
17061       *p++ = '4';
17062       *p = '\0';
17063       mnemonicendp = p;
17064     }
17065   OP_M (bytemode, sizeflag);
17066 }
17067
17068 static void
17069 PCMPESTR_Fixup (int bytemode, int sizeflag)
17070 {
17071   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17072   if (!intel_syntax)
17073     {
17074       char *p = mnemonicendp;
17075
17076       USED_REX (REX_W);
17077       if (rex & REX_W)
17078         *p++ = 'q';
17079       else if (sizeflag & SUFFIX_ALWAYS)
17080         *p++ = 'l';
17081
17082       *p = '\0';
17083       mnemonicendp = p;
17084     }
17085
17086   OP_EX (bytemode, sizeflag);
17087 }
17088
17089 /* Display the destination register operand for instructions with
17090    VEX. */
17091
17092 static void
17093 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17094 {
17095   int reg;
17096   const char **names;
17097
17098   if (!need_vex)
17099     abort ();
17100
17101   if (!need_vex_reg)
17102     return;
17103
17104   reg = vex.register_specifier;
17105   if (address_mode != mode_64bit)
17106     reg &= 7;
17107   else if (vex.evex && !vex.v)
17108     reg += 16;
17109
17110   if (bytemode == vex_scalar_mode)
17111     {
17112       oappend (names_xmm[reg]);
17113       return;
17114     }
17115
17116   switch (vex.length)
17117     {
17118     case 128:
17119       switch (bytemode)
17120         {
17121         case vex_mode:
17122         case vex128_mode:
17123         case vex_vsib_q_w_dq_mode:
17124         case vex_vsib_q_w_d_mode:
17125           names = names_xmm;
17126           break;
17127         case dq_mode:
17128           if (rex & REX_W)
17129             names = names64;
17130           else
17131             names = names32;
17132           break;
17133         case mask_bd_mode:
17134         case mask_mode:
17135           if (reg > 0x7)
17136             {
17137               oappend ("(bad)");
17138               return;
17139             }
17140           names = names_mask;
17141           break;
17142         default:
17143           abort ();
17144           return;
17145         }
17146       break;
17147     case 256:
17148       switch (bytemode)
17149         {
17150         case vex_mode:
17151         case vex256_mode:
17152           names = names_ymm;
17153           break;
17154         case vex_vsib_q_w_dq_mode:
17155         case vex_vsib_q_w_d_mode:
17156           names = vex.w ? names_ymm : names_xmm;
17157           break;
17158         case mask_bd_mode:
17159         case mask_mode:
17160           if (reg > 0x7)
17161             {
17162               oappend ("(bad)");
17163               return;
17164             }
17165           names = names_mask;
17166           break;
17167         default:
17168           /* See PR binutils/20893 for a reproducer.  */
17169           oappend ("(bad)");
17170           return;
17171         }
17172       break;
17173     case 512:
17174       names = names_zmm;
17175       break;
17176     default:
17177       abort ();
17178       break;
17179     }
17180   oappend (names[reg]);
17181 }
17182
17183 /* Get the VEX immediate byte without moving codep.  */
17184
17185 static unsigned char
17186 get_vex_imm8 (int sizeflag, int opnum)
17187 {
17188   int bytes_before_imm = 0;
17189
17190   if (modrm.mod != 3)
17191     {
17192       /* There are SIB/displacement bytes.  */
17193       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17194         {
17195           /* 32/64 bit address mode */
17196           int base = modrm.rm;
17197
17198           /* Check SIB byte.  */
17199           if (base == 4)
17200             {
17201               FETCH_DATA (the_info, codep + 1);
17202               base = *codep & 7;
17203               /* When decoding the third source, don't increase
17204                  bytes_before_imm as this has already been incremented
17205                  by one in OP_E_memory while decoding the second
17206                  source operand.  */
17207               if (opnum == 0)
17208                 bytes_before_imm++;
17209             }
17210
17211           /* Don't increase bytes_before_imm when decoding the third source,
17212              it has already been incremented by OP_E_memory while decoding
17213              the second source operand.  */
17214           if (opnum == 0)
17215             {
17216               switch (modrm.mod)
17217                 {
17218                   case 0:
17219                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17220                        SIB == 5, there is a 4 byte displacement.  */
17221                     if (base != 5)
17222                       /* No displacement. */
17223                       break;
17224                     /* Fall through.  */
17225                   case 2:
17226                     /* 4 byte displacement.  */
17227                     bytes_before_imm += 4;
17228                     break;
17229                   case 1:
17230                     /* 1 byte displacement.  */
17231                     bytes_before_imm++;
17232                     break;
17233                 }
17234             }
17235         }
17236       else
17237         {
17238           /* 16 bit address mode */
17239           /* Don't increase bytes_before_imm when decoding the third source,
17240              it has already been incremented by OP_E_memory while decoding
17241              the second source operand.  */
17242           if (opnum == 0)
17243             {
17244               switch (modrm.mod)
17245                 {
17246                 case 0:
17247                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17248                   if (modrm.rm != 6)
17249                     /* No displacement. */
17250                     break;
17251                   /* Fall through.  */
17252                 case 2:
17253                   /* 2 byte displacement.  */
17254                   bytes_before_imm += 2;
17255                   break;
17256                 case 1:
17257                   /* 1 byte displacement: when decoding the third source,
17258                      don't increase bytes_before_imm as this has already
17259                      been incremented by one in OP_E_memory while decoding
17260                      the second source operand.  */
17261                   if (opnum == 0)
17262                     bytes_before_imm++;
17263
17264                   break;
17265                 }
17266             }
17267         }
17268     }
17269
17270   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17271   return codep [bytes_before_imm];
17272 }
17273
17274 static void
17275 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17276 {
17277   const char **names;
17278
17279   if (reg == -1 && modrm.mod != 3)
17280     {
17281       OP_E_memory (bytemode, sizeflag);
17282       return;
17283     }
17284   else
17285     {
17286       if (reg == -1)
17287         {
17288           reg = modrm.rm;
17289           USED_REX (REX_B);
17290           if (rex & REX_B)
17291             reg += 8;
17292         }
17293       if (address_mode != mode_64bit)
17294         reg &= 7;
17295     }
17296
17297   switch (vex.length)
17298     {
17299     case 128:
17300       names = names_xmm;
17301       break;
17302     case 256:
17303       names = names_ymm;
17304       break;
17305     default:
17306       abort ();
17307     }
17308   oappend (names[reg]);
17309 }
17310
17311 static void
17312 OP_EX_VexImmW (int bytemode, int sizeflag)
17313 {
17314   int reg = -1;
17315   static unsigned char vex_imm8;
17316
17317   if (vex_w_done == 0)
17318     {
17319       vex_w_done = 1;
17320
17321       /* Skip mod/rm byte.  */
17322       MODRM_CHECK;
17323       codep++;
17324
17325       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17326
17327       if (vex.w)
17328           reg = vex_imm8 >> 4;
17329
17330       OP_EX_VexReg (bytemode, sizeflag, reg);
17331     }
17332   else if (vex_w_done == 1)
17333     {
17334       vex_w_done = 2;
17335
17336       if (!vex.w)
17337           reg = vex_imm8 >> 4;
17338
17339       OP_EX_VexReg (bytemode, sizeflag, reg);
17340     }
17341   else
17342     {
17343       /* Output the imm8 directly.  */
17344       scratchbuf[0] = '$';
17345       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17346       oappend_maybe_intel (scratchbuf);
17347       scratchbuf[0] = '\0';
17348       codep++;
17349     }
17350 }
17351
17352 static void
17353 OP_Vex_2src (int bytemode, int sizeflag)
17354 {
17355   if (modrm.mod == 3)
17356     {
17357       int reg = modrm.rm;
17358       USED_REX (REX_B);
17359       if (rex & REX_B)
17360         reg += 8;
17361       oappend (names_xmm[reg]);
17362     }
17363   else
17364     {
17365       if (intel_syntax
17366           && (bytemode == v_mode || bytemode == v_swap_mode))
17367         {
17368           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17369           used_prefixes |= (prefixes & PREFIX_DATA);
17370         }
17371       OP_E (bytemode, sizeflag);
17372     }
17373 }
17374
17375 static void
17376 OP_Vex_2src_1 (int bytemode, int sizeflag)
17377 {
17378   if (modrm.mod == 3)
17379     {
17380       /* Skip mod/rm byte.   */
17381       MODRM_CHECK;
17382       codep++;
17383     }
17384
17385   if (vex.w)
17386     {
17387       unsigned int reg = vex.register_specifier;
17388
17389       if (address_mode != mode_64bit)
17390         reg &= 7;
17391       oappend (names_xmm[reg]);
17392     }
17393   else
17394     OP_Vex_2src (bytemode, sizeflag);
17395 }
17396
17397 static void
17398 OP_Vex_2src_2 (int bytemode, int sizeflag)
17399 {
17400   if (vex.w)
17401     OP_Vex_2src (bytemode, sizeflag);
17402   else
17403     {
17404       unsigned int reg = vex.register_specifier;
17405
17406       if (address_mode != mode_64bit)
17407         reg &= 7;
17408       oappend (names_xmm[reg]);
17409     }
17410 }
17411
17412 static void
17413 OP_EX_VexW (int bytemode, int sizeflag)
17414 {
17415   int reg = -1;
17416
17417   if (!vex_w_done)
17418     {
17419       /* Skip mod/rm byte.  */
17420       MODRM_CHECK;
17421       codep++;
17422
17423       if (vex.w)
17424         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17425     }
17426   else
17427     {
17428       if (!vex.w)
17429         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17430     }
17431
17432   OP_EX_VexReg (bytemode, sizeflag, reg);
17433
17434   if (vex_w_done)
17435     codep++;
17436   vex_w_done = 1;
17437 }
17438
17439 static void
17440 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17441 {
17442   int reg;
17443   const char **names;
17444
17445   FETCH_DATA (the_info, codep + 1);
17446   reg = *codep++;
17447
17448   if (bytemode != x_mode)
17449     abort ();
17450
17451   reg >>= 4;
17452   if (address_mode != mode_64bit)
17453     reg &= 7;
17454
17455   switch (vex.length)
17456     {
17457     case 128:
17458       names = names_xmm;
17459       break;
17460     case 256:
17461       names = names_ymm;
17462       break;
17463     default:
17464       abort ();
17465     }
17466   oappend (names[reg]);
17467 }
17468
17469 static void
17470 OP_XMM_VexW (int bytemode, int sizeflag)
17471 {
17472   /* Turn off the REX.W bit since it is used for swapping operands
17473      now.  */
17474   rex &= ~REX_W;
17475   OP_XMM (bytemode, sizeflag);
17476 }
17477
17478 static void
17479 OP_EX_Vex (int bytemode, int sizeflag)
17480 {
17481   if (modrm.mod != 3)
17482     {
17483       if (vex.register_specifier != 0)
17484         BadOp ();
17485       need_vex_reg = 0;
17486     }
17487   OP_EX (bytemode, sizeflag);
17488 }
17489
17490 static void
17491 OP_XMM_Vex (int bytemode, int sizeflag)
17492 {
17493   if (modrm.mod != 3)
17494     {
17495       if (vex.register_specifier != 0)
17496         BadOp ();
17497       need_vex_reg = 0;
17498     }
17499   OP_XMM (bytemode, sizeflag);
17500 }
17501
17502 static void
17503 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17504 {
17505   switch (vex.length)
17506     {
17507     case 128:
17508       mnemonicendp = stpcpy (obuf, "vzeroupper");
17509       break;
17510     case 256:
17511       mnemonicendp = stpcpy (obuf, "vzeroall");
17512       break;
17513     default:
17514       abort ();
17515     }
17516 }
17517
17518 static struct op vex_cmp_op[] =
17519 {
17520   { STRING_COMMA_LEN ("eq") },
17521   { STRING_COMMA_LEN ("lt") },
17522   { STRING_COMMA_LEN ("le") },
17523   { STRING_COMMA_LEN ("unord") },
17524   { STRING_COMMA_LEN ("neq") },
17525   { STRING_COMMA_LEN ("nlt") },
17526   { STRING_COMMA_LEN ("nle") },
17527   { STRING_COMMA_LEN ("ord") },
17528   { STRING_COMMA_LEN ("eq_uq") },
17529   { STRING_COMMA_LEN ("nge") },
17530   { STRING_COMMA_LEN ("ngt") },
17531   { STRING_COMMA_LEN ("false") },
17532   { STRING_COMMA_LEN ("neq_oq") },
17533   { STRING_COMMA_LEN ("ge") },
17534   { STRING_COMMA_LEN ("gt") },
17535   { STRING_COMMA_LEN ("true") },
17536   { STRING_COMMA_LEN ("eq_os") },
17537   { STRING_COMMA_LEN ("lt_oq") },
17538   { STRING_COMMA_LEN ("le_oq") },
17539   { STRING_COMMA_LEN ("unord_s") },
17540   { STRING_COMMA_LEN ("neq_us") },
17541   { STRING_COMMA_LEN ("nlt_uq") },
17542   { STRING_COMMA_LEN ("nle_uq") },
17543   { STRING_COMMA_LEN ("ord_s") },
17544   { STRING_COMMA_LEN ("eq_us") },
17545   { STRING_COMMA_LEN ("nge_uq") },
17546   { STRING_COMMA_LEN ("ngt_uq") },
17547   { STRING_COMMA_LEN ("false_os") },
17548   { STRING_COMMA_LEN ("neq_os") },
17549   { STRING_COMMA_LEN ("ge_oq") },
17550   { STRING_COMMA_LEN ("gt_oq") },
17551   { STRING_COMMA_LEN ("true_us") },
17552 };
17553
17554 static void
17555 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17556 {
17557   unsigned int cmp_type;
17558
17559   FETCH_DATA (the_info, codep + 1);
17560   cmp_type = *codep++ & 0xff;
17561   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17562     {
17563       char suffix [3];
17564       char *p = mnemonicendp - 2;
17565       suffix[0] = p[0];
17566       suffix[1] = p[1];
17567       suffix[2] = '\0';
17568       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17569       mnemonicendp += vex_cmp_op[cmp_type].len;
17570     }
17571   else
17572     {
17573       /* We have a reserved extension byte.  Output it directly.  */
17574       scratchbuf[0] = '$';
17575       print_operand_value (scratchbuf + 1, 1, cmp_type);
17576       oappend_maybe_intel (scratchbuf);
17577       scratchbuf[0] = '\0';
17578     }
17579 }
17580
17581 static void
17582 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17583              int sizeflag ATTRIBUTE_UNUSED)
17584 {
17585   unsigned int cmp_type;
17586
17587   if (!vex.evex)
17588     abort ();
17589
17590   FETCH_DATA (the_info, codep + 1);
17591   cmp_type = *codep++ & 0xff;
17592   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17593      If it's the case, print suffix, otherwise - print the immediate.  */
17594   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17595       && cmp_type != 3
17596       && cmp_type != 7)
17597     {
17598       char suffix [3];
17599       char *p = mnemonicendp - 2;
17600
17601       /* vpcmp* can have both one- and two-lettered suffix.  */
17602       if (p[0] == 'p')
17603         {
17604           p++;
17605           suffix[0] = p[0];
17606           suffix[1] = '\0';
17607         }
17608       else
17609         {
17610           suffix[0] = p[0];
17611           suffix[1] = p[1];
17612           suffix[2] = '\0';
17613         }
17614
17615       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17616       mnemonicendp += simd_cmp_op[cmp_type].len;
17617     }
17618   else
17619     {
17620       /* We have a reserved extension byte.  Output it directly.  */
17621       scratchbuf[0] = '$';
17622       print_operand_value (scratchbuf + 1, 1, cmp_type);
17623       oappend_maybe_intel (scratchbuf);
17624       scratchbuf[0] = '\0';
17625     }
17626 }
17627
17628 static const struct op xop_cmp_op[] =
17629 {
17630   { STRING_COMMA_LEN ("lt") },
17631   { STRING_COMMA_LEN ("le") },
17632   { STRING_COMMA_LEN ("gt") },
17633   { STRING_COMMA_LEN ("ge") },
17634   { STRING_COMMA_LEN ("eq") },
17635   { STRING_COMMA_LEN ("neq") },
17636   { STRING_COMMA_LEN ("false") },
17637   { STRING_COMMA_LEN ("true") }
17638 };
17639
17640 static void
17641 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17642              int sizeflag ATTRIBUTE_UNUSED)
17643 {
17644   unsigned int cmp_type;
17645
17646   FETCH_DATA (the_info, codep + 1);
17647   cmp_type = *codep++ & 0xff;
17648   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17649     {
17650       char suffix[3];
17651       char *p = mnemonicendp - 2;
17652
17653       /* vpcom* can have both one- and two-lettered suffix.  */
17654       if (p[0] == 'm')
17655         {
17656           p++;
17657           suffix[0] = p[0];
17658           suffix[1] = '\0';
17659         }
17660       else
17661         {
17662           suffix[0] = p[0];
17663           suffix[1] = p[1];
17664           suffix[2] = '\0';
17665         }
17666
17667       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17668       mnemonicendp += xop_cmp_op[cmp_type].len;
17669     }
17670   else
17671     {
17672       /* We have a reserved extension byte.  Output it directly.  */
17673       scratchbuf[0] = '$';
17674       print_operand_value (scratchbuf + 1, 1, cmp_type);
17675       oappend_maybe_intel (scratchbuf);
17676       scratchbuf[0] = '\0';
17677     }
17678 }
17679
17680 static const struct op pclmul_op[] =
17681 {
17682   { STRING_COMMA_LEN ("lql") },
17683   { STRING_COMMA_LEN ("hql") },
17684   { STRING_COMMA_LEN ("lqh") },
17685   { STRING_COMMA_LEN ("hqh") }
17686 };
17687
17688 static void
17689 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17690               int sizeflag ATTRIBUTE_UNUSED)
17691 {
17692   unsigned int pclmul_type;
17693
17694   FETCH_DATA (the_info, codep + 1);
17695   pclmul_type = *codep++ & 0xff;
17696   switch (pclmul_type)
17697     {
17698     case 0x10:
17699       pclmul_type = 2;
17700       break;
17701     case 0x11:
17702       pclmul_type = 3;
17703       break;
17704     default:
17705       break;
17706     }
17707   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17708     {
17709       char suffix [4];
17710       char *p = mnemonicendp - 3;
17711       suffix[0] = p[0];
17712       suffix[1] = p[1];
17713       suffix[2] = p[2];
17714       suffix[3] = '\0';
17715       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17716       mnemonicendp += pclmul_op[pclmul_type].len;
17717     }
17718   else
17719     {
17720       /* We have a reserved extension byte.  Output it directly.  */
17721       scratchbuf[0] = '$';
17722       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17723       oappend_maybe_intel (scratchbuf);
17724       scratchbuf[0] = '\0';
17725     }
17726 }
17727
17728 static void
17729 MOVBE_Fixup (int bytemode, int sizeflag)
17730 {
17731   /* Add proper suffix to "movbe".  */
17732   char *p = mnemonicendp;
17733
17734   switch (bytemode)
17735     {
17736     case v_mode:
17737       if (intel_syntax)
17738         goto skip;
17739
17740       USED_REX (REX_W);
17741       if (sizeflag & SUFFIX_ALWAYS)
17742         {
17743           if (rex & REX_W)
17744             *p++ = 'q';
17745           else
17746             {
17747               if (sizeflag & DFLAG)
17748                 *p++ = 'l';
17749               else
17750                 *p++ = 'w';
17751               used_prefixes |= (prefixes & PREFIX_DATA);
17752             }
17753         }
17754       break;
17755     default:
17756       oappend (INTERNAL_DISASSEMBLER_ERROR);
17757       break;
17758     }
17759   mnemonicendp = p;
17760   *p = '\0';
17761
17762 skip:
17763   OP_M (bytemode, sizeflag);
17764 }
17765
17766 static void
17767 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17768 {
17769   int reg;
17770   const char **names;
17771
17772   /* Skip mod/rm byte.  */
17773   MODRM_CHECK;
17774   codep++;
17775
17776   if (rex & REX_W)
17777     names = names64;
17778   else
17779     names = names32;
17780
17781   reg = modrm.rm;
17782   USED_REX (REX_B);
17783   if (rex & REX_B)
17784     reg += 8;
17785
17786   oappend (names[reg]);
17787 }
17788
17789 static void
17790 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17791 {
17792   const char **names;
17793   unsigned int reg = vex.register_specifier;
17794
17795   if (rex & REX_W)
17796     names = names64;
17797   else
17798     names = names32;
17799
17800   if (address_mode != mode_64bit)
17801     reg &= 7;
17802   oappend (names[reg]);
17803 }
17804
17805 static void
17806 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17807 {
17808   if (!vex.evex
17809       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17810     abort ();
17811
17812   USED_REX (REX_R);
17813   if ((rex & REX_R) != 0 || !vex.r)
17814     {
17815       BadOp ();
17816       return;
17817     }
17818
17819   oappend (names_mask [modrm.reg]);
17820 }
17821
17822 static void
17823 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17824 {
17825   if (!vex.evex
17826       || (bytemode != evex_rounding_mode
17827           && bytemode != evex_sae_mode))
17828     abort ();
17829   if (modrm.mod == 3 && vex.b)
17830     switch (bytemode)
17831       {
17832       case evex_rounding_mode:
17833         oappend (names_rounding[vex.ll]);
17834         break;
17835       case evex_sae_mode:
17836         oappend ("{sae}");
17837         break;
17838       default:
17839         break;
17840       }
17841 }