opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115 static void OP_LWPCB_E (int, int);
 116 static void OP_LWP_E (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define Iq { OP_I, q_mode }
 257 #define Iv64 { OP_I64, v_mode }
 258 #define Iw { OP_I, w_mode }
 259 #define I1 { OP_I, const_1_mode }
 260 #define Jb { OP_J, b_mode }
 261 #define Jv { OP_J, v_mode }
 262 #define Cm { OP_C, m_mode }
 263 #define Dm { OP_D, m_mode }
 264 #define Td { OP_T, d_mode }
 265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 266
 267 #define RMeAX { OP_REG, eAX_reg }
 268 #define RMeBX { OP_REG, eBX_reg }
 269 #define RMeCX { OP_REG, eCX_reg }
 270 #define RMeDX { OP_REG, eDX_reg }
 271 #define RMeSP { OP_REG, eSP_reg }
 272 #define RMeBP { OP_REG, eBP_reg }
 273 #define RMeSI { OP_REG, eSI_reg }
 274 #define RMeDI { OP_REG, eDI_reg }
 275 #define RMrAX { OP_REG, rAX_reg }
 276 #define RMrBX { OP_REG, rBX_reg }
 277 #define RMrCX { OP_REG, rCX_reg }
 278 #define RMrDX { OP_REG, rDX_reg }
 279 #define RMrSP { OP_REG, rSP_reg }
 280 #define RMrBP { OP_REG, rBP_reg }
 281 #define RMrSI { OP_REG, rSI_reg }
 282 #define RMrDI { OP_REG, rDI_reg }
 283 #define RMAL { OP_REG, al_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMScalar { OP_XMM, scalar_mode }
 338 #define XMM { OP_XMM, xmm_mode }
 339 #define EM { OP_EM, v_mode }
 340 #define EMS { OP_EM, v_swap_mode }
 341 #define EMd { OP_EM, d_mode }
 342 #define EMx { OP_EM, x_mode }
 343 #define EXw { OP_EX, w_mode }
 344 #define EXd { OP_EX, d_mode }
 345 #define EXdScalar { OP_EX, d_scalar_mode }
 346 #define EXdS { OP_EX, d_swap_mode }
 347 #define EXq { OP_EX, q_mode }
 348 #define EXqScalar { OP_EX, q_scalar_mode }
 349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 350 #define EXqS { OP_EX, q_swap_mode }
 351 #define EXx { OP_EX, x_mode }
 352 #define EXxS { OP_EX, x_swap_mode }
 353 #define EXxmm { OP_EX, xmm_mode }
 354 #define EXxmmq { OP_EX, xmmq_mode }
 355 #define EXymmq { OP_EX, ymmq_mode }
 356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 358 #define MS { OP_MS, v_mode }
 359 #define XS { OP_XS, v_mode }
 360 #define EMCq { OP_EMC, q_mode }
 361 #define MXC { OP_MXC, 0 }
 362 #define OPSUF { OP_3DNowSuffix, 0 }
 363 #define CMP { CMP_Fixup, 0 }
 364 #define XMM0 { XMM_Fixup, 0 }
 365 #define FXSAVE { FXSAVE_Fixup, 0 }
 366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 368
 369 #define Vex { OP_VEX, vex_mode }
 370 #define VexScalar { OP_VEX, vex_scalar_mode }
 371 #define Vex128 { OP_VEX, vex128_mode }
 372 #define Vex256 { OP_VEX, vex256_mode }
 373 #define VexI4 { VEXI4_Fixup, 0}
 374 #define EXdVex { OP_EX_Vex, d_mode }
 375 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 376 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 377 #define EXqVex { OP_EX_Vex, q_mode }
 378 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 379 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 380 #define EXVexW { OP_EX_VexW, x_mode }
 381 #define EXdVexW { OP_EX_VexW, d_mode }
 382 #define EXqVexW { OP_EX_VexW, q_mode }
 383 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 384 #define XMVex { OP_XMM_Vex, 0 }
 385 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 386 #define XMVexW { OP_XMM_VexW, 0 }
 387 #define XMVexI4 { OP_REG_VexI4, x_mode }
 388 #define PCLMUL { PCLMUL_Fixup, 0 }
 389 #define VZERO { VZERO_Fixup, 0 }
 390 #define VCMP { VCMP_Fixup, 0 }
 391
 392 /* Used handle "rep" prefix for string instructions.  */
 393 #define Xbr { REP_Fixup, eSI_reg }
 394 #define Xvr { REP_Fixup, eSI_reg }
 395 #define Ybr { REP_Fixup, eDI_reg }
 396 #define Yvr { REP_Fixup, eDI_reg }
 397 #define Yzr { REP_Fixup, eDI_reg }
 398 #define indirDXr { REP_Fixup, indir_dx_reg }
 399 #define ALr { REP_Fixup, al_reg }
 400 #define eAXr { REP_Fixup, eAX_reg }
 401
 402 #define cond_jump_flag { NULL, cond_jump_mode }
 403 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 404
 405 /* bits in sizeflag */
 406 #define SUFFIX_ALWAYS 4
 407 #define AFLAG 2
 408 #define DFLAG 1
 409
 410 enum
 411 {
 412   /* byte operand */
 413   b_mode = 1,
 414   /* byte operand with operand swapped */
 415   b_swap_mode,
 416   /* operand size depends on prefixes */
 417   v_mode,
 418   /* operand size depends on prefixes with operand swapped */
 419   v_swap_mode,
 420   /* word operand */
 421   w_mode,
 422   /* double word operand  */
 423   d_mode,
 424   /* double word operand with operand swapped */
 425   d_swap_mode,
 426   /* quad word operand */
 427   q_mode,
 428   /* quad word operand with operand swapped */
 429   q_swap_mode,
 430   /* ten-byte operand */
 431   t_mode,
 432   /* 16-byte XMM or 32-byte YMM operand */
 433   x_mode,
 434   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 435   x_swap_mode,
 436   /* 16-byte XMM operand */
 437   xmm_mode,
 438   /* 16-byte XMM or quad word operand */
 439   xmmq_mode,
 440   /* 32-byte YMM or quad word operand */
 441   ymmq_mode,
 442   /* d_mode in 32bit, q_mode in 64bit mode.  */
 443   m_mode,
 444   /* pair of v_mode operands */
 445   a_mode,
 446   cond_jump_mode,
 447   loop_jcxz_mode,
 448   /* operand size depends on REX prefixes.  */
 449   dq_mode,
 450   /* registers like dq_mode, memory like w_mode.  */
 451   dqw_mode,
 452   /* 4- or 6-byte pointer operand */
 453   f_mode,
 454   const_1_mode,
 455   /* v_mode for stack-related opcodes.  */
 456   stack_v_mode,
 457   /* non-quad operand size depends on prefixes */
 458   z_mode,
 459   /* 16-byte operand */
 460   o_mode,
 461   /* registers like dq_mode, memory like b_mode.  */
 462   dqb_mode,
 463   /* registers like dq_mode, memory like d_mode.  */
 464   dqd_mode,
 465   /* normal vex mode */
 466   vex_mode,
 467   /* 128bit vex mode */
 468   vex128_mode,
 469   /* 256bit vex mode */
 470   vex256_mode,
 471   /* operand size depends on the VEX.W bit.  */
 472   vex_w_dq_mode,
 473
 474   /* scalar, ignore vector length.  */
 475   scalar_mode,
 476   /* like d_mode, ignore vector length.  */
 477   d_scalar_mode,
 478   /* like d_swap_mode, ignore vector length.  */
 479   d_scalar_swap_mode,
 480   /* like q_mode, ignore vector length.  */
 481   q_scalar_mode,
 482   /* like q_swap_mode, ignore vector length.  */
 483   q_scalar_swap_mode,
 484   /* like vex_mode, ignore vector length.  */
 485   vex_scalar_mode,
 486   /* like vex_w_dq_mode, ignore vector length.  */
 487   vex_scalar_w_dq_mode,
 488
 489   es_reg,
 490   cs_reg,
 491   ss_reg,
 492   ds_reg,
 493   fs_reg,
 494   gs_reg,
 495
 496   eAX_reg,
 497   eCX_reg,
 498   eDX_reg,
 499   eBX_reg,
 500   eSP_reg,
 501   eBP_reg,
 502   eSI_reg,
 503   eDI_reg,
 504
 505   al_reg,
 506   cl_reg,
 507   dl_reg,
 508   bl_reg,
 509   ah_reg,
 510   ch_reg,
 511   dh_reg,
 512   bh_reg,
 513
 514   ax_reg,
 515   cx_reg,
 516   dx_reg,
 517   bx_reg,
 518   sp_reg,
 519   bp_reg,
 520   si_reg,
 521   di_reg,
 522
 523   rAX_reg,
 524   rCX_reg,
 525   rDX_reg,
 526   rBX_reg,
 527   rSP_reg,
 528   rBP_reg,
 529   rSI_reg,
 530   rDI_reg,
 531
 532   z_mode_ax_reg,
 533   indir_dx_reg
 534 };
 535
 536 enum
 537 {
 538   FLOATCODE = 1,
 539   USE_REG_TABLE,
 540   USE_MOD_TABLE,
 541   USE_RM_TABLE,
 542   USE_PREFIX_TABLE,
 543   USE_X86_64_TABLE,
 544   USE_3BYTE_TABLE,
 545   USE_XOP_8F_TABLE,
 546   USE_VEX_C4_TABLE,
 547   USE_VEX_C5_TABLE,
 548   USE_VEX_LEN_TABLE,
 549   USE_VEX_W_TABLE
 550 };
 551
 552 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 553
 554 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 555 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 556 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 557 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 558 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 559 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 560 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 561 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 562 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 563 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 564 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 565 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 566
 567 enum
 568 {
 569   REG_80 = 0,
 570   REG_81,
 571   REG_82,
 572   REG_8F,
 573   REG_C0,
 574   REG_C1,
 575   REG_C6,
 576   REG_C7,
 577   REG_D0,
 578   REG_D1,
 579   REG_D2,
 580   REG_D3,
 581   REG_F6,
 582   REG_F7,
 583   REG_FE,
 584   REG_FF,
 585   REG_0F00,
 586   REG_0F01,
 587   REG_0F0D,
 588   REG_0F18,
 589   REG_0F71,
 590   REG_0F72,
 591   REG_0F73,
 592   REG_0FA6,
 593   REG_0FA7,
 594   REG_0FAE,
 595   REG_0FBA,
 596   REG_0FC7,
 597   REG_VEX_71,
 598   REG_VEX_72,
 599   REG_VEX_73,
 600   REG_VEX_AE,
 601   REG_XOP_LWPCB,
 602   REG_XOP_LWP
 603 };
 604
 605 enum
 606 {
 607   MOD_8D = 0,
 608   MOD_0F01_REG_0,
 609   MOD_0F01_REG_1,
 610   MOD_0F01_REG_2,
 611   MOD_0F01_REG_3,
 612   MOD_0F01_REG_7,
 613   MOD_0F12_PREFIX_0,
 614   MOD_0F13,
 615   MOD_0F16_PREFIX_0,
 616   MOD_0F17,
 617   MOD_0F18_REG_0,
 618   MOD_0F18_REG_1,
 619   MOD_0F18_REG_2,
 620   MOD_0F18_REG_3,
 621   MOD_0F20,
 622   MOD_0F21,
 623   MOD_0F22,
 624   MOD_0F23,
 625   MOD_0F24,
 626   MOD_0F26,
 627   MOD_0F2B_PREFIX_0,
 628   MOD_0F2B_PREFIX_1,
 629   MOD_0F2B_PREFIX_2,
 630   MOD_0F2B_PREFIX_3,
 631   MOD_0F51,
 632   MOD_0F71_REG_2,
 633   MOD_0F71_REG_4,
 634   MOD_0F71_REG_6,
 635   MOD_0F72_REG_2,
 636   MOD_0F72_REG_4,
 637   MOD_0F72_REG_6,
 638   MOD_0F73_REG_2,
 639   MOD_0F73_REG_3,
 640   MOD_0F73_REG_6,
 641   MOD_0F73_REG_7,
 642   MOD_0FAE_REG_0,
 643   MOD_0FAE_REG_1,
 644   MOD_0FAE_REG_2,
 645   MOD_0FAE_REG_3,
 646   MOD_0FAE_REG_4,
 647   MOD_0FAE_REG_5,
 648   MOD_0FAE_REG_6,
 649   MOD_0FAE_REG_7,
 650   MOD_0FB2,
 651   MOD_0FB4,
 652   MOD_0FB5,
 653   MOD_0FC7_REG_6,
 654   MOD_0FC7_REG_7,
 655   MOD_0FD7,
 656   MOD_0FE7_PREFIX_2,
 657   MOD_0FF0_PREFIX_3,
 658   MOD_0F382A_PREFIX_2,
 659   MOD_62_32BIT,
 660   MOD_C4_32BIT,
 661   MOD_C5_32BIT,
 662   MOD_VEX_12_PREFIX_0,
 663   MOD_VEX_13,
 664   MOD_VEX_16_PREFIX_0,
 665   MOD_VEX_17,
 666   MOD_VEX_2B,
 667   MOD_VEX_50,
 668   MOD_VEX_71_REG_2,
 669   MOD_VEX_71_REG_4,
 670   MOD_VEX_71_REG_6,
 671   MOD_VEX_72_REG_2,
 672   MOD_VEX_72_REG_4,
 673   MOD_VEX_72_REG_6,
 674   MOD_VEX_73_REG_2,
 675   MOD_VEX_73_REG_3,
 676   MOD_VEX_73_REG_6,
 677   MOD_VEX_73_REG_7,
 678   MOD_VEX_AE_REG_2,
 679   MOD_VEX_AE_REG_3,
 680   MOD_VEX_D7_PREFIX_2,
 681   MOD_VEX_E7_PREFIX_2,
 682   MOD_VEX_F0_PREFIX_3,
 683   MOD_VEX_3818_PREFIX_2,
 684   MOD_VEX_3819_PREFIX_2,
 685   MOD_VEX_381A_PREFIX_2,
 686   MOD_VEX_382A_PREFIX_2,
 687   MOD_VEX_382C_PREFIX_2,
 688   MOD_VEX_382D_PREFIX_2,
 689   MOD_VEX_382E_PREFIX_2,
 690   MOD_VEX_382F_PREFIX_2
 691 };
 692
 693 enum
 694 {
 695   RM_0F01_REG_0 = 0,
 696   RM_0F01_REG_1,
 697   RM_0F01_REG_2,
 698   RM_0F01_REG_3,
 699   RM_0F01_REG_7,
 700   RM_0FAE_REG_5,
 701   RM_0FAE_REG_6,
 702   RM_0FAE_REG_7
 703 };
 704
 705 enum
 706 {
 707   PREFIX_90 = 0,
 708   PREFIX_0F10,
 709   PREFIX_0F11,
 710   PREFIX_0F12,
 711   PREFIX_0F16,
 712   PREFIX_0F2A,
 713   PREFIX_0F2B,
 714   PREFIX_0F2C,
 715   PREFIX_0F2D,
 716   PREFIX_0F2E,
 717   PREFIX_0F2F,
 718   PREFIX_0F51,
 719   PREFIX_0F52,
 720   PREFIX_0F53,
 721   PREFIX_0F58,
 722   PREFIX_0F59,
 723   PREFIX_0F5A,
 724   PREFIX_0F5B,
 725   PREFIX_0F5C,
 726   PREFIX_0F5D,
 727   PREFIX_0F5E,
 728   PREFIX_0F5F,
 729   PREFIX_0F60,
 730   PREFIX_0F61,
 731   PREFIX_0F62,
 732   PREFIX_0F6C,
 733   PREFIX_0F6D,
 734   PREFIX_0F6F,
 735   PREFIX_0F70,
 736   PREFIX_0F73_REG_3,
 737   PREFIX_0F73_REG_7,
 738   PREFIX_0F78,
 739   PREFIX_0F79,
 740   PREFIX_0F7C,
 741   PREFIX_0F7D,
 742   PREFIX_0F7E,
 743   PREFIX_0F7F,
 744   PREFIX_0FB8,
 745   PREFIX_0FBD,
 746   PREFIX_0FC2,
 747   PREFIX_0FC3,
 748   PREFIX_0FC7_REG_6,
 749   PREFIX_0FD0,
 750   PREFIX_0FD6,
 751   PREFIX_0FE6,
 752   PREFIX_0FE7,
 753   PREFIX_0FF0,
 754   PREFIX_0FF7,
 755   PREFIX_0F3810,
 756   PREFIX_0F3814,
 757   PREFIX_0F3815,
 758   PREFIX_0F3817,
 759   PREFIX_0F3820,
 760   PREFIX_0F3821,
 761   PREFIX_0F3822,
 762   PREFIX_0F3823,
 763   PREFIX_0F3824,
 764   PREFIX_0F3825,
 765   PREFIX_0F3828,
 766   PREFIX_0F3829,
 767   PREFIX_0F382A,
 768   PREFIX_0F382B,
 769   PREFIX_0F3830,
 770   PREFIX_0F3831,
 771   PREFIX_0F3832,
 772   PREFIX_0F3833,
 773   PREFIX_0F3834,
 774   PREFIX_0F3835,
 775   PREFIX_0F3837,
 776   PREFIX_0F3838,
 777   PREFIX_0F3839,
 778   PREFIX_0F383A,
 779   PREFIX_0F383B,
 780   PREFIX_0F383C,
 781   PREFIX_0F383D,
 782   PREFIX_0F383E,
 783   PREFIX_0F383F,
 784   PREFIX_0F3840,
 785   PREFIX_0F3841,
 786   PREFIX_0F3880,
 787   PREFIX_0F3881,
 788   PREFIX_0F38DB,
 789   PREFIX_0F38DC,
 790   PREFIX_0F38DD,
 791   PREFIX_0F38DE,
 792   PREFIX_0F38DF,
 793   PREFIX_0F38F0,
 794   PREFIX_0F38F1,
 795   PREFIX_0F3A08,
 796   PREFIX_0F3A09,
 797   PREFIX_0F3A0A,
 798   PREFIX_0F3A0B,
 799   PREFIX_0F3A0C,
 800   PREFIX_0F3A0D,
 801   PREFIX_0F3A0E,
 802   PREFIX_0F3A14,
 803   PREFIX_0F3A15,
 804   PREFIX_0F3A16,
 805   PREFIX_0F3A17,
 806   PREFIX_0F3A20,
 807   PREFIX_0F3A21,
 808   PREFIX_0F3A22,
 809   PREFIX_0F3A40,
 810   PREFIX_0F3A41,
 811   PREFIX_0F3A42,
 812   PREFIX_0F3A44,
 813   PREFIX_0F3A60,
 814   PREFIX_0F3A61,
 815   PREFIX_0F3A62,
 816   PREFIX_0F3A63,
 817   PREFIX_0F3ADF,
 818   PREFIX_VEX_10,
 819   PREFIX_VEX_11,
 820   PREFIX_VEX_12,
 821   PREFIX_VEX_16,
 822   PREFIX_VEX_2A,
 823   PREFIX_VEX_2C,
 824   PREFIX_VEX_2D,
 825   PREFIX_VEX_2E,
 826   PREFIX_VEX_2F,
 827   PREFIX_VEX_51,
 828   PREFIX_VEX_52,
 829   PREFIX_VEX_53,
 830   PREFIX_VEX_58,
 831   PREFIX_VEX_59,
 832   PREFIX_VEX_5A,
 833   PREFIX_VEX_5B,
 834   PREFIX_VEX_5C,
 835   PREFIX_VEX_5D,
 836   PREFIX_VEX_5E,
 837   PREFIX_VEX_5F,
 838   PREFIX_VEX_60,
 839   PREFIX_VEX_61,
 840   PREFIX_VEX_62,
 841   PREFIX_VEX_63,
 842   PREFIX_VEX_64,
 843   PREFIX_VEX_65,
 844   PREFIX_VEX_66,
 845   PREFIX_VEX_67,
 846   PREFIX_VEX_68,
 847   PREFIX_VEX_69,
 848   PREFIX_VEX_6A,
 849   PREFIX_VEX_6B,
 850   PREFIX_VEX_6C,
 851   PREFIX_VEX_6D,
 852   PREFIX_VEX_6E,
 853   PREFIX_VEX_6F,
 854   PREFIX_VEX_70,
 855   PREFIX_VEX_71_REG_2,
 856   PREFIX_VEX_71_REG_4,
 857   PREFIX_VEX_71_REG_6,
 858   PREFIX_VEX_72_REG_2,
 859   PREFIX_VEX_72_REG_4,
 860   PREFIX_VEX_72_REG_6,
 861   PREFIX_VEX_73_REG_2,
 862   PREFIX_VEX_73_REG_3,
 863   PREFIX_VEX_73_REG_6,
 864   PREFIX_VEX_73_REG_7,
 865   PREFIX_VEX_74,
 866   PREFIX_VEX_75,
 867   PREFIX_VEX_76,
 868   PREFIX_VEX_77,
 869   PREFIX_VEX_7C,
 870   PREFIX_VEX_7D,
 871   PREFIX_VEX_7E,
 872   PREFIX_VEX_7F,
 873   PREFIX_VEX_C2,
 874   PREFIX_VEX_C4,
 875   PREFIX_VEX_C5,
 876   PREFIX_VEX_D0,
 877   PREFIX_VEX_D1,
 878   PREFIX_VEX_D2,
 879   PREFIX_VEX_D3,
 880   PREFIX_VEX_D4,
 881   PREFIX_VEX_D5,
 882   PREFIX_VEX_D6,
 883   PREFIX_VEX_D7,
 884   PREFIX_VEX_D8,
 885   PREFIX_VEX_D9,
 886   PREFIX_VEX_DA,
 887   PREFIX_VEX_DB,
 888   PREFIX_VEX_DC,
 889   PREFIX_VEX_DD,
 890   PREFIX_VEX_DE,
 891   PREFIX_VEX_DF,
 892   PREFIX_VEX_E0,
 893   PREFIX_VEX_E1,
 894   PREFIX_VEX_E2,
 895   PREFIX_VEX_E3,
 896   PREFIX_VEX_E4,
 897   PREFIX_VEX_E5,
 898   PREFIX_VEX_E6,
 899   PREFIX_VEX_E7,
 900   PREFIX_VEX_E8,
 901   PREFIX_VEX_E9,
 902   PREFIX_VEX_EA,
 903   PREFIX_VEX_EB,
 904   PREFIX_VEX_EC,
 905   PREFIX_VEX_ED,
 906   PREFIX_VEX_EE,
 907   PREFIX_VEX_EF,
 908   PREFIX_VEX_F0,
 909   PREFIX_VEX_F1,
 910   PREFIX_VEX_F2,
 911   PREFIX_VEX_F3,
 912   PREFIX_VEX_F4,
 913   PREFIX_VEX_F5,
 914   PREFIX_VEX_F6,
 915   PREFIX_VEX_F7,
 916   PREFIX_VEX_F8,
 917   PREFIX_VEX_F9,
 918   PREFIX_VEX_FA,
 919   PREFIX_VEX_FB,
 920   PREFIX_VEX_FC,
 921   PREFIX_VEX_FD,
 922   PREFIX_VEX_FE,
 923   PREFIX_VEX_3800,
 924   PREFIX_VEX_3801,
 925   PREFIX_VEX_3802,
 926   PREFIX_VEX_3803,
 927   PREFIX_VEX_3804,
 928   PREFIX_VEX_3805,
 929   PREFIX_VEX_3806,
 930   PREFIX_VEX_3807,
 931   PREFIX_VEX_3808,
 932   PREFIX_VEX_3809,
 933   PREFIX_VEX_380A,
 934   PREFIX_VEX_380B,
 935   PREFIX_VEX_380C,
 936   PREFIX_VEX_380D,
 937   PREFIX_VEX_380E,
 938   PREFIX_VEX_380F,
 939   PREFIX_VEX_3817,
 940   PREFIX_VEX_3818,
 941   PREFIX_VEX_3819,
 942   PREFIX_VEX_381A,
 943   PREFIX_VEX_381C,
 944   PREFIX_VEX_381D,
 945   PREFIX_VEX_381E,
 946   PREFIX_VEX_3820,
 947   PREFIX_VEX_3821,
 948   PREFIX_VEX_3822,
 949   PREFIX_VEX_3823,
 950   PREFIX_VEX_3824,
 951   PREFIX_VEX_3825,
 952   PREFIX_VEX_3828,
 953   PREFIX_VEX_3829,
 954   PREFIX_VEX_382A,
 955   PREFIX_VEX_382B,
 956   PREFIX_VEX_382C,
 957   PREFIX_VEX_382D,
 958   PREFIX_VEX_382E,
 959   PREFIX_VEX_382F,
 960   PREFIX_VEX_3830,
 961   PREFIX_VEX_3831,
 962   PREFIX_VEX_3832,
 963   PREFIX_VEX_3833,
 964   PREFIX_VEX_3834,
 965   PREFIX_VEX_3835,
 966   PREFIX_VEX_3837,
 967   PREFIX_VEX_3838,
 968   PREFIX_VEX_3839,
 969   PREFIX_VEX_383A,
 970   PREFIX_VEX_383B,
 971   PREFIX_VEX_383C,
 972   PREFIX_VEX_383D,
 973   PREFIX_VEX_383E,
 974   PREFIX_VEX_383F,
 975   PREFIX_VEX_3840,
 976   PREFIX_VEX_3841,
 977   PREFIX_VEX_3896,
 978   PREFIX_VEX_3897,
 979   PREFIX_VEX_3898,
 980   PREFIX_VEX_3899,
 981   PREFIX_VEX_389A,
 982   PREFIX_VEX_389B,
 983   PREFIX_VEX_389C,
 984   PREFIX_VEX_389D,
 985   PREFIX_VEX_389E,
 986   PREFIX_VEX_389F,
 987   PREFIX_VEX_38A6,
 988   PREFIX_VEX_38A7,
 989   PREFIX_VEX_38A8,
 990   PREFIX_VEX_38A9,
 991   PREFIX_VEX_38AA,
 992   PREFIX_VEX_38AB,
 993   PREFIX_VEX_38AC,
 994   PREFIX_VEX_38AD,
 995   PREFIX_VEX_38AE,
 996   PREFIX_VEX_38AF,
 997   PREFIX_VEX_38B6,
 998   PREFIX_VEX_38B7,
 999   PREFIX_VEX_38B8,
1000   PREFIX_VEX_38B9,
1001   PREFIX_VEX_38BA,
1002   PREFIX_VEX_38BB,
1003   PREFIX_VEX_38BC,
1004   PREFIX_VEX_38BD,
1005   PREFIX_VEX_38BE,
1006   PREFIX_VEX_38BF,
1007   PREFIX_VEX_38DB,
1008   PREFIX_VEX_38DC,
1009   PREFIX_VEX_38DD,
1010   PREFIX_VEX_38DE,
1011   PREFIX_VEX_38DF,
1012   PREFIX_VEX_3A04,
1013   PREFIX_VEX_3A05,
1014   PREFIX_VEX_3A06,
1015   PREFIX_VEX_3A08,
1016   PREFIX_VEX_3A09,
1017   PREFIX_VEX_3A0A,
1018   PREFIX_VEX_3A0B,
1019   PREFIX_VEX_3A0C,
1020   PREFIX_VEX_3A0D,
1021   PREFIX_VEX_3A0E,
1022   PREFIX_VEX_3A0F,
1023   PREFIX_VEX_3A14,
1024   PREFIX_VEX_3A15,
1025   PREFIX_VEX_3A16,
1026   PREFIX_VEX_3A17,
1027   PREFIX_VEX_3A18,
1028   PREFIX_VEX_3A19,
1029   PREFIX_VEX_3A20,
1030   PREFIX_VEX_3A21,
1031   PREFIX_VEX_3A22,
1032   PREFIX_VEX_3A40,
1033   PREFIX_VEX_3A41,
1034   PREFIX_VEX_3A42,
1035   PREFIX_VEX_3A44,
1036   PREFIX_VEX_3A48,
1037   PREFIX_VEX_3A49,
1038   PREFIX_VEX_3A4A,
1039   PREFIX_VEX_3A4B,
1040   PREFIX_VEX_3A4C,
1041   PREFIX_VEX_3A5C,
1042   PREFIX_VEX_3A5D,
1043   PREFIX_VEX_3A5E,
1044   PREFIX_VEX_3A5F,
1045   PREFIX_VEX_3A60,
1046   PREFIX_VEX_3A61,
1047   PREFIX_VEX_3A62,
1048   PREFIX_VEX_3A63,
1049   PREFIX_VEX_3A68,
1050   PREFIX_VEX_3A69,
1051   PREFIX_VEX_3A6A,
1052   PREFIX_VEX_3A6B,
1053   PREFIX_VEX_3A6C,
1054   PREFIX_VEX_3A6D,
1055   PREFIX_VEX_3A6E,
1056   PREFIX_VEX_3A6F,
1057   PREFIX_VEX_3A78,
1058   PREFIX_VEX_3A79,
1059   PREFIX_VEX_3A7A,
1060   PREFIX_VEX_3A7B,
1061   PREFIX_VEX_3A7C,
1062   PREFIX_VEX_3A7D,
1063   PREFIX_VEX_3A7E,
1064   PREFIX_VEX_3A7F,
1065   PREFIX_VEX_3ADF
1066 };
1067
1068 enum
1069 {
1070   X86_64_06 = 0,
1071   X86_64_07,
1072   X86_64_0D,
1073   X86_64_16,
1074   X86_64_17,
1075   X86_64_1E,
1076   X86_64_1F,
1077   X86_64_27,
1078   X86_64_2F,
1079   X86_64_37,
1080   X86_64_3F,
1081   X86_64_60,
1082   X86_64_61,
1083   X86_64_62,
1084   X86_64_63,
1085   X86_64_6D,
1086   X86_64_6F,
1087   X86_64_9A,
1088   X86_64_C4,
1089   X86_64_C5,
1090   X86_64_CE,
1091   X86_64_D4,
1092   X86_64_D5,
1093   X86_64_EA,
1094   X86_64_0F01_REG_0,
1095   X86_64_0F01_REG_1,
1096   X86_64_0F01_REG_2,
1097   X86_64_0F01_REG_3
1098 };
1099
1100 enum
1101 {
1102   THREE_BYTE_0F38 = 0,
1103   THREE_BYTE_0F3A,
1104   THREE_BYTE_0F7A
1105 };
1106
1107 enum
1108 {
1109   XOP_08 = 0,
1110   XOP_09,
1111   XOP_0A
1112 };
1113
1114 enum
1115 {
1116   VEX_0F = 0,
1117   VEX_0F38,
1118   VEX_0F3A
1119 };
1120
1121 enum
1122 {
1123   VEX_LEN_10_P_1 = 0,
1124   VEX_LEN_10_P_3,
1125   VEX_LEN_11_P_1,
1126   VEX_LEN_11_P_3,
1127   VEX_LEN_12_P_0_M_0,
1128   VEX_LEN_12_P_0_M_1,
1129   VEX_LEN_12_P_2,
1130   VEX_LEN_13_M_0,
1131   VEX_LEN_16_P_0_M_0,
1132   VEX_LEN_16_P_0_M_1,
1133   VEX_LEN_16_P_2,
1134   VEX_LEN_17_M_0,
1135   VEX_LEN_2A_P_1,
1136   VEX_LEN_2A_P_3,
1137   VEX_LEN_2C_P_1,
1138   VEX_LEN_2C_P_3,
1139   VEX_LEN_2D_P_1,
1140   VEX_LEN_2D_P_3,
1141   VEX_LEN_2E_P_0,
1142   VEX_LEN_2E_P_2,
1143   VEX_LEN_2F_P_0,
1144   VEX_LEN_2F_P_2,
1145   VEX_LEN_51_P_1,
1146   VEX_LEN_51_P_3,
1147   VEX_LEN_52_P_1,
1148   VEX_LEN_53_P_1,
1149   VEX_LEN_58_P_1,
1150   VEX_LEN_58_P_3,
1151   VEX_LEN_59_P_1,
1152   VEX_LEN_59_P_3,
1153   VEX_LEN_5A_P_1,
1154   VEX_LEN_5A_P_3,
1155   VEX_LEN_5C_P_1,
1156   VEX_LEN_5C_P_3,
1157   VEX_LEN_5D_P_1,
1158   VEX_LEN_5D_P_3,
1159   VEX_LEN_5E_P_1,
1160   VEX_LEN_5E_P_3,
1161   VEX_LEN_5F_P_1,
1162   VEX_LEN_5F_P_3,
1163   VEX_LEN_60_P_2,
1164   VEX_LEN_61_P_2,
1165   VEX_LEN_62_P_2,
1166   VEX_LEN_63_P_2,
1167   VEX_LEN_64_P_2,
1168   VEX_LEN_65_P_2,
1169   VEX_LEN_66_P_2,
1170   VEX_LEN_67_P_2,
1171   VEX_LEN_68_P_2,
1172   VEX_LEN_69_P_2,
1173   VEX_LEN_6A_P_2,
1174   VEX_LEN_6B_P_2,
1175   VEX_LEN_6C_P_2,
1176   VEX_LEN_6D_P_2,
1177   VEX_LEN_6E_P_2,
1178   VEX_LEN_70_P_1,
1179   VEX_LEN_70_P_2,
1180   VEX_LEN_70_P_3,
1181   VEX_LEN_71_R_2_P_2,
1182   VEX_LEN_71_R_4_P_2,
1183   VEX_LEN_71_R_6_P_2,
1184   VEX_LEN_72_R_2_P_2,
1185   VEX_LEN_72_R_4_P_2,
1186   VEX_LEN_72_R_6_P_2,
1187   VEX_LEN_73_R_2_P_2,
1188   VEX_LEN_73_R_3_P_2,
1189   VEX_LEN_73_R_6_P_2,
1190   VEX_LEN_73_R_7_P_2,
1191   VEX_LEN_74_P_2,
1192   VEX_LEN_75_P_2,
1193   VEX_LEN_76_P_2,
1194   VEX_LEN_7E_P_1,
1195   VEX_LEN_7E_P_2,
1196   VEX_LEN_AE_R_2_M_0,
1197   VEX_LEN_AE_R_3_M_0,
1198   VEX_LEN_C2_P_1,
1199   VEX_LEN_C2_P_3,
1200   VEX_LEN_C4_P_2,
1201   VEX_LEN_C5_P_2,
1202   VEX_LEN_D1_P_2,
1203   VEX_LEN_D2_P_2,
1204   VEX_LEN_D3_P_2,
1205   VEX_LEN_D4_P_2,
1206   VEX_LEN_D5_P_2,
1207   VEX_LEN_D6_P_2,
1208   VEX_LEN_D7_P_2_M_1,
1209   VEX_LEN_D8_P_2,
1210   VEX_LEN_D9_P_2,
1211   VEX_LEN_DA_P_2,
1212   VEX_LEN_DB_P_2,
1213   VEX_LEN_DC_P_2,
1214   VEX_LEN_DD_P_2,
1215   VEX_LEN_DE_P_2,
1216   VEX_LEN_DF_P_2,
1217   VEX_LEN_E0_P_2,
1218   VEX_LEN_E1_P_2,
1219   VEX_LEN_E2_P_2,
1220   VEX_LEN_E3_P_2,
1221   VEX_LEN_E4_P_2,
1222   VEX_LEN_E5_P_2,
1223   VEX_LEN_E8_P_2,
1224   VEX_LEN_E9_P_2,
1225   VEX_LEN_EA_P_2,
1226   VEX_LEN_EB_P_2,
1227   VEX_LEN_EC_P_2,
1228   VEX_LEN_ED_P_2,
1229   VEX_LEN_EE_P_2,
1230   VEX_LEN_EF_P_2,
1231   VEX_LEN_F1_P_2,
1232   VEX_LEN_F2_P_2,
1233   VEX_LEN_F3_P_2,
1234   VEX_LEN_F4_P_2,
1235   VEX_LEN_F5_P_2,
1236   VEX_LEN_F6_P_2,
1237   VEX_LEN_F7_P_2,
1238   VEX_LEN_F8_P_2,
1239   VEX_LEN_F9_P_2,
1240   VEX_LEN_FA_P_2,
1241   VEX_LEN_FB_P_2,
1242   VEX_LEN_FC_P_2,
1243   VEX_LEN_FD_P_2,
1244   VEX_LEN_FE_P_2,
1245   VEX_LEN_3800_P_2,
1246   VEX_LEN_3801_P_2,
1247   VEX_LEN_3802_P_2,
1248   VEX_LEN_3803_P_2,
1249   VEX_LEN_3804_P_2,
1250   VEX_LEN_3805_P_2,
1251   VEX_LEN_3806_P_2,
1252   VEX_LEN_3807_P_2,
1253   VEX_LEN_3808_P_2,
1254   VEX_LEN_3809_P_2,
1255   VEX_LEN_380A_P_2,
1256   VEX_LEN_380B_P_2,
1257   VEX_LEN_3819_P_2_M_0,
1258   VEX_LEN_381A_P_2_M_0,
1259   VEX_LEN_381C_P_2,
1260   VEX_LEN_381D_P_2,
1261   VEX_LEN_381E_P_2,
1262   VEX_LEN_3820_P_2,
1263   VEX_LEN_3821_P_2,
1264   VEX_LEN_3822_P_2,
1265   VEX_LEN_3823_P_2,
1266   VEX_LEN_3824_P_2,
1267   VEX_LEN_3825_P_2,
1268   VEX_LEN_3828_P_2,
1269   VEX_LEN_3829_P_2,
1270   VEX_LEN_382A_P_2_M_0,
1271   VEX_LEN_382B_P_2,
1272   VEX_LEN_3830_P_2,
1273   VEX_LEN_3831_P_2,
1274   VEX_LEN_3832_P_2,
1275   VEX_LEN_3833_P_2,
1276   VEX_LEN_3834_P_2,
1277   VEX_LEN_3835_P_2,
1278   VEX_LEN_3837_P_2,
1279   VEX_LEN_3838_P_2,
1280   VEX_LEN_3839_P_2,
1281   VEX_LEN_383A_P_2,
1282   VEX_LEN_383B_P_2,
1283   VEX_LEN_383C_P_2,
1284   VEX_LEN_383D_P_2,
1285   VEX_LEN_383E_P_2,
1286   VEX_LEN_383F_P_2,
1287   VEX_LEN_3840_P_2,
1288   VEX_LEN_3841_P_2,
1289   VEX_LEN_38DB_P_2,
1290   VEX_LEN_38DC_P_2,
1291   VEX_LEN_38DD_P_2,
1292   VEX_LEN_38DE_P_2,
1293   VEX_LEN_38DF_P_2,
1294   VEX_LEN_3A06_P_2,
1295   VEX_LEN_3A0A_P_2,
1296   VEX_LEN_3A0B_P_2,
1297   VEX_LEN_3A0E_P_2,
1298   VEX_LEN_3A0F_P_2,
1299   VEX_LEN_3A14_P_2,
1300   VEX_LEN_3A15_P_2,
1301   VEX_LEN_3A16_P_2,
1302   VEX_LEN_3A17_P_2,
1303   VEX_LEN_3A18_P_2,
1304   VEX_LEN_3A19_P_2,
1305   VEX_LEN_3A20_P_2,
1306   VEX_LEN_3A21_P_2,
1307   VEX_LEN_3A22_P_2,
1308   VEX_LEN_3A41_P_2,
1309   VEX_LEN_3A42_P_2,
1310   VEX_LEN_3A44_P_2,
1311   VEX_LEN_3A4C_P_2,
1312   VEX_LEN_3A60_P_2,
1313   VEX_LEN_3A61_P_2,
1314   VEX_LEN_3A62_P_2,
1315   VEX_LEN_3A63_P_2,
1316   VEX_LEN_3A6A_P_2,
1317   VEX_LEN_3A6B_P_2,
1318   VEX_LEN_3A6E_P_2,
1319   VEX_LEN_3A6F_P_2,
1320   VEX_LEN_3A7A_P_2,
1321   VEX_LEN_3A7B_P_2,
1322   VEX_LEN_3A7E_P_2,
1323   VEX_LEN_3A7F_P_2,
1324   VEX_LEN_3ADF_P_2,
1325   VEX_LEN_XOP_09_80,
1326   VEX_LEN_XOP_09_81
1327 };
1328
1329 enum
1330 {
1331   VEX_W_10_P_0 = 0,
1332   VEX_W_10_P_1,
1333   VEX_W_10_P_2,
1334   VEX_W_10_P_3,
1335   VEX_W_11_P_0,
1336   VEX_W_11_P_1,
1337   VEX_W_11_P_2,
1338   VEX_W_11_P_3,
1339   VEX_W_12_P_0_M_0,
1340   VEX_W_12_P_0_M_1,
1341   VEX_W_12_P_1,
1342   VEX_W_12_P_2,
1343   VEX_W_12_P_3,
1344   VEX_W_13_M_0,
1345   VEX_W_14,
1346   VEX_W_15,
1347   VEX_W_16_P_0_M_0,
1348   VEX_W_16_P_0_M_1,
1349   VEX_W_16_P_1,
1350   VEX_W_16_P_2,
1351   VEX_W_17_M_0,
1352   VEX_W_28,
1353   VEX_W_29,
1354   VEX_W_2B_M_0,
1355   VEX_W_2E_P_0,
1356   VEX_W_2E_P_2,
1357   VEX_W_2F_P_0,
1358   VEX_W_2F_P_2,
1359   VEX_W_50_M_0,
1360   VEX_W_51_P_0,
1361   VEX_W_51_P_1,
1362   VEX_W_51_P_2,
1363   VEX_W_51_P_3,
1364   VEX_W_52_P_0,
1365   VEX_W_52_P_1,
1366   VEX_W_53_P_0,
1367   VEX_W_53_P_1,
1368   VEX_W_58_P_0,
1369   VEX_W_58_P_1,
1370   VEX_W_58_P_2,
1371   VEX_W_58_P_3,
1372   VEX_W_59_P_0,
1373   VEX_W_59_P_1,
1374   VEX_W_59_P_2,
1375   VEX_W_59_P_3,
1376   VEX_W_5A_P_0,
1377   VEX_W_5A_P_1,
1378   VEX_W_5A_P_3,
1379   VEX_W_5B_P_0,
1380   VEX_W_5B_P_1,
1381   VEX_W_5B_P_2,
1382   VEX_W_5C_P_0,
1383   VEX_W_5C_P_1,
1384   VEX_W_5C_P_2,
1385   VEX_W_5C_P_3,
1386   VEX_W_5D_P_0,
1387   VEX_W_5D_P_1,
1388   VEX_W_5D_P_2,
1389   VEX_W_5D_P_3,
1390   VEX_W_5E_P_0,
1391   VEX_W_5E_P_1,
1392   VEX_W_5E_P_2,
1393   VEX_W_5E_P_3,
1394   VEX_W_5F_P_0,
1395   VEX_W_5F_P_1,
1396   VEX_W_5F_P_2,
1397   VEX_W_5F_P_3,
1398   VEX_W_60_P_2,
1399   VEX_W_61_P_2,
1400   VEX_W_62_P_2,
1401   VEX_W_63_P_2,
1402   VEX_W_64_P_2,
1403   VEX_W_65_P_2,
1404   VEX_W_66_P_2,
1405   VEX_W_67_P_2,
1406   VEX_W_68_P_2,
1407   VEX_W_69_P_2,
1408   VEX_W_6A_P_2,
1409   VEX_W_6B_P_2,
1410   VEX_W_6C_P_2,
1411   VEX_W_6D_P_2,
1412   VEX_W_6F_P_1,
1413   VEX_W_6F_P_2,
1414   VEX_W_70_P_1,
1415   VEX_W_70_P_2,
1416   VEX_W_70_P_3,
1417   VEX_W_71_R_2_P_2,
1418   VEX_W_71_R_4_P_2,
1419   VEX_W_71_R_6_P_2,
1420   VEX_W_72_R_2_P_2,
1421   VEX_W_72_R_4_P_2,
1422   VEX_W_72_R_6_P_2,
1423   VEX_W_73_R_2_P_2,
1424   VEX_W_73_R_3_P_2,
1425   VEX_W_73_R_6_P_2,
1426   VEX_W_73_R_7_P_2,
1427   VEX_W_74_P_2,
1428   VEX_W_75_P_2,
1429   VEX_W_76_P_2,
1430   VEX_W_77_P_0,
1431   VEX_W_7C_P_2,
1432   VEX_W_7C_P_3,
1433   VEX_W_7D_P_2,
1434   VEX_W_7D_P_3,
1435   VEX_W_7E_P_1,
1436   VEX_W_7F_P_1,
1437   VEX_W_7F_P_2,
1438   VEX_W_AE_R_2_M_0,
1439   VEX_W_AE_R_3_M_0,
1440   VEX_W_C2_P_0,
1441   VEX_W_C2_P_1,
1442   VEX_W_C2_P_2,
1443   VEX_W_C2_P_3,
1444   VEX_W_C4_P_2,
1445   VEX_W_C5_P_2,
1446   VEX_W_D0_P_2,
1447   VEX_W_D0_P_3,
1448   VEX_W_D1_P_2,
1449   VEX_W_D2_P_2,
1450   VEX_W_D3_P_2,
1451   VEX_W_D4_P_2,
1452   VEX_W_D5_P_2,
1453   VEX_W_D6_P_2,
1454   VEX_W_D7_P_2_M_1,
1455   VEX_W_D8_P_2,
1456   VEX_W_D9_P_2,
1457   VEX_W_DA_P_2,
1458   VEX_W_DB_P_2,
1459   VEX_W_DC_P_2,
1460   VEX_W_DD_P_2,
1461   VEX_W_DE_P_2,
1462   VEX_W_DF_P_2,
1463   VEX_W_E0_P_2,
1464   VEX_W_E1_P_2,
1465   VEX_W_E2_P_2,
1466   VEX_W_E3_P_2,
1467   VEX_W_E4_P_2,
1468   VEX_W_E5_P_2,
1469   VEX_W_E6_P_1,
1470   VEX_W_E6_P_2,
1471   VEX_W_E6_P_3,
1472   VEX_W_E7_P_2_M_0,
1473   VEX_W_E8_P_2,
1474   VEX_W_E9_P_2,
1475   VEX_W_EA_P_2,
1476   VEX_W_EB_P_2,
1477   VEX_W_EC_P_2,
1478   VEX_W_ED_P_2,
1479   VEX_W_EE_P_2,
1480   VEX_W_EF_P_2,
1481   VEX_W_F0_P_3_M_0,
1482   VEX_W_F1_P_2,
1483   VEX_W_F2_P_2,
1484   VEX_W_F3_P_2,
1485   VEX_W_F4_P_2,
1486   VEX_W_F5_P_2,
1487   VEX_W_F6_P_2,
1488   VEX_W_F7_P_2,
1489   VEX_W_F8_P_2,
1490   VEX_W_F9_P_2,
1491   VEX_W_FA_P_2,
1492   VEX_W_FB_P_2,
1493   VEX_W_FC_P_2,
1494   VEX_W_FD_P_2,
1495   VEX_W_FE_P_2,
1496   VEX_W_3800_P_2,
1497   VEX_W_3801_P_2,
1498   VEX_W_3802_P_2,
1499   VEX_W_3803_P_2,
1500   VEX_W_3804_P_2,
1501   VEX_W_3805_P_2,
1502   VEX_W_3806_P_2,
1503   VEX_W_3807_P_2,
1504   VEX_W_3808_P_2,
1505   VEX_W_3809_P_2,
1506   VEX_W_380A_P_2,
1507   VEX_W_380B_P_2,
1508   VEX_W_380C_P_2,
1509   VEX_W_380D_P_2,
1510   VEX_W_380E_P_2,
1511   VEX_W_380F_P_2,
1512   VEX_W_3817_P_2,
1513   VEX_W_3818_P_2_M_0,
1514   VEX_W_3819_P_2_M_0,
1515   VEX_W_381A_P_2_M_0,
1516   VEX_W_381C_P_2,
1517   VEX_W_381D_P_2,
1518   VEX_W_381E_P_2,
1519   VEX_W_3820_P_2,
1520   VEX_W_3821_P_2,
1521   VEX_W_3822_P_2,
1522   VEX_W_3823_P_2,
1523   VEX_W_3824_P_2,
1524   VEX_W_3825_P_2,
1525   VEX_W_3828_P_2,
1526   VEX_W_3829_P_2,
1527   VEX_W_382A_P_2_M_0,
1528   VEX_W_382B_P_2,
1529   VEX_W_382C_P_2_M_0,
1530   VEX_W_382D_P_2_M_0,
1531   VEX_W_382E_P_2_M_0,
1532   VEX_W_382F_P_2_M_0,
1533   VEX_W_3830_P_2,
1534   VEX_W_3831_P_2,
1535   VEX_W_3832_P_2,
1536   VEX_W_3833_P_2,
1537   VEX_W_3834_P_2,
1538   VEX_W_3835_P_2,
1539   VEX_W_3837_P_2,
1540   VEX_W_3838_P_2,
1541   VEX_W_3839_P_2,
1542   VEX_W_383A_P_2,
1543   VEX_W_383B_P_2,
1544   VEX_W_383C_P_2,
1545   VEX_W_383D_P_2,
1546   VEX_W_383E_P_2,
1547   VEX_W_383F_P_2,
1548   VEX_W_3840_P_2,
1549   VEX_W_3841_P_2,
1550   VEX_W_38DB_P_2,
1551   VEX_W_38DC_P_2,
1552   VEX_W_38DD_P_2,
1553   VEX_W_38DE_P_2,
1554   VEX_W_38DF_P_2,
1555   VEX_W_3A04_P_2,
1556   VEX_W_3A05_P_2,
1557   VEX_W_3A06_P_2,
1558   VEX_W_3A08_P_2,
1559   VEX_W_3A09_P_2,
1560   VEX_W_3A0A_P_2,
1561   VEX_W_3A0B_P_2,
1562   VEX_W_3A0C_P_2,
1563   VEX_W_3A0D_P_2,
1564   VEX_W_3A0E_P_2,
1565   VEX_W_3A0F_P_2,
1566   VEX_W_3A14_P_2,
1567   VEX_W_3A15_P_2,
1568   VEX_W_3A18_P_2,
1569   VEX_W_3A19_P_2,
1570   VEX_W_3A20_P_2,
1571   VEX_W_3A21_P_2,
1572   VEX_W_3A40_P_2,
1573   VEX_W_3A41_P_2,
1574   VEX_W_3A42_P_2,
1575   VEX_W_3A44_P_2,
1576   VEX_W_3A48_P_2,
1577   VEX_W_3A49_P_2,
1578   VEX_W_3A4A_P_2,
1579   VEX_W_3A4B_P_2,
1580   VEX_W_3A4C_P_2,
1581   VEX_W_3A60_P_2,
1582   VEX_W_3A61_P_2,
1583   VEX_W_3A62_P_2,
1584   VEX_W_3A63_P_2,
1585   VEX_W_3ADF_P_2
1586 };
1587
1588 typedef void (*op_rtn) (int bytemode, int sizeflag);
1589
1590 struct dis386 {
1591   const char *name;
1592   struct
1593     {
1594       op_rtn rtn;
1595       int bytemode;
1596     } op[MAX_OPERANDS];
1597 };
1598
1599 /* Upper case letters in the instruction names here are macros.
1600    'A' => print 'b' if no register operands or suffix_always is true
1601    'B' => print 'b' if suffix_always is true
1602    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1603           size prefix
1604    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1605           suffix_always is true
1606    'E' => print 'e' if 32-bit form of jcxz
1607    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1608    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1609    'H' => print ",pt" or ",pn" branch hint
1610    'I' => honor following macro letter even in Intel mode (implemented only
1611           for some of the macro letters)
1612    'J' => print 'l'
1613    'K' => print 'd' or 'q' if rex prefix is present.
1614    'L' => print 'l' if suffix_always is true
1615    'M' => print 'r' if intel_mnemonic is false.
1616    'N' => print 'n' if instruction has no wait "prefix"
1617    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1618    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1619           or suffix_always is true.  print 'q' if rex prefix is present.
1620    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1621           is true
1622    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1623    'S' => print 'w', 'l' or 'q' if suffix_always is true
1624    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1625    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1626    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1627    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1628    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1629    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1630           suffix_always is true.
1631    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1632    '!' => change condition from true to false or from false to true.
1633    '%' => add 1 upper case letter to the macro.
1634
1635    2 upper case letter macros:
1636    "XY" => print 'x' or 'y' if no register operands or suffix_always
1637            is true.
1638    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1639    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1640            or suffix_always is true
1641    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1642    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1643    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1644
1645    Many of the above letters print nothing in Intel mode.  See "putop"
1646    for the details.
1647
1648    Braces '{' and '}', and vertical bars '|', indicate alternative
1649    mnemonic strings for AT&T and Intel.  */
1650
1651 static const struct dis386 dis386[] = {
1652   /* 00 */
1653   { "addB",             { Eb, Gb } },
1654   { "addS",             { Ev, Gv } },
1655   { "addB",             { Gb, EbS } },
1656   { "addS",             { Gv, EvS } },
1657   { "addB",             { AL, Ib } },
1658   { "addS",             { eAX, Iv } },
1659   { X86_64_TABLE (X86_64_06) },
1660   { X86_64_TABLE (X86_64_07) },
1661   /* 08 */
1662   { "orB",              { Eb, Gb } },
1663   { "orS",              { Ev, Gv } },
1664   { "orB",              { Gb, EbS } },
1665   { "orS",              { Gv, EvS } },
1666   { "orB",              { AL, Ib } },
1667   { "orS",              { eAX, Iv } },
1668   { X86_64_TABLE (X86_64_0D) },
1669   { Bad_Opcode },       /* 0x0f extended opcode escape */
1670   /* 10 */
1671   { "adcB",             { Eb, Gb } },
1672   { "adcS",             { Ev, Gv } },
1673   { "adcB",             { Gb, EbS } },
1674   { "adcS",             { Gv, EvS } },
1675   { "adcB",             { AL, Ib } },
1676   { "adcS",             { eAX, Iv } },
1677   { X86_64_TABLE (X86_64_16) },
1678   { X86_64_TABLE (X86_64_17) },
1679   /* 18 */
1680   { "sbbB",             { Eb, Gb } },
1681   { "sbbS",             { Ev, Gv } },
1682   { "sbbB",             { Gb, EbS } },
1683   { "sbbS",             { Gv, EvS } },
1684   { "sbbB",             { AL, Ib } },
1685   { "sbbS",             { eAX, Iv } },
1686   { X86_64_TABLE (X86_64_1E) },
1687   { X86_64_TABLE (X86_64_1F) },
1688   /* 20 */
1689   { "andB",             { Eb, Gb } },
1690   { "andS",             { Ev, Gv } },
1691   { "andB",             { Gb, EbS } },
1692   { "andS",             { Gv, EvS } },
1693   { "andB",             { AL, Ib } },
1694   { "andS",             { eAX, Iv } },
1695   { Bad_Opcode },       /* SEG ES prefix */
1696   { X86_64_TABLE (X86_64_27) },
1697   /* 28 */
1698   { "subB",             { Eb, Gb } },
1699   { "subS",             { Ev, Gv } },
1700   { "subB",             { Gb, EbS } },
1701   { "subS",             { Gv, EvS } },
1702   { "subB",             { AL, Ib } },
1703   { "subS",             { eAX, Iv } },
1704   { Bad_Opcode },       /* SEG CS prefix */
1705   { X86_64_TABLE (X86_64_2F) },
1706   /* 30 */
1707   { "xorB",             { Eb, Gb } },
1708   { "xorS",             { Ev, Gv } },
1709   { "xorB",             { Gb, EbS } },
1710   { "xorS",             { Gv, EvS } },
1711   { "xorB",             { AL, Ib } },
1712   { "xorS",             { eAX, Iv } },
1713   { Bad_Opcode },       /* SEG SS prefix */
1714   { X86_64_TABLE (X86_64_37) },
1715   /* 38 */
1716   { "cmpB",             { Eb, Gb } },
1717   { "cmpS",             { Ev, Gv } },
1718   { "cmpB",             { Gb, EbS } },
1719   { "cmpS",             { Gv, EvS } },
1720   { "cmpB",             { AL, Ib } },
1721   { "cmpS",             { eAX, Iv } },
1722   { Bad_Opcode },       /* SEG DS prefix */
1723   { X86_64_TABLE (X86_64_3F) },
1724   /* 40 */
1725   { "inc{S|}",          { RMeAX } },
1726   { "inc{S|}",          { RMeCX } },
1727   { "inc{S|}",          { RMeDX } },
1728   { "inc{S|}",          { RMeBX } },
1729   { "inc{S|}",          { RMeSP } },
1730   { "inc{S|}",          { RMeBP } },
1731   { "inc{S|}",          { RMeSI } },
1732   { "inc{S|}",          { RMeDI } },
1733   /* 48 */
1734   { "dec{S|}",          { RMeAX } },
1735   { "dec{S|}",          { RMeCX } },
1736   { "dec{S|}",          { RMeDX } },
1737   { "dec{S|}",          { RMeBX } },
1738   { "dec{S|}",          { RMeSP } },
1739   { "dec{S|}",          { RMeBP } },
1740   { "dec{S|}",          { RMeSI } },
1741   { "dec{S|}",          { RMeDI } },
1742   /* 50 */
1743   { "pushV",            { RMrAX } },
1744   { "pushV",            { RMrCX } },
1745   { "pushV",            { RMrDX } },
1746   { "pushV",            { RMrBX } },
1747   { "pushV",            { RMrSP } },
1748   { "pushV",            { RMrBP } },
1749   { "pushV",            { RMrSI } },
1750   { "pushV",            { RMrDI } },
1751   /* 58 */
1752   { "popV",             { RMrAX } },
1753   { "popV",             { RMrCX } },
1754   { "popV",             { RMrDX } },
1755   { "popV",             { RMrBX } },
1756   { "popV",             { RMrSP } },
1757   { "popV",             { RMrBP } },
1758   { "popV",             { RMrSI } },
1759   { "popV",             { RMrDI } },
1760   /* 60 */
1761   { X86_64_TABLE (X86_64_60) },
1762   { X86_64_TABLE (X86_64_61) },
1763   { X86_64_TABLE (X86_64_62) },
1764   { X86_64_TABLE (X86_64_63) },
1765   { Bad_Opcode },       /* seg fs */
1766   { Bad_Opcode },       /* seg gs */
1767   { Bad_Opcode },       /* op size prefix */
1768   { Bad_Opcode },       /* adr size prefix */
1769   /* 68 */
1770   { "pushT",            { Iq } },
1771   { "imulS",            { Gv, Ev, Iv } },
1772   { "pushT",            { sIb } },
1773   { "imulS",            { Gv, Ev, sIb } },
1774   { "ins{b|}",          { Ybr, indirDX } },
1775   { X86_64_TABLE (X86_64_6D) },
1776   { "outs{b|}",         { indirDXr, Xb } },
1777   { X86_64_TABLE (X86_64_6F) },
1778   /* 70 */
1779   { "joH",              { Jb, XX, cond_jump_flag } },
1780   { "jnoH",             { Jb, XX, cond_jump_flag } },
1781   { "jbH",              { Jb, XX, cond_jump_flag } },
1782   { "jaeH",             { Jb, XX, cond_jump_flag } },
1783   { "jeH",              { Jb, XX, cond_jump_flag } },
1784   { "jneH",             { Jb, XX, cond_jump_flag } },
1785   { "jbeH",             { Jb, XX, cond_jump_flag } },
1786   { "jaH",              { Jb, XX, cond_jump_flag } },
1787   /* 78 */
1788   { "jsH",              { Jb, XX, cond_jump_flag } },
1789   { "jnsH",             { Jb, XX, cond_jump_flag } },
1790   { "jpH",              { Jb, XX, cond_jump_flag } },
1791   { "jnpH",             { Jb, XX, cond_jump_flag } },
1792   { "jlH",              { Jb, XX, cond_jump_flag } },
1793   { "jgeH",             { Jb, XX, cond_jump_flag } },
1794   { "jleH",             { Jb, XX, cond_jump_flag } },
1795   { "jgH",              { Jb, XX, cond_jump_flag } },
1796   /* 80 */
1797   { REG_TABLE (REG_80) },
1798   { REG_TABLE (REG_81) },
1799   { Bad_Opcode },
1800   { REG_TABLE (REG_82) },
1801   { "testB",            { Eb, Gb } },
1802   { "testS",            { Ev, Gv } },
1803   { "xchgB",            { Eb, Gb } },
1804   { "xchgS",            { Ev, Gv } },
1805   /* 88 */
1806   { "movB",             { Eb, Gb } },
1807   { "movS",             { Ev, Gv } },
1808   { "movB",             { Gb, EbS } },
1809   { "movS",             { Gv, EvS } },
1810   { "movD",             { Sv, Sw } },
1811   { MOD_TABLE (MOD_8D) },
1812   { "movD",             { Sw, Sv } },
1813   { REG_TABLE (REG_8F) },
1814   /* 90 */
1815   { PREFIX_TABLE (PREFIX_90) },
1816   { "xchgS",            { RMeCX, eAX } },
1817   { "xchgS",            { RMeDX, eAX } },
1818   { "xchgS",            { RMeBX, eAX } },
1819   { "xchgS",            { RMeSP, eAX } },
1820   { "xchgS",            { RMeBP, eAX } },
1821   { "xchgS",            { RMeSI, eAX } },
1822   { "xchgS",            { RMeDI, eAX } },
1823   /* 98 */
1824   { "cW{t|}R",          { XX } },
1825   { "cR{t|}O",          { XX } },
1826   { X86_64_TABLE (X86_64_9A) },
1827   { Bad_Opcode },       /* fwait */
1828   { "pushfT",           { XX } },
1829   { "popfT",            { XX } },
1830   { "sahf",             { XX } },
1831   { "lahf",             { XX } },
1832   /* a0 */
1833   { "mov%LB",           { AL, Ob } },
1834   { "mov%LS",           { eAX, Ov } },
1835   { "mov%LB",           { Ob, AL } },
1836   { "mov%LS",           { Ov, eAX } },
1837   { "movs{b|}",         { Ybr, Xb } },
1838   { "movs{R|}",         { Yvr, Xv } },
1839   { "cmps{b|}",         { Xb, Yb } },
1840   { "cmps{R|}",         { Xv, Yv } },
1841   /* a8 */
1842   { "testB",            { AL, Ib } },
1843   { "testS",            { eAX, Iv } },
1844   { "stosB",            { Ybr, AL } },
1845   { "stosS",            { Yvr, eAX } },
1846   { "lodsB",            { ALr, Xb } },
1847   { "lodsS",            { eAXr, Xv } },
1848   { "scasB",            { AL, Yb } },
1849   { "scasS",            { eAX, Yv } },
1850   /* b0 */
1851   { "movB",             { RMAL, Ib } },
1852   { "movB",             { RMCL, Ib } },
1853   { "movB",             { RMDL, Ib } },
1854   { "movB",             { RMBL, Ib } },
1855   { "movB",             { RMAH, Ib } },
1856   { "movB",             { RMCH, Ib } },
1857   { "movB",             { RMDH, Ib } },
1858   { "movB",             { RMBH, Ib } },
1859   /* b8 */
1860   { "mov%LV",           { RMeAX, Iv64 } },
1861   { "mov%LV",           { RMeCX, Iv64 } },
1862   { "mov%LV",           { RMeDX, Iv64 } },
1863   { "mov%LV",           { RMeBX, Iv64 } },
1864   { "mov%LV",           { RMeSP, Iv64 } },
1865   { "mov%LV",           { RMeBP, Iv64 } },
1866   { "mov%LV",           { RMeSI, Iv64 } },
1867   { "mov%LV",           { RMeDI, Iv64 } },
1868   /* c0 */
1869   { REG_TABLE (REG_C0) },
1870   { REG_TABLE (REG_C1) },
1871   { "retT",             { Iw } },
1872   { "retT",             { XX } },
1873   { X86_64_TABLE (X86_64_C4) },
1874   { X86_64_TABLE (X86_64_C5) },
1875   { REG_TABLE (REG_C6) },
1876   { REG_TABLE (REG_C7) },
1877   /* c8 */
1878   { "enterT",           { Iw, Ib } },
1879   { "leaveT",           { XX } },
1880   { "Jret{|f}P",        { Iw } },
1881   { "Jret{|f}P",        { XX } },
1882   { "int3",             { XX } },
1883   { "int",              { Ib } },
1884   { X86_64_TABLE (X86_64_CE) },
1885   { "iretP",            { XX } },
1886   /* d0 */
1887   { REG_TABLE (REG_D0) },
1888   { REG_TABLE (REG_D1) },
1889   { REG_TABLE (REG_D2) },
1890   { REG_TABLE (REG_D3) },
1891   { X86_64_TABLE (X86_64_D4) },
1892   { X86_64_TABLE (X86_64_D5) },
1893   { Bad_Opcode },
1894   { "xlat",             { DSBX } },
1895   /* d8 */
1896   { FLOAT },
1897   { FLOAT },
1898   { FLOAT },
1899   { FLOAT },
1900   { FLOAT },
1901   { FLOAT },
1902   { FLOAT },
1903   { FLOAT },
1904   /* e0 */
1905   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1906   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1907   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1908   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1909   { "inB",              { AL, Ib } },
1910   { "inG",              { zAX, Ib } },
1911   { "outB",             { Ib, AL } },
1912   { "outG",             { Ib, zAX } },
1913   /* e8 */
1914   { "callT",            { Jv } },
1915   { "jmpT",             { Jv } },
1916   { X86_64_TABLE (X86_64_EA) },
1917   { "jmp",              { Jb } },
1918   { "inB",              { AL, indirDX } },
1919   { "inG",              { zAX, indirDX } },
1920   { "outB",             { indirDX, AL } },
1921   { "outG",             { indirDX, zAX } },
1922   /* f0 */
1923   { Bad_Opcode },       /* lock prefix */
1924   { "icebp",            { XX } },
1925   { Bad_Opcode },       /* repne */
1926   { Bad_Opcode },       /* repz */
1927   { "hlt",              { XX } },
1928   { "cmc",              { XX } },
1929   { REG_TABLE (REG_F6) },
1930   { REG_TABLE (REG_F7) },
1931   /* f8 */
1932   { "clc",              { XX } },
1933   { "stc",              { XX } },
1934   { "cli",              { XX } },
1935   { "sti",              { XX } },
1936   { "cld",              { XX } },
1937   { "std",              { XX } },
1938   { REG_TABLE (REG_FE) },
1939   { REG_TABLE (REG_FF) },
1940 };
1941
1942 static const struct dis386 dis386_twobyte[] = {
1943   /* 00 */
1944   { REG_TABLE (REG_0F00 ) },
1945   { REG_TABLE (REG_0F01 ) },
1946   { "larS",             { Gv, Ew } },
1947   { "lslS",             { Gv, Ew } },
1948   { Bad_Opcode },
1949   { "syscall",          { XX } },
1950   { "clts",             { XX } },
1951   { "sysretP",          { XX } },
1952   /* 08 */
1953   { "invd",             { XX } },
1954   { "wbinvd",           { XX } },
1955   { Bad_Opcode },
1956   { "ud2a",             { XX } },
1957   { Bad_Opcode },
1958   { REG_TABLE (REG_0F0D) },
1959   { "femms",            { XX } },
1960   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1961   /* 10 */
1962   { PREFIX_TABLE (PREFIX_0F10) },
1963   { PREFIX_TABLE (PREFIX_0F11) },
1964   { PREFIX_TABLE (PREFIX_0F12) },
1965   { MOD_TABLE (MOD_0F13) },
1966   { "unpcklpX",         { XM, EXx } },
1967   { "unpckhpX",         { XM, EXx } },
1968   { PREFIX_TABLE (PREFIX_0F16) },
1969   { MOD_TABLE (MOD_0F17) },
1970   /* 18 */
1971   { REG_TABLE (REG_0F18) },
1972   { "nopQ",             { Ev } },
1973   { "nopQ",             { Ev } },
1974   { "nopQ",             { Ev } },
1975   { "nopQ",             { Ev } },
1976   { "nopQ",             { Ev } },
1977   { "nopQ",             { Ev } },
1978   { "nopQ",             { Ev } },
1979   /* 20 */
1980   { MOD_TABLE (MOD_0F20) },
1981   { MOD_TABLE (MOD_0F21) },
1982   { MOD_TABLE (MOD_0F22) },
1983   { MOD_TABLE (MOD_0F23) },
1984   { MOD_TABLE (MOD_0F24) },
1985   { Bad_Opcode },
1986   { MOD_TABLE (MOD_0F26) },
1987   { Bad_Opcode },
1988   /* 28 */
1989   { "movapX",           { XM, EXx } },
1990   { "movapX",           { EXxS, XM } },
1991   { PREFIX_TABLE (PREFIX_0F2A) },
1992   { PREFIX_TABLE (PREFIX_0F2B) },
1993   { PREFIX_TABLE (PREFIX_0F2C) },
1994   { PREFIX_TABLE (PREFIX_0F2D) },
1995   { PREFIX_TABLE (PREFIX_0F2E) },
1996   { PREFIX_TABLE (PREFIX_0F2F) },
1997   /* 30 */
1998   { "wrmsr",            { XX } },
1999   { "rdtsc",            { XX } },
2000   { "rdmsr",            { XX } },
2001   { "rdpmc",            { XX } },
2002   { "sysenter",         { XX } },
2003   { "sysexit",          { XX } },
2004   { Bad_Opcode },
2005   { "getsec",           { XX } },
2006   /* 38 */
2007   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2008   { Bad_Opcode },
2009   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2010   { Bad_Opcode },
2011   { Bad_Opcode },
2012   { Bad_Opcode },
2013   { Bad_Opcode },
2014   { Bad_Opcode },
2015   /* 40 */
2016   { "cmovoS",           { Gv, Ev } },
2017   { "cmovnoS",          { Gv, Ev } },
2018   { "cmovbS",           { Gv, Ev } },
2019   { "cmovaeS",          { Gv, Ev } },
2020   { "cmoveS",           { Gv, Ev } },
2021   { "cmovneS",          { Gv, Ev } },
2022   { "cmovbeS",          { Gv, Ev } },
2023   { "cmovaS",           { Gv, Ev } },
2024   /* 48 */
2025   { "cmovsS",           { Gv, Ev } },
2026   { "cmovnsS",          { Gv, Ev } },
2027   { "cmovpS",           { Gv, Ev } },
2028   { "cmovnpS",          { Gv, Ev } },
2029   { "cmovlS",           { Gv, Ev } },
2030   { "cmovgeS",          { Gv, Ev } },
2031   { "cmovleS",          { Gv, Ev } },
2032   { "cmovgS",           { Gv, Ev } },
2033   /* 50 */
2034   { MOD_TABLE (MOD_0F51) },
2035   { PREFIX_TABLE (PREFIX_0F51) },
2036   { PREFIX_TABLE (PREFIX_0F52) },
2037   { PREFIX_TABLE (PREFIX_0F53) },
2038   { "andpX",            { XM, EXx } },
2039   { "andnpX",           { XM, EXx } },
2040   { "orpX",             { XM, EXx } },
2041   { "xorpX",            { XM, EXx } },
2042   /* 58 */
2043   { PREFIX_TABLE (PREFIX_0F58) },
2044   { PREFIX_TABLE (PREFIX_0F59) },
2045   { PREFIX_TABLE (PREFIX_0F5A) },
2046   { PREFIX_TABLE (PREFIX_0F5B) },
2047   { PREFIX_TABLE (PREFIX_0F5C) },
2048   { PREFIX_TABLE (PREFIX_0F5D) },
2049   { PREFIX_TABLE (PREFIX_0F5E) },
2050   { PREFIX_TABLE (PREFIX_0F5F) },
2051   /* 60 */
2052   { PREFIX_TABLE (PREFIX_0F60) },
2053   { PREFIX_TABLE (PREFIX_0F61) },
2054   { PREFIX_TABLE (PREFIX_0F62) },
2055   { "packsswb",         { MX, EM } },
2056   { "pcmpgtb",          { MX, EM } },
2057   { "pcmpgtw",          { MX, EM } },
2058   { "pcmpgtd",          { MX, EM } },
2059   { "packuswb",         { MX, EM } },
2060   /* 68 */
2061   { "punpckhbw",        { MX, EM } },
2062   { "punpckhwd",        { MX, EM } },
2063   { "punpckhdq",        { MX, EM } },
2064   { "packssdw",         { MX, EM } },
2065   { PREFIX_TABLE (PREFIX_0F6C) },
2066   { PREFIX_TABLE (PREFIX_0F6D) },
2067   { "movK",             { MX, Edq } },
2068   { PREFIX_TABLE (PREFIX_0F6F) },
2069   /* 70 */
2070   { PREFIX_TABLE (PREFIX_0F70) },
2071   { REG_TABLE (REG_0F71) },
2072   { REG_TABLE (REG_0F72) },
2073   { REG_TABLE (REG_0F73) },
2074   { "pcmpeqb",          { MX, EM } },
2075   { "pcmpeqw",          { MX, EM } },
2076   { "pcmpeqd",          { MX, EM } },
2077   { "emms",             { XX } },
2078   /* 78 */
2079   { PREFIX_TABLE (PREFIX_0F78) },
2080   { PREFIX_TABLE (PREFIX_0F79) },
2081   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2082   { Bad_Opcode },
2083   { PREFIX_TABLE (PREFIX_0F7C) },
2084   { PREFIX_TABLE (PREFIX_0F7D) },
2085   { PREFIX_TABLE (PREFIX_0F7E) },
2086   { PREFIX_TABLE (PREFIX_0F7F) },
2087   /* 80 */
2088   { "joH",              { Jv, XX, cond_jump_flag } },
2089   { "jnoH",             { Jv, XX, cond_jump_flag } },
2090   { "jbH",              { Jv, XX, cond_jump_flag } },
2091   { "jaeH",             { Jv, XX, cond_jump_flag } },
2092   { "jeH",              { Jv, XX, cond_jump_flag } },
2093   { "jneH",             { Jv, XX, cond_jump_flag } },
2094   { "jbeH",             { Jv, XX, cond_jump_flag } },
2095   { "jaH",              { Jv, XX, cond_jump_flag } },
2096   /* 88 */
2097   { "jsH",              { Jv, XX, cond_jump_flag } },
2098   { "jnsH",             { Jv, XX, cond_jump_flag } },
2099   { "jpH",              { Jv, XX, cond_jump_flag } },
2100   { "jnpH",             { Jv, XX, cond_jump_flag } },
2101   { "jlH",              { Jv, XX, cond_jump_flag } },
2102   { "jgeH",             { Jv, XX, cond_jump_flag } },
2103   { "jleH",             { Jv, XX, cond_jump_flag } },
2104   { "jgH",              { Jv, XX, cond_jump_flag } },
2105   /* 90 */
2106   { "seto",             { Eb } },
2107   { "setno",            { Eb } },
2108   { "setb",             { Eb } },
2109   { "setae",            { Eb } },
2110   { "sete",             { Eb } },
2111   { "setne",            { Eb } },
2112   { "setbe",            { Eb } },
2113   { "seta",             { Eb } },
2114   /* 98 */
2115   { "sets",             { Eb } },
2116   { "setns",            { Eb } },
2117   { "setp",             { Eb } },
2118   { "setnp",            { Eb } },
2119   { "setl",             { Eb } },
2120   { "setge",            { Eb } },
2121   { "setle",            { Eb } },
2122   { "setg",             { Eb } },
2123   /* a0 */
2124   { "pushT",            { fs } },
2125   { "popT",             { fs } },
2126   { "cpuid",            { XX } },
2127   { "btS",              { Ev, Gv } },
2128   { "shldS",            { Ev, Gv, Ib } },
2129   { "shldS",            { Ev, Gv, CL } },
2130   { REG_TABLE (REG_0FA6) },
2131   { REG_TABLE (REG_0FA7) },
2132   /* a8 */
2133   { "pushT",            { gs } },
2134   { "popT",             { gs } },
2135   { "rsm",              { XX } },
2136   { "btsS",             { Ev, Gv } },
2137   { "shrdS",            { Ev, Gv, Ib } },
2138   { "shrdS",            { Ev, Gv, CL } },
2139   { REG_TABLE (REG_0FAE) },
2140   { "imulS",            { Gv, Ev } },
2141   /* b0 */
2142   { "cmpxchgB",         { Eb, Gb } },
2143   { "cmpxchgS",         { Ev, Gv } },
2144   { MOD_TABLE (MOD_0FB2) },
2145   { "btrS",             { Ev, Gv } },
2146   { MOD_TABLE (MOD_0FB4) },
2147   { MOD_TABLE (MOD_0FB5) },
2148   { "movz{bR|x}",       { Gv, Eb } },
2149   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2150   /* b8 */
2151   { PREFIX_TABLE (PREFIX_0FB8) },
2152   { "ud2b",             { XX } },
2153   { REG_TABLE (REG_0FBA) },
2154   { "btcS",             { Ev, Gv } },
2155   { "bsfS",             { Gv, Ev } },
2156   { PREFIX_TABLE (PREFIX_0FBD) },
2157   { "movs{bR|x}",       { Gv, Eb } },
2158   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2159   /* c0 */
2160   { "xaddB",            { Eb, Gb } },
2161   { "xaddS",            { Ev, Gv } },
2162   { PREFIX_TABLE (PREFIX_0FC2) },
2163   { PREFIX_TABLE (PREFIX_0FC3) },
2164   { "pinsrw",           { MX, Edqw, Ib } },
2165   { "pextrw",           { Gdq, MS, Ib } },
2166   { "shufpX",           { XM, EXx, Ib } },
2167   { REG_TABLE (REG_0FC7) },
2168   /* c8 */
2169   { "bswap",            { RMeAX } },
2170   { "bswap",            { RMeCX } },
2171   { "bswap",            { RMeDX } },
2172   { "bswap",            { RMeBX } },
2173   { "bswap",            { RMeSP } },
2174   { "bswap",            { RMeBP } },
2175   { "bswap",            { RMeSI } },
2176   { "bswap",            { RMeDI } },
2177   /* d0 */
2178   { PREFIX_TABLE (PREFIX_0FD0) },
2179   { "psrlw",            { MX, EM } },
2180   { "psrld",            { MX, EM } },
2181   { "psrlq",            { MX, EM } },
2182   { "paddq",            { MX, EM } },
2183   { "pmullw",           { MX, EM } },
2184   { PREFIX_TABLE (PREFIX_0FD6) },
2185   { MOD_TABLE (MOD_0FD7) },
2186   /* d8 */
2187   { "psubusb",          { MX, EM } },
2188   { "psubusw",          { MX, EM } },
2189   { "pminub",           { MX, EM } },
2190   { "pand",             { MX, EM } },
2191   { "paddusb",          { MX, EM } },
2192   { "paddusw",          { MX, EM } },
2193   { "pmaxub",           { MX, EM } },
2194   { "pandn",            { MX, EM } },
2195   /* e0 */
2196   { "pavgb",            { MX, EM } },
2197   { "psraw",            { MX, EM } },
2198   { "psrad",            { MX, EM } },
2199   { "pavgw",            { MX, EM } },
2200   { "pmulhuw",          { MX, EM } },
2201   { "pmulhw",           { MX, EM } },
2202   { PREFIX_TABLE (PREFIX_0FE6) },
2203   { PREFIX_TABLE (PREFIX_0FE7) },
2204   /* e8 */
2205   { "psubsb",           { MX, EM } },
2206   { "psubsw",           { MX, EM } },
2207   { "pminsw",           { MX, EM } },
2208   { "por",              { MX, EM } },
2209   { "paddsb",           { MX, EM } },
2210   { "paddsw",           { MX, EM } },
2211   { "pmaxsw",           { MX, EM } },
2212   { "pxor",             { MX, EM } },
2213   /* f0 */
2214   { PREFIX_TABLE (PREFIX_0FF0) },
2215   { "psllw",            { MX, EM } },
2216   { "pslld",            { MX, EM } },
2217   { "psllq",            { MX, EM } },
2218   { "pmuludq",          { MX, EM } },
2219   { "pmaddwd",          { MX, EM } },
2220   { "psadbw",           { MX, EM } },
2221   { PREFIX_TABLE (PREFIX_0FF7) },
2222   /* f8 */
2223   { "psubb",            { MX, EM } },
2224   { "psubw",            { MX, EM } },
2225   { "psubd",            { MX, EM } },
2226   { "psubq",            { MX, EM } },
2227   { "paddb",            { MX, EM } },
2228   { "paddw",            { MX, EM } },
2229   { "paddd",            { MX, EM } },
2230   { Bad_Opcode },
2231 };
2232
2233 static const unsigned char onebyte_has_modrm[256] = {
2234   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2235   /*       -------------------------------        */
2236   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2237   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2238   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2239   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2240   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2241   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2242   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2243   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2244   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2245   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2246   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2247   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2248   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2249   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2250   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2251   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2252   /*       -------------------------------        */
2253   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2254 };
2255
2256 static const unsigned char twobyte_has_modrm[256] = {
2257   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2258   /*       -------------------------------        */
2259   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2260   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2261   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2262   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2263   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2264   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2265   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2266   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2267   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2268   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2269   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2270   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2271   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2272   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2273   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2274   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2275   /*       -------------------------------        */
2276   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2277 };
2278
2279 static char obuf[100];
2280 static char *obufp;
2281 static char *mnemonicendp;
2282 static char scratchbuf[100];
2283 static unsigned char *start_codep;
2284 static unsigned char *insn_codep;
2285 static unsigned char *codep;
2286 static int last_lock_prefix;
2287 static int last_repz_prefix;
2288 static int last_repnz_prefix;
2289 static int last_data_prefix;
2290 static int last_addr_prefix;
2291 static int last_rex_prefix;
2292 static int last_seg_prefix;
2293 #define MAX_CODE_LENGTH 15
2294 /* We can up to 14 prefixes since the maximum instruction length is
2295    15bytes.  */
2296 static int all_prefixes[MAX_CODE_LENGTH - 1];
2297 static disassemble_info *the_info;
2298 static struct
2299   {
2300     int mod;
2301     int reg;
2302     int rm;
2303   }
2304 modrm;
2305 static unsigned char need_modrm;
2306 static struct
2307   {
2308     int scale;
2309     int index;
2310     int base;
2311   }
2312 sib;
2313 static struct
2314   {
2315     int register_specifier;
2316     int length;
2317     int prefix;
2318     int w;
2319   }
2320 vex;
2321 static unsigned char need_vex;
2322 static unsigned char need_vex_reg;
2323 static unsigned char vex_w_done;
2324
2325 struct op
2326   {
2327     const char *name;
2328     unsigned int len;
2329   };
2330
2331 /* If we are accessing mod/rm/reg without need_modrm set, then the
2332    values are stale.  Hitting this abort likely indicates that you
2333    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2334 #define MODRM_CHECK  if (!need_modrm) abort ()
2335
2336 static const char **names64;
2337 static const char **names32;
2338 static const char **names16;
2339 static const char **names8;
2340 static const char **names8rex;
2341 static const char **names_seg;
2342 static const char *index64;
2343 static const char *index32;
2344 static const char **index16;
2345
2346 static const char *intel_names64[] = {
2347   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2348   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2349 };
2350 static const char *intel_names32[] = {
2351   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2352   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2353 };
2354 static const char *intel_names16[] = {
2355   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2356   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2357 };
2358 static const char *intel_names8[] = {
2359   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2360 };
2361 static const char *intel_names8rex[] = {
2362   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2363   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2364 };
2365 static const char *intel_names_seg[] = {
2366   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2367 };
2368 static const char *intel_index64 = "riz";
2369 static const char *intel_index32 = "eiz";
2370 static const char *intel_index16[] = {
2371   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2372 };
2373
2374 static const char *att_names64[] = {
2375   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2376   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2377 };
2378 static const char *att_names32[] = {
2379   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2380   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2381 };
2382 static const char *att_names16[] = {
2383   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2384   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2385 };
2386 static const char *att_names8[] = {
2387   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2388 };
2389 static const char *att_names8rex[] = {
2390   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2391   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2392 };
2393 static const char *att_names_seg[] = {
2394   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2395 };
2396 static const char *att_index64 = "%riz";
2397 static const char *att_index32 = "%eiz";
2398 static const char *att_index16[] = {
2399   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2400 };
2401
2402 static const char **names_mm;
2403 static const char *intel_names_mm[] = {
2404   "mm0", "mm1", "mm2", "mm3",
2405   "mm4", "mm5", "mm6", "mm7"
2406 };
2407 static const char *att_names_mm[] = {
2408   "%mm0", "%mm1", "%mm2", "%mm3",
2409   "%mm4", "%mm5", "%mm6", "%mm7"
2410 };
2411
2412 static const char **names_xmm;
2413 static const char *intel_names_xmm[] = {
2414   "xmm0", "xmm1", "xmm2", "xmm3",
2415   "xmm4", "xmm5", "xmm6", "xmm7",
2416   "xmm8", "xmm9", "xmm10", "xmm11",
2417   "xmm12", "xmm13", "xmm14", "xmm15"
2418 };
2419 static const char *att_names_xmm[] = {
2420   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2421   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2422   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2423   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2424 };
2425
2426 static const char **names_ymm;
2427 static const char *intel_names_ymm[] = {
2428   "ymm0", "ymm1", "ymm2", "ymm3",
2429   "ymm4", "ymm5", "ymm6", "ymm7",
2430   "ymm8", "ymm9", "ymm10", "ymm11",
2431   "ymm12", "ymm13", "ymm14", "ymm15"
2432 };
2433 static const char *att_names_ymm[] = {
2434   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2435   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2436   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2437   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2438 };
2439
2440 static const struct dis386 reg_table[][8] = {
2441   /* REG_80 */
2442   {
2443     { "addA",   { Eb, Ib } },
2444     { "orA",    { Eb, Ib } },
2445     { "adcA",   { Eb, Ib } },
2446     { "sbbA",   { Eb, Ib } },
2447     { "andA",   { Eb, Ib } },
2448     { "subA",   { Eb, Ib } },
2449     { "xorA",   { Eb, Ib } },
2450     { "cmpA",   { Eb, Ib } },
2451   },
2452   /* REG_81 */
2453   {
2454     { "addQ",   { Ev, Iv } },
2455     { "orQ",    { Ev, Iv } },
2456     { "adcQ",   { Ev, Iv } },
2457     { "sbbQ",   { Ev, Iv } },
2458     { "andQ",   { Ev, Iv } },
2459     { "subQ",   { Ev, Iv } },
2460     { "xorQ",   { Ev, Iv } },
2461     { "cmpQ",   { Ev, Iv } },
2462   },
2463   /* REG_82 */
2464   {
2465     { "addQ",   { Ev, sIb } },
2466     { "orQ",    { Ev, sIb } },
2467     { "adcQ",   { Ev, sIb } },
2468     { "sbbQ",   { Ev, sIb } },
2469     { "andQ",   { Ev, sIb } },
2470     { "subQ",   { Ev, sIb } },
2471     { "xorQ",   { Ev, sIb } },
2472     { "cmpQ",   { Ev, sIb } },
2473   },
2474   /* REG_8F */
2475   {
2476     { "popU",   { stackEv } },
2477     { XOP_8F_TABLE (XOP_09) },
2478     { Bad_Opcode },
2479     { Bad_Opcode },
2480     { Bad_Opcode },
2481     { XOP_8F_TABLE (XOP_09) },
2482   },
2483   /* REG_C0 */
2484   {
2485     { "rolA",   { Eb, Ib } },
2486     { "rorA",   { Eb, Ib } },
2487     { "rclA",   { Eb, Ib } },
2488     { "rcrA",   { Eb, Ib } },
2489     { "shlA",   { Eb, Ib } },
2490     { "shrA",   { Eb, Ib } },
2491     { Bad_Opcode },
2492     { "sarA",   { Eb, Ib } },
2493   },
2494   /* REG_C1 */
2495   {
2496     { "rolQ",   { Ev, Ib } },
2497     { "rorQ",   { Ev, Ib } },
2498     { "rclQ",   { Ev, Ib } },
2499     { "rcrQ",   { Ev, Ib } },
2500     { "shlQ",   { Ev, Ib } },
2501     { "shrQ",   { Ev, Ib } },
2502     { Bad_Opcode },
2503     { "sarQ",   { Ev, Ib } },
2504   },
2505   /* REG_C6 */
2506   {
2507     { "movA",   { Eb, Ib } },
2508   },
2509   /* REG_C7 */
2510   {
2511     { "movQ",   { Ev, Iv } },
2512   },
2513   /* REG_D0 */
2514   {
2515     { "rolA",   { Eb, I1 } },
2516     { "rorA",   { Eb, I1 } },
2517     { "rclA",   { Eb, I1 } },
2518     { "rcrA",   { Eb, I1 } },
2519     { "shlA",   { Eb, I1 } },
2520     { "shrA",   { Eb, I1 } },
2521     { Bad_Opcode },
2522     { "sarA",   { Eb, I1 } },
2523   },
2524   /* REG_D1 */
2525   {
2526     { "rolQ",   { Ev, I1 } },
2527     { "rorQ",   { Ev, I1 } },
2528     { "rclQ",   { Ev, I1 } },
2529     { "rcrQ",   { Ev, I1 } },
2530     { "shlQ",   { Ev, I1 } },
2531     { "shrQ",   { Ev, I1 } },
2532     { Bad_Opcode },
2533     { "sarQ",   { Ev, I1 } },
2534   },
2535   /* REG_D2 */
2536   {
2537     { "rolA",   { Eb, CL } },
2538     { "rorA",   { Eb, CL } },
2539     { "rclA",   { Eb, CL } },
2540     { "rcrA",   { Eb, CL } },
2541     { "shlA",   { Eb, CL } },
2542     { "shrA",   { Eb, CL } },
2543     { Bad_Opcode },
2544     { "sarA",   { Eb, CL } },
2545   },
2546   /* REG_D3 */
2547   {
2548     { "rolQ",   { Ev, CL } },
2549     { "rorQ",   { Ev, CL } },
2550     { "rclQ",   { Ev, CL } },
2551     { "rcrQ",   { Ev, CL } },
2552     { "shlQ",   { Ev, CL } },
2553     { "shrQ",   { Ev, CL } },
2554     { Bad_Opcode },
2555     { "sarQ",   { Ev, CL } },
2556   },
2557   /* REG_F6 */
2558   {
2559     { "testA",  { Eb, Ib } },
2560     { Bad_Opcode },
2561     { "notA",   { Eb } },
2562     { "negA",   { Eb } },
2563     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2564     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2565     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2566     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2567   },
2568   /* REG_F7 */
2569   {
2570     { "testQ",  { Ev, Iv } },
2571     { Bad_Opcode },
2572     { "notQ",   { Ev } },
2573     { "negQ",   { Ev } },
2574     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2575     { "imulQ",  { Ev } },
2576     { "divQ",   { Ev } },
2577     { "idivQ",  { Ev } },
2578   },
2579   /* REG_FE */
2580   {
2581     { "incA",   { Eb } },
2582     { "decA",   { Eb } },
2583   },
2584   /* REG_FF */
2585   {
2586     { "incQ",   { Ev } },
2587     { "decQ",   { Ev } },
2588     { "callT",  { indirEv } },
2589     { "JcallT", { indirEp } },
2590     { "jmpT",   { indirEv } },
2591     { "JjmpT",  { indirEp } },
2592     { "pushU",  { stackEv } },
2593     { Bad_Opcode },
2594   },
2595   /* REG_0F00 */
2596   {
2597     { "sldtD",  { Sv } },
2598     { "strD",   { Sv } },
2599     { "lldt",   { Ew } },
2600     { "ltr",    { Ew } },
2601     { "verr",   { Ew } },
2602     { "verw",   { Ew } },
2603     { Bad_Opcode },
2604     { Bad_Opcode },
2605   },
2606   /* REG_0F01 */
2607   {
2608     { MOD_TABLE (MOD_0F01_REG_0) },
2609     { MOD_TABLE (MOD_0F01_REG_1) },
2610     { MOD_TABLE (MOD_0F01_REG_2) },
2611     { MOD_TABLE (MOD_0F01_REG_3) },
2612     { "smswD",  { Sv } },
2613     { Bad_Opcode },
2614     { "lmsw",   { Ew } },
2615     { MOD_TABLE (MOD_0F01_REG_7) },
2616   },
2617   /* REG_0F0D */
2618   {
2619     { "prefetch",       { Eb } },
2620     { "prefetchw",      { Eb } },
2621   },
2622   /* REG_0F18 */
2623   {
2624     { MOD_TABLE (MOD_0F18_REG_0) },
2625     { MOD_TABLE (MOD_0F18_REG_1) },
2626     { MOD_TABLE (MOD_0F18_REG_2) },
2627     { MOD_TABLE (MOD_0F18_REG_3) },
2628   },
2629   /* REG_0F71 */
2630   {
2631     { Bad_Opcode },
2632     { Bad_Opcode },
2633     { MOD_TABLE (MOD_0F71_REG_2) },
2634     { Bad_Opcode },
2635     { MOD_TABLE (MOD_0F71_REG_4) },
2636     { Bad_Opcode },
2637     { MOD_TABLE (MOD_0F71_REG_6) },
2638   },
2639   /* REG_0F72 */
2640   {
2641     { Bad_Opcode },
2642     { Bad_Opcode },
2643     { MOD_TABLE (MOD_0F72_REG_2) },
2644     { Bad_Opcode },
2645     { MOD_TABLE (MOD_0F72_REG_4) },
2646     { Bad_Opcode },
2647     { MOD_TABLE (MOD_0F72_REG_6) },
2648   },
2649   /* REG_0F73 */
2650   {
2651     { Bad_Opcode },
2652     { Bad_Opcode },
2653     { MOD_TABLE (MOD_0F73_REG_2) },
2654     { MOD_TABLE (MOD_0F73_REG_3) },
2655     { Bad_Opcode },
2656     { Bad_Opcode },
2657     { MOD_TABLE (MOD_0F73_REG_6) },
2658     { MOD_TABLE (MOD_0F73_REG_7) },
2659   },
2660   /* REG_0FA6 */
2661   {
2662     { "montmul",        { { OP_0f07, 0 } } },
2663     { "xsha1",          { { OP_0f07, 0 } } },
2664     { "xsha256",        { { OP_0f07, 0 } } },
2665   },
2666   /* REG_0FA7 */
2667   {
2668     { "xstore-rng",     { { OP_0f07, 0 } } },
2669     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2670     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2671     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2672     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2673     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2674   },
2675   /* REG_0FAE */
2676   {
2677     { MOD_TABLE (MOD_0FAE_REG_0) },
2678     { MOD_TABLE (MOD_0FAE_REG_1) },
2679     { MOD_TABLE (MOD_0FAE_REG_2) },
2680     { MOD_TABLE (MOD_0FAE_REG_3) },
2681     { MOD_TABLE (MOD_0FAE_REG_4) },
2682     { MOD_TABLE (MOD_0FAE_REG_5) },
2683     { MOD_TABLE (MOD_0FAE_REG_6) },
2684     { MOD_TABLE (MOD_0FAE_REG_7) },
2685   },
2686   /* REG_0FBA */
2687   {
2688     { Bad_Opcode },
2689     { Bad_Opcode },
2690     { Bad_Opcode },
2691     { Bad_Opcode },
2692     { "btQ",    { Ev, Ib } },
2693     { "btsQ",   { Ev, Ib } },
2694     { "btrQ",   { Ev, Ib } },
2695     { "btcQ",   { Ev, Ib } },
2696   },
2697   /* REG_0FC7 */
2698   {
2699     { Bad_Opcode },
2700     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2701     { Bad_Opcode },
2702     { Bad_Opcode },
2703     { Bad_Opcode },
2704     { Bad_Opcode },
2705     { MOD_TABLE (MOD_0FC7_REG_6) },
2706     { MOD_TABLE (MOD_0FC7_REG_7) },
2707   },
2708   /* REG_VEX_71 */
2709   {
2710     { Bad_Opcode },
2711     { Bad_Opcode },
2712     { MOD_TABLE (MOD_VEX_71_REG_2) },
2713     { Bad_Opcode },
2714     { MOD_TABLE (MOD_VEX_71_REG_4) },
2715     { Bad_Opcode },
2716     { MOD_TABLE (MOD_VEX_71_REG_6) },
2717   },
2718   /* REG_VEX_72 */
2719   {
2720     { Bad_Opcode },
2721     { Bad_Opcode },
2722     { MOD_TABLE (MOD_VEX_72_REG_2) },
2723     { Bad_Opcode },
2724     { MOD_TABLE (MOD_VEX_72_REG_4) },
2725     { Bad_Opcode },
2726     { MOD_TABLE (MOD_VEX_72_REG_6) },
2727   },
2728   /* REG_VEX_73 */
2729   {
2730     { Bad_Opcode },
2731     { Bad_Opcode },
2732     { MOD_TABLE (MOD_VEX_73_REG_2) },
2733     { MOD_TABLE (MOD_VEX_73_REG_3) },
2734     { Bad_Opcode },
2735     { Bad_Opcode },
2736     { MOD_TABLE (MOD_VEX_73_REG_6) },
2737     { MOD_TABLE (MOD_VEX_73_REG_7) },
2738   },
2739   /* REG_VEX_AE */
2740   {
2741     { Bad_Opcode },
2742     { Bad_Opcode },
2743     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2744     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2745   },
2746   /* REG_XOP_LWPCB */
2747   {
2748     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2749     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2750   },
2751   /* REG_XOP_LWP */
2752   {
2753     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2754     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2755   },
2756 };
2757
2758 static const struct dis386 prefix_table[][4] = {
2759   /* PREFIX_90 */
2760   {
2761     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2762     { "pause", { XX } },
2763     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2764   },
2765
2766   /* PREFIX_0F10 */
2767   {
2768     { "movups", { XM, EXx } },
2769     { "movss",  { XM, EXd } },
2770     { "movupd", { XM, EXx } },
2771     { "movsd",  { XM, EXq } },
2772   },
2773
2774   /* PREFIX_0F11 */
2775   {
2776     { "movups", { EXxS, XM } },
2777     { "movss",  { EXdS, XM } },
2778     { "movupd", { EXxS, XM } },
2779     { "movsd",  { EXqS, XM } },
2780   },
2781
2782   /* PREFIX_0F12 */
2783   {
2784     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2785     { "movsldup", { XM, EXx } },
2786     { "movlpd", { XM, EXq } },
2787     { "movddup", { XM, EXq } },
2788   },
2789
2790   /* PREFIX_0F16 */
2791   {
2792     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2793     { "movshdup", { XM, EXx } },
2794     { "movhpd", { XM, EXq } },
2795   },
2796
2797   /* PREFIX_0F2A */
2798   {
2799     { "cvtpi2ps", { XM, EMCq } },
2800     { "cvtsi2ss%LQ", { XM, Ev } },
2801     { "cvtpi2pd", { XM, EMCq } },
2802     { "cvtsi2sd%LQ", { XM, Ev } },
2803   },
2804
2805   /* PREFIX_0F2B */
2806   {
2807     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2808     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2809     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2810     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2811   },
2812
2813   /* PREFIX_0F2C */
2814   {
2815     { "cvttps2pi", { MXC, EXq } },
2816     { "cvttss2siY", { Gv, EXd } },
2817     { "cvttpd2pi", { MXC, EXx } },
2818     { "cvttsd2siY", { Gv, EXq } },
2819   },
2820
2821   /* PREFIX_0F2D */
2822   {
2823     { "cvtps2pi", { MXC, EXq } },
2824     { "cvtss2siY", { Gv, EXd } },
2825     { "cvtpd2pi", { MXC, EXx } },
2826     { "cvtsd2siY", { Gv, EXq } },
2827   },
2828
2829   /* PREFIX_0F2E */
2830   {
2831     { "ucomiss",{ XM, EXd } },
2832     { Bad_Opcode },
2833     { "ucomisd",{ XM, EXq } },
2834   },
2835
2836   /* PREFIX_0F2F */
2837   {
2838     { "comiss", { XM, EXd } },
2839     { Bad_Opcode },
2840     { "comisd", { XM, EXq } },
2841   },
2842
2843   /* PREFIX_0F51 */
2844   {
2845     { "sqrtps", { XM, EXx } },
2846     { "sqrtss", { XM, EXd } },
2847     { "sqrtpd", { XM, EXx } },
2848     { "sqrtsd", { XM, EXq } },
2849   },
2850
2851   /* PREFIX_0F52 */
2852   {
2853     { "rsqrtps",{ XM, EXx } },
2854     { "rsqrtss",{ XM, EXd } },
2855   },
2856
2857   /* PREFIX_0F53 */
2858   {
2859     { "rcpps",  { XM, EXx } },
2860     { "rcpss",  { XM, EXd } },
2861   },
2862
2863   /* PREFIX_0F58 */
2864   {
2865     { "addps", { XM, EXx } },
2866     { "addss", { XM, EXd } },
2867     { "addpd", { XM, EXx } },
2868     { "addsd", { XM, EXq } },
2869   },
2870
2871   /* PREFIX_0F59 */
2872   {
2873     { "mulps",  { XM, EXx } },
2874     { "mulss",  { XM, EXd } },
2875     { "mulpd",  { XM, EXx } },
2876     { "mulsd",  { XM, EXq } },
2877   },
2878
2879   /* PREFIX_0F5A */
2880   {
2881     { "cvtps2pd", { XM, EXq } },
2882     { "cvtss2sd", { XM, EXd } },
2883     { "cvtpd2ps", { XM, EXx } },
2884     { "cvtsd2ss", { XM, EXq } },
2885   },
2886
2887   /* PREFIX_0F5B */
2888   {
2889     { "cvtdq2ps", { XM, EXx } },
2890     { "cvttps2dq", { XM, EXx } },
2891     { "cvtps2dq", { XM, EXx } },
2892   },
2893
2894   /* PREFIX_0F5C */
2895   {
2896     { "subps",  { XM, EXx } },
2897     { "subss",  { XM, EXd } },
2898     { "subpd",  { XM, EXx } },
2899     { "subsd",  { XM, EXq } },
2900   },
2901
2902   /* PREFIX_0F5D */
2903   {
2904     { "minps",  { XM, EXx } },
2905     { "minss",  { XM, EXd } },
2906     { "minpd",  { XM, EXx } },
2907     { "minsd",  { XM, EXq } },
2908   },
2909
2910   /* PREFIX_0F5E */
2911   {
2912     { "divps",  { XM, EXx } },
2913     { "divss",  { XM, EXd } },
2914     { "divpd",  { XM, EXx } },
2915     { "divsd",  { XM, EXq } },
2916   },
2917
2918   /* PREFIX_0F5F */
2919   {
2920     { "maxps",  { XM, EXx } },
2921     { "maxss",  { XM, EXd } },
2922     { "maxpd",  { XM, EXx } },
2923     { "maxsd",  { XM, EXq } },
2924   },
2925
2926   /* PREFIX_0F60 */
2927   {
2928     { "punpcklbw",{ MX, EMd } },
2929     { Bad_Opcode },
2930     { "punpcklbw",{ MX, EMx } },
2931   },
2932
2933   /* PREFIX_0F61 */
2934   {
2935     { "punpcklwd",{ MX, EMd } },
2936     { Bad_Opcode },
2937     { "punpcklwd",{ MX, EMx } },
2938   },
2939
2940   /* PREFIX_0F62 */
2941   {
2942     { "punpckldq",{ MX, EMd } },
2943     { Bad_Opcode },
2944     { "punpckldq",{ MX, EMx } },
2945   },
2946
2947   /* PREFIX_0F6C */
2948   {
2949     { Bad_Opcode },
2950     { Bad_Opcode },
2951     { "punpcklqdq", { XM, EXx } },
2952   },
2953
2954   /* PREFIX_0F6D */
2955   {
2956     { Bad_Opcode },
2957     { Bad_Opcode },
2958     { "punpckhqdq", { XM, EXx } },
2959   },
2960
2961   /* PREFIX_0F6F */
2962   {
2963     { "movq",   { MX, EM } },
2964     { "movdqu", { XM, EXx } },
2965     { "movdqa", { XM, EXx } },
2966   },
2967
2968   /* PREFIX_0F70 */
2969   {
2970     { "pshufw", { MX, EM, Ib } },
2971     { "pshufhw",{ XM, EXx, Ib } },
2972     { "pshufd", { XM, EXx, Ib } },
2973     { "pshuflw",{ XM, EXx, Ib } },
2974   },
2975
2976   /* PREFIX_0F73_REG_3 */
2977   {
2978     { Bad_Opcode },
2979     { Bad_Opcode },
2980     { "psrldq", { XS, Ib } },
2981   },
2982
2983   /* PREFIX_0F73_REG_7 */
2984   {
2985     { Bad_Opcode },
2986     { Bad_Opcode },
2987     { "pslldq", { XS, Ib } },
2988   },
2989
2990   /* PREFIX_0F78 */
2991   {
2992     {"vmread",  { Em, Gm } },
2993     { Bad_Opcode },
2994     {"extrq",   { XS, Ib, Ib } },
2995     {"insertq", { XM, XS, Ib, Ib } },
2996   },
2997
2998   /* PREFIX_0F79 */
2999   {
3000     {"vmwrite", { Gm, Em } },
3001     { Bad_Opcode },
3002     {"extrq",   { XM, XS } },
3003     {"insertq", { XM, XS } },
3004   },
3005
3006   /* PREFIX_0F7C */
3007   {
3008     { Bad_Opcode },
3009     { Bad_Opcode },
3010     { "haddpd", { XM, EXx } },
3011     { "haddps", { XM, EXx } },
3012   },
3013
3014   /* PREFIX_0F7D */
3015   {
3016     { Bad_Opcode },
3017     { Bad_Opcode },
3018     { "hsubpd", { XM, EXx } },
3019     { "hsubps", { XM, EXx } },
3020   },
3021
3022   /* PREFIX_0F7E */
3023   {
3024     { "movK",   { Edq, MX } },
3025     { "movq",   { XM, EXq } },
3026     { "movK",   { Edq, XM } },
3027   },
3028
3029   /* PREFIX_0F7F */
3030   {
3031     { "movq",   { EMS, MX } },
3032     { "movdqu", { EXxS, XM } },
3033     { "movdqa", { EXxS, XM } },
3034   },
3035
3036   /* PREFIX_0FB8 */
3037   {
3038     { Bad_Opcode },
3039     { "popcntS", { Gv, Ev } },
3040   },
3041
3042   /* PREFIX_0FBD */
3043   {
3044     { "bsrS",   { Gv, Ev } },
3045     { "lzcntS", { Gv, Ev } },
3046     { "bsrS",   { Gv, Ev } },
3047   },
3048
3049   /* PREFIX_0FC2 */
3050   {
3051     { "cmpps",  { XM, EXx, CMP } },
3052     { "cmpss",  { XM, EXd, CMP } },
3053     { "cmppd",  { XM, EXx, CMP } },
3054     { "cmpsd",  { XM, EXq, CMP } },
3055   },
3056
3057   /* PREFIX_0FC3 */
3058   {
3059     { "movntiS", { Ma, Gv } },
3060   },
3061
3062   /* PREFIX_0FC7_REG_6 */
3063   {
3064     { "vmptrld",{ Mq } },
3065     { "vmxon",  { Mq } },
3066     { "vmclear",{ Mq } },
3067   },
3068
3069   /* PREFIX_0FD0 */
3070   {
3071     { Bad_Opcode },
3072     { Bad_Opcode },
3073     { "addsubpd", { XM, EXx } },
3074     { "addsubps", { XM, EXx } },
3075   },
3076
3077   /* PREFIX_0FD6 */
3078   {
3079     { Bad_Opcode },
3080     { "movq2dq",{ XM, MS } },
3081     { "movq",   { EXqS, XM } },
3082     { "movdq2q",{ MX, XS } },
3083   },
3084
3085   /* PREFIX_0FE6 */
3086   {
3087     { Bad_Opcode },
3088     { "cvtdq2pd", { XM, EXq } },
3089     { "cvttpd2dq", { XM, EXx } },
3090     { "cvtpd2dq", { XM, EXx } },
3091   },
3092
3093   /* PREFIX_0FE7 */
3094   {
3095     { "movntq", { Mq, MX } },
3096     { Bad_Opcode },
3097     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3098   },
3099
3100   /* PREFIX_0FF0 */
3101   {
3102     { Bad_Opcode },
3103     { Bad_Opcode },
3104     { Bad_Opcode },
3105     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3106   },
3107
3108   /* PREFIX_0FF7 */
3109   {
3110     { "maskmovq", { MX, MS } },
3111     { Bad_Opcode },
3112     { "maskmovdqu", { XM, XS } },
3113   },
3114
3115   /* PREFIX_0F3810 */
3116   {
3117     { Bad_Opcode },
3118     { Bad_Opcode },
3119     { "pblendvb", { XM, EXx, XMM0 } },
3120   },
3121
3122   /* PREFIX_0F3814 */
3123   {
3124     { Bad_Opcode },
3125     { Bad_Opcode },
3126     { "blendvps", { XM, EXx, XMM0 } },
3127   },
3128
3129   /* PREFIX_0F3815 */
3130   {
3131     { Bad_Opcode },
3132     { Bad_Opcode },
3133     { "blendvpd", { XM, EXx, XMM0 } },
3134   },
3135
3136   /* PREFIX_0F3817 */
3137   {
3138     { Bad_Opcode },
3139     { Bad_Opcode },
3140     { "ptest",  { XM, EXx } },
3141   },
3142
3143   /* PREFIX_0F3820 */
3144   {
3145     { Bad_Opcode },
3146     { Bad_Opcode },
3147     { "pmovsxbw", { XM, EXq } },
3148   },
3149
3150   /* PREFIX_0F3821 */
3151   {
3152     { Bad_Opcode },
3153     { Bad_Opcode },
3154     { "pmovsxbd", { XM, EXd } },
3155   },
3156
3157   /* PREFIX_0F3822 */
3158   {
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { "pmovsxbq", { XM, EXw } },
3162   },
3163
3164   /* PREFIX_0F3823 */
3165   {
3166     { Bad_Opcode },
3167     { Bad_Opcode },
3168     { "pmovsxwd", { XM, EXq } },
3169   },
3170
3171   /* PREFIX_0F3824 */
3172   {
3173     { Bad_Opcode },
3174     { Bad_Opcode },
3175     { "pmovsxwq", { XM, EXd } },
3176   },
3177
3178   /* PREFIX_0F3825 */
3179   {
3180     { Bad_Opcode },
3181     { Bad_Opcode },
3182     { "pmovsxdq", { XM, EXq } },
3183   },
3184
3185   /* PREFIX_0F3828 */
3186   {
3187     { Bad_Opcode },
3188     { Bad_Opcode },
3189     { "pmuldq", { XM, EXx } },
3190   },
3191
3192   /* PREFIX_0F3829 */
3193   {
3194     { Bad_Opcode },
3195     { Bad_Opcode },
3196     { "pcmpeqq", { XM, EXx } },
3197   },
3198
3199   /* PREFIX_0F382A */
3200   {
3201     { Bad_Opcode },
3202     { Bad_Opcode },
3203     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3204   },
3205
3206   /* PREFIX_0F382B */
3207   {
3208     { Bad_Opcode },
3209     { Bad_Opcode },
3210     { "packusdw", { XM, EXx } },
3211   },
3212
3213   /* PREFIX_0F3830 */
3214   {
3215     { Bad_Opcode },
3216     { Bad_Opcode },
3217     { "pmovzxbw", { XM, EXq } },
3218   },
3219
3220   /* PREFIX_0F3831 */
3221   {
3222     { Bad_Opcode },
3223     { Bad_Opcode },
3224     { "pmovzxbd", { XM, EXd } },
3225   },
3226
3227   /* PREFIX_0F3832 */
3228   {
3229     { Bad_Opcode },
3230     { Bad_Opcode },
3231     { "pmovzxbq", { XM, EXw } },
3232   },
3233
3234   /* PREFIX_0F3833 */
3235   {
3236     { Bad_Opcode },
3237     { Bad_Opcode },
3238     { "pmovzxwd", { XM, EXq } },
3239   },
3240
3241   /* PREFIX_0F3834 */
3242   {
3243     { Bad_Opcode },
3244     { Bad_Opcode },
3245     { "pmovzxwq", { XM, EXd } },
3246   },
3247
3248   /* PREFIX_0F3835 */
3249   {
3250     { Bad_Opcode },
3251     { Bad_Opcode },
3252     { "pmovzxdq", { XM, EXq } },
3253   },
3254
3255   /* PREFIX_0F3837 */
3256   {
3257     { Bad_Opcode },
3258     { Bad_Opcode },
3259     { "pcmpgtq", { XM, EXx } },
3260   },
3261
3262   /* PREFIX_0F3838 */
3263   {
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266     { "pminsb", { XM, EXx } },
3267   },
3268
3269   /* PREFIX_0F3839 */
3270   {
3271     { Bad_Opcode },
3272     { Bad_Opcode },
3273     { "pminsd", { XM, EXx } },
3274   },
3275
3276   /* PREFIX_0F383A */
3277   {
3278     { Bad_Opcode },
3279     { Bad_Opcode },
3280     { "pminuw", { XM, EXx } },
3281   },
3282
3283   /* PREFIX_0F383B */
3284   {
3285     { Bad_Opcode },
3286     { Bad_Opcode },
3287     { "pminud", { XM, EXx } },
3288   },
3289
3290   /* PREFIX_0F383C */
3291   {
3292     { Bad_Opcode },
3293     { Bad_Opcode },
3294     { "pmaxsb", { XM, EXx } },
3295   },
3296
3297   /* PREFIX_0F383D */
3298   {
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { "pmaxsd", { XM, EXx } },
3302   },
3303
3304   /* PREFIX_0F383E */
3305   {
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { "pmaxuw", { XM, EXx } },
3309   },
3310
3311   /* PREFIX_0F383F */
3312   {
3313     { Bad_Opcode },
3314     { Bad_Opcode },
3315     { "pmaxud", { XM, EXx } },
3316   },
3317
3318   /* PREFIX_0F3840 */
3319   {
3320     { Bad_Opcode },
3321     { Bad_Opcode },
3322     { "pmulld", { XM, EXx } },
3323   },
3324
3325   /* PREFIX_0F3841 */
3326   {
3327     { Bad_Opcode },
3328     { Bad_Opcode },
3329     { "phminposuw", { XM, EXx } },
3330   },
3331
3332   /* PREFIX_0F3880 */
3333   {
3334     { Bad_Opcode },
3335     { Bad_Opcode },
3336     { "invept", { Gm, Mo } },
3337   },
3338
3339   /* PREFIX_0F3881 */
3340   {
3341     { Bad_Opcode },
3342     { Bad_Opcode },
3343     { "invvpid", { Gm, Mo } },
3344   },
3345
3346   /* PREFIX_0F38DB */
3347   {
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { "aesimc", { XM, EXx } },
3351   },
3352
3353   /* PREFIX_0F38DC */
3354   {
3355     { Bad_Opcode },
3356     { Bad_Opcode },
3357     { "aesenc", { XM, EXx } },
3358   },
3359
3360   /* PREFIX_0F38DD */
3361   {
3362     { Bad_Opcode },
3363     { Bad_Opcode },
3364     { "aesenclast", { XM, EXx } },
3365   },
3366
3367   /* PREFIX_0F38DE */
3368   {
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { "aesdec", { XM, EXx } },
3372   },
3373
3374   /* PREFIX_0F38DF */
3375   {
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { "aesdeclast", { XM, EXx } },
3379   },
3380
3381   /* PREFIX_0F38F0 */
3382   {
3383     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3384     { Bad_Opcode },
3385     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3386     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3387   },
3388
3389   /* PREFIX_0F38F1 */
3390   {
3391     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3392     { Bad_Opcode },
3393     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3394     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3395   },
3396
3397   /* PREFIX_0F3A08 */
3398   {
3399     { Bad_Opcode },
3400     { Bad_Opcode },
3401     { "roundps", { XM, EXx, Ib } },
3402   },
3403
3404   /* PREFIX_0F3A09 */
3405   {
3406     { Bad_Opcode },
3407     { Bad_Opcode },
3408     { "roundpd", { XM, EXx, Ib } },
3409   },
3410
3411   /* PREFIX_0F3A0A */
3412   {
3413     { Bad_Opcode },
3414     { Bad_Opcode },
3415     { "roundss", { XM, EXd, Ib } },
3416   },
3417
3418   /* PREFIX_0F3A0B */
3419   {
3420     { Bad_Opcode },
3421     { Bad_Opcode },
3422     { "roundsd", { XM, EXq, Ib } },
3423   },
3424
3425   /* PREFIX_0F3A0C */
3426   {
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { "blendps", { XM, EXx, Ib } },
3430   },
3431
3432   /* PREFIX_0F3A0D */
3433   {
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { "blendpd", { XM, EXx, Ib } },
3437   },
3438
3439   /* PREFIX_0F3A0E */
3440   {
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { "pblendw", { XM, EXx, Ib } },
3444   },
3445
3446   /* PREFIX_0F3A14 */
3447   {
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { "pextrb", { Edqb, XM, Ib } },
3451   },
3452
3453   /* PREFIX_0F3A15 */
3454   {
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { "pextrw", { Edqw, XM, Ib } },
3458   },
3459
3460   /* PREFIX_0F3A16 */
3461   {
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { "pextrK", { Edq, XM, Ib } },
3465   },
3466
3467   /* PREFIX_0F3A17 */
3468   {
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { "extractps", { Edqd, XM, Ib } },
3472   },
3473
3474   /* PREFIX_0F3A20 */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { "pinsrb", { XM, Edqb, Ib } },
3479   },
3480
3481   /* PREFIX_0F3A21 */
3482   {
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { "insertps", { XM, EXd, Ib } },
3486   },
3487
3488   /* PREFIX_0F3A22 */
3489   {
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { "pinsrK", { XM, Edq, Ib } },
3493   },
3494
3495   /* PREFIX_0F3A40 */
3496   {
3497     { Bad_Opcode },
3498     { Bad_Opcode },
3499     { "dpps",   { XM, EXx, Ib } },
3500   },
3501
3502   /* PREFIX_0F3A41 */
3503   {
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { "dppd",   { XM, EXx, Ib } },
3507   },
3508
3509   /* PREFIX_0F3A42 */
3510   {
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { "mpsadbw", { XM, EXx, Ib } },
3514   },
3515
3516   /* PREFIX_0F3A44 */
3517   {
3518     { Bad_Opcode },
3519     { Bad_Opcode },
3520     { "pclmulqdq", { XM, EXx, PCLMUL } },
3521   },
3522
3523   /* PREFIX_0F3A60 */
3524   {
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { "pcmpestrm", { XM, EXx, Ib } },
3528   },
3529
3530   /* PREFIX_0F3A61 */
3531   {
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { "pcmpestri", { XM, EXx, Ib } },
3535   },
3536
3537   /* PREFIX_0F3A62 */
3538   {
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { "pcmpistrm", { XM, EXx, Ib } },
3542   },
3543
3544   /* PREFIX_0F3A63 */
3545   {
3546     { Bad_Opcode },
3547     { Bad_Opcode },
3548     { "pcmpistri", { XM, EXx, Ib } },
3549   },
3550
3551   /* PREFIX_0F3ADF */
3552   {
3553     { Bad_Opcode },
3554     { Bad_Opcode },
3555     { "aeskeygenassist", { XM, EXx, Ib } },
3556   },
3557
3558   /* PREFIX_VEX_10 */
3559   {
3560     { VEX_W_TABLE (VEX_W_10_P_0) },
3561     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3562     { VEX_W_TABLE (VEX_W_10_P_2) },
3563     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3564   },
3565
3566   /* PREFIX_VEX_11 */
3567   {
3568     { VEX_W_TABLE (VEX_W_11_P_0) },
3569     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3570     { VEX_W_TABLE (VEX_W_11_P_2) },
3571     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3572   },
3573
3574   /* PREFIX_VEX_12 */
3575   {
3576     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3577     { VEX_W_TABLE (VEX_W_12_P_1) },
3578     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3579     { VEX_W_TABLE (VEX_W_12_P_3) },
3580   },
3581
3582   /* PREFIX_VEX_16 */
3583   {
3584     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3585     { VEX_W_TABLE (VEX_W_16_P_1) },
3586     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3587   },
3588
3589   /* PREFIX_VEX_2A */
3590   {
3591     { Bad_Opcode },
3592     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3593     { Bad_Opcode },
3594     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3595   },
3596
3597   /* PREFIX_VEX_2C */
3598   {
3599     { Bad_Opcode },
3600     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3601     { Bad_Opcode },
3602     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3603   },
3604
3605   /* PREFIX_VEX_2D */
3606   {
3607     { Bad_Opcode },
3608     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3609     { Bad_Opcode },
3610     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3611   },
3612
3613   /* PREFIX_VEX_2E */
3614   {
3615     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3616     { Bad_Opcode },
3617     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3618   },
3619
3620   /* PREFIX_VEX_2F */
3621   {
3622     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3623     { Bad_Opcode },
3624     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3625   },
3626
3627   /* PREFIX_VEX_51 */
3628   {
3629     { VEX_W_TABLE (VEX_W_51_P_0) },
3630     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3631     { VEX_W_TABLE (VEX_W_51_P_2) },
3632     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3633   },
3634
3635   /* PREFIX_VEX_52 */
3636   {
3637     { VEX_W_TABLE (VEX_W_52_P_0) },
3638     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3639   },
3640
3641   /* PREFIX_VEX_53 */
3642   {
3643     { VEX_W_TABLE (VEX_W_53_P_0) },
3644     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3645   },
3646
3647   /* PREFIX_VEX_58 */
3648   {
3649     { VEX_W_TABLE (VEX_W_58_P_0) },
3650     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3651     { VEX_W_TABLE (VEX_W_58_P_2) },
3652     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3653   },
3654
3655   /* PREFIX_VEX_59 */
3656   {
3657     { VEX_W_TABLE (VEX_W_59_P_0) },
3658     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3659     { VEX_W_TABLE (VEX_W_59_P_2) },
3660     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3661   },
3662
3663   /* PREFIX_VEX_5A */
3664   {
3665     { VEX_W_TABLE (VEX_W_5A_P_0) },
3666     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3667     { "vcvtpd2ps%XY", { XMM, EXx } },
3668     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3669   },
3670
3671   /* PREFIX_VEX_5B */
3672   {
3673     { VEX_W_TABLE (VEX_W_5B_P_0) },
3674     { VEX_W_TABLE (VEX_W_5B_P_1) },
3675     { VEX_W_TABLE (VEX_W_5B_P_2) },
3676   },
3677
3678   /* PREFIX_VEX_5C */
3679   {
3680     { VEX_W_TABLE (VEX_W_5C_P_0) },
3681     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3682     { VEX_W_TABLE (VEX_W_5C_P_2) },
3683     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3684   },
3685
3686   /* PREFIX_VEX_5D */
3687   {
3688     { VEX_W_TABLE (VEX_W_5D_P_0) },
3689     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3690     { VEX_W_TABLE (VEX_W_5D_P_2) },
3691     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3692   },
3693
3694   /* PREFIX_VEX_5E */
3695   {
3696     { VEX_W_TABLE (VEX_W_5E_P_0) },
3697     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3698     { VEX_W_TABLE (VEX_W_5E_P_2) },
3699     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3700   },
3701
3702   /* PREFIX_VEX_5F */
3703   {
3704     { VEX_W_TABLE (VEX_W_5F_P_0) },
3705     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3706     { VEX_W_TABLE (VEX_W_5F_P_2) },
3707     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3708   },
3709
3710   /* PREFIX_VEX_60 */
3711   {
3712     { Bad_Opcode },
3713     { Bad_Opcode },
3714     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3715   },
3716
3717   /* PREFIX_VEX_61 */
3718   {
3719     { Bad_Opcode },
3720     { Bad_Opcode },
3721     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3722   },
3723
3724   /* PREFIX_VEX_62 */
3725   {
3726     { Bad_Opcode },
3727     { Bad_Opcode },
3728     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3729   },
3730
3731   /* PREFIX_VEX_63 */
3732   {
3733     { Bad_Opcode },
3734     { Bad_Opcode },
3735     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3736   },
3737
3738   /* PREFIX_VEX_64 */
3739   {
3740     { Bad_Opcode },
3741     { Bad_Opcode },
3742     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3743   },
3744
3745   /* PREFIX_VEX_65 */
3746   {
3747     { Bad_Opcode },
3748     { Bad_Opcode },
3749     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3750   },
3751
3752   /* PREFIX_VEX_66 */
3753   {
3754     { Bad_Opcode },
3755     { Bad_Opcode },
3756     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3757   },
3758
3759   /* PREFIX_VEX_67 */
3760   {
3761     { Bad_Opcode },
3762     { Bad_Opcode },
3763     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3764   },
3765
3766   /* PREFIX_VEX_68 */
3767   {
3768     { Bad_Opcode },
3769     { Bad_Opcode },
3770     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3771   },
3772
3773   /* PREFIX_VEX_69 */
3774   {
3775     { Bad_Opcode },
3776     { Bad_Opcode },
3777     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3778   },
3779
3780   /* PREFIX_VEX_6A */
3781   {
3782     { Bad_Opcode },
3783     { Bad_Opcode },
3784     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3785   },
3786
3787   /* PREFIX_VEX_6B */
3788   {
3789     { Bad_Opcode },
3790     { Bad_Opcode },
3791     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3792   },
3793
3794   /* PREFIX_VEX_6C */
3795   {
3796     { Bad_Opcode },
3797     { Bad_Opcode },
3798     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3799   },
3800
3801   /* PREFIX_VEX_6D */
3802   {
3803     { Bad_Opcode },
3804     { Bad_Opcode },
3805     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3806   },
3807
3808   /* PREFIX_VEX_6E */
3809   {
3810     { Bad_Opcode },
3811     { Bad_Opcode },
3812     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3813   },
3814
3815   /* PREFIX_VEX_6F */
3816   {
3817     { Bad_Opcode },
3818     { VEX_W_TABLE (VEX_W_6F_P_1) },
3819     { VEX_W_TABLE (VEX_W_6F_P_2) },
3820   },
3821
3822   /* PREFIX_VEX_70 */
3823   {
3824     { Bad_Opcode },
3825     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3826     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3827     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3828   },
3829
3830   /* PREFIX_VEX_71_REG_2 */
3831   {
3832     { Bad_Opcode },
3833     { Bad_Opcode },
3834     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3835   },
3836
3837   /* PREFIX_VEX_71_REG_4 */
3838   {
3839     { Bad_Opcode },
3840     { Bad_Opcode },
3841     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3842   },
3843
3844   /* PREFIX_VEX_71_REG_6 */
3845   {
3846     { Bad_Opcode },
3847     { Bad_Opcode },
3848     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3849   },
3850
3851   /* PREFIX_VEX_72_REG_2 */
3852   {
3853     { Bad_Opcode },
3854     { Bad_Opcode },
3855     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3856   },
3857
3858   /* PREFIX_VEX_72_REG_4 */
3859   {
3860     { Bad_Opcode },
3861     { Bad_Opcode },
3862     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3863   },
3864
3865   /* PREFIX_VEX_72_REG_6 */
3866   {
3867     { Bad_Opcode },
3868     { Bad_Opcode },
3869     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3870   },
3871
3872   /* PREFIX_VEX_73_REG_2 */
3873   {
3874     { Bad_Opcode },
3875     { Bad_Opcode },
3876     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3877   },
3878
3879   /* PREFIX_VEX_73_REG_3 */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3884   },
3885
3886   /* PREFIX_VEX_73_REG_6 */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3891   },
3892
3893   /* PREFIX_VEX_73_REG_7 */
3894   {
3895     { Bad_Opcode },
3896     { Bad_Opcode },
3897     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3898   },
3899
3900   /* PREFIX_VEX_74 */
3901   {
3902     { Bad_Opcode },
3903     { Bad_Opcode },
3904     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3905   },
3906
3907   /* PREFIX_VEX_75 */
3908   {
3909     { Bad_Opcode },
3910     { Bad_Opcode },
3911     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3912   },
3913
3914   /* PREFIX_VEX_76 */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3919   },
3920
3921   /* PREFIX_VEX_77 */
3922   {
3923     { VEX_W_TABLE (VEX_W_77_P_0) },
3924   },
3925
3926   /* PREFIX_VEX_7C */
3927   {
3928     { Bad_Opcode },
3929     { Bad_Opcode },
3930     { VEX_W_TABLE (VEX_W_7C_P_2) },
3931     { VEX_W_TABLE (VEX_W_7C_P_3) },
3932   },
3933
3934   /* PREFIX_VEX_7D */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { VEX_W_TABLE (VEX_W_7D_P_2) },
3939     { VEX_W_TABLE (VEX_W_7D_P_3) },
3940   },
3941
3942   /* PREFIX_VEX_7E */
3943   {
3944     { Bad_Opcode },
3945     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3946     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3947   },
3948
3949   /* PREFIX_VEX_7F */
3950   {
3951     { Bad_Opcode },
3952     { VEX_W_TABLE (VEX_W_7F_P_1) },
3953     { VEX_W_TABLE (VEX_W_7F_P_2) },
3954   },
3955
3956   /* PREFIX_VEX_C2 */
3957   {
3958     { VEX_W_TABLE (VEX_W_C2_P_0) },
3959     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3960     { VEX_W_TABLE (VEX_W_C2_P_2) },
3961     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3962   },
3963
3964   /* PREFIX_VEX_C4 */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3969   },
3970
3971   /* PREFIX_VEX_C5 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3976   },
3977
3978   /* PREFIX_VEX_D0 */
3979   {
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { VEX_W_TABLE (VEX_W_D0_P_2) },
3983     { VEX_W_TABLE (VEX_W_D0_P_3) },
3984   },
3985
3986   /* PREFIX_VEX_D1 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3991   },
3992
3993   /* PREFIX_VEX_D2 */
3994   {
3995     { Bad_Opcode },
3996     { Bad_Opcode },
3997     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3998   },
3999
4000   /* PREFIX_VEX_D3 */
4001   {
4002     { Bad_Opcode },
4003     { Bad_Opcode },
4004     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
4005   },
4006
4007   /* PREFIX_VEX_D4 */
4008   {
4009     { Bad_Opcode },
4010     { Bad_Opcode },
4011     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4012   },
4013
4014   /* PREFIX_VEX_D5 */
4015   {
4016     { Bad_Opcode },
4017     { Bad_Opcode },
4018     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4019   },
4020
4021   /* PREFIX_VEX_D6 */
4022   {
4023     { Bad_Opcode },
4024     { Bad_Opcode },
4025     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4026   },
4027
4028   /* PREFIX_VEX_D7 */
4029   {
4030     { Bad_Opcode },
4031     { Bad_Opcode },
4032     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4033   },
4034
4035   /* PREFIX_VEX_D8 */
4036   {
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4040   },
4041
4042   /* PREFIX_VEX_D9 */
4043   {
4044     { Bad_Opcode },
4045     { Bad_Opcode },
4046     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4047   },
4048
4049   /* PREFIX_VEX_DA */
4050   {
4051     { Bad_Opcode },
4052     { Bad_Opcode },
4053     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4054   },
4055
4056   /* PREFIX_VEX_DB */
4057   {
4058     { Bad_Opcode },
4059     { Bad_Opcode },
4060     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4061   },
4062
4063   /* PREFIX_VEX_DC */
4064   {
4065     { Bad_Opcode },
4066     { Bad_Opcode },
4067     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4068   },
4069
4070   /* PREFIX_VEX_DD */
4071   {
4072     { Bad_Opcode },
4073     { Bad_Opcode },
4074     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4075   },
4076
4077   /* PREFIX_VEX_DE */
4078   {
4079     { Bad_Opcode },
4080     { Bad_Opcode },
4081     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4082   },
4083
4084   /* PREFIX_VEX_DF */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4089   },
4090
4091   /* PREFIX_VEX_E0 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4096   },
4097
4098   /* PREFIX_VEX_E1 */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4103   },
4104
4105   /* PREFIX_VEX_E2 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4110   },
4111
4112   /* PREFIX_VEX_E3 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4117   },
4118
4119   /* PREFIX_VEX_E4 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4124   },
4125
4126   /* PREFIX_VEX_E5 */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4131   },
4132
4133   /* PREFIX_VEX_E6 */
4134   {
4135     { Bad_Opcode },
4136     { VEX_W_TABLE (VEX_W_E6_P_1) },
4137     { VEX_W_TABLE (VEX_W_E6_P_2) },
4138     { VEX_W_TABLE (VEX_W_E6_P_3) },
4139   },
4140
4141   /* PREFIX_VEX_E7 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4146   },
4147
4148   /* PREFIX_VEX_E8 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4153   },
4154
4155   /* PREFIX_VEX_E9 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4160   },
4161
4162   /* PREFIX_VEX_EA */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4167   },
4168
4169   /* PREFIX_VEX_EB */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4174   },
4175
4176   /* PREFIX_VEX_EC */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4181   },
4182
4183   /* PREFIX_VEX_ED */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4188   },
4189
4190   /* PREFIX_VEX_EE */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4195   },
4196
4197   /* PREFIX_VEX_EF */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4202   },
4203
4204   /* PREFIX_VEX_F0 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4210   },
4211
4212   /* PREFIX_VEX_F1 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4217   },
4218
4219   /* PREFIX_VEX_F2 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4224   },
4225
4226   /* PREFIX_VEX_F3 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4231   },
4232
4233   /* PREFIX_VEX_F4 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4238   },
4239
4240   /* PREFIX_VEX_F5 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4245   },
4246
4247   /* PREFIX_VEX_F6 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4252   },
4253
4254   /* PREFIX_VEX_F7 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4259   },
4260
4261   /* PREFIX_VEX_F8 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4266   },
4267
4268   /* PREFIX_VEX_F9 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4273   },
4274
4275   /* PREFIX_VEX_FA */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4280   },
4281
4282   /* PREFIX_VEX_FB */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4287   },
4288
4289   /* PREFIX_VEX_FC */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4294   },
4295
4296   /* PREFIX_VEX_FD */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4301   },
4302
4303   /* PREFIX_VEX_FE */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4308   },
4309
4310   /* PREFIX_VEX_3800 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4315   },
4316
4317   /* PREFIX_VEX_3801 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4322   },
4323
4324   /* PREFIX_VEX_3802 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4329   },
4330
4331   /* PREFIX_VEX_3803 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4336   },
4337
4338   /* PREFIX_VEX_3804 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4343   },
4344
4345   /* PREFIX_VEX_3805 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4350   },
4351
4352   /* PREFIX_VEX_3806 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4357   },
4358
4359   /* PREFIX_VEX_3807 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4364   },
4365
4366   /* PREFIX_VEX_3808 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4371   },
4372
4373   /* PREFIX_VEX_3809 */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4378   },
4379
4380   /* PREFIX_VEX_380A */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4385   },
4386
4387   /* PREFIX_VEX_380B */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4392   },
4393
4394   /* PREFIX_VEX_380C */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { VEX_W_TABLE (VEX_W_380C_P_2) },
4399   },
4400
4401   /* PREFIX_VEX_380D */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { VEX_W_TABLE (VEX_W_380D_P_2) },
4406   },
4407
4408   /* PREFIX_VEX_380E */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { VEX_W_TABLE (VEX_W_380E_P_2) },
4413   },
4414
4415   /* PREFIX_VEX_380F */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { VEX_W_TABLE (VEX_W_380F_P_2) },
4420   },
4421
4422   /* PREFIX_VEX_3817 */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { VEX_W_TABLE (VEX_W_3817_P_2) },
4427   },
4428
4429   /* PREFIX_VEX_3818 */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4434   },
4435
4436   /* PREFIX_VEX_3819 */
4437   {
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4441   },
4442
4443   /* PREFIX_VEX_381A */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4448   },
4449
4450   /* PREFIX_VEX_381C */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4455   },
4456
4457   /* PREFIX_VEX_381D */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4462   },
4463
4464   /* PREFIX_VEX_381E */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4469   },
4470
4471   /* PREFIX_VEX_3820 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4476   },
4477
4478   /* PREFIX_VEX_3821 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4483   },
4484
4485   /* PREFIX_VEX_3822 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4490   },
4491
4492   /* PREFIX_VEX_3823 */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4497   },
4498
4499   /* PREFIX_VEX_3824 */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4504   },
4505
4506   /* PREFIX_VEX_3825 */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4511   },
4512
4513   /* PREFIX_VEX_3828 */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4518   },
4519
4520   /* PREFIX_VEX_3829 */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4525   },
4526
4527   /* PREFIX_VEX_382A */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4532   },
4533
4534   /* PREFIX_VEX_382B */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4539   },
4540
4541   /* PREFIX_VEX_382C */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4546   },
4547
4548   /* PREFIX_VEX_382D */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4553   },
4554
4555   /* PREFIX_VEX_382E */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4560   },
4561
4562   /* PREFIX_VEX_382F */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4567   },
4568
4569   /* PREFIX_VEX_3830 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4574   },
4575
4576   /* PREFIX_VEX_3831 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4581   },
4582
4583   /* PREFIX_VEX_3832 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_3833 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_3834 */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_3835 */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_3837 */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_3838 */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_3839 */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_383A */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_383B */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_383C */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4651   },
4652
4653   /* PREFIX_VEX_383D */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4658   },
4659
4660   /* PREFIX_VEX_383E */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4665   },
4666
4667   /* PREFIX_VEX_383F */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4672   },
4673
4674   /* PREFIX_VEX_3840 */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4679   },
4680
4681   /* PREFIX_VEX_3841 */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4686   },
4687
4688   /* PREFIX_VEX_3896 */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4693   },
4694
4695   /* PREFIX_VEX_3897 */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4700   },
4701
4702   /* PREFIX_VEX_3898 */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "vfmadd132p%XW", { XM, Vex, EXx } },
4707   },
4708
4709   /* PREFIX_VEX_3899 */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4714   },
4715
4716   /* PREFIX_VEX_389A */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "vfmsub132p%XW", { XM, Vex, EXx } },
4721   },
4722
4723   /* PREFIX_VEX_389B */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4728   },
4729
4730   /* PREFIX_VEX_389C */
4731   {
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4735   },
4736
4737   /* PREFIX_VEX_389D */
4738   {
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4742   },
4743
4744   /* PREFIX_VEX_389E */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4749   },
4750
4751   /* PREFIX_VEX_389F */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4756   },
4757
4758   /* PREFIX_VEX_38A6 */
4759   {
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4763     { Bad_Opcode },
4764   },
4765
4766   /* PREFIX_VEX_38A7 */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4771   },
4772
4773   /* PREFIX_VEX_38A8 */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vfmadd213p%XW", { XM, Vex, EXx } },
4778   },
4779
4780   /* PREFIX_VEX_38A9 */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4785   },
4786
4787   /* PREFIX_VEX_38AA */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vfmsub213p%XW", { XM, Vex, EXx } },
4792   },
4793
4794   /* PREFIX_VEX_38AB */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4799   },
4800
4801   /* PREFIX_VEX_38AC */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4806   },
4807
4808   /* PREFIX_VEX_38AD */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4813   },
4814
4815   /* PREFIX_VEX_38AE */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4820   },
4821
4822   /* PREFIX_VEX_38AF */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4827   },
4828
4829   /* PREFIX_VEX_38B6 */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4834   },
4835
4836   /* PREFIX_VEX_38B7 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4841   },
4842
4843   /* PREFIX_VEX_38B8 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vfmadd231p%XW", { XM, Vex, EXx } },
4848   },
4849
4850   /* PREFIX_VEX_38B9 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4855   },
4856
4857   /* PREFIX_VEX_38BA */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vfmsub231p%XW", { XM, Vex, EXx } },
4862   },
4863
4864   /* PREFIX_VEX_38BB */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4869   },
4870
4871   /* PREFIX_VEX_38BC */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4876   },
4877
4878   /* PREFIX_VEX_38BD */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4883   },
4884
4885   /* PREFIX_VEX_38BE */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4890   },
4891
4892   /* PREFIX_VEX_38BF */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4897   },
4898
4899   /* PREFIX_VEX_38DB */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_38DC */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_38DD */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_38DE */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_38DF */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_3A04 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_W_TABLE (VEX_W_3A04_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_3A05 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_W_TABLE (VEX_W_3A05_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_3A06 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_3A08 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_3A08_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_3A09 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_W_TABLE (VEX_W_3A09_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_3A0A */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_3A0B */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_3A0C */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_3A0D */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_3A0E */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_3A0F */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_3A14 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_3A15 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_3A16 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_3A17 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_3A18 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_3A19 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_3A20 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_3A21 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_3A22 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_3A40 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_3A40_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_3A41 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_3A42 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_3A44 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_3A48 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_W_TABLE (VEX_W_3A48_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_3A49 */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_W_TABLE (VEX_W_3A49_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_3A4A */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_3A4B */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_3A4C */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_3A5C */
5138   {
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5142   },
5143
5144   /* PREFIX_VEX_3A5D */
5145   {
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5149   },
5150
5151   /* PREFIX_VEX_3A5E */
5152   {
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5156   },
5157
5158   /* PREFIX_VEX_3A5F */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5163   },
5164
5165   /* PREFIX_VEX_3A60 */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5170     { Bad_Opcode },
5171   },
5172
5173   /* PREFIX_VEX_3A61 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_3A62 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_3A63 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_3A68 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5199   },
5200
5201   /* PREFIX_VEX_3A69 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5206   },
5207
5208   /* PREFIX_VEX_3A6A */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_3A6B */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_3A6C */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5227   },
5228
5229   /* PREFIX_VEX_3A6D */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5234   },
5235
5236   /* PREFIX_VEX_3A6E */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_3A6F */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5248   },
5249
5250   /* PREFIX_VEX_3A78 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5255   },
5256
5257   /* PREFIX_VEX_3A79 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5262   },
5263
5264   /* PREFIX_VEX_3A7A */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_3A7B */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_3A7C */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5283     { Bad_Opcode },
5284   },
5285
5286   /* PREFIX_VEX_3A7D */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5291   },
5292
5293   /* PREFIX_VEX_3A7E */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5298   },
5299
5300   /* PREFIX_VEX_3A7F */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5305   },
5306
5307   /* PREFIX_VEX_3ADF */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5312   },
5313 };
5314
5315 static const struct dis386 x86_64_table[][2] = {
5316   /* X86_64_06 */
5317   {
5318     { "push{T|}", { es } },
5319   },
5320
5321   /* X86_64_07 */
5322   {
5323     { "pop{T|}", { es } },
5324   },
5325
5326   /* X86_64_0D */
5327   {
5328     { "push{T|}", { cs } },
5329   },
5330
5331   /* X86_64_16 */
5332   {
5333     { "push{T|}", { ss } },
5334   },
5335
5336   /* X86_64_17 */
5337   {
5338     { "pop{T|}", { ss } },
5339   },
5340
5341   /* X86_64_1E */
5342   {
5343     { "push{T|}", { ds } },
5344   },
5345
5346   /* X86_64_1F */
5347   {
5348     { "pop{T|}", { ds } },
5349   },
5350
5351   /* X86_64_27 */
5352   {
5353     { "daa", { XX } },
5354   },
5355
5356   /* X86_64_2F */
5357   {
5358     { "das", { XX } },
5359   },
5360
5361   /* X86_64_37 */
5362   {
5363     { "aaa", { XX } },
5364   },
5365
5366   /* X86_64_3F */
5367   {
5368     { "aas", { XX } },
5369   },
5370
5371   /* X86_64_60 */
5372   {
5373     { "pusha{P|}", { XX } },
5374   },
5375
5376   /* X86_64_61 */
5377   {
5378     { "popa{P|}", { XX } },
5379   },
5380
5381   /* X86_64_62 */
5382   {
5383     { MOD_TABLE (MOD_62_32BIT) },
5384   },
5385
5386   /* X86_64_63 */
5387   {
5388     { "arpl", { Ew, Gw } },
5389     { "movs{lq|xd}", { Gv, Ed } },
5390   },
5391
5392   /* X86_64_6D */
5393   {
5394     { "ins{R|}", { Yzr, indirDX } },
5395     { "ins{G|}", { Yzr, indirDX } },
5396   },
5397
5398   /* X86_64_6F */
5399   {
5400     { "outs{R|}", { indirDXr, Xz } },
5401     { "outs{G|}", { indirDXr, Xz } },
5402   },
5403
5404   /* X86_64_9A */
5405   {
5406     { "Jcall{T|}", { Ap } },
5407   },
5408
5409   /* X86_64_C4 */
5410   {
5411     { MOD_TABLE (MOD_C4_32BIT) },
5412     { VEX_C4_TABLE (VEX_0F) },
5413   },
5414
5415   /* X86_64_C5 */
5416   {
5417     { MOD_TABLE (MOD_C5_32BIT) },
5418     { VEX_C5_TABLE (VEX_0F) },
5419   },
5420
5421   /* X86_64_CE */
5422   {
5423     { "into", { XX } },
5424   },
5425
5426   /* X86_64_D4 */
5427   {
5428     { "aam", { sIb } },
5429   },
5430
5431   /* X86_64_D5 */
5432   {
5433     { "aad", { sIb } },
5434   },
5435
5436   /* X86_64_EA */
5437   {
5438     { "Jjmp{T|}", { Ap } },
5439   },
5440
5441   /* X86_64_0F01_REG_0 */
5442   {
5443     { "sgdt{Q|IQ}", { M } },
5444     { "sgdt", { M } },
5445   },
5446
5447   /* X86_64_0F01_REG_1 */
5448   {
5449     { "sidt{Q|IQ}", { M } },
5450     { "sidt", { M } },
5451   },
5452
5453   /* X86_64_0F01_REG_2 */
5454   {
5455     { "lgdt{Q|Q}", { M } },
5456     { "lgdt", { M } },
5457   },
5458
5459   /* X86_64_0F01_REG_3 */
5460   {
5461     { "lidt{Q|Q}", { M } },
5462     { "lidt", { M } },
5463   },
5464 };
5465
5466 static const struct dis386 three_byte_table[][256] = {
5467
5468   /* THREE_BYTE_0F38 */
5469   {
5470     /* 00 */
5471     { "pshufb",         { MX, EM } },
5472     { "phaddw",         { MX, EM } },
5473     { "phaddd",         { MX, EM } },
5474     { "phaddsw",        { MX, EM } },
5475     { "pmaddubsw",      { MX, EM } },
5476     { "phsubw",         { MX, EM } },
5477     { "phsubd",         { MX, EM } },
5478     { "phsubsw",        { MX, EM } },
5479     /* 08 */
5480     { "psignb",         { MX, EM } },
5481     { "psignw",         { MX, EM } },
5482     { "psignd",         { MX, EM } },
5483     { "pmulhrsw",       { MX, EM } },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     /* 10 */
5489     { PREFIX_TABLE (PREFIX_0F3810) },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { PREFIX_TABLE (PREFIX_0F3814) },
5494     { PREFIX_TABLE (PREFIX_0F3815) },
5495     { Bad_Opcode },
5496     { PREFIX_TABLE (PREFIX_0F3817) },
5497     /* 18 */
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { "pabsb",          { MX, EM } },
5503     { "pabsw",          { MX, EM } },
5504     { "pabsd",          { MX, EM } },
5505     { Bad_Opcode },
5506     /* 20 */
5507     { PREFIX_TABLE (PREFIX_0F3820) },
5508     { PREFIX_TABLE (PREFIX_0F3821) },
5509     { PREFIX_TABLE (PREFIX_0F3822) },
5510     { PREFIX_TABLE (PREFIX_0F3823) },
5511     { PREFIX_TABLE (PREFIX_0F3824) },
5512     { PREFIX_TABLE (PREFIX_0F3825) },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     /* 28 */
5516     { PREFIX_TABLE (PREFIX_0F3828) },
5517     { PREFIX_TABLE (PREFIX_0F3829) },
5518     { PREFIX_TABLE (PREFIX_0F382A) },
5519     { PREFIX_TABLE (PREFIX_0F382B) },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     /* 30 */
5525     { PREFIX_TABLE (PREFIX_0F3830) },
5526     { PREFIX_TABLE (PREFIX_0F3831) },
5527     { PREFIX_TABLE (PREFIX_0F3832) },
5528     { PREFIX_TABLE (PREFIX_0F3833) },
5529     { PREFIX_TABLE (PREFIX_0F3834) },
5530     { PREFIX_TABLE (PREFIX_0F3835) },
5531     { Bad_Opcode },
5532     { PREFIX_TABLE (PREFIX_0F3837) },
5533     /* 38 */
5534     { PREFIX_TABLE (PREFIX_0F3838) },
5535     { PREFIX_TABLE (PREFIX_0F3839) },
5536     { PREFIX_TABLE (PREFIX_0F383A) },
5537     { PREFIX_TABLE (PREFIX_0F383B) },
5538     { PREFIX_TABLE (PREFIX_0F383C) },
5539     { PREFIX_TABLE (PREFIX_0F383D) },
5540     { PREFIX_TABLE (PREFIX_0F383E) },
5541     { PREFIX_TABLE (PREFIX_0F383F) },
5542     /* 40 */
5543     { PREFIX_TABLE (PREFIX_0F3840) },
5544     { PREFIX_TABLE (PREFIX_0F3841) },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     /* 48 */
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     /* 50 */
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     /* 58 */
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     /* 60 */
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     /* 68 */
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     /* 70 */
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     /* 78 */
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     /* 80 */
5615     { PREFIX_TABLE (PREFIX_0F3880) },
5616     { PREFIX_TABLE (PREFIX_0F3881) },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     /* 88 */
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     /* 90 */
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     /* 98 */
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     /* a0 */
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     /* a8 */
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     /* b0 */
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     /* b8 */
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     /* c0 */
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     /* c8 */
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     /* d0 */
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     /* d8 */
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { PREFIX_TABLE (PREFIX_0F38DB) },
5718     { PREFIX_TABLE (PREFIX_0F38DC) },
5719     { PREFIX_TABLE (PREFIX_0F38DD) },
5720     { PREFIX_TABLE (PREFIX_0F38DE) },
5721     { PREFIX_TABLE (PREFIX_0F38DF) },
5722     /* e0 */
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     /* e8 */
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     /* f0 */
5741     { PREFIX_TABLE (PREFIX_0F38F0) },
5742     { PREFIX_TABLE (PREFIX_0F38F1) },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     /* f8 */
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758   },
5759   /* THREE_BYTE_0F3A */
5760   {
5761     /* 00 */
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     /* 08 */
5771     { PREFIX_TABLE (PREFIX_0F3A08) },
5772     { PREFIX_TABLE (PREFIX_0F3A09) },
5773     { PREFIX_TABLE (PREFIX_0F3A0A) },
5774     { PREFIX_TABLE (PREFIX_0F3A0B) },
5775     { PREFIX_TABLE (PREFIX_0F3A0C) },
5776     { PREFIX_TABLE (PREFIX_0F3A0D) },
5777     { PREFIX_TABLE (PREFIX_0F3A0E) },
5778     { "palignr",        { MX, EM, Ib } },
5779     /* 10 */
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { PREFIX_TABLE (PREFIX_0F3A14) },
5785     { PREFIX_TABLE (PREFIX_0F3A15) },
5786     { PREFIX_TABLE (PREFIX_0F3A16) },
5787     { PREFIX_TABLE (PREFIX_0F3A17) },
5788     /* 18 */
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     /* 20 */
5798     { PREFIX_TABLE (PREFIX_0F3A20) },
5799     { PREFIX_TABLE (PREFIX_0F3A21) },
5800     { PREFIX_TABLE (PREFIX_0F3A22) },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     /* 28 */
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     /* 30 */
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     /* 38 */
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     /* 40 */
5834     { PREFIX_TABLE (PREFIX_0F3A40) },
5835     { PREFIX_TABLE (PREFIX_0F3A41) },
5836     { PREFIX_TABLE (PREFIX_0F3A42) },
5837     { Bad_Opcode },
5838     { PREFIX_TABLE (PREFIX_0F3A44) },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     /* 48 */
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     /* 50 */
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     /* 58 */
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     /* 60 */
5870     { PREFIX_TABLE (PREFIX_0F3A60) },
5871     { PREFIX_TABLE (PREFIX_0F3A61) },
5872     { PREFIX_TABLE (PREFIX_0F3A62) },
5873     { PREFIX_TABLE (PREFIX_0F3A63) },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     /* 68 */
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     /* 70 */
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     /* 78 */
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     /* 80 */
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     /* 88 */
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     /* 90 */
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     /* 98 */
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     /* a0 */
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     /* a8 */
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     /* b0 */
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     /* b8 */
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     /* c0 */
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     /* c8 */
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     /* d0 */
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     /* d8 */
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { PREFIX_TABLE (PREFIX_0F3ADF) },
6013     /* e0 */
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     /* e8 */
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* f0 */
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     /* f8 */
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049   },
6050
6051   /* THREE_BYTE_0F7A */
6052   {
6053     /* 00 */
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     /* 08 */
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     /* 10 */
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     /* 18 */
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     /* 20 */
6090     { "ptest",          { XX } },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     /* 28 */
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     /* 30 */
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     /* 38 */
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     /* 40 */
6126     { Bad_Opcode },
6127     { "phaddbw",        { XM, EXq } },
6128     { "phaddbd",        { XM, EXq } },
6129     { "phaddbq",        { XM, EXq } },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "phaddwd",        { XM, EXq } },
6133     { "phaddwq",        { XM, EXq } },
6134     /* 48 */
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { "phadddq",        { XM, EXq } },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     /* 50 */
6144     { Bad_Opcode },
6145     { "phaddubw",       { XM, EXq } },
6146     { "phaddubd",       { XM, EXq } },
6147     { "phaddubq",       { XM, EXq } },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "phadduwd",       { XM, EXq } },
6151     { "phadduwq",       { XM, EXq } },
6152     /* 58 */
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "phaddudq",       { XM, EXq } },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     /* 60 */
6162     { Bad_Opcode },
6163     { "phsubbw",        { XM, EXq } },
6164     { "phsubbd",        { XM, EXq } },
6165     { "phsubbq",        { XM, EXq } },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     /* 68 */
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     /* 70 */
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     /* 78 */
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     /* 80 */
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     /* 88 */
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     /* 90 */
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     /* 98 */
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     /* a0 */
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     /* a8 */
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     /* b0 */
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     /* b8 */
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     /* c0 */
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     /* c8 */
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     /* d0 */
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     /* d8 */
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     /* e0 */
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     /* e8 */
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     /* f0 */
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     /* f8 */
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341   },
6342 };
6343
6344 static const struct dis386 xop_table[][256] = {
6345   /* XOP_08 */
6346   {
6347     /* 00 */
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     /* 08 */
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     /* 10 */
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     /* 18 */
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     /* 20 */
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     /* 28 */
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     /* 30 */
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     /* 38 */
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     /* 40 */
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     /* 48 */
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     /* 50 */
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     /* 58 */
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     /* 60 */
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     /* 68 */
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     /* 70 */
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     /* 78 */
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     /* 80 */
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6498     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6499     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6500     /* 88 */
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6508     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6509     /* 90 */
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6516     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6517     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6518     /* 98 */
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6526     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6527     /* a0 */
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6531     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6535     { Bad_Opcode },
6536     /* a8 */
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     /* b0 */
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6553     { Bad_Opcode },
6554     /* b8 */
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     /* c0 */
6564     { "vprotb",         { XM, Vex_2src_1, Ib } },
6565     { "vprotw",         { XM, Vex_2src_1, Ib } },
6566     { "vprotd",         { XM, Vex_2src_1, Ib } },
6567     { "vprotq",         { XM, Vex_2src_1, Ib } },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     /* c8 */
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6578     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6579     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6580     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6581     /* d0 */
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     /* d8 */
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     /* e0 */
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     /* e8 */
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6614     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6615     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6616     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6617     /* f0 */
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     /* f8 */
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635   },
6636   /* XOP_09 */
6637   {
6638     /* 00 */
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     /* 08 */
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     /* 10 */
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { REG_TABLE (REG_XOP_LWPCB) },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     /* 18 */
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     /* 20 */
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     /* 28 */
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     /* 30 */
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     /* 38 */
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     /* 40 */
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     /* 48 */
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     /* 50 */
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     /* 58 */
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     /* 60 */
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     /* 68 */
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     /* 70 */
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     /* 78 */
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     /* 80 */
6783     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6784     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6785     { "vfrczss",        { XM, EXd } },
6786     { "vfrczsd",        { XM, EXq } },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     /* 88 */
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     /* 90 */
6801     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6802     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6803     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6804     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6805     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6806     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6807     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6808     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6809     /* 98 */
6810     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6811     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6812     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6813     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     /* a0 */
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     /* a8 */
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     /* b0 */
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     /* b8 */
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     /* c0 */
6855     { Bad_Opcode },
6856     { "vphaddbw",       { XM, EXxmm } },
6857     { "vphaddbd",       { XM, EXxmm } },
6858     { "vphaddbq",       { XM, EXxmm } },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { "vphaddwd",       { XM, EXxmm } },
6862     { "vphaddwq",       { XM, EXxmm } },
6863     /* c8 */
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { "vphadddq",       { XM, EXxmm } },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     /* d0 */
6873     { Bad_Opcode },
6874     { "vphaddubw",      { XM, EXxmm } },
6875     { "vphaddubd",      { XM, EXxmm } },
6876     { "vphaddubq",      { XM, EXxmm } },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { "vphadduwd",      { XM, EXxmm } },
6880     { "vphadduwq",      { XM, EXxmm } },
6881     /* d8 */
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { "vphaddudq",      { XM, EXxmm } },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* e0 */
6891     { Bad_Opcode },
6892     { "vphsubbw",       { XM, EXxmm } },
6893     { "vphsubwd",       { XM, EXxmm } },
6894     { "vphsubdq",       { XM, EXxmm } },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     /* e8 */
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* f0 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* f8 */
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926   },
6927   /* XOP_0A */
6928   {
6929     /* 00 */
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     /* 08 */
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     /* 10 */
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { REG_TABLE (REG_XOP_LWP) },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     /* 18 */
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     /* 20 */
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     /* 28 */
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 30 */
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 38 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* 40 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* 48 */
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* 50 */
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* 58 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* 60 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* 68 */
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* 70 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* 78 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* 80 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* 88 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* 90 */
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* 98 */
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* a0 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* a8 */
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* b0 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* b8 */
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     /* c0 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* c8 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     /* d0 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* d8 */
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* e0 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* e8 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* f0 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* f8 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217   },
7218 };
7219
7220 static const struct dis386 vex_table[][256] = {
7221   /* VEX_0F */
7222   {
7223     /* 00 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* 08 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* 10 */
7242     { PREFIX_TABLE (PREFIX_VEX_10) },
7243     { PREFIX_TABLE (PREFIX_VEX_11) },
7244     { PREFIX_TABLE (PREFIX_VEX_12) },
7245     { MOD_TABLE (MOD_VEX_13) },
7246     { VEX_W_TABLE (VEX_W_14) },
7247     { VEX_W_TABLE (VEX_W_15) },
7248     { PREFIX_TABLE (PREFIX_VEX_16) },
7249     { MOD_TABLE (MOD_VEX_17) },
7250     /* 18 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* 20 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* 28 */
7269     { VEX_W_TABLE (VEX_W_28) },
7270     { VEX_W_TABLE (VEX_W_29) },
7271     { PREFIX_TABLE (PREFIX_VEX_2A) },
7272     { MOD_TABLE (MOD_VEX_2B) },
7273     { PREFIX_TABLE (PREFIX_VEX_2C) },
7274     { PREFIX_TABLE (PREFIX_VEX_2D) },
7275     { PREFIX_TABLE (PREFIX_VEX_2E) },
7276     { PREFIX_TABLE (PREFIX_VEX_2F) },
7277     /* 30 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 38 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 40 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 48 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 50 */
7314     { MOD_TABLE (MOD_VEX_50) },
7315     { PREFIX_TABLE (PREFIX_VEX_51) },
7316     { PREFIX_TABLE (PREFIX_VEX_52) },
7317     { PREFIX_TABLE (PREFIX_VEX_53) },
7318     { "vandpX",         { XM, Vex, EXx } },
7319     { "vandnpX",        { XM, Vex, EXx } },
7320     { "vorpX",          { XM, Vex, EXx } },
7321     { "vxorpX",         { XM, Vex, EXx } },
7322     /* 58 */
7323     { PREFIX_TABLE (PREFIX_VEX_58) },
7324     { PREFIX_TABLE (PREFIX_VEX_59) },
7325     { PREFIX_TABLE (PREFIX_VEX_5A) },
7326     { PREFIX_TABLE (PREFIX_VEX_5B) },
7327     { PREFIX_TABLE (PREFIX_VEX_5C) },
7328     { PREFIX_TABLE (PREFIX_VEX_5D) },
7329     { PREFIX_TABLE (PREFIX_VEX_5E) },
7330     { PREFIX_TABLE (PREFIX_VEX_5F) },
7331     /* 60 */
7332     { PREFIX_TABLE (PREFIX_VEX_60) },
7333     { PREFIX_TABLE (PREFIX_VEX_61) },
7334     { PREFIX_TABLE (PREFIX_VEX_62) },
7335     { PREFIX_TABLE (PREFIX_VEX_63) },
7336     { PREFIX_TABLE (PREFIX_VEX_64) },
7337     { PREFIX_TABLE (PREFIX_VEX_65) },
7338     { PREFIX_TABLE (PREFIX_VEX_66) },
7339     { PREFIX_TABLE (PREFIX_VEX_67) },
7340     /* 68 */
7341     { PREFIX_TABLE (PREFIX_VEX_68) },
7342     { PREFIX_TABLE (PREFIX_VEX_69) },
7343     { PREFIX_TABLE (PREFIX_VEX_6A) },
7344     { PREFIX_TABLE (PREFIX_VEX_6B) },
7345     { PREFIX_TABLE (PREFIX_VEX_6C) },
7346     { PREFIX_TABLE (PREFIX_VEX_6D) },
7347     { PREFIX_TABLE (PREFIX_VEX_6E) },
7348     { PREFIX_TABLE (PREFIX_VEX_6F) },
7349     /* 70 */
7350     { PREFIX_TABLE (PREFIX_VEX_70) },
7351     { REG_TABLE (REG_VEX_71) },
7352     { REG_TABLE (REG_VEX_72) },
7353     { REG_TABLE (REG_VEX_73) },
7354     { PREFIX_TABLE (PREFIX_VEX_74) },
7355     { PREFIX_TABLE (PREFIX_VEX_75) },
7356     { PREFIX_TABLE (PREFIX_VEX_76) },
7357     { PREFIX_TABLE (PREFIX_VEX_77) },
7358     /* 78 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { PREFIX_TABLE (PREFIX_VEX_7C) },
7364     { PREFIX_TABLE (PREFIX_VEX_7D) },
7365     { PREFIX_TABLE (PREFIX_VEX_7E) },
7366     { PREFIX_TABLE (PREFIX_VEX_7F) },
7367     /* 80 */
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* 88 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* 90 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* 98 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* a0 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* a8 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { REG_TABLE (REG_VEX_AE) },
7420     { Bad_Opcode },
7421     /* b0 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* b8 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* c0 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { PREFIX_TABLE (PREFIX_VEX_C2) },
7443     { Bad_Opcode },
7444     { PREFIX_TABLE (PREFIX_VEX_C4) },
7445     { PREFIX_TABLE (PREFIX_VEX_C5) },
7446     { "vshufpX",        { XM, Vex, EXx, Ib } },
7447     { Bad_Opcode },
7448     /* c8 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* d0 */
7458     { PREFIX_TABLE (PREFIX_VEX_D0) },
7459     { PREFIX_TABLE (PREFIX_VEX_D1) },
7460     { PREFIX_TABLE (PREFIX_VEX_D2) },
7461     { PREFIX_TABLE (PREFIX_VEX_D3) },
7462     { PREFIX_TABLE (PREFIX_VEX_D4) },
7463     { PREFIX_TABLE (PREFIX_VEX_D5) },
7464     { PREFIX_TABLE (PREFIX_VEX_D6) },
7465     { PREFIX_TABLE (PREFIX_VEX_D7) },
7466     /* d8 */
7467     { PREFIX_TABLE (PREFIX_VEX_D8) },
7468     { PREFIX_TABLE (PREFIX_VEX_D9) },
7469     { PREFIX_TABLE (PREFIX_VEX_DA) },
7470     { PREFIX_TABLE (PREFIX_VEX_DB) },
7471     { PREFIX_TABLE (PREFIX_VEX_DC) },
7472     { PREFIX_TABLE (PREFIX_VEX_DD) },
7473     { PREFIX_TABLE (PREFIX_VEX_DE) },
7474     { PREFIX_TABLE (PREFIX_VEX_DF) },
7475     /* e0 */
7476     { PREFIX_TABLE (PREFIX_VEX_E0) },
7477     { PREFIX_TABLE (PREFIX_VEX_E1) },
7478     { PREFIX_TABLE (PREFIX_VEX_E2) },
7479     { PREFIX_TABLE (PREFIX_VEX_E3) },
7480     { PREFIX_TABLE (PREFIX_VEX_E4) },
7481     { PREFIX_TABLE (PREFIX_VEX_E5) },
7482     { PREFIX_TABLE (PREFIX_VEX_E6) },
7483     { PREFIX_TABLE (PREFIX_VEX_E7) },
7484     /* e8 */
7485     { PREFIX_TABLE (PREFIX_VEX_E8) },
7486     { PREFIX_TABLE (PREFIX_VEX_E9) },
7487     { PREFIX_TABLE (PREFIX_VEX_EA) },
7488     { PREFIX_TABLE (PREFIX_VEX_EB) },
7489     { PREFIX_TABLE (PREFIX_VEX_EC) },
7490     { PREFIX_TABLE (PREFIX_VEX_ED) },
7491     { PREFIX_TABLE (PREFIX_VEX_EE) },
7492     { PREFIX_TABLE (PREFIX_VEX_EF) },
7493     /* f0 */
7494     { PREFIX_TABLE (PREFIX_VEX_F0) },
7495     { PREFIX_TABLE (PREFIX_VEX_F1) },
7496     { PREFIX_TABLE (PREFIX_VEX_F2) },
7497     { PREFIX_TABLE (PREFIX_VEX_F3) },
7498     { PREFIX_TABLE (PREFIX_VEX_F4) },
7499     { PREFIX_TABLE (PREFIX_VEX_F5) },
7500     { PREFIX_TABLE (PREFIX_VEX_F6) },
7501     { PREFIX_TABLE (PREFIX_VEX_F7) },
7502     /* f8 */
7503     { PREFIX_TABLE (PREFIX_VEX_F8) },
7504     { PREFIX_TABLE (PREFIX_VEX_F9) },
7505     { PREFIX_TABLE (PREFIX_VEX_FA) },
7506     { PREFIX_TABLE (PREFIX_VEX_FB) },
7507     { PREFIX_TABLE (PREFIX_VEX_FC) },
7508     { PREFIX_TABLE (PREFIX_VEX_FD) },
7509     { PREFIX_TABLE (PREFIX_VEX_FE) },
7510     { Bad_Opcode },
7511   },
7512   /* VEX_0F38 */
7513   {
7514     /* 00 */
7515     { PREFIX_TABLE (PREFIX_VEX_3800) },
7516     { PREFIX_TABLE (PREFIX_VEX_3801) },
7517     { PREFIX_TABLE (PREFIX_VEX_3802) },
7518     { PREFIX_TABLE (PREFIX_VEX_3803) },
7519     { PREFIX_TABLE (PREFIX_VEX_3804) },
7520     { PREFIX_TABLE (PREFIX_VEX_3805) },
7521     { PREFIX_TABLE (PREFIX_VEX_3806) },
7522     { PREFIX_TABLE (PREFIX_VEX_3807) },
7523     /* 08 */
7524     { PREFIX_TABLE (PREFIX_VEX_3808) },
7525     { PREFIX_TABLE (PREFIX_VEX_3809) },
7526     { PREFIX_TABLE (PREFIX_VEX_380A) },
7527     { PREFIX_TABLE (PREFIX_VEX_380B) },
7528     { PREFIX_TABLE (PREFIX_VEX_380C) },
7529     { PREFIX_TABLE (PREFIX_VEX_380D) },
7530     { PREFIX_TABLE (PREFIX_VEX_380E) },
7531     { PREFIX_TABLE (PREFIX_VEX_380F) },
7532     /* 10 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { PREFIX_TABLE (PREFIX_VEX_3817) },
7541     /* 18 */
7542     { PREFIX_TABLE (PREFIX_VEX_3818) },
7543     { PREFIX_TABLE (PREFIX_VEX_3819) },
7544     { PREFIX_TABLE (PREFIX_VEX_381A) },
7545     { Bad_Opcode },
7546     { PREFIX_TABLE (PREFIX_VEX_381C) },
7547     { PREFIX_TABLE (PREFIX_VEX_381D) },
7548     { PREFIX_TABLE (PREFIX_VEX_381E) },
7549     { Bad_Opcode },
7550     /* 20 */
7551     { PREFIX_TABLE (PREFIX_VEX_3820) },
7552     { PREFIX_TABLE (PREFIX_VEX_3821) },
7553     { PREFIX_TABLE (PREFIX_VEX_3822) },
7554     { PREFIX_TABLE (PREFIX_VEX_3823) },
7555     { PREFIX_TABLE (PREFIX_VEX_3824) },
7556     { PREFIX_TABLE (PREFIX_VEX_3825) },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* 28 */
7560     { PREFIX_TABLE (PREFIX_VEX_3828) },
7561     { PREFIX_TABLE (PREFIX_VEX_3829) },
7562     { PREFIX_TABLE (PREFIX_VEX_382A) },
7563     { PREFIX_TABLE (PREFIX_VEX_382B) },
7564     { PREFIX_TABLE (PREFIX_VEX_382C) },
7565     { PREFIX_TABLE (PREFIX_VEX_382D) },
7566     { PREFIX_TABLE (PREFIX_VEX_382E) },
7567     { PREFIX_TABLE (PREFIX_VEX_382F) },
7568     /* 30 */
7569     { PREFIX_TABLE (PREFIX_VEX_3830) },
7570     { PREFIX_TABLE (PREFIX_VEX_3831) },
7571     { PREFIX_TABLE (PREFIX_VEX_3832) },
7572     { PREFIX_TABLE (PREFIX_VEX_3833) },
7573     { PREFIX_TABLE (PREFIX_VEX_3834) },
7574     { PREFIX_TABLE (PREFIX_VEX_3835) },
7575     { Bad_Opcode },
7576     { PREFIX_TABLE (PREFIX_VEX_3837) },
7577     /* 38 */
7578     { PREFIX_TABLE (PREFIX_VEX_3838) },
7579     { PREFIX_TABLE (PREFIX_VEX_3839) },
7580     { PREFIX_TABLE (PREFIX_VEX_383A) },
7581     { PREFIX_TABLE (PREFIX_VEX_383B) },
7582     { PREFIX_TABLE (PREFIX_VEX_383C) },
7583     { PREFIX_TABLE (PREFIX_VEX_383D) },
7584     { PREFIX_TABLE (PREFIX_VEX_383E) },
7585     { PREFIX_TABLE (PREFIX_VEX_383F) },
7586     /* 40 */
7587     { PREFIX_TABLE (PREFIX_VEX_3840) },
7588     { PREFIX_TABLE (PREFIX_VEX_3841) },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* 48 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* 50 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     /* 58 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     /* 60 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* 68 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* 70 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* 78 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* 80 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* 88 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* 90 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { PREFIX_TABLE (PREFIX_VEX_3896) },
7684     { PREFIX_TABLE (PREFIX_VEX_3897) },
7685     /* 98 */
7686     { PREFIX_TABLE (PREFIX_VEX_3898) },
7687     { PREFIX_TABLE (PREFIX_VEX_3899) },
7688     { PREFIX_TABLE (PREFIX_VEX_389A) },
7689     { PREFIX_TABLE (PREFIX_VEX_389B) },
7690     { PREFIX_TABLE (PREFIX_VEX_389C) },
7691     { PREFIX_TABLE (PREFIX_VEX_389D) },
7692     { PREFIX_TABLE (PREFIX_VEX_389E) },
7693     { PREFIX_TABLE (PREFIX_VEX_389F) },
7694     /* a0 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7702     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7703     /* a8 */
7704     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7705     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7706     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7707     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7708     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7709     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7710     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7711     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7712     /* b0 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7720     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7721     /* b8 */
7722     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7723     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7724     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7725     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7726     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7727     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7728     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7729     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7730     /* c0 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* c8 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     /* d0 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* d8 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7762     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7763     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7764     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7765     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7766     /* e0 */
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     /* e8 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* f0 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* f8 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802   },
7803   /* VEX_0F3A */
7804   {
7805     /* 00 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7811     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7812     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7813     { Bad_Opcode },
7814     /* 08 */
7815     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7816     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7817     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7818     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7819     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7820     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7821     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7822     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7823     /* 10 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7829     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7830     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7831     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7832     /* 18 */
7833     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7834     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 20 */
7842     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7843     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7844     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 28 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 30 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 38 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 40 */
7878     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7879     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7880     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7881     { Bad_Opcode },
7882     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 48 */
7887     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7888     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7889     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7890     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7891     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 50 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 58 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7910     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7911     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7912     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7913     /* 60 */
7914     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7915     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7916     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7917     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* 68 */
7923     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7924     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7925     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7926     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7927     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7928     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7929     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7930     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7931     /* 70 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* 78 */
7941     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7942     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7943     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7944     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7945     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7946     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7947     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7948     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7949     /* 80 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* 88 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* 90 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* 98 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* a0 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* a8 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* b0 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* b8 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* c0 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* c8 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* d0 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* d8 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8057     /* e0 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* e8 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* f0 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* f8 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093   },
8094 };
8095
8096 static const struct dis386 vex_len_table[][2] = {
8097   /* VEX_LEN_10_P_1 */
8098   {
8099     { VEX_W_TABLE (VEX_W_10_P_1) },
8100     { VEX_W_TABLE (VEX_W_10_P_1) },
8101   },
8102
8103   /* VEX_LEN_10_P_3 */
8104   {
8105     { VEX_W_TABLE (VEX_W_10_P_3) },
8106     { VEX_W_TABLE (VEX_W_10_P_3) },
8107   },
8108
8109   /* VEX_LEN_11_P_1 */
8110   {
8111     { VEX_W_TABLE (VEX_W_11_P_1) },
8112     { VEX_W_TABLE (VEX_W_11_P_1) },
8113   },
8114
8115   /* VEX_LEN_11_P_3 */
8116   {
8117     { VEX_W_TABLE (VEX_W_11_P_3) },
8118     { VEX_W_TABLE (VEX_W_11_P_3) },
8119   },
8120
8121   /* VEX_LEN_12_P_0_M_0 */
8122   {
8123     { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8124   },
8125
8126   /* VEX_LEN_12_P_0_M_1 */
8127   {
8128     { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8129   },
8130
8131   /* VEX_LEN_12_P_2 */
8132   {
8133     { VEX_W_TABLE (VEX_W_12_P_2) },
8134   },
8135
8136   /* VEX_LEN_13_M_0 */
8137   {
8138     { VEX_W_TABLE (VEX_W_13_M_0) },
8139   },
8140
8141   /* VEX_LEN_16_P_0_M_0 */
8142   {
8143     { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8144   },
8145
8146   /* VEX_LEN_16_P_0_M_1 */
8147   {
8148     { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8149   },
8150
8151   /* VEX_LEN_16_P_2 */
8152   {
8153     { VEX_W_TABLE (VEX_W_16_P_2) },
8154   },
8155
8156   /* VEX_LEN_17_M_0 */
8157   {
8158     { VEX_W_TABLE (VEX_W_17_M_0) },
8159   },
8160
8161   /* VEX_LEN_2A_P_1 */
8162   {
8163     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8164     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8165   },
8166
8167   /* VEX_LEN_2A_P_3 */
8168   {
8169     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8170     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8171   },
8172
8173   /* VEX_LEN_2C_P_1 */
8174   {
8175     { "vcvttss2siY",    { Gv, EXdScalar } },
8176     { "vcvttss2siY",    { Gv, EXdScalar } },
8177   },
8178
8179   /* VEX_LEN_2C_P_3 */
8180   {
8181     { "vcvttsd2siY",    { Gv, EXqScalar } },
8182     { "vcvttsd2siY",    { Gv, EXqScalar } },
8183   },
8184
8185   /* VEX_LEN_2D_P_1 */
8186   {
8187     { "vcvtss2siY",     { Gv, EXdScalar } },
8188     { "vcvtss2siY",     { Gv, EXdScalar } },
8189   },
8190
8191   /* VEX_LEN_2D_P_3 */
8192   {
8193     { "vcvtsd2siY",     { Gv, EXqScalar } },
8194     { "vcvtsd2siY",     { Gv, EXqScalar } },
8195   },
8196
8197   /* VEX_LEN_2E_P_0 */
8198   {
8199     { VEX_W_TABLE (VEX_W_2E_P_0) },
8200     { VEX_W_TABLE (VEX_W_2E_P_0) },
8201   },
8202
8203   /* VEX_LEN_2E_P_2 */
8204   {
8205     { VEX_W_TABLE (VEX_W_2E_P_2) },
8206     { VEX_W_TABLE (VEX_W_2E_P_2) },
8207   },
8208
8209   /* VEX_LEN_2F_P_0 */
8210   {
8211     { VEX_W_TABLE (VEX_W_2F_P_0) },
8212     { VEX_W_TABLE (VEX_W_2F_P_0) },
8213   },
8214
8215   /* VEX_LEN_2F_P_2 */
8216   {
8217     { VEX_W_TABLE (VEX_W_2F_P_2) },
8218     { VEX_W_TABLE (VEX_W_2F_P_2) },
8219   },
8220
8221   /* VEX_LEN_51_P_1 */
8222   {
8223     { VEX_W_TABLE (VEX_W_51_P_1) },
8224     { VEX_W_TABLE (VEX_W_51_P_1) },
8225   },
8226
8227   /* VEX_LEN_51_P_3 */
8228   {
8229     { VEX_W_TABLE (VEX_W_51_P_3) },
8230     { VEX_W_TABLE (VEX_W_51_P_3) },
8231   },
8232
8233   /* VEX_LEN_52_P_1 */
8234   {
8235     { VEX_W_TABLE (VEX_W_52_P_1) },
8236     { VEX_W_TABLE (VEX_W_52_P_1) },
8237   },
8238
8239   /* VEX_LEN_53_P_1 */
8240   {
8241     { VEX_W_TABLE (VEX_W_53_P_1) },
8242     { VEX_W_TABLE (VEX_W_53_P_1) },
8243   },
8244
8245   /* VEX_LEN_58_P_1 */
8246   {
8247     { VEX_W_TABLE (VEX_W_58_P_1) },
8248     { VEX_W_TABLE (VEX_W_58_P_1) },
8249   },
8250
8251   /* VEX_LEN_58_P_3 */
8252   {
8253     { VEX_W_TABLE (VEX_W_58_P_3) },
8254     { VEX_W_TABLE (VEX_W_58_P_3) },
8255   },
8256
8257   /* VEX_LEN_59_P_1 */
8258   {
8259     { VEX_W_TABLE (VEX_W_59_P_1) },
8260     { VEX_W_TABLE (VEX_W_59_P_1) },
8261   },
8262
8263   /* VEX_LEN_59_P_3 */
8264   {
8265     { VEX_W_TABLE (VEX_W_59_P_3) },
8266     { VEX_W_TABLE (VEX_W_59_P_3) },
8267   },
8268
8269   /* VEX_LEN_5A_P_1 */
8270   {
8271     { VEX_W_TABLE (VEX_W_5A_P_1) },
8272     { VEX_W_TABLE (VEX_W_5A_P_1) },
8273   },
8274
8275   /* VEX_LEN_5A_P_3 */
8276   {
8277     { VEX_W_TABLE (VEX_W_5A_P_3) },
8278     { VEX_W_TABLE (VEX_W_5A_P_3) },
8279   },
8280
8281   /* VEX_LEN_5C_P_1 */
8282   {
8283     { VEX_W_TABLE (VEX_W_5C_P_1) },
8284     { VEX_W_TABLE (VEX_W_5C_P_1) },
8285   },
8286
8287   /* VEX_LEN_5C_P_3 */
8288   {
8289     { VEX_W_TABLE (VEX_W_5C_P_3) },
8290     { VEX_W_TABLE (VEX_W_5C_P_3) },
8291   },
8292
8293   /* VEX_LEN_5D_P_1 */
8294   {
8295     { VEX_W_TABLE (VEX_W_5D_P_1) },
8296     { VEX_W_TABLE (VEX_W_5D_P_1) },
8297   },
8298
8299   /* VEX_LEN_5D_P_3 */
8300   {
8301     { VEX_W_TABLE (VEX_W_5D_P_3) },
8302     { VEX_W_TABLE (VEX_W_5D_P_3) },
8303   },
8304
8305   /* VEX_LEN_5E_P_1 */
8306   {
8307     { VEX_W_TABLE (VEX_W_5E_P_1) },
8308     { VEX_W_TABLE (VEX_W_5E_P_1) },
8309   },
8310
8311   /* VEX_LEN_5E_P_3 */
8312   {
8313     { VEX_W_TABLE (VEX_W_5E_P_3) },
8314     { VEX_W_TABLE (VEX_W_5E_P_3) },
8315   },
8316
8317   /* VEX_LEN_5F_P_1 */
8318   {
8319     { VEX_W_TABLE (VEX_W_5F_P_1) },
8320     { VEX_W_TABLE (VEX_W_5F_P_1) },
8321   },
8322
8323   /* VEX_LEN_5F_P_3 */
8324   {
8325     { VEX_W_TABLE (VEX_W_5F_P_3) },
8326     { VEX_W_TABLE (VEX_W_5F_P_3) },
8327   },
8328
8329   /* VEX_LEN_60_P_2 */
8330   {
8331     { VEX_W_TABLE (VEX_W_60_P_2) },
8332   },
8333
8334   /* VEX_LEN_61_P_2 */
8335   {
8336     { VEX_W_TABLE (VEX_W_61_P_2) },
8337   },
8338
8339   /* VEX_LEN_62_P_2 */
8340   {
8341     { VEX_W_TABLE (VEX_W_62_P_2) },
8342   },
8343
8344   /* VEX_LEN_63_P_2 */
8345   {
8346     { VEX_W_TABLE (VEX_W_63_P_2) },
8347   },
8348
8349   /* VEX_LEN_64_P_2 */
8350   {
8351     { VEX_W_TABLE (VEX_W_64_P_2) },
8352   },
8353
8354   /* VEX_LEN_65_P_2 */
8355   {
8356     { VEX_W_TABLE (VEX_W_65_P_2) },
8357   },
8358
8359   /* VEX_LEN_66_P_2 */
8360   {
8361     { VEX_W_TABLE (VEX_W_66_P_2) },
8362   },
8363
8364   /* VEX_LEN_67_P_2 */
8365   {
8366     { VEX_W_TABLE (VEX_W_67_P_2) },
8367   },
8368
8369   /* VEX_LEN_68_P_2 */
8370   {
8371     { VEX_W_TABLE (VEX_W_68_P_2) },
8372   },
8373
8374   /* VEX_LEN_69_P_2 */
8375   {
8376     { VEX_W_TABLE (VEX_W_69_P_2) },
8377   },
8378
8379   /* VEX_LEN_6A_P_2 */
8380   {
8381     { VEX_W_TABLE (VEX_W_6A_P_2) },
8382   },
8383
8384   /* VEX_LEN_6B_P_2 */
8385   {
8386     { VEX_W_TABLE (VEX_W_6B_P_2) },
8387   },
8388
8389   /* VEX_LEN_6C_P_2 */
8390   {
8391     { VEX_W_TABLE (VEX_W_6C_P_2) },
8392   },
8393
8394   /* VEX_LEN_6D_P_2 */
8395   {
8396     { VEX_W_TABLE (VEX_W_6D_P_2) },
8397   },
8398
8399   /* VEX_LEN_6E_P_2 */
8400   {
8401     { "vmovK",          { XMScalar, Edq } },
8402     { "vmovK",          { XMScalar, Edq } },
8403   },
8404
8405   /* VEX_LEN_70_P_1 */
8406   {
8407     { VEX_W_TABLE (VEX_W_70_P_1) },
8408   },
8409
8410   /* VEX_LEN_70_P_2 */
8411   {
8412     { VEX_W_TABLE (VEX_W_70_P_2) },
8413   },
8414
8415   /* VEX_LEN_70_P_3 */
8416   {
8417     { VEX_W_TABLE (VEX_W_70_P_3) },
8418   },
8419
8420   /* VEX_LEN_71_R_2_P_2 */
8421   {
8422     { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8423   },
8424
8425   /* VEX_LEN_71_R_4_P_2 */
8426   {
8427     { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8428   },
8429
8430   /* VEX_LEN_71_R_6_P_2 */
8431   {
8432     { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8433   },
8434
8435   /* VEX_LEN_72_R_2_P_2 */
8436   {
8437     { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8438   },
8439
8440   /* VEX_LEN_72_R_4_P_2 */
8441   {
8442     { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8443   },
8444
8445   /* VEX_LEN_72_R_6_P_2 */
8446   {
8447     { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8448   },
8449
8450   /* VEX_LEN_73_R_2_P_2 */
8451   {
8452     { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8453   },
8454
8455   /* VEX_LEN_73_R_3_P_2 */
8456   {
8457     { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8458   },
8459
8460   /* VEX_LEN_73_R_6_P_2 */
8461   {
8462     { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8463   },
8464
8465   /* VEX_LEN_73_R_7_P_2 */
8466   {
8467     { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8468   },
8469
8470   /* VEX_LEN_74_P_2 */
8471   {
8472     { VEX_W_TABLE (VEX_W_74_P_2) },
8473   },
8474
8475   /* VEX_LEN_75_P_2 */
8476   {
8477     { VEX_W_TABLE (VEX_W_75_P_2) },
8478   },
8479
8480   /* VEX_LEN_76_P_2 */
8481   {
8482     { VEX_W_TABLE (VEX_W_76_P_2) },
8483   },
8484
8485   /* VEX_LEN_7E_P_1 */
8486   {
8487     { VEX_W_TABLE (VEX_W_7E_P_1) },
8488     { VEX_W_TABLE (VEX_W_7E_P_1) },
8489   },
8490
8491   /* VEX_LEN_7E_P_2 */
8492   {
8493     { "vmovK",          { Edq, XMScalar } },
8494     { "vmovK",          { Edq, XMScalar } },
8495   },
8496
8497   /* VEX_LEN_AE_R_2_M_0 */
8498   {
8499     { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8500   },
8501
8502   /* VEX_LEN_AE_R_3_M_0 */
8503   {
8504     { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8505   },
8506
8507   /* VEX_LEN_C2_P_1 */
8508   {
8509     { VEX_W_TABLE (VEX_W_C2_P_1) },
8510     { VEX_W_TABLE (VEX_W_C2_P_1) },
8511   },
8512
8513   /* VEX_LEN_C2_P_3 */
8514   {
8515     { VEX_W_TABLE (VEX_W_C2_P_3) },
8516     { VEX_W_TABLE (VEX_W_C2_P_3) },
8517   },
8518
8519   /* VEX_LEN_C4_P_2 */
8520   {
8521     { VEX_W_TABLE (VEX_W_C4_P_2) },
8522   },
8523
8524   /* VEX_LEN_C5_P_2 */
8525   {
8526     { VEX_W_TABLE (VEX_W_C5_P_2) },
8527   },
8528
8529   /* VEX_LEN_D1_P_2 */
8530   {
8531     { VEX_W_TABLE (VEX_W_D1_P_2) },
8532   },
8533
8534   /* VEX_LEN_D2_P_2 */
8535   {
8536     { VEX_W_TABLE (VEX_W_D2_P_2) },
8537   },
8538
8539   /* VEX_LEN_D3_P_2 */
8540   {
8541     { VEX_W_TABLE (VEX_W_D3_P_2) },
8542   },
8543
8544   /* VEX_LEN_D4_P_2 */
8545   {
8546     { VEX_W_TABLE (VEX_W_D4_P_2) },
8547   },
8548
8549   /* VEX_LEN_D5_P_2 */
8550   {
8551     { VEX_W_TABLE (VEX_W_D5_P_2) },
8552   },
8553
8554   /* VEX_LEN_D6_P_2 */
8555   {
8556     { VEX_W_TABLE (VEX_W_D6_P_2) },
8557     { VEX_W_TABLE (VEX_W_D6_P_2) },
8558   },
8559
8560   /* VEX_LEN_D7_P_2_M_1 */
8561   {
8562     { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8563   },
8564
8565   /* VEX_LEN_D8_P_2 */
8566   {
8567     { VEX_W_TABLE (VEX_W_D8_P_2) },
8568   },
8569
8570   /* VEX_LEN_D9_P_2 */
8571   {
8572     { VEX_W_TABLE (VEX_W_D9_P_2) },
8573   },
8574
8575   /* VEX_LEN_DA_P_2 */
8576   {
8577     { VEX_W_TABLE (VEX_W_DA_P_2) },
8578   },
8579
8580   /* VEX_LEN_DB_P_2 */
8581   {
8582     { VEX_W_TABLE (VEX_W_DB_P_2) },
8583   },
8584
8585   /* VEX_LEN_DC_P_2 */
8586   {
8587     { VEX_W_TABLE (VEX_W_DC_P_2) },
8588   },
8589
8590   /* VEX_LEN_DD_P_2 */
8591   {
8592     { VEX_W_TABLE (VEX_W_DD_P_2) },
8593   },
8594
8595   /* VEX_LEN_DE_P_2 */
8596   {
8597     { VEX_W_TABLE (VEX_W_DE_P_2) },
8598   },
8599
8600   /* VEX_LEN_DF_P_2 */
8601   {
8602     { VEX_W_TABLE (VEX_W_DF_P_2) },
8603   },
8604
8605   /* VEX_LEN_E0_P_2 */
8606   {
8607     { VEX_W_TABLE (VEX_W_E0_P_2) },
8608   },
8609
8610   /* VEX_LEN_E1_P_2 */
8611   {
8612     { VEX_W_TABLE (VEX_W_E1_P_2) },
8613   },
8614
8615   /* VEX_LEN_E2_P_2 */
8616   {
8617     { VEX_W_TABLE (VEX_W_E2_P_2) },
8618   },
8619
8620   /* VEX_LEN_E3_P_2 */
8621   {
8622     { VEX_W_TABLE (VEX_W_E3_P_2) },
8623   },
8624
8625   /* VEX_LEN_E4_P_2 */
8626   {
8627     { VEX_W_TABLE (VEX_W_E4_P_2) },
8628   },
8629
8630   /* VEX_LEN_E5_P_2 */
8631   {
8632     { VEX_W_TABLE (VEX_W_E5_P_2) },
8633   },
8634
8635   /* VEX_LEN_E8_P_2 */
8636   {
8637     { VEX_W_TABLE (VEX_W_E8_P_2) },
8638   },
8639
8640   /* VEX_LEN_E9_P_2 */
8641   {
8642     { VEX_W_TABLE (VEX_W_E9_P_2) },
8643   },
8644
8645   /* VEX_LEN_EA_P_2 */
8646   {
8647     { VEX_W_TABLE (VEX_W_EA_P_2) },
8648   },
8649
8650   /* VEX_LEN_EB_P_2 */
8651   {
8652     { VEX_W_TABLE (VEX_W_EB_P_2) },
8653   },
8654
8655   /* VEX_LEN_EC_P_2 */
8656   {
8657     { VEX_W_TABLE (VEX_W_EC_P_2) },
8658   },
8659
8660   /* VEX_LEN_ED_P_2 */
8661   {
8662     { VEX_W_TABLE (VEX_W_ED_P_2) },
8663   },
8664
8665   /* VEX_LEN_EE_P_2 */
8666   {
8667     { VEX_W_TABLE (VEX_W_EE_P_2) },
8668   },
8669
8670   /* VEX_LEN_EF_P_2 */
8671   {
8672     { VEX_W_TABLE (VEX_W_EF_P_2) },
8673   },
8674
8675   /* VEX_LEN_F1_P_2 */
8676   {
8677     { VEX_W_TABLE (VEX_W_F1_P_2) },
8678   },
8679
8680   /* VEX_LEN_F2_P_2 */
8681   {
8682     { VEX_W_TABLE (VEX_W_F2_P_2) },
8683   },
8684
8685   /* VEX_LEN_F3_P_2 */
8686   {
8687     { VEX_W_TABLE (VEX_W_F3_P_2) },
8688   },
8689
8690   /* VEX_LEN_F4_P_2 */
8691   {
8692     { VEX_W_TABLE (VEX_W_F4_P_2) },
8693   },
8694
8695   /* VEX_LEN_F5_P_2 */
8696   {
8697     { VEX_W_TABLE (VEX_W_F5_P_2) },
8698   },
8699
8700   /* VEX_LEN_F6_P_2 */
8701   {
8702     { VEX_W_TABLE (VEX_W_F6_P_2) },
8703   },
8704
8705   /* VEX_LEN_F7_P_2 */
8706   {
8707     { VEX_W_TABLE (VEX_W_F7_P_2) },
8708   },
8709
8710   /* VEX_LEN_F8_P_2 */
8711   {
8712     { VEX_W_TABLE (VEX_W_F8_P_2) },
8713   },
8714
8715   /* VEX_LEN_F9_P_2 */
8716   {
8717     { VEX_W_TABLE (VEX_W_F9_P_2) },
8718   },
8719
8720   /* VEX_LEN_FA_P_2 */
8721   {
8722     { VEX_W_TABLE (VEX_W_FA_P_2) },
8723   },
8724
8725   /* VEX_LEN_FB_P_2 */
8726   {
8727     { VEX_W_TABLE (VEX_W_FB_P_2) },
8728   },
8729
8730   /* VEX_LEN_FC_P_2 */
8731   {
8732     { VEX_W_TABLE (VEX_W_FC_P_2) },
8733   },
8734
8735   /* VEX_LEN_FD_P_2 */
8736   {
8737     { VEX_W_TABLE (VEX_W_FD_P_2) },
8738   },
8739
8740   /* VEX_LEN_FE_P_2 */
8741   {
8742     { VEX_W_TABLE (VEX_W_FE_P_2) },
8743   },
8744
8745   /* VEX_LEN_3800_P_2 */
8746   {
8747     { VEX_W_TABLE (VEX_W_3800_P_2) },
8748   },
8749
8750   /* VEX_LEN_3801_P_2 */
8751   {
8752     { VEX_W_TABLE (VEX_W_3801_P_2) },
8753   },
8754
8755   /* VEX_LEN_3802_P_2 */
8756   {
8757     { VEX_W_TABLE (VEX_W_3802_P_2) },
8758   },
8759
8760   /* VEX_LEN_3803_P_2 */
8761   {
8762     { VEX_W_TABLE (VEX_W_3803_P_2) },
8763   },
8764
8765   /* VEX_LEN_3804_P_2 */
8766   {
8767     { VEX_W_TABLE (VEX_W_3804_P_2) },
8768   },
8769
8770   /* VEX_LEN_3805_P_2 */
8771   {
8772     { VEX_W_TABLE (VEX_W_3805_P_2) },
8773   },
8774
8775   /* VEX_LEN_3806_P_2 */
8776   {
8777     { VEX_W_TABLE (VEX_W_3806_P_2) },
8778   },
8779
8780   /* VEX_LEN_3807_P_2 */
8781   {
8782     { VEX_W_TABLE (VEX_W_3807_P_2) },
8783   },
8784
8785   /* VEX_LEN_3808_P_2 */
8786   {
8787     { VEX_W_TABLE (VEX_W_3808_P_2) },
8788   },
8789
8790   /* VEX_LEN_3809_P_2 */
8791   {
8792     { VEX_W_TABLE (VEX_W_3809_P_2) },
8793   },
8794
8795   /* VEX_LEN_380A_P_2 */
8796   {
8797     { VEX_W_TABLE (VEX_W_380A_P_2) },
8798   },
8799
8800   /* VEX_LEN_380B_P_2 */
8801   {
8802     { VEX_W_TABLE (VEX_W_380B_P_2) },
8803   },
8804
8805   /* VEX_LEN_3819_P_2_M_0 */
8806   {
8807     { Bad_Opcode },
8808     { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8809   },
8810
8811   /* VEX_LEN_381A_P_2_M_0 */
8812   {
8813     { Bad_Opcode },
8814     { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8815   },
8816
8817   /* VEX_LEN_381C_P_2 */
8818   {
8819     { VEX_W_TABLE (VEX_W_381C_P_2) },
8820   },
8821
8822   /* VEX_LEN_381D_P_2 */
8823   {
8824     { VEX_W_TABLE (VEX_W_381D_P_2) },
8825   },
8826
8827   /* VEX_LEN_381E_P_2 */
8828   {
8829     { VEX_W_TABLE (VEX_W_381E_P_2) },
8830   },
8831
8832   /* VEX_LEN_3820_P_2 */
8833   {
8834     { VEX_W_TABLE (VEX_W_3820_P_2) },
8835   },
8836
8837   /* VEX_LEN_3821_P_2 */
8838   {
8839     { VEX_W_TABLE (VEX_W_3821_P_2) },
8840   },
8841
8842   /* VEX_LEN_3822_P_2 */
8843   {
8844     { VEX_W_TABLE (VEX_W_3822_P_2) },
8845   },
8846
8847   /* VEX_LEN_3823_P_2 */
8848   {
8849     { VEX_W_TABLE (VEX_W_3823_P_2) },
8850   },
8851
8852   /* VEX_LEN_3824_P_2 */
8853   {
8854     { VEX_W_TABLE (VEX_W_3824_P_2) },
8855   },
8856
8857   /* VEX_LEN_3825_P_2 */
8858   {
8859     { VEX_W_TABLE (VEX_W_3825_P_2) },
8860   },
8861
8862   /* VEX_LEN_3828_P_2 */
8863   {
8864     { VEX_W_TABLE (VEX_W_3828_P_2) },
8865   },
8866
8867   /* VEX_LEN_3829_P_2 */
8868   {
8869     { VEX_W_TABLE (VEX_W_3829_P_2) },
8870   },
8871
8872   /* VEX_LEN_382A_P_2_M_0 */
8873   {
8874     { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8875   },
8876
8877   /* VEX_LEN_382B_P_2 */
8878   {
8879     { VEX_W_TABLE (VEX_W_382B_P_2) },
8880   },
8881
8882   /* VEX_LEN_3830_P_2 */
8883   {
8884     { VEX_W_TABLE (VEX_W_3830_P_2) },
8885   },
8886
8887   /* VEX_LEN_3831_P_2 */
8888   {
8889     { VEX_W_TABLE (VEX_W_3831_P_2) },
8890   },
8891
8892   /* VEX_LEN_3832_P_2 */
8893   {
8894     { VEX_W_TABLE (VEX_W_3832_P_2) },
8895   },
8896
8897   /* VEX_LEN_3833_P_2 */
8898   {
8899     { VEX_W_TABLE (VEX_W_3833_P_2) },
8900   },
8901
8902   /* VEX_LEN_3834_P_2 */
8903   {
8904     { VEX_W_TABLE (VEX_W_3834_P_2) },
8905   },
8906
8907   /* VEX_LEN_3835_P_2 */
8908   {
8909     { VEX_W_TABLE (VEX_W_3835_P_2) },
8910   },
8911
8912   /* VEX_LEN_3837_P_2 */
8913   {
8914     { VEX_W_TABLE (VEX_W_3837_P_2) },
8915   },
8916
8917   /* VEX_LEN_3838_P_2 */
8918   {
8919     { VEX_W_TABLE (VEX_W_3838_P_2) },
8920   },
8921
8922   /* VEX_LEN_3839_P_2 */
8923   {
8924     { VEX_W_TABLE (VEX_W_3839_P_2) },
8925   },
8926
8927   /* VEX_LEN_383A_P_2 */
8928   {
8929     { VEX_W_TABLE (VEX_W_383A_P_2) },
8930   },
8931
8932   /* VEX_LEN_383B_P_2 */
8933   {
8934     { VEX_W_TABLE (VEX_W_383B_P_2) },
8935   },
8936
8937   /* VEX_LEN_383C_P_2 */
8938   {
8939     { VEX_W_TABLE (VEX_W_383C_P_2) },
8940   },
8941
8942   /* VEX_LEN_383D_P_2 */
8943   {
8944     { VEX_W_TABLE (VEX_W_383D_P_2) },
8945   },
8946
8947   /* VEX_LEN_383E_P_2 */
8948   {
8949     { VEX_W_TABLE (VEX_W_383E_P_2) },
8950   },
8951
8952   /* VEX_LEN_383F_P_2 */
8953   {
8954     { VEX_W_TABLE (VEX_W_383F_P_2) },
8955   },
8956
8957   /* VEX_LEN_3840_P_2 */
8958   {
8959     { VEX_W_TABLE (VEX_W_3840_P_2) },
8960   },
8961
8962   /* VEX_LEN_3841_P_2 */
8963   {
8964     { VEX_W_TABLE (VEX_W_3841_P_2) },
8965   },
8966
8967   /* VEX_LEN_38DB_P_2 */
8968   {
8969     { VEX_W_TABLE (VEX_W_38DB_P_2) },
8970   },
8971
8972   /* VEX_LEN_38DC_P_2 */
8973   {
8974     { VEX_W_TABLE (VEX_W_38DC_P_2) },
8975   },
8976
8977   /* VEX_LEN_38DD_P_2 */
8978   {
8979     { VEX_W_TABLE (VEX_W_38DD_P_2) },
8980   },
8981
8982   /* VEX_LEN_38DE_P_2 */
8983   {
8984     { VEX_W_TABLE (VEX_W_38DE_P_2) },
8985   },
8986
8987   /* VEX_LEN_38DF_P_2 */
8988   {
8989     { VEX_W_TABLE (VEX_W_38DF_P_2) },
8990   },
8991
8992   /* VEX_LEN_3A06_P_2 */
8993   {
8994     { Bad_Opcode },
8995     { VEX_W_TABLE (VEX_W_3A06_P_2) },
8996   },
8997
8998   /* VEX_LEN_3A0A_P_2 */
8999   {
9000     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
9001     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
9002   },
9003
9004   /* VEX_LEN_3A0B_P_2 */
9005   {
9006     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9007     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9008   },
9009
9010   /* VEX_LEN_3A0E_P_2 */
9011   {
9012     { VEX_W_TABLE (VEX_W_3A0E_P_2) },
9013   },
9014
9015   /* VEX_LEN_3A0F_P_2 */
9016   {
9017     { VEX_W_TABLE (VEX_W_3A0F_P_2) },
9018   },
9019
9020   /* VEX_LEN_3A14_P_2 */
9021   {
9022     { VEX_W_TABLE (VEX_W_3A14_P_2) },
9023   },
9024
9025   /* VEX_LEN_3A15_P_2 */
9026   {
9027     { VEX_W_TABLE (VEX_W_3A15_P_2) },
9028   },
9029
9030   /* VEX_LEN_3A16_P_2  */
9031   {
9032     { "vpextrK",        { Edq, XM, Ib } },
9033   },
9034
9035   /* VEX_LEN_3A17_P_2 */
9036   {
9037     { "vextractps",     { Edqd, XM, Ib } },
9038   },
9039
9040   /* VEX_LEN_3A18_P_2 */
9041   {
9042     { Bad_Opcode },
9043     { VEX_W_TABLE (VEX_W_3A18_P_2) },
9044   },
9045
9046   /* VEX_LEN_3A19_P_2 */
9047   {
9048     { Bad_Opcode },
9049     { VEX_W_TABLE (VEX_W_3A19_P_2) },
9050   },
9051
9052   /* VEX_LEN_3A20_P_2 */
9053   {
9054     { VEX_W_TABLE (VEX_W_3A20_P_2) },
9055   },
9056
9057   /* VEX_LEN_3A21_P_2 */
9058   {
9059     { VEX_W_TABLE (VEX_W_3A21_P_2) },
9060   },
9061
9062   /* VEX_LEN_3A22_P_2 */
9063   {
9064     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9065   },
9066
9067   /* VEX_LEN_3A41_P_2 */
9068   {
9069     { VEX_W_TABLE (VEX_W_3A41_P_2) },
9070   },
9071
9072   /* VEX_LEN_3A42_P_2 */
9073   {
9074     { VEX_W_TABLE (VEX_W_3A42_P_2) },
9075   },
9076
9077   /* VEX_LEN_3A44_P_2 */
9078   {
9079     { VEX_W_TABLE (VEX_W_3A44_P_2) },
9080   },
9081
9082   /* VEX_LEN_3A4C_P_2 */
9083   {
9084     { VEX_W_TABLE (VEX_W_3A4C_P_2) },
9085   },
9086
9087   /* VEX_LEN_3A60_P_2 */
9088   {
9089     { VEX_W_TABLE (VEX_W_3A60_P_2) },
9090   },
9091
9092   /* VEX_LEN_3A61_P_2 */
9093   {
9094     { VEX_W_TABLE (VEX_W_3A61_P_2) },
9095   },
9096
9097   /* VEX_LEN_3A62_P_2 */
9098   {
9099     { VEX_W_TABLE (VEX_W_3A62_P_2) },
9100   },
9101
9102   /* VEX_LEN_3A63_P_2 */
9103   {
9104     { VEX_W_TABLE (VEX_W_3A63_P_2) },
9105   },
9106
9107   /* VEX_LEN_3A6A_P_2 */
9108   {
9109     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9110   },
9111
9112   /* VEX_LEN_3A6B_P_2 */
9113   {
9114     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9115   },
9116
9117   /* VEX_LEN_3A6E_P_2 */
9118   {
9119     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9120   },
9121
9122   /* VEX_LEN_3A6F_P_2 */
9123   {
9124     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9125   },
9126
9127   /* VEX_LEN_3A7A_P_2 */
9128   {
9129     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9130   },
9131
9132   /* VEX_LEN_3A7B_P_2 */
9133   {
9134     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9135   },
9136
9137   /* VEX_LEN_3A7E_P_2 */
9138   {
9139     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9140   },
9141
9142   /* VEX_LEN_3A7F_P_2 */
9143   {
9144     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9145   },
9146
9147   /* VEX_LEN_3ADF_P_2 */
9148   {
9149     { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9150   },
9151
9152   /* VEX_LEN_XOP_09_80 */
9153   {
9154     { "vfrczps",        { XM, EXxmm } },
9155     { "vfrczps",        { XM, EXymmq } },
9156   },
9157
9158   /* VEX_LEN_XOP_09_81 */
9159   {
9160     { "vfrczpd",        { XM, EXxmm } },
9161     { "vfrczpd",        { XM, EXymmq } },
9162   },
9163 };
9164
9165 static const struct dis386 vex_w_table[][2] = {
9166   {
9167     /* VEX_W_10_P_0 */
9168     { "vmovups",        { XM, EXx } },
9169   },
9170   {
9171     /* VEX_W_10_P_1 */
9172     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9173   },
9174   {
9175     /* VEX_W_10_P_2 */
9176     { "vmovupd",        { XM, EXx } },
9177   },
9178   {
9179     /* VEX_W_10_P_3 */
9180     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9181   },
9182   {
9183     /* VEX_W_11_P_0 */
9184     { "vmovups",        { EXxS, XM } },
9185   },
9186   {
9187     /* VEX_W_11_P_1 */
9188     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9189   },
9190   {
9191     /* VEX_W_11_P_2 */
9192     { "vmovupd",        { EXxS, XM } },
9193   },
9194   {
9195     /* VEX_W_11_P_3 */
9196     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9197   },
9198   {
9199     /* VEX_W_12_P_0_M_0 */
9200     { "vmovlps",        { XM, Vex128, EXq } },
9201   },
9202   {
9203     /* VEX_W_12_P_0_M_1 */
9204     { "vmovhlps",       { XM, Vex128, EXq } },
9205   },
9206   {
9207     /* VEX_W_12_P_1 */
9208     { "vmovsldup",      { XM, EXx } },
9209   },
9210   {
9211     /* VEX_W_12_P_2 */
9212     { "vmovlpd",        { XM, Vex128, EXq } },
9213   },
9214   {
9215     /* VEX_W_12_P_3 */
9216     { "vmovddup",       { XM, EXymmq } },
9217   },
9218   {
9219     /* VEX_W_13_M_0 */
9220     { "vmovlpX",        { EXq, XM } },
9221   },
9222   {
9223     /* VEX_W_14 */
9224     { "vunpcklpX",      { XM, Vex, EXx } },
9225   },
9226   {
9227     /* VEX_W_15 */
9228     { "vunpckhpX",      { XM, Vex, EXx } },
9229   },
9230   {
9231     /* VEX_W_16_P_0_M_0 */
9232     { "vmovhps",        { XM, Vex128, EXq } },
9233   },
9234   {
9235     /* VEX_W_16_P_0_M_1 */
9236     { "vmovlhps",       { XM, Vex128, EXq } },
9237   },
9238   {
9239     /* VEX_W_16_P_1 */
9240     { "vmovshdup",      { XM, EXx } },
9241   },
9242   {
9243     /* VEX_W_16_P_2 */
9244     { "vmovhpd",        { XM, Vex128, EXq } },
9245   },
9246   {
9247     /* VEX_W_17_M_0 */
9248     { "vmovhpX",        { EXq, XM } },
9249   },
9250   {
9251     /* VEX_W_28 */
9252     { "vmovapX",        { XM, EXx } },
9253   },
9254   {
9255     /* VEX_W_29 */
9256     { "vmovapX",        { EXxS, XM } },
9257   },
9258   {
9259     /* VEX_W_2B_M_0 */
9260     { "vmovntpX",       { Mx, XM } },
9261   },
9262   {
9263     /* VEX_W_2E_P_0 */
9264     { "vucomiss",       { XMScalar, EXdScalar } },
9265   },
9266   {
9267     /* VEX_W_2E_P_2 */
9268     { "vucomisd",       { XMScalar, EXqScalar } },
9269   },
9270   {
9271     /* VEX_W_2F_P_0 */
9272     { "vcomiss",        { XMScalar, EXdScalar } },
9273   },
9274   {
9275     /* VEX_W_2F_P_2 */
9276     { "vcomisd",        { XMScalar, EXqScalar } },
9277   },
9278   {
9279     /* VEX_W_50_M_0 */
9280     { "vmovmskpX",      { Gdq, XS } },
9281   },
9282   {
9283     /* VEX_W_51_P_0 */
9284     { "vsqrtps",        { XM, EXx } },
9285   },
9286   {
9287     /* VEX_W_51_P_1 */
9288     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9289   },
9290   {
9291     /* VEX_W_51_P_2  */
9292     { "vsqrtpd",        { XM, EXx } },
9293   },
9294   {
9295     /* VEX_W_51_P_3 */
9296     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9297   },
9298   {
9299     /* VEX_W_52_P_0 */
9300     { "vrsqrtps",       { XM, EXx } },
9301   },
9302   {
9303     /* VEX_W_52_P_1 */
9304     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9305   },
9306   {
9307     /* VEX_W_53_P_0  */
9308     { "vrcpps",         { XM, EXx } },
9309   },
9310   {
9311     /* VEX_W_53_P_1  */
9312     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9313   },
9314   {
9315     /* VEX_W_58_P_0  */
9316     { "vaddps",         { XM, Vex, EXx } },
9317   },
9318   {
9319     /* VEX_W_58_P_1  */
9320     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9321   },
9322   {
9323     /* VEX_W_58_P_2  */
9324     { "vaddpd",         { XM, Vex, EXx } },
9325   },
9326   {
9327     /* VEX_W_58_P_3  */
9328     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9329   },
9330   {
9331     /* VEX_W_59_P_0  */
9332     { "vmulps",         { XM, Vex, EXx } },
9333   },
9334   {
9335     /* VEX_W_59_P_1  */
9336     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9337   },
9338   {
9339     /* VEX_W_59_P_2  */
9340     { "vmulpd",         { XM, Vex, EXx } },
9341   },
9342   {
9343     /* VEX_W_59_P_3  */
9344     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9345   },
9346   {
9347     /* VEX_W_5A_P_0  */
9348     { "vcvtps2pd",      { XM, EXxmmq } },
9349   },
9350   {
9351     /* VEX_W_5A_P_1  */
9352     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9353   },
9354   {
9355     /* VEX_W_5A_P_3  */
9356     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9357   },
9358   {
9359     /* VEX_W_5B_P_0  */
9360     { "vcvtdq2ps",      { XM, EXx } },
9361   },
9362   {
9363     /* VEX_W_5B_P_1  */
9364     { "vcvttps2dq",     { XM, EXx } },
9365   },
9366   {
9367     /* VEX_W_5B_P_2  */
9368     { "vcvtps2dq",      { XM, EXx } },
9369   },
9370   {
9371     /* VEX_W_5C_P_0  */
9372     { "vsubps",         { XM, Vex, EXx } },
9373   },
9374   {
9375     /* VEX_W_5C_P_1  */
9376     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9377   },
9378   {
9379     /* VEX_W_5C_P_2  */
9380     { "vsubpd",         { XM, Vex, EXx } },
9381   },
9382   {
9383     /* VEX_W_5C_P_3  */
9384     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9385   },
9386   {
9387     /* VEX_W_5D_P_0  */
9388     { "vminps",         { XM, Vex, EXx } },
9389   },
9390   {
9391     /* VEX_W_5D_P_1  */
9392     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9393   },
9394   {
9395     /* VEX_W_5D_P_2  */
9396     { "vminpd",         { XM, Vex, EXx } },
9397   },
9398   {
9399     /* VEX_W_5D_P_3  */
9400     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9401   },
9402   {
9403     /* VEX_W_5E_P_0  */
9404     { "vdivps",         { XM, Vex, EXx } },
9405   },
9406   {
9407     /* VEX_W_5E_P_1  */
9408     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9409   },
9410   {
9411     /* VEX_W_5E_P_2  */
9412     { "vdivpd",         { XM, Vex, EXx } },
9413   },
9414   {
9415     /* VEX_W_5E_P_3  */
9416     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9417   },
9418   {
9419     /* VEX_W_5F_P_0  */
9420     { "vmaxps",         { XM, Vex, EXx } },
9421   },
9422   {
9423     /* VEX_W_5F_P_1  */
9424     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9425   },
9426   {
9427     /* VEX_W_5F_P_2  */
9428     { "vmaxpd",         { XM, Vex, EXx } },
9429   },
9430   {
9431     /* VEX_W_5F_P_3  */
9432     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9433   },
9434   {
9435     /* VEX_W_60_P_2  */
9436     { "vpunpcklbw",     { XM, Vex128, EXx } },
9437   },
9438   {
9439     /* VEX_W_61_P_2  */
9440     { "vpunpcklwd",     { XM, Vex128, EXx } },
9441   },
9442   {
9443     /* VEX_W_62_P_2  */
9444     { "vpunpckldq",     { XM, Vex128, EXx } },
9445   },
9446   {
9447     /* VEX_W_63_P_2  */
9448     { "vpacksswb",      { XM, Vex128, EXx } },
9449   },
9450   {
9451     /* VEX_W_64_P_2  */
9452     { "vpcmpgtb",       { XM, Vex128, EXx } },
9453   },
9454   {
9455     /* VEX_W_65_P_2  */
9456     { "vpcmpgtw",       { XM, Vex128, EXx } },
9457   },
9458   {
9459     /* VEX_W_66_P_2  */
9460     { "vpcmpgtd",       { XM, Vex128, EXx } },
9461   },
9462   {
9463     /* VEX_W_67_P_2  */
9464     { "vpackuswb",      { XM, Vex128, EXx } },
9465   },
9466   {
9467     /* VEX_W_68_P_2  */
9468     { "vpunpckhbw",     { XM, Vex128, EXx } },
9469   },
9470   {
9471     /* VEX_W_69_P_2  */
9472     { "vpunpckhwd",     { XM, Vex128, EXx } },
9473   },
9474   {
9475     /* VEX_W_6A_P_2  */
9476     { "vpunpckhdq",     { XM, Vex128, EXx } },
9477   },
9478   {
9479     /* VEX_W_6B_P_2  */
9480     { "vpackssdw",      { XM, Vex128, EXx } },
9481   },
9482   {
9483     /* VEX_W_6C_P_2  */
9484     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9485   },
9486   {
9487     /* VEX_W_6D_P_2  */
9488     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9489   },
9490   {
9491     /* VEX_W_6F_P_1  */
9492     { "vmovdqu",        { XM, EXx } },
9493   },
9494   {
9495     /* VEX_W_6F_P_2  */
9496     { "vmovdqa",        { XM, EXx } },
9497   },
9498   {
9499     /* VEX_W_70_P_1 */
9500     { "vpshufhw",       { XM, EXx, Ib } },
9501   },
9502   {
9503     /* VEX_W_70_P_2 */
9504     { "vpshufd",        { XM, EXx, Ib } },
9505   },
9506   {
9507     /* VEX_W_70_P_3 */
9508     { "vpshuflw",       { XM, EXx, Ib } },
9509   },
9510   {
9511     /* VEX_W_71_R_2_P_2  */
9512     { "vpsrlw",         { Vex128, XS, Ib } },
9513   },
9514   {
9515     /* VEX_W_71_R_4_P_2  */
9516     { "vpsraw",         { Vex128, XS, Ib } },
9517   },
9518   {
9519     /* VEX_W_71_R_6_P_2  */
9520     { "vpsllw",         { Vex128, XS, Ib } },
9521   },
9522   {
9523     /* VEX_W_72_R_2_P_2  */
9524     { "vpsrld",         { Vex128, XS, Ib } },
9525   },
9526   {
9527     /* VEX_W_72_R_4_P_2  */
9528     { "vpsrad",         { Vex128, XS, Ib } },
9529   },
9530   {
9531     /* VEX_W_72_R_6_P_2  */
9532     { "vpslld",         { Vex128, XS, Ib } },
9533   },
9534   {
9535     /* VEX_W_73_R_2_P_2  */
9536     { "vpsrlq",         { Vex128, XS, Ib } },
9537   },
9538   {
9539     /* VEX_W_73_R_3_P_2  */
9540     { "vpsrldq",        { Vex128, XS, Ib } },
9541   },
9542   {
9543     /* VEX_W_73_R_6_P_2  */
9544     { "vpsllq",         { Vex128, XS, Ib } },
9545   },
9546   {
9547     /* VEX_W_73_R_7_P_2  */
9548     { "vpslldq",        { Vex128, XS, Ib } },
9549   },
9550   {
9551     /* VEX_W_74_P_2 */
9552     { "vpcmpeqb",       { XM, Vex128, EXx } },
9553   },
9554   {
9555     /* VEX_W_75_P_2 */
9556     { "vpcmpeqw",       { XM, Vex128, EXx } },
9557   },
9558   {
9559     /* VEX_W_76_P_2 */
9560     { "vpcmpeqd",       { XM, Vex128, EXx } },
9561   },
9562   {
9563     /* VEX_W_77_P_0 */
9564     { "",               { VZERO } },
9565   },
9566   {
9567     /* VEX_W_7C_P_2 */
9568     { "vhaddpd",        { XM, Vex, EXx } },
9569   },
9570   {
9571     /* VEX_W_7C_P_3 */
9572     { "vhaddps",        { XM, Vex, EXx } },
9573   },
9574   {
9575     /* VEX_W_7D_P_2 */
9576     { "vhsubpd",        { XM, Vex, EXx } },
9577   },
9578   {
9579     /* VEX_W_7D_P_3 */
9580     { "vhsubps",        { XM, Vex, EXx } },
9581   },
9582   {
9583     /* VEX_W_7E_P_1 */
9584     { "vmovq",          { XMScalar, EXqScalar } },
9585   },
9586   {
9587     /* VEX_W_7F_P_1 */
9588     { "vmovdqu",        { EXxS, XM } },
9589   },
9590   {
9591     /* VEX_W_7F_P_2 */
9592     { "vmovdqa",        { EXxS, XM } },
9593   },
9594   {
9595     /* VEX_W_AE_R_2_M_0 */
9596     { "vldmxcsr",       { Md } },
9597   },
9598   {
9599     /* VEX_W_AE_R_3_M_0 */
9600     { "vstmxcsr",       { Md } },
9601   },
9602   {
9603     /* VEX_W_C2_P_0 */
9604     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9605   },
9606   {
9607     /* VEX_W_C2_P_1 */
9608     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9609   },
9610   {
9611     /* VEX_W_C2_P_2 */
9612     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9613   },
9614   {
9615     /* VEX_W_C2_P_3 */
9616     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9617   },
9618   {
9619     /* VEX_W_C4_P_2 */
9620     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9621   },
9622   {
9623     /* VEX_W_C5_P_2 */
9624     { "vpextrw",        { Gdq, XS, Ib } },
9625   },
9626   {
9627     /* VEX_W_D0_P_2 */
9628     { "vaddsubpd",      { XM, Vex, EXx } },
9629   },
9630   {
9631     /* VEX_W_D0_P_3 */
9632     { "vaddsubps",      { XM, Vex, EXx } },
9633   },
9634   {
9635     /* VEX_W_D1_P_2 */
9636     { "vpsrlw",         { XM, Vex128, EXx } },
9637   },
9638   {
9639     /* VEX_W_D2_P_2 */
9640     { "vpsrld",         { XM, Vex128, EXx } },
9641   },
9642   {
9643     /* VEX_W_D3_P_2 */
9644     { "vpsrlq",         { XM, Vex128, EXx } },
9645   },
9646   {
9647     /* VEX_W_D4_P_2 */
9648     { "vpaddq",         { XM, Vex128, EXx } },
9649   },
9650   {
9651     /* VEX_W_D5_P_2 */
9652     { "vpmullw",        { XM, Vex128, EXx } },
9653   },
9654   {
9655     /* VEX_W_D6_P_2 */
9656     { "vmovq",          { EXqScalarS, XMScalar } },
9657   },
9658   {
9659     /* VEX_W_D7_P_2_M_1 */
9660     { "vpmovmskb",      { Gdq, XS } },
9661   },
9662   {
9663     /* VEX_W_D8_P_2 */
9664     { "vpsubusb",       { XM, Vex128, EXx } },
9665   },
9666   {
9667     /* VEX_W_D9_P_2 */
9668     { "vpsubusw",       { XM, Vex128, EXx } },
9669   },
9670   {
9671     /* VEX_W_DA_P_2 */
9672     { "vpminub",        { XM, Vex128, EXx } },
9673   },
9674   {
9675     /* VEX_W_DB_P_2 */
9676     { "vpand",          { XM, Vex128, EXx } },
9677   },
9678   {
9679     /* VEX_W_DC_P_2 */
9680     { "vpaddusb",       { XM, Vex128, EXx } },
9681   },
9682   {
9683     /* VEX_W_DD_P_2 */
9684     { "vpaddusw",       { XM, Vex128, EXx } },
9685   },
9686   {
9687     /* VEX_W_DE_P_2 */
9688     { "vpmaxub",        { XM, Vex128, EXx } },
9689   },
9690   {
9691     /* VEX_W_DF_P_2 */
9692     { "vpandn",         { XM, Vex128, EXx } },
9693   },
9694   {
9695     /* VEX_W_E0_P_2  */
9696     { "vpavgb",         { XM, Vex128, EXx } },
9697   },
9698   {
9699     /* VEX_W_E1_P_2  */
9700     { "vpsraw",         { XM, Vex128, EXx } },
9701   },
9702   {
9703     /* VEX_W_E2_P_2  */
9704     { "vpsrad",         { XM, Vex128, EXx } },
9705   },
9706   {
9707     /* VEX_W_E3_P_2  */
9708     { "vpavgw",         { XM, Vex128, EXx } },
9709   },
9710   {
9711     /* VEX_W_E4_P_2  */
9712     { "vpmulhuw",       { XM, Vex128, EXx } },
9713   },
9714   {
9715     /* VEX_W_E5_P_2  */
9716     { "vpmulhw",        { XM, Vex128, EXx } },
9717   },
9718   {
9719     /* VEX_W_E6_P_1  */
9720     { "vcvtdq2pd",      { XM, EXxmmq } },
9721   },
9722   {
9723     /* VEX_W_E6_P_2  */
9724     { "vcvttpd2dq%XY",  { XMM, EXx } },
9725   },
9726   {
9727     /* VEX_W_E6_P_3  */
9728     { "vcvtpd2dq%XY",   { XMM, EXx } },
9729   },
9730   {
9731     /* VEX_W_E7_P_2_M_0 */
9732     { "vmovntdq",       { Mx, XM } },
9733   },
9734   {
9735     /* VEX_W_E8_P_2  */
9736     { "vpsubsb",        { XM, Vex128, EXx } },
9737   },
9738   {
9739     /* VEX_W_E9_P_2  */
9740     { "vpsubsw",        { XM, Vex128, EXx } },
9741   },
9742   {
9743     /* VEX_W_EA_P_2  */
9744     { "vpminsw",        { XM, Vex128, EXx } },
9745   },
9746   {
9747     /* VEX_W_EB_P_2  */
9748     { "vpor",           { XM, Vex128, EXx } },
9749   },
9750   {
9751     /* VEX_W_EC_P_2  */
9752     { "vpaddsb",        { XM, Vex128, EXx } },
9753   },
9754   {
9755     /* VEX_W_ED_P_2  */
9756     { "vpaddsw",        { XM, Vex128, EXx } },
9757   },
9758   {
9759     /* VEX_W_EE_P_2  */
9760     { "vpmaxsw",        { XM, Vex128, EXx } },
9761   },
9762   {
9763     /* VEX_W_EF_P_2  */
9764     { "vpxor",          { XM, Vex128, EXx } },
9765   },
9766   {
9767     /* VEX_W_F0_P_3_M_0 */
9768     { "vlddqu",         { XM, M } },
9769   },
9770   {
9771     /* VEX_W_F1_P_2 */
9772     { "vpsllw",         { XM, Vex128, EXx } },
9773   },
9774   {
9775     /* VEX_W_F2_P_2 */
9776     { "vpslld",         { XM, Vex128, EXx } },
9777   },
9778   {
9779     /* VEX_W_F3_P_2 */
9780     { "vpsllq",         { XM, Vex128, EXx } },
9781   },
9782   {
9783     /* VEX_W_F4_P_2 */
9784     { "vpmuludq",       { XM, Vex128, EXx } },
9785   },
9786   {
9787     /* VEX_W_F5_P_2 */
9788     { "vpmaddwd",       { XM, Vex128, EXx } },
9789   },
9790   {
9791     /* VEX_W_F6_P_2 */
9792     { "vpsadbw",        { XM, Vex128, EXx } },
9793   },
9794   {
9795     /* VEX_W_F7_P_2 */
9796     { "vmaskmovdqu",    { XM, XS } },
9797   },
9798   {
9799     /* VEX_W_F8_P_2 */
9800     { "vpsubb",         { XM, Vex128, EXx } },
9801   },
9802   {
9803     /* VEX_W_F9_P_2 */
9804     { "vpsubw",         { XM, Vex128, EXx } },
9805   },
9806   {
9807     /* VEX_W_FA_P_2 */
9808     { "vpsubd",         { XM, Vex128, EXx } },
9809   },
9810   {
9811     /* VEX_W_FB_P_2 */
9812     { "vpsubq",         { XM, Vex128, EXx } },
9813   },
9814   {
9815     /* VEX_W_FC_P_2 */
9816     { "vpaddb",         { XM, Vex128, EXx } },
9817   },
9818   {
9819     /* VEX_W_FD_P_2 */
9820     { "vpaddw",         { XM, Vex128, EXx } },
9821   },
9822   {
9823     /* VEX_W_FE_P_2 */
9824     { "vpaddd",         { XM, Vex128, EXx } },
9825   },
9826   {
9827     /* VEX_W_3800_P_2  */
9828     { "vpshufb",        { XM, Vex128, EXx } },
9829   },
9830   {
9831     /* VEX_W_3801_P_2  */
9832     { "vphaddw",        { XM, Vex128, EXx } },
9833   },
9834   {
9835     /* VEX_W_3802_P_2  */
9836     { "vphaddd",        { XM, Vex128, EXx } },
9837   },
9838   {
9839     /* VEX_W_3803_P_2  */
9840     { "vphaddsw",       { XM, Vex128, EXx } },
9841   },
9842   {
9843     /* VEX_W_3804_P_2  */
9844     { "vpmaddubsw",     { XM, Vex128, EXx } },
9845   },
9846   {
9847     /* VEX_W_3805_P_2  */
9848     { "vphsubw",        { XM, Vex128, EXx } },
9849   },
9850   {
9851     /* VEX_W_3806_P_2  */
9852     { "vphsubd",        { XM, Vex128, EXx } },
9853   },
9854   {
9855     /* VEX_W_3807_P_2  */
9856     { "vphsubsw",       { XM, Vex128, EXx } },
9857   },
9858   {
9859     /* VEX_W_3808_P_2  */
9860     { "vpsignb",        { XM, Vex128, EXx } },
9861   },
9862   {
9863     /* VEX_W_3809_P_2  */
9864     { "vpsignw",        { XM, Vex128, EXx } },
9865   },
9866   {
9867     /* VEX_W_380A_P_2  */
9868     { "vpsignd",        { XM, Vex128, EXx } },
9869   },
9870   {
9871     /* VEX_W_380B_P_2  */
9872     { "vpmulhrsw",      { XM, Vex128, EXx } },
9873   },
9874   {
9875     /* VEX_W_380C_P_2  */
9876     { "vpermilps",      { XM, Vex, EXx } },
9877   },
9878   {
9879     /* VEX_W_380D_P_2  */
9880     { "vpermilpd",      { XM, Vex, EXx } },
9881   },
9882   {
9883     /* VEX_W_380E_P_2  */
9884     { "vtestps",        { XM, EXx } },
9885   },
9886   {
9887     /* VEX_W_380F_P_2  */
9888     { "vtestpd",        { XM, EXx } },
9889   },
9890   {
9891     /* VEX_W_3817_P_2 */
9892     { "vptest",         { XM, EXx } },
9893   },
9894   {
9895     /* VEX_W_3818_P_2_M_0 */
9896     { "vbroadcastss",   { XM, Md } },
9897   },
9898   {
9899     /* VEX_W_3819_P_2_M_0 */
9900     { "vbroadcastsd",   { XM, Mq } },
9901   },
9902   {
9903     /* VEX_W_381A_P_2_M_0 */
9904     { "vbroadcastf128", { XM, Mxmm } },
9905   },
9906   {
9907     /* VEX_W_381C_P_2 */
9908     { "vpabsb",         { XM, EXx } },
9909   },
9910   {
9911     /* VEX_W_381D_P_2 */
9912     { "vpabsw",         { XM, EXx } },
9913   },
9914   {
9915     /* VEX_W_381E_P_2 */
9916     { "vpabsd",         { XM, EXx } },
9917   },
9918   {
9919     /* VEX_W_3820_P_2 */
9920     { "vpmovsxbw",      { XM, EXq } },
9921   },
9922   {
9923     /* VEX_W_3821_P_2 */
9924     { "vpmovsxbd",      { XM, EXd } },
9925   },
9926   {
9927     /* VEX_W_3822_P_2 */
9928     { "vpmovsxbq",      { XM, EXw } },
9929   },
9930   {
9931     /* VEX_W_3823_P_2 */
9932     { "vpmovsxwd",      { XM, EXq } },
9933   },
9934   {
9935     /* VEX_W_3824_P_2 */
9936     { "vpmovsxwq",      { XM, EXd } },
9937   },
9938   {
9939     /* VEX_W_3825_P_2 */
9940     { "vpmovsxdq",      { XM, EXq } },
9941   },
9942   {
9943     /* VEX_W_3828_P_2 */
9944     { "vpmuldq",        { XM, Vex128, EXx } },
9945   },
9946   {
9947     /* VEX_W_3829_P_2 */
9948     { "vpcmpeqq",       { XM, Vex128, EXx } },
9949   },
9950   {
9951     /* VEX_W_382A_P_2_M_0 */
9952     { "vmovntdqa",      { XM, Mx } },
9953   },
9954   {
9955     /* VEX_W_382B_P_2 */
9956     { "vpackusdw",      { XM, Vex128, EXx } },
9957   },
9958   {
9959     /* VEX_W_382C_P_2_M_0 */
9960     { "vmaskmovps",     { XM, Vex, Mx } },
9961   },
9962   {
9963     /* VEX_W_382D_P_2_M_0 */
9964     { "vmaskmovpd",     { XM, Vex, Mx } },
9965   },
9966   {
9967     /* VEX_W_382E_P_2_M_0 */
9968     { "vmaskmovps",     { Mx, Vex, XM } },
9969   },
9970   {
9971     /* VEX_W_382F_P_2_M_0 */
9972     { "vmaskmovpd",     { Mx, Vex, XM } },
9973   },
9974   {
9975     /* VEX_W_3830_P_2 */
9976     { "vpmovzxbw",      { XM, EXq } },
9977   },
9978   {
9979     /* VEX_W_3831_P_2 */
9980     { "vpmovzxbd",      { XM, EXd } },
9981   },
9982   {
9983     /* VEX_W_3832_P_2 */
9984     { "vpmovzxbq",      { XM, EXw } },
9985   },
9986   {
9987     /* VEX_W_3833_P_2 */
9988     { "vpmovzxwd",      { XM, EXq } },
9989   },
9990   {
9991     /* VEX_W_3834_P_2 */
9992     { "vpmovzxwq",      { XM, EXd } },
9993   },
9994   {
9995     /* VEX_W_3835_P_2 */
9996     { "vpmovzxdq",      { XM, EXq } },
9997   },
9998   {
9999     /* VEX_W_3837_P_2 */
10000     { "vpcmpgtq",       { XM, Vex128, EXx } },
10001   },
10002   {
10003     /* VEX_W_3838_P_2 */
10004     { "vpminsb",        { XM, Vex128, EXx } },
10005   },
10006   {
10007     /* VEX_W_3839_P_2 */
10008     { "vpminsd",        { XM, Vex128, EXx } },
10009   },
10010   {
10011     /* VEX_W_383A_P_2 */
10012     { "vpminuw",        { XM, Vex128, EXx } },
10013   },
10014   {
10015     /* VEX_W_383B_P_2 */
10016     { "vpminud",        { XM, Vex128, EXx } },
10017   },
10018   {
10019     /* VEX_W_383C_P_2 */
10020     { "vpmaxsb",        { XM, Vex128, EXx } },
10021   },
10022   {
10023     /* VEX_W_383D_P_2 */
10024     { "vpmaxsd",        { XM, Vex128, EXx } },
10025   },
10026   {
10027     /* VEX_W_383E_P_2 */
10028     { "vpmaxuw",        { XM, Vex128, EXx } },
10029   },
10030   {
10031     /* VEX_W_383F_P_2 */
10032     { "vpmaxud",        { XM, Vex128, EXx } },
10033   },
10034   {
10035     /* VEX_W_3840_P_2 */
10036     { "vpmulld",        { XM, Vex128, EXx } },
10037   },
10038   {
10039     /* VEX_W_3841_P_2 */
10040     { "vphminposuw",    { XM, EXx } },
10041   },
10042   {
10043     /* VEX_W_38DB_P_2 */
10044     { "vaesimc",        { XM, EXx } },
10045   },
10046   {
10047     /* VEX_W_38DC_P_2 */
10048     { "vaesenc",        { XM, Vex128, EXx } },
10049   },
10050   {
10051     /* VEX_W_38DD_P_2 */
10052     { "vaesenclast",    { XM, Vex128, EXx } },
10053   },
10054   {
10055     /* VEX_W_38DE_P_2 */
10056     { "vaesdec",        { XM, Vex128, EXx } },
10057   },
10058   {
10059     /* VEX_W_38DF_P_2 */
10060     { "vaesdeclast",    { XM, Vex128, EXx } },
10061   },
10062   {
10063     /* VEX_W_3A04_P_2 */
10064     { "vpermilps",      { XM, EXx, Ib } },
10065   },
10066   {
10067     /* VEX_W_3A05_P_2 */
10068     { "vpermilpd",      { XM, EXx, Ib } },
10069   },
10070   {
10071     /* VEX_W_3A06_P_2 */
10072     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10073   },
10074   {
10075     /* VEX_W_3A08_P_2 */
10076     { "vroundps",       { XM, EXx, Ib } },
10077   },
10078   {
10079     /* VEX_W_3A09_P_2 */
10080     { "vroundpd",       { XM, EXx, Ib } },
10081   },
10082   {
10083     /* VEX_W_3A0A_P_2 */
10084     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10085   },
10086   {
10087     /* VEX_W_3A0B_P_2 */
10088     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10089   },
10090   {
10091     /* VEX_W_3A0C_P_2 */
10092     { "vblendps",       { XM, Vex, EXx, Ib } },
10093   },
10094   {
10095     /* VEX_W_3A0D_P_2 */
10096     { "vblendpd",       { XM, Vex, EXx, Ib } },
10097   },
10098   {
10099     /* VEX_W_3A0E_P_2 */
10100     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10101   },
10102   {
10103     /* VEX_W_3A0F_P_2 */
10104     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10105   },
10106   {
10107     /* VEX_W_3A14_P_2 */
10108     { "vpextrb",        { Edqb, XM, Ib } },
10109   },
10110   {
10111     /* VEX_W_3A15_P_2 */
10112     { "vpextrw",        { Edqw, XM, Ib } },
10113   },
10114   {
10115     /* VEX_W_3A18_P_2 */
10116     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10117   },
10118   {
10119     /* VEX_W_3A19_P_2 */
10120     { "vextractf128",   { EXxmm, XM, Ib } },
10121   },
10122   {
10123     /* VEX_W_3A20_P_2 */
10124     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10125   },
10126   {
10127     /* VEX_W_3A21_P_2 */
10128     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10129   },
10130   {
10131     /* VEX_W_3A40_P_2 */
10132     { "vdpps",          { XM, Vex, EXx, Ib } },
10133   },
10134   {
10135     /* VEX_W_3A41_P_2 */
10136     { "vdppd",          { XM, Vex128, EXx, Ib } },
10137   },
10138   {
10139     /* VEX_W_3A42_P_2 */
10140     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10141   },
10142   {
10143     /* VEX_W_3A44_P_2 */
10144     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10145   },
10146   {
10147     /* VEX_W_3A48_P_2 */
10148     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10149     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10150   },
10151   {
10152     /* VEX_W_3A49_P_2 */
10153     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10154     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10155   },
10156   {
10157     /* VEX_W_3A4A_P_2 */
10158     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10159   },
10160   {
10161     /* VEX_W_3A4B_P_2 */
10162     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10163   },
10164   {
10165     /* VEX_W_3A4C_P_2 */
10166     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10167   },
10168   {
10169     /* VEX_W_3A60_P_2 */
10170     { "vpcmpestrm",     { XM, EXx, Ib } },
10171   },
10172   {
10173     /* VEX_W_3A61_P_2 */
10174     { "vpcmpestri",     { XM, EXx, Ib } },
10175   },
10176   {
10177     /* VEX_W_3A62_P_2 */
10178     { "vpcmpistrm",     { XM, EXx, Ib } },
10179   },
10180   {
10181     /* VEX_W_3A63_P_2 */
10182     { "vpcmpistri",     { XM, EXx, Ib } },
10183   },
10184   {
10185     /* VEX_W_3ADF_P_2 */
10186     { "vaeskeygenassist", { XM, EXx, Ib } },
10187   },
10188 };
10189
10190 static const struct dis386 mod_table[][2] = {
10191   {
10192     /* MOD_8D */
10193     { "leaS",           { Gv, M } },
10194   },
10195   {
10196     /* MOD_0F01_REG_0 */
10197     { X86_64_TABLE (X86_64_0F01_REG_0) },
10198     { RM_TABLE (RM_0F01_REG_0) },
10199   },
10200   {
10201     /* MOD_0F01_REG_1 */
10202     { X86_64_TABLE (X86_64_0F01_REG_1) },
10203     { RM_TABLE (RM_0F01_REG_1) },
10204   },
10205   {
10206     /* MOD_0F01_REG_2 */
10207     { X86_64_TABLE (X86_64_0F01_REG_2) },
10208     { RM_TABLE (RM_0F01_REG_2) },
10209   },
10210   {
10211     /* MOD_0F01_REG_3 */
10212     { X86_64_TABLE (X86_64_0F01_REG_3) },
10213     { RM_TABLE (RM_0F01_REG_3) },
10214   },
10215   {
10216     /* MOD_0F01_REG_7 */
10217     { "invlpg",         { Mb } },
10218     { RM_TABLE (RM_0F01_REG_7) },
10219   },
10220   {
10221     /* MOD_0F12_PREFIX_0 */
10222     { "movlps",         { XM, EXq } },
10223     { "movhlps",        { XM, EXq } },
10224   },
10225   {
10226     /* MOD_0F13 */
10227     { "movlpX",         { EXq, XM } },
10228   },
10229   {
10230     /* MOD_0F16_PREFIX_0 */
10231     { "movhps",         { XM, EXq } },
10232     { "movlhps",        { XM, EXq } },
10233   },
10234   {
10235     /* MOD_0F17 */
10236     { "movhpX",         { EXq, XM } },
10237   },
10238   {
10239     /* MOD_0F18_REG_0 */
10240     { "prefetchnta",    { Mb } },
10241   },
10242   {
10243     /* MOD_0F18_REG_1 */
10244     { "prefetcht0",     { Mb } },
10245   },
10246   {
10247     /* MOD_0F18_REG_2 */
10248     { "prefetcht1",     { Mb } },
10249   },
10250   {
10251     /* MOD_0F18_REG_3 */
10252     { "prefetcht2",     { Mb } },
10253   },
10254   {
10255     /* MOD_0F20 */
10256     { Bad_Opcode },
10257     { "movZ",           { Rm, Cm } },
10258   },
10259   {
10260     /* MOD_0F21 */
10261     { Bad_Opcode },
10262     { "movZ",           { Rm, Dm } },
10263   },
10264   {
10265     /* MOD_0F22 */
10266     { Bad_Opcode },
10267     { "movZ",           { Cm, Rm } },
10268   },
10269   {
10270     /* MOD_0F23 */
10271     { Bad_Opcode },
10272     { "movZ",           { Dm, Rm } },
10273   },
10274   {
10275     /* MOD_0F24 */
10276     { Bad_Opcode },
10277     { "movL",           { Rd, Td } },
10278   },
10279   {
10280     /* MOD_0F26 */
10281     { Bad_Opcode },
10282     { "movL",           { Td, Rd } },
10283   },
10284   {
10285     /* MOD_0F2B_PREFIX_0 */
10286     {"movntps",         { Mx, XM } },
10287   },
10288   {
10289     /* MOD_0F2B_PREFIX_1 */
10290     {"movntss",         { Md, XM } },
10291   },
10292   {
10293     /* MOD_0F2B_PREFIX_2 */
10294     {"movntpd",         { Mx, XM } },
10295   },
10296   {
10297     /* MOD_0F2B_PREFIX_3 */
10298     {"movntsd",         { Mq, XM } },
10299   },
10300   {
10301     /* MOD_0F51 */
10302     { Bad_Opcode },
10303     { "movmskpX",       { Gdq, XS } },
10304   },
10305   {
10306     /* MOD_0F71_REG_2 */
10307     { Bad_Opcode },
10308     { "psrlw",          { MS, Ib } },
10309   },
10310   {
10311     /* MOD_0F71_REG_4 */
10312     { Bad_Opcode },
10313     { "psraw",          { MS, Ib } },
10314   },
10315   {
10316     /* MOD_0F71_REG_6 */
10317     { Bad_Opcode },
10318     { "psllw",          { MS, Ib } },
10319   },
10320   {
10321     /* MOD_0F72_REG_2 */
10322     { Bad_Opcode },
10323     { "psrld",          { MS, Ib } },
10324   },
10325   {
10326     /* MOD_0F72_REG_4 */
10327     { Bad_Opcode },
10328     { "psrad",          { MS, Ib } },
10329   },
10330   {
10331     /* MOD_0F72_REG_6 */
10332     { Bad_Opcode },
10333     { "pslld",          { MS, Ib } },
10334   },
10335   {
10336     /* MOD_0F73_REG_2 */
10337     { Bad_Opcode },
10338     { "psrlq",          { MS, Ib } },
10339   },
10340   {
10341     /* MOD_0F73_REG_3 */
10342     { Bad_Opcode },
10343     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10344   },
10345   {
10346     /* MOD_0F73_REG_6 */
10347     { Bad_Opcode },
10348     { "psllq",          { MS, Ib } },
10349   },
10350   {
10351     /* MOD_0F73_REG_7 */
10352     { Bad_Opcode },
10353     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10354   },
10355   {
10356     /* MOD_0FAE_REG_0 */
10357     { "fxsave",         { FXSAVE } },
10358   },
10359   {
10360     /* MOD_0FAE_REG_1 */
10361     { "fxrstor",        { FXSAVE } },
10362   },
10363   {
10364     /* MOD_0FAE_REG_2 */
10365     { "ldmxcsr",        { Md } },
10366   },
10367   {
10368     /* MOD_0FAE_REG_3 */
10369     { "stmxcsr",        { Md } },
10370   },
10371   {
10372     /* MOD_0FAE_REG_4 */
10373     { "xsave",          { FXSAVE } },
10374   },
10375   {
10376     /* MOD_0FAE_REG_5 */
10377     { "xrstor",         { FXSAVE } },
10378     { RM_TABLE (RM_0FAE_REG_5) },
10379   },
10380   {
10381     /* MOD_0FAE_REG_6 */
10382     { Bad_Opcode },
10383     { RM_TABLE (RM_0FAE_REG_6) },
10384   },
10385   {
10386     /* MOD_0FAE_REG_7 */
10387     { "clflush",        { Mb } },
10388     { RM_TABLE (RM_0FAE_REG_7) },
10389   },
10390   {
10391     /* MOD_0FB2 */
10392     { "lssS",           { Gv, Mp } },
10393   },
10394   {
10395     /* MOD_0FB4 */
10396     { "lfsS",           { Gv, Mp } },
10397   },
10398   {
10399     /* MOD_0FB5 */
10400     { "lgsS",           { Gv, Mp } },
10401   },
10402   {
10403     /* MOD_0FC7_REG_6 */
10404     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10405   },
10406   {
10407     /* MOD_0FC7_REG_7 */
10408     { "vmptrst",        { Mq } },
10409   },
10410   {
10411     /* MOD_0FD7 */
10412     { Bad_Opcode },
10413     { "pmovmskb",       { Gdq, MS } },
10414   },
10415   {
10416     /* MOD_0FE7_PREFIX_2 */
10417     { "movntdq",        { Mx, XM } },
10418   },
10419   {
10420     /* MOD_0FF0_PREFIX_3 */
10421     { "lddqu",          { XM, M } },
10422   },
10423   {
10424     /* MOD_0F382A_PREFIX_2 */
10425     { "movntdqa",       { XM, Mx } },
10426   },
10427   {
10428     /* MOD_62_32BIT */
10429     { "bound{S|}",      { Gv, Ma } },
10430   },
10431   {
10432     /* MOD_C4_32BIT */
10433     { "lesS",           { Gv, Mp } },
10434     { VEX_C4_TABLE (VEX_0F) },
10435   },
10436   {
10437     /* MOD_C5_32BIT */
10438     { "ldsS",           { Gv, Mp } },
10439     { VEX_C5_TABLE (VEX_0F) },
10440   },
10441   {
10442     /* MOD_VEX_12_PREFIX_0 */
10443     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10444     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10445   },
10446   {
10447     /* MOD_VEX_13 */
10448     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10449   },
10450   {
10451     /* MOD_VEX_16_PREFIX_0 */
10452     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10453     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10454   },
10455   {
10456     /* MOD_VEX_17 */
10457     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10458   },
10459   {
10460     /* MOD_VEX_2B */
10461     { VEX_W_TABLE (VEX_W_2B_M_0) },
10462   },
10463   {
10464     /* MOD_VEX_50 */
10465     { Bad_Opcode },
10466     { VEX_W_TABLE (VEX_W_50_M_0) },
10467   },
10468   {
10469     /* MOD_VEX_71_REG_2 */
10470     { Bad_Opcode },
10471     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10472   },
10473   {
10474     /* MOD_VEX_71_REG_4 */
10475     { Bad_Opcode },
10476     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10477   },
10478   {
10479     /* MOD_VEX_71_REG_6 */
10480     { Bad_Opcode },
10481     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10482   },
10483   {
10484     /* MOD_VEX_72_REG_2 */
10485     { Bad_Opcode },
10486     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10487   },
10488   {
10489     /* MOD_VEX_72_REG_4 */
10490     { Bad_Opcode },
10491     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10492   },
10493   {
10494     /* MOD_VEX_72_REG_6 */
10495     { Bad_Opcode },
10496     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10497   },
10498   {
10499     /* MOD_VEX_73_REG_2 */
10500     { Bad_Opcode },
10501     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10502   },
10503   {
10504     /* MOD_VEX_73_REG_3 */
10505     { Bad_Opcode },
10506     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10507   },
10508   {
10509     /* MOD_VEX_73_REG_6 */
10510     { Bad_Opcode },
10511     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10512   },
10513   {
10514     /* MOD_VEX_73_REG_7 */
10515     { Bad_Opcode },
10516     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10517   },
10518   {
10519     /* MOD_VEX_AE_REG_2 */
10520     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10521   },
10522   {
10523     /* MOD_VEX_AE_REG_3 */
10524     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10525   },
10526   {
10527     /* MOD_VEX_D7_PREFIX_2 */
10528     { Bad_Opcode },
10529     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10530   },
10531   {
10532     /* MOD_VEX_E7_PREFIX_2 */
10533     { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10534   },
10535   {
10536     /* MOD_VEX_F0_PREFIX_3 */
10537     { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10538   },
10539   {
10540     /* MOD_VEX_3818_PREFIX_2 */
10541     { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10542   },
10543   {
10544     /* MOD_VEX_3819_PREFIX_2 */
10545     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10546   },
10547   {
10548     /* MOD_VEX_381A_PREFIX_2 */
10549     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10550   },
10551   {
10552     /* MOD_VEX_382A_PREFIX_2 */
10553     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10554   },
10555   {
10556     /* MOD_VEX_382C_PREFIX_2 */
10557     { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10558   },
10559   {
10560     /* MOD_VEX_382D_PREFIX_2 */
10561     { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10562   },
10563   {
10564     /* MOD_VEX_382E_PREFIX_2 */
10565     { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10566   },
10567   {
10568     /* MOD_VEX_382F_PREFIX_2 */
10569     { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10570   },
10571 };
10572
10573 static const struct dis386 rm_table[][8] = {
10574   {
10575     /* RM_0F01_REG_0 */
10576     { Bad_Opcode },
10577     { "vmcall",         { Skip_MODRM } },
10578     { "vmlaunch",       { Skip_MODRM } },
10579     { "vmresume",       { Skip_MODRM } },
10580     { "vmxoff",         { Skip_MODRM } },
10581   },
10582   {
10583     /* RM_0F01_REG_1 */
10584     { "monitor",        { { OP_Monitor, 0 } } },
10585     { "mwait",          { { OP_Mwait, 0 } } },
10586   },
10587   {
10588     /* RM_0F01_REG_2 */
10589     { "xgetbv",         { Skip_MODRM } },
10590     { "xsetbv",         { Skip_MODRM } },
10591   },
10592   {
10593     /* RM_0F01_REG_3 */
10594     { "vmrun",          { Skip_MODRM } },
10595     { "vmmcall",        { Skip_MODRM } },
10596     { "vmload",         { Skip_MODRM } },
10597     { "vmsave",         { Skip_MODRM } },
10598     { "stgi",           { Skip_MODRM } },
10599     { "clgi",           { Skip_MODRM } },
10600     { "skinit",         { Skip_MODRM } },
10601     { "invlpga",        { Skip_MODRM } },
10602   },
10603   {
10604     /* RM_0F01_REG_7 */
10605     { "swapgs",         { Skip_MODRM } },
10606     { "rdtscp",         { Skip_MODRM } },
10607   },
10608   {
10609     /* RM_0FAE_REG_5 */
10610     { "lfence",         { Skip_MODRM } },
10611   },
10612   {
10613     /* RM_0FAE_REG_6 */
10614     { "mfence",         { Skip_MODRM } },
10615   },
10616   {
10617     /* RM_0FAE_REG_7 */
10618     { "sfence",         { Skip_MODRM } },
10619   },
10620 };
10621
10622 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10623
10624 /* We use the high bit to indicate different name for the same
10625    prefix.  */
10626 #define ADDR16_PREFIX   (0x67 | 0x100)
10627 #define ADDR32_PREFIX   (0x67 | 0x200)
10628 #define DATA16_PREFIX   (0x66 | 0x100)
10629 #define DATA32_PREFIX   (0x66 | 0x200)
10630 #define REP_PREFIX      (0xf3 | 0x100)
10631
10632 static int
10633 ckprefix (void)
10634 {
10635   int newrex, i, length;
10636   rex = 0;
10637   rex_ignored = 0;
10638   prefixes = 0;
10639   used_prefixes = 0;
10640   rex_used = 0;
10641   last_lock_prefix = -1;
10642   last_repz_prefix = -1;
10643   last_repnz_prefix = -1;
10644   last_data_prefix = -1;
10645   last_addr_prefix = -1;
10646   last_rex_prefix = -1;
10647   last_seg_prefix = -1;
10648   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10649     all_prefixes[i] = 0;
10650   i = 0;
10651   length = 0;
10652   /* The maximum instruction length is 15bytes.  */
10653   while (length < MAX_CODE_LENGTH - 1)
10654     {
10655       FETCH_DATA (the_info, codep + 1);
10656       newrex = 0;
10657       switch (*codep)
10658         {
10659         /* REX prefixes family.  */
10660         case 0x40:
10661         case 0x41:
10662         case 0x42:
10663         case 0x43:
10664         case 0x44:
10665         case 0x45:
10666         case 0x46:
10667         case 0x47:
10668         case 0x48:
10669         case 0x49:
10670         case 0x4a:
10671         case 0x4b:
10672         case 0x4c:
10673         case 0x4d:
10674         case 0x4e:
10675         case 0x4f:
10676           if (address_mode == mode_64bit)
10677             newrex = *codep;
10678           else
10679             return 1;
10680           last_rex_prefix = i;
10681           break;
10682         case 0xf3:
10683           prefixes |= PREFIX_REPZ;
10684           last_repz_prefix = i;
10685           break;
10686         case 0xf2:
10687           prefixes |= PREFIX_REPNZ;
10688           last_repnz_prefix = i;
10689           break;
10690         case 0xf0:
10691           prefixes |= PREFIX_LOCK;
10692           last_lock_prefix = i;
10693           break;
10694         case 0x2e:
10695           prefixes |= PREFIX_CS;
10696           last_seg_prefix = i;
10697           break;
10698         case 0x36:
10699           prefixes |= PREFIX_SS;
10700           last_seg_prefix = i;
10701           break;
10702         case 0x3e:
10703           prefixes |= PREFIX_DS;
10704           last_seg_prefix = i;
10705           break;
10706         case 0x26:
10707           prefixes |= PREFIX_ES;
10708           last_seg_prefix = i;
10709           break;
10710         case 0x64:
10711           prefixes |= PREFIX_FS;
10712           last_seg_prefix = i;
10713           break;
10714         case 0x65:
10715           prefixes |= PREFIX_GS;
10716           last_seg_prefix = i;
10717           break;
10718         case 0x66:
10719           prefixes |= PREFIX_DATA;
10720           last_data_prefix = i;
10721           break;
10722         case 0x67:
10723           prefixes |= PREFIX_ADDR;
10724           last_addr_prefix = i;
10725           break;
10726         case FWAIT_OPCODE:
10727           /* fwait is really an instruction.  If there are prefixes
10728              before the fwait, they belong to the fwait, *not* to the
10729              following instruction.  */
10730           if (prefixes || rex)
10731             {
10732               prefixes |= PREFIX_FWAIT;
10733               codep++;
10734               return 1;
10735             }
10736           prefixes = PREFIX_FWAIT;
10737           break;
10738         default:
10739           return 1;
10740         }
10741       /* Rex is ignored when followed by another prefix.  */
10742       if (rex)
10743         {
10744           rex_used = rex;
10745           return 1;
10746         }
10747       if (*codep != FWAIT_OPCODE)
10748         all_prefixes[i++] = *codep;
10749       rex = newrex;
10750       codep++;
10751       length++;
10752     }
10753   return 0;
10754 }
10755
10756 static int
10757 seg_prefix (int pref)
10758 {
10759   switch (pref)
10760     {
10761     case 0x2e:
10762       return PREFIX_CS;
10763     case 0x36:
10764       return PREFIX_SS;
10765     case 0x3e:
10766       return PREFIX_DS;
10767     case 0x26:
10768       return PREFIX_ES;
10769     case 0x64:
10770       return PREFIX_FS;
10771     case 0x65:
10772       return PREFIX_GS;
10773     default:
10774       return 0;
10775     }
10776 }
10777
10778 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10779    prefix byte.  */
10780
10781 static const char *
10782 prefix_name (int pref, int sizeflag)
10783 {
10784   static const char *rexes [16] =
10785     {
10786       "rex",            /* 0x40 */
10787       "rex.B",          /* 0x41 */
10788       "rex.X",          /* 0x42 */
10789       "rex.XB",         /* 0x43 */
10790       "rex.R",          /* 0x44 */
10791       "rex.RB",         /* 0x45 */
10792       "rex.RX",         /* 0x46 */
10793       "rex.RXB",        /* 0x47 */
10794       "rex.W",          /* 0x48 */
10795       "rex.WB",         /* 0x49 */
10796       "rex.WX",         /* 0x4a */
10797       "rex.WXB",        /* 0x4b */
10798       "rex.WR",         /* 0x4c */
10799       "rex.WRB",        /* 0x4d */
10800       "rex.WRX",        /* 0x4e */
10801       "rex.WRXB",       /* 0x4f */
10802     };
10803
10804   switch (pref)
10805     {
10806     /* REX prefixes family.  */
10807     case 0x40:
10808     case 0x41:
10809     case 0x42:
10810     case 0x43:
10811     case 0x44:
10812     case 0x45:
10813     case 0x46:
10814     case 0x47:
10815     case 0x48:
10816     case 0x49:
10817     case 0x4a:
10818     case 0x4b:
10819     case 0x4c:
10820     case 0x4d:
10821     case 0x4e:
10822     case 0x4f:
10823       return rexes [pref - 0x40];
10824     case 0xf3:
10825       return "repz";
10826     case 0xf2:
10827       return "repnz";
10828     case 0xf0:
10829       return "lock";
10830     case 0x2e:
10831       return "cs";
10832     case 0x36:
10833       return "ss";
10834     case 0x3e:
10835       return "ds";
10836     case 0x26:
10837       return "es";
10838     case 0x64:
10839       return "fs";
10840     case 0x65:
10841       return "gs";
10842     case 0x66:
10843       return (sizeflag & DFLAG) ? "data16" : "data32";
10844     case 0x67:
10845       if (address_mode == mode_64bit)
10846         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10847       else
10848         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10849     case FWAIT_OPCODE:
10850       return "fwait";
10851     case ADDR16_PREFIX:
10852       return "addr16";
10853     case ADDR32_PREFIX:
10854       return "addr32";
10855     case DATA16_PREFIX:
10856       return "data16";
10857     case DATA32_PREFIX:
10858       return "data32";
10859     case REP_PREFIX:
10860       return "rep";
10861     default:
10862       return NULL;
10863     }
10864 }
10865
10866 static char op_out[MAX_OPERANDS][100];
10867 static int op_ad, op_index[MAX_OPERANDS];
10868 static int two_source_ops;
10869 static bfd_vma op_address[MAX_OPERANDS];
10870 static bfd_vma op_riprel[MAX_OPERANDS];
10871 static bfd_vma start_pc;
10872
10873 /*
10874  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10875  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10876  *   section of the "Virtual 8086 Mode" chapter.)
10877  * 'pc' should be the address of this instruction, it will
10878  *   be used to print the target address if this is a relative jump or call
10879  * The function returns the length of this instruction in bytes.
10880  */
10881
10882 static char intel_syntax;
10883 static char intel_mnemonic = !SYSV386_COMPAT;
10884 static char open_char;
10885 static char close_char;
10886 static char separator_char;
10887 static char scale_char;
10888
10889 /* Here for backwards compatibility.  When gdb stops using
10890    print_insn_i386_att and print_insn_i386_intel these functions can
10891    disappear, and print_insn_i386 be merged into print_insn.  */
10892 int
10893 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10894 {
10895   intel_syntax = 0;
10896
10897   return print_insn (pc, info);
10898 }
10899
10900 int
10901 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10902 {
10903   intel_syntax = 1;
10904
10905   return print_insn (pc, info);
10906 }
10907
10908 int
10909 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10910 {
10911   intel_syntax = -1;
10912
10913   return print_insn (pc, info);
10914 }
10915
10916 void
10917 print_i386_disassembler_options (FILE *stream)
10918 {
10919   fprintf (stream, _("\n\
10920 The following i386/x86-64 specific disassembler options are supported for use\n\
10921 with the -M switch (multiple options should be separated by commas):\n"));
10922
10923   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10924   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10925   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10926   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10927   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10928   fprintf (stream, _("  att-mnemonic\n"
10929                      "              Display instruction in AT&T mnemonic\n"));
10930   fprintf (stream, _("  intel-mnemonic\n"
10931                      "              Display instruction in Intel mnemonic\n"));
10932   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10933   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10934   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10935   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10936   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10937   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10938 }
10939
10940 /* Bad opcode.  */
10941 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10942
10943 /* Get a pointer to struct dis386 with a valid name.  */
10944
10945 static const struct dis386 *
10946 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10947 {
10948   int vindex, vex_table_index;
10949
10950   if (dp->name != NULL)
10951     return dp;
10952
10953   switch (dp->op[0].bytemode)
10954     {
10955     case USE_REG_TABLE:
10956       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10957       break;
10958
10959     case USE_MOD_TABLE:
10960       vindex = modrm.mod == 0x3 ? 1 : 0;
10961       dp = &mod_table[dp->op[1].bytemode][vindex];
10962       break;
10963
10964     case USE_RM_TABLE:
10965       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10966       break;
10967
10968     case USE_PREFIX_TABLE:
10969       if (need_vex)
10970         {
10971           /* The prefix in VEX is implicit.  */
10972           switch (vex.prefix)
10973             {
10974             case 0:
10975               vindex = 0;
10976               break;
10977             case REPE_PREFIX_OPCODE:
10978               vindex = 1;
10979               break;
10980             case DATA_PREFIX_OPCODE:
10981               vindex = 2;
10982               break;
10983             case REPNE_PREFIX_OPCODE:
10984               vindex = 3;
10985               break;
10986             default:
10987               abort ();
10988               break;
10989             }
10990         }
10991       else
10992         {
10993           vindex = 0;
10994           used_prefixes |= (prefixes & PREFIX_REPZ);
10995           if (prefixes & PREFIX_REPZ)
10996             {
10997               vindex = 1;
10998               all_prefixes[last_repz_prefix] = 0;
10999             }
11000           else
11001             {
11002               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11003                  PREFIX_DATA.  */
11004               used_prefixes |= (prefixes & PREFIX_REPNZ);
11005               if (prefixes & PREFIX_REPNZ)
11006                 {
11007                   vindex = 3;
11008                   all_prefixes[last_repnz_prefix] = 0;
11009                 }
11010               else
11011                 {
11012                   used_prefixes |= (prefixes & PREFIX_DATA);
11013                   if (prefixes & PREFIX_DATA)
11014                     {
11015                       vindex = 2;
11016                       all_prefixes[last_data_prefix] = 0;
11017                     }
11018                 }
11019             }
11020         }
11021       dp = &prefix_table[dp->op[1].bytemode][vindex];
11022       break;
11023
11024     case USE_X86_64_TABLE:
11025       vindex = address_mode == mode_64bit ? 1 : 0;
11026       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11027       break;
11028
11029     case USE_3BYTE_TABLE:
11030       FETCH_DATA (info, codep + 2);
11031       vindex = *codep++;
11032       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11033       modrm.mod = (*codep >> 6) & 3;
11034       modrm.reg = (*codep >> 3) & 7;
11035       modrm.rm = *codep & 7;
11036       break;
11037
11038     case USE_VEX_LEN_TABLE:
11039       if (!need_vex)
11040         abort ();
11041
11042       switch (vex.length)
11043         {
11044         case 128:
11045           vindex = 0;
11046           break;
11047         case 256:
11048           vindex = 1;
11049           break;
11050         default:
11051           abort ();
11052           break;
11053         }
11054
11055       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11056       break;
11057
11058     case USE_XOP_8F_TABLE:
11059       FETCH_DATA (info, codep + 3);
11060       /* All bits in the REX prefix are ignored.  */
11061       rex_ignored = rex;
11062       rex = ~(*codep >> 5) & 0x7;
11063
11064       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11065       switch ((*codep & 0x1f))
11066         {
11067         default:
11068           dp = &bad_opcode;
11069           return dp;
11070         case 0x8:
11071           vex_table_index = XOP_08;
11072           break;
11073         case 0x9:
11074           vex_table_index = XOP_09;
11075           break;
11076         case 0xa:
11077           vex_table_index = XOP_0A;
11078           break;
11079         }
11080       codep++;
11081       vex.w = *codep & 0x80;
11082       if (vex.w && address_mode == mode_64bit)
11083         rex |= REX_W;
11084
11085       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11086       if (address_mode != mode_64bit
11087           && vex.register_specifier > 0x7)
11088         {
11089           dp = &bad_opcode;
11090           return dp;
11091         }
11092
11093       vex.length = (*codep & 0x4) ? 256 : 128;
11094       switch ((*codep & 0x3))
11095         {
11096         case 0:
11097           vex.prefix = 0;
11098           break;
11099         case 1:
11100           vex.prefix = DATA_PREFIX_OPCODE;
11101           break;
11102         case 2:
11103           vex.prefix = REPE_PREFIX_OPCODE;
11104           break;
11105         case 3:
11106           vex.prefix = REPNE_PREFIX_OPCODE;
11107           break;
11108         }
11109       need_vex = 1;
11110       need_vex_reg = 1;
11111       codep++;
11112       vindex = *codep++;
11113       dp = &xop_table[vex_table_index][vindex];
11114
11115       FETCH_DATA (info, codep + 1);
11116       modrm.mod = (*codep >> 6) & 3;
11117       modrm.reg = (*codep >> 3) & 7;
11118       modrm.rm = *codep & 7;
11119       break;
11120
11121     case USE_VEX_C4_TABLE:
11122       FETCH_DATA (info, codep + 3);
11123       /* All bits in the REX prefix are ignored.  */
11124       rex_ignored = rex;
11125       rex = ~(*codep >> 5) & 0x7;
11126       switch ((*codep & 0x1f))
11127         {
11128         default:
11129           dp = &bad_opcode;
11130           return dp;
11131         case 0x1:
11132           vex_table_index = VEX_0F;
11133           break;
11134         case 0x2:
11135           vex_table_index = VEX_0F38;
11136           break;
11137         case 0x3:
11138           vex_table_index = VEX_0F3A;
11139           break;
11140         }
11141       codep++;
11142       vex.w = *codep & 0x80;
11143       if (vex.w && address_mode == mode_64bit)
11144         rex |= REX_W;
11145
11146       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11147       if (address_mode != mode_64bit
11148           && vex.register_specifier > 0x7)
11149         {
11150           dp = &bad_opcode;
11151           return dp;
11152         }
11153
11154       vex.length = (*codep & 0x4) ? 256 : 128;
11155       switch ((*codep & 0x3))
11156         {
11157         case 0:
11158           vex.prefix = 0;
11159           break;
11160         case 1:
11161           vex.prefix = DATA_PREFIX_OPCODE;
11162           break;
11163         case 2:
11164           vex.prefix = REPE_PREFIX_OPCODE;
11165           break;
11166         case 3:
11167           vex.prefix = REPNE_PREFIX_OPCODE;
11168           break;
11169         }
11170       need_vex = 1;
11171       need_vex_reg = 1;
11172       codep++;
11173       vindex = *codep++;
11174       dp = &vex_table[vex_table_index][vindex];
11175       /* There is no MODRM byte for VEX [82|77].  */
11176       if (vindex != 0x77 && vindex != 0x82)
11177         {
11178           FETCH_DATA (info, codep + 1);
11179           modrm.mod = (*codep >> 6) & 3;
11180           modrm.reg = (*codep >> 3) & 7;
11181           modrm.rm = *codep & 7;
11182         }
11183       break;
11184
11185     case USE_VEX_C5_TABLE:
11186       FETCH_DATA (info, codep + 2);
11187       /* All bits in the REX prefix are ignored.  */
11188       rex_ignored = rex;
11189       rex = (*codep & 0x80) ? 0 : REX_R;
11190
11191       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11192       if (address_mode != mode_64bit
11193           && vex.register_specifier > 0x7)
11194         {
11195           dp = &bad_opcode;
11196           return dp;
11197         }
11198
11199       vex.w = 0;
11200
11201       vex.length = (*codep & 0x4) ? 256 : 128;
11202       switch ((*codep & 0x3))
11203         {
11204         case 0:
11205           vex.prefix = 0;
11206           break;
11207         case 1:
11208           vex.prefix = DATA_PREFIX_OPCODE;
11209           break;
11210         case 2:
11211           vex.prefix = REPE_PREFIX_OPCODE;
11212           break;
11213         case 3:
11214           vex.prefix = REPNE_PREFIX_OPCODE;
11215           break;
11216         }
11217       need_vex = 1;
11218       need_vex_reg = 1;
11219       codep++;
11220       vindex = *codep++;
11221       dp = &vex_table[dp->op[1].bytemode][vindex];
11222       /* There is no MODRM byte for VEX [82|77].  */
11223       if (vindex != 0x77 && vindex != 0x82)
11224         {
11225           FETCH_DATA (info, codep + 1);
11226           modrm.mod = (*codep >> 6) & 3;
11227           modrm.reg = (*codep >> 3) & 7;
11228           modrm.rm = *codep & 7;
11229         }
11230       break;
11231
11232     case USE_VEX_W_TABLE:
11233       if (!need_vex)
11234         abort ();
11235
11236       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11237       break;
11238
11239     case 0:
11240       dp = &bad_opcode;
11241       break;
11242
11243     default:
11244       abort ();
11245     }
11246
11247   if (dp->name != NULL)
11248     return dp;
11249   else
11250     return get_valid_dis386 (dp, info);
11251 }
11252
11253 static void
11254 get_sib (disassemble_info *info)
11255 {
11256   /* If modrm.mod == 3, operand must be register.  */
11257   if (need_modrm
11258       && address_mode != mode_16bit
11259       && modrm.mod != 3
11260       && modrm.rm == 4)
11261     {
11262       FETCH_DATA (info, codep + 2);
11263       sib.index = (codep [1] >> 3) & 7;
11264       sib.scale = (codep [1] >> 6) & 3;
11265       sib.base = codep [1] & 7;
11266     }
11267 }
11268
11269 static int
11270 print_insn (bfd_vma pc, disassemble_info *info)
11271 {
11272   const struct dis386 *dp;
11273   int i;
11274   char *op_txt[MAX_OPERANDS];
11275   int needcomma;
11276   int sizeflag;
11277   const char *p;
11278   struct dis_private priv;
11279   int prefix_length;
11280   int default_prefixes;
11281
11282   if (info->mach == bfd_mach_x86_64_intel_syntax
11283       || info->mach == bfd_mach_x86_64
11284       || info->mach == bfd_mach_l1om
11285       || info->mach == bfd_mach_l1om_intel_syntax)
11286     address_mode = mode_64bit;
11287   else
11288     address_mode = mode_32bit;
11289
11290   if (intel_syntax == (char) -1)
11291     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11292                     || info->mach == bfd_mach_x86_64_intel_syntax
11293                     || info->mach == bfd_mach_l1om_intel_syntax);
11294
11295   if (info->mach == bfd_mach_i386_i386
11296       || info->mach == bfd_mach_x86_64
11297       || info->mach == bfd_mach_l1om
11298       || info->mach == bfd_mach_i386_i386_intel_syntax
11299       || info->mach == bfd_mach_x86_64_intel_syntax
11300       || info->mach == bfd_mach_l1om_intel_syntax)
11301     priv.orig_sizeflag = AFLAG | DFLAG;
11302   else if (info->mach == bfd_mach_i386_i8086)
11303     priv.orig_sizeflag = 0;
11304   else
11305     abort ();
11306
11307   for (p = info->disassembler_options; p != NULL; )
11308     {
11309       if (CONST_STRNEQ (p, "x86-64"))
11310         {
11311           address_mode = mode_64bit;
11312           priv.orig_sizeflag = AFLAG | DFLAG;
11313         }
11314       else if (CONST_STRNEQ (p, "i386"))
11315         {
11316           address_mode = mode_32bit;
11317           priv.orig_sizeflag = AFLAG | DFLAG;
11318         }
11319       else if (CONST_STRNEQ (p, "i8086"))
11320         {
11321           address_mode = mode_16bit;
11322           priv.orig_sizeflag = 0;
11323         }
11324       else if (CONST_STRNEQ (p, "intel"))
11325         {
11326           intel_syntax = 1;
11327           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11328             intel_mnemonic = 1;
11329         }
11330       else if (CONST_STRNEQ (p, "att"))
11331         {
11332           intel_syntax = 0;
11333           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11334             intel_mnemonic = 0;
11335         }
11336       else if (CONST_STRNEQ (p, "addr"))
11337         {
11338           if (address_mode == mode_64bit)
11339             {
11340               if (p[4] == '3' && p[5] == '2')
11341                 priv.orig_sizeflag &= ~AFLAG;
11342               else if (p[4] == '6' && p[5] == '4')
11343                 priv.orig_sizeflag |= AFLAG;
11344             }
11345           else
11346             {
11347               if (p[4] == '1' && p[5] == '6')
11348                 priv.orig_sizeflag &= ~AFLAG;
11349               else if (p[4] == '3' && p[5] == '2')
11350                 priv.orig_sizeflag |= AFLAG;
11351             }
11352         }
11353       else if (CONST_STRNEQ (p, "data"))
11354         {
11355           if (p[4] == '1' && p[5] == '6')
11356             priv.orig_sizeflag &= ~DFLAG;
11357           else if (p[4] == '3' && p[5] == '2')
11358             priv.orig_sizeflag |= DFLAG;
11359         }
11360       else if (CONST_STRNEQ (p, "suffix"))
11361         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11362
11363       p = strchr (p, ',');
11364       if (p != NULL)
11365         p++;
11366     }
11367
11368   if (intel_syntax)
11369     {
11370       names64 = intel_names64;
11371       names32 = intel_names32;
11372       names16 = intel_names16;
11373       names8 = intel_names8;
11374       names8rex = intel_names8rex;
11375       names_seg = intel_names_seg;
11376       names_mm = intel_names_mm;
11377       names_xmm = intel_names_xmm;
11378       names_ymm = intel_names_ymm;
11379       index64 = intel_index64;
11380       index32 = intel_index32;
11381       index16 = intel_index16;
11382       open_char = '[';
11383       close_char = ']';
11384       separator_char = '+';
11385       scale_char = '*';
11386     }
11387   else
11388     {
11389       names64 = att_names64;
11390       names32 = att_names32;
11391       names16 = att_names16;
11392       names8 = att_names8;
11393       names8rex = att_names8rex;
11394       names_seg = att_names_seg;
11395       names_mm = att_names_mm;
11396       names_xmm = att_names_xmm;
11397       names_ymm = att_names_ymm;
11398       index64 = att_index64;
11399       index32 = att_index32;
11400       index16 = att_index16;
11401       open_char = '(';
11402       close_char =  ')';
11403       separator_char = ',';
11404       scale_char = ',';
11405     }
11406
11407   /* The output looks better if we put 7 bytes on a line, since that
11408      puts most long word instructions on a single line.  Use 8 bytes
11409      for Intel L1OM.  */
11410   if (info->mach == bfd_mach_l1om
11411       || info->mach == bfd_mach_l1om_intel_syntax)
11412     info->bytes_per_line = 8;
11413   else
11414     info->bytes_per_line = 7;
11415
11416   info->private_data = &priv;
11417   priv.max_fetched = priv.the_buffer;
11418   priv.insn_start = pc;
11419
11420   obuf[0] = 0;
11421   for (i = 0; i < MAX_OPERANDS; ++i)
11422     {
11423       op_out[i][0] = 0;
11424       op_index[i] = -1;
11425     }
11426
11427   the_info = info;
11428   start_pc = pc;
11429   start_codep = priv.the_buffer;
11430   codep = priv.the_buffer;
11431
11432   if (setjmp (priv.bailout) != 0)
11433     {
11434       const char *name;
11435
11436       /* Getting here means we tried for data but didn't get it.  That
11437          means we have an incomplete instruction of some sort.  Just
11438          print the first byte as a prefix or a .byte pseudo-op.  */
11439       if (codep > priv.the_buffer)
11440         {
11441           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11442           if (name != NULL)
11443             (*info->fprintf_func) (info->stream, "%s", name);
11444           else
11445             {
11446               /* Just print the first byte as a .byte instruction.  */
11447               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11448                                      (unsigned int) priv.the_buffer[0]);
11449             }
11450
11451           return 1;
11452         }
11453
11454       return -1;
11455     }
11456
11457   obufp = obuf;
11458   sizeflag = priv.orig_sizeflag;
11459
11460   if (!ckprefix () || rex_used)
11461     {
11462       /* Too many prefixes or unused REX prefixes.  */
11463       for (i = 0;
11464            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11465            i++)
11466         (*info->fprintf_func) (info->stream, "%s",
11467                                prefix_name (all_prefixes[i], sizeflag));
11468       return 1;
11469     }
11470
11471   insn_codep = codep;
11472
11473   FETCH_DATA (info, codep + 1);
11474   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11475
11476   if (((prefixes & PREFIX_FWAIT)
11477        && ((*codep < 0xd8) || (*codep > 0xdf))))
11478     {
11479       (*info->fprintf_func) (info->stream, "fwait");
11480       return 1;
11481     }
11482
11483   if (*codep == 0x0f)
11484     {
11485       unsigned char threebyte;
11486       FETCH_DATA (info, codep + 2);
11487       threebyte = *++codep;
11488       dp = &dis386_twobyte[threebyte];
11489       need_modrm = twobyte_has_modrm[*codep];
11490       codep++;
11491     }
11492   else
11493     {
11494       dp = &dis386[*codep];
11495       need_modrm = onebyte_has_modrm[*codep];
11496       codep++;
11497     }
11498
11499   if ((prefixes & PREFIX_REPZ))
11500     used_prefixes |= PREFIX_REPZ;
11501   if ((prefixes & PREFIX_REPNZ))
11502     used_prefixes |= PREFIX_REPNZ;
11503   if ((prefixes & PREFIX_LOCK))
11504     used_prefixes |= PREFIX_LOCK;
11505
11506   default_prefixes = 0;
11507   if (prefixes & PREFIX_ADDR)
11508     {
11509       sizeflag ^= AFLAG;
11510       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11511         {
11512           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11513             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11514           else
11515             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11516           default_prefixes |= PREFIX_ADDR;
11517         }
11518     }
11519
11520   if ((prefixes & PREFIX_DATA))
11521     {
11522       sizeflag ^= DFLAG;
11523       if (dp->op[2].bytemode == cond_jump_mode
11524           && dp->op[0].bytemode == v_mode
11525           && !intel_syntax)
11526         {
11527           if (sizeflag & DFLAG)
11528             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11529           else
11530             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11531           default_prefixes |= PREFIX_DATA;
11532         }
11533       else if (rex & REX_W)
11534         {
11535           /* REX_W will override PREFIX_DATA.  */
11536           default_prefixes |= PREFIX_DATA;
11537         }
11538     }
11539
11540   if (need_modrm)
11541     {
11542       FETCH_DATA (info, codep + 1);
11543       modrm.mod = (*codep >> 6) & 3;
11544       modrm.reg = (*codep >> 3) & 7;
11545       modrm.rm = *codep & 7;
11546     }
11547
11548    need_vex = 0;
11549    need_vex_reg = 0;
11550    vex_w_done = 0;
11551
11552   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11553     {
11554       get_sib (info);
11555       dofloat (sizeflag);
11556     }
11557   else
11558     {
11559       dp = get_valid_dis386 (dp, info);
11560       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11561         {
11562           get_sib (info);
11563           for (i = 0; i < MAX_OPERANDS; ++i)
11564             {
11565               obufp = op_out[i];
11566               op_ad = MAX_OPERANDS - 1 - i;
11567               if (dp->op[i].rtn)
11568                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11569             }
11570         }
11571     }
11572
11573   /* See if any prefixes were not used.  If so, print the first one
11574      separately.  If we don't do this, we'll wind up printing an
11575      instruction stream which does not precisely correspond to the
11576      bytes we are disassembling.  */
11577   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11578     {
11579       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11580         if (all_prefixes[i])
11581           {
11582             const char *name;
11583             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11584             if (name == NULL)
11585               name = INTERNAL_DISASSEMBLER_ERROR;
11586             (*info->fprintf_func) (info->stream, "%s", name);
11587             return 1;
11588           }
11589     }
11590
11591   /* Check if the REX prefix is used.  */
11592   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11593     all_prefixes[last_rex_prefix] = 0;
11594
11595   /* Check if the SEG prefix is used.  */
11596   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11597                    | PREFIX_FS | PREFIX_GS)) != 0
11598       && (used_prefixes
11599           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11600     all_prefixes[last_seg_prefix] = 0;
11601
11602   /* Check if the ADDR prefix is used.  */
11603   if ((prefixes & PREFIX_ADDR) != 0
11604       && (used_prefixes & PREFIX_ADDR) != 0)
11605     all_prefixes[last_addr_prefix] = 0;
11606
11607   /* Check if the DATA prefix is used.  */
11608   if ((prefixes & PREFIX_DATA) != 0
11609       && (used_prefixes & PREFIX_DATA) != 0)
11610     all_prefixes[last_data_prefix] = 0;
11611
11612   prefix_length = 0;
11613   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11614     if (all_prefixes[i])
11615       {
11616         const char *name;
11617         name = prefix_name (all_prefixes[i], sizeflag);
11618         if (name == NULL)
11619           abort ();
11620         prefix_length += strlen (name) + 1;
11621         (*info->fprintf_func) (info->stream, "%s ", name);
11622       }
11623
11624   /* Check maximum code length.  */
11625   if ((codep - start_codep) > MAX_CODE_LENGTH)
11626     {
11627       (*info->fprintf_func) (info->stream, "(bad)");
11628       return MAX_CODE_LENGTH;
11629     }
11630
11631   obufp = mnemonicendp;
11632   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11633     oappend (" ");
11634   oappend (" ");
11635   (*info->fprintf_func) (info->stream, "%s", obuf);
11636
11637   /* The enter and bound instructions are printed with operands in the same
11638      order as the intel book; everything else is printed in reverse order.  */
11639   if (intel_syntax || two_source_ops)
11640     {
11641       bfd_vma riprel;
11642
11643       for (i = 0; i < MAX_OPERANDS; ++i)
11644         op_txt[i] = op_out[i];
11645
11646       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11647         {
11648           op_ad = op_index[i];
11649           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11650           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11651           riprel = op_riprel[i];
11652           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11653           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11654         }
11655     }
11656   else
11657     {
11658       for (i = 0; i < MAX_OPERANDS; ++i)
11659         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11660     }
11661
11662   needcomma = 0;
11663   for (i = 0; i < MAX_OPERANDS; ++i)
11664     if (*op_txt[i])
11665       {
11666         if (needcomma)
11667           (*info->fprintf_func) (info->stream, ",");
11668         if (op_index[i] != -1 && !op_riprel[i])
11669           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11670         else
11671           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11672         needcomma = 1;
11673       }
11674
11675   for (i = 0; i < MAX_OPERANDS; i++)
11676     if (op_index[i] != -1 && op_riprel[i])
11677       {
11678         (*info->fprintf_func) (info->stream, "        # ");
11679         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11680                                                 + op_address[op_index[i]]), info);
11681         break;
11682       }
11683   return codep - priv.the_buffer;
11684 }
11685
11686 static const char *float_mem[] = {
11687   /* d8 */
11688   "fadd{s|}",
11689   "fmul{s|}",
11690   "fcom{s|}",
11691   "fcomp{s|}",
11692   "fsub{s|}",
11693   "fsubr{s|}",
11694   "fdiv{s|}",
11695   "fdivr{s|}",
11696   /* d9 */
11697   "fld{s|}",
11698   "(bad)",
11699   "fst{s|}",
11700   "fstp{s|}",
11701   "fldenvIC",
11702   "fldcw",
11703   "fNstenvIC",
11704   "fNstcw",
11705   /* da */
11706   "fiadd{l|}",
11707   "fimul{l|}",
11708   "ficom{l|}",
11709   "ficomp{l|}",
11710   "fisub{l|}",
11711   "fisubr{l|}",
11712   "fidiv{l|}",
11713   "fidivr{l|}",
11714   /* db */
11715   "fild{l|}",
11716   "fisttp{l|}",
11717   "fist{l|}",
11718   "fistp{l|}",
11719   "(bad)",
11720   "fld{t||t|}",
11721   "(bad)",
11722   "fstp{t||t|}",
11723   /* dc */
11724   "fadd{l|}",
11725   "fmul{l|}",
11726   "fcom{l|}",
11727   "fcomp{l|}",
11728   "fsub{l|}",
11729   "fsubr{l|}",
11730   "fdiv{l|}",
11731   "fdivr{l|}",
11732   /* dd */
11733   "fld{l|}",
11734   "fisttp{ll|}",
11735   "fst{l||}",
11736   "fstp{l|}",
11737   "frstorIC",
11738   "(bad)",
11739   "fNsaveIC",
11740   "fNstsw",
11741   /* de */
11742   "fiadd",
11743   "fimul",
11744   "ficom",
11745   "ficomp",
11746   "fisub",
11747   "fisubr",
11748   "fidiv",
11749   "fidivr",
11750   /* df */
11751   "fild",
11752   "fisttp",
11753   "fist",
11754   "fistp",
11755   "fbld",
11756   "fild{ll|}",
11757   "fbstp",
11758   "fistp{ll|}",
11759 };
11760
11761 static const unsigned char float_mem_mode[] = {
11762   /* d8 */
11763   d_mode,
11764   d_mode,
11765   d_mode,
11766   d_mode,
11767   d_mode,
11768   d_mode,
11769   d_mode,
11770   d_mode,
11771   /* d9 */
11772   d_mode,
11773   0,
11774   d_mode,
11775   d_mode,
11776   0,
11777   w_mode,
11778   0,
11779   w_mode,
11780   /* da */
11781   d_mode,
11782   d_mode,
11783   d_mode,
11784   d_mode,
11785   d_mode,
11786   d_mode,
11787   d_mode,
11788   d_mode,
11789   /* db */
11790   d_mode,
11791   d_mode,
11792   d_mode,
11793   d_mode,
11794   0,
11795   t_mode,
11796   0,
11797   t_mode,
11798   /* dc */
11799   q_mode,
11800   q_mode,
11801   q_mode,
11802   q_mode,
11803   q_mode,
11804   q_mode,
11805   q_mode,
11806   q_mode,
11807   /* dd */
11808   q_mode,
11809   q_mode,
11810   q_mode,
11811   q_mode,
11812   0,
11813   0,
11814   0,
11815   w_mode,
11816   /* de */
11817   w_mode,
11818   w_mode,
11819   w_mode,
11820   w_mode,
11821   w_mode,
11822   w_mode,
11823   w_mode,
11824   w_mode,
11825   /* df */
11826   w_mode,
11827   w_mode,
11828   w_mode,
11829   w_mode,
11830   t_mode,
11831   q_mode,
11832   t_mode,
11833   q_mode
11834 };
11835
11836 #define ST { OP_ST, 0 }
11837 #define STi { OP_STi, 0 }
11838
11839 #define FGRPd9_2 NULL, { { NULL, 0 } }
11840 #define FGRPd9_4 NULL, { { NULL, 1 } }
11841 #define FGRPd9_5 NULL, { { NULL, 2 } }
11842 #define FGRPd9_6 NULL, { { NULL, 3 } }
11843 #define FGRPd9_7 NULL, { { NULL, 4 } }
11844 #define FGRPda_5 NULL, { { NULL, 5 } }
11845 #define FGRPdb_4 NULL, { { NULL, 6 } }
11846 #define FGRPde_3 NULL, { { NULL, 7 } }
11847 #define FGRPdf_4 NULL, { { NULL, 8 } }
11848
11849 static const struct dis386 float_reg[][8] = {
11850   /* d8 */
11851   {
11852     { "fadd",   { ST, STi } },
11853     { "fmul",   { ST, STi } },
11854     { "fcom",   { STi } },
11855     { "fcomp",  { STi } },
11856     { "fsub",   { ST, STi } },
11857     { "fsubr",  { ST, STi } },
11858     { "fdiv",   { ST, STi } },
11859     { "fdivr",  { ST, STi } },
11860   },
11861   /* d9 */
11862   {
11863     { "fld",    { STi } },
11864     { "fxch",   { STi } },
11865     { FGRPd9_2 },
11866     { Bad_Opcode },
11867     { FGRPd9_4 },
11868     { FGRPd9_5 },
11869     { FGRPd9_6 },
11870     { FGRPd9_7 },
11871   },
11872   /* da */
11873   {
11874     { "fcmovb", { ST, STi } },
11875     { "fcmove", { ST, STi } },
11876     { "fcmovbe",{ ST, STi } },
11877     { "fcmovu", { ST, STi } },
11878     { Bad_Opcode },
11879     { FGRPda_5 },
11880     { Bad_Opcode },
11881     { Bad_Opcode },
11882   },
11883   /* db */
11884   {
11885     { "fcmovnb",{ ST, STi } },
11886     { "fcmovne",{ ST, STi } },
11887     { "fcmovnbe",{ ST, STi } },
11888     { "fcmovnu",{ ST, STi } },
11889     { FGRPdb_4 },
11890     { "fucomi", { ST, STi } },
11891     { "fcomi",  { ST, STi } },
11892     { Bad_Opcode },
11893   },
11894   /* dc */
11895   {
11896     { "fadd",   { STi, ST } },
11897     { "fmul",   { STi, ST } },
11898     { Bad_Opcode },
11899     { Bad_Opcode },
11900     { "fsub!M", { STi, ST } },
11901     { "fsubM",  { STi, ST } },
11902     { "fdiv!M", { STi, ST } },
11903     { "fdivM",  { STi, ST } },
11904   },
11905   /* dd */
11906   {
11907     { "ffree",  { STi } },
11908     { Bad_Opcode },
11909     { "fst",    { STi } },
11910     { "fstp",   { STi } },
11911     { "fucom",  { STi } },
11912     { "fucomp", { STi } },
11913     { Bad_Opcode },
11914     { Bad_Opcode },
11915   },
11916   /* de */
11917   {
11918     { "faddp",  { STi, ST } },
11919     { "fmulp",  { STi, ST } },
11920     { Bad_Opcode },
11921     { FGRPde_3 },
11922     { "fsub!Mp", { STi, ST } },
11923     { "fsubMp", { STi, ST } },
11924     { "fdiv!Mp", { STi, ST } },
11925     { "fdivMp", { STi, ST } },
11926   },
11927   /* df */
11928   {
11929     { "ffreep", { STi } },
11930     { Bad_Opcode },
11931     { Bad_Opcode },
11932     { Bad_Opcode },
11933     { FGRPdf_4 },
11934     { "fucomip", { ST, STi } },
11935     { "fcomip", { ST, STi } },
11936     { Bad_Opcode },
11937   },
11938 };
11939
11940 static char *fgrps[][8] = {
11941   /* d9_2  0 */
11942   {
11943     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11944   },
11945
11946   /* d9_4  1 */
11947   {
11948     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11949   },
11950
11951   /* d9_5  2 */
11952   {
11953     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11954   },
11955
11956   /* d9_6  3 */
11957   {
11958     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11959   },
11960
11961   /* d9_7  4 */
11962   {
11963     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11964   },
11965
11966   /* da_5  5 */
11967   {
11968     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11969   },
11970
11971   /* db_4  6 */
11972   {
11973     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11974     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11975   },
11976
11977   /* de_3  7 */
11978   {
11979     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11980   },
11981
11982   /* df_4  8 */
11983   {
11984     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11985   },
11986 };
11987
11988 static void
11989 swap_operand (void)
11990 {
11991   mnemonicendp[0] = '.';
11992   mnemonicendp[1] = 's';
11993   mnemonicendp += 2;
11994 }
11995
11996 static void
11997 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11998                int sizeflag ATTRIBUTE_UNUSED)
11999 {
12000   /* Skip mod/rm byte.  */
12001   MODRM_CHECK;
12002   codep++;
12003 }
12004
12005 static void
12006 dofloat (int sizeflag)
12007 {
12008   const struct dis386 *dp;
12009   unsigned char floatop;
12010
12011   floatop = codep[-1];
12012
12013   if (modrm.mod != 3)
12014     {
12015       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12016
12017       putop (float_mem[fp_indx], sizeflag);
12018       obufp = op_out[0];
12019       op_ad = 2;
12020       OP_E (float_mem_mode[fp_indx], sizeflag);
12021       return;
12022     }
12023   /* Skip mod/rm byte.  */
12024   MODRM_CHECK;
12025   codep++;
12026
12027   dp = &float_reg[floatop - 0xd8][modrm.reg];
12028   if (dp->name == NULL)
12029     {
12030       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12031
12032       /* Instruction fnstsw is only one with strange arg.  */
12033       if (floatop == 0xdf && codep[-1] == 0xe0)
12034         strcpy (op_out[0], names16[0]);
12035     }
12036   else
12037     {
12038       putop (dp->name, sizeflag);
12039
12040       obufp = op_out[0];
12041       op_ad = 2;
12042       if (dp->op[0].rtn)
12043         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12044
12045       obufp = op_out[1];
12046       op_ad = 1;
12047       if (dp->op[1].rtn)
12048         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12049     }
12050 }
12051
12052 static void
12053 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12054 {
12055   oappend ("%st" + intel_syntax);
12056 }
12057
12058 static void
12059 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12060 {
12061   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12062   oappend (scratchbuf + intel_syntax);
12063 }
12064
12065 /* Capital letters in template are macros.  */
12066 static int
12067 putop (const char *in_template, int sizeflag)
12068 {
12069   const char *p;
12070   int alt = 0;
12071   int cond = 1;
12072   unsigned int l = 0, len = 1;
12073   char last[4];
12074
12075 #define SAVE_LAST(c)                    \
12076   if (l < len && l < sizeof (last))     \
12077     last[l++] = c;                      \
12078   else                                  \
12079     abort ();
12080
12081   for (p = in_template; *p; p++)
12082     {
12083       switch (*p)
12084         {
12085         default:
12086           *obufp++ = *p;
12087           break;
12088         case '%':
12089           len++;
12090           break;
12091         case '!':
12092           cond = 0;
12093           break;
12094         case '{':
12095           alt = 0;
12096           if (intel_syntax)
12097             {
12098               while (*++p != '|')
12099                 if (*p == '}' || *p == '\0')
12100                   abort ();
12101             }
12102           /* Fall through.  */
12103         case 'I':
12104           alt = 1;
12105           continue;
12106         case '|':
12107           while (*++p != '}')
12108             {
12109               if (*p == '\0')
12110                 abort ();
12111             }
12112           break;
12113         case '}':
12114           break;
12115         case 'A':
12116           if (intel_syntax)
12117             break;
12118           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12119             *obufp++ = 'b';
12120           break;
12121         case 'B':
12122           if (l == 0 && len == 1)
12123             {
12124 case_B:
12125               if (intel_syntax)
12126                 break;
12127               if (sizeflag & SUFFIX_ALWAYS)
12128                 *obufp++ = 'b';
12129             }
12130           else
12131             {
12132               if (l != 1
12133                   || len != 2
12134                   || last[0] != 'L')
12135                 {
12136                   SAVE_LAST (*p);
12137                   break;
12138                 }
12139
12140               if (address_mode == mode_64bit
12141                   && !(prefixes & PREFIX_ADDR))
12142                 {
12143                   *obufp++ = 'a';
12144                   *obufp++ = 'b';
12145                   *obufp++ = 's';
12146                 }
12147
12148               goto case_B;
12149             }
12150           break;
12151         case 'C':
12152           if (intel_syntax && !alt)
12153             break;
12154           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12155             {
12156               if (sizeflag & DFLAG)
12157                 *obufp++ = intel_syntax ? 'd' : 'l';
12158               else
12159                 *obufp++ = intel_syntax ? 'w' : 's';
12160               used_prefixes |= (prefixes & PREFIX_DATA);
12161             }
12162           break;
12163         case 'D':
12164           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12165             break;
12166           USED_REX (REX_W);
12167           if (modrm.mod == 3)
12168             {
12169               if (rex & REX_W)
12170                 *obufp++ = 'q';
12171               else
12172                 {
12173                   if (sizeflag & DFLAG)
12174                     *obufp++ = intel_syntax ? 'd' : 'l';
12175                   else
12176                     *obufp++ = 'w';
12177                   used_prefixes |= (prefixes & PREFIX_DATA);
12178                 }
12179             }
12180           else
12181             *obufp++ = 'w';
12182           break;
12183         case 'E':               /* For jcxz/jecxz */
12184           if (address_mode == mode_64bit)
12185             {
12186               if (sizeflag & AFLAG)
12187                 *obufp++ = 'r';
12188               else
12189                 *obufp++ = 'e';
12190             }
12191           else
12192             if (sizeflag & AFLAG)
12193               *obufp++ = 'e';
12194           used_prefixes |= (prefixes & PREFIX_ADDR);
12195           break;
12196         case 'F':
12197           if (intel_syntax)
12198             break;
12199           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12200             {
12201               if (sizeflag & AFLAG)
12202                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12203               else
12204                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12205               used_prefixes |= (prefixes & PREFIX_ADDR);
12206             }
12207           break;
12208         case 'G':
12209           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12210             break;
12211           if ((rex & REX_W) || (sizeflag & DFLAG))
12212             *obufp++ = 'l';
12213           else
12214             *obufp++ = 'w';
12215           if (!(rex & REX_W))
12216             used_prefixes |= (prefixes & PREFIX_DATA);
12217           break;
12218         case 'H':
12219           if (intel_syntax)
12220             break;
12221           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12222               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12223             {
12224               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12225               *obufp++ = ',';
12226               *obufp++ = 'p';
12227               if (prefixes & PREFIX_DS)
12228                 *obufp++ = 't';
12229               else
12230                 *obufp++ = 'n';
12231             }
12232           break;
12233         case 'J':
12234           if (intel_syntax)
12235             break;
12236           *obufp++ = 'l';
12237           break;
12238         case 'K':
12239           USED_REX (REX_W);
12240           if (rex & REX_W)
12241             *obufp++ = 'q';
12242           else
12243             *obufp++ = 'd';
12244           break;
12245         case 'Z':
12246           if (intel_syntax)
12247             break;
12248           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12249             {
12250               *obufp++ = 'q';
12251               break;
12252             }
12253           /* Fall through.  */
12254           goto case_L;
12255         case 'L':
12256           if (l != 0 || len != 1)
12257             {
12258               SAVE_LAST (*p);
12259               break;
12260             }
12261 case_L:
12262           if (intel_syntax)
12263             break;
12264           if (sizeflag & SUFFIX_ALWAYS)
12265             *obufp++ = 'l';
12266           break;
12267         case 'M':
12268           if (intel_mnemonic != cond)
12269             *obufp++ = 'r';
12270           break;
12271         case 'N':
12272           if ((prefixes & PREFIX_FWAIT) == 0)
12273             *obufp++ = 'n';
12274           else
12275             used_prefixes |= PREFIX_FWAIT;
12276           break;
12277         case 'O':
12278           USED_REX (REX_W);
12279           if (rex & REX_W)
12280             *obufp++ = 'o';
12281           else if (intel_syntax && (sizeflag & DFLAG))
12282             *obufp++ = 'q';
12283           else
12284             *obufp++ = 'd';
12285           if (!(rex & REX_W))
12286             used_prefixes |= (prefixes & PREFIX_DATA);
12287           break;
12288         case 'T':
12289           if (intel_syntax)
12290             break;
12291           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12292             {
12293               *obufp++ = 'q';
12294               break;
12295             }
12296           /* Fall through.  */
12297         case 'P':
12298           if (intel_syntax)
12299             break;
12300           if ((prefixes & PREFIX_DATA)
12301               || (rex & REX_W)
12302               || (sizeflag & SUFFIX_ALWAYS))
12303             {
12304               USED_REX (REX_W);
12305               if (rex & REX_W)
12306                 *obufp++ = 'q';
12307               else
12308                 {
12309                    if (sizeflag & DFLAG)
12310                       *obufp++ = 'l';
12311                    else
12312                      *obufp++ = 'w';
12313                    used_prefixes |= (prefixes & PREFIX_DATA);
12314                 }
12315             }
12316           break;
12317         case 'U':
12318           if (intel_syntax)
12319             break;
12320           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12321             {
12322               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12323                 *obufp++ = 'q';
12324               break;
12325             }
12326           /* Fall through.  */
12327           goto case_Q;
12328         case 'Q':
12329           if (l == 0 && len == 1)
12330             {
12331 case_Q:
12332               if (intel_syntax && !alt)
12333                 break;
12334               USED_REX (REX_W);
12335               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12336                 {
12337                   if (rex & REX_W)
12338                     *obufp++ = 'q';
12339                   else
12340                     {
12341                       if (sizeflag & DFLAG)
12342                         *obufp++ = intel_syntax ? 'd' : 'l';
12343                       else
12344                         *obufp++ = 'w';
12345                       used_prefixes |= (prefixes & PREFIX_DATA);
12346                     }
12347                 }
12348             }
12349           else
12350             {
12351               if (l != 1 || len != 2 || last[0] != 'L')
12352                 {
12353                   SAVE_LAST (*p);
12354                   break;
12355                 }
12356               if (intel_syntax
12357                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12358                 break;
12359               if ((rex & REX_W))
12360                 {
12361                   USED_REX (REX_W);
12362                   *obufp++ = 'q';
12363                 }
12364               else
12365                 *obufp++ = 'l';
12366             }
12367           break;
12368         case 'R':
12369           USED_REX (REX_W);
12370           if (rex & REX_W)
12371             *obufp++ = 'q';
12372           else if (sizeflag & DFLAG)
12373             {
12374               if (intel_syntax)
12375                   *obufp++ = 'd';
12376               else
12377                   *obufp++ = 'l';
12378             }
12379           else
12380             *obufp++ = 'w';
12381           if (intel_syntax && !p[1]
12382               && ((rex & REX_W) || (sizeflag & DFLAG)))
12383             *obufp++ = 'e';
12384           if (!(rex & REX_W))
12385             used_prefixes |= (prefixes & PREFIX_DATA);
12386           break;
12387         case 'V':
12388           if (l == 0 && len == 1)
12389             {
12390               if (intel_syntax)
12391                 break;
12392               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12393                 {
12394                   if (sizeflag & SUFFIX_ALWAYS)
12395                     *obufp++ = 'q';
12396                   break;
12397                 }
12398             }
12399           else
12400             {
12401               if (l != 1
12402                   || len != 2
12403                   || last[0] != 'L')
12404                 {
12405                   SAVE_LAST (*p);
12406                   break;
12407                 }
12408
12409               if (rex & REX_W)
12410                 {
12411                   *obufp++ = 'a';
12412                   *obufp++ = 'b';
12413                   *obufp++ = 's';
12414                 }
12415             }
12416           /* Fall through.  */
12417           goto case_S;
12418         case 'S':
12419           if (l == 0 && len == 1)
12420             {
12421 case_S:
12422               if (intel_syntax)
12423                 break;
12424               if (sizeflag & SUFFIX_ALWAYS)
12425                 {
12426                   if (rex & REX_W)
12427                     *obufp++ = 'q';
12428                   else
12429                     {
12430                       if (sizeflag & DFLAG)
12431                         *obufp++ = 'l';
12432                       else
12433                         *obufp++ = 'w';
12434                       used_prefixes |= (prefixes & PREFIX_DATA);
12435                     }
12436                 }
12437             }
12438           else
12439             {
12440               if (l != 1
12441                   || len != 2
12442                   || last[0] != 'L')
12443                 {
12444                   SAVE_LAST (*p);
12445                   break;
12446                 }
12447
12448               if (address_mode == mode_64bit
12449                   && !(prefixes & PREFIX_ADDR))
12450                 {
12451                   *obufp++ = 'a';
12452                   *obufp++ = 'b';
12453                   *obufp++ = 's';
12454                 }
12455
12456               goto case_S;
12457             }
12458           break;
12459         case 'X':
12460           if (l != 0 || len != 1)
12461             {
12462               SAVE_LAST (*p);
12463               break;
12464             }
12465           if (need_vex && vex.prefix)
12466             {
12467               if (vex.prefix == DATA_PREFIX_OPCODE)
12468                 *obufp++ = 'd';
12469               else
12470                 *obufp++ = 's';
12471             }
12472           else
12473             {
12474               if (prefixes & PREFIX_DATA)
12475                 *obufp++ = 'd';
12476               else
12477                 *obufp++ = 's';
12478               used_prefixes |= (prefixes & PREFIX_DATA);
12479             }
12480           break;
12481         case 'Y':
12482           if (l == 0 && len == 1)
12483             {
12484               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12485                 break;
12486               if (rex & REX_W)
12487                 {
12488                   USED_REX (REX_W);
12489                   *obufp++ = 'q';
12490                 }
12491               break;
12492             }
12493           else
12494             {
12495               if (l != 1 || len != 2 || last[0] != 'X')
12496                 {
12497                   SAVE_LAST (*p);
12498                   break;
12499                 }
12500               if (!need_vex)
12501                 abort ();
12502               if (intel_syntax
12503                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12504                 break;
12505               switch (vex.length)
12506                 {
12507                 case 128:
12508                   *obufp++ = 'x';
12509                   break;
12510                 case 256:
12511                   *obufp++ = 'y';
12512                   break;
12513                 default:
12514                   abort ();
12515                 }
12516             }
12517           break;
12518         case 'W':
12519           if (l == 0 && len == 1)
12520             {
12521               /* operand size flag for cwtl, cbtw */
12522               USED_REX (REX_W);
12523               if (rex & REX_W)
12524                 {
12525                   if (intel_syntax)
12526                     *obufp++ = 'd';
12527                   else
12528                     *obufp++ = 'l';
12529                 }
12530               else if (sizeflag & DFLAG)
12531                 *obufp++ = 'w';
12532               else
12533                 *obufp++ = 'b';
12534               if (!(rex & REX_W))
12535                 used_prefixes |= (prefixes & PREFIX_DATA);
12536             }
12537           else
12538             {
12539               if (l != 1 || len != 2 || last[0] != 'X')
12540                 {
12541                   SAVE_LAST (*p);
12542                   break;
12543                 }
12544               if (!need_vex)
12545                 abort ();
12546               *obufp++ = vex.w ? 'd': 's';
12547             }
12548           break;
12549         }
12550       alt = 0;
12551     }
12552   *obufp = 0;
12553   mnemonicendp = obufp;
12554   return 0;
12555 }
12556
12557 static void
12558 oappend (const char *s)
12559 {
12560   obufp = stpcpy (obufp, s);
12561 }
12562
12563 static void
12564 append_seg (void)
12565 {
12566   if (prefixes & PREFIX_CS)
12567     {
12568       used_prefixes |= PREFIX_CS;
12569       oappend ("%cs:" + intel_syntax);
12570     }
12571   if (prefixes & PREFIX_DS)
12572     {
12573       used_prefixes |= PREFIX_DS;
12574       oappend ("%ds:" + intel_syntax);
12575     }
12576   if (prefixes & PREFIX_SS)
12577     {
12578       used_prefixes |= PREFIX_SS;
12579       oappend ("%ss:" + intel_syntax);
12580     }
12581   if (prefixes & PREFIX_ES)
12582     {
12583       used_prefixes |= PREFIX_ES;
12584       oappend ("%es:" + intel_syntax);
12585     }
12586   if (prefixes & PREFIX_FS)
12587     {
12588       used_prefixes |= PREFIX_FS;
12589       oappend ("%fs:" + intel_syntax);
12590     }
12591   if (prefixes & PREFIX_GS)
12592     {
12593       used_prefixes |= PREFIX_GS;
12594       oappend ("%gs:" + intel_syntax);
12595     }
12596 }
12597
12598 static void
12599 OP_indirE (int bytemode, int sizeflag)
12600 {
12601   if (!intel_syntax)
12602     oappend ("*");
12603   OP_E (bytemode, sizeflag);
12604 }
12605
12606 static void
12607 print_operand_value (char *buf, int hex, bfd_vma disp)
12608 {
12609   if (address_mode == mode_64bit)
12610     {
12611       if (hex)
12612         {
12613           char tmp[30];
12614           int i;
12615           buf[0] = '0';
12616           buf[1] = 'x';
12617           sprintf_vma (tmp, disp);
12618           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12619           strcpy (buf + 2, tmp + i);
12620         }
12621       else
12622         {
12623           bfd_signed_vma v = disp;
12624           char tmp[30];
12625           int i;
12626           if (v < 0)
12627             {
12628               *(buf++) = '-';
12629               v = -disp;
12630               /* Check for possible overflow on 0x8000000000000000.  */
12631               if (v < 0)
12632                 {
12633                   strcpy (buf, "9223372036854775808");
12634                   return;
12635                 }
12636             }
12637           if (!v)
12638             {
12639               strcpy (buf, "0");
12640               return;
12641             }
12642
12643           i = 0;
12644           tmp[29] = 0;
12645           while (v)
12646             {
12647               tmp[28 - i] = (v % 10) + '0';
12648               v /= 10;
12649               i++;
12650             }
12651           strcpy (buf, tmp + 29 - i);
12652         }
12653     }
12654   else
12655     {
12656       if (hex)
12657         sprintf (buf, "0x%x", (unsigned int) disp);
12658       else
12659         sprintf (buf, "%d", (int) disp);
12660     }
12661 }
12662
12663 /* Put DISP in BUF as signed hex number.  */
12664
12665 static void
12666 print_displacement (char *buf, bfd_vma disp)
12667 {
12668   bfd_signed_vma val = disp;
12669   char tmp[30];
12670   int i, j = 0;
12671
12672   if (val < 0)
12673     {
12674       buf[j++] = '-';
12675       val = -disp;
12676
12677       /* Check for possible overflow.  */
12678       if (val < 0)
12679         {
12680           switch (address_mode)
12681             {
12682             case mode_64bit:
12683               strcpy (buf + j, "0x8000000000000000");
12684               break;
12685             case mode_32bit:
12686               strcpy (buf + j, "0x80000000");
12687               break;
12688             case mode_16bit:
12689               strcpy (buf + j, "0x8000");
12690               break;
12691             }
12692           return;
12693         }
12694     }
12695
12696   buf[j++] = '0';
12697   buf[j++] = 'x';
12698
12699   sprintf_vma (tmp, (bfd_vma) val);
12700   for (i = 0; tmp[i] == '0'; i++)
12701     continue;
12702   if (tmp[i] == '\0')
12703     i--;
12704   strcpy (buf + j, tmp + i);
12705 }
12706
12707 static void
12708 intel_operand_size (int bytemode, int sizeflag)
12709 {
12710   switch (bytemode)
12711     {
12712     case b_mode:
12713     case b_swap_mode:
12714     case dqb_mode:
12715       oappend ("BYTE PTR ");
12716       break;
12717     case w_mode:
12718     case dqw_mode:
12719       oappend ("WORD PTR ");
12720       break;
12721     case stack_v_mode:
12722       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12723         {
12724           oappend ("QWORD PTR ");
12725           break;
12726         }
12727       /* FALLTHRU */
12728     case v_mode:
12729     case v_swap_mode:
12730     case dq_mode:
12731       USED_REX (REX_W);
12732       if (rex & REX_W)
12733         oappend ("QWORD PTR ");
12734       else
12735         {
12736           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12737             oappend ("DWORD PTR ");
12738           else
12739             oappend ("WORD PTR ");
12740           used_prefixes |= (prefixes & PREFIX_DATA);
12741         }
12742       break;
12743     case z_mode:
12744       if ((rex & REX_W) || (sizeflag & DFLAG))
12745         *obufp++ = 'D';
12746       oappend ("WORD PTR ");
12747       if (!(rex & REX_W))
12748         used_prefixes |= (prefixes & PREFIX_DATA);
12749       break;
12750     case a_mode:
12751       if (sizeflag & DFLAG)
12752         oappend ("QWORD PTR ");
12753       else
12754         oappend ("DWORD PTR ");
12755       used_prefixes |= (prefixes & PREFIX_DATA);
12756       break;
12757     case d_mode:
12758     case d_scalar_mode:
12759     case d_scalar_swap_mode:
12760     case d_swap_mode:
12761     case dqd_mode:
12762       oappend ("DWORD PTR ");
12763       break;
12764     case q_mode:
12765     case q_scalar_mode:
12766     case q_scalar_swap_mode:
12767     case q_swap_mode:
12768       oappend ("QWORD PTR ");
12769       break;
12770     case m_mode:
12771       if (address_mode == mode_64bit)
12772         oappend ("QWORD PTR ");
12773       else
12774         oappend ("DWORD PTR ");
12775       break;
12776     case f_mode:
12777       if (sizeflag & DFLAG)
12778         oappend ("FWORD PTR ");
12779       else
12780         oappend ("DWORD PTR ");
12781       used_prefixes |= (prefixes & PREFIX_DATA);
12782       break;
12783     case t_mode:
12784       oappend ("TBYTE PTR ");
12785       break;
12786     case x_mode:
12787     case x_swap_mode:
12788       if (need_vex)
12789         {
12790           switch (vex.length)
12791             {
12792             case 128:
12793               oappend ("XMMWORD PTR ");
12794               break;
12795             case 256:
12796               oappend ("YMMWORD PTR ");
12797               break;
12798             default:
12799               abort ();
12800             }
12801         }
12802       else
12803         oappend ("XMMWORD PTR ");
12804       break;
12805     case xmm_mode:
12806       oappend ("XMMWORD PTR ");
12807       break;
12808     case xmmq_mode:
12809       if (!need_vex)
12810         abort ();
12811
12812       switch (vex.length)
12813         {
12814         case 128:
12815           oappend ("QWORD PTR ");
12816           break;
12817         case 256:
12818           oappend ("XMMWORD PTR ");
12819           break;
12820         default:
12821           abort ();
12822         }
12823       break;
12824     case ymmq_mode:
12825       if (!need_vex)
12826         abort ();
12827
12828       switch (vex.length)
12829         {
12830         case 128:
12831           oappend ("QWORD PTR ");
12832           break;
12833         case 256:
12834           oappend ("YMMWORD PTR ");
12835           break;
12836         default:
12837           abort ();
12838         }
12839       break;
12840     case o_mode:
12841       oappend ("OWORD PTR ");
12842       break;
12843     case vex_w_dq_mode:
12844     case vex_scalar_w_dq_mode:
12845       if (!need_vex)
12846         abort ();
12847
12848       if (vex.w)
12849         oappend ("QWORD PTR ");
12850       else
12851         oappend ("DWORD PTR ");
12852       break;
12853     default:
12854       break;
12855     }
12856 }
12857
12858 static void
12859 OP_E_register (int bytemode, int sizeflag)
12860 {
12861   int reg = modrm.rm;
12862   const char **names;
12863
12864   USED_REX (REX_B);
12865   if ((rex & REX_B))
12866     reg += 8;
12867
12868   if ((sizeflag & SUFFIX_ALWAYS)
12869       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12870     swap_operand ();
12871
12872   switch (bytemode)
12873     {
12874     case b_mode:
12875     case b_swap_mode:
12876       USED_REX (0);
12877       if (rex)
12878         names = names8rex;
12879       else
12880         names = names8;
12881       break;
12882     case w_mode:
12883       names = names16;
12884       break;
12885     case d_mode:
12886       names = names32;
12887       break;
12888     case q_mode:
12889       names = names64;
12890       break;
12891     case m_mode:
12892       names = address_mode == mode_64bit ? names64 : names32;
12893       break;
12894     case stack_v_mode:
12895       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12896         {
12897           names = names64;
12898           break;
12899         }
12900       bytemode = v_mode;
12901       /* FALLTHRU */
12902     case v_mode:
12903     case v_swap_mode:
12904     case dq_mode:
12905     case dqb_mode:
12906     case dqd_mode:
12907     case dqw_mode:
12908       USED_REX (REX_W);
12909       if (rex & REX_W)
12910         names = names64;
12911       else
12912         {
12913           if ((sizeflag & DFLAG)
12914               || (bytemode != v_mode
12915                   && bytemode != v_swap_mode))
12916             names = names32;
12917           else
12918             names = names16;
12919           used_prefixes |= (prefixes & PREFIX_DATA);
12920         }
12921       break;
12922     case 0:
12923       return;
12924     default:
12925       oappend (INTERNAL_DISASSEMBLER_ERROR);
12926       return;
12927     }
12928   oappend (names[reg]);
12929 }
12930
12931 static void
12932 OP_E_memory (int bytemode, int sizeflag)
12933 {
12934   bfd_vma disp = 0;
12935   int add = (rex & REX_B) ? 8 : 0;
12936   int riprel = 0;
12937
12938   USED_REX (REX_B);
12939   if (intel_syntax)
12940     intel_operand_size (bytemode, sizeflag);
12941   append_seg ();
12942
12943   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12944     {
12945       /* 32/64 bit address mode */
12946       int havedisp;
12947       int havesib;
12948       int havebase;
12949       int haveindex;
12950       int needindex;
12951       int base, rbase;
12952       int vindex = 0;
12953       int scale = 0;
12954
12955       havesib = 0;
12956       havebase = 1;
12957       haveindex = 0;
12958       base = modrm.rm;
12959
12960       if (base == 4)
12961         {
12962           havesib = 1;
12963           vindex = sib.index;
12964           scale = sib.scale;
12965           base = sib.base;
12966           USED_REX (REX_X);
12967           if (rex & REX_X)
12968             vindex += 8;
12969           haveindex = vindex != 4;
12970           codep++;
12971         }
12972       rbase = base + add;
12973
12974       switch (modrm.mod)
12975         {
12976         case 0:
12977           if (base == 5)
12978             {
12979               havebase = 0;
12980               if (address_mode == mode_64bit && !havesib)
12981                 riprel = 1;
12982               disp = get32s ();
12983             }
12984           break;
12985         case 1:
12986           FETCH_DATA (the_info, codep + 1);
12987           disp = *codep++;
12988           if ((disp & 0x80) != 0)
12989             disp -= 0x100;
12990           break;
12991         case 2:
12992           disp = get32s ();
12993           break;
12994         }
12995
12996       /* In 32bit mode, we need index register to tell [offset] from
12997          [eiz*1 + offset].  */
12998       needindex = (havesib
12999                    && !havebase
13000                    && !haveindex
13001                    && address_mode == mode_32bit);
13002       havedisp = (havebase
13003                   || needindex
13004                   || (havesib && (haveindex || scale != 0)));
13005
13006       if (!intel_syntax)
13007         if (modrm.mod != 0 || base == 5)
13008           {
13009             if (havedisp || riprel)
13010               print_displacement (scratchbuf, disp);
13011             else
13012               print_operand_value (scratchbuf, 1, disp);
13013             oappend (scratchbuf);
13014             if (riprel)
13015               {
13016                 set_op (disp, 1);
13017                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13018               }
13019           }
13020
13021       if (havebase || haveindex || riprel)
13022         used_prefixes |= PREFIX_ADDR;
13023
13024       if (havedisp || (intel_syntax && riprel))
13025         {
13026           *obufp++ = open_char;
13027           if (intel_syntax && riprel)
13028             {
13029               set_op (disp, 1);
13030               oappend (sizeflag & AFLAG ? "rip" : "eip");
13031             }
13032           *obufp = '\0';
13033           if (havebase)
13034             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13035                      ? names64[rbase] : names32[rbase]);
13036           if (havesib)
13037             {
13038               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13039                  print index to tell base + index from base.  */
13040               if (scale != 0
13041                   || needindex
13042                   || haveindex
13043                   || (havebase && base != ESP_REG_NUM))
13044                 {
13045                   if (!intel_syntax || havebase)
13046                     {
13047                       *obufp++ = separator_char;
13048                       *obufp = '\0';
13049                     }
13050                   if (haveindex)
13051                     oappend (address_mode == mode_64bit
13052                              && (sizeflag & AFLAG)
13053                              ? names64[vindex] : names32[vindex]);
13054                   else
13055                     oappend (address_mode == mode_64bit
13056                              && (sizeflag & AFLAG)
13057                              ? index64 : index32);
13058
13059                   *obufp++ = scale_char;
13060                   *obufp = '\0';
13061                   sprintf (scratchbuf, "%d", 1 << scale);
13062                   oappend (scratchbuf);
13063                 }
13064             }
13065           if (intel_syntax
13066               && (disp || modrm.mod != 0 || base == 5))
13067             {
13068               if (!havedisp || (bfd_signed_vma) disp >= 0)
13069                 {
13070                   *obufp++ = '+';
13071                   *obufp = '\0';
13072                 }
13073               else if (modrm.mod != 1 && disp != -disp)
13074                 {
13075                   *obufp++ = '-';
13076                   *obufp = '\0';
13077                   disp = - (bfd_signed_vma) disp;
13078                 }
13079
13080               if (havedisp)
13081                 print_displacement (scratchbuf, disp);
13082               else
13083                 print_operand_value (scratchbuf, 1, disp);
13084               oappend (scratchbuf);
13085             }
13086
13087           *obufp++ = close_char;
13088           *obufp = '\0';
13089         }
13090       else if (intel_syntax)
13091         {
13092           if (modrm.mod != 0 || base == 5)
13093             {
13094               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13095                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13096                 ;
13097               else
13098                 {
13099                   oappend (names_seg[ds_reg - es_reg]);
13100                   oappend (":");
13101                 }
13102               print_operand_value (scratchbuf, 1, disp);
13103               oappend (scratchbuf);
13104             }
13105         }
13106     }
13107   else
13108     {
13109       /* 16 bit address mode */
13110       used_prefixes |= prefixes & PREFIX_ADDR;
13111       switch (modrm.mod)
13112         {
13113         case 0:
13114           if (modrm.rm == 6)
13115             {
13116               disp = get16 ();
13117               if ((disp & 0x8000) != 0)
13118                 disp -= 0x10000;
13119             }
13120           break;
13121         case 1:
13122           FETCH_DATA (the_info, codep + 1);
13123           disp = *codep++;
13124           if ((disp & 0x80) != 0)
13125             disp -= 0x100;
13126           break;
13127         case 2:
13128           disp = get16 ();
13129           if ((disp & 0x8000) != 0)
13130             disp -= 0x10000;
13131           break;
13132         }
13133
13134       if (!intel_syntax)
13135         if (modrm.mod != 0 || modrm.rm == 6)
13136           {
13137             print_displacement (scratchbuf, disp);
13138             oappend (scratchbuf);
13139           }
13140
13141       if (modrm.mod != 0 || modrm.rm != 6)
13142         {
13143           *obufp++ = open_char;
13144           *obufp = '\0';
13145           oappend (index16[modrm.rm]);
13146           if (intel_syntax
13147               && (disp || modrm.mod != 0 || modrm.rm == 6))
13148             {
13149               if ((bfd_signed_vma) disp >= 0)
13150                 {
13151                   *obufp++ = '+';
13152                   *obufp = '\0';
13153                 }
13154               else if (modrm.mod != 1)
13155                 {
13156                   *obufp++ = '-';
13157                   *obufp = '\0';
13158                   disp = - (bfd_signed_vma) disp;
13159                 }
13160
13161               print_displacement (scratchbuf, disp);
13162               oappend (scratchbuf);
13163             }
13164
13165           *obufp++ = close_char;
13166           *obufp = '\0';
13167         }
13168       else if (intel_syntax)
13169         {
13170           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13171                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13172             ;
13173           else
13174             {
13175               oappend (names_seg[ds_reg - es_reg]);
13176               oappend (":");
13177             }
13178           print_operand_value (scratchbuf, 1, disp & 0xffff);
13179           oappend (scratchbuf);
13180         }
13181     }
13182 }
13183
13184 static void
13185 OP_E (int bytemode, int sizeflag)
13186 {
13187   /* Skip mod/rm byte.  */
13188   MODRM_CHECK;
13189   codep++;
13190
13191   if (modrm.mod == 3)
13192     OP_E_register (bytemode, sizeflag);
13193   else
13194     OP_E_memory (bytemode, sizeflag);
13195 }
13196
13197 static void
13198 OP_G (int bytemode, int sizeflag)
13199 {
13200   int add = 0;
13201   USED_REX (REX_R);
13202   if (rex & REX_R)
13203     add += 8;
13204   switch (bytemode)
13205     {
13206     case b_mode:
13207       USED_REX (0);
13208       if (rex)
13209         oappend (names8rex[modrm.reg + add]);
13210       else
13211         oappend (names8[modrm.reg + add]);
13212       break;
13213     case w_mode:
13214       oappend (names16[modrm.reg + add]);
13215       break;
13216     case d_mode:
13217       oappend (names32[modrm.reg + add]);
13218       break;
13219     case q_mode:
13220       oappend (names64[modrm.reg + add]);
13221       break;
13222     case v_mode:
13223     case dq_mode:
13224     case dqb_mode:
13225     case dqd_mode:
13226     case dqw_mode:
13227       USED_REX (REX_W);
13228       if (rex & REX_W)
13229         oappend (names64[modrm.reg + add]);
13230       else
13231         {
13232           if ((sizeflag & DFLAG) || bytemode != v_mode)
13233             oappend (names32[modrm.reg + add]);
13234           else
13235             oappend (names16[modrm.reg + add]);
13236           used_prefixes |= (prefixes & PREFIX_DATA);
13237         }
13238       break;
13239     case m_mode:
13240       if (address_mode == mode_64bit)
13241         oappend (names64[modrm.reg + add]);
13242       else
13243         oappend (names32[modrm.reg + add]);
13244       break;
13245     default:
13246       oappend (INTERNAL_DISASSEMBLER_ERROR);
13247       break;
13248     }
13249 }
13250
13251 static bfd_vma
13252 get64 (void)
13253 {
13254   bfd_vma x;
13255 #ifdef BFD64
13256   unsigned int a;
13257   unsigned int b;
13258
13259   FETCH_DATA (the_info, codep + 8);
13260   a = *codep++ & 0xff;
13261   a |= (*codep++ & 0xff) << 8;
13262   a |= (*codep++ & 0xff) << 16;
13263   a |= (*codep++ & 0xff) << 24;
13264   b = *codep++ & 0xff;
13265   b |= (*codep++ & 0xff) << 8;
13266   b |= (*codep++ & 0xff) << 16;
13267   b |= (*codep++ & 0xff) << 24;
13268   x = a + ((bfd_vma) b << 32);
13269 #else
13270   abort ();
13271   x = 0;
13272 #endif
13273   return x;
13274 }
13275
13276 static bfd_signed_vma
13277 get32 (void)
13278 {
13279   bfd_signed_vma x = 0;
13280
13281   FETCH_DATA (the_info, codep + 4);
13282   x = *codep++ & (bfd_signed_vma) 0xff;
13283   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13284   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13285   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13286   return x;
13287 }
13288
13289 static bfd_signed_vma
13290 get32s (void)
13291 {
13292   bfd_signed_vma x = 0;
13293
13294   FETCH_DATA (the_info, codep + 4);
13295   x = *codep++ & (bfd_signed_vma) 0xff;
13296   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13297   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13298   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13299
13300   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13301
13302   return x;
13303 }
13304
13305 static int
13306 get16 (void)
13307 {
13308   int x = 0;
13309
13310   FETCH_DATA (the_info, codep + 2);
13311   x = *codep++ & 0xff;
13312   x |= (*codep++ & 0xff) << 8;
13313   return x;
13314 }
13315
13316 static void
13317 set_op (bfd_vma op, int riprel)
13318 {
13319   op_index[op_ad] = op_ad;
13320   if (address_mode == mode_64bit)
13321     {
13322       op_address[op_ad] = op;
13323       op_riprel[op_ad] = riprel;
13324     }
13325   else
13326     {
13327       /* Mask to get a 32-bit address.  */
13328       op_address[op_ad] = op & 0xffffffff;
13329       op_riprel[op_ad] = riprel & 0xffffffff;
13330     }
13331 }
13332
13333 static void
13334 OP_REG (int code, int sizeflag)
13335 {
13336   const char *s;
13337   int add;
13338   USED_REX (REX_B);
13339   if (rex & REX_B)
13340     add = 8;
13341   else
13342     add = 0;
13343
13344   switch (code)
13345     {
13346     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13347     case sp_reg: case bp_reg: case si_reg: case di_reg:
13348       s = names16[code - ax_reg + add];
13349       break;
13350     case es_reg: case ss_reg: case cs_reg:
13351     case ds_reg: case fs_reg: case gs_reg:
13352       s = names_seg[code - es_reg + add];
13353       break;
13354     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13355     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13356       USED_REX (0);
13357       if (rex)
13358         s = names8rex[code - al_reg + add];
13359       else
13360         s = names8[code - al_reg];
13361       break;
13362     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13363     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13364       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13365         {
13366           s = names64[code - rAX_reg + add];
13367           break;
13368         }
13369       code += eAX_reg - rAX_reg;
13370       /* Fall through.  */
13371     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13372     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13373       USED_REX (REX_W);
13374       if (rex & REX_W)
13375         s = names64[code - eAX_reg + add];
13376       else
13377         {
13378           if (sizeflag & DFLAG)
13379             s = names32[code - eAX_reg + add];
13380           else
13381             s = names16[code - eAX_reg + add];
13382           used_prefixes |= (prefixes & PREFIX_DATA);
13383         }
13384       break;
13385     default:
13386       s = INTERNAL_DISASSEMBLER_ERROR;
13387       break;
13388     }
13389   oappend (s);
13390 }
13391
13392 static void
13393 OP_IMREG (int code, int sizeflag)
13394 {
13395   const char *s;
13396
13397   switch (code)
13398     {
13399     case indir_dx_reg:
13400       if (intel_syntax)
13401         s = "dx";
13402       else
13403         s = "(%dx)";
13404       break;
13405     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13406     case sp_reg: case bp_reg: case si_reg: case di_reg:
13407       s = names16[code - ax_reg];
13408       break;
13409     case es_reg: case ss_reg: case cs_reg:
13410     case ds_reg: case fs_reg: case gs_reg:
13411       s = names_seg[code - es_reg];
13412       break;
13413     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13414     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13415       USED_REX (0);
13416       if (rex)
13417         s = names8rex[code - al_reg];
13418       else
13419         s = names8[code - al_reg];
13420       break;
13421     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13422     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13423       USED_REX (REX_W);
13424       if (rex & REX_W)
13425         s = names64[code - eAX_reg];
13426       else
13427         {
13428           if (sizeflag & DFLAG)
13429             s = names32[code - eAX_reg];
13430           else
13431             s = names16[code - eAX_reg];
13432           used_prefixes |= (prefixes & PREFIX_DATA);
13433         }
13434       break;
13435     case z_mode_ax_reg:
13436       if ((rex & REX_W) || (sizeflag & DFLAG))
13437         s = *names32;
13438       else
13439         s = *names16;
13440       if (!(rex & REX_W))
13441         used_prefixes |= (prefixes & PREFIX_DATA);
13442       break;
13443     default:
13444       s = INTERNAL_DISASSEMBLER_ERROR;
13445       break;
13446     }
13447   oappend (s);
13448 }
13449
13450 static void
13451 OP_I (int bytemode, int sizeflag)
13452 {
13453   bfd_signed_vma op;
13454   bfd_signed_vma mask = -1;
13455
13456   switch (bytemode)
13457     {
13458     case b_mode:
13459       FETCH_DATA (the_info, codep + 1);
13460       op = *codep++;
13461       mask = 0xff;
13462       break;
13463     case q_mode:
13464       if (address_mode == mode_64bit)
13465         {
13466           op = get32s ();
13467           break;
13468         }
13469       /* Fall through.  */
13470     case v_mode:
13471       USED_REX (REX_W);
13472       if (rex & REX_W)
13473         op = get32s ();
13474       else
13475         {
13476           if (sizeflag & DFLAG)
13477             {
13478               op = get32 ();
13479               mask = 0xffffffff;
13480             }
13481           else
13482             {
13483               op = get16 ();
13484               mask = 0xfffff;
13485             }
13486           used_prefixes |= (prefixes & PREFIX_DATA);
13487         }
13488       break;
13489     case w_mode:
13490       mask = 0xfffff;
13491       op = get16 ();
13492       break;
13493     case const_1_mode:
13494       if (intel_syntax)
13495         oappend ("1");
13496       return;
13497     default:
13498       oappend (INTERNAL_DISASSEMBLER_ERROR);
13499       return;
13500     }
13501
13502   op &= mask;
13503   scratchbuf[0] = '$';
13504   print_operand_value (scratchbuf + 1, 1, op);
13505   oappend (scratchbuf + intel_syntax);
13506   scratchbuf[0] = '\0';
13507 }
13508
13509 static void
13510 OP_I64 (int bytemode, int sizeflag)
13511 {
13512   bfd_signed_vma op;
13513   bfd_signed_vma mask = -1;
13514
13515   if (address_mode != mode_64bit)
13516     {
13517       OP_I (bytemode, sizeflag);
13518       return;
13519     }
13520
13521   switch (bytemode)
13522     {
13523     case b_mode:
13524       FETCH_DATA (the_info, codep + 1);
13525       op = *codep++;
13526       mask = 0xff;
13527       break;
13528     case v_mode:
13529       USED_REX (REX_W);
13530       if (rex & REX_W)
13531         op = get64 ();
13532       else
13533         {
13534           if (sizeflag & DFLAG)
13535             {
13536               op = get32 ();
13537               mask = 0xffffffff;
13538             }
13539           else
13540             {
13541               op = get16 ();
13542               mask = 0xfffff;
13543             }
13544           used_prefixes |= (prefixes & PREFIX_DATA);
13545         }
13546       break;
13547     case w_mode:
13548       mask = 0xfffff;
13549       op = get16 ();
13550       break;
13551     default:
13552       oappend (INTERNAL_DISASSEMBLER_ERROR);
13553       return;
13554     }
13555
13556   op &= mask;
13557   scratchbuf[0] = '$';
13558   print_operand_value (scratchbuf + 1, 1, op);
13559   oappend (scratchbuf + intel_syntax);
13560   scratchbuf[0] = '\0';
13561 }
13562
13563 static void
13564 OP_sI (int bytemode, int sizeflag)
13565 {
13566   bfd_signed_vma op;
13567
13568   switch (bytemode)
13569     {
13570     case b_mode:
13571       FETCH_DATA (the_info, codep + 1);
13572       op = *codep++;
13573       if ((op & 0x80) != 0)
13574         op -= 0x100;
13575       break;
13576     case v_mode:
13577       USED_REX (REX_W);
13578       if (rex & REX_W)
13579         op = get32s ();
13580       else
13581         {
13582           if (sizeflag & DFLAG)
13583             {
13584               op = get32s ();
13585             }
13586           else
13587             {
13588               op = get16 ();
13589               if ((op & 0x8000) != 0)
13590                 op -= 0x10000;
13591             }
13592           used_prefixes |= (prefixes & PREFIX_DATA);
13593         }
13594       break;
13595     case w_mode:
13596       op = get16 ();
13597       if ((op & 0x8000) != 0)
13598         op -= 0x10000;
13599       break;
13600     default:
13601       oappend (INTERNAL_DISASSEMBLER_ERROR);
13602       return;
13603     }
13604
13605   scratchbuf[0] = '$';
13606   print_operand_value (scratchbuf + 1, 1, op);
13607   oappend (scratchbuf + intel_syntax);
13608 }
13609
13610 static void
13611 OP_J (int bytemode, int sizeflag)
13612 {
13613   bfd_vma disp;
13614   bfd_vma mask = -1;
13615   bfd_vma segment = 0;
13616
13617   switch (bytemode)
13618     {
13619     case b_mode:
13620       FETCH_DATA (the_info, codep + 1);
13621       disp = *codep++;
13622       if ((disp & 0x80) != 0)
13623         disp -= 0x100;
13624       break;
13625     case v_mode:
13626       USED_REX (REX_W);
13627       if ((sizeflag & DFLAG) || (rex & REX_W))
13628         disp = get32s ();
13629       else
13630         {
13631           disp = get16 ();
13632           if ((disp & 0x8000) != 0)
13633             disp -= 0x10000;
13634           /* In 16bit mode, address is wrapped around at 64k within
13635              the same segment.  Otherwise, a data16 prefix on a jump
13636              instruction means that the pc is masked to 16 bits after
13637              the displacement is added!  */
13638           mask = 0xffff;
13639           if ((prefixes & PREFIX_DATA) == 0)
13640             segment = ((start_pc + codep - start_codep)
13641                        & ~((bfd_vma) 0xffff));
13642         }
13643       if (!(rex & REX_W))
13644         used_prefixes |= (prefixes & PREFIX_DATA);
13645       break;
13646     default:
13647       oappend (INTERNAL_DISASSEMBLER_ERROR);
13648       return;
13649     }
13650   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13651   set_op (disp, 0);
13652   print_operand_value (scratchbuf, 1, disp);
13653   oappend (scratchbuf);
13654 }
13655
13656 static void
13657 OP_SEG (int bytemode, int sizeflag)
13658 {
13659   if (bytemode == w_mode)
13660     oappend (names_seg[modrm.reg]);
13661   else
13662     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13663 }
13664
13665 static void
13666 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13667 {
13668   int seg, offset;
13669
13670   if (sizeflag & DFLAG)
13671     {
13672       offset = get32 ();
13673       seg = get16 ();
13674     }
13675   else
13676     {
13677       offset = get16 ();
13678       seg = get16 ();
13679     }
13680   used_prefixes |= (prefixes & PREFIX_DATA);
13681   if (intel_syntax)
13682     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13683   else
13684     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13685   oappend (scratchbuf);
13686 }
13687
13688 static void
13689 OP_OFF (int bytemode, int sizeflag)
13690 {
13691   bfd_vma off;
13692
13693   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13694     intel_operand_size (bytemode, sizeflag);
13695   append_seg ();
13696
13697   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13698     off = get32 ();
13699   else
13700     off = get16 ();
13701
13702   if (intel_syntax)
13703     {
13704       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13705                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13706         {
13707           oappend (names_seg[ds_reg - es_reg]);
13708           oappend (":");
13709         }
13710     }
13711   print_operand_value (scratchbuf, 1, off);
13712   oappend (scratchbuf);
13713 }
13714
13715 static void
13716 OP_OFF64 (int bytemode, int sizeflag)
13717 {
13718   bfd_vma off;
13719
13720   if (address_mode != mode_64bit
13721       || (prefixes & PREFIX_ADDR))
13722     {
13723       OP_OFF (bytemode, sizeflag);
13724       return;
13725     }
13726
13727   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13728     intel_operand_size (bytemode, sizeflag);
13729   append_seg ();
13730
13731   off = get64 ();
13732
13733   if (intel_syntax)
13734     {
13735       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13736                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13737         {
13738           oappend (names_seg[ds_reg - es_reg]);
13739           oappend (":");
13740         }
13741     }
13742   print_operand_value (scratchbuf, 1, off);
13743   oappend (scratchbuf);
13744 }
13745
13746 static void
13747 ptr_reg (int code, int sizeflag)
13748 {
13749   const char *s;
13750
13751   *obufp++ = open_char;
13752   used_prefixes |= (prefixes & PREFIX_ADDR);
13753   if (address_mode == mode_64bit)
13754     {
13755       if (!(sizeflag & AFLAG))
13756         s = names32[code - eAX_reg];
13757       else
13758         s = names64[code - eAX_reg];
13759     }
13760   else if (sizeflag & AFLAG)
13761     s = names32[code - eAX_reg];
13762   else
13763     s = names16[code - eAX_reg];
13764   oappend (s);
13765   *obufp++ = close_char;
13766   *obufp = 0;
13767 }
13768
13769 static void
13770 OP_ESreg (int code, int sizeflag)
13771 {
13772   if (intel_syntax)
13773     {
13774       switch (codep[-1])
13775         {
13776         case 0x6d:      /* insw/insl */
13777           intel_operand_size (z_mode, sizeflag);
13778           break;
13779         case 0xa5:      /* movsw/movsl/movsq */
13780         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13781         case 0xab:      /* stosw/stosl */
13782         case 0xaf:      /* scasw/scasl */
13783           intel_operand_size (v_mode, sizeflag);
13784           break;
13785         default:
13786           intel_operand_size (b_mode, sizeflag);
13787         }
13788     }
13789   oappend ("%es:" + intel_syntax);
13790   ptr_reg (code, sizeflag);
13791 }
13792
13793 static void
13794 OP_DSreg (int code, int sizeflag)
13795 {
13796   if (intel_syntax)
13797     {
13798       switch (codep[-1])
13799         {
13800         case 0x6f:      /* outsw/outsl */
13801           intel_operand_size (z_mode, sizeflag);
13802           break;
13803         case 0xa5:      /* movsw/movsl/movsq */
13804         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13805         case 0xad:      /* lodsw/lodsl/lodsq */
13806           intel_operand_size (v_mode, sizeflag);
13807           break;
13808         default:
13809           intel_operand_size (b_mode, sizeflag);
13810         }
13811     }
13812   if ((prefixes
13813        & (PREFIX_CS
13814           | PREFIX_DS
13815           | PREFIX_SS
13816           | PREFIX_ES
13817           | PREFIX_FS
13818           | PREFIX_GS)) == 0)
13819     prefixes |= PREFIX_DS;
13820   append_seg ();
13821   ptr_reg (code, sizeflag);
13822 }
13823
13824 static void
13825 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13826 {
13827   int add;
13828   if (rex & REX_R)
13829     {
13830       USED_REX (REX_R);
13831       add = 8;
13832     }
13833   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13834     {
13835       all_prefixes[last_lock_prefix] = 0;
13836       used_prefixes |= PREFIX_LOCK;
13837       add = 8;
13838     }
13839   else
13840     add = 0;
13841   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13842   oappend (scratchbuf + intel_syntax);
13843 }
13844
13845 static void
13846 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13847 {
13848   int add;
13849   USED_REX (REX_R);
13850   if (rex & REX_R)
13851     add = 8;
13852   else
13853     add = 0;
13854   if (intel_syntax)
13855     sprintf (scratchbuf, "db%d", modrm.reg + add);
13856   else
13857     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13858   oappend (scratchbuf);
13859 }
13860
13861 static void
13862 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13863 {
13864   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13865   oappend (scratchbuf + intel_syntax);
13866 }
13867
13868 static void
13869 OP_R (int bytemode, int sizeflag)
13870 {
13871   if (modrm.mod == 3)
13872     OP_E (bytemode, sizeflag);
13873   else
13874     BadOp ();
13875 }
13876
13877 static void
13878 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13879 {
13880   int reg = modrm.reg;
13881   const char **names;
13882
13883   used_prefixes |= (prefixes & PREFIX_DATA);
13884   if (prefixes & PREFIX_DATA)
13885     {
13886       names = names_xmm;
13887       USED_REX (REX_R);
13888       if (rex & REX_R)
13889         reg += 8;
13890     }
13891   else
13892     names = names_mm;
13893   oappend (names[reg]);
13894 }
13895
13896 static void
13897 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13898 {
13899   int reg = modrm.reg;
13900   const char **names;
13901
13902   USED_REX (REX_R);
13903   if (rex & REX_R)
13904     reg += 8;
13905   if (need_vex
13906       && bytemode != xmm_mode
13907       && bytemode != scalar_mode)
13908     {
13909       switch (vex.length)
13910         {
13911         case 128:
13912           names = names_xmm;
13913           break;
13914         case 256:
13915           names = names_ymm;
13916           break;
13917         default:
13918           abort ();
13919         }
13920     }
13921   else
13922     names = names_xmm;
13923   oappend (names[reg]);
13924 }
13925
13926 static void
13927 OP_EM (int bytemode, int sizeflag)
13928 {
13929   int reg;
13930   const char **names;
13931
13932   if (modrm.mod != 3)
13933     {
13934       if (intel_syntax
13935           && (bytemode == v_mode || bytemode == v_swap_mode))
13936         {
13937           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13938           used_prefixes |= (prefixes & PREFIX_DATA);
13939         }
13940       OP_E (bytemode, sizeflag);
13941       return;
13942     }
13943
13944   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13945     swap_operand ();
13946
13947   /* Skip mod/rm byte.  */
13948   MODRM_CHECK;
13949   codep++;
13950   used_prefixes |= (prefixes & PREFIX_DATA);
13951   reg = modrm.rm;
13952   if (prefixes & PREFIX_DATA)
13953     {
13954       names = names_xmm;
13955       USED_REX (REX_B);
13956       if (rex & REX_B)
13957         reg += 8;
13958     }
13959   else
13960     names = names_mm;
13961   oappend (names[reg]);
13962 }
13963
13964 /* cvt* are the only instructions in sse2 which have
13965    both SSE and MMX operands and also have 0x66 prefix
13966    in their opcode. 0x66 was originally used to differentiate
13967    between SSE and MMX instruction(operands). So we have to handle the
13968    cvt* separately using OP_EMC and OP_MXC */
13969 static void
13970 OP_EMC (int bytemode, int sizeflag)
13971 {
13972   if (modrm.mod != 3)
13973     {
13974       if (intel_syntax && bytemode == v_mode)
13975         {
13976           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13977           used_prefixes |= (prefixes & PREFIX_DATA);
13978         }
13979       OP_E (bytemode, sizeflag);
13980       return;
13981     }
13982
13983   /* Skip mod/rm byte.  */
13984   MODRM_CHECK;
13985   codep++;
13986   used_prefixes |= (prefixes & PREFIX_DATA);
13987   oappend (names_mm[modrm.rm]);
13988 }
13989
13990 static void
13991 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13992 {
13993   used_prefixes |= (prefixes & PREFIX_DATA);
13994   oappend (names_mm[modrm.reg]);
13995 }
13996
13997 static void
13998 OP_EX (int bytemode, int sizeflag)
13999 {
14000   int reg;
14001   const char **names;
14002
14003   /* Skip mod/rm byte.  */
14004   MODRM_CHECK;
14005   codep++;
14006
14007   if (modrm.mod != 3)
14008     {
14009       OP_E_memory (bytemode, sizeflag);
14010       return;
14011     }
14012
14013   reg = modrm.rm;
14014   USED_REX (REX_B);
14015   if (rex & REX_B)
14016     reg += 8;
14017
14018   if ((sizeflag & SUFFIX_ALWAYS)
14019       && (bytemode == x_swap_mode
14020           || bytemode == d_swap_mode
14021           || bytemode == d_scalar_swap_mode
14022           || bytemode == q_swap_mode
14023           || bytemode == q_scalar_swap_mode))
14024     swap_operand ();
14025
14026   if (need_vex
14027       && bytemode != xmm_mode
14028       && bytemode != xmmq_mode
14029       && bytemode != d_scalar_mode
14030       && bytemode != d_scalar_swap_mode
14031       && bytemode != q_scalar_mode
14032       && bytemode != q_scalar_swap_mode
14033       && bytemode != vex_scalar_w_dq_mode)
14034     {
14035       switch (vex.length)
14036         {
14037         case 128:
14038           names = names_xmm;
14039           break;
14040         case 256:
14041           names = names_ymm;
14042           break;
14043         default:
14044           abort ();
14045         }
14046     }
14047   else
14048     names = names_xmm;
14049   oappend (names[reg]);
14050 }
14051
14052 static void
14053 OP_MS (int bytemode, int sizeflag)
14054 {
14055   if (modrm.mod == 3)
14056     OP_EM (bytemode, sizeflag);
14057   else
14058     BadOp ();
14059 }
14060
14061 static void
14062 OP_XS (int bytemode, int sizeflag)
14063 {
14064   if (modrm.mod == 3)
14065     OP_EX (bytemode, sizeflag);
14066   else
14067     BadOp ();
14068 }
14069
14070 static void
14071 OP_M (int bytemode, int sizeflag)
14072 {
14073   if (modrm.mod == 3)
14074     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14075     BadOp ();
14076   else
14077     OP_E (bytemode, sizeflag);
14078 }
14079
14080 static void
14081 OP_0f07 (int bytemode, int sizeflag)
14082 {
14083   if (modrm.mod != 3 || modrm.rm != 0)
14084     BadOp ();
14085   else
14086     OP_E (bytemode, sizeflag);
14087 }
14088
14089 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14090    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14091
14092 static void
14093 NOP_Fixup1 (int bytemode, int sizeflag)
14094 {
14095   if ((prefixes & PREFIX_DATA) != 0
14096       || (rex != 0
14097           && rex != 0x48
14098           && address_mode == mode_64bit))
14099     OP_REG (bytemode, sizeflag);
14100   else
14101     strcpy (obuf, "nop");
14102 }
14103
14104 static void
14105 NOP_Fixup2 (int bytemode, int sizeflag)
14106 {
14107   if ((prefixes & PREFIX_DATA) != 0
14108       || (rex != 0
14109           && rex != 0x48
14110           && address_mode == mode_64bit))
14111     OP_IMREG (bytemode, sizeflag);
14112 }
14113
14114 static const char *const Suffix3DNow[] = {
14115 /* 00 */        NULL,           NULL,           NULL,           NULL,
14116 /* 04 */        NULL,           NULL,           NULL,           NULL,
14117 /* 08 */        NULL,           NULL,           NULL,           NULL,
14118 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14119 /* 10 */        NULL,           NULL,           NULL,           NULL,
14120 /* 14 */        NULL,           NULL,           NULL,           NULL,
14121 /* 18 */        NULL,           NULL,           NULL,           NULL,
14122 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14123 /* 20 */        NULL,           NULL,           NULL,           NULL,
14124 /* 24 */        NULL,           NULL,           NULL,           NULL,
14125 /* 28 */        NULL,           NULL,           NULL,           NULL,
14126 /* 2C */        NULL,           NULL,           NULL,           NULL,
14127 /* 30 */        NULL,           NULL,           NULL,           NULL,
14128 /* 34 */        NULL,           NULL,           NULL,           NULL,
14129 /* 38 */        NULL,           NULL,           NULL,           NULL,
14130 /* 3C */        NULL,           NULL,           NULL,           NULL,
14131 /* 40 */        NULL,           NULL,           NULL,           NULL,
14132 /* 44 */        NULL,           NULL,           NULL,           NULL,
14133 /* 48 */        NULL,           NULL,           NULL,           NULL,
14134 /* 4C */        NULL,           NULL,           NULL,           NULL,
14135 /* 50 */        NULL,           NULL,           NULL,           NULL,
14136 /* 54 */        NULL,           NULL,           NULL,           NULL,
14137 /* 58 */        NULL,           NULL,           NULL,           NULL,
14138 /* 5C */        NULL,           NULL,           NULL,           NULL,
14139 /* 60 */        NULL,           NULL,           NULL,           NULL,
14140 /* 64 */        NULL,           NULL,           NULL,           NULL,
14141 /* 68 */        NULL,           NULL,           NULL,           NULL,
14142 /* 6C */        NULL,           NULL,           NULL,           NULL,
14143 /* 70 */        NULL,           NULL,           NULL,           NULL,
14144 /* 74 */        NULL,           NULL,           NULL,           NULL,
14145 /* 78 */        NULL,           NULL,           NULL,           NULL,
14146 /* 7C */        NULL,           NULL,           NULL,           NULL,
14147 /* 80 */        NULL,           NULL,           NULL,           NULL,
14148 /* 84 */        NULL,           NULL,           NULL,           NULL,
14149 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14150 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14151 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14152 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14153 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14154 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14155 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14156 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14157 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14158 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14159 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14160 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14161 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14162 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14163 /* C0 */        NULL,           NULL,           NULL,           NULL,
14164 /* C4 */        NULL,           NULL,           NULL,           NULL,
14165 /* C8 */        NULL,           NULL,           NULL,           NULL,
14166 /* CC */        NULL,           NULL,           NULL,           NULL,
14167 /* D0 */        NULL,           NULL,           NULL,           NULL,
14168 /* D4 */        NULL,           NULL,           NULL,           NULL,
14169 /* D8 */        NULL,           NULL,           NULL,           NULL,
14170 /* DC */        NULL,           NULL,           NULL,           NULL,
14171 /* E0 */        NULL,           NULL,           NULL,           NULL,
14172 /* E4 */        NULL,           NULL,           NULL,           NULL,
14173 /* E8 */        NULL,           NULL,           NULL,           NULL,
14174 /* EC */        NULL,           NULL,           NULL,           NULL,
14175 /* F0 */        NULL,           NULL,           NULL,           NULL,
14176 /* F4 */        NULL,           NULL,           NULL,           NULL,
14177 /* F8 */        NULL,           NULL,           NULL,           NULL,
14178 /* FC */        NULL,           NULL,           NULL,           NULL,
14179 };
14180
14181 static void
14182 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14183 {
14184   const char *mnemonic;
14185
14186   FETCH_DATA (the_info, codep + 1);
14187   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14188      place where an 8-bit immediate would normally go.  ie. the last
14189      byte of the instruction.  */
14190   obufp = mnemonicendp;
14191   mnemonic = Suffix3DNow[*codep++ & 0xff];
14192   if (mnemonic)
14193     oappend (mnemonic);
14194   else
14195     {
14196       /* Since a variable sized modrm/sib chunk is between the start
14197          of the opcode (0x0f0f) and the opcode suffix, we need to do
14198          all the modrm processing first, and don't know until now that
14199          we have a bad opcode.  This necessitates some cleaning up.  */
14200       op_out[0][0] = '\0';
14201       op_out[1][0] = '\0';
14202       BadOp ();
14203     }
14204   mnemonicendp = obufp;
14205 }
14206
14207 static struct op simd_cmp_op[] =
14208 {
14209   { STRING_COMMA_LEN ("eq") },
14210   { STRING_COMMA_LEN ("lt") },
14211   { STRING_COMMA_LEN ("le") },
14212   { STRING_COMMA_LEN ("unord") },
14213   { STRING_COMMA_LEN ("neq") },
14214   { STRING_COMMA_LEN ("nlt") },
14215   { STRING_COMMA_LEN ("nle") },
14216   { STRING_COMMA_LEN ("ord") }
14217 };
14218
14219 static void
14220 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14221 {
14222   unsigned int cmp_type;
14223
14224   FETCH_DATA (the_info, codep + 1);
14225   cmp_type = *codep++ & 0xff;
14226   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14227     {
14228       char suffix [3];
14229       char *p = mnemonicendp - 2;
14230       suffix[0] = p[0];
14231       suffix[1] = p[1];
14232       suffix[2] = '\0';
14233       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14234       mnemonicendp += simd_cmp_op[cmp_type].len;
14235     }
14236   else
14237     {
14238       /* We have a reserved extension byte.  Output it directly.  */
14239       scratchbuf[0] = '$';
14240       print_operand_value (scratchbuf + 1, 1, cmp_type);
14241       oappend (scratchbuf + intel_syntax);
14242       scratchbuf[0] = '\0';
14243     }
14244 }
14245
14246 static void
14247 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14248           int sizeflag ATTRIBUTE_UNUSED)
14249 {
14250   /* mwait %eax,%ecx  */
14251   if (!intel_syntax)
14252     {
14253       const char **names = (address_mode == mode_64bit
14254                             ? names64 : names32);
14255       strcpy (op_out[0], names[0]);
14256       strcpy (op_out[1], names[1]);
14257       two_source_ops = 1;
14258     }
14259   /* Skip mod/rm byte.  */
14260   MODRM_CHECK;
14261   codep++;
14262 }
14263
14264 static void
14265 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14266             int sizeflag ATTRIBUTE_UNUSED)
14267 {
14268   /* monitor %eax,%ecx,%edx"  */
14269   if (!intel_syntax)
14270     {
14271       const char **op1_names;
14272       const char **names = (address_mode == mode_64bit
14273                             ? names64 : names32);
14274
14275       if (!(prefixes & PREFIX_ADDR))
14276         op1_names = (address_mode == mode_16bit
14277                      ? names16 : names);
14278       else
14279         {
14280           /* Remove "addr16/addr32".  */
14281           all_prefixes[last_addr_prefix] = 0;
14282           op1_names = (address_mode != mode_32bit
14283                        ? names32 : names16);
14284           used_prefixes |= PREFIX_ADDR;
14285         }
14286       strcpy (op_out[0], op1_names[0]);
14287       strcpy (op_out[1], names[1]);
14288       strcpy (op_out[2], names[2]);
14289       two_source_ops = 1;
14290     }
14291   /* Skip mod/rm byte.  */
14292   MODRM_CHECK;
14293   codep++;
14294 }
14295
14296 static void
14297 BadOp (void)
14298 {
14299   /* Throw away prefixes and 1st. opcode byte.  */
14300   codep = insn_codep + 1;
14301   oappend ("(bad)");
14302 }
14303
14304 static void
14305 REP_Fixup (int bytemode, int sizeflag)
14306 {
14307   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14308      lods and stos.  */
14309   if (prefixes & PREFIX_REPZ)
14310     all_prefixes[last_repz_prefix] = REP_PREFIX;
14311
14312   switch (bytemode)
14313     {
14314     case al_reg:
14315     case eAX_reg:
14316     case indir_dx_reg:
14317       OP_IMREG (bytemode, sizeflag);
14318       break;
14319     case eDI_reg:
14320       OP_ESreg (bytemode, sizeflag);
14321       break;
14322     case eSI_reg:
14323       OP_DSreg (bytemode, sizeflag);
14324       break;
14325     default:
14326       abort ();
14327       break;
14328     }
14329 }
14330
14331 static void
14332 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14333 {
14334   USED_REX (REX_W);
14335   if (rex & REX_W)
14336     {
14337       /* Change cmpxchg8b to cmpxchg16b.  */
14338       char *p = mnemonicendp - 2;
14339       mnemonicendp = stpcpy (p, "16b");
14340       bytemode = o_mode;
14341     }
14342   OP_M (bytemode, sizeflag);
14343 }
14344
14345 static void
14346 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14347 {
14348   const char **names;
14349
14350   if (need_vex)
14351     {
14352       switch (vex.length)
14353         {
14354         case 128:
14355           names = names_xmm;
14356           break;
14357         case 256:
14358           names = names_ymm;
14359           break;
14360         default:
14361           abort ();
14362         }
14363     }
14364   else
14365     names = names_xmm;
14366   oappend (names[reg]);
14367 }
14368
14369 static void
14370 CRC32_Fixup (int bytemode, int sizeflag)
14371 {
14372   /* Add proper suffix to "crc32".  */
14373   char *p = mnemonicendp;
14374
14375   switch (bytemode)
14376     {
14377     case b_mode:
14378       if (intel_syntax)
14379         goto skip;
14380
14381       *p++ = 'b';
14382       break;
14383     case v_mode:
14384       if (intel_syntax)
14385         goto skip;
14386
14387       USED_REX (REX_W);
14388       if (rex & REX_W)
14389         *p++ = 'q';
14390       else
14391         {
14392           if (sizeflag & DFLAG)
14393             *p++ = 'l';
14394           else
14395             *p++ = 'w';
14396           used_prefixes |= (prefixes & PREFIX_DATA);
14397         }
14398       break;
14399     default:
14400       oappend (INTERNAL_DISASSEMBLER_ERROR);
14401       break;
14402     }
14403   mnemonicendp = p;
14404   *p = '\0';
14405
14406 skip:
14407   if (modrm.mod == 3)
14408     {
14409       int add;
14410
14411       /* Skip mod/rm byte.  */
14412       MODRM_CHECK;
14413       codep++;
14414
14415       USED_REX (REX_B);
14416       add = (rex & REX_B) ? 8 : 0;
14417       if (bytemode == b_mode)
14418         {
14419           USED_REX (0);
14420           if (rex)
14421             oappend (names8rex[modrm.rm + add]);
14422           else
14423             oappend (names8[modrm.rm + add]);
14424         }
14425       else
14426         {
14427           USED_REX (REX_W);
14428           if (rex & REX_W)
14429             oappend (names64[modrm.rm + add]);
14430           else if ((prefixes & PREFIX_DATA))
14431             oappend (names16[modrm.rm + add]);
14432           else
14433             oappend (names32[modrm.rm + add]);
14434         }
14435     }
14436   else
14437     OP_E (bytemode, sizeflag);
14438 }
14439
14440 static void
14441 FXSAVE_Fixup (int bytemode, int sizeflag)
14442 {
14443   /* Add proper suffix to "fxsave" and "fxrstor".  */
14444   USED_REX (REX_W);
14445   if (rex & REX_W)
14446     {
14447       char *p = mnemonicendp;
14448       *p++ = '6';
14449       *p++ = '4';
14450       *p = '\0';
14451       mnemonicendp = p;
14452     }
14453   OP_M (bytemode, sizeflag);
14454 }
14455
14456 /* Display the destination register operand for instructions with
14457    VEX. */
14458
14459 static void
14460 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14461 {
14462   int reg;
14463   const char **names;
14464
14465   if (!need_vex)
14466     abort ();
14467
14468   if (!need_vex_reg)
14469     return;
14470
14471   reg = vex.register_specifier;
14472   if (bytemode == vex_scalar_mode)
14473     {
14474       oappend (names_xmm[reg]);
14475       return;
14476     }
14477
14478   switch (vex.length)
14479     {
14480     case 128:
14481       switch (bytemode)
14482         {
14483         case vex_mode:
14484         case vex128_mode:
14485           break;
14486         default:
14487           abort ();
14488           return;
14489         }
14490
14491       names = names_xmm;
14492       break;
14493     case 256:
14494       switch (bytemode)
14495         {
14496         case vex_mode:
14497         case vex256_mode:
14498           break;
14499         default:
14500           abort ();
14501           return;
14502         }
14503
14504       names = names_ymm;
14505       break;
14506     default:
14507       abort ();
14508       break;
14509     }
14510   oappend (names[reg]);
14511 }
14512
14513 /* Get the VEX immediate byte without moving codep.  */
14514
14515 static unsigned char
14516 get_vex_imm8 (int sizeflag, int opnum)
14517 {
14518   int bytes_before_imm = 0;
14519
14520   if (modrm.mod != 3)
14521     {
14522       /* There are SIB/displacement bytes.  */
14523       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14524         {
14525           /* 32/64 bit address mode */
14526           int base = modrm.rm;
14527
14528           /* Check SIB byte.  */
14529           if (base == 4)
14530             {
14531               FETCH_DATA (the_info, codep + 1);
14532               base = *codep & 7;
14533               /* When decoding the third source, don't increase
14534                  bytes_before_imm as this has already been incremented
14535                  by one in OP_E_memory while decoding the second
14536                  source operand.  */
14537               if (opnum == 0)
14538                 bytes_before_imm++;
14539             }
14540
14541           /* Don't increase bytes_before_imm when decoding the third source,
14542              it has already been incremented by OP_E_memory while decoding
14543              the second source operand.  */
14544           if (opnum == 0)
14545             {
14546               switch (modrm.mod)
14547                 {
14548                   case 0:
14549                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14550                        SIB == 5, there is a 4 byte displacement.  */
14551                     if (base != 5)
14552                       /* No displacement. */
14553                       break;
14554                   case 2:
14555                     /* 4 byte displacement.  */
14556                     bytes_before_imm += 4;
14557                     break;
14558                   case 1:
14559                     /* 1 byte displacement.  */
14560                     bytes_before_imm++;
14561                     break;
14562                 }
14563             }
14564         }
14565       else
14566         {
14567           /* 16 bit address mode */
14568           /* Don't increase bytes_before_imm when decoding the third source,
14569              it has already been incremented by OP_E_memory while decoding
14570              the second source operand.  */
14571           if (opnum == 0)
14572             {
14573               switch (modrm.mod)
14574                 {
14575                 case 0:
14576                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14577                   if (modrm.rm != 6)
14578                     /* No displacement. */
14579                     break;
14580                 case 2:
14581                   /* 2 byte displacement.  */
14582                   bytes_before_imm += 2;
14583                   break;
14584                 case 1:
14585                   /* 1 byte displacement: when decoding the third source,
14586                      don't increase bytes_before_imm as this has already
14587                      been incremented by one in OP_E_memory while decoding
14588                      the second source operand.  */
14589                   if (opnum == 0)
14590                     bytes_before_imm++;
14591
14592                   break;
14593                 }
14594             }
14595         }
14596     }
14597
14598   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14599   return codep [bytes_before_imm];
14600 }
14601
14602 static void
14603 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14604 {
14605   const char **names;
14606
14607   if (reg == -1 && modrm.mod != 3)
14608     {
14609       OP_E_memory (bytemode, sizeflag);
14610       return;
14611     }
14612   else
14613     {
14614       if (reg == -1)
14615         {
14616           reg = modrm.rm;
14617           USED_REX (REX_B);
14618           if (rex & REX_B)
14619             reg += 8;
14620         }
14621       else if (reg > 7 && address_mode != mode_64bit)
14622         BadOp ();
14623     }
14624
14625   switch (vex.length)
14626     {
14627     case 128:
14628       names = names_xmm;
14629       break;
14630     case 256:
14631       names = names_ymm;
14632       break;
14633     default:
14634       abort ();
14635     }
14636   oappend (names[reg]);
14637 }
14638
14639 static void
14640 OP_EX_VexImmW (int bytemode, int sizeflag)
14641 {
14642   int reg = -1;
14643   static unsigned char vex_imm8;
14644
14645   if (vex_w_done == 0)
14646     {
14647       vex_w_done = 1;
14648
14649       /* Skip mod/rm byte.  */
14650       MODRM_CHECK;
14651       codep++;
14652
14653       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14654
14655       if (vex.w)
14656           reg = vex_imm8 >> 4;
14657
14658       OP_EX_VexReg (bytemode, sizeflag, reg);
14659     }
14660   else if (vex_w_done == 1)
14661     {
14662       vex_w_done = 2;
14663
14664       if (!vex.w)
14665           reg = vex_imm8 >> 4;
14666
14667       OP_EX_VexReg (bytemode, sizeflag, reg);
14668     }
14669   else
14670     {
14671       /* Output the imm8 directly.  */
14672       scratchbuf[0] = '$';
14673       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14674       oappend (scratchbuf + intel_syntax);
14675       scratchbuf[0] = '\0';
14676       codep++;
14677     }
14678 }
14679
14680 static void
14681 OP_Vex_2src (int bytemode, int sizeflag)
14682 {
14683   if (modrm.mod == 3)
14684     {
14685       int reg = modrm.rm;
14686       USED_REX (REX_B);
14687       if (rex & REX_B)
14688         reg += 8;
14689       oappend (names_xmm[reg]);
14690     }
14691   else
14692     {
14693       if (intel_syntax
14694           && (bytemode == v_mode || bytemode == v_swap_mode))
14695         {
14696           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14697           used_prefixes |= (prefixes & PREFIX_DATA);
14698         }
14699       OP_E (bytemode, sizeflag);
14700     }
14701 }
14702
14703 static void
14704 OP_Vex_2src_1 (int bytemode, int sizeflag)
14705 {
14706   if (modrm.mod == 3)
14707     {
14708       /* Skip mod/rm byte.   */
14709       MODRM_CHECK;
14710       codep++;
14711     }
14712
14713   if (vex.w)
14714     oappend (names_xmm[vex.register_specifier]);
14715   else
14716     OP_Vex_2src (bytemode, sizeflag);
14717 }
14718
14719 static void
14720 OP_Vex_2src_2 (int bytemode, int sizeflag)
14721 {
14722   if (vex.w)
14723     OP_Vex_2src (bytemode, sizeflag);
14724   else
14725     oappend (names_xmm[vex.register_specifier]);
14726 }
14727
14728 static void
14729 OP_EX_VexW (int bytemode, int sizeflag)
14730 {
14731   int reg = -1;
14732
14733   if (!vex_w_done)
14734     {
14735       vex_w_done = 1;
14736
14737       /* Skip mod/rm byte.  */
14738       MODRM_CHECK;
14739       codep++;
14740
14741       if (vex.w)
14742         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14743     }
14744   else
14745     {
14746       if (!vex.w)
14747         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14748     }
14749
14750   OP_EX_VexReg (bytemode, sizeflag, reg);
14751 }
14752
14753 static void
14754 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14755              int sizeflag ATTRIBUTE_UNUSED)
14756 {
14757   /* Skip the immediate byte and check for invalid bits.  */
14758   FETCH_DATA (the_info, codep + 1);
14759   if (*codep++ & 0xf)
14760     BadOp ();
14761 }
14762
14763 static void
14764 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14765 {
14766   int reg;
14767   const char **names;
14768
14769   FETCH_DATA (the_info, codep + 1);
14770   reg = *codep++;
14771
14772   if (bytemode != x_mode)
14773     abort ();
14774
14775   if (reg & 0xf)
14776       BadOp ();
14777
14778   reg >>= 4;
14779   if (reg > 7 && address_mode != mode_64bit)
14780     BadOp ();
14781
14782   switch (vex.length)
14783     {
14784     case 128:
14785       names = names_xmm;
14786       break;
14787     case 256:
14788       names = names_ymm;
14789       break;
14790     default:
14791       abort ();
14792     }
14793   oappend (names[reg]);
14794 }
14795
14796 static void
14797 OP_XMM_VexW (int bytemode, int sizeflag)
14798 {
14799   /* Turn off the REX.W bit since it is used for swapping operands
14800      now.  */
14801   rex &= ~REX_W;
14802   OP_XMM (bytemode, sizeflag);
14803 }
14804
14805 static void
14806 OP_EX_Vex (int bytemode, int sizeflag)
14807 {
14808   if (modrm.mod != 3)
14809     {
14810       if (vex.register_specifier != 0)
14811         BadOp ();
14812       need_vex_reg = 0;
14813     }
14814   OP_EX (bytemode, sizeflag);
14815 }
14816
14817 static void
14818 OP_XMM_Vex (int bytemode, int sizeflag)
14819 {
14820   if (modrm.mod != 3)
14821     {
14822       if (vex.register_specifier != 0)
14823         BadOp ();
14824       need_vex_reg = 0;
14825     }
14826   OP_XMM (bytemode, sizeflag);
14827 }
14828
14829 static void
14830 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14831 {
14832   switch (vex.length)
14833     {
14834     case 128:
14835       mnemonicendp = stpcpy (obuf, "vzeroupper");
14836       break;
14837     case 256:
14838       mnemonicendp = stpcpy (obuf, "vzeroall");
14839       break;
14840     default:
14841       abort ();
14842     }
14843 }
14844
14845 static struct op vex_cmp_op[] =
14846 {
14847   { STRING_COMMA_LEN ("eq") },
14848   { STRING_COMMA_LEN ("lt") },
14849   { STRING_COMMA_LEN ("le") },
14850   { STRING_COMMA_LEN ("unord") },
14851   { STRING_COMMA_LEN ("neq") },
14852   { STRING_COMMA_LEN ("nlt") },
14853   { STRING_COMMA_LEN ("nle") },
14854   { STRING_COMMA_LEN ("ord") },
14855   { STRING_COMMA_LEN ("eq_uq") },
14856   { STRING_COMMA_LEN ("nge") },
14857   { STRING_COMMA_LEN ("ngt") },
14858   { STRING_COMMA_LEN ("false") },
14859   { STRING_COMMA_LEN ("neq_oq") },
14860   { STRING_COMMA_LEN ("ge") },
14861   { STRING_COMMA_LEN ("gt") },
14862   { STRING_COMMA_LEN ("true") },
14863   { STRING_COMMA_LEN ("eq_os") },
14864   { STRING_COMMA_LEN ("lt_oq") },
14865   { STRING_COMMA_LEN ("le_oq") },
14866   { STRING_COMMA_LEN ("unord_s") },
14867   { STRING_COMMA_LEN ("neq_us") },
14868   { STRING_COMMA_LEN ("nlt_uq") },
14869   { STRING_COMMA_LEN ("nle_uq") },
14870   { STRING_COMMA_LEN ("ord_s") },
14871   { STRING_COMMA_LEN ("eq_us") },
14872   { STRING_COMMA_LEN ("nge_uq") },
14873   { STRING_COMMA_LEN ("ngt_uq") },
14874   { STRING_COMMA_LEN ("false_os") },
14875   { STRING_COMMA_LEN ("neq_os") },
14876   { STRING_COMMA_LEN ("ge_oq") },
14877   { STRING_COMMA_LEN ("gt_oq") },
14878   { STRING_COMMA_LEN ("true_us") },
14879 };
14880
14881 static void
14882 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14883 {
14884   unsigned int cmp_type;
14885
14886   FETCH_DATA (the_info, codep + 1);
14887   cmp_type = *codep++ & 0xff;
14888   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14889     {
14890       char suffix [3];
14891       char *p = mnemonicendp - 2;
14892       suffix[0] = p[0];
14893       suffix[1] = p[1];
14894       suffix[2] = '\0';
14895       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14896       mnemonicendp += vex_cmp_op[cmp_type].len;
14897     }
14898   else
14899     {
14900       /* We have a reserved extension byte.  Output it directly.  */
14901       scratchbuf[0] = '$';
14902       print_operand_value (scratchbuf + 1, 1, cmp_type);
14903       oappend (scratchbuf + intel_syntax);
14904       scratchbuf[0] = '\0';
14905     }
14906 }
14907
14908 static const struct op pclmul_op[] =
14909 {
14910   { STRING_COMMA_LEN ("lql") },
14911   { STRING_COMMA_LEN ("hql") },
14912   { STRING_COMMA_LEN ("lqh") },
14913   { STRING_COMMA_LEN ("hqh") }
14914 };
14915
14916 static void
14917 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14918               int sizeflag ATTRIBUTE_UNUSED)
14919 {
14920   unsigned int pclmul_type;
14921
14922   FETCH_DATA (the_info, codep + 1);
14923   pclmul_type = *codep++ & 0xff;
14924   switch (pclmul_type)
14925     {
14926     case 0x10:
14927       pclmul_type = 2;
14928       break;
14929     case 0x11:
14930       pclmul_type = 3;
14931       break;
14932     default:
14933       break;
14934     }
14935   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14936     {
14937       char suffix [4];
14938       char *p = mnemonicendp - 3;
14939       suffix[0] = p[0];
14940       suffix[1] = p[1];
14941       suffix[2] = p[2];
14942       suffix[3] = '\0';
14943       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14944       mnemonicendp += pclmul_op[pclmul_type].len;
14945     }
14946   else
14947     {
14948       /* We have a reserved extension byte.  Output it directly.  */
14949       scratchbuf[0] = '$';
14950       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14951       oappend (scratchbuf + intel_syntax);
14952       scratchbuf[0] = '\0';
14953     }
14954 }
14955
14956 static void
14957 MOVBE_Fixup (int bytemode, int sizeflag)
14958 {
14959   /* Add proper suffix to "movbe".  */
14960   char *p = mnemonicendp;
14961
14962   switch (bytemode)
14963     {
14964     case v_mode:
14965       if (intel_syntax)
14966         goto skip;
14967
14968       USED_REX (REX_W);
14969       if (sizeflag & SUFFIX_ALWAYS)
14970         {
14971           if (rex & REX_W)
14972             *p++ = 'q';
14973           else
14974             {
14975               if (sizeflag & DFLAG)
14976                 *p++ = 'l';
14977               else
14978                 *p++ = 'w';
14979               used_prefixes |= (prefixes & PREFIX_DATA);
14980             }
14981         }
14982       break;
14983     default:
14984       oappend (INTERNAL_DISASSEMBLER_ERROR);
14985       break;
14986     }
14987   mnemonicendp = p;
14988   *p = '\0';
14989
14990 skip:
14991   OP_M (bytemode, sizeflag);
14992 }
14993
14994 static void
14995 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14996 {
14997   int reg;
14998   const char **names;
14999
15000   /* Skip mod/rm byte.  */
15001   MODRM_CHECK;
15002   codep++;
15003
15004   if (vex.w)
15005     names = names64;
15006   else
15007     names = names32;
15008
15009   reg = modrm.rm;
15010   USED_REX (REX_B);
15011   if (rex & REX_B)
15012     reg += 8;
15013
15014   oappend (names[reg]);
15015 }
15016
15017 static void
15018 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15019 {
15020   const char **names;
15021
15022   if (vex.w)
15023     names = names64;
15024   else
15025     names = names32;
15026
15027   oappend (names[vex.register_specifier]);
15028 }
15029