opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 389 #define EXq { OP_EX, q_mode }
 390 #define EXqScalar { OP_EX, q_scalar_mode }
 391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 392 #define EXqS { OP_EX, q_swap_mode }
 393 #define EXx { OP_EX, x_mode }
 394 #define EXxS { OP_EX, x_swap_mode }
 395 #define EXxmm { OP_EX, xmm_mode }
 396 #define EXymm { OP_EX, ymm_mode }
 397 #define EXxmmq { OP_EX, xmmq_mode }
 398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 401 #define EXxmm_md { OP_EX, xmm_md_mode }
 402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 411 #define MS { OP_MS, v_mode }
 412 #define XS { OP_XS, v_mode }
 413 #define EMCq { OP_EMC, q_mode }
 414 #define MXC { OP_MXC, 0 }
 415 #define OPSUF { OP_3DNowSuffix, 0 }
 416 #define CMP { CMP_Fixup, 0 }
 417 #define XMM0 { XMM_Fixup, 0 }
 418 #define FXSAVE { FXSAVE_Fixup, 0 }
 419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 421
 422 #define Vex { OP_VEX, vex_mode }
 423 #define VexScalar { OP_VEX, vex_scalar_mode }
 424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 425 #define Vex128 { OP_VEX, vex128_mode }
 426 #define Vex256 { OP_VEX, vex256_mode }
 427 #define VexGdq { OP_VEX, dq_mode }
 428 #define EXdVex { OP_EX_Vex, d_mode }
 429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 431 #define EXqVex { OP_EX_Vex, q_mode }
 432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 434 #define EXVexW { OP_EX_VexW, x_mode }
 435 #define EXdVexW { OP_EX_VexW, d_mode }
 436 #define EXqVexW { OP_EX_VexW, q_mode }
 437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 438 #define XMVex { OP_XMM_Vex, 0 }
 439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 440 #define XMVexW { OP_XMM_VexW, 0 }
 441 #define XMVexI4 { OP_REG_VexI4, x_mode }
 442 #define PCLMUL { PCLMUL_Fixup, 0 }
 443 #define VCMP { VCMP_Fixup, 0 }
 444 #define VPCMP { VPCMP_Fixup, 0 }
 445 #define VPCOM { VPCOM_Fixup, 0 }
 446
 447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 448 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 449 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 450
 451 #define XMask { OP_Mask, mask_mode }
 452 #define MaskG { OP_G, mask_mode }
 453 #define MaskE { OP_E, mask_mode }
 454 #define MaskBDE { OP_E, mask_bd_mode }
 455 #define MaskR { OP_R, mask_mode }
 456 #define MaskVex { OP_VEX, mask_mode }
 457
 458 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 459 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 460 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 461 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 462
 463 /* Used handle "rep" prefix for string instructions.  */
 464 #define Xbr { REP_Fixup, eSI_reg }
 465 #define Xvr { REP_Fixup, eSI_reg }
 466 #define Ybr { REP_Fixup, eDI_reg }
 467 #define Yvr { REP_Fixup, eDI_reg }
 468 #define Yzr { REP_Fixup, eDI_reg }
 469 #define indirDXr { REP_Fixup, indir_dx_reg }
 470 #define ALr { REP_Fixup, al_reg }
 471 #define eAXr { REP_Fixup, eAX_reg }
 472
 473 /* Used handle HLE prefix for lockable instructions.  */
 474 #define Ebh1 { HLE_Fixup1, b_mode }
 475 #define Evh1 { HLE_Fixup1, v_mode }
 476 #define Ebh2 { HLE_Fixup2, b_mode }
 477 #define Evh2 { HLE_Fixup2, v_mode }
 478 #define Ebh3 { HLE_Fixup3, b_mode }
 479 #define Evh3 { HLE_Fixup3, v_mode }
 480
 481 #define BND { BND_Fixup, 0 }
 482 #define NOTRACK { NOTRACK_Fixup, 0 }
 483
 484 #define cond_jump_flag { NULL, cond_jump_mode }
 485 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 486
 487 /* bits in sizeflag */
 488 #define SUFFIX_ALWAYS 4
 489 #define AFLAG 2
 490 #define DFLAG 1
 491
 492 enum
 493 {
 494   /* byte operand */
 495   b_mode = 1,
 496   /* byte operand with operand swapped */
 497   b_swap_mode,
 498   /* byte operand, sign extend like 'T' suffix */
 499   b_T_mode,
 500   /* operand size depends on prefixes */
 501   v_mode,
 502   /* operand size depends on prefixes with operand swapped */
 503   v_swap_mode,
 504   /* operand size depends on address prefix */
 505   va_mode,
 506   /* word operand */
 507   w_mode,
 508   /* double word operand  */
 509   d_mode,
 510   /* double word operand with operand swapped */
 511   d_swap_mode,
 512   /* quad word operand */
 513   q_mode,
 514   /* quad word operand with operand swapped */
 515   q_swap_mode,
 516   /* ten-byte operand */
 517   t_mode,
 518   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 519      broadcast enabled.  */
 520   x_mode,
 521   /* Similar to x_mode, but with different EVEX mem shifts.  */
 522   evex_x_gscat_mode,
 523   /* Similar to x_mode, but with disabled broadcast.  */
 524   evex_x_nobcst_mode,
 525   /* Similar to x_mode, but with operands swapped and disabled broadcast
 526      in EVEX.  */
 527   x_swap_mode,
 528   /* 16-byte XMM operand */
 529   xmm_mode,
 530   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 531      memory operand (depending on vector length).  Broadcast isn't
 532      allowed.  */
 533   xmmq_mode,
 534   /* Same as xmmq_mode, but broadcast is allowed.  */
 535   evex_half_bcst_xmmq_mode,
 536   /* XMM register or byte memory operand */
 537   xmm_mb_mode,
 538   /* XMM register or word memory operand */
 539   xmm_mw_mode,
 540   /* XMM register or double word memory operand */
 541   xmm_md_mode,
 542   /* XMM register or quad word memory operand */
 543   xmm_mq_mode,
 544   /* XMM register or double/quad word memory operand, depending on
 545      VEX.W.  */
 546   xmm_mdq_mode,
 547   /* 16-byte XMM, word, double word or quad word operand.  */
 548   xmmdw_mode,
 549   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 550   xmmqd_mode,
 551   /* 32-byte YMM operand */
 552   ymm_mode,
 553   /* quad word, ymmword or zmmword memory operand.  */
 554   ymmq_mode,
 555   /* 32-byte YMM or 16-byte word operand */
 556   ymmxmm_mode,
 557   /* d_mode in 32bit, q_mode in 64bit mode.  */
 558   m_mode,
 559   /* pair of v_mode operands */
 560   a_mode,
 561   cond_jump_mode,
 562   loop_jcxz_mode,
 563   v_bnd_mode,
 564   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 565   v_bndmk_mode,
 566   /* operand size depends on REX prefixes.  */
 567   dq_mode,
 568   /* registers like dq_mode, memory like w_mode.  */
 569   dqw_mode,
 570   /* bounds operand */
 571   bnd_mode,
 572   /* bounds operand with operand swapped */
 573   bnd_swap_mode,
 574   /* 4- or 6-byte pointer operand */
 575   f_mode,
 576   const_1_mode,
 577   /* v_mode for indirect branch opcodes.  */
 578   indir_v_mode,
 579   /* v_mode for stack-related opcodes.  */
 580   stack_v_mode,
 581   /* non-quad operand size depends on prefixes */
 582   z_mode,
 583   /* 16-byte operand */
 584   o_mode,
 585   /* registers like dq_mode, memory like b_mode.  */
 586   dqb_mode,
 587   /* registers like d_mode, memory like b_mode.  */
 588   db_mode,
 589   /* registers like d_mode, memory like w_mode.  */
 590   dw_mode,
 591   /* registers like dq_mode, memory like d_mode.  */
 592   dqd_mode,
 593   /* normal vex mode */
 594   vex_mode,
 595   /* 128bit vex mode */
 596   vex128_mode,
 597   /* 256bit vex mode */
 598   vex256_mode,
 599   /* operand size depends on the VEX.W bit.  */
 600   vex_w_dq_mode,
 601
 602   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 603   vex_vsib_d_w_dq_mode,
 604   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 605   vex_vsib_d_w_d_mode,
 606   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 607   vex_vsib_q_w_dq_mode,
 608   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 609   vex_vsib_q_w_d_mode,
 610
 611   /* scalar, ignore vector length.  */
 612   scalar_mode,
 613   /* like b_mode, ignore vector length.  */
 614   b_scalar_mode,
 615   /* like w_mode, ignore vector length.  */
 616   w_scalar_mode,
 617   /* like d_mode, ignore vector length.  */
 618   d_scalar_mode,
 619   /* like d_swap_mode, ignore vector length.  */
 620   d_scalar_swap_mode,
 621   /* like q_mode, ignore vector length.  */
 622   q_scalar_mode,
 623   /* like q_swap_mode, ignore vector length.  */
 624   q_scalar_swap_mode,
 625   /* like vex_mode, ignore vector length.  */
 626   vex_scalar_mode,
 627   /* like vex_w_dq_mode, ignore vector length.  */
 628   vex_scalar_w_dq_mode,
 629
 630   /* Static rounding.  */
 631   evex_rounding_mode,
 632   /* Static rounding, 64-bit mode only.  */
 633   evex_rounding_64_mode,
 634   /* Supress all exceptions.  */
 635   evex_sae_mode,
 636
 637   /* Mask register operand.  */
 638   mask_mode,
 639   /* Mask register operand.  */
 640   mask_bd_mode,
 641
 642   es_reg,
 643   cs_reg,
 644   ss_reg,
 645   ds_reg,
 646   fs_reg,
 647   gs_reg,
 648
 649   eAX_reg,
 650   eCX_reg,
 651   eDX_reg,
 652   eBX_reg,
 653   eSP_reg,
 654   eBP_reg,
 655   eSI_reg,
 656   eDI_reg,
 657
 658   al_reg,
 659   cl_reg,
 660   dl_reg,
 661   bl_reg,
 662   ah_reg,
 663   ch_reg,
 664   dh_reg,
 665   bh_reg,
 666
 667   ax_reg,
 668   cx_reg,
 669   dx_reg,
 670   bx_reg,
 671   sp_reg,
 672   bp_reg,
 673   si_reg,
 674   di_reg,
 675
 676   rAX_reg,
 677   rCX_reg,
 678   rDX_reg,
 679   rBX_reg,
 680   rSP_reg,
 681   rBP_reg,
 682   rSI_reg,
 683   rDI_reg,
 684
 685   z_mode_ax_reg,
 686   indir_dx_reg
 687 };
 688
 689 enum
 690 {
 691   FLOATCODE = 1,
 692   USE_REG_TABLE,
 693   USE_MOD_TABLE,
 694   USE_RM_TABLE,
 695   USE_PREFIX_TABLE,
 696   USE_X86_64_TABLE,
 697   USE_3BYTE_TABLE,
 698   USE_XOP_8F_TABLE,
 699   USE_VEX_C4_TABLE,
 700   USE_VEX_C5_TABLE,
 701   USE_VEX_LEN_TABLE,
 702   USE_VEX_W_TABLE,
 703   USE_EVEX_TABLE,
 704   USE_EVEX_LEN_TABLE
 705 };
 706
 707 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 708
 709 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 710 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 711 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 712 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 713 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 714 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 715 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 716 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 717 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 718 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 719 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 720 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 721 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 722 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 723 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 724 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 725
 726 enum
 727 {
 728   REG_80 = 0,
 729   REG_81,
 730   REG_83,
 731   REG_8F,
 732   REG_C0,
 733   REG_C1,
 734   REG_C6,
 735   REG_C7,
 736   REG_D0,
 737   REG_D1,
 738   REG_D2,
 739   REG_D3,
 740   REG_F6,
 741   REG_F7,
 742   REG_FE,
 743   REG_FF,
 744   REG_0F00,
 745   REG_0F01,
 746   REG_0F0D,
 747   REG_0F18,
 748   REG_0F1C_MOD_0,
 749   REG_0F1E_MOD_3,
 750   REG_0F71,
 751   REG_0F72,
 752   REG_0F73,
 753   REG_0FA6,
 754   REG_0FA7,
 755   REG_0FAE,
 756   REG_0FBA,
 757   REG_0FC7,
 758   REG_VEX_0F71,
 759   REG_VEX_0F72,
 760   REG_VEX_0F73,
 761   REG_VEX_0FAE,
 762   REG_VEX_0F38F3,
 763   REG_XOP_LWPCB,
 764   REG_XOP_LWP,
 765   REG_XOP_TBM_01,
 766   REG_XOP_TBM_02,
 767
 768   REG_EVEX_0F71,
 769   REG_EVEX_0F72,
 770   REG_EVEX_0F73,
 771   REG_EVEX_0F38C6,
 772   REG_EVEX_0F38C7
 773 };
 774
 775 enum
 776 {
 777   MOD_8D = 0,
 778   MOD_C6_REG_7,
 779   MOD_C7_REG_7,
 780   MOD_FF_REG_3,
 781   MOD_FF_REG_5,
 782   MOD_0F01_REG_0,
 783   MOD_0F01_REG_1,
 784   MOD_0F01_REG_2,
 785   MOD_0F01_REG_3,
 786   MOD_0F01_REG_5,
 787   MOD_0F01_REG_7,
 788   MOD_0F12_PREFIX_0,
 789   MOD_0F13,
 790   MOD_0F16_PREFIX_0,
 791   MOD_0F17,
 792   MOD_0F18_REG_0,
 793   MOD_0F18_REG_1,
 794   MOD_0F18_REG_2,
 795   MOD_0F18_REG_3,
 796   MOD_0F18_REG_4,
 797   MOD_0F18_REG_5,
 798   MOD_0F18_REG_6,
 799   MOD_0F18_REG_7,
 800   MOD_0F1A_PREFIX_0,
 801   MOD_0F1B_PREFIX_0,
 802   MOD_0F1B_PREFIX_1,
 803   MOD_0F1C_PREFIX_0,
 804   MOD_0F1E_PREFIX_1,
 805   MOD_0F24,
 806   MOD_0F26,
 807   MOD_0F2B_PREFIX_0,
 808   MOD_0F2B_PREFIX_1,
 809   MOD_0F2B_PREFIX_2,
 810   MOD_0F2B_PREFIX_3,
 811   MOD_0F51,
 812   MOD_0F71_REG_2,
 813   MOD_0F71_REG_4,
 814   MOD_0F71_REG_6,
 815   MOD_0F72_REG_2,
 816   MOD_0F72_REG_4,
 817   MOD_0F72_REG_6,
 818   MOD_0F73_REG_2,
 819   MOD_0F73_REG_3,
 820   MOD_0F73_REG_6,
 821   MOD_0F73_REG_7,
 822   MOD_0FAE_REG_0,
 823   MOD_0FAE_REG_1,
 824   MOD_0FAE_REG_2,
 825   MOD_0FAE_REG_3,
 826   MOD_0FAE_REG_4,
 827   MOD_0FAE_REG_5,
 828   MOD_0FAE_REG_6,
 829   MOD_0FAE_REG_7,
 830   MOD_0FB2,
 831   MOD_0FB4,
 832   MOD_0FB5,
 833   MOD_0FC3,
 834   MOD_0FC7_REG_3,
 835   MOD_0FC7_REG_4,
 836   MOD_0FC7_REG_5,
 837   MOD_0FC7_REG_6,
 838   MOD_0FC7_REG_7,
 839   MOD_0FD7,
 840   MOD_0FE7_PREFIX_2,
 841   MOD_0FF0_PREFIX_3,
 842   MOD_0F382A_PREFIX_2,
 843   MOD_0F38F5_PREFIX_2,
 844   MOD_0F38F6_PREFIX_0,
 845   MOD_0F38F8_PREFIX_1,
 846   MOD_0F38F8_PREFIX_2,
 847   MOD_0F38F8_PREFIX_3,
 848   MOD_0F38F9_PREFIX_0,
 849   MOD_62_32BIT,
 850   MOD_C4_32BIT,
 851   MOD_C5_32BIT,
 852   MOD_VEX_0F12_PREFIX_0,
 853   MOD_VEX_0F13,
 854   MOD_VEX_0F16_PREFIX_0,
 855   MOD_VEX_0F17,
 856   MOD_VEX_0F2B,
 857   MOD_VEX_W_0_0F41_P_0_LEN_1,
 858   MOD_VEX_W_1_0F41_P_0_LEN_1,
 859   MOD_VEX_W_0_0F41_P_2_LEN_1,
 860   MOD_VEX_W_1_0F41_P_2_LEN_1,
 861   MOD_VEX_W_0_0F42_P_0_LEN_1,
 862   MOD_VEX_W_1_0F42_P_0_LEN_1,
 863   MOD_VEX_W_0_0F42_P_2_LEN_1,
 864   MOD_VEX_W_1_0F42_P_2_LEN_1,
 865   MOD_VEX_W_0_0F44_P_0_LEN_1,
 866   MOD_VEX_W_1_0F44_P_0_LEN_1,
 867   MOD_VEX_W_0_0F44_P_2_LEN_1,
 868   MOD_VEX_W_1_0F44_P_2_LEN_1,
 869   MOD_VEX_W_0_0F45_P_0_LEN_1,
 870   MOD_VEX_W_1_0F45_P_0_LEN_1,
 871   MOD_VEX_W_0_0F45_P_2_LEN_1,
 872   MOD_VEX_W_1_0F45_P_2_LEN_1,
 873   MOD_VEX_W_0_0F46_P_0_LEN_1,
 874   MOD_VEX_W_1_0F46_P_0_LEN_1,
 875   MOD_VEX_W_0_0F46_P_2_LEN_1,
 876   MOD_VEX_W_1_0F46_P_2_LEN_1,
 877   MOD_VEX_W_0_0F47_P_0_LEN_1,
 878   MOD_VEX_W_1_0F47_P_0_LEN_1,
 879   MOD_VEX_W_0_0F47_P_2_LEN_1,
 880   MOD_VEX_W_1_0F47_P_2_LEN_1,
 881   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 882   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 884   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 886   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 888   MOD_VEX_0F50,
 889   MOD_VEX_0F71_REG_2,
 890   MOD_VEX_0F71_REG_4,
 891   MOD_VEX_0F71_REG_6,
 892   MOD_VEX_0F72_REG_2,
 893   MOD_VEX_0F72_REG_4,
 894   MOD_VEX_0F72_REG_6,
 895   MOD_VEX_0F73_REG_2,
 896   MOD_VEX_0F73_REG_3,
 897   MOD_VEX_0F73_REG_6,
 898   MOD_VEX_0F73_REG_7,
 899   MOD_VEX_W_0_0F91_P_0_LEN_0,
 900   MOD_VEX_W_1_0F91_P_0_LEN_0,
 901   MOD_VEX_W_0_0F91_P_2_LEN_0,
 902   MOD_VEX_W_1_0F91_P_2_LEN_0,
 903   MOD_VEX_W_0_0F92_P_0_LEN_0,
 904   MOD_VEX_W_0_0F92_P_2_LEN_0,
 905   MOD_VEX_0F92_P_3_LEN_0,
 906   MOD_VEX_W_0_0F93_P_0_LEN_0,
 907   MOD_VEX_W_0_0F93_P_2_LEN_0,
 908   MOD_VEX_0F93_P_3_LEN_0,
 909   MOD_VEX_W_0_0F98_P_0_LEN_0,
 910   MOD_VEX_W_1_0F98_P_0_LEN_0,
 911   MOD_VEX_W_0_0F98_P_2_LEN_0,
 912   MOD_VEX_W_1_0F98_P_2_LEN_0,
 913   MOD_VEX_W_0_0F99_P_0_LEN_0,
 914   MOD_VEX_W_1_0F99_P_0_LEN_0,
 915   MOD_VEX_W_0_0F99_P_2_LEN_0,
 916   MOD_VEX_W_1_0F99_P_2_LEN_0,
 917   MOD_VEX_0FAE_REG_2,
 918   MOD_VEX_0FAE_REG_3,
 919   MOD_VEX_0FD7_PREFIX_2,
 920   MOD_VEX_0FE7_PREFIX_2,
 921   MOD_VEX_0FF0_PREFIX_3,
 922   MOD_VEX_0F381A_PREFIX_2,
 923   MOD_VEX_0F382A_PREFIX_2,
 924   MOD_VEX_0F382C_PREFIX_2,
 925   MOD_VEX_0F382D_PREFIX_2,
 926   MOD_VEX_0F382E_PREFIX_2,
 927   MOD_VEX_0F382F_PREFIX_2,
 928   MOD_VEX_0F385A_PREFIX_2,
 929   MOD_VEX_0F388C_PREFIX_2,
 930   MOD_VEX_0F388E_PREFIX_2,
 931   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 933   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 934   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 935   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 936   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 937   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 938   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 939
 940   MOD_EVEX_0F10_PREFIX_1,
 941   MOD_EVEX_0F10_PREFIX_3,
 942   MOD_EVEX_0F11_PREFIX_1,
 943   MOD_EVEX_0F11_PREFIX_3,
 944   MOD_EVEX_0F12_PREFIX_0,
 945   MOD_EVEX_0F16_PREFIX_0,
 946   MOD_EVEX_0F38C6_REG_1,
 947   MOD_EVEX_0F38C6_REG_2,
 948   MOD_EVEX_0F38C6_REG_5,
 949   MOD_EVEX_0F38C6_REG_6,
 950   MOD_EVEX_0F38C7_REG_1,
 951   MOD_EVEX_0F38C7_REG_2,
 952   MOD_EVEX_0F38C7_REG_5,
 953   MOD_EVEX_0F38C7_REG_6
 954 };
 955
 956 enum
 957 {
 958   RM_C6_REG_7 = 0,
 959   RM_C7_REG_7,
 960   RM_0F01_REG_0,
 961   RM_0F01_REG_1,
 962   RM_0F01_REG_2,
 963   RM_0F01_REG_3,
 964   RM_0F01_REG_5,
 965   RM_0F01_REG_7,
 966   RM_0F1E_MOD_3_REG_7,
 967   RM_0FAE_REG_6,
 968   RM_0FAE_REG_7
 969 };
 970
 971 enum
 972 {
 973   PREFIX_90 = 0,
 974   PREFIX_MOD_0_0F01_REG_5,
 975   PREFIX_MOD_3_0F01_REG_5_RM_0,
 976   PREFIX_MOD_3_0F01_REG_5_RM_2,
 977   PREFIX_0F09,
 978   PREFIX_0F10,
 979   PREFIX_0F11,
 980   PREFIX_0F12,
 981   PREFIX_0F16,
 982   PREFIX_0F1A,
 983   PREFIX_0F1B,
 984   PREFIX_0F1C,
 985   PREFIX_0F1E,
 986   PREFIX_0F2A,
 987   PREFIX_0F2B,
 988   PREFIX_0F2C,
 989   PREFIX_0F2D,
 990   PREFIX_0F2E,
 991   PREFIX_0F2F,
 992   PREFIX_0F51,
 993   PREFIX_0F52,
 994   PREFIX_0F53,
 995   PREFIX_0F58,
 996   PREFIX_0F59,
 997   PREFIX_0F5A,
 998   PREFIX_0F5B,
 999   PREFIX_0F5C,
1000   PREFIX_0F5D,
1001   PREFIX_0F5E,
1002   PREFIX_0F5F,
1003   PREFIX_0F60,
1004   PREFIX_0F61,
1005   PREFIX_0F62,
1006   PREFIX_0F6C,
1007   PREFIX_0F6D,
1008   PREFIX_0F6F,
1009   PREFIX_0F70,
1010   PREFIX_0F73_REG_3,
1011   PREFIX_0F73_REG_7,
1012   PREFIX_0F78,
1013   PREFIX_0F79,
1014   PREFIX_0F7C,
1015   PREFIX_0F7D,
1016   PREFIX_0F7E,
1017   PREFIX_0F7F,
1018   PREFIX_0FAE_REG_0,
1019   PREFIX_0FAE_REG_1,
1020   PREFIX_0FAE_REG_2,
1021   PREFIX_0FAE_REG_3,
1022   PREFIX_MOD_0_0FAE_REG_4,
1023   PREFIX_MOD_3_0FAE_REG_4,
1024   PREFIX_MOD_0_0FAE_REG_5,
1025   PREFIX_MOD_3_0FAE_REG_5,
1026   PREFIX_MOD_0_0FAE_REG_6,
1027   PREFIX_MOD_1_0FAE_REG_6,
1028   PREFIX_0FAE_REG_7,
1029   PREFIX_0FB8,
1030   PREFIX_0FBC,
1031   PREFIX_0FBD,
1032   PREFIX_0FC2,
1033   PREFIX_MOD_0_0FC3,
1034   PREFIX_MOD_0_0FC7_REG_6,
1035   PREFIX_MOD_3_0FC7_REG_6,
1036   PREFIX_MOD_3_0FC7_REG_7,
1037   PREFIX_0FD0,
1038   PREFIX_0FD6,
1039   PREFIX_0FE6,
1040   PREFIX_0FE7,
1041   PREFIX_0FF0,
1042   PREFIX_0FF7,
1043   PREFIX_0F3810,
1044   PREFIX_0F3814,
1045   PREFIX_0F3815,
1046   PREFIX_0F3817,
1047   PREFIX_0F3820,
1048   PREFIX_0F3821,
1049   PREFIX_0F3822,
1050   PREFIX_0F3823,
1051   PREFIX_0F3824,
1052   PREFIX_0F3825,
1053   PREFIX_0F3828,
1054   PREFIX_0F3829,
1055   PREFIX_0F382A,
1056   PREFIX_0F382B,
1057   PREFIX_0F3830,
1058   PREFIX_0F3831,
1059   PREFIX_0F3832,
1060   PREFIX_0F3833,
1061   PREFIX_0F3834,
1062   PREFIX_0F3835,
1063   PREFIX_0F3837,
1064   PREFIX_0F3838,
1065   PREFIX_0F3839,
1066   PREFIX_0F383A,
1067   PREFIX_0F383B,
1068   PREFIX_0F383C,
1069   PREFIX_0F383D,
1070   PREFIX_0F383E,
1071   PREFIX_0F383F,
1072   PREFIX_0F3840,
1073   PREFIX_0F3841,
1074   PREFIX_0F3880,
1075   PREFIX_0F3881,
1076   PREFIX_0F3882,
1077   PREFIX_0F38C8,
1078   PREFIX_0F38C9,
1079   PREFIX_0F38CA,
1080   PREFIX_0F38CB,
1081   PREFIX_0F38CC,
1082   PREFIX_0F38CD,
1083   PREFIX_0F38CF,
1084   PREFIX_0F38DB,
1085   PREFIX_0F38DC,
1086   PREFIX_0F38DD,
1087   PREFIX_0F38DE,
1088   PREFIX_0F38DF,
1089   PREFIX_0F38F0,
1090   PREFIX_0F38F1,
1091   PREFIX_0F38F5,
1092   PREFIX_0F38F6,
1093   PREFIX_0F38F8,
1094   PREFIX_0F38F9,
1095   PREFIX_0F3A08,
1096   PREFIX_0F3A09,
1097   PREFIX_0F3A0A,
1098   PREFIX_0F3A0B,
1099   PREFIX_0F3A0C,
1100   PREFIX_0F3A0D,
1101   PREFIX_0F3A0E,
1102   PREFIX_0F3A14,
1103   PREFIX_0F3A15,
1104   PREFIX_0F3A16,
1105   PREFIX_0F3A17,
1106   PREFIX_0F3A20,
1107   PREFIX_0F3A21,
1108   PREFIX_0F3A22,
1109   PREFIX_0F3A40,
1110   PREFIX_0F3A41,
1111   PREFIX_0F3A42,
1112   PREFIX_0F3A44,
1113   PREFIX_0F3A60,
1114   PREFIX_0F3A61,
1115   PREFIX_0F3A62,
1116   PREFIX_0F3A63,
1117   PREFIX_0F3ACC,
1118   PREFIX_0F3ACE,
1119   PREFIX_0F3ACF,
1120   PREFIX_0F3ADF,
1121   PREFIX_VEX_0F10,
1122   PREFIX_VEX_0F11,
1123   PREFIX_VEX_0F12,
1124   PREFIX_VEX_0F16,
1125   PREFIX_VEX_0F2A,
1126   PREFIX_VEX_0F2C,
1127   PREFIX_VEX_0F2D,
1128   PREFIX_VEX_0F2E,
1129   PREFIX_VEX_0F2F,
1130   PREFIX_VEX_0F41,
1131   PREFIX_VEX_0F42,
1132   PREFIX_VEX_0F44,
1133   PREFIX_VEX_0F45,
1134   PREFIX_VEX_0F46,
1135   PREFIX_VEX_0F47,
1136   PREFIX_VEX_0F4A,
1137   PREFIX_VEX_0F4B,
1138   PREFIX_VEX_0F51,
1139   PREFIX_VEX_0F52,
1140   PREFIX_VEX_0F53,
1141   PREFIX_VEX_0F58,
1142   PREFIX_VEX_0F59,
1143   PREFIX_VEX_0F5A,
1144   PREFIX_VEX_0F5B,
1145   PREFIX_VEX_0F5C,
1146   PREFIX_VEX_0F5D,
1147   PREFIX_VEX_0F5E,
1148   PREFIX_VEX_0F5F,
1149   PREFIX_VEX_0F60,
1150   PREFIX_VEX_0F61,
1151   PREFIX_VEX_0F62,
1152   PREFIX_VEX_0F63,
1153   PREFIX_VEX_0F64,
1154   PREFIX_VEX_0F65,
1155   PREFIX_VEX_0F66,
1156   PREFIX_VEX_0F67,
1157   PREFIX_VEX_0F68,
1158   PREFIX_VEX_0F69,
1159   PREFIX_VEX_0F6A,
1160   PREFIX_VEX_0F6B,
1161   PREFIX_VEX_0F6C,
1162   PREFIX_VEX_0F6D,
1163   PREFIX_VEX_0F6E,
1164   PREFIX_VEX_0F6F,
1165   PREFIX_VEX_0F70,
1166   PREFIX_VEX_0F71_REG_2,
1167   PREFIX_VEX_0F71_REG_4,
1168   PREFIX_VEX_0F71_REG_6,
1169   PREFIX_VEX_0F72_REG_2,
1170   PREFIX_VEX_0F72_REG_4,
1171   PREFIX_VEX_0F72_REG_6,
1172   PREFIX_VEX_0F73_REG_2,
1173   PREFIX_VEX_0F73_REG_3,
1174   PREFIX_VEX_0F73_REG_6,
1175   PREFIX_VEX_0F73_REG_7,
1176   PREFIX_VEX_0F74,
1177   PREFIX_VEX_0F75,
1178   PREFIX_VEX_0F76,
1179   PREFIX_VEX_0F77,
1180   PREFIX_VEX_0F7C,
1181   PREFIX_VEX_0F7D,
1182   PREFIX_VEX_0F7E,
1183   PREFIX_VEX_0F7F,
1184   PREFIX_VEX_0F90,
1185   PREFIX_VEX_0F91,
1186   PREFIX_VEX_0F92,
1187   PREFIX_VEX_0F93,
1188   PREFIX_VEX_0F98,
1189   PREFIX_VEX_0F99,
1190   PREFIX_VEX_0FC2,
1191   PREFIX_VEX_0FC4,
1192   PREFIX_VEX_0FC5,
1193   PREFIX_VEX_0FD0,
1194   PREFIX_VEX_0FD1,
1195   PREFIX_VEX_0FD2,
1196   PREFIX_VEX_0FD3,
1197   PREFIX_VEX_0FD4,
1198   PREFIX_VEX_0FD5,
1199   PREFIX_VEX_0FD6,
1200   PREFIX_VEX_0FD7,
1201   PREFIX_VEX_0FD8,
1202   PREFIX_VEX_0FD9,
1203   PREFIX_VEX_0FDA,
1204   PREFIX_VEX_0FDB,
1205   PREFIX_VEX_0FDC,
1206   PREFIX_VEX_0FDD,
1207   PREFIX_VEX_0FDE,
1208   PREFIX_VEX_0FDF,
1209   PREFIX_VEX_0FE0,
1210   PREFIX_VEX_0FE1,
1211   PREFIX_VEX_0FE2,
1212   PREFIX_VEX_0FE3,
1213   PREFIX_VEX_0FE4,
1214   PREFIX_VEX_0FE5,
1215   PREFIX_VEX_0FE6,
1216   PREFIX_VEX_0FE7,
1217   PREFIX_VEX_0FE8,
1218   PREFIX_VEX_0FE9,
1219   PREFIX_VEX_0FEA,
1220   PREFIX_VEX_0FEB,
1221   PREFIX_VEX_0FEC,
1222   PREFIX_VEX_0FED,
1223   PREFIX_VEX_0FEE,
1224   PREFIX_VEX_0FEF,
1225   PREFIX_VEX_0FF0,
1226   PREFIX_VEX_0FF1,
1227   PREFIX_VEX_0FF2,
1228   PREFIX_VEX_0FF3,
1229   PREFIX_VEX_0FF4,
1230   PREFIX_VEX_0FF5,
1231   PREFIX_VEX_0FF6,
1232   PREFIX_VEX_0FF7,
1233   PREFIX_VEX_0FF8,
1234   PREFIX_VEX_0FF9,
1235   PREFIX_VEX_0FFA,
1236   PREFIX_VEX_0FFB,
1237   PREFIX_VEX_0FFC,
1238   PREFIX_VEX_0FFD,
1239   PREFIX_VEX_0FFE,
1240   PREFIX_VEX_0F3800,
1241   PREFIX_VEX_0F3801,
1242   PREFIX_VEX_0F3802,
1243   PREFIX_VEX_0F3803,
1244   PREFIX_VEX_0F3804,
1245   PREFIX_VEX_0F3805,
1246   PREFIX_VEX_0F3806,
1247   PREFIX_VEX_0F3807,
1248   PREFIX_VEX_0F3808,
1249   PREFIX_VEX_0F3809,
1250   PREFIX_VEX_0F380A,
1251   PREFIX_VEX_0F380B,
1252   PREFIX_VEX_0F380C,
1253   PREFIX_VEX_0F380D,
1254   PREFIX_VEX_0F380E,
1255   PREFIX_VEX_0F380F,
1256   PREFIX_VEX_0F3813,
1257   PREFIX_VEX_0F3816,
1258   PREFIX_VEX_0F3817,
1259   PREFIX_VEX_0F3818,
1260   PREFIX_VEX_0F3819,
1261   PREFIX_VEX_0F381A,
1262   PREFIX_VEX_0F381C,
1263   PREFIX_VEX_0F381D,
1264   PREFIX_VEX_0F381E,
1265   PREFIX_VEX_0F3820,
1266   PREFIX_VEX_0F3821,
1267   PREFIX_VEX_0F3822,
1268   PREFIX_VEX_0F3823,
1269   PREFIX_VEX_0F3824,
1270   PREFIX_VEX_0F3825,
1271   PREFIX_VEX_0F3828,
1272   PREFIX_VEX_0F3829,
1273   PREFIX_VEX_0F382A,
1274   PREFIX_VEX_0F382B,
1275   PREFIX_VEX_0F382C,
1276   PREFIX_VEX_0F382D,
1277   PREFIX_VEX_0F382E,
1278   PREFIX_VEX_0F382F,
1279   PREFIX_VEX_0F3830,
1280   PREFIX_VEX_0F3831,
1281   PREFIX_VEX_0F3832,
1282   PREFIX_VEX_0F3833,
1283   PREFIX_VEX_0F3834,
1284   PREFIX_VEX_0F3835,
1285   PREFIX_VEX_0F3836,
1286   PREFIX_VEX_0F3837,
1287   PREFIX_VEX_0F3838,
1288   PREFIX_VEX_0F3839,
1289   PREFIX_VEX_0F383A,
1290   PREFIX_VEX_0F383B,
1291   PREFIX_VEX_0F383C,
1292   PREFIX_VEX_0F383D,
1293   PREFIX_VEX_0F383E,
1294   PREFIX_VEX_0F383F,
1295   PREFIX_VEX_0F3840,
1296   PREFIX_VEX_0F3841,
1297   PREFIX_VEX_0F3845,
1298   PREFIX_VEX_0F3846,
1299   PREFIX_VEX_0F3847,
1300   PREFIX_VEX_0F3858,
1301   PREFIX_VEX_0F3859,
1302   PREFIX_VEX_0F385A,
1303   PREFIX_VEX_0F3878,
1304   PREFIX_VEX_0F3879,
1305   PREFIX_VEX_0F388C,
1306   PREFIX_VEX_0F388E,
1307   PREFIX_VEX_0F3890,
1308   PREFIX_VEX_0F3891,
1309   PREFIX_VEX_0F3892,
1310   PREFIX_VEX_0F3893,
1311   PREFIX_VEX_0F3896,
1312   PREFIX_VEX_0F3897,
1313   PREFIX_VEX_0F3898,
1314   PREFIX_VEX_0F3899,
1315   PREFIX_VEX_0F389A,
1316   PREFIX_VEX_0F389B,
1317   PREFIX_VEX_0F389C,
1318   PREFIX_VEX_0F389D,
1319   PREFIX_VEX_0F389E,
1320   PREFIX_VEX_0F389F,
1321   PREFIX_VEX_0F38A6,
1322   PREFIX_VEX_0F38A7,
1323   PREFIX_VEX_0F38A8,
1324   PREFIX_VEX_0F38A9,
1325   PREFIX_VEX_0F38AA,
1326   PREFIX_VEX_0F38AB,
1327   PREFIX_VEX_0F38AC,
1328   PREFIX_VEX_0F38AD,
1329   PREFIX_VEX_0F38AE,
1330   PREFIX_VEX_0F38AF,
1331   PREFIX_VEX_0F38B6,
1332   PREFIX_VEX_0F38B7,
1333   PREFIX_VEX_0F38B8,
1334   PREFIX_VEX_0F38B9,
1335   PREFIX_VEX_0F38BA,
1336   PREFIX_VEX_0F38BB,
1337   PREFIX_VEX_0F38BC,
1338   PREFIX_VEX_0F38BD,
1339   PREFIX_VEX_0F38BE,
1340   PREFIX_VEX_0F38BF,
1341   PREFIX_VEX_0F38CF,
1342   PREFIX_VEX_0F38DB,
1343   PREFIX_VEX_0F38DC,
1344   PREFIX_VEX_0F38DD,
1345   PREFIX_VEX_0F38DE,
1346   PREFIX_VEX_0F38DF,
1347   PREFIX_VEX_0F38F2,
1348   PREFIX_VEX_0F38F3_REG_1,
1349   PREFIX_VEX_0F38F3_REG_2,
1350   PREFIX_VEX_0F38F3_REG_3,
1351   PREFIX_VEX_0F38F5,
1352   PREFIX_VEX_0F38F6,
1353   PREFIX_VEX_0F38F7,
1354   PREFIX_VEX_0F3A00,
1355   PREFIX_VEX_0F3A01,
1356   PREFIX_VEX_0F3A02,
1357   PREFIX_VEX_0F3A04,
1358   PREFIX_VEX_0F3A05,
1359   PREFIX_VEX_0F3A06,
1360   PREFIX_VEX_0F3A08,
1361   PREFIX_VEX_0F3A09,
1362   PREFIX_VEX_0F3A0A,
1363   PREFIX_VEX_0F3A0B,
1364   PREFIX_VEX_0F3A0C,
1365   PREFIX_VEX_0F3A0D,
1366   PREFIX_VEX_0F3A0E,
1367   PREFIX_VEX_0F3A0F,
1368   PREFIX_VEX_0F3A14,
1369   PREFIX_VEX_0F3A15,
1370   PREFIX_VEX_0F3A16,
1371   PREFIX_VEX_0F3A17,
1372   PREFIX_VEX_0F3A18,
1373   PREFIX_VEX_0F3A19,
1374   PREFIX_VEX_0F3A1D,
1375   PREFIX_VEX_0F3A20,
1376   PREFIX_VEX_0F3A21,
1377   PREFIX_VEX_0F3A22,
1378   PREFIX_VEX_0F3A30,
1379   PREFIX_VEX_0F3A31,
1380   PREFIX_VEX_0F3A32,
1381   PREFIX_VEX_0F3A33,
1382   PREFIX_VEX_0F3A38,
1383   PREFIX_VEX_0F3A39,
1384   PREFIX_VEX_0F3A40,
1385   PREFIX_VEX_0F3A41,
1386   PREFIX_VEX_0F3A42,
1387   PREFIX_VEX_0F3A44,
1388   PREFIX_VEX_0F3A46,
1389   PREFIX_VEX_0F3A48,
1390   PREFIX_VEX_0F3A49,
1391   PREFIX_VEX_0F3A4A,
1392   PREFIX_VEX_0F3A4B,
1393   PREFIX_VEX_0F3A4C,
1394   PREFIX_VEX_0F3A5C,
1395   PREFIX_VEX_0F3A5D,
1396   PREFIX_VEX_0F3A5E,
1397   PREFIX_VEX_0F3A5F,
1398   PREFIX_VEX_0F3A60,
1399   PREFIX_VEX_0F3A61,
1400   PREFIX_VEX_0F3A62,
1401   PREFIX_VEX_0F3A63,
1402   PREFIX_VEX_0F3A68,
1403   PREFIX_VEX_0F3A69,
1404   PREFIX_VEX_0F3A6A,
1405   PREFIX_VEX_0F3A6B,
1406   PREFIX_VEX_0F3A6C,
1407   PREFIX_VEX_0F3A6D,
1408   PREFIX_VEX_0F3A6E,
1409   PREFIX_VEX_0F3A6F,
1410   PREFIX_VEX_0F3A78,
1411   PREFIX_VEX_0F3A79,
1412   PREFIX_VEX_0F3A7A,
1413   PREFIX_VEX_0F3A7B,
1414   PREFIX_VEX_0F3A7C,
1415   PREFIX_VEX_0F3A7D,
1416   PREFIX_VEX_0F3A7E,
1417   PREFIX_VEX_0F3A7F,
1418   PREFIX_VEX_0F3ACE,
1419   PREFIX_VEX_0F3ACF,
1420   PREFIX_VEX_0F3ADF,
1421   PREFIX_VEX_0F3AF0,
1422
1423   PREFIX_EVEX_0F10,
1424   PREFIX_EVEX_0F11,
1425   PREFIX_EVEX_0F12,
1426   PREFIX_EVEX_0F13,
1427   PREFIX_EVEX_0F14,
1428   PREFIX_EVEX_0F15,
1429   PREFIX_EVEX_0F16,
1430   PREFIX_EVEX_0F17,
1431   PREFIX_EVEX_0F28,
1432   PREFIX_EVEX_0F29,
1433   PREFIX_EVEX_0F2A,
1434   PREFIX_EVEX_0F2B,
1435   PREFIX_EVEX_0F2C,
1436   PREFIX_EVEX_0F2D,
1437   PREFIX_EVEX_0F2E,
1438   PREFIX_EVEX_0F2F,
1439   PREFIX_EVEX_0F51,
1440   PREFIX_EVEX_0F54,
1441   PREFIX_EVEX_0F55,
1442   PREFIX_EVEX_0F56,
1443   PREFIX_EVEX_0F57,
1444   PREFIX_EVEX_0F58,
1445   PREFIX_EVEX_0F59,
1446   PREFIX_EVEX_0F5A,
1447   PREFIX_EVEX_0F5B,
1448   PREFIX_EVEX_0F5C,
1449   PREFIX_EVEX_0F5D,
1450   PREFIX_EVEX_0F5E,
1451   PREFIX_EVEX_0F5F,
1452   PREFIX_EVEX_0F60,
1453   PREFIX_EVEX_0F61,
1454   PREFIX_EVEX_0F62,
1455   PREFIX_EVEX_0F63,
1456   PREFIX_EVEX_0F64,
1457   PREFIX_EVEX_0F65,
1458   PREFIX_EVEX_0F66,
1459   PREFIX_EVEX_0F67,
1460   PREFIX_EVEX_0F68,
1461   PREFIX_EVEX_0F69,
1462   PREFIX_EVEX_0F6A,
1463   PREFIX_EVEX_0F6B,
1464   PREFIX_EVEX_0F6C,
1465   PREFIX_EVEX_0F6D,
1466   PREFIX_EVEX_0F6E,
1467   PREFIX_EVEX_0F6F,
1468   PREFIX_EVEX_0F70,
1469   PREFIX_EVEX_0F71_REG_2,
1470   PREFIX_EVEX_0F71_REG_4,
1471   PREFIX_EVEX_0F71_REG_6,
1472   PREFIX_EVEX_0F72_REG_0,
1473   PREFIX_EVEX_0F72_REG_1,
1474   PREFIX_EVEX_0F72_REG_2,
1475   PREFIX_EVEX_0F72_REG_4,
1476   PREFIX_EVEX_0F72_REG_6,
1477   PREFIX_EVEX_0F73_REG_2,
1478   PREFIX_EVEX_0F73_REG_3,
1479   PREFIX_EVEX_0F73_REG_6,
1480   PREFIX_EVEX_0F73_REG_7,
1481   PREFIX_EVEX_0F74,
1482   PREFIX_EVEX_0F75,
1483   PREFIX_EVEX_0F76,
1484   PREFIX_EVEX_0F78,
1485   PREFIX_EVEX_0F79,
1486   PREFIX_EVEX_0F7A,
1487   PREFIX_EVEX_0F7B,
1488   PREFIX_EVEX_0F7E,
1489   PREFIX_EVEX_0F7F,
1490   PREFIX_EVEX_0FC2,
1491   PREFIX_EVEX_0FC4,
1492   PREFIX_EVEX_0FC5,
1493   PREFIX_EVEX_0FC6,
1494   PREFIX_EVEX_0FD1,
1495   PREFIX_EVEX_0FD2,
1496   PREFIX_EVEX_0FD3,
1497   PREFIX_EVEX_0FD4,
1498   PREFIX_EVEX_0FD5,
1499   PREFIX_EVEX_0FD6,
1500   PREFIX_EVEX_0FD8,
1501   PREFIX_EVEX_0FD9,
1502   PREFIX_EVEX_0FDA,
1503   PREFIX_EVEX_0FDB,
1504   PREFIX_EVEX_0FDC,
1505   PREFIX_EVEX_0FDD,
1506   PREFIX_EVEX_0FDE,
1507   PREFIX_EVEX_0FDF,
1508   PREFIX_EVEX_0FE0,
1509   PREFIX_EVEX_0FE1,
1510   PREFIX_EVEX_0FE2,
1511   PREFIX_EVEX_0FE3,
1512   PREFIX_EVEX_0FE4,
1513   PREFIX_EVEX_0FE5,
1514   PREFIX_EVEX_0FE6,
1515   PREFIX_EVEX_0FE7,
1516   PREFIX_EVEX_0FE8,
1517   PREFIX_EVEX_0FE9,
1518   PREFIX_EVEX_0FEA,
1519   PREFIX_EVEX_0FEB,
1520   PREFIX_EVEX_0FEC,
1521   PREFIX_EVEX_0FED,
1522   PREFIX_EVEX_0FEE,
1523   PREFIX_EVEX_0FEF,
1524   PREFIX_EVEX_0FF1,
1525   PREFIX_EVEX_0FF2,
1526   PREFIX_EVEX_0FF3,
1527   PREFIX_EVEX_0FF4,
1528   PREFIX_EVEX_0FF5,
1529   PREFIX_EVEX_0FF6,
1530   PREFIX_EVEX_0FF8,
1531   PREFIX_EVEX_0FF9,
1532   PREFIX_EVEX_0FFA,
1533   PREFIX_EVEX_0FFB,
1534   PREFIX_EVEX_0FFC,
1535   PREFIX_EVEX_0FFD,
1536   PREFIX_EVEX_0FFE,
1537   PREFIX_EVEX_0F3800,
1538   PREFIX_EVEX_0F3804,
1539   PREFIX_EVEX_0F380B,
1540   PREFIX_EVEX_0F380C,
1541   PREFIX_EVEX_0F380D,
1542   PREFIX_EVEX_0F3810,
1543   PREFIX_EVEX_0F3811,
1544   PREFIX_EVEX_0F3812,
1545   PREFIX_EVEX_0F3813,
1546   PREFIX_EVEX_0F3814,
1547   PREFIX_EVEX_0F3815,
1548   PREFIX_EVEX_0F3816,
1549   PREFIX_EVEX_0F3818,
1550   PREFIX_EVEX_0F3819,
1551   PREFIX_EVEX_0F381A,
1552   PREFIX_EVEX_0F381B,
1553   PREFIX_EVEX_0F381C,
1554   PREFIX_EVEX_0F381D,
1555   PREFIX_EVEX_0F381E,
1556   PREFIX_EVEX_0F381F,
1557   PREFIX_EVEX_0F3820,
1558   PREFIX_EVEX_0F3821,
1559   PREFIX_EVEX_0F3822,
1560   PREFIX_EVEX_0F3823,
1561   PREFIX_EVEX_0F3824,
1562   PREFIX_EVEX_0F3825,
1563   PREFIX_EVEX_0F3826,
1564   PREFIX_EVEX_0F3827,
1565   PREFIX_EVEX_0F3828,
1566   PREFIX_EVEX_0F3829,
1567   PREFIX_EVEX_0F382A,
1568   PREFIX_EVEX_0F382B,
1569   PREFIX_EVEX_0F382C,
1570   PREFIX_EVEX_0F382D,
1571   PREFIX_EVEX_0F3830,
1572   PREFIX_EVEX_0F3831,
1573   PREFIX_EVEX_0F3832,
1574   PREFIX_EVEX_0F3833,
1575   PREFIX_EVEX_0F3834,
1576   PREFIX_EVEX_0F3835,
1577   PREFIX_EVEX_0F3836,
1578   PREFIX_EVEX_0F3837,
1579   PREFIX_EVEX_0F3838,
1580   PREFIX_EVEX_0F3839,
1581   PREFIX_EVEX_0F383A,
1582   PREFIX_EVEX_0F383B,
1583   PREFIX_EVEX_0F383C,
1584   PREFIX_EVEX_0F383D,
1585   PREFIX_EVEX_0F383E,
1586   PREFIX_EVEX_0F383F,
1587   PREFIX_EVEX_0F3840,
1588   PREFIX_EVEX_0F3842,
1589   PREFIX_EVEX_0F3843,
1590   PREFIX_EVEX_0F3844,
1591   PREFIX_EVEX_0F3845,
1592   PREFIX_EVEX_0F3846,
1593   PREFIX_EVEX_0F3847,
1594   PREFIX_EVEX_0F384C,
1595   PREFIX_EVEX_0F384D,
1596   PREFIX_EVEX_0F384E,
1597   PREFIX_EVEX_0F384F,
1598   PREFIX_EVEX_0F3850,
1599   PREFIX_EVEX_0F3851,
1600   PREFIX_EVEX_0F3852,
1601   PREFIX_EVEX_0F3853,
1602   PREFIX_EVEX_0F3854,
1603   PREFIX_EVEX_0F3855,
1604   PREFIX_EVEX_0F3858,
1605   PREFIX_EVEX_0F3859,
1606   PREFIX_EVEX_0F385A,
1607   PREFIX_EVEX_0F385B,
1608   PREFIX_EVEX_0F3862,
1609   PREFIX_EVEX_0F3863,
1610   PREFIX_EVEX_0F3864,
1611   PREFIX_EVEX_0F3865,
1612   PREFIX_EVEX_0F3866,
1613   PREFIX_EVEX_0F3868,
1614   PREFIX_EVEX_0F3870,
1615   PREFIX_EVEX_0F3871,
1616   PREFIX_EVEX_0F3872,
1617   PREFIX_EVEX_0F3873,
1618   PREFIX_EVEX_0F3875,
1619   PREFIX_EVEX_0F3876,
1620   PREFIX_EVEX_0F3877,
1621   PREFIX_EVEX_0F3878,
1622   PREFIX_EVEX_0F3879,
1623   PREFIX_EVEX_0F387A,
1624   PREFIX_EVEX_0F387B,
1625   PREFIX_EVEX_0F387C,
1626   PREFIX_EVEX_0F387D,
1627   PREFIX_EVEX_0F387E,
1628   PREFIX_EVEX_0F387F,
1629   PREFIX_EVEX_0F3883,
1630   PREFIX_EVEX_0F3888,
1631   PREFIX_EVEX_0F3889,
1632   PREFIX_EVEX_0F388A,
1633   PREFIX_EVEX_0F388B,
1634   PREFIX_EVEX_0F388D,
1635   PREFIX_EVEX_0F388F,
1636   PREFIX_EVEX_0F3890,
1637   PREFIX_EVEX_0F3891,
1638   PREFIX_EVEX_0F3892,
1639   PREFIX_EVEX_0F3893,
1640   PREFIX_EVEX_0F3896,
1641   PREFIX_EVEX_0F3897,
1642   PREFIX_EVEX_0F3898,
1643   PREFIX_EVEX_0F3899,
1644   PREFIX_EVEX_0F389A,
1645   PREFIX_EVEX_0F389B,
1646   PREFIX_EVEX_0F389C,
1647   PREFIX_EVEX_0F389D,
1648   PREFIX_EVEX_0F389E,
1649   PREFIX_EVEX_0F389F,
1650   PREFIX_EVEX_0F38A0,
1651   PREFIX_EVEX_0F38A1,
1652   PREFIX_EVEX_0F38A2,
1653   PREFIX_EVEX_0F38A3,
1654   PREFIX_EVEX_0F38A6,
1655   PREFIX_EVEX_0F38A7,
1656   PREFIX_EVEX_0F38A8,
1657   PREFIX_EVEX_0F38A9,
1658   PREFIX_EVEX_0F38AA,
1659   PREFIX_EVEX_0F38AB,
1660   PREFIX_EVEX_0F38AC,
1661   PREFIX_EVEX_0F38AD,
1662   PREFIX_EVEX_0F38AE,
1663   PREFIX_EVEX_0F38AF,
1664   PREFIX_EVEX_0F38B4,
1665   PREFIX_EVEX_0F38B5,
1666   PREFIX_EVEX_0F38B6,
1667   PREFIX_EVEX_0F38B7,
1668   PREFIX_EVEX_0F38B8,
1669   PREFIX_EVEX_0F38B9,
1670   PREFIX_EVEX_0F38BA,
1671   PREFIX_EVEX_0F38BB,
1672   PREFIX_EVEX_0F38BC,
1673   PREFIX_EVEX_0F38BD,
1674   PREFIX_EVEX_0F38BE,
1675   PREFIX_EVEX_0F38BF,
1676   PREFIX_EVEX_0F38C4,
1677   PREFIX_EVEX_0F38C6_REG_1,
1678   PREFIX_EVEX_0F38C6_REG_2,
1679   PREFIX_EVEX_0F38C6_REG_5,
1680   PREFIX_EVEX_0F38C6_REG_6,
1681   PREFIX_EVEX_0F38C7_REG_1,
1682   PREFIX_EVEX_0F38C7_REG_2,
1683   PREFIX_EVEX_0F38C7_REG_5,
1684   PREFIX_EVEX_0F38C7_REG_6,
1685   PREFIX_EVEX_0F38C8,
1686   PREFIX_EVEX_0F38CA,
1687   PREFIX_EVEX_0F38CB,
1688   PREFIX_EVEX_0F38CC,
1689   PREFIX_EVEX_0F38CD,
1690   PREFIX_EVEX_0F38CF,
1691   PREFIX_EVEX_0F38DC,
1692   PREFIX_EVEX_0F38DD,
1693   PREFIX_EVEX_0F38DE,
1694   PREFIX_EVEX_0F38DF,
1695
1696   PREFIX_EVEX_0F3A00,
1697   PREFIX_EVEX_0F3A01,
1698   PREFIX_EVEX_0F3A03,
1699   PREFIX_EVEX_0F3A04,
1700   PREFIX_EVEX_0F3A05,
1701   PREFIX_EVEX_0F3A08,
1702   PREFIX_EVEX_0F3A09,
1703   PREFIX_EVEX_0F3A0A,
1704   PREFIX_EVEX_0F3A0B,
1705   PREFIX_EVEX_0F3A0F,
1706   PREFIX_EVEX_0F3A14,
1707   PREFIX_EVEX_0F3A15,
1708   PREFIX_EVEX_0F3A16,
1709   PREFIX_EVEX_0F3A17,
1710   PREFIX_EVEX_0F3A18,
1711   PREFIX_EVEX_0F3A19,
1712   PREFIX_EVEX_0F3A1A,
1713   PREFIX_EVEX_0F3A1B,
1714   PREFIX_EVEX_0F3A1D,
1715   PREFIX_EVEX_0F3A1E,
1716   PREFIX_EVEX_0F3A1F,
1717   PREFIX_EVEX_0F3A20,
1718   PREFIX_EVEX_0F3A21,
1719   PREFIX_EVEX_0F3A22,
1720   PREFIX_EVEX_0F3A23,
1721   PREFIX_EVEX_0F3A25,
1722   PREFIX_EVEX_0F3A26,
1723   PREFIX_EVEX_0F3A27,
1724   PREFIX_EVEX_0F3A38,
1725   PREFIX_EVEX_0F3A39,
1726   PREFIX_EVEX_0F3A3A,
1727   PREFIX_EVEX_0F3A3B,
1728   PREFIX_EVEX_0F3A3E,
1729   PREFIX_EVEX_0F3A3F,
1730   PREFIX_EVEX_0F3A42,
1731   PREFIX_EVEX_0F3A43,
1732   PREFIX_EVEX_0F3A44,
1733   PREFIX_EVEX_0F3A50,
1734   PREFIX_EVEX_0F3A51,
1735   PREFIX_EVEX_0F3A54,
1736   PREFIX_EVEX_0F3A55,
1737   PREFIX_EVEX_0F3A56,
1738   PREFIX_EVEX_0F3A57,
1739   PREFIX_EVEX_0F3A66,
1740   PREFIX_EVEX_0F3A67,
1741   PREFIX_EVEX_0F3A70,
1742   PREFIX_EVEX_0F3A71,
1743   PREFIX_EVEX_0F3A72,
1744   PREFIX_EVEX_0F3A73,
1745   PREFIX_EVEX_0F3ACE,
1746   PREFIX_EVEX_0F3ACF
1747 };
1748
1749 enum
1750 {
1751   X86_64_06 = 0,
1752   X86_64_07,
1753   X86_64_0D,
1754   X86_64_16,
1755   X86_64_17,
1756   X86_64_1E,
1757   X86_64_1F,
1758   X86_64_27,
1759   X86_64_2F,
1760   X86_64_37,
1761   X86_64_3F,
1762   X86_64_60,
1763   X86_64_61,
1764   X86_64_62,
1765   X86_64_63,
1766   X86_64_6D,
1767   X86_64_6F,
1768   X86_64_82,
1769   X86_64_9A,
1770   X86_64_C4,
1771   X86_64_C5,
1772   X86_64_CE,
1773   X86_64_D4,
1774   X86_64_D5,
1775   X86_64_E8,
1776   X86_64_E9,
1777   X86_64_EA,
1778   X86_64_0F01_REG_0,
1779   X86_64_0F01_REG_1,
1780   X86_64_0F01_REG_2,
1781   X86_64_0F01_REG_3
1782 };
1783
1784 enum
1785 {
1786   THREE_BYTE_0F38 = 0,
1787   THREE_BYTE_0F3A
1788 };
1789
1790 enum
1791 {
1792   XOP_08 = 0,
1793   XOP_09,
1794   XOP_0A
1795 };
1796
1797 enum
1798 {
1799   VEX_0F = 0,
1800   VEX_0F38,
1801   VEX_0F3A
1802 };
1803
1804 enum
1805 {
1806   EVEX_0F = 0,
1807   EVEX_0F38,
1808   EVEX_0F3A
1809 };
1810
1811 enum
1812 {
1813   VEX_LEN_0F12_P_0_M_0 = 0,
1814   VEX_LEN_0F12_P_0_M_1,
1815   VEX_LEN_0F12_P_2,
1816   VEX_LEN_0F13_M_0,
1817   VEX_LEN_0F16_P_0_M_0,
1818   VEX_LEN_0F16_P_0_M_1,
1819   VEX_LEN_0F16_P_2,
1820   VEX_LEN_0F17_M_0,
1821   VEX_LEN_0F41_P_0,
1822   VEX_LEN_0F41_P_2,
1823   VEX_LEN_0F42_P_0,
1824   VEX_LEN_0F42_P_2,
1825   VEX_LEN_0F44_P_0,
1826   VEX_LEN_0F44_P_2,
1827   VEX_LEN_0F45_P_0,
1828   VEX_LEN_0F45_P_2,
1829   VEX_LEN_0F46_P_0,
1830   VEX_LEN_0F46_P_2,
1831   VEX_LEN_0F47_P_0,
1832   VEX_LEN_0F47_P_2,
1833   VEX_LEN_0F4A_P_0,
1834   VEX_LEN_0F4A_P_2,
1835   VEX_LEN_0F4B_P_0,
1836   VEX_LEN_0F4B_P_2,
1837   VEX_LEN_0F6E_P_2,
1838   VEX_LEN_0F77_P_0,
1839   VEX_LEN_0F7E_P_1,
1840   VEX_LEN_0F7E_P_2,
1841   VEX_LEN_0F90_P_0,
1842   VEX_LEN_0F90_P_2,
1843   VEX_LEN_0F91_P_0,
1844   VEX_LEN_0F91_P_2,
1845   VEX_LEN_0F92_P_0,
1846   VEX_LEN_0F92_P_2,
1847   VEX_LEN_0F92_P_3,
1848   VEX_LEN_0F93_P_0,
1849   VEX_LEN_0F93_P_2,
1850   VEX_LEN_0F93_P_3,
1851   VEX_LEN_0F98_P_0,
1852   VEX_LEN_0F98_P_2,
1853   VEX_LEN_0F99_P_0,
1854   VEX_LEN_0F99_P_2,
1855   VEX_LEN_0FAE_R_2_M_0,
1856   VEX_LEN_0FAE_R_3_M_0,
1857   VEX_LEN_0FC4_P_2,
1858   VEX_LEN_0FC5_P_2,
1859   VEX_LEN_0FD6_P_2,
1860   VEX_LEN_0FF7_P_2,
1861   VEX_LEN_0F3816_P_2,
1862   VEX_LEN_0F3819_P_2,
1863   VEX_LEN_0F381A_P_2_M_0,
1864   VEX_LEN_0F3836_P_2,
1865   VEX_LEN_0F3841_P_2,
1866   VEX_LEN_0F385A_P_2_M_0,
1867   VEX_LEN_0F38DB_P_2,
1868   VEX_LEN_0F38F2_P_0,
1869   VEX_LEN_0F38F3_R_1_P_0,
1870   VEX_LEN_0F38F3_R_2_P_0,
1871   VEX_LEN_0F38F3_R_3_P_0,
1872   VEX_LEN_0F38F5_P_0,
1873   VEX_LEN_0F38F5_P_1,
1874   VEX_LEN_0F38F5_P_3,
1875   VEX_LEN_0F38F6_P_3,
1876   VEX_LEN_0F38F7_P_0,
1877   VEX_LEN_0F38F7_P_1,
1878   VEX_LEN_0F38F7_P_2,
1879   VEX_LEN_0F38F7_P_3,
1880   VEX_LEN_0F3A00_P_2,
1881   VEX_LEN_0F3A01_P_2,
1882   VEX_LEN_0F3A06_P_2,
1883   VEX_LEN_0F3A14_P_2,
1884   VEX_LEN_0F3A15_P_2,
1885   VEX_LEN_0F3A16_P_2,
1886   VEX_LEN_0F3A17_P_2,
1887   VEX_LEN_0F3A18_P_2,
1888   VEX_LEN_0F3A19_P_2,
1889   VEX_LEN_0F3A20_P_2,
1890   VEX_LEN_0F3A21_P_2,
1891   VEX_LEN_0F3A22_P_2,
1892   VEX_LEN_0F3A30_P_2,
1893   VEX_LEN_0F3A31_P_2,
1894   VEX_LEN_0F3A32_P_2,
1895   VEX_LEN_0F3A33_P_2,
1896   VEX_LEN_0F3A38_P_2,
1897   VEX_LEN_0F3A39_P_2,
1898   VEX_LEN_0F3A41_P_2,
1899   VEX_LEN_0F3A46_P_2,
1900   VEX_LEN_0F3A60_P_2,
1901   VEX_LEN_0F3A61_P_2,
1902   VEX_LEN_0F3A62_P_2,
1903   VEX_LEN_0F3A63_P_2,
1904   VEX_LEN_0F3A6A_P_2,
1905   VEX_LEN_0F3A6B_P_2,
1906   VEX_LEN_0F3A6E_P_2,
1907   VEX_LEN_0F3A6F_P_2,
1908   VEX_LEN_0F3A7A_P_2,
1909   VEX_LEN_0F3A7B_P_2,
1910   VEX_LEN_0F3A7E_P_2,
1911   VEX_LEN_0F3A7F_P_2,
1912   VEX_LEN_0F3ADF_P_2,
1913   VEX_LEN_0F3AF0_P_3,
1914   VEX_LEN_0FXOP_08_CC,
1915   VEX_LEN_0FXOP_08_CD,
1916   VEX_LEN_0FXOP_08_CE,
1917   VEX_LEN_0FXOP_08_CF,
1918   VEX_LEN_0FXOP_08_EC,
1919   VEX_LEN_0FXOP_08_ED,
1920   VEX_LEN_0FXOP_08_EE,
1921   VEX_LEN_0FXOP_08_EF,
1922   VEX_LEN_0FXOP_09_80,
1923   VEX_LEN_0FXOP_09_81
1924 };
1925
1926 enum
1927 {
1928   EVEX_LEN_0F6E_P_2 = 0,
1929   EVEX_LEN_0F7E_P_1,
1930   EVEX_LEN_0F7E_P_2,
1931   EVEX_LEN_0FD6_P_2,
1932   EVEX_LEN_0F3819_P_2_W_0,
1933   EVEX_LEN_0F3819_P_2_W_1,
1934   EVEX_LEN_0F381A_P_2_W_0,
1935   EVEX_LEN_0F381A_P_2_W_1,
1936   EVEX_LEN_0F381B_P_2_W_0,
1937   EVEX_LEN_0F381B_P_2_W_1,
1938   EVEX_LEN_0F385A_P_2_W_0,
1939   EVEX_LEN_0F385A_P_2_W_1,
1940   EVEX_LEN_0F385B_P_2_W_0,
1941   EVEX_LEN_0F385B_P_2_W_1,
1942   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1943   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1944   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1945   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1946   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1947   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1948   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1949   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1950   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1951   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1952   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1953   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1954   EVEX_LEN_0F3A18_P_2_W_0,
1955   EVEX_LEN_0F3A18_P_2_W_1,
1956   EVEX_LEN_0F3A19_P_2_W_0,
1957   EVEX_LEN_0F3A19_P_2_W_1,
1958   EVEX_LEN_0F3A1A_P_2_W_0,
1959   EVEX_LEN_0F3A1A_P_2_W_1,
1960   EVEX_LEN_0F3A1B_P_2_W_0,
1961   EVEX_LEN_0F3A1B_P_2_W_1,
1962   EVEX_LEN_0F3A23_P_2_W_0,
1963   EVEX_LEN_0F3A23_P_2_W_1,
1964   EVEX_LEN_0F3A38_P_2_W_0,
1965   EVEX_LEN_0F3A38_P_2_W_1,
1966   EVEX_LEN_0F3A39_P_2_W_0,
1967   EVEX_LEN_0F3A39_P_2_W_1,
1968   EVEX_LEN_0F3A3A_P_2_W_0,
1969   EVEX_LEN_0F3A3A_P_2_W_1,
1970   EVEX_LEN_0F3A3B_P_2_W_0,
1971   EVEX_LEN_0F3A3B_P_2_W_1,
1972   EVEX_LEN_0F3A43_P_2_W_0,
1973   EVEX_LEN_0F3A43_P_2_W_1
1974 };
1975
1976 enum
1977 {
1978   VEX_W_0F41_P_0_LEN_1 = 0,
1979   VEX_W_0F41_P_2_LEN_1,
1980   VEX_W_0F42_P_0_LEN_1,
1981   VEX_W_0F42_P_2_LEN_1,
1982   VEX_W_0F44_P_0_LEN_0,
1983   VEX_W_0F44_P_2_LEN_0,
1984   VEX_W_0F45_P_0_LEN_1,
1985   VEX_W_0F45_P_2_LEN_1,
1986   VEX_W_0F46_P_0_LEN_1,
1987   VEX_W_0F46_P_2_LEN_1,
1988   VEX_W_0F47_P_0_LEN_1,
1989   VEX_W_0F47_P_2_LEN_1,
1990   VEX_W_0F4A_P_0_LEN_1,
1991   VEX_W_0F4A_P_2_LEN_1,
1992   VEX_W_0F4B_P_0_LEN_1,
1993   VEX_W_0F4B_P_2_LEN_1,
1994   VEX_W_0F90_P_0_LEN_0,
1995   VEX_W_0F90_P_2_LEN_0,
1996   VEX_W_0F91_P_0_LEN_0,
1997   VEX_W_0F91_P_2_LEN_0,
1998   VEX_W_0F92_P_0_LEN_0,
1999   VEX_W_0F92_P_2_LEN_0,
2000   VEX_W_0F93_P_0_LEN_0,
2001   VEX_W_0F93_P_2_LEN_0,
2002   VEX_W_0F98_P_0_LEN_0,
2003   VEX_W_0F98_P_2_LEN_0,
2004   VEX_W_0F99_P_0_LEN_0,
2005   VEX_W_0F99_P_2_LEN_0,
2006   VEX_W_0F380C_P_2,
2007   VEX_W_0F380D_P_2,
2008   VEX_W_0F380E_P_2,
2009   VEX_W_0F380F_P_2,
2010   VEX_W_0F3816_P_2,
2011   VEX_W_0F3818_P_2,
2012   VEX_W_0F3819_P_2,
2013   VEX_W_0F381A_P_2_M_0,
2014   VEX_W_0F382C_P_2_M_0,
2015   VEX_W_0F382D_P_2_M_0,
2016   VEX_W_0F382E_P_2_M_0,
2017   VEX_W_0F382F_P_2_M_0,
2018   VEX_W_0F3836_P_2,
2019   VEX_W_0F3846_P_2,
2020   VEX_W_0F3858_P_2,
2021   VEX_W_0F3859_P_2,
2022   VEX_W_0F385A_P_2_M_0,
2023   VEX_W_0F3878_P_2,
2024   VEX_W_0F3879_P_2,
2025   VEX_W_0F38CF_P_2,
2026   VEX_W_0F3A00_P_2,
2027   VEX_W_0F3A01_P_2,
2028   VEX_W_0F3A02_P_2,
2029   VEX_W_0F3A04_P_2,
2030   VEX_W_0F3A05_P_2,
2031   VEX_W_0F3A06_P_2,
2032   VEX_W_0F3A18_P_2,
2033   VEX_W_0F3A19_P_2,
2034   VEX_W_0F3A30_P_2_LEN_0,
2035   VEX_W_0F3A31_P_2_LEN_0,
2036   VEX_W_0F3A32_P_2_LEN_0,
2037   VEX_W_0F3A33_P_2_LEN_0,
2038   VEX_W_0F3A38_P_2,
2039   VEX_W_0F3A39_P_2,
2040   VEX_W_0F3A46_P_2,
2041   VEX_W_0F3A48_P_2,
2042   VEX_W_0F3A49_P_2,
2043   VEX_W_0F3A4A_P_2,
2044   VEX_W_0F3A4B_P_2,
2045   VEX_W_0F3A4C_P_2,
2046   VEX_W_0F3ACE_P_2,
2047   VEX_W_0F3ACF_P_2,
2048
2049   EVEX_W_0F10_P_0,
2050   EVEX_W_0F10_P_1_M_0,
2051   EVEX_W_0F10_P_1_M_1,
2052   EVEX_W_0F10_P_2,
2053   EVEX_W_0F10_P_3_M_0,
2054   EVEX_W_0F10_P_3_M_1,
2055   EVEX_W_0F11_P_0,
2056   EVEX_W_0F11_P_1_M_0,
2057   EVEX_W_0F11_P_1_M_1,
2058   EVEX_W_0F11_P_2,
2059   EVEX_W_0F11_P_3_M_0,
2060   EVEX_W_0F11_P_3_M_1,
2061   EVEX_W_0F12_P_0_M_0,
2062   EVEX_W_0F12_P_0_M_1,
2063   EVEX_W_0F12_P_1,
2064   EVEX_W_0F12_P_2,
2065   EVEX_W_0F12_P_3,
2066   EVEX_W_0F13_P_0,
2067   EVEX_W_0F13_P_2,
2068   EVEX_W_0F14_P_0,
2069   EVEX_W_0F14_P_2,
2070   EVEX_W_0F15_P_0,
2071   EVEX_W_0F15_P_2,
2072   EVEX_W_0F16_P_0_M_0,
2073   EVEX_W_0F16_P_0_M_1,
2074   EVEX_W_0F16_P_1,
2075   EVEX_W_0F16_P_2,
2076   EVEX_W_0F17_P_0,
2077   EVEX_W_0F17_P_2,
2078   EVEX_W_0F28_P_0,
2079   EVEX_W_0F28_P_2,
2080   EVEX_W_0F29_P_0,
2081   EVEX_W_0F29_P_2,
2082   EVEX_W_0F2A_P_3,
2083   EVEX_W_0F2B_P_0,
2084   EVEX_W_0F2B_P_2,
2085   EVEX_W_0F2E_P_0,
2086   EVEX_W_0F2E_P_2,
2087   EVEX_W_0F2F_P_0,
2088   EVEX_W_0F2F_P_2,
2089   EVEX_W_0F51_P_0,
2090   EVEX_W_0F51_P_1,
2091   EVEX_W_0F51_P_2,
2092   EVEX_W_0F51_P_3,
2093   EVEX_W_0F54_P_0,
2094   EVEX_W_0F54_P_2,
2095   EVEX_W_0F55_P_0,
2096   EVEX_W_0F55_P_2,
2097   EVEX_W_0F56_P_0,
2098   EVEX_W_0F56_P_2,
2099   EVEX_W_0F57_P_0,
2100   EVEX_W_0F57_P_2,
2101   EVEX_W_0F58_P_0,
2102   EVEX_W_0F58_P_1,
2103   EVEX_W_0F58_P_2,
2104   EVEX_W_0F58_P_3,
2105   EVEX_W_0F59_P_0,
2106   EVEX_W_0F59_P_1,
2107   EVEX_W_0F59_P_2,
2108   EVEX_W_0F59_P_3,
2109   EVEX_W_0F5A_P_0,
2110   EVEX_W_0F5A_P_1,
2111   EVEX_W_0F5A_P_2,
2112   EVEX_W_0F5A_P_3,
2113   EVEX_W_0F5B_P_0,
2114   EVEX_W_0F5B_P_1,
2115   EVEX_W_0F5B_P_2,
2116   EVEX_W_0F5C_P_0,
2117   EVEX_W_0F5C_P_1,
2118   EVEX_W_0F5C_P_2,
2119   EVEX_W_0F5C_P_3,
2120   EVEX_W_0F5D_P_0,
2121   EVEX_W_0F5D_P_1,
2122   EVEX_W_0F5D_P_2,
2123   EVEX_W_0F5D_P_3,
2124   EVEX_W_0F5E_P_0,
2125   EVEX_W_0F5E_P_1,
2126   EVEX_W_0F5E_P_2,
2127   EVEX_W_0F5E_P_3,
2128   EVEX_W_0F5F_P_0,
2129   EVEX_W_0F5F_P_1,
2130   EVEX_W_0F5F_P_2,
2131   EVEX_W_0F5F_P_3,
2132   EVEX_W_0F62_P_2,
2133   EVEX_W_0F66_P_2,
2134   EVEX_W_0F6A_P_2,
2135   EVEX_W_0F6B_P_2,
2136   EVEX_W_0F6C_P_2,
2137   EVEX_W_0F6D_P_2,
2138   EVEX_W_0F6F_P_1,
2139   EVEX_W_0F6F_P_2,
2140   EVEX_W_0F6F_P_3,
2141   EVEX_W_0F70_P_2,
2142   EVEX_W_0F72_R_2_P_2,
2143   EVEX_W_0F72_R_6_P_2,
2144   EVEX_W_0F73_R_2_P_2,
2145   EVEX_W_0F73_R_6_P_2,
2146   EVEX_W_0F76_P_2,
2147   EVEX_W_0F78_P_0,
2148   EVEX_W_0F78_P_2,
2149   EVEX_W_0F79_P_0,
2150   EVEX_W_0F79_P_2,
2151   EVEX_W_0F7A_P_1,
2152   EVEX_W_0F7A_P_2,
2153   EVEX_W_0F7A_P_3,
2154   EVEX_W_0F7B_P_2,
2155   EVEX_W_0F7B_P_3,
2156   EVEX_W_0F7E_P_1,
2157   EVEX_W_0F7F_P_1,
2158   EVEX_W_0F7F_P_2,
2159   EVEX_W_0F7F_P_3,
2160   EVEX_W_0FC2_P_0,
2161   EVEX_W_0FC2_P_1,
2162   EVEX_W_0FC2_P_2,
2163   EVEX_W_0FC2_P_3,
2164   EVEX_W_0FC6_P_0,
2165   EVEX_W_0FC6_P_2,
2166   EVEX_W_0FD2_P_2,
2167   EVEX_W_0FD3_P_2,
2168   EVEX_W_0FD4_P_2,
2169   EVEX_W_0FD6_P_2,
2170   EVEX_W_0FE6_P_1,
2171   EVEX_W_0FE6_P_2,
2172   EVEX_W_0FE6_P_3,
2173   EVEX_W_0FE7_P_2,
2174   EVEX_W_0FF2_P_2,
2175   EVEX_W_0FF3_P_2,
2176   EVEX_W_0FF4_P_2,
2177   EVEX_W_0FFA_P_2,
2178   EVEX_W_0FFB_P_2,
2179   EVEX_W_0FFE_P_2,
2180   EVEX_W_0F380C_P_2,
2181   EVEX_W_0F380D_P_2,
2182   EVEX_W_0F3810_P_1,
2183   EVEX_W_0F3810_P_2,
2184   EVEX_W_0F3811_P_1,
2185   EVEX_W_0F3811_P_2,
2186   EVEX_W_0F3812_P_1,
2187   EVEX_W_0F3812_P_2,
2188   EVEX_W_0F3813_P_1,
2189   EVEX_W_0F3813_P_2,
2190   EVEX_W_0F3814_P_1,
2191   EVEX_W_0F3815_P_1,
2192   EVEX_W_0F3818_P_2,
2193   EVEX_W_0F3819_P_2,
2194   EVEX_W_0F381A_P_2,
2195   EVEX_W_0F381B_P_2,
2196   EVEX_W_0F381E_P_2,
2197   EVEX_W_0F381F_P_2,
2198   EVEX_W_0F3820_P_1,
2199   EVEX_W_0F3821_P_1,
2200   EVEX_W_0F3822_P_1,
2201   EVEX_W_0F3823_P_1,
2202   EVEX_W_0F3824_P_1,
2203   EVEX_W_0F3825_P_1,
2204   EVEX_W_0F3825_P_2,
2205   EVEX_W_0F3826_P_1,
2206   EVEX_W_0F3826_P_2,
2207   EVEX_W_0F3828_P_1,
2208   EVEX_W_0F3828_P_2,
2209   EVEX_W_0F3829_P_1,
2210   EVEX_W_0F3829_P_2,
2211   EVEX_W_0F382A_P_1,
2212   EVEX_W_0F382A_P_2,
2213   EVEX_W_0F382B_P_2,
2214   EVEX_W_0F3830_P_1,
2215   EVEX_W_0F3831_P_1,
2216   EVEX_W_0F3832_P_1,
2217   EVEX_W_0F3833_P_1,
2218   EVEX_W_0F3834_P_1,
2219   EVEX_W_0F3835_P_1,
2220   EVEX_W_0F3835_P_2,
2221   EVEX_W_0F3837_P_2,
2222   EVEX_W_0F3838_P_1,
2223   EVEX_W_0F3839_P_1,
2224   EVEX_W_0F383A_P_1,
2225   EVEX_W_0F3840_P_2,
2226   EVEX_W_0F3852_P_1,
2227   EVEX_W_0F3854_P_2,
2228   EVEX_W_0F3855_P_2,
2229   EVEX_W_0F3858_P_2,
2230   EVEX_W_0F3859_P_2,
2231   EVEX_W_0F385A_P_2,
2232   EVEX_W_0F385B_P_2,
2233   EVEX_W_0F3862_P_2,
2234   EVEX_W_0F3863_P_2,
2235   EVEX_W_0F3866_P_2,
2236   EVEX_W_0F3868_P_3,
2237   EVEX_W_0F3870_P_2,
2238   EVEX_W_0F3871_P_2,
2239   EVEX_W_0F3872_P_1,
2240   EVEX_W_0F3872_P_2,
2241   EVEX_W_0F3872_P_3,
2242   EVEX_W_0F3873_P_2,
2243   EVEX_W_0F3875_P_2,
2244   EVEX_W_0F3878_P_2,
2245   EVEX_W_0F3879_P_2,
2246   EVEX_W_0F387A_P_2,
2247   EVEX_W_0F387B_P_2,
2248   EVEX_W_0F387D_P_2,
2249   EVEX_W_0F3883_P_2,
2250   EVEX_W_0F388D_P_2,
2251   EVEX_W_0F3891_P_2,
2252   EVEX_W_0F3893_P_2,
2253   EVEX_W_0F38A1_P_2,
2254   EVEX_W_0F38A3_P_2,
2255   EVEX_W_0F38C7_R_1_P_2,
2256   EVEX_W_0F38C7_R_2_P_2,
2257   EVEX_W_0F38C7_R_5_P_2,
2258   EVEX_W_0F38C7_R_6_P_2,
2259
2260   EVEX_W_0F3A00_P_2,
2261   EVEX_W_0F3A01_P_2,
2262   EVEX_W_0F3A04_P_2,
2263   EVEX_W_0F3A05_P_2,
2264   EVEX_W_0F3A08_P_2,
2265   EVEX_W_0F3A09_P_2,
2266   EVEX_W_0F3A0A_P_2,
2267   EVEX_W_0F3A0B_P_2,
2268   EVEX_W_0F3A18_P_2,
2269   EVEX_W_0F3A19_P_2,
2270   EVEX_W_0F3A1A_P_2,
2271   EVEX_W_0F3A1B_P_2,
2272   EVEX_W_0F3A1D_P_2,
2273   EVEX_W_0F3A21_P_2,
2274   EVEX_W_0F3A23_P_2,
2275   EVEX_W_0F3A38_P_2,
2276   EVEX_W_0F3A39_P_2,
2277   EVEX_W_0F3A3A_P_2,
2278   EVEX_W_0F3A3B_P_2,
2279   EVEX_W_0F3A3E_P_2,
2280   EVEX_W_0F3A3F_P_2,
2281   EVEX_W_0F3A42_P_2,
2282   EVEX_W_0F3A43_P_2,
2283   EVEX_W_0F3A50_P_2,
2284   EVEX_W_0F3A51_P_2,
2285   EVEX_W_0F3A56_P_2,
2286   EVEX_W_0F3A57_P_2,
2287   EVEX_W_0F3A66_P_2,
2288   EVEX_W_0F3A67_P_2,
2289   EVEX_W_0F3A70_P_2,
2290   EVEX_W_0F3A71_P_2,
2291   EVEX_W_0F3A72_P_2,
2292   EVEX_W_0F3A73_P_2,
2293   EVEX_W_0F3ACE_P_2,
2294   EVEX_W_0F3ACF_P_2
2295 };
2296
2297 typedef void (*op_rtn) (int bytemode, int sizeflag);
2298
2299 struct dis386 {
2300   const char *name;
2301   struct
2302     {
2303       op_rtn rtn;
2304       int bytemode;
2305     } op[MAX_OPERANDS];
2306   unsigned int prefix_requirement;
2307 };
2308
2309 /* Upper case letters in the instruction names here are macros.
2310    'A' => print 'b' if no register operands or suffix_always is true
2311    'B' => print 'b' if suffix_always is true
2312    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2313           size prefix
2314    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2315           suffix_always is true
2316    'E' => print 'e' if 32-bit form of jcxz
2317    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2318    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2319    'H' => print ",pt" or ",pn" branch hint
2320    'I' => honor following macro letter even in Intel mode (implemented only
2321           for some of the macro letters)
2322    'J' => print 'l'
2323    'K' => print 'd' or 'q' if rex prefix is present.
2324    'L' => print 'l' if suffix_always is true
2325    'M' => print 'r' if intel_mnemonic is false.
2326    'N' => print 'n' if instruction has no wait "prefix"
2327    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2328    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2329           or suffix_always is true.  print 'q' if rex prefix is present.
2330    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2331           is true
2332    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2333    'S' => print 'w', 'l' or 'q' if suffix_always is true
2334    'T' => print 'q' in 64bit mode if instruction has no operand size
2335           prefix and behave as 'P' otherwise
2336    'U' => print 'q' in 64bit mode if instruction has no operand size
2337           prefix and behave as 'Q' otherwise
2338    'V' => print 'q' in 64bit mode if instruction has no operand size
2339           prefix and behave as 'S' otherwise
2340    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2341    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2342    'Y' unused.
2343    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2344    '!' => change condition from true to false or from false to true.
2345    '%' => add 1 upper case letter to the macro.
2346    '^' => print 'w' or 'l' depending on operand size prefix or
2347           suffix_always is true (lcall/ljmp).
2348    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2349           on operand size prefix.
2350    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2351           has no operand size prefix for AMD64 ISA, behave as 'P'
2352           otherwise
2353
2354    2 upper case letter macros:
2355    "XY" => print 'x' or 'y' if suffix_always is true or no register
2356            operands and no broadcast.
2357    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2358            register operands and no broadcast.
2359    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2360    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2361            or suffix_always is true
2362    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2363    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2364    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2365    "LW" => print 'd', 'q' depending on the VEX.W bit
2366    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2367            an operand size prefix, or suffix_always is true.  print
2368            'q' if rex prefix is present.
2369
2370    Many of the above letters print nothing in Intel mode.  See "putop"
2371    for the details.
2372
2373    Braces '{' and '}', and vertical bars '|', indicate alternative
2374    mnemonic strings for AT&T and Intel.  */
2375
2376 static const struct dis386 dis386[] = {
2377   /* 00 */
2378   { "addB",             { Ebh1, Gb }, 0 },
2379   { "addS",             { Evh1, Gv }, 0 },
2380   { "addB",             { Gb, EbS }, 0 },
2381   { "addS",             { Gv, EvS }, 0 },
2382   { "addB",             { AL, Ib }, 0 },
2383   { "addS",             { eAX, Iv }, 0 },
2384   { X86_64_TABLE (X86_64_06) },
2385   { X86_64_TABLE (X86_64_07) },
2386   /* 08 */
2387   { "orB",              { Ebh1, Gb }, 0 },
2388   { "orS",              { Evh1, Gv }, 0 },
2389   { "orB",              { Gb, EbS }, 0 },
2390   { "orS",              { Gv, EvS }, 0 },
2391   { "orB",              { AL, Ib }, 0 },
2392   { "orS",              { eAX, Iv }, 0 },
2393   { X86_64_TABLE (X86_64_0D) },
2394   { Bad_Opcode },       /* 0x0f extended opcode escape */
2395   /* 10 */
2396   { "adcB",             { Ebh1, Gb }, 0 },
2397   { "adcS",             { Evh1, Gv }, 0 },
2398   { "adcB",             { Gb, EbS }, 0 },
2399   { "adcS",             { Gv, EvS }, 0 },
2400   { "adcB",             { AL, Ib }, 0 },
2401   { "adcS",             { eAX, Iv }, 0 },
2402   { X86_64_TABLE (X86_64_16) },
2403   { X86_64_TABLE (X86_64_17) },
2404   /* 18 */
2405   { "sbbB",             { Ebh1, Gb }, 0 },
2406   { "sbbS",             { Evh1, Gv }, 0 },
2407   { "sbbB",             { Gb, EbS }, 0 },
2408   { "sbbS",             { Gv, EvS }, 0 },
2409   { "sbbB",             { AL, Ib }, 0 },
2410   { "sbbS",             { eAX, Iv }, 0 },
2411   { X86_64_TABLE (X86_64_1E) },
2412   { X86_64_TABLE (X86_64_1F) },
2413   /* 20 */
2414   { "andB",             { Ebh1, Gb }, 0 },
2415   { "andS",             { Evh1, Gv }, 0 },
2416   { "andB",             { Gb, EbS }, 0 },
2417   { "andS",             { Gv, EvS }, 0 },
2418   { "andB",             { AL, Ib }, 0 },
2419   { "andS",             { eAX, Iv }, 0 },
2420   { Bad_Opcode },       /* SEG ES prefix */
2421   { X86_64_TABLE (X86_64_27) },
2422   /* 28 */
2423   { "subB",             { Ebh1, Gb }, 0 },
2424   { "subS",             { Evh1, Gv }, 0 },
2425   { "subB",             { Gb, EbS }, 0 },
2426   { "subS",             { Gv, EvS }, 0 },
2427   { "subB",             { AL, Ib }, 0 },
2428   { "subS",             { eAX, Iv }, 0 },
2429   { Bad_Opcode },       /* SEG CS prefix */
2430   { X86_64_TABLE (X86_64_2F) },
2431   /* 30 */
2432   { "xorB",             { Ebh1, Gb }, 0 },
2433   { "xorS",             { Evh1, Gv }, 0 },
2434   { "xorB",             { Gb, EbS }, 0 },
2435   { "xorS",             { Gv, EvS }, 0 },
2436   { "xorB",             { AL, Ib }, 0 },
2437   { "xorS",             { eAX, Iv }, 0 },
2438   { Bad_Opcode },       /* SEG SS prefix */
2439   { X86_64_TABLE (X86_64_37) },
2440   /* 38 */
2441   { "cmpB",             { Eb, Gb }, 0 },
2442   { "cmpS",             { Ev, Gv }, 0 },
2443   { "cmpB",             { Gb, EbS }, 0 },
2444   { "cmpS",             { Gv, EvS }, 0 },
2445   { "cmpB",             { AL, Ib }, 0 },
2446   { "cmpS",             { eAX, Iv }, 0 },
2447   { Bad_Opcode },       /* SEG DS prefix */
2448   { X86_64_TABLE (X86_64_3F) },
2449   /* 40 */
2450   { "inc{S|}",          { RMeAX }, 0 },
2451   { "inc{S|}",          { RMeCX }, 0 },
2452   { "inc{S|}",          { RMeDX }, 0 },
2453   { "inc{S|}",          { RMeBX }, 0 },
2454   { "inc{S|}",          { RMeSP }, 0 },
2455   { "inc{S|}",          { RMeBP }, 0 },
2456   { "inc{S|}",          { RMeSI }, 0 },
2457   { "inc{S|}",          { RMeDI }, 0 },
2458   /* 48 */
2459   { "dec{S|}",          { RMeAX }, 0 },
2460   { "dec{S|}",          { RMeCX }, 0 },
2461   { "dec{S|}",          { RMeDX }, 0 },
2462   { "dec{S|}",          { RMeBX }, 0 },
2463   { "dec{S|}",          { RMeSP }, 0 },
2464   { "dec{S|}",          { RMeBP }, 0 },
2465   { "dec{S|}",          { RMeSI }, 0 },
2466   { "dec{S|}",          { RMeDI }, 0 },
2467   /* 50 */
2468   { "pushV",            { RMrAX }, 0 },
2469   { "pushV",            { RMrCX }, 0 },
2470   { "pushV",            { RMrDX }, 0 },
2471   { "pushV",            { RMrBX }, 0 },
2472   { "pushV",            { RMrSP }, 0 },
2473   { "pushV",            { RMrBP }, 0 },
2474   { "pushV",            { RMrSI }, 0 },
2475   { "pushV",            { RMrDI }, 0 },
2476   /* 58 */
2477   { "popV",             { RMrAX }, 0 },
2478   { "popV",             { RMrCX }, 0 },
2479   { "popV",             { RMrDX }, 0 },
2480   { "popV",             { RMrBX }, 0 },
2481   { "popV",             { RMrSP }, 0 },
2482   { "popV",             { RMrBP }, 0 },
2483   { "popV",             { RMrSI }, 0 },
2484   { "popV",             { RMrDI }, 0 },
2485   /* 60 */
2486   { X86_64_TABLE (X86_64_60) },
2487   { X86_64_TABLE (X86_64_61) },
2488   { X86_64_TABLE (X86_64_62) },
2489   { X86_64_TABLE (X86_64_63) },
2490   { Bad_Opcode },       /* seg fs */
2491   { Bad_Opcode },       /* seg gs */
2492   { Bad_Opcode },       /* op size prefix */
2493   { Bad_Opcode },       /* adr size prefix */
2494   /* 68 */
2495   { "pushT",            { sIv }, 0 },
2496   { "imulS",            { Gv, Ev, Iv }, 0 },
2497   { "pushT",            { sIbT }, 0 },
2498   { "imulS",            { Gv, Ev, sIb }, 0 },
2499   { "ins{b|}",          { Ybr, indirDX }, 0 },
2500   { X86_64_TABLE (X86_64_6D) },
2501   { "outs{b|}",         { indirDXr, Xb }, 0 },
2502   { X86_64_TABLE (X86_64_6F) },
2503   /* 70 */
2504   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2505   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2507   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2508   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2509   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2510   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2511   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2512   /* 78 */
2513   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2514   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2515   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2516   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2517   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2518   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2519   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2520   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2521   /* 80 */
2522   { REG_TABLE (REG_80) },
2523   { REG_TABLE (REG_81) },
2524   { X86_64_TABLE (X86_64_82) },
2525   { REG_TABLE (REG_83) },
2526   { "testB",            { Eb, Gb }, 0 },
2527   { "testS",            { Ev, Gv }, 0 },
2528   { "xchgB",            { Ebh2, Gb }, 0 },
2529   { "xchgS",            { Evh2, Gv }, 0 },
2530   /* 88 */
2531   { "movB",             { Ebh3, Gb }, 0 },
2532   { "movS",             { Evh3, Gv }, 0 },
2533   { "movB",             { Gb, EbS }, 0 },
2534   { "movS",             { Gv, EvS }, 0 },
2535   { "movD",             { Sv, Sw }, 0 },
2536   { MOD_TABLE (MOD_8D) },
2537   { "movD",             { Sw, Sv }, 0 },
2538   { REG_TABLE (REG_8F) },
2539   /* 90 */
2540   { PREFIX_TABLE (PREFIX_90) },
2541   { "xchgS",            { RMeCX, eAX }, 0 },
2542   { "xchgS",            { RMeDX, eAX }, 0 },
2543   { "xchgS",            { RMeBX, eAX }, 0 },
2544   { "xchgS",            { RMeSP, eAX }, 0 },
2545   { "xchgS",            { RMeBP, eAX }, 0 },
2546   { "xchgS",            { RMeSI, eAX }, 0 },
2547   { "xchgS",            { RMeDI, eAX }, 0 },
2548   /* 98 */
2549   { "cW{t|}R",          { XX }, 0 },
2550   { "cR{t|}O",          { XX }, 0 },
2551   { X86_64_TABLE (X86_64_9A) },
2552   { Bad_Opcode },       /* fwait */
2553   { "pushfT",           { XX }, 0 },
2554   { "popfT",            { XX }, 0 },
2555   { "sahf",             { XX }, 0 },
2556   { "lahf",             { XX }, 0 },
2557   /* a0 */
2558   { "mov%LB",           { AL, Ob }, 0 },
2559   { "mov%LS",           { eAX, Ov }, 0 },
2560   { "mov%LB",           { Ob, AL }, 0 },
2561   { "mov%LS",           { Ov, eAX }, 0 },
2562   { "movs{b|}",         { Ybr, Xb }, 0 },
2563   { "movs{R|}",         { Yvr, Xv }, 0 },
2564   { "cmps{b|}",         { Xb, Yb }, 0 },
2565   { "cmps{R|}",         { Xv, Yv }, 0 },
2566   /* a8 */
2567   { "testB",            { AL, Ib }, 0 },
2568   { "testS",            { eAX, Iv }, 0 },
2569   { "stosB",            { Ybr, AL }, 0 },
2570   { "stosS",            { Yvr, eAX }, 0 },
2571   { "lodsB",            { ALr, Xb }, 0 },
2572   { "lodsS",            { eAXr, Xv }, 0 },
2573   { "scasB",            { AL, Yb }, 0 },
2574   { "scasS",            { eAX, Yv }, 0 },
2575   /* b0 */
2576   { "movB",             { RMAL, Ib }, 0 },
2577   { "movB",             { RMCL, Ib }, 0 },
2578   { "movB",             { RMDL, Ib }, 0 },
2579   { "movB",             { RMBL, Ib }, 0 },
2580   { "movB",             { RMAH, Ib }, 0 },
2581   { "movB",             { RMCH, Ib }, 0 },
2582   { "movB",             { RMDH, Ib }, 0 },
2583   { "movB",             { RMBH, Ib }, 0 },
2584   /* b8 */
2585   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2586   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2587   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2588   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2589   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2590   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2591   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2592   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2593   /* c0 */
2594   { REG_TABLE (REG_C0) },
2595   { REG_TABLE (REG_C1) },
2596   { "retT",             { Iw, BND }, 0 },
2597   { "retT",             { BND }, 0 },
2598   { X86_64_TABLE (X86_64_C4) },
2599   { X86_64_TABLE (X86_64_C5) },
2600   { REG_TABLE (REG_C6) },
2601   { REG_TABLE (REG_C7) },
2602   /* c8 */
2603   { "enterT",           { Iw, Ib }, 0 },
2604   { "leaveT",           { XX }, 0 },
2605   { "Jret{|f}P",        { Iw }, 0 },
2606   { "Jret{|f}P",        { XX }, 0 },
2607   { "int3",             { XX }, 0 },
2608   { "int",              { Ib }, 0 },
2609   { X86_64_TABLE (X86_64_CE) },
2610   { "iret%LP",          { XX }, 0 },
2611   /* d0 */
2612   { REG_TABLE (REG_D0) },
2613   { REG_TABLE (REG_D1) },
2614   { REG_TABLE (REG_D2) },
2615   { REG_TABLE (REG_D3) },
2616   { X86_64_TABLE (X86_64_D4) },
2617   { X86_64_TABLE (X86_64_D5) },
2618   { Bad_Opcode },
2619   { "xlat",             { DSBX }, 0 },
2620   /* d8 */
2621   { FLOAT },
2622   { FLOAT },
2623   { FLOAT },
2624   { FLOAT },
2625   { FLOAT },
2626   { FLOAT },
2627   { FLOAT },
2628   { FLOAT },
2629   /* e0 */
2630   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2631   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2632   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2633   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2634   { "inB",              { AL, Ib }, 0 },
2635   { "inG",              { zAX, Ib }, 0 },
2636   { "outB",             { Ib, AL }, 0 },
2637   { "outG",             { Ib, zAX }, 0 },
2638   /* e8 */
2639   { X86_64_TABLE (X86_64_E8) },
2640   { X86_64_TABLE (X86_64_E9) },
2641   { X86_64_TABLE (X86_64_EA) },
2642   { "jmp",              { Jb, BND }, 0 },
2643   { "inB",              { AL, indirDX }, 0 },
2644   { "inG",              { zAX, indirDX }, 0 },
2645   { "outB",             { indirDX, AL }, 0 },
2646   { "outG",             { indirDX, zAX }, 0 },
2647   /* f0 */
2648   { Bad_Opcode },       /* lock prefix */
2649   { "icebp",            { XX }, 0 },
2650   { Bad_Opcode },       /* repne */
2651   { Bad_Opcode },       /* repz */
2652   { "hlt",              { XX }, 0 },
2653   { "cmc",              { XX }, 0 },
2654   { REG_TABLE (REG_F6) },
2655   { REG_TABLE (REG_F7) },
2656   /* f8 */
2657   { "clc",              { XX }, 0 },
2658   { "stc",              { XX }, 0 },
2659   { "cli",              { XX }, 0 },
2660   { "sti",              { XX }, 0 },
2661   { "cld",              { XX }, 0 },
2662   { "std",              { XX }, 0 },
2663   { REG_TABLE (REG_FE) },
2664   { REG_TABLE (REG_FF) },
2665 };
2666
2667 static const struct dis386 dis386_twobyte[] = {
2668   /* 00 */
2669   { REG_TABLE (REG_0F00 ) },
2670   { REG_TABLE (REG_0F01 ) },
2671   { "larS",             { Gv, Ew }, 0 },
2672   { "lslS",             { Gv, Ew }, 0 },
2673   { Bad_Opcode },
2674   { "syscall",          { XX }, 0 },
2675   { "clts",             { XX }, 0 },
2676   { "sysret%LP",                { XX }, 0 },
2677   /* 08 */
2678   { "invd",             { XX }, 0 },
2679   { PREFIX_TABLE (PREFIX_0F09) },
2680   { Bad_Opcode },
2681   { "ud2",              { XX }, 0 },
2682   { Bad_Opcode },
2683   { REG_TABLE (REG_0F0D) },
2684   { "femms",            { XX }, 0 },
2685   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2686   /* 10 */
2687   { PREFIX_TABLE (PREFIX_0F10) },
2688   { PREFIX_TABLE (PREFIX_0F11) },
2689   { PREFIX_TABLE (PREFIX_0F12) },
2690   { MOD_TABLE (MOD_0F13) },
2691   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2692   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2693   { PREFIX_TABLE (PREFIX_0F16) },
2694   { MOD_TABLE (MOD_0F17) },
2695   /* 18 */
2696   { REG_TABLE (REG_0F18) },
2697   { "nopQ",             { Ev }, 0 },
2698   { PREFIX_TABLE (PREFIX_0F1A) },
2699   { PREFIX_TABLE (PREFIX_0F1B) },
2700   { PREFIX_TABLE (PREFIX_0F1C) },
2701   { "nopQ",             { Ev }, 0 },
2702   { PREFIX_TABLE (PREFIX_0F1E) },
2703   { "nopQ",             { Ev }, 0 },
2704   /* 20 */
2705   { "movZ",             { Rm, Cm }, 0 },
2706   { "movZ",             { Rm, Dm }, 0 },
2707   { "movZ",             { Cm, Rm }, 0 },
2708   { "movZ",             { Dm, Rm }, 0 },
2709   { MOD_TABLE (MOD_0F24) },
2710   { Bad_Opcode },
2711   { MOD_TABLE (MOD_0F26) },
2712   { Bad_Opcode },
2713   /* 28 */
2714   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2715   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2716   { PREFIX_TABLE (PREFIX_0F2A) },
2717   { PREFIX_TABLE (PREFIX_0F2B) },
2718   { PREFIX_TABLE (PREFIX_0F2C) },
2719   { PREFIX_TABLE (PREFIX_0F2D) },
2720   { PREFIX_TABLE (PREFIX_0F2E) },
2721   { PREFIX_TABLE (PREFIX_0F2F) },
2722   /* 30 */
2723   { "wrmsr",            { XX }, 0 },
2724   { "rdtsc",            { XX }, 0 },
2725   { "rdmsr",            { XX }, 0 },
2726   { "rdpmc",            { XX }, 0 },
2727   { "sysenter",         { XX }, 0 },
2728   { "sysexit",          { XX }, 0 },
2729   { Bad_Opcode },
2730   { "getsec",           { XX }, 0 },
2731   /* 38 */
2732   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2733   { Bad_Opcode },
2734   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2735   { Bad_Opcode },
2736   { Bad_Opcode },
2737   { Bad_Opcode },
2738   { Bad_Opcode },
2739   { Bad_Opcode },
2740   /* 40 */
2741   { "cmovoS",           { Gv, Ev }, 0 },
2742   { "cmovnoS",          { Gv, Ev }, 0 },
2743   { "cmovbS",           { Gv, Ev }, 0 },
2744   { "cmovaeS",          { Gv, Ev }, 0 },
2745   { "cmoveS",           { Gv, Ev }, 0 },
2746   { "cmovneS",          { Gv, Ev }, 0 },
2747   { "cmovbeS",          { Gv, Ev }, 0 },
2748   { "cmovaS",           { Gv, Ev }, 0 },
2749   /* 48 */
2750   { "cmovsS",           { Gv, Ev }, 0 },
2751   { "cmovnsS",          { Gv, Ev }, 0 },
2752   { "cmovpS",           { Gv, Ev }, 0 },
2753   { "cmovnpS",          { Gv, Ev }, 0 },
2754   { "cmovlS",           { Gv, Ev }, 0 },
2755   { "cmovgeS",          { Gv, Ev }, 0 },
2756   { "cmovleS",          { Gv, Ev }, 0 },
2757   { "cmovgS",           { Gv, Ev }, 0 },
2758   /* 50 */
2759   { MOD_TABLE (MOD_0F51) },
2760   { PREFIX_TABLE (PREFIX_0F51) },
2761   { PREFIX_TABLE (PREFIX_0F52) },
2762   { PREFIX_TABLE (PREFIX_0F53) },
2763   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2764   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2765   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2766   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2767   /* 58 */
2768   { PREFIX_TABLE (PREFIX_0F58) },
2769   { PREFIX_TABLE (PREFIX_0F59) },
2770   { PREFIX_TABLE (PREFIX_0F5A) },
2771   { PREFIX_TABLE (PREFIX_0F5B) },
2772   { PREFIX_TABLE (PREFIX_0F5C) },
2773   { PREFIX_TABLE (PREFIX_0F5D) },
2774   { PREFIX_TABLE (PREFIX_0F5E) },
2775   { PREFIX_TABLE (PREFIX_0F5F) },
2776   /* 60 */
2777   { PREFIX_TABLE (PREFIX_0F60) },
2778   { PREFIX_TABLE (PREFIX_0F61) },
2779   { PREFIX_TABLE (PREFIX_0F62) },
2780   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2781   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2782   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2783   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2784   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2785   /* 68 */
2786   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2787   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2788   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2789   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2790   { PREFIX_TABLE (PREFIX_0F6C) },
2791   { PREFIX_TABLE (PREFIX_0F6D) },
2792   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2793   { PREFIX_TABLE (PREFIX_0F6F) },
2794   /* 70 */
2795   { PREFIX_TABLE (PREFIX_0F70) },
2796   { REG_TABLE (REG_0F71) },
2797   { REG_TABLE (REG_0F72) },
2798   { REG_TABLE (REG_0F73) },
2799   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2800   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2801   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2802   { "emms",             { XX }, PREFIX_OPCODE },
2803   /* 78 */
2804   { PREFIX_TABLE (PREFIX_0F78) },
2805   { PREFIX_TABLE (PREFIX_0F79) },
2806   { Bad_Opcode },
2807   { Bad_Opcode },
2808   { PREFIX_TABLE (PREFIX_0F7C) },
2809   { PREFIX_TABLE (PREFIX_0F7D) },
2810   { PREFIX_TABLE (PREFIX_0F7E) },
2811   { PREFIX_TABLE (PREFIX_0F7F) },
2812   /* 80 */
2813   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2814   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2816   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2817   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2818   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2819   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2820   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2821   /* 88 */
2822   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2823   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2824   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2825   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2826   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2827   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2828   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2829   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2830   /* 90 */
2831   { "seto",             { Eb }, 0 },
2832   { "setno",            { Eb }, 0 },
2833   { "setb",             { Eb }, 0 },
2834   { "setae",            { Eb }, 0 },
2835   { "sete",             { Eb }, 0 },
2836   { "setne",            { Eb }, 0 },
2837   { "setbe",            { Eb }, 0 },
2838   { "seta",             { Eb }, 0 },
2839   /* 98 */
2840   { "sets",             { Eb }, 0 },
2841   { "setns",            { Eb }, 0 },
2842   { "setp",             { Eb }, 0 },
2843   { "setnp",            { Eb }, 0 },
2844   { "setl",             { Eb }, 0 },
2845   { "setge",            { Eb }, 0 },
2846   { "setle",            { Eb }, 0 },
2847   { "setg",             { Eb }, 0 },
2848   /* a0 */
2849   { "pushT",            { fs }, 0 },
2850   { "popT",             { fs }, 0 },
2851   { "cpuid",            { XX }, 0 },
2852   { "btS",              { Ev, Gv }, 0 },
2853   { "shldS",            { Ev, Gv, Ib }, 0 },
2854   { "shldS",            { Ev, Gv, CL }, 0 },
2855   { REG_TABLE (REG_0FA6) },
2856   { REG_TABLE (REG_0FA7) },
2857   /* a8 */
2858   { "pushT",            { gs }, 0 },
2859   { "popT",             { gs }, 0 },
2860   { "rsm",              { XX }, 0 },
2861   { "btsS",             { Evh1, Gv }, 0 },
2862   { "shrdS",            { Ev, Gv, Ib }, 0 },
2863   { "shrdS",            { Ev, Gv, CL }, 0 },
2864   { REG_TABLE (REG_0FAE) },
2865   { "imulS",            { Gv, Ev }, 0 },
2866   /* b0 */
2867   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2868   { "cmpxchgS",         { Evh1, Gv }, 0 },
2869   { MOD_TABLE (MOD_0FB2) },
2870   { "btrS",             { Evh1, Gv }, 0 },
2871   { MOD_TABLE (MOD_0FB4) },
2872   { MOD_TABLE (MOD_0FB5) },
2873   { "movz{bR|x}",       { Gv, Eb }, 0 },
2874   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2875   /* b8 */
2876   { PREFIX_TABLE (PREFIX_0FB8) },
2877   { "ud1S",             { Gv, Ev }, 0 },
2878   { REG_TABLE (REG_0FBA) },
2879   { "btcS",             { Evh1, Gv }, 0 },
2880   { PREFIX_TABLE (PREFIX_0FBC) },
2881   { PREFIX_TABLE (PREFIX_0FBD) },
2882   { "movs{bR|x}",       { Gv, Eb }, 0 },
2883   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2884   /* c0 */
2885   { "xaddB",            { Ebh1, Gb }, 0 },
2886   { "xaddS",            { Evh1, Gv }, 0 },
2887   { PREFIX_TABLE (PREFIX_0FC2) },
2888   { MOD_TABLE (MOD_0FC3) },
2889   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2890   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2891   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2892   { REG_TABLE (REG_0FC7) },
2893   /* c8 */
2894   { "bswap",            { RMeAX }, 0 },
2895   { "bswap",            { RMeCX }, 0 },
2896   { "bswap",            { RMeDX }, 0 },
2897   { "bswap",            { RMeBX }, 0 },
2898   { "bswap",            { RMeSP }, 0 },
2899   { "bswap",            { RMeBP }, 0 },
2900   { "bswap",            { RMeSI }, 0 },
2901   { "bswap",            { RMeDI }, 0 },
2902   /* d0 */
2903   { PREFIX_TABLE (PREFIX_0FD0) },
2904   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2905   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2906   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2907   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2908   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2909   { PREFIX_TABLE (PREFIX_0FD6) },
2910   { MOD_TABLE (MOD_0FD7) },
2911   /* d8 */
2912   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2913   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2914   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2915   { "pand",             { MX, EM }, PREFIX_OPCODE },
2916   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2917   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2918   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2919   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2920   /* e0 */
2921   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2922   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2923   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2924   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2925   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2926   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2927   { PREFIX_TABLE (PREFIX_0FE6) },
2928   { PREFIX_TABLE (PREFIX_0FE7) },
2929   /* e8 */
2930   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2931   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2932   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2933   { "por",              { MX, EM }, PREFIX_OPCODE },
2934   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2935   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2936   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2937   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2938   /* f0 */
2939   { PREFIX_TABLE (PREFIX_0FF0) },
2940   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2941   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2942   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2943   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2944   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2945   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2946   { PREFIX_TABLE (PREFIX_0FF7) },
2947   /* f8 */
2948   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2949   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2950   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2951   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2952   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2953   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2954   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2955   { "ud0S",             { Gv, Ev }, 0 },
2956 };
2957
2958 static const unsigned char onebyte_has_modrm[256] = {
2959   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2960   /*       -------------------------------        */
2961   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2962   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2963   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2964   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2965   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2966   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2967   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2968   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2969   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2970   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2971   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2972   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2973   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2974   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2975   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2976   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2977   /*       -------------------------------        */
2978   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2979 };
2980
2981 static const unsigned char twobyte_has_modrm[256] = {
2982   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2983   /*       -------------------------------        */
2984   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2985   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2986   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2987   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2988   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2989   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2990   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2991   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2992   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2993   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2994   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2995   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2996   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2997   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2998   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2999   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3000   /*       -------------------------------        */
3001   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3002 };
3003
3004 static char obuf[100];
3005 static char *obufp;
3006 static char *mnemonicendp;
3007 static char scratchbuf[100];
3008 static unsigned char *start_codep;
3009 static unsigned char *insn_codep;
3010 static unsigned char *codep;
3011 static unsigned char *end_codep;
3012 static int last_lock_prefix;
3013 static int last_repz_prefix;
3014 static int last_repnz_prefix;
3015 static int last_data_prefix;
3016 static int last_addr_prefix;
3017 static int last_rex_prefix;
3018 static int last_seg_prefix;
3019 static int fwait_prefix;
3020 /* The active segment register prefix.  */
3021 static int active_seg_prefix;
3022 #define MAX_CODE_LENGTH 15
3023 /* We can up to 14 prefixes since the maximum instruction length is
3024    15bytes.  */
3025 static int all_prefixes[MAX_CODE_LENGTH - 1];
3026 static disassemble_info *the_info;
3027 static struct
3028   {
3029     int mod;
3030     int reg;
3031     int rm;
3032   }
3033 modrm;
3034 static unsigned char need_modrm;
3035 static struct
3036   {
3037     int scale;
3038     int index;
3039     int base;
3040   }
3041 sib;
3042 static struct
3043   {
3044     int register_specifier;
3045     int length;
3046     int prefix;
3047     int w;
3048     int evex;
3049     int r;
3050     int v;
3051     int mask_register_specifier;
3052     int zeroing;
3053     int ll;
3054     int b;
3055   }
3056 vex;
3057 static unsigned char need_vex;
3058 static unsigned char need_vex_reg;
3059 static unsigned char vex_w_done;
3060
3061 struct op
3062   {
3063     const char *name;
3064     unsigned int len;
3065   };
3066
3067 /* If we are accessing mod/rm/reg without need_modrm set, then the
3068    values are stale.  Hitting this abort likely indicates that you
3069    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3070 #define MODRM_CHECK  if (!need_modrm) abort ()
3071
3072 static const char **names64;
3073 static const char **names32;
3074 static const char **names16;
3075 static const char **names8;
3076 static const char **names8rex;
3077 static const char **names_seg;
3078 static const char *index64;
3079 static const char *index32;
3080 static const char **index16;
3081 static const char **names_bnd;
3082
3083 static const char *intel_names64[] = {
3084   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3085   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3086 };
3087 static const char *intel_names32[] = {
3088   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3089   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3090 };
3091 static const char *intel_names16[] = {
3092   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3093   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3094 };
3095 static const char *intel_names8[] = {
3096   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3097 };
3098 static const char *intel_names8rex[] = {
3099   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3100   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3101 };
3102 static const char *intel_names_seg[] = {
3103   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3104 };
3105 static const char *intel_index64 = "riz";
3106 static const char *intel_index32 = "eiz";
3107 static const char *intel_index16[] = {
3108   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3109 };
3110
3111 static const char *att_names64[] = {
3112   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3113   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3114 };
3115 static const char *att_names32[] = {
3116   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3117   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3118 };
3119 static const char *att_names16[] = {
3120   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3121   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3122 };
3123 static const char *att_names8[] = {
3124   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3125 };
3126 static const char *att_names8rex[] = {
3127   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3128   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3129 };
3130 static const char *att_names_seg[] = {
3131   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3132 };
3133 static const char *att_index64 = "%riz";
3134 static const char *att_index32 = "%eiz";
3135 static const char *att_index16[] = {
3136   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3137 };
3138
3139 static const char **names_mm;
3140 static const char *intel_names_mm[] = {
3141   "mm0", "mm1", "mm2", "mm3",
3142   "mm4", "mm5", "mm6", "mm7"
3143 };
3144 static const char *att_names_mm[] = {
3145   "%mm0", "%mm1", "%mm2", "%mm3",
3146   "%mm4", "%mm5", "%mm6", "%mm7"
3147 };
3148
3149 static const char *intel_names_bnd[] = {
3150   "bnd0", "bnd1", "bnd2", "bnd3"
3151 };
3152
3153 static const char *att_names_bnd[] = {
3154   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3155 };
3156
3157 static const char **names_xmm;
3158 static const char *intel_names_xmm[] = {
3159   "xmm0", "xmm1", "xmm2", "xmm3",
3160   "xmm4", "xmm5", "xmm6", "xmm7",
3161   "xmm8", "xmm9", "xmm10", "xmm11",
3162   "xmm12", "xmm13", "xmm14", "xmm15",
3163   "xmm16", "xmm17", "xmm18", "xmm19",
3164   "xmm20", "xmm21", "xmm22", "xmm23",
3165   "xmm24", "xmm25", "xmm26", "xmm27",
3166   "xmm28", "xmm29", "xmm30", "xmm31"
3167 };
3168 static const char *att_names_xmm[] = {
3169   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3170   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3171   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3172   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3173   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3174   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3175   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3176   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3177 };
3178
3179 static const char **names_ymm;
3180 static const char *intel_names_ymm[] = {
3181   "ymm0", "ymm1", "ymm2", "ymm3",
3182   "ymm4", "ymm5", "ymm6", "ymm7",
3183   "ymm8", "ymm9", "ymm10", "ymm11",
3184   "ymm12", "ymm13", "ymm14", "ymm15",
3185   "ymm16", "ymm17", "ymm18", "ymm19",
3186   "ymm20", "ymm21", "ymm22", "ymm23",
3187   "ymm24", "ymm25", "ymm26", "ymm27",
3188   "ymm28", "ymm29", "ymm30", "ymm31"
3189 };
3190 static const char *att_names_ymm[] = {
3191   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3192   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3193   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3194   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3195   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3196   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3197   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3198   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3199 };
3200
3201 static const char **names_zmm;
3202 static const char *intel_names_zmm[] = {
3203   "zmm0", "zmm1", "zmm2", "zmm3",
3204   "zmm4", "zmm5", "zmm6", "zmm7",
3205   "zmm8", "zmm9", "zmm10", "zmm11",
3206   "zmm12", "zmm13", "zmm14", "zmm15",
3207   "zmm16", "zmm17", "zmm18", "zmm19",
3208   "zmm20", "zmm21", "zmm22", "zmm23",
3209   "zmm24", "zmm25", "zmm26", "zmm27",
3210   "zmm28", "zmm29", "zmm30", "zmm31"
3211 };
3212 static const char *att_names_zmm[] = {
3213   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3214   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3215   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3216   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3217   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3218   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3219   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3220   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3221 };
3222
3223 static const char **names_mask;
3224 static const char *intel_names_mask[] = {
3225   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3226 };
3227 static const char *att_names_mask[] = {
3228   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3229 };
3230
3231 static const char *names_rounding[] =
3232 {
3233   "{rn-sae}",
3234   "{rd-sae}",
3235   "{ru-sae}",
3236   "{rz-sae}"
3237 };
3238
3239 static const struct dis386 reg_table[][8] = {
3240   /* REG_80 */
3241   {
3242     { "addA",   { Ebh1, Ib }, 0 },
3243     { "orA",    { Ebh1, Ib }, 0 },
3244     { "adcA",   { Ebh1, Ib }, 0 },
3245     { "sbbA",   { Ebh1, Ib }, 0 },
3246     { "andA",   { Ebh1, Ib }, 0 },
3247     { "subA",   { Ebh1, Ib }, 0 },
3248     { "xorA",   { Ebh1, Ib }, 0 },
3249     { "cmpA",   { Eb, Ib }, 0 },
3250   },
3251   /* REG_81 */
3252   {
3253     { "addQ",   { Evh1, Iv }, 0 },
3254     { "orQ",    { Evh1, Iv }, 0 },
3255     { "adcQ",   { Evh1, Iv }, 0 },
3256     { "sbbQ",   { Evh1, Iv }, 0 },
3257     { "andQ",   { Evh1, Iv }, 0 },
3258     { "subQ",   { Evh1, Iv }, 0 },
3259     { "xorQ",   { Evh1, Iv }, 0 },
3260     { "cmpQ",   { Ev, Iv }, 0 },
3261   },
3262   /* REG_83 */
3263   {
3264     { "addQ",   { Evh1, sIb }, 0 },
3265     { "orQ",    { Evh1, sIb }, 0 },
3266     { "adcQ",   { Evh1, sIb }, 0 },
3267     { "sbbQ",   { Evh1, sIb }, 0 },
3268     { "andQ",   { Evh1, sIb }, 0 },
3269     { "subQ",   { Evh1, sIb }, 0 },
3270     { "xorQ",   { Evh1, sIb }, 0 },
3271     { "cmpQ",   { Ev, sIb }, 0 },
3272   },
3273   /* REG_8F */
3274   {
3275     { "popU",   { stackEv }, 0 },
3276     { XOP_8F_TABLE (XOP_09) },
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { Bad_Opcode },
3280     { XOP_8F_TABLE (XOP_09) },
3281   },
3282   /* REG_C0 */
3283   {
3284     { "rolA",   { Eb, Ib }, 0 },
3285     { "rorA",   { Eb, Ib }, 0 },
3286     { "rclA",   { Eb, Ib }, 0 },
3287     { "rcrA",   { Eb, Ib }, 0 },
3288     { "shlA",   { Eb, Ib }, 0 },
3289     { "shrA",   { Eb, Ib }, 0 },
3290     { "shlA",   { Eb, Ib }, 0 },
3291     { "sarA",   { Eb, Ib }, 0 },
3292   },
3293   /* REG_C1 */
3294   {
3295     { "rolQ",   { Ev, Ib }, 0 },
3296     { "rorQ",   { Ev, Ib }, 0 },
3297     { "rclQ",   { Ev, Ib }, 0 },
3298     { "rcrQ",   { Ev, Ib }, 0 },
3299     { "shlQ",   { Ev, Ib }, 0 },
3300     { "shrQ",   { Ev, Ib }, 0 },
3301     { "shlQ",   { Ev, Ib }, 0 },
3302     { "sarQ",   { Ev, Ib }, 0 },
3303   },
3304   /* REG_C6 */
3305   {
3306     { "movA",   { Ebh3, Ib }, 0 },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { MOD_TABLE (MOD_C6_REG_7) },
3314   },
3315   /* REG_C7 */
3316   {
3317     { "movQ",   { Evh3, Iv }, 0 },
3318     { Bad_Opcode },
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { Bad_Opcode },
3324     { MOD_TABLE (MOD_C7_REG_7) },
3325   },
3326   /* REG_D0 */
3327   {
3328     { "rolA",   { Eb, I1 }, 0 },
3329     { "rorA",   { Eb, I1 }, 0 },
3330     { "rclA",   { Eb, I1 }, 0 },
3331     { "rcrA",   { Eb, I1 }, 0 },
3332     { "shlA",   { Eb, I1 }, 0 },
3333     { "shrA",   { Eb, I1 }, 0 },
3334     { "shlA",   { Eb, I1 }, 0 },
3335     { "sarA",   { Eb, I1 }, 0 },
3336   },
3337   /* REG_D1 */
3338   {
3339     { "rolQ",   { Ev, I1 }, 0 },
3340     { "rorQ",   { Ev, I1 }, 0 },
3341     { "rclQ",   { Ev, I1 }, 0 },
3342     { "rcrQ",   { Ev, I1 }, 0 },
3343     { "shlQ",   { Ev, I1 }, 0 },
3344     { "shrQ",   { Ev, I1 }, 0 },
3345     { "shlQ",   { Ev, I1 }, 0 },
3346     { "sarQ",   { Ev, I1 }, 0 },
3347   },
3348   /* REG_D2 */
3349   {
3350     { "rolA",   { Eb, CL }, 0 },
3351     { "rorA",   { Eb, CL }, 0 },
3352     { "rclA",   { Eb, CL }, 0 },
3353     { "rcrA",   { Eb, CL }, 0 },
3354     { "shlA",   { Eb, CL }, 0 },
3355     { "shrA",   { Eb, CL }, 0 },
3356     { "shlA",   { Eb, CL }, 0 },
3357     { "sarA",   { Eb, CL }, 0 },
3358   },
3359   /* REG_D3 */
3360   {
3361     { "rolQ",   { Ev, CL }, 0 },
3362     { "rorQ",   { Ev, CL }, 0 },
3363     { "rclQ",   { Ev, CL }, 0 },
3364     { "rcrQ",   { Ev, CL }, 0 },
3365     { "shlQ",   { Ev, CL }, 0 },
3366     { "shrQ",   { Ev, CL }, 0 },
3367     { "shlQ",   { Ev, CL }, 0 },
3368     { "sarQ",   { Ev, CL }, 0 },
3369   },
3370   /* REG_F6 */
3371   {
3372     { "testA",  { Eb, Ib }, 0 },
3373     { "testA",  { Eb, Ib }, 0 },
3374     { "notA",   { Ebh1 }, 0 },
3375     { "negA",   { Ebh1 }, 0 },
3376     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3377     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3378     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3379     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3380   },
3381   /* REG_F7 */
3382   {
3383     { "testQ",  { Ev, Iv }, 0 },
3384     { "testQ",  { Ev, Iv }, 0 },
3385     { "notQ",   { Evh1 }, 0 },
3386     { "negQ",   { Evh1 }, 0 },
3387     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3388     { "imulQ",  { Ev }, 0 },
3389     { "divQ",   { Ev }, 0 },
3390     { "idivQ",  { Ev }, 0 },
3391   },
3392   /* REG_FE */
3393   {
3394     { "incA",   { Ebh1 }, 0 },
3395     { "decA",   { Ebh1 }, 0 },
3396   },
3397   /* REG_FF */
3398   {
3399     { "incQ",   { Evh1 }, 0 },
3400     { "decQ",   { Evh1 }, 0 },
3401     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3402     { MOD_TABLE (MOD_FF_REG_3) },
3403     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3404     { MOD_TABLE (MOD_FF_REG_5) },
3405     { "pushU",  { stackEv }, 0 },
3406     { Bad_Opcode },
3407   },
3408   /* REG_0F00 */
3409   {
3410     { "sldtD",  { Sv }, 0 },
3411     { "strD",   { Sv }, 0 },
3412     { "lldt",   { Ew }, 0 },
3413     { "ltr",    { Ew }, 0 },
3414     { "verr",   { Ew }, 0 },
3415     { "verw",   { Ew }, 0 },
3416     { Bad_Opcode },
3417     { Bad_Opcode },
3418   },
3419   /* REG_0F01 */
3420   {
3421     { MOD_TABLE (MOD_0F01_REG_0) },
3422     { MOD_TABLE (MOD_0F01_REG_1) },
3423     { MOD_TABLE (MOD_0F01_REG_2) },
3424     { MOD_TABLE (MOD_0F01_REG_3) },
3425     { "smswD",  { Sv }, 0 },
3426     { MOD_TABLE (MOD_0F01_REG_5) },
3427     { "lmsw",   { Ew }, 0 },
3428     { MOD_TABLE (MOD_0F01_REG_7) },
3429   },
3430   /* REG_0F0D */
3431   {
3432     { "prefetch",       { Mb }, 0 },
3433     { "prefetchw",      { Mb }, 0 },
3434     { "prefetchwt1",    { Mb }, 0 },
3435     { "prefetch",       { Mb }, 0 },
3436     { "prefetch",       { Mb }, 0 },
3437     { "prefetch",       { Mb }, 0 },
3438     { "prefetch",       { Mb }, 0 },
3439     { "prefetch",       { Mb }, 0 },
3440   },
3441   /* REG_0F18 */
3442   {
3443     { MOD_TABLE (MOD_0F18_REG_0) },
3444     { MOD_TABLE (MOD_0F18_REG_1) },
3445     { MOD_TABLE (MOD_0F18_REG_2) },
3446     { MOD_TABLE (MOD_0F18_REG_3) },
3447     { MOD_TABLE (MOD_0F18_REG_4) },
3448     { MOD_TABLE (MOD_0F18_REG_5) },
3449     { MOD_TABLE (MOD_0F18_REG_6) },
3450     { MOD_TABLE (MOD_0F18_REG_7) },
3451   },
3452   /* REG_0F1C_MOD_0 */
3453   {
3454     { "cldemote",       { Mb }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461     { "nopQ",           { Ev }, 0 },
3462   },
3463   /* REG_0F1E_MOD_3 */
3464   {
3465     { "nopQ",           { Ev }, 0 },
3466     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3467     { "nopQ",           { Ev }, 0 },
3468     { "nopQ",           { Ev }, 0 },
3469     { "nopQ",           { Ev }, 0 },
3470     { "nopQ",           { Ev }, 0 },
3471     { "nopQ",           { Ev }, 0 },
3472     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3473   },
3474   /* REG_0F71 */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_0F71_REG_2) },
3479     { Bad_Opcode },
3480     { MOD_TABLE (MOD_0F71_REG_4) },
3481     { Bad_Opcode },
3482     { MOD_TABLE (MOD_0F71_REG_6) },
3483   },
3484   /* REG_0F72 */
3485   {
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_0F72_REG_2) },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_0F72_REG_4) },
3491     { Bad_Opcode },
3492     { MOD_TABLE (MOD_0F72_REG_6) },
3493   },
3494   /* REG_0F73 */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { MOD_TABLE (MOD_0F73_REG_2) },
3499     { MOD_TABLE (MOD_0F73_REG_3) },
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { MOD_TABLE (MOD_0F73_REG_6) },
3503     { MOD_TABLE (MOD_0F73_REG_7) },
3504   },
3505   /* REG_0FA6 */
3506   {
3507     { "montmul",        { { OP_0f07, 0 } }, 0 },
3508     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3509     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3510   },
3511   /* REG_0FA7 */
3512   {
3513     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3514     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3515     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3516     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3517     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3518     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3519   },
3520   /* REG_0FAE */
3521   {
3522     { MOD_TABLE (MOD_0FAE_REG_0) },
3523     { MOD_TABLE (MOD_0FAE_REG_1) },
3524     { MOD_TABLE (MOD_0FAE_REG_2) },
3525     { MOD_TABLE (MOD_0FAE_REG_3) },
3526     { MOD_TABLE (MOD_0FAE_REG_4) },
3527     { MOD_TABLE (MOD_0FAE_REG_5) },
3528     { MOD_TABLE (MOD_0FAE_REG_6) },
3529     { MOD_TABLE (MOD_0FAE_REG_7) },
3530   },
3531   /* REG_0FBA */
3532   {
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { "btQ",    { Ev, Ib }, 0 },
3538     { "btsQ",   { Evh1, Ib }, 0 },
3539     { "btrQ",   { Evh1, Ib }, 0 },
3540     { "btcQ",   { Evh1, Ib }, 0 },
3541   },
3542   /* REG_0FC7 */
3543   {
3544     { Bad_Opcode },
3545     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_0FC7_REG_3) },
3548     { MOD_TABLE (MOD_0FC7_REG_4) },
3549     { MOD_TABLE (MOD_0FC7_REG_5) },
3550     { MOD_TABLE (MOD_0FC7_REG_6) },
3551     { MOD_TABLE (MOD_0FC7_REG_7) },
3552   },
3553   /* REG_VEX_0F71 */
3554   {
3555     { Bad_Opcode },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3558     { Bad_Opcode },
3559     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3560     { Bad_Opcode },
3561     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3562   },
3563   /* REG_VEX_0F72 */
3564   {
3565     { Bad_Opcode },
3566     { Bad_Opcode },
3567     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3568     { Bad_Opcode },
3569     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3570     { Bad_Opcode },
3571     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3572   },
3573   /* REG_VEX_0F73 */
3574   {
3575     { Bad_Opcode },
3576     { Bad_Opcode },
3577     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3578     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3579     { Bad_Opcode },
3580     { Bad_Opcode },
3581     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3582     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3583   },
3584   /* REG_VEX_0FAE */
3585   {
3586     { Bad_Opcode },
3587     { Bad_Opcode },
3588     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3589     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3590   },
3591   /* REG_VEX_0F38F3 */
3592   {
3593     { Bad_Opcode },
3594     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3595     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3596     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3597   },
3598   /* REG_XOP_LWPCB */
3599   {
3600     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3601     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3602   },
3603   /* REG_XOP_LWP */
3604   {
3605     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3606     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3607   },
3608   /* REG_XOP_TBM_01 */
3609   {
3610     { Bad_Opcode },
3611     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3612     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3613     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3614     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3615     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3616     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3617     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3618   },
3619   /* REG_XOP_TBM_02 */
3620   {
3621     { Bad_Opcode },
3622     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3623     { Bad_Opcode },
3624     { Bad_Opcode },
3625     { Bad_Opcode },
3626     { Bad_Opcode },
3627     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3628   },
3629
3630 #include "i386-dis-evex-reg.h"
3631 };
3632
3633 static const struct dis386 prefix_table[][4] = {
3634   /* PREFIX_90 */
3635   {
3636     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3637     { "pause", { XX }, 0 },
3638     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3639     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3640   },
3641
3642   /* PREFIX_MOD_0_0F01_REG_5 */
3643   {
3644     { Bad_Opcode },
3645     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3649   {
3650     { Bad_Opcode },
3651     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3655   {
3656     { Bad_Opcode },
3657     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3658   },
3659
3660   /* PREFIX_0F09 */
3661   {
3662     { "wbinvd",   { XX }, 0 },
3663     { "wbnoinvd", { XX }, 0 },
3664   },
3665
3666   /* PREFIX_0F10 */
3667   {
3668     { "movups", { XM, EXx }, PREFIX_OPCODE },
3669     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3670     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3671     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3672   },
3673
3674   /* PREFIX_0F11 */
3675   {
3676     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3677     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3678     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3679     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3680   },
3681
3682   /* PREFIX_0F12 */
3683   {
3684     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3685     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3686     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3687     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3688   },
3689
3690   /* PREFIX_0F16 */
3691   {
3692     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3693     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3694     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F1A */
3698   {
3699     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3700     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3701     { "bndmov", { Gbnd, Ebnd }, 0 },
3702     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3703   },
3704
3705   /* PREFIX_0F1B */
3706   {
3707     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3708     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3709     { "bndmov", { EbndS, Gbnd }, 0 },
3710     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3711   },
3712
3713   /* PREFIX_0F1C */
3714   {
3715     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3716     { "nopQ",   { Ev }, PREFIX_OPCODE },
3717     { "nopQ",   { Ev }, PREFIX_OPCODE },
3718     { "nopQ",   { Ev }, PREFIX_OPCODE },
3719   },
3720
3721   /* PREFIX_0F1E */
3722   {
3723     { "nopQ",   { Ev }, PREFIX_OPCODE },
3724     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3725     { "nopQ",   { Ev }, PREFIX_OPCODE },
3726     { "nopQ",   { Ev }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F2A */
3730   {
3731     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3732     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3733     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3734     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3735   },
3736
3737   /* PREFIX_0F2B */
3738   {
3739     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3741     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3742     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3743   },
3744
3745   /* PREFIX_0F2C */
3746   {
3747     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3748     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3749     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3750     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F2D */
3754   {
3755     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3756     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3757     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3758     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F2E */
3762   {
3763     { "ucomiss",{ XM, EXd }, 0 },
3764     { Bad_Opcode },
3765     { "ucomisd",{ XM, EXq }, 0 },
3766   },
3767
3768   /* PREFIX_0F2F */
3769   {
3770     { "comiss", { XM, EXd }, 0 },
3771     { Bad_Opcode },
3772     { "comisd", { XM, EXq }, 0 },
3773   },
3774
3775   /* PREFIX_0F51 */
3776   {
3777     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3778     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3779     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3780     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F52 */
3784   {
3785     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3786     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F53 */
3790   {
3791     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3792     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F58 */
3796   {
3797     { "addps", { XM, EXx }, PREFIX_OPCODE },
3798     { "addss", { XM, EXd }, PREFIX_OPCODE },
3799     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3800     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F59 */
3804   {
3805     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3806     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3807     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3808     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F5A */
3812   {
3813     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3814     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3815     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3816     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F5B */
3820   {
3821     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3823     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F5C */
3827   {
3828     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3829     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3830     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3831     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F5D */
3835   {
3836     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3837     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3838     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3839     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F5E */
3843   {
3844     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3845     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3846     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3847     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F5F */
3851   {
3852     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3853     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3854     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3855     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F60 */
3859   {
3860     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3861     { Bad_Opcode },
3862     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F61 */
3866   {
3867     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3868     { Bad_Opcode },
3869     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3870   },
3871
3872   /* PREFIX_0F62 */
3873   {
3874     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3875     { Bad_Opcode },
3876     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F6C */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F6D */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3891   },
3892
3893   /* PREFIX_0F6F */
3894   {
3895     { "movq",   { MX, EM }, PREFIX_OPCODE },
3896     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3897     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F70 */
3901   {
3902     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3903     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3905     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F73_REG_3 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "psrldq", { XS, Ib }, 0 },
3913   },
3914
3915   /* PREFIX_0F73_REG_7 */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "pslldq", { XS, Ib }, 0 },
3920   },
3921
3922   /* PREFIX_0F78 */
3923   {
3924     {"vmread",  { Em, Gm }, 0 },
3925     { Bad_Opcode },
3926     {"extrq",   { XS, Ib, Ib }, 0 },
3927     {"insertq", { XM, XS, Ib, Ib }, 0 },
3928   },
3929
3930   /* PREFIX_0F79 */
3931   {
3932     {"vmwrite", { Gm, Em }, 0 },
3933     { Bad_Opcode },
3934     {"extrq",   { XM, XS }, 0 },
3935     {"insertq", { XM, XS }, 0 },
3936   },
3937
3938   /* PREFIX_0F7C */
3939   {
3940     { Bad_Opcode },
3941     { Bad_Opcode },
3942     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3943     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0F7D */
3947   {
3948     { Bad_Opcode },
3949     { Bad_Opcode },
3950     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3951     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0F7E */
3955   {
3956     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3957     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3958     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3959   },
3960
3961   /* PREFIX_0F7F */
3962   {
3963     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3964     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3965     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3966   },
3967
3968   /* PREFIX_0FAE_REG_0 */
3969   {
3970     { Bad_Opcode },
3971     { "rdfsbase", { Ev }, 0 },
3972   },
3973
3974   /* PREFIX_0FAE_REG_1 */
3975   {
3976     { Bad_Opcode },
3977     { "rdgsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_2 */
3981   {
3982     { Bad_Opcode },
3983     { "wrfsbase", { Ev }, 0 },
3984   },
3985
3986   /* PREFIX_0FAE_REG_3 */
3987   {
3988     { Bad_Opcode },
3989     { "wrgsbase", { Ev }, 0 },
3990   },
3991
3992   /* PREFIX_MOD_0_0FAE_REG_4 */
3993   {
3994     { "xsave",  { FXSAVE }, 0 },
3995     { "ptwrite%LQ", { Edq }, 0 },
3996   },
3997
3998   /* PREFIX_MOD_3_0FAE_REG_4 */
3999   {
4000     { Bad_Opcode },
4001     { "ptwrite%LQ", { Edq }, 0 },
4002   },
4003
4004   /* PREFIX_MOD_0_0FAE_REG_5 */
4005   {
4006     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4007   },
4008
4009   /* PREFIX_MOD_3_0FAE_REG_5 */
4010   {
4011     { "lfence",         { Skip_MODRM }, 0 },
4012     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_MOD_0_0FAE_REG_6 */
4016   {
4017     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4018     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4019     { "clwb",   { Mb }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_MOD_1_0FAE_REG_6 */
4023   {
4024     { RM_TABLE (RM_0FAE_REG_6) },
4025     { "umonitor",       { Eva }, PREFIX_OPCODE },
4026     { "tpause", { Edq }, PREFIX_OPCODE },
4027     { "umwait", { Edq }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0FAE_REG_7 */
4031   {
4032     { "clflush",        { Mb }, 0 },
4033     { Bad_Opcode },
4034     { "clflushopt",     { Mb }, 0 },
4035   },
4036
4037   /* PREFIX_0FB8 */
4038   {
4039     { Bad_Opcode },
4040     { "popcntS", { Gv, Ev }, 0 },
4041   },
4042
4043   /* PREFIX_0FBC */
4044   {
4045     { "bsfS",   { Gv, Ev }, 0 },
4046     { "tzcntS", { Gv, Ev }, 0 },
4047     { "bsfS",   { Gv, Ev }, 0 },
4048   },
4049
4050   /* PREFIX_0FBD */
4051   {
4052     { "bsrS",   { Gv, Ev }, 0 },
4053     { "lzcntS", { Gv, Ev }, 0 },
4054     { "bsrS",   { Gv, Ev }, 0 },
4055   },
4056
4057   /* PREFIX_0FC2 */
4058   {
4059     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4060     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4061     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4062     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4063   },
4064
4065   /* PREFIX_MOD_0_0FC3 */
4066   {
4067     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4068   },
4069
4070   /* PREFIX_MOD_0_0FC7_REG_6 */
4071   {
4072     { "vmptrld",{ Mq }, 0 },
4073     { "vmxon",  { Mq }, 0 },
4074     { "vmclear",{ Mq }, 0 },
4075   },
4076
4077   /* PREFIX_MOD_3_0FC7_REG_6 */
4078   {
4079     { "rdrand", { Ev }, 0 },
4080     { Bad_Opcode },
4081     { "rdrand", { Ev }, 0 }
4082   },
4083
4084   /* PREFIX_MOD_3_0FC7_REG_7 */
4085   {
4086     { "rdseed", { Ev }, 0 },
4087     { "rdpid",  { Em }, 0 },
4088     { "rdseed", { Ev }, 0 },
4089   },
4090
4091   /* PREFIX_0FD0 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "addsubpd", { XM, EXx }, 0 },
4096     { "addsubps", { XM, EXx }, 0 },
4097   },
4098
4099   /* PREFIX_0FD6 */
4100   {
4101     { Bad_Opcode },
4102     { "movq2dq",{ XM, MS }, 0 },
4103     { "movq",   { EXqS, XM }, 0 },
4104     { "movdq2q",{ MX, XS }, 0 },
4105   },
4106
4107   /* PREFIX_0FE6 */
4108   {
4109     { Bad_Opcode },
4110     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4111     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4112     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0FE7 */
4116   {
4117     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4118     { Bad_Opcode },
4119     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4120   },
4121
4122   /* PREFIX_0FF0 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4128   },
4129
4130   /* PREFIX_0FF7 */
4131   {
4132     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4133     { Bad_Opcode },
4134     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F3810 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0F3814 */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0F3815 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4156   },
4157
4158   /* PREFIX_0F3817 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4163   },
4164
4165   /* PREFIX_0F3820 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4170   },
4171
4172   /* PREFIX_0F3821 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4177   },
4178
4179   /* PREFIX_0F3822 */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_0F3823 */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4191   },
4192
4193   /* PREFIX_0F3824 */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4198   },
4199
4200   /* PREFIX_0F3825 */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4205   },
4206
4207   /* PREFIX_0F3828 */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4212   },
4213
4214   /* PREFIX_0F3829 */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4219   },
4220
4221   /* PREFIX_0F382A */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4226   },
4227
4228   /* PREFIX_0F382B */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0F3830 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4240   },
4241
4242   /* PREFIX_0F3831 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F3832 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4254   },
4255
4256   /* PREFIX_0F3833 */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4261   },
4262
4263   /* PREFIX_0F3834 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4268   },
4269
4270   /* PREFIX_0F3835 */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4275   },
4276
4277   /* PREFIX_0F3837 */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4282   },
4283
4284   /* PREFIX_0F3838 */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4289   },
4290
4291   /* PREFIX_0F3839 */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F383A */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F383B */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F383C */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F383D */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F383E */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F383F */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3840 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3841 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3880 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F3881 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F3882 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38C8 */
4376   {
4377     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38C9 */
4381   {
4382     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F38CA */
4386   {
4387     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38CB */
4391   {
4392     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38CC */
4396   {
4397     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F38CD */
4401   {
4402     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F38CF */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F38DB */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F38DC */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F38DD */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38DE */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F38DF */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F38F0 */
4448   {
4449     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4450     { Bad_Opcode },
4451     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4452     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F38F1 */
4456   {
4457     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4458     { Bad_Opcode },
4459     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4460     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F38F5 */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4468   },
4469
4470   /* PREFIX_0F38F6 */
4471   {
4472     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4473     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4474     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4475     { Bad_Opcode },
4476   },
4477
4478   /* PREFIX_0F38F8 */
4479   {
4480     { Bad_Opcode },
4481     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4482     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4483     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4484   },
4485
4486   /* PREFIX_0F38F9 */
4487   {
4488     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4489   },
4490
4491   /* PREFIX_0F3A08 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F3A09 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F3A0A */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3A0B */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A0C */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3A0D */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A0E */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A14 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A15 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A16 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A17 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A20 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A21 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A22 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A40 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A41 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3A42 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3A44 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_0F3A60 */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F3A61 */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F3A62 */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F3A63 */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F3ACC */
4646   {
4647     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3ACE */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3ACF */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3ADF */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_VEX_0F10 */
4672   {
4673     { "vmovups",        { XM, EXx }, 0 },
4674     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4675     { "vmovupd",        { XM, EXx }, 0 },
4676     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4677   },
4678
4679   /* PREFIX_VEX_0F11 */
4680   {
4681     { "vmovups",        { EXxS, XM }, 0 },
4682     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4683     { "vmovupd",        { EXxS, XM }, 0 },
4684     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4685   },
4686
4687   /* PREFIX_VEX_0F12 */
4688   {
4689     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4690     { "vmovsldup",      { XM, EXx }, 0 },
4691     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4692     { "vmovddup",       { XM, EXymmq }, 0 },
4693   },
4694
4695   /* PREFIX_VEX_0F16 */
4696   {
4697     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4698     { "vmovshdup",      { XM, EXx }, 0 },
4699     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4700   },
4701
4702   /* PREFIX_VEX_0F2A */
4703   {
4704     { Bad_Opcode },
4705     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4706     { Bad_Opcode },
4707     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4708   },
4709
4710   /* PREFIX_VEX_0F2C */
4711   {
4712     { Bad_Opcode },
4713     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4714     { Bad_Opcode },
4715     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4716   },
4717
4718   /* PREFIX_VEX_0F2D */
4719   {
4720     { Bad_Opcode },
4721     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4722     { Bad_Opcode },
4723     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4724   },
4725
4726   /* PREFIX_VEX_0F2E */
4727   {
4728     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4729     { Bad_Opcode },
4730     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4731   },
4732
4733   /* PREFIX_VEX_0F2F */
4734   {
4735     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4736     { Bad_Opcode },
4737     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4738   },
4739
4740   /* PREFIX_VEX_0F41 */
4741   {
4742     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F42 */
4748   {
4749     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F44 */
4755   {
4756     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F45 */
4762   {
4763     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F46 */
4769   {
4770     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4771     { Bad_Opcode },
4772     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F47 */
4776   {
4777     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4778     { Bad_Opcode },
4779     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F4A */
4783   {
4784     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4785     { Bad_Opcode },
4786     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F4B */
4790   {
4791     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4792     { Bad_Opcode },
4793     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4794   },
4795
4796   /* PREFIX_VEX_0F51 */
4797   {
4798     { "vsqrtps",        { XM, EXx }, 0 },
4799     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4800     { "vsqrtpd",        { XM, EXx }, 0 },
4801     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F52 */
4805   {
4806     { "vrsqrtps",       { XM, EXx }, 0 },
4807     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F53 */
4811   {
4812     { "vrcpps",         { XM, EXx }, 0 },
4813     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4814   },
4815
4816   /* PREFIX_VEX_0F58 */
4817   {
4818     { "vaddps",         { XM, Vex, EXx }, 0 },
4819     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4820     { "vaddpd",         { XM, Vex, EXx }, 0 },
4821     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4822   },
4823
4824   /* PREFIX_VEX_0F59 */
4825   {
4826     { "vmulps",         { XM, Vex, EXx }, 0 },
4827     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4828     { "vmulpd",         { XM, Vex, EXx }, 0 },
4829     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4830   },
4831
4832   /* PREFIX_VEX_0F5A */
4833   {
4834     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4835     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4836     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4837     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4838   },
4839
4840   /* PREFIX_VEX_0F5B */
4841   {
4842     { "vcvtdq2ps",      { XM, EXx }, 0 },
4843     { "vcvttps2dq",     { XM, EXx }, 0 },
4844     { "vcvtps2dq",      { XM, EXx }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F5C */
4848   {
4849     { "vsubps",         { XM, Vex, EXx }, 0 },
4850     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4851     { "vsubpd",         { XM, Vex, EXx }, 0 },
4852     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F5D */
4856   {
4857     { "vminps",         { XM, Vex, EXx }, 0 },
4858     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4859     { "vminpd",         { XM, Vex, EXx }, 0 },
4860     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F5E */
4864   {
4865     { "vdivps",         { XM, Vex, EXx }, 0 },
4866     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4867     { "vdivpd",         { XM, Vex, EXx }, 0 },
4868     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F5F */
4872   {
4873     { "vmaxps",         { XM, Vex, EXx }, 0 },
4874     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4875     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4876     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F60 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4884   },
4885
4886   /* PREFIX_VEX_0F61 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4891   },
4892
4893   /* PREFIX_VEX_0F62 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4898   },
4899
4900   /* PREFIX_VEX_0F63 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4905   },
4906
4907   /* PREFIX_VEX_0F64 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4912   },
4913
4914   /* PREFIX_VEX_0F65 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4919   },
4920
4921   /* PREFIX_VEX_0F66 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4926   },
4927
4928   /* PREFIX_VEX_0F67 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4933   },
4934
4935   /* PREFIX_VEX_0F68 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4940   },
4941
4942   /* PREFIX_VEX_0F69 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4947   },
4948
4949   /* PREFIX_VEX_0F6A */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F6B */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F6C */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F6D */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F6E */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F6F */
4985   {
4986     { Bad_Opcode },
4987     { "vmovdqu",        { XM, EXx }, 0 },
4988     { "vmovdqa",        { XM, EXx }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F70 */
4992   {
4993     { Bad_Opcode },
4994     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4995     { "vpshufd",        { XM, EXx, Ib }, 0 },
4996     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4997   },
4998
4999   /* PREFIX_VEX_0F71_REG_2 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5004   },
5005
5006   /* PREFIX_VEX_0F71_REG_4 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { "vpsraw",         { Vex, XS, Ib }, 0 },
5011   },
5012
5013   /* PREFIX_VEX_0F71_REG_6 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { "vpsllw",         { Vex, XS, Ib }, 0 },
5018   },
5019
5020   /* PREFIX_VEX_0F72_REG_2 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { "vpsrld",         { Vex, XS, Ib }, 0 },
5025   },
5026
5027   /* PREFIX_VEX_0F72_REG_4 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { "vpsrad",         { Vex, XS, Ib }, 0 },
5032   },
5033
5034   /* PREFIX_VEX_0F72_REG_6 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { "vpslld",         { Vex, XS, Ib }, 0 },
5039   },
5040
5041   /* PREFIX_VEX_0F73_REG_2 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5046   },
5047
5048   /* PREFIX_VEX_0F73_REG_3 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5053   },
5054
5055   /* PREFIX_VEX_0F73_REG_6 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { "vpsllq",         { Vex, XS, Ib }, 0 },
5060   },
5061
5062   /* PREFIX_VEX_0F73_REG_7 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { "vpslldq",        { Vex, XS, Ib }, 0 },
5067   },
5068
5069   /* PREFIX_VEX_0F74 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5074   },
5075
5076   /* PREFIX_VEX_0F75 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5081   },
5082
5083   /* PREFIX_VEX_0F76 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5088   },
5089
5090   /* PREFIX_VEX_0F77 */
5091   {
5092     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5093   },
5094
5095   /* PREFIX_VEX_0F7C */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5100     { "vhaddps",        { XM, Vex, EXx }, 0 },
5101   },
5102
5103   /* PREFIX_VEX_0F7D */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5108     { "vhsubps",        { XM, Vex, EXx }, 0 },
5109   },
5110
5111   /* PREFIX_VEX_0F7E */
5112   {
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5115     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F7F */
5119   {
5120     { Bad_Opcode },
5121     { "vmovdqu",        { EXxS, XM }, 0 },
5122     { "vmovdqa",        { EXxS, XM }, 0 },
5123   },
5124
5125   /* PREFIX_VEX_0F90 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F91 */
5133   {
5134     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F92 */
5140   {
5141     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5144     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5145   },
5146
5147   /* PREFIX_VEX_0F93 */
5148   {
5149     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5152     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5153   },
5154
5155   /* PREFIX_VEX_0F98 */
5156   {
5157     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5158     { Bad_Opcode },
5159     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0F99 */
5163   {
5164     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5165     { Bad_Opcode },
5166     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0FC2 */
5170   {
5171     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5172     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5173     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5174     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FC4 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0FC5 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FD0 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5196     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5197   },
5198
5199   /* PREFIX_VEX_0FD1 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5204   },
5205
5206   /* PREFIX_VEX_0FD2 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5211   },
5212
5213   /* PREFIX_VEX_0FD3 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5218   },
5219
5220   /* PREFIX_VEX_0FD4 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { "vpaddq",         { XM, Vex, EXx }, 0 },
5225   },
5226
5227   /* PREFIX_VEX_0FD5 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { "vpmullw",        { XM, Vex, EXx }, 0 },
5232   },
5233
5234   /* PREFIX_VEX_0FD6 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0FD7 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5246   },
5247
5248   /* PREFIX_VEX_0FD8 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5253   },
5254
5255   /* PREFIX_VEX_0FD9 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5260   },
5261
5262   /* PREFIX_VEX_0FDA */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { "vpminub",        { XM, Vex, EXx }, 0 },
5267   },
5268
5269   /* PREFIX_VEX_0FDB */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { "vpand",          { XM, Vex, EXx }, 0 },
5274   },
5275
5276   /* PREFIX_VEX_0FDC */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5281   },
5282
5283   /* PREFIX_VEX_0FDD */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5288   },
5289
5290   /* PREFIX_VEX_0FDE */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5295   },
5296
5297   /* PREFIX_VEX_0FDF */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { "vpandn",         { XM, Vex, EXx }, 0 },
5302   },
5303
5304   /* PREFIX_VEX_0FE0 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { "vpavgb",         { XM, Vex, EXx }, 0 },
5309   },
5310
5311   /* PREFIX_VEX_0FE1 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5316   },
5317
5318   /* PREFIX_VEX_0FE2 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5323   },
5324
5325   /* PREFIX_VEX_0FE3 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpavgw",         { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FE4 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5337   },
5338
5339   /* PREFIX_VEX_0FE5 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FE6 */
5347   {
5348     { Bad_Opcode },
5349     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5350     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5351     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FE7 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FE8 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5366   },
5367
5368   /* PREFIX_VEX_0FE9 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5373   },
5374
5375   /* PREFIX_VEX_0FEA */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vpminsw",        { XM, Vex, EXx }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0FEB */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vpor",           { XM, Vex, EXx }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0FEC */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FED */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FEE */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FEF */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpxor",          { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF0 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5423   },
5424
5425   /* PREFIX_VEX_0FF1 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5430   },
5431
5432   /* PREFIX_VEX_0FF2 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5437   },
5438
5439   /* PREFIX_VEX_0FF3 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5444   },
5445
5446   /* PREFIX_VEX_0FF4 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5451   },
5452
5453   /* PREFIX_VEX_0FF5 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5458   },
5459
5460   /* PREFIX_VEX_0FF6 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5465   },
5466
5467   /* PREFIX_VEX_0FF7 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0FF8 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { "vpsubb",         { XM, Vex, EXx }, 0 },
5479   },
5480
5481   /* PREFIX_VEX_0FF9 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { "vpsubw",         { XM, Vex, EXx }, 0 },
5486   },
5487
5488   /* PREFIX_VEX_0FFA */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { "vpsubd",         { XM, Vex, EXx }, 0 },
5493   },
5494
5495   /* PREFIX_VEX_0FFB */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { "vpsubq",         { XM, Vex, EXx }, 0 },
5500   },
5501
5502   /* PREFIX_VEX_0FFC */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { "vpaddb",         { XM, Vex, EXx }, 0 },
5507   },
5508
5509   /* PREFIX_VEX_0FFD */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { "vpaddw",         { XM, Vex, EXx }, 0 },
5514   },
5515
5516   /* PREFIX_VEX_0FFE */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { "vpaddd",         { XM, Vex, EXx }, 0 },
5521   },
5522
5523   /* PREFIX_VEX_0F3800 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { "vpshufb",        { XM, Vex, EXx }, 0 },
5528   },
5529
5530   /* PREFIX_VEX_0F3801 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { "vphaddw",        { XM, Vex, EXx }, 0 },
5535   },
5536
5537   /* PREFIX_VEX_0F3802 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { "vphaddd",        { XM, Vex, EXx }, 0 },
5542   },
5543
5544   /* PREFIX_VEX_0F3803 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5549   },
5550
5551   /* PREFIX_VEX_0F3804 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5556   },
5557
5558   /* PREFIX_VEX_0F3805 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { "vphsubw",        { XM, Vex, EXx }, 0 },
5563   },
5564
5565   /* PREFIX_VEX_0F3806 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { "vphsubd",        { XM, Vex, EXx }, 0 },
5570   },
5571
5572   /* PREFIX_VEX_0F3807 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5577   },
5578
5579   /* PREFIX_VEX_0F3808 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { "vpsignb",        { XM, Vex, EXx }, 0 },
5584   },
5585
5586   /* PREFIX_VEX_0F3809 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { "vpsignw",        { XM, Vex, EXx }, 0 },
5591   },
5592
5593   /* PREFIX_VEX_0F380A */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { "vpsignd",        { XM, Vex, EXx }, 0 },
5598   },
5599
5600   /* PREFIX_VEX_0F380B */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5605   },
5606
5607   /* PREFIX_VEX_0F380C */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F380D */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F380E */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F380F */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F3813 */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5640   },
5641
5642   /* PREFIX_VEX_0F3816 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5647   },
5648
5649   /* PREFIX_VEX_0F3817 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { "vptest",         { XM, EXx }, 0 },
5654   },
5655
5656   /* PREFIX_VEX_0F3818 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F3819 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F381A */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F381C */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { "vpabsb",         { XM, EXx }, 0 },
5682   },
5683
5684   /* PREFIX_VEX_0F381D */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { "vpabsw",         { XM, EXx }, 0 },
5689   },
5690
5691   /* PREFIX_VEX_0F381E */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { "vpabsd",         { XM, EXx }, 0 },
5696   },
5697
5698   /* PREFIX_VEX_0F3820 */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5703   },
5704
5705   /* PREFIX_VEX_0F3821 */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5710   },
5711
5712   /* PREFIX_VEX_0F3822 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5717   },
5718
5719   /* PREFIX_VEX_0F3823 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5724   },
5725
5726   /* PREFIX_VEX_0F3824 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5731   },
5732
5733   /* PREFIX_VEX_0F3825 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5738   },
5739
5740   /* PREFIX_VEX_0F3828 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5745   },
5746
5747   /* PREFIX_VEX_0F3829 */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5752   },
5753
5754   /* PREFIX_VEX_0F382A */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F382B */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5766   },
5767
5768   /* PREFIX_VEX_0F382C */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F382D */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F382E */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5787   },
5788
5789   /* PREFIX_VEX_0F382F */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5794   },
5795
5796   /* PREFIX_VEX_0F3830 */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5801   },
5802
5803   /* PREFIX_VEX_0F3831 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5808   },
5809
5810   /* PREFIX_VEX_0F3832 */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5815   },
5816
5817   /* PREFIX_VEX_0F3833 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5822   },
5823
5824   /* PREFIX_VEX_0F3834 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5829   },
5830
5831   /* PREFIX_VEX_0F3835 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5836   },
5837
5838   /* PREFIX_VEX_0F3836 */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5843   },
5844
5845   /* PREFIX_VEX_0F3837 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5850   },
5851
5852   /* PREFIX_VEX_0F3838 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { "vpminsb",        { XM, Vex, EXx }, 0 },
5857   },
5858
5859   /* PREFIX_VEX_0F3839 */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { "vpminsd",        { XM, Vex, EXx }, 0 },
5864   },
5865
5866   /* PREFIX_VEX_0F383A */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { "vpminuw",        { XM, Vex, EXx }, 0 },
5871   },
5872
5873   /* PREFIX_VEX_0F383B */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { "vpminud",        { XM, Vex, EXx }, 0 },
5878   },
5879
5880   /* PREFIX_VEX_0F383C */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5885   },
5886
5887   /* PREFIX_VEX_0F383D */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5892   },
5893
5894   /* PREFIX_VEX_0F383E */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5899   },
5900
5901   /* PREFIX_VEX_0F383F */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5906   },
5907
5908   /* PREFIX_VEX_0F3840 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { "vpmulld",        { XM, Vex, EXx }, 0 },
5913   },
5914
5915   /* PREFIX_VEX_0F3841 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F3845 */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5927   },
5928
5929   /* PREFIX_VEX_0F3846 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5934   },
5935
5936   /* PREFIX_VEX_0F3847 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5941   },
5942
5943   /* PREFIX_VEX_0F3858 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5948   },
5949
5950   /* PREFIX_VEX_0F3859 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F385A */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5962   },
5963
5964   /* PREFIX_VEX_0F3878 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F3879 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F388C */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F388E */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F3890 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F3891 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3892 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F3893 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3896 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3897 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F3898 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F3899 */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F389A */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F389B */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F389C */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389D */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F389E */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F389F */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38A6 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6095     { Bad_Opcode },
6096   },
6097
6098   /* PREFIX_VEX_0F38A7 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38A8 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38A9 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38AA */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38AB */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38AC */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AD */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38AE */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38AF */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38B6 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38B7 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38B8 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38B9 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38BA */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38BB */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38BC */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BD */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38BE */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38BF */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F38CF */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6236   },
6237
6238   /* PREFIX_VEX_0F38DB */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6243   },
6244
6245   /* PREFIX_VEX_0F38DC */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vaesenc",        { XM, Vex, EXx }, 0 },
6250   },
6251
6252   /* PREFIX_VEX_0F38DD */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6257   },
6258
6259   /* PREFIX_VEX_0F38DE */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { "vaesdec",        { XM, Vex, EXx }, 0 },
6264   },
6265
6266   /* PREFIX_VEX_0F38DF */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6271   },
6272
6273   /* PREFIX_VEX_0F38F2 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6276   },
6277
6278   /* PREFIX_VEX_0F38F3_REG_1 */
6279   {
6280     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6281   },
6282
6283   /* PREFIX_VEX_0F38F3_REG_2 */
6284   {
6285     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6286   },
6287
6288   /* PREFIX_VEX_0F38F3_REG_3 */
6289   {
6290     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6291   },
6292
6293   /* PREFIX_VEX_0F38F5 */
6294   {
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6297     { Bad_Opcode },
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6299   },
6300
6301   /* PREFIX_VEX_0F38F6 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6307   },
6308
6309   /* PREFIX_VEX_0F38F7 */
6310   {
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A00 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A01 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A02 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A04 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A05 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A06 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A08 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { "vroundps",       { XM, EXx, Ib }, 0 },
6364   },
6365
6366   /* PREFIX_VEX_0F3A09 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vroundpd",       { XM, EXx, Ib }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F3A0A */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F3A0B */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0C */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0D */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F3A0E */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6406   },
6407
6408   /* PREFIX_VEX_0F3A0F */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6413   },
6414
6415   /* PREFIX_VEX_0F3A14 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A15 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A16 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A17 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A18 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A19 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A1D */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6462   },
6463
6464   /* PREFIX_VEX_0F3A20 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A21 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A22 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A30 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A31 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A32 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A33 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A38 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A39 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A40 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6532   },
6533
6534   /* PREFIX_VEX_0F3A41 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A42 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6546   },
6547
6548   /* PREFIX_VEX_0F3A44 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6553   },
6554
6555   /* PREFIX_VEX_0F3A46 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A48 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A49 */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A4A */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A4B */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A4C */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A5C */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6602   },
6603
6604   /* PREFIX_VEX_0F3A5D */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6609   },
6610
6611   /* PREFIX_VEX_0F3A5E */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A5F */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A60 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6630     { Bad_Opcode },
6631   },
6632
6633   /* PREFIX_VEX_0F3A61 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A62 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A63 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A68 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6659   },
6660
6661   /* PREFIX_VEX_0F3A69 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6666   },
6667
6668   /* PREFIX_VEX_0F3A6A */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A6B */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6C */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6D */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6694   },
6695
6696   /* PREFIX_VEX_0F3A6E */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A6F */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6708   },
6709
6710   /* PREFIX_VEX_0F3A78 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A79 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7A */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7B */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7C */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6743     { Bad_Opcode },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7D */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6751   },
6752
6753   /* PREFIX_VEX_0F3A7E */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6758   },
6759
6760   /* PREFIX_VEX_0F3A7F */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6765   },
6766
6767   /* PREFIX_VEX_0F3ACE */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3ACF */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3ADF */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3AF0 */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6794   },
6795
6796 #include "i386-dis-evex-prefix.h"
6797 };
6798
6799 static const struct dis386 x86_64_table[][2] = {
6800   /* X86_64_06 */
6801   {
6802     { "pushP", { es }, 0 },
6803   },
6804
6805   /* X86_64_07 */
6806   {
6807     { "popP", { es }, 0 },
6808   },
6809
6810   /* X86_64_0D */
6811   {
6812     { "pushP", { cs }, 0 },
6813   },
6814
6815   /* X86_64_16 */
6816   {
6817     { "pushP", { ss }, 0 },
6818   },
6819
6820   /* X86_64_17 */
6821   {
6822     { "popP", { ss }, 0 },
6823   },
6824
6825   /* X86_64_1E */
6826   {
6827     { "pushP", { ds }, 0 },
6828   },
6829
6830   /* X86_64_1F */
6831   {
6832     { "popP", { ds }, 0 },
6833   },
6834
6835   /* X86_64_27 */
6836   {
6837     { "daa", { XX }, 0 },
6838   },
6839
6840   /* X86_64_2F */
6841   {
6842     { "das", { XX }, 0 },
6843   },
6844
6845   /* X86_64_37 */
6846   {
6847     { "aaa", { XX }, 0 },
6848   },
6849
6850   /* X86_64_3F */
6851   {
6852     { "aas", { XX }, 0 },
6853   },
6854
6855   /* X86_64_60 */
6856   {
6857     { "pushaP", { XX }, 0 },
6858   },
6859
6860   /* X86_64_61 */
6861   {
6862     { "popaP", { XX }, 0 },
6863   },
6864
6865   /* X86_64_62 */
6866   {
6867     { MOD_TABLE (MOD_62_32BIT) },
6868     { EVEX_TABLE (EVEX_0F) },
6869   },
6870
6871   /* X86_64_63 */
6872   {
6873     { "arpl", { Ew, Gw }, 0 },
6874     { "movs{lq|xd}", { Gv, Ed }, 0 },
6875   },
6876
6877   /* X86_64_6D */
6878   {
6879     { "ins{R|}", { Yzr, indirDX }, 0 },
6880     { "ins{G|}", { Yzr, indirDX }, 0 },
6881   },
6882
6883   /* X86_64_6F */
6884   {
6885     { "outs{R|}", { indirDXr, Xz }, 0 },
6886     { "outs{G|}", { indirDXr, Xz }, 0 },
6887   },
6888
6889   /* X86_64_82 */
6890   {
6891     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6892     { REG_TABLE (REG_80) },
6893   },
6894
6895   /* X86_64_9A */
6896   {
6897     { "Jcall{T|}", { Ap }, 0 },
6898   },
6899
6900   /* X86_64_C4 */
6901   {
6902     { MOD_TABLE (MOD_C4_32BIT) },
6903     { VEX_C4_TABLE (VEX_0F) },
6904   },
6905
6906   /* X86_64_C5 */
6907   {
6908     { MOD_TABLE (MOD_C5_32BIT) },
6909     { VEX_C5_TABLE (VEX_0F) },
6910   },
6911
6912   /* X86_64_CE */
6913   {
6914     { "into", { XX }, 0 },
6915   },
6916
6917   /* X86_64_D4 */
6918   {
6919     { "aam", { Ib }, 0 },
6920   },
6921
6922   /* X86_64_D5 */
6923   {
6924     { "aad", { Ib }, 0 },
6925   },
6926
6927   /* X86_64_E8 */
6928   {
6929     { "callP",          { Jv, BND }, 0 },
6930     { "call@",          { Jv, BND }, 0 }
6931   },
6932
6933   /* X86_64_E9 */
6934   {
6935     { "jmpP",           { Jv, BND }, 0 },
6936     { "jmp@",           { Jv, BND }, 0 }
6937   },
6938
6939   /* X86_64_EA */
6940   {
6941     { "Jjmp{T|}", { Ap }, 0 },
6942   },
6943
6944   /* X86_64_0F01_REG_0 */
6945   {
6946     { "sgdt{Q|IQ}", { M }, 0 },
6947     { "sgdt", { M }, 0 },
6948   },
6949
6950   /* X86_64_0F01_REG_1 */
6951   {
6952     { "sidt{Q|IQ}", { M }, 0 },
6953     { "sidt", { M }, 0 },
6954   },
6955
6956   /* X86_64_0F01_REG_2 */
6957   {
6958     { "lgdt{Q|Q}", { M }, 0 },
6959     { "lgdt", { M }, 0 },
6960   },
6961
6962   /* X86_64_0F01_REG_3 */
6963   {
6964     { "lidt{Q|Q}", { M }, 0 },
6965     { "lidt", { M }, 0 },
6966   },
6967 };
6968
6969 static const struct dis386 three_byte_table[][256] = {
6970
6971   /* THREE_BYTE_0F38 */
6972   {
6973     /* 00 */
6974     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6975     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6976     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6978     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6979     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6980     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6981     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6982     /* 08 */
6983     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6984     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6985     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6986     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* 10 */
6992     { PREFIX_TABLE (PREFIX_0F3810) },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { PREFIX_TABLE (PREFIX_0F3814) },
6997     { PREFIX_TABLE (PREFIX_0F3815) },
6998     { Bad_Opcode },
6999     { PREFIX_TABLE (PREFIX_0F3817) },
7000     /* 18 */
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7006     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7007     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7008     { Bad_Opcode },
7009     /* 20 */
7010     { PREFIX_TABLE (PREFIX_0F3820) },
7011     { PREFIX_TABLE (PREFIX_0F3821) },
7012     { PREFIX_TABLE (PREFIX_0F3822) },
7013     { PREFIX_TABLE (PREFIX_0F3823) },
7014     { PREFIX_TABLE (PREFIX_0F3824) },
7015     { PREFIX_TABLE (PREFIX_0F3825) },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* 28 */
7019     { PREFIX_TABLE (PREFIX_0F3828) },
7020     { PREFIX_TABLE (PREFIX_0F3829) },
7021     { PREFIX_TABLE (PREFIX_0F382A) },
7022     { PREFIX_TABLE (PREFIX_0F382B) },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 30 */
7028     { PREFIX_TABLE (PREFIX_0F3830) },
7029     { PREFIX_TABLE (PREFIX_0F3831) },
7030     { PREFIX_TABLE (PREFIX_0F3832) },
7031     { PREFIX_TABLE (PREFIX_0F3833) },
7032     { PREFIX_TABLE (PREFIX_0F3834) },
7033     { PREFIX_TABLE (PREFIX_0F3835) },
7034     { Bad_Opcode },
7035     { PREFIX_TABLE (PREFIX_0F3837) },
7036     /* 38 */
7037     { PREFIX_TABLE (PREFIX_0F3838) },
7038     { PREFIX_TABLE (PREFIX_0F3839) },
7039     { PREFIX_TABLE (PREFIX_0F383A) },
7040     { PREFIX_TABLE (PREFIX_0F383B) },
7041     { PREFIX_TABLE (PREFIX_0F383C) },
7042     { PREFIX_TABLE (PREFIX_0F383D) },
7043     { PREFIX_TABLE (PREFIX_0F383E) },
7044     { PREFIX_TABLE (PREFIX_0F383F) },
7045     /* 40 */
7046     { PREFIX_TABLE (PREFIX_0F3840) },
7047     { PREFIX_TABLE (PREFIX_0F3841) },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 48 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 50 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 58 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 60 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* 68 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 70 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* 78 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* 80 */
7118     { PREFIX_TABLE (PREFIX_0F3880) },
7119     { PREFIX_TABLE (PREFIX_0F3881) },
7120     { PREFIX_TABLE (PREFIX_0F3882) },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* 88 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* 90 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 98 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* a0 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* a8 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* b0 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* b8 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* c0 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* c8 */
7199     { PREFIX_TABLE (PREFIX_0F38C8) },
7200     { PREFIX_TABLE (PREFIX_0F38C9) },
7201     { PREFIX_TABLE (PREFIX_0F38CA) },
7202     { PREFIX_TABLE (PREFIX_0F38CB) },
7203     { PREFIX_TABLE (PREFIX_0F38CC) },
7204     { PREFIX_TABLE (PREFIX_0F38CD) },
7205     { Bad_Opcode },
7206     { PREFIX_TABLE (PREFIX_0F38CF) },
7207     /* d0 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* d8 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { PREFIX_TABLE (PREFIX_0F38DB) },
7221     { PREFIX_TABLE (PREFIX_0F38DC) },
7222     { PREFIX_TABLE (PREFIX_0F38DD) },
7223     { PREFIX_TABLE (PREFIX_0F38DE) },
7224     { PREFIX_TABLE (PREFIX_0F38DF) },
7225     /* e0 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* e8 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* f0 */
7244     { PREFIX_TABLE (PREFIX_0F38F0) },
7245     { PREFIX_TABLE (PREFIX_0F38F1) },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { PREFIX_TABLE (PREFIX_0F38F5) },
7250     { PREFIX_TABLE (PREFIX_0F38F6) },
7251     { Bad_Opcode },
7252     /* f8 */
7253     { PREFIX_TABLE (PREFIX_0F38F8) },
7254     { PREFIX_TABLE (PREFIX_0F38F9) },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261   },
7262   /* THREE_BYTE_0F3A */
7263   {
7264     /* 00 */
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     /* 08 */
7274     { PREFIX_TABLE (PREFIX_0F3A08) },
7275     { PREFIX_TABLE (PREFIX_0F3A09) },
7276     { PREFIX_TABLE (PREFIX_0F3A0A) },
7277     { PREFIX_TABLE (PREFIX_0F3A0B) },
7278     { PREFIX_TABLE (PREFIX_0F3A0C) },
7279     { PREFIX_TABLE (PREFIX_0F3A0D) },
7280     { PREFIX_TABLE (PREFIX_0F3A0E) },
7281     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7282     /* 10 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { PREFIX_TABLE (PREFIX_0F3A14) },
7288     { PREFIX_TABLE (PREFIX_0F3A15) },
7289     { PREFIX_TABLE (PREFIX_0F3A16) },
7290     { PREFIX_TABLE (PREFIX_0F3A17) },
7291     /* 18 */
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* 20 */
7301     { PREFIX_TABLE (PREFIX_0F3A20) },
7302     { PREFIX_TABLE (PREFIX_0F3A21) },
7303     { PREFIX_TABLE (PREFIX_0F3A22) },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* 28 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 30 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 38 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 40 */
7337     { PREFIX_TABLE (PREFIX_0F3A40) },
7338     { PREFIX_TABLE (PREFIX_0F3A41) },
7339     { PREFIX_TABLE (PREFIX_0F3A42) },
7340     { Bad_Opcode },
7341     { PREFIX_TABLE (PREFIX_0F3A44) },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 48 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 50 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 58 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 60 */
7373     { PREFIX_TABLE (PREFIX_0F3A60) },
7374     { PREFIX_TABLE (PREFIX_0F3A61) },
7375     { PREFIX_TABLE (PREFIX_0F3A62) },
7376     { PREFIX_TABLE (PREFIX_0F3A63) },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* 68 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* 70 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* 78 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* 80 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* 88 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* 90 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     /* 98 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* a0 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* a8 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* b0 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* b8 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* c0 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* c8 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { PREFIX_TABLE (PREFIX_0F3ACC) },
7495     { Bad_Opcode },
7496     { PREFIX_TABLE (PREFIX_0F3ACE) },
7497     { PREFIX_TABLE (PREFIX_0F3ACF) },
7498     /* d0 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* d8 */
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { PREFIX_TABLE (PREFIX_0F3ADF) },
7516     /* e0 */
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     /* e8 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     /* f0 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* f8 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552   },
7553 };
7554
7555 static const struct dis386 xop_table[][256] = {
7556   /* XOP_08 */
7557   {
7558     /* 00 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 08 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 10 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 18 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 20 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 28 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 30 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 38 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 40 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 48 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 50 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* 58 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 60 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* 68 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* 70 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* 78 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     /* 80 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7711     /* 88 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7719     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7720     /* 90 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729     /* 98 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7737     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7738     /* a0 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7742     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7746     { Bad_Opcode },
7747     /* a8 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* b0 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7764     { Bad_Opcode },
7765     /* b8 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* c0 */
7775     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7776     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7777     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7778     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* c8 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7792     /* d0 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* d8 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* e0 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* e8 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7827     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7828     /* f0 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* f8 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846   },
7847   /* XOP_09 */
7848   {
7849     /* 00 */
7850     { Bad_Opcode },
7851     { REG_TABLE (REG_XOP_TBM_01) },
7852     { REG_TABLE (REG_XOP_TBM_02) },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* 08 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     /* 10 */
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { REG_TABLE (REG_XOP_LWPCB) },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     /* 18 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     /* 20 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     /* 28 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     /* 30 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     /* 38 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     /* 40 */
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     /* 48 */
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* 50 */
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     /* 58 */
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     /* 60 */
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     /* 68 */
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     /* 70 */
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     /* 78 */
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* 80 */
7994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7995     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7996     { "vfrczss",        { XM, EXd }, 0 },
7997     { "vfrczsd",        { XM, EXq }, 0 },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     /* 88 */
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     /* 90 */
8012     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     /* 98 */
8021     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* a0 */
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* a8 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* b0 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* b8 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* c0 */
8066     { Bad_Opcode },
8067     { "vphaddbw",       { XM, EXxmm }, 0 },
8068     { "vphaddbd",       { XM, EXxmm }, 0 },
8069     { "vphaddbq",       { XM, EXxmm }, 0 },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { "vphaddwd",       { XM, EXxmm }, 0 },
8073     { "vphaddwq",       { XM, EXxmm }, 0 },
8074     /* c8 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { "vphadddq",       { XM, EXxmm }, 0 },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* d0 */
8084     { Bad_Opcode },
8085     { "vphaddubw",      { XM, EXxmm }, 0 },
8086     { "vphaddubd",      { XM, EXxmm }, 0 },
8087     { "vphaddubq",      { XM, EXxmm }, 0 },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { "vphadduwd",      { XM, EXxmm }, 0 },
8091     { "vphadduwq",      { XM, EXxmm }, 0 },
8092     /* d8 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { "vphaddudq",      { XM, EXxmm }, 0 },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* e0 */
8102     { Bad_Opcode },
8103     { "vphsubbw",       { XM, EXxmm }, 0 },
8104     { "vphsubwd",       { XM, EXxmm }, 0 },
8105     { "vphsubdq",       { XM, EXxmm }, 0 },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* e8 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* f0 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* f8 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137   },
8138   /* XOP_0A */
8139   {
8140     /* 00 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* 08 */
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     /* 10 */
8159     { "bextrS", { Gdq, Edq, Id }, 0 },
8160     { Bad_Opcode },
8161     { REG_TABLE (REG_XOP_LWP) },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* 18 */
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     /* 20 */
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* 28 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* 30 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* 38 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     /* 40 */
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* 48 */
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     /* 50 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* 58 */
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     /* 60 */
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* 68 */
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     /* 70 */
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* 78 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* 80 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     /* 88 */
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     /* 90 */
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     /* 98 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* a0 */
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     /* a8 */
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* b0 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* b8 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* c0 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     /* c8 */
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     /* d0 */
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     /* d8 */
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     /* e0 */
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     /* e8 */
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     /* f0 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* f8 */
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428   },
8429 };
8430
8431 static const struct dis386 vex_table[][256] = {
8432   /* VEX_0F */
8433   {
8434     /* 00 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 08 */
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* 10 */
8453     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8456     { MOD_TABLE (MOD_VEX_0F13) },
8457     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8458     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8459     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8460     { MOD_TABLE (MOD_VEX_0F17) },
8461     /* 18 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 20 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* 28 */
8480     { "vmovapX",        { XM, EXx }, 0 },
8481     { "vmovapX",        { EXxS, XM }, 0 },
8482     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8483     { MOD_TABLE (MOD_VEX_0F2B) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8488     /* 30 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* 38 */
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     /* 40 */
8507     { Bad_Opcode },
8508     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8510     { Bad_Opcode },
8511     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8515     /* 48 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 50 */
8525     { MOD_TABLE (MOD_VEX_0F50) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8529     { "vandpX",         { XM, Vex, EXx }, 0 },
8530     { "vandnpX",        { XM, Vex, EXx }, 0 },
8531     { "vorpX",          { XM, Vex, EXx }, 0 },
8532     { "vxorpX",         { XM, Vex, EXx }, 0 },
8533     /* 58 */
8534     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8542     /* 60 */
8543     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8551     /* 68 */
8552     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8560     /* 70 */
8561     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8562     { REG_TABLE (REG_VEX_0F71) },
8563     { REG_TABLE (REG_VEX_0F72) },
8564     { REG_TABLE (REG_VEX_0F73) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8569     /* 78 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8578     /* 80 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* 88 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     /* 90 */
8597     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* 98 */
8606     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* a0 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* a8 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { REG_TABLE (REG_VEX_0FAE) },
8631     { Bad_Opcode },
8632     /* b0 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* b8 */
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     /* c0 */
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8654     { Bad_Opcode },
8655     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8657     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8658     { Bad_Opcode },
8659     /* c8 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     /* d0 */
8669     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8677     /* d8 */
8678     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8686     /* e0 */
8687     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8695     /* e8 */
8696     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8704     /* f0 */
8705     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8713     /* f8 */
8714     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8721     { Bad_Opcode },
8722   },
8723   /* VEX_0F38 */
8724   {
8725     /* 00 */
8726     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8734     /* 08 */
8735     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8743     /* 10 */
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8752     /* 18 */
8753     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8756     { Bad_Opcode },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8760     { Bad_Opcode },
8761     /* 20 */
8762     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     /* 28 */
8771     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8779     /* 30 */
8780     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8788     /* 38 */
8789     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8797     /* 40 */
8798     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8806     /* 48 */
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     /* 50 */
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     /* 58 */
8825     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     /* 60 */
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     /* 68 */
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     /* 70 */
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     /* 78 */
8861     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     /* 80 */
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     /* 88 */
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8884     { Bad_Opcode },
8885     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8886     { Bad_Opcode },
8887     /* 90 */
8888     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8896     /* 98 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8905     /* a0 */
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8914     /* a8 */
8915     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8923     /* b0 */
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8932     /* b8 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8941     /* c0 */
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* c8 */
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8959     /* d0 */
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     /* d8 */
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8977     /* e0 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* e8 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     /* f0 */
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8999     { REG_TABLE (REG_VEX_0F38F3) },
9000     { Bad_Opcode },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9004     /* f8 */
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013   },
9014   /* VEX_0F3A */
9015   {
9016     /* 00 */
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9020     { Bad_Opcode },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9024     { Bad_Opcode },
9025     /* 08 */
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9034     /* 10 */
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9043     /* 18 */
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     /* 20 */
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     /* 28 */
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     /* 30 */
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     /* 38 */
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     /* 40 */
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9092     { Bad_Opcode },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9094     { Bad_Opcode },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9096     { Bad_Opcode },
9097     /* 48 */
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     /* 50 */
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     /* 58 */
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9124     /* 60 */
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     /* 68 */
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9142     /* 70 */
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     /* 78 */
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9160     /* 80 */
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     /* 88 */
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     /* 90 */
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     /* 98 */
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     /* a0 */
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     /* a8 */
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     /* b0 */
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     /* b8 */
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     /* c0 */
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     /* c8 */
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9249     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9250     /* d0 */
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     /* d8 */
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9268     /* e0 */
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     /* e8 */
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     /* f0 */
9287     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     /* f8 */
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304   },
9305 };
9306
9307 #include "i386-dis-evex.h"
9308
9309 static const struct dis386 vex_len_table[][2] = {
9310   /* VEX_LEN_0F12_P_0_M_0 */
9311   {
9312     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9313   },
9314
9315   /* VEX_LEN_0F12_P_0_M_1 */
9316   {
9317     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9318   },
9319
9320   /* VEX_LEN_0F12_P_2 */
9321   {
9322     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9323   },
9324
9325   /* VEX_LEN_0F13_M_0 */
9326   {
9327     { "vmovlpX",        { EXq, XM }, 0 },
9328   },
9329
9330   /* VEX_LEN_0F16_P_0_M_0 */
9331   {
9332     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9333   },
9334
9335   /* VEX_LEN_0F16_P_0_M_1 */
9336   {
9337     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9338   },
9339
9340   /* VEX_LEN_0F16_P_2 */
9341   {
9342     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9343   },
9344
9345   /* VEX_LEN_0F17_M_0 */
9346   {
9347     { "vmovhpX",        { EXq, XM }, 0 },
9348   },
9349
9350   /* VEX_LEN_0F41_P_0 */
9351   {
9352     { Bad_Opcode },
9353     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9354   },
9355   /* VEX_LEN_0F41_P_2 */
9356   {
9357     { Bad_Opcode },
9358     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9359   },
9360   /* VEX_LEN_0F42_P_0 */
9361   {
9362     { Bad_Opcode },
9363     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9364   },
9365   /* VEX_LEN_0F42_P_2 */
9366   {
9367     { Bad_Opcode },
9368     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9369   },
9370   /* VEX_LEN_0F44_P_0 */
9371   {
9372     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9373   },
9374   /* VEX_LEN_0F44_P_2 */
9375   {
9376     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9377   },
9378   /* VEX_LEN_0F45_P_0 */
9379   {
9380     { Bad_Opcode },
9381     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9382   },
9383   /* VEX_LEN_0F45_P_2 */
9384   {
9385     { Bad_Opcode },
9386     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9387   },
9388   /* VEX_LEN_0F46_P_0 */
9389   {
9390     { Bad_Opcode },
9391     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9392   },
9393   /* VEX_LEN_0F46_P_2 */
9394   {
9395     { Bad_Opcode },
9396     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9397   },
9398   /* VEX_LEN_0F47_P_0 */
9399   {
9400     { Bad_Opcode },
9401     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9402   },
9403   /* VEX_LEN_0F47_P_2 */
9404   {
9405     { Bad_Opcode },
9406     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9407   },
9408   /* VEX_LEN_0F4A_P_0 */
9409   {
9410     { Bad_Opcode },
9411     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9412   },
9413   /* VEX_LEN_0F4A_P_2 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9417   },
9418   /* VEX_LEN_0F4B_P_0 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9422   },
9423   /* VEX_LEN_0F4B_P_2 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9427   },
9428
9429   /* VEX_LEN_0F6E_P_2 */
9430   {
9431     { "vmovK",          { XMScalar, Edq }, 0 },
9432   },
9433
9434   /* VEX_LEN_0F77_P_1 */
9435   {
9436     { "vzeroupper",     { XX }, 0 },
9437     { "vzeroall",       { XX }, 0 },
9438   },
9439
9440   /* VEX_LEN_0F7E_P_1 */
9441   {
9442     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F7E_P_2 */
9446   {
9447     { "vmovK",          { Edq, XMScalar }, 0 },
9448   },
9449
9450   /* VEX_LEN_0F90_P_0 */
9451   {
9452     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9453   },
9454
9455   /* VEX_LEN_0F90_P_2 */
9456   {
9457     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9458   },
9459
9460   /* VEX_LEN_0F91_P_0 */
9461   {
9462     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9463   },
9464
9465   /* VEX_LEN_0F91_P_2 */
9466   {
9467     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9468   },
9469
9470   /* VEX_LEN_0F92_P_0 */
9471   {
9472     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9473   },
9474
9475   /* VEX_LEN_0F92_P_2 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9478   },
9479
9480   /* VEX_LEN_0F92_P_3 */
9481   {
9482     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F93_P_0 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F93_P_2 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F93_P_3 */
9496   {
9497     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F98_P_0 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F98_P_2 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F99_P_0 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0F99_P_2 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9518   },
9519
9520   /* VEX_LEN_0FAE_R_2_M_0 */
9521   {
9522     { "vldmxcsr",       { Md }, 0 },
9523   },
9524
9525   /* VEX_LEN_0FAE_R_3_M_0 */
9526   {
9527     { "vstmxcsr",       { Md }, 0 },
9528   },
9529
9530   /* VEX_LEN_0FC4_P_2 */
9531   {
9532     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9533   },
9534
9535   /* VEX_LEN_0FC5_P_2 */
9536   {
9537     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9538   },
9539
9540   /* VEX_LEN_0FD6_P_2 */
9541   {
9542     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9543   },
9544
9545   /* VEX_LEN_0FF7_P_2 */
9546   {
9547     { "vmaskmovdqu",    { XM, XS }, 0 },
9548   },
9549
9550   /* VEX_LEN_0F3816_P_2 */
9551   {
9552     { Bad_Opcode },
9553     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9554   },
9555
9556   /* VEX_LEN_0F3819_P_2 */
9557   {
9558     { Bad_Opcode },
9559     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9560   },
9561
9562   /* VEX_LEN_0F381A_P_2_M_0 */
9563   {
9564     { Bad_Opcode },
9565     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9566   },
9567
9568   /* VEX_LEN_0F3836_P_2 */
9569   {
9570     { Bad_Opcode },
9571     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9572   },
9573
9574   /* VEX_LEN_0F3841_P_2 */
9575   {
9576     { "vphminposuw",    { XM, EXx }, 0 },
9577   },
9578
9579   /* VEX_LEN_0F385A_P_2_M_0 */
9580   {
9581     { Bad_Opcode },
9582     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9583   },
9584
9585   /* VEX_LEN_0F38DB_P_2 */
9586   {
9587     { "vaesimc",        { XM, EXx }, 0 },
9588   },
9589
9590   /* VEX_LEN_0F38F2_P_0 */
9591   {
9592     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F38F3_R_1_P_0 */
9596   {
9597     { "blsrS",          { VexGdq, Edq }, 0 },
9598   },
9599
9600   /* VEX_LEN_0F38F3_R_2_P_0 */
9601   {
9602     { "blsmskS",        { VexGdq, Edq }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F38F3_R_3_P_0 */
9606   {
9607     { "blsiS",          { VexGdq, Edq }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F38F5_P_0 */
9611   {
9612     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F38F5_P_1 */
9616   {
9617     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F38F5_P_3 */
9621   {
9622     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F38F6_P_3 */
9626   {
9627     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F38F7_P_0 */
9631   {
9632     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F38F7_P_1 */
9636   {
9637     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F38F7_P_2 */
9641   {
9642     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F38F7_P_3 */
9646   {
9647     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F3A00_P_2 */
9651   {
9652     { Bad_Opcode },
9653     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9654   },
9655
9656   /* VEX_LEN_0F3A01_P_2 */
9657   {
9658     { Bad_Opcode },
9659     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9660   },
9661
9662   /* VEX_LEN_0F3A06_P_2 */
9663   {
9664     { Bad_Opcode },
9665     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9666   },
9667
9668   /* VEX_LEN_0F3A14_P_2 */
9669   {
9670     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F3A15_P_2 */
9674   {
9675     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9676   },
9677
9678   /* VEX_LEN_0F3A16_P_2  */
9679   {
9680     { "vpextrK",        { Edq, XM, Ib }, 0 },
9681   },
9682
9683   /* VEX_LEN_0F3A17_P_2 */
9684   {
9685     { "vextractps",     { Edqd, XM, Ib }, 0 },
9686   },
9687
9688   /* VEX_LEN_0F3A18_P_2 */
9689   {
9690     { Bad_Opcode },
9691     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9692   },
9693
9694   /* VEX_LEN_0F3A19_P_2 */
9695   {
9696     { Bad_Opcode },
9697     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9698   },
9699
9700   /* VEX_LEN_0F3A20_P_2 */
9701   {
9702     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9703   },
9704
9705   /* VEX_LEN_0F3A21_P_2 */
9706   {
9707     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9708   },
9709
9710   /* VEX_LEN_0F3A22_P_2 */
9711   {
9712     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9713   },
9714
9715   /* VEX_LEN_0F3A30_P_2 */
9716   {
9717     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9718   },
9719
9720   /* VEX_LEN_0F3A31_P_2 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9723   },
9724
9725   /* VEX_LEN_0F3A32_P_2 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9728   },
9729
9730   /* VEX_LEN_0F3A33_P_2 */
9731   {
9732     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9733   },
9734
9735   /* VEX_LEN_0F3A38_P_2 */
9736   {
9737     { Bad_Opcode },
9738     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9739   },
9740
9741   /* VEX_LEN_0F3A39_P_2 */
9742   {
9743     { Bad_Opcode },
9744     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9745   },
9746
9747   /* VEX_LEN_0F3A41_P_2 */
9748   {
9749     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9750   },
9751
9752   /* VEX_LEN_0F3A46_P_2 */
9753   {
9754     { Bad_Opcode },
9755     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9756   },
9757
9758   /* VEX_LEN_0F3A60_P_2 */
9759   {
9760     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9761   },
9762
9763   /* VEX_LEN_0F3A61_P_2 */
9764   {
9765     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9766   },
9767
9768   /* VEX_LEN_0F3A62_P_2 */
9769   {
9770     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9771   },
9772
9773   /* VEX_LEN_0F3A63_P_2 */
9774   {
9775     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9776   },
9777
9778   /* VEX_LEN_0F3A6A_P_2 */
9779   {
9780     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3A6B_P_2 */
9784   {
9785     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F3A6E_P_2 */
9789   {
9790     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9791   },
9792
9793   /* VEX_LEN_0F3A6F_P_2 */
9794   {
9795     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A7A_P_2 */
9799   {
9800     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A7B_P_2 */
9804   {
9805     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A7E_P_2 */
9809   {
9810     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9811   },
9812
9813   /* VEX_LEN_0F3A7F_P_2 */
9814   {
9815     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3ADF_P_2 */
9819   {
9820     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9821   },
9822
9823   /* VEX_LEN_0F3AF0_P_3 */
9824   {
9825     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9826   },
9827
9828   /* VEX_LEN_0FXOP_08_CC */
9829   {
9830      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9831   },
9832
9833   /* VEX_LEN_0FXOP_08_CD */
9834   {
9835      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9836   },
9837
9838   /* VEX_LEN_0FXOP_08_CE */
9839   {
9840      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9841   },
9842
9843   /* VEX_LEN_0FXOP_08_CF */
9844   {
9845      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9846   },
9847
9848   /* VEX_LEN_0FXOP_08_EC */
9849   {
9850      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9851   },
9852
9853   /* VEX_LEN_0FXOP_08_ED */
9854   {
9855      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_EE */
9859   {
9860      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_EF */
9864   {
9865      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9866   },
9867
9868   /* VEX_LEN_0FXOP_09_80 */
9869   {
9870     { "vfrczps",        { XM, EXxmm }, 0 },
9871     { "vfrczps",        { XM, EXymmq }, 0 },
9872   },
9873
9874   /* VEX_LEN_0FXOP_09_81 */
9875   {
9876     { "vfrczpd",        { XM, EXxmm }, 0 },
9877     { "vfrczpd",        { XM, EXymmq }, 0 },
9878   },
9879 };
9880
9881 #include "i386-dis-evex-len.h"
9882
9883 static const struct dis386 vex_w_table[][2] = {
9884   {
9885     /* VEX_W_0F41_P_0_LEN_1 */
9886     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9887     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9888   },
9889   {
9890     /* VEX_W_0F41_P_2_LEN_1 */
9891     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9892     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9893   },
9894   {
9895     /* VEX_W_0F42_P_0_LEN_1 */
9896     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9897     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9898   },
9899   {
9900     /* VEX_W_0F42_P_2_LEN_1 */
9901     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9902     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9903   },
9904   {
9905     /* VEX_W_0F44_P_0_LEN_0 */
9906     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9907     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9908   },
9909   {
9910     /* VEX_W_0F44_P_2_LEN_0 */
9911     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9912     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9913   },
9914   {
9915     /* VEX_W_0F45_P_0_LEN_1 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F45_P_2_LEN_1 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F46_P_0_LEN_1 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F46_P_2_LEN_1 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F47_P_0_LEN_1 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F47_P_2_LEN_1 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F4A_P_0_LEN_1 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F4A_P_2_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F4B_P_0_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9957     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9958   },
9959   {
9960     /* VEX_W_0F4B_P_2_LEN_1 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9962   },
9963   {
9964     /* VEX_W_0F90_P_0_LEN_0 */
9965     { "kmovw",          { MaskG, MaskE }, 0 },
9966     { "kmovq",          { MaskG, MaskE }, 0 },
9967   },
9968   {
9969     /* VEX_W_0F90_P_2_LEN_0 */
9970     { "kmovb",          { MaskG, MaskBDE }, 0 },
9971     { "kmovd",          { MaskG, MaskBDE }, 0 },
9972   },
9973   {
9974     /* VEX_W_0F91_P_0_LEN_0 */
9975     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9976     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9977   },
9978   {
9979     /* VEX_W_0F91_P_2_LEN_0 */
9980     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9981     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9982   },
9983   {
9984     /* VEX_W_0F92_P_0_LEN_0 */
9985     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9986   },
9987   {
9988     /* VEX_W_0F92_P_2_LEN_0 */
9989     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9990   },
9991   {
9992     /* VEX_W_0F93_P_0_LEN_0 */
9993     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9994   },
9995   {
9996     /* VEX_W_0F93_P_2_LEN_0 */
9997     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9998   },
9999   {
10000     /* VEX_W_0F98_P_0_LEN_0 */
10001     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10002     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10003   },
10004   {
10005     /* VEX_W_0F98_P_2_LEN_0 */
10006     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10007     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10008   },
10009   {
10010     /* VEX_W_0F99_P_0_LEN_0 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10012     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10013   },
10014   {
10015     /* VEX_W_0F99_P_2_LEN_0 */
10016     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10017     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10018   },
10019   {
10020     /* VEX_W_0F380C_P_2  */
10021     { "vpermilps",      { XM, Vex, EXx }, 0 },
10022   },
10023   {
10024     /* VEX_W_0F380D_P_2  */
10025     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10026   },
10027   {
10028     /* VEX_W_0F380E_P_2  */
10029     { "vtestps",        { XM, EXx }, 0 },
10030   },
10031   {
10032     /* VEX_W_0F380F_P_2  */
10033     { "vtestpd",        { XM, EXx }, 0 },
10034   },
10035   {
10036     /* VEX_W_0F3816_P_2  */
10037     { "vpermps",        { XM, Vex, EXx }, 0 },
10038   },
10039   {
10040     /* VEX_W_0F3818_P_2 */
10041     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10042   },
10043   {
10044     /* VEX_W_0F3819_P_2 */
10045     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10046   },
10047   {
10048     /* VEX_W_0F381A_P_2_M_0 */
10049     { "vbroadcastf128", { XM, Mxmm }, 0 },
10050   },
10051   {
10052     /* VEX_W_0F382C_P_2_M_0 */
10053     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10054   },
10055   {
10056     /* VEX_W_0F382D_P_2_M_0 */
10057     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10058   },
10059   {
10060     /* VEX_W_0F382E_P_2_M_0 */
10061     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10062   },
10063   {
10064     /* VEX_W_0F382F_P_2_M_0 */
10065     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10066   },
10067   {
10068     /* VEX_W_0F3836_P_2  */
10069     { "vpermd",         { XM, Vex, EXx }, 0 },
10070   },
10071   {
10072     /* VEX_W_0F3846_P_2 */
10073     { "vpsravd",        { XM, Vex, EXx }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F3858_P_2 */
10077     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F3859_P_2 */
10081     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F385A_P_2_M_0 */
10085     { "vbroadcasti128", { XM, Mxmm }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F3878_P_2 */
10089     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10090   },
10091   {
10092     /* VEX_W_0F3879_P_2 */
10093     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10094   },
10095   {
10096     /* VEX_W_0F38CF_P_2 */
10097     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F3A00_P_2 */
10101     { Bad_Opcode },
10102     { "vpermq",         { XM, EXx, Ib }, 0 },
10103   },
10104   {
10105     /* VEX_W_0F3A01_P_2 */
10106     { Bad_Opcode },
10107     { "vpermpd",        { XM, EXx, Ib }, 0 },
10108   },
10109   {
10110     /* VEX_W_0F3A02_P_2 */
10111     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10112   },
10113   {
10114     /* VEX_W_0F3A04_P_2 */
10115     { "vpermilps",      { XM, EXx, Ib }, 0 },
10116   },
10117   {
10118     /* VEX_W_0F3A05_P_2 */
10119     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10120   },
10121   {
10122     /* VEX_W_0F3A06_P_2 */
10123     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10124   },
10125   {
10126     /* VEX_W_0F3A18_P_2 */
10127     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10128   },
10129   {
10130     /* VEX_W_0F3A19_P_2 */
10131     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10132   },
10133   {
10134     /* VEX_W_0F3A30_P_2_LEN_0 */
10135     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10136     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10137   },
10138   {
10139     /* VEX_W_0F3A31_P_2_LEN_0 */
10140     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10141     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10142   },
10143   {
10144     /* VEX_W_0F3A32_P_2_LEN_0 */
10145     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10146     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10147   },
10148   {
10149     /* VEX_W_0F3A33_P_2_LEN_0 */
10150     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10151     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10152   },
10153   {
10154     /* VEX_W_0F3A38_P_2 */
10155     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10156   },
10157   {
10158     /* VEX_W_0F3A39_P_2 */
10159     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10160   },
10161   {
10162     /* VEX_W_0F3A46_P_2 */
10163     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10164   },
10165   {
10166     /* VEX_W_0F3A48_P_2 */
10167     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10168     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10169   },
10170   {
10171     /* VEX_W_0F3A49_P_2 */
10172     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10173     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10174   },
10175   {
10176     /* VEX_W_0F3A4A_P_2 */
10177     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10178   },
10179   {
10180     /* VEX_W_0F3A4B_P_2 */
10181     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10182   },
10183   {
10184     /* VEX_W_0F3A4C_P_2 */
10185     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10186   },
10187   {
10188     /* VEX_W_0F3ACE_P_2 */
10189     { Bad_Opcode },
10190     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10191   },
10192   {
10193     /* VEX_W_0F3ACF_P_2 */
10194     { Bad_Opcode },
10195     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10196   },
10197
10198 #include "i386-dis-evex-w.h"
10199 };
10200
10201 static const struct dis386 mod_table[][2] = {
10202   {
10203     /* MOD_8D */
10204     { "leaS",           { Gv, M }, 0 },
10205   },
10206   {
10207     /* MOD_C6_REG_7 */
10208     { Bad_Opcode },
10209     { RM_TABLE (RM_C6_REG_7) },
10210   },
10211   {
10212     /* MOD_C7_REG_7 */
10213     { Bad_Opcode },
10214     { RM_TABLE (RM_C7_REG_7) },
10215   },
10216   {
10217     /* MOD_FF_REG_3 */
10218     { "Jcall^", { indirEp }, 0 },
10219   },
10220   {
10221     /* MOD_FF_REG_5 */
10222     { "Jjmp^", { indirEp }, 0 },
10223   },
10224   {
10225     /* MOD_0F01_REG_0 */
10226     { X86_64_TABLE (X86_64_0F01_REG_0) },
10227     { RM_TABLE (RM_0F01_REG_0) },
10228   },
10229   {
10230     /* MOD_0F01_REG_1 */
10231     { X86_64_TABLE (X86_64_0F01_REG_1) },
10232     { RM_TABLE (RM_0F01_REG_1) },
10233   },
10234   {
10235     /* MOD_0F01_REG_2 */
10236     { X86_64_TABLE (X86_64_0F01_REG_2) },
10237     { RM_TABLE (RM_0F01_REG_2) },
10238   },
10239   {
10240     /* MOD_0F01_REG_3 */
10241     { X86_64_TABLE (X86_64_0F01_REG_3) },
10242     { RM_TABLE (RM_0F01_REG_3) },
10243   },
10244   {
10245     /* MOD_0F01_REG_5 */
10246     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10247     { RM_TABLE (RM_0F01_REG_5) },
10248   },
10249   {
10250     /* MOD_0F01_REG_7 */
10251     { "invlpg",         { Mb }, 0 },
10252     { RM_TABLE (RM_0F01_REG_7) },
10253   },
10254   {
10255     /* MOD_0F12_PREFIX_0 */
10256     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10257     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10258   },
10259   {
10260     /* MOD_0F13 */
10261     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10262   },
10263   {
10264     /* MOD_0F16_PREFIX_0 */
10265     { "movhps",         { XM, EXq }, 0 },
10266     { "movlhps",        { XM, EXq }, 0 },
10267   },
10268   {
10269     /* MOD_0F17 */
10270     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10271   },
10272   {
10273     /* MOD_0F18_REG_0 */
10274     { "prefetchnta",    { Mb }, 0 },
10275   },
10276   {
10277     /* MOD_0F18_REG_1 */
10278     { "prefetcht0",     { Mb }, 0 },
10279   },
10280   {
10281     /* MOD_0F18_REG_2 */
10282     { "prefetcht1",     { Mb }, 0 },
10283   },
10284   {
10285     /* MOD_0F18_REG_3 */
10286     { "prefetcht2",     { Mb }, 0 },
10287   },
10288   {
10289     /* MOD_0F18_REG_4 */
10290     { "nop/reserved",   { Mb }, 0 },
10291   },
10292   {
10293     /* MOD_0F18_REG_5 */
10294     { "nop/reserved",   { Mb }, 0 },
10295   },
10296   {
10297     /* MOD_0F18_REG_6 */
10298     { "nop/reserved",   { Mb }, 0 },
10299   },
10300   {
10301     /* MOD_0F18_REG_7 */
10302     { "nop/reserved",   { Mb }, 0 },
10303   },
10304   {
10305     /* MOD_0F1A_PREFIX_0 */
10306     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10307     { "nopQ",           { Ev }, 0 },
10308   },
10309   {
10310     /* MOD_0F1B_PREFIX_0 */
10311     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10312     { "nopQ",           { Ev }, 0 },
10313   },
10314   {
10315     /* MOD_0F1B_PREFIX_1 */
10316     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10317     { "nopQ",           { Ev }, 0 },
10318   },
10319   {
10320     /* MOD_0F1C_PREFIX_0 */
10321     { REG_TABLE (REG_0F1C_MOD_0) },
10322     { "nopQ",           { Ev }, 0 },
10323   },
10324   {
10325     /* MOD_0F1E_PREFIX_1 */
10326     { "nopQ",           { Ev }, 0 },
10327     { REG_TABLE (REG_0F1E_MOD_3) },
10328   },
10329   {
10330     /* MOD_0F24 */
10331     { Bad_Opcode },
10332     { "movL",           { Rd, Td }, 0 },
10333   },
10334   {
10335     /* MOD_0F26 */
10336     { Bad_Opcode },
10337     { "movL",           { Td, Rd }, 0 },
10338   },
10339   {
10340     /* MOD_0F2B_PREFIX_0 */
10341     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10342   },
10343   {
10344     /* MOD_0F2B_PREFIX_1 */
10345     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10346   },
10347   {
10348     /* MOD_0F2B_PREFIX_2 */
10349     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10350   },
10351   {
10352     /* MOD_0F2B_PREFIX_3 */
10353     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10354   },
10355   {
10356     /* MOD_0F51 */
10357     { Bad_Opcode },
10358     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10359   },
10360   {
10361     /* MOD_0F71_REG_2 */
10362     { Bad_Opcode },
10363     { "psrlw",          { MS, Ib }, 0 },
10364   },
10365   {
10366     /* MOD_0F71_REG_4 */
10367     { Bad_Opcode },
10368     { "psraw",          { MS, Ib }, 0 },
10369   },
10370   {
10371     /* MOD_0F71_REG_6 */
10372     { Bad_Opcode },
10373     { "psllw",          { MS, Ib }, 0 },
10374   },
10375   {
10376     /* MOD_0F72_REG_2 */
10377     { Bad_Opcode },
10378     { "psrld",          { MS, Ib }, 0 },
10379   },
10380   {
10381     /* MOD_0F72_REG_4 */
10382     { Bad_Opcode },
10383     { "psrad",          { MS, Ib }, 0 },
10384   },
10385   {
10386     /* MOD_0F72_REG_6 */
10387     { Bad_Opcode },
10388     { "pslld",          { MS, Ib }, 0 },
10389   },
10390   {
10391     /* MOD_0F73_REG_2 */
10392     { Bad_Opcode },
10393     { "psrlq",          { MS, Ib }, 0 },
10394   },
10395   {
10396     /* MOD_0F73_REG_3 */
10397     { Bad_Opcode },
10398     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10399   },
10400   {
10401     /* MOD_0F73_REG_6 */
10402     { Bad_Opcode },
10403     { "psllq",          { MS, Ib }, 0 },
10404   },
10405   {
10406     /* MOD_0F73_REG_7 */
10407     { Bad_Opcode },
10408     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10409   },
10410   {
10411     /* MOD_0FAE_REG_0 */
10412     { "fxsave",         { FXSAVE }, 0 },
10413     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10414   },
10415   {
10416     /* MOD_0FAE_REG_1 */
10417     { "fxrstor",        { FXSAVE }, 0 },
10418     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10419   },
10420   {
10421     /* MOD_0FAE_REG_2 */
10422     { "ldmxcsr",        { Md }, 0 },
10423     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10424   },
10425   {
10426     /* MOD_0FAE_REG_3 */
10427     { "stmxcsr",        { Md }, 0 },
10428     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10429   },
10430   {
10431     /* MOD_0FAE_REG_4 */
10432     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10433     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10434   },
10435   {
10436     /* MOD_0FAE_REG_5 */
10437     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10438     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10439   },
10440   {
10441     /* MOD_0FAE_REG_6 */
10442     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10443     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10444   },
10445   {
10446     /* MOD_0FAE_REG_7 */
10447     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10448     { RM_TABLE (RM_0FAE_REG_7) },
10449   },
10450   {
10451     /* MOD_0FB2 */
10452     { "lssS",           { Gv, Mp }, 0 },
10453   },
10454   {
10455     /* MOD_0FB4 */
10456     { "lfsS",           { Gv, Mp }, 0 },
10457   },
10458   {
10459     /* MOD_0FB5 */
10460     { "lgsS",           { Gv, Mp }, 0 },
10461   },
10462   {
10463     /* MOD_0FC3 */
10464     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10465   },
10466   {
10467     /* MOD_0FC7_REG_3 */
10468     { "xrstors",        { FXSAVE }, 0 },
10469   },
10470   {
10471     /* MOD_0FC7_REG_4 */
10472     { "xsavec",         { FXSAVE }, 0 },
10473   },
10474   {
10475     /* MOD_0FC7_REG_5 */
10476     { "xsaves",         { FXSAVE }, 0 },
10477   },
10478   {
10479     /* MOD_0FC7_REG_6 */
10480     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10481     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10482   },
10483   {
10484     /* MOD_0FC7_REG_7 */
10485     { "vmptrst",        { Mq }, 0 },
10486     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10487   },
10488   {
10489     /* MOD_0FD7 */
10490     { Bad_Opcode },
10491     { "pmovmskb",       { Gdq, MS }, 0 },
10492   },
10493   {
10494     /* MOD_0FE7_PREFIX_2 */
10495     { "movntdq",        { Mx, XM }, 0 },
10496   },
10497   {
10498     /* MOD_0FF0_PREFIX_3 */
10499     { "lddqu",          { XM, M }, 0 },
10500   },
10501   {
10502     /* MOD_0F382A_PREFIX_2 */
10503     { "movntdqa",       { XM, Mx }, 0 },
10504   },
10505   {
10506     /* MOD_0F38F5_PREFIX_2 */
10507     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10508   },
10509   {
10510     /* MOD_0F38F6_PREFIX_0 */
10511     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10512   },
10513   {
10514     /* MOD_0F38F8_PREFIX_1 */
10515     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10516   },
10517   {
10518     /* MOD_0F38F8_PREFIX_2 */
10519     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10520   },
10521   {
10522     /* MOD_0F38F8_PREFIX_3 */
10523     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10524   },
10525   {
10526     /* MOD_0F38F9_PREFIX_0 */
10527     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10528   },
10529   {
10530     /* MOD_62_32BIT */
10531     { "bound{S|}",      { Gv, Ma }, 0 },
10532     { EVEX_TABLE (EVEX_0F) },
10533   },
10534   {
10535     /* MOD_C4_32BIT */
10536     { "lesS",           { Gv, Mp }, 0 },
10537     { VEX_C4_TABLE (VEX_0F) },
10538   },
10539   {
10540     /* MOD_C5_32BIT */
10541     { "ldsS",           { Gv, Mp }, 0 },
10542     { VEX_C5_TABLE (VEX_0F) },
10543   },
10544   {
10545     /* MOD_VEX_0F12_PREFIX_0 */
10546     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10547     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10548   },
10549   {
10550     /* MOD_VEX_0F13 */
10551     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10552   },
10553   {
10554     /* MOD_VEX_0F16_PREFIX_0 */
10555     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10556     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10557   },
10558   {
10559     /* MOD_VEX_0F17 */
10560     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10561   },
10562   {
10563     /* MOD_VEX_0F2B */
10564     { "vmovntpX",       { Mx, XM }, 0 },
10565   },
10566   {
10567     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10568     { Bad_Opcode },
10569     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10570   },
10571   {
10572     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10573     { Bad_Opcode },
10574     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10575   },
10576   {
10577     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10578     { Bad_Opcode },
10579     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10583     { Bad_Opcode },
10584     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10588     { Bad_Opcode },
10589     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10593     { Bad_Opcode },
10594     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10608     { Bad_Opcode },
10609     { "knotw",          { MaskG, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10613     { Bad_Opcode },
10614     { "knotq",          { MaskG, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10618     { Bad_Opcode },
10619     { "knotb",          { MaskG, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10623     { Bad_Opcode },
10624     { "knotd",          { MaskG, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10628     { Bad_Opcode },
10629     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10633     { Bad_Opcode },
10634     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10638     { Bad_Opcode },
10639     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10643     { Bad_Opcode },
10644     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10645   },
10646  {
10647     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10648     { Bad_Opcode },
10649     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10653     { Bad_Opcode },
10654     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10658     { Bad_Opcode },
10659     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10663     { Bad_Opcode },
10664     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10673     { Bad_Opcode },
10674     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10693     { Bad_Opcode },
10694     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10698     { Bad_Opcode },
10699     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10703     { Bad_Opcode },
10704     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10708     { Bad_Opcode },
10709     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10713     { Bad_Opcode },
10714     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10718     { Bad_Opcode },
10719     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_0F50 */
10723     { Bad_Opcode },
10724     { "vmovmskpX",      { Gdq, XS }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_0F71_REG_2 */
10728     { Bad_Opcode },
10729     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10730   },
10731   {
10732     /* MOD_VEX_0F71_REG_4 */
10733     { Bad_Opcode },
10734     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10735   },
10736   {
10737     /* MOD_VEX_0F71_REG_6 */
10738     { Bad_Opcode },
10739     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10740   },
10741   {
10742     /* MOD_VEX_0F72_REG_2 */
10743     { Bad_Opcode },
10744     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10745   },
10746   {
10747     /* MOD_VEX_0F72_REG_4 */
10748     { Bad_Opcode },
10749     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10750   },
10751   {
10752     /* MOD_VEX_0F72_REG_6 */
10753     { Bad_Opcode },
10754     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10755   },
10756   {
10757     /* MOD_VEX_0F73_REG_2 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10760   },
10761   {
10762     /* MOD_VEX_0F73_REG_3 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10765   },
10766   {
10767     /* MOD_VEX_0F73_REG_6 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10770   },
10771   {
10772     /* MOD_VEX_0F73_REG_7 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10775   },
10776   {
10777     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10778     { "kmovw",          { Ew, MaskG }, 0 },
10779     { Bad_Opcode },
10780   },
10781   {
10782     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10783     { "kmovq",          { Eq, MaskG }, 0 },
10784     { Bad_Opcode },
10785   },
10786   {
10787     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10788     { "kmovb",          { Eb, MaskG }, 0 },
10789     { Bad_Opcode },
10790   },
10791   {
10792     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10793     { "kmovd",          { Ed, MaskG }, 0 },
10794     { Bad_Opcode },
10795   },
10796   {
10797     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10798     { Bad_Opcode },
10799     { "kmovw",          { MaskG, Rdq }, 0 },
10800   },
10801   {
10802     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10803     { Bad_Opcode },
10804     { "kmovb",          { MaskG, Rdq }, 0 },
10805   },
10806   {
10807     /* MOD_VEX_0F92_P_3_LEN_0 */
10808     { Bad_Opcode },
10809     { "kmovK",          { MaskG, Rdq }, 0 },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10813     { Bad_Opcode },
10814     { "kmovw",          { Gdq, MaskR }, 0 },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10818     { Bad_Opcode },
10819     { "kmovb",          { Gdq, MaskR }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_0F93_P_3_LEN_0 */
10823     { Bad_Opcode },
10824     { "kmovK",          { Gdq, MaskR }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10828     { Bad_Opcode },
10829     { "kortestw", { MaskG, MaskR }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10833     { Bad_Opcode },
10834     { "kortestq", { MaskG, MaskR }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "kortestb", { MaskG, MaskR }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10843     { Bad_Opcode },
10844     { "kortestd", { MaskG, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10848     { Bad_Opcode },
10849     { "ktestw", { MaskG, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10853     { Bad_Opcode },
10854     { "ktestq", { MaskG, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10858     { Bad_Opcode },
10859     { "ktestb", { MaskG, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10863     { Bad_Opcode },
10864     { "ktestd", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_0FAE_REG_2 */
10868     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10869   },
10870   {
10871     /* MOD_VEX_0FAE_REG_3 */
10872     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10873   },
10874   {
10875     /* MOD_VEX_0FD7_PREFIX_2 */
10876     { Bad_Opcode },
10877     { "vpmovmskb",      { Gdq, XS }, 0 },
10878   },
10879   {
10880     /* MOD_VEX_0FE7_PREFIX_2 */
10881     { "vmovntdq",       { Mx, XM }, 0 },
10882   },
10883   {
10884     /* MOD_VEX_0FF0_PREFIX_3 */
10885     { "vlddqu",         { XM, M }, 0 },
10886   },
10887   {
10888     /* MOD_VEX_0F381A_PREFIX_2 */
10889     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10890   },
10891   {
10892     /* MOD_VEX_0F382A_PREFIX_2 */
10893     { "vmovntdqa",      { XM, Mx }, 0 },
10894   },
10895   {
10896     /* MOD_VEX_0F382C_PREFIX_2 */
10897     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10898   },
10899   {
10900     /* MOD_VEX_0F382D_PREFIX_2 */
10901     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10902   },
10903   {
10904     /* MOD_VEX_0F382E_PREFIX_2 */
10905     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10906   },
10907   {
10908     /* MOD_VEX_0F382F_PREFIX_2 */
10909     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10910   },
10911   {
10912     /* MOD_VEX_0F385A_PREFIX_2 */
10913     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10914   },
10915   {
10916     /* MOD_VEX_0F388C_PREFIX_2 */
10917     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10918   },
10919   {
10920     /* MOD_VEX_0F388E_PREFIX_2 */
10921     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10922   },
10923   {
10924     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10925     { Bad_Opcode },
10926     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10927   },
10928   {
10929     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10930     { Bad_Opcode },
10931     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10932   },
10933   {
10934     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10935     { Bad_Opcode },
10936     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10937   },
10938   {
10939     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10940     { Bad_Opcode },
10941     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10942   },
10943   {
10944     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10945     { Bad_Opcode },
10946     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10947   },
10948   {
10949     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10950     { Bad_Opcode },
10951     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10952   },
10953   {
10954     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10955     { Bad_Opcode },
10956     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963
10964 #include "i386-dis-evex-mod.h"
10965 };
10966
10967 static const struct dis386 rm_table[][8] = {
10968   {
10969     /* RM_C6_REG_7 */
10970     { "xabort",         { Skip_MODRM, Ib }, 0 },
10971   },
10972   {
10973     /* RM_C7_REG_7 */
10974     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10975   },
10976   {
10977     /* RM_0F01_REG_0 */
10978     { "enclv",          { Skip_MODRM }, 0 },
10979     { "vmcall",         { Skip_MODRM }, 0 },
10980     { "vmlaunch",       { Skip_MODRM }, 0 },
10981     { "vmresume",       { Skip_MODRM }, 0 },
10982     { "vmxoff",         { Skip_MODRM }, 0 },
10983     { "pconfig",        { Skip_MODRM }, 0 },
10984   },
10985   {
10986     /* RM_0F01_REG_1 */
10987     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10988     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10989     { "clac",           { Skip_MODRM }, 0 },
10990     { "stac",           { Skip_MODRM }, 0 },
10991     { Bad_Opcode },
10992     { Bad_Opcode },
10993     { Bad_Opcode },
10994     { "encls",          { Skip_MODRM }, 0 },
10995   },
10996   {
10997     /* RM_0F01_REG_2 */
10998     { "xgetbv",         { Skip_MODRM }, 0 },
10999     { "xsetbv",         { Skip_MODRM }, 0 },
11000     { Bad_Opcode },
11001     { Bad_Opcode },
11002     { "vmfunc",         { Skip_MODRM }, 0 },
11003     { "xend",           { Skip_MODRM }, 0 },
11004     { "xtest",          { Skip_MODRM }, 0 },
11005     { "enclu",          { Skip_MODRM }, 0 },
11006   },
11007   {
11008     /* RM_0F01_REG_3 */
11009     { "vmrun",          { Skip_MODRM }, 0 },
11010     { "vmmcall",        { Skip_MODRM }, 0 },
11011     { "vmload",         { Skip_MODRM }, 0 },
11012     { "vmsave",         { Skip_MODRM }, 0 },
11013     { "stgi",           { Skip_MODRM }, 0 },
11014     { "clgi",           { Skip_MODRM }, 0 },
11015     { "skinit",         { Skip_MODRM }, 0 },
11016     { "invlpga",        { Skip_MODRM }, 0 },
11017   },
11018   {
11019     /* RM_0F01_REG_5 */
11020     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11021     { Bad_Opcode },
11022     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11023     { Bad_Opcode },
11024     { Bad_Opcode },
11025     { Bad_Opcode },
11026     { "rdpkru",         { Skip_MODRM }, 0 },
11027     { "wrpkru",         { Skip_MODRM }, 0 },
11028   },
11029   {
11030     /* RM_0F01_REG_7 */
11031     { "swapgs",         { Skip_MODRM }, 0  },
11032     { "rdtscp",         { Skip_MODRM }, 0  },
11033     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11034     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11035     { "clzero",         { Skip_MODRM }, 0  },
11036   },
11037   {
11038     /* RM_0F1E_MOD_3_REG_7 */
11039     { "nopQ",           { Ev }, 0 },
11040     { "nopQ",           { Ev }, 0 },
11041     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11042     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11043     { "nopQ",           { Ev }, 0 },
11044     { "nopQ",           { Ev }, 0 },
11045     { "nopQ",           { Ev }, 0 },
11046     { "nopQ",           { Ev }, 0 },
11047   },
11048   {
11049     /* RM_0FAE_REG_6 */
11050     { "mfence",         { Skip_MODRM }, 0 },
11051   },
11052   {
11053     /* RM_0FAE_REG_7 */
11054     { "sfence",         { Skip_MODRM }, 0 },
11055
11056   },
11057 };
11058
11059 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11060
11061 /* We use the high bit to indicate different name for the same
11062    prefix.  */
11063 #define REP_PREFIX      (0xf3 | 0x100)
11064 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11065 #define XRELEASE_PREFIX (0xf3 | 0x400)
11066 #define BND_PREFIX      (0xf2 | 0x400)
11067 #define NOTRACK_PREFIX  (0x3e | 0x100)
11068
11069 static int
11070 ckprefix (void)
11071 {
11072   int newrex, i, length;
11073   rex = 0;
11074   rex_ignored = 0;
11075   prefixes = 0;
11076   used_prefixes = 0;
11077   rex_used = 0;
11078   last_lock_prefix = -1;
11079   last_repz_prefix = -1;
11080   last_repnz_prefix = -1;
11081   last_data_prefix = -1;
11082   last_addr_prefix = -1;
11083   last_rex_prefix = -1;
11084   last_seg_prefix = -1;
11085   fwait_prefix = -1;
11086   active_seg_prefix = 0;
11087   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11088     all_prefixes[i] = 0;
11089   i = 0;
11090   length = 0;
11091   /* The maximum instruction length is 15bytes.  */
11092   while (length < MAX_CODE_LENGTH - 1)
11093     {
11094       FETCH_DATA (the_info, codep + 1);
11095       newrex = 0;
11096       switch (*codep)
11097         {
11098         /* REX prefixes family.  */
11099         case 0x40:
11100         case 0x41:
11101         case 0x42:
11102         case 0x43:
11103         case 0x44:
11104         case 0x45:
11105         case 0x46:
11106         case 0x47:
11107         case 0x48:
11108         case 0x49:
11109         case 0x4a:
11110         case 0x4b:
11111         case 0x4c:
11112         case 0x4d:
11113         case 0x4e:
11114         case 0x4f:
11115           if (address_mode == mode_64bit)
11116             newrex = *codep;
11117           else
11118             return 1;
11119           last_rex_prefix = i;
11120           break;
11121         case 0xf3:
11122           prefixes |= PREFIX_REPZ;
11123           last_repz_prefix = i;
11124           break;
11125         case 0xf2:
11126           prefixes |= PREFIX_REPNZ;
11127           last_repnz_prefix = i;
11128           break;
11129         case 0xf0:
11130           prefixes |= PREFIX_LOCK;
11131           last_lock_prefix = i;
11132           break;
11133         case 0x2e:
11134           prefixes |= PREFIX_CS;
11135           last_seg_prefix = i;
11136           active_seg_prefix = PREFIX_CS;
11137           break;
11138         case 0x36:
11139           prefixes |= PREFIX_SS;
11140           last_seg_prefix = i;
11141           active_seg_prefix = PREFIX_SS;
11142           break;
11143         case 0x3e:
11144           prefixes |= PREFIX_DS;
11145           last_seg_prefix = i;
11146           active_seg_prefix = PREFIX_DS;
11147           break;
11148         case 0x26:
11149           prefixes |= PREFIX_ES;
11150           last_seg_prefix = i;
11151           active_seg_prefix = PREFIX_ES;
11152           break;
11153         case 0x64:
11154           prefixes |= PREFIX_FS;
11155           last_seg_prefix = i;
11156           active_seg_prefix = PREFIX_FS;
11157           break;
11158         case 0x65:
11159           prefixes |= PREFIX_GS;
11160           last_seg_prefix = i;
11161           active_seg_prefix = PREFIX_GS;
11162           break;
11163         case 0x66:
11164           prefixes |= PREFIX_DATA;
11165           last_data_prefix = i;
11166           break;
11167         case 0x67:
11168           prefixes |= PREFIX_ADDR;
11169           last_addr_prefix = i;
11170           break;
11171         case FWAIT_OPCODE:
11172           /* fwait is really an instruction.  If there are prefixes
11173              before the fwait, they belong to the fwait, *not* to the
11174              following instruction.  */
11175           fwait_prefix = i;
11176           if (prefixes || rex)
11177             {
11178               prefixes |= PREFIX_FWAIT;
11179               codep++;
11180               /* This ensures that the previous REX prefixes are noticed
11181                  as unused prefixes, as in the return case below.  */
11182               rex_used = rex;
11183               return 1;
11184             }
11185           prefixes = PREFIX_FWAIT;
11186           break;
11187         default:
11188           return 1;
11189         }
11190       /* Rex is ignored when followed by another prefix.  */
11191       if (rex)
11192         {
11193           rex_used = rex;
11194           return 1;
11195         }
11196       if (*codep != FWAIT_OPCODE)
11197         all_prefixes[i++] = *codep;
11198       rex = newrex;
11199       codep++;
11200       length++;
11201     }
11202   return 0;
11203 }
11204
11205 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11206    prefix byte.  */
11207
11208 static const char *
11209 prefix_name (int pref, int sizeflag)
11210 {
11211   static const char *rexes [16] =
11212     {
11213       "rex",            /* 0x40 */
11214       "rex.B",          /* 0x41 */
11215       "rex.X",          /* 0x42 */
11216       "rex.XB",         /* 0x43 */
11217       "rex.R",          /* 0x44 */
11218       "rex.RB",         /* 0x45 */
11219       "rex.RX",         /* 0x46 */
11220       "rex.RXB",        /* 0x47 */
11221       "rex.W",          /* 0x48 */
11222       "rex.WB",         /* 0x49 */
11223       "rex.WX",         /* 0x4a */
11224       "rex.WXB",        /* 0x4b */
11225       "rex.WR",         /* 0x4c */
11226       "rex.WRB",        /* 0x4d */
11227       "rex.WRX",        /* 0x4e */
11228       "rex.WRXB",       /* 0x4f */
11229     };
11230
11231   switch (pref)
11232     {
11233     /* REX prefixes family.  */
11234     case 0x40:
11235     case 0x41:
11236     case 0x42:
11237     case 0x43:
11238     case 0x44:
11239     case 0x45:
11240     case 0x46:
11241     case 0x47:
11242     case 0x48:
11243     case 0x49:
11244     case 0x4a:
11245     case 0x4b:
11246     case 0x4c:
11247     case 0x4d:
11248     case 0x4e:
11249     case 0x4f:
11250       return rexes [pref - 0x40];
11251     case 0xf3:
11252       return "repz";
11253     case 0xf2:
11254       return "repnz";
11255     case 0xf0:
11256       return "lock";
11257     case 0x2e:
11258       return "cs";
11259     case 0x36:
11260       return "ss";
11261     case 0x3e:
11262       return "ds";
11263     case 0x26:
11264       return "es";
11265     case 0x64:
11266       return "fs";
11267     case 0x65:
11268       return "gs";
11269     case 0x66:
11270       return (sizeflag & DFLAG) ? "data16" : "data32";
11271     case 0x67:
11272       if (address_mode == mode_64bit)
11273         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11274       else
11275         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11276     case FWAIT_OPCODE:
11277       return "fwait";
11278     case REP_PREFIX:
11279       return "rep";
11280     case XACQUIRE_PREFIX:
11281       return "xacquire";
11282     case XRELEASE_PREFIX:
11283       return "xrelease";
11284     case BND_PREFIX:
11285       return "bnd";
11286     case NOTRACK_PREFIX:
11287       return "notrack";
11288     default:
11289       return NULL;
11290     }
11291 }
11292
11293 static char op_out[MAX_OPERANDS][100];
11294 static int op_ad, op_index[MAX_OPERANDS];
11295 static int two_source_ops;
11296 static bfd_vma op_address[MAX_OPERANDS];
11297 static bfd_vma op_riprel[MAX_OPERANDS];
11298 static bfd_vma start_pc;
11299
11300 /*
11301  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11302  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11303  *   section of the "Virtual 8086 Mode" chapter.)
11304  * 'pc' should be the address of this instruction, it will
11305  *   be used to print the target address if this is a relative jump or call
11306  * The function returns the length of this instruction in bytes.
11307  */
11308
11309 static char intel_syntax;
11310 static char intel_mnemonic = !SYSV386_COMPAT;
11311 static char open_char;
11312 static char close_char;
11313 static char separator_char;
11314 static char scale_char;
11315
11316 enum x86_64_isa
11317 {
11318   amd64 = 0,
11319   intel64
11320 };
11321
11322 static enum x86_64_isa isa64;
11323
11324 /* Here for backwards compatibility.  When gdb stops using
11325    print_insn_i386_att and print_insn_i386_intel these functions can
11326    disappear, and print_insn_i386 be merged into print_insn.  */
11327 int
11328 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11329 {
11330   intel_syntax = 0;
11331
11332   return print_insn (pc, info);
11333 }
11334
11335 int
11336 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11337 {
11338   intel_syntax = 1;
11339
11340   return print_insn (pc, info);
11341 }
11342
11343 int
11344 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11345 {
11346   intel_syntax = -1;
11347
11348   return print_insn (pc, info);
11349 }
11350
11351 void
11352 print_i386_disassembler_options (FILE *stream)
11353 {
11354   fprintf (stream, _("\n\
11355 The following i386/x86-64 specific disassembler options are supported for use\n\
11356 with the -M switch (multiple options should be separated by commas):\n"));
11357
11358   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11359   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11360   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11361   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11362   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11363   fprintf (stream, _("  att-mnemonic\n"
11364                      "              Display instruction in AT&T mnemonic\n"));
11365   fprintf (stream, _("  intel-mnemonic\n"
11366                      "              Display instruction in Intel mnemonic\n"));
11367   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11368   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11369   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11370   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11371   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11372   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11373   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11374   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11375 }
11376
11377 /* Bad opcode.  */
11378 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11379
11380 /* Get a pointer to struct dis386 with a valid name.  */
11381
11382 static const struct dis386 *
11383 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11384 {
11385   int vindex, vex_table_index;
11386
11387   if (dp->name != NULL)
11388     return dp;
11389
11390   switch (dp->op[0].bytemode)
11391     {
11392     case USE_REG_TABLE:
11393       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11394       break;
11395
11396     case USE_MOD_TABLE:
11397       vindex = modrm.mod == 0x3 ? 1 : 0;
11398       dp = &mod_table[dp->op[1].bytemode][vindex];
11399       break;
11400
11401     case USE_RM_TABLE:
11402       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11403       break;
11404
11405     case USE_PREFIX_TABLE:
11406       if (need_vex)
11407         {
11408           /* The prefix in VEX is implicit.  */
11409           switch (vex.prefix)
11410             {
11411             case 0:
11412               vindex = 0;
11413               break;
11414             case REPE_PREFIX_OPCODE:
11415               vindex = 1;
11416               break;
11417             case DATA_PREFIX_OPCODE:
11418               vindex = 2;
11419               break;
11420             case REPNE_PREFIX_OPCODE:
11421               vindex = 3;
11422               break;
11423             default:
11424               abort ();
11425               break;
11426             }
11427         }
11428       else
11429         {
11430           int last_prefix = -1;
11431           int prefix = 0;
11432           vindex = 0;
11433           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11434              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11435              last one wins.  */
11436           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11437             {
11438               if (last_repz_prefix > last_repnz_prefix)
11439                 {
11440                   vindex = 1;
11441                   prefix = PREFIX_REPZ;
11442                   last_prefix = last_repz_prefix;
11443                 }
11444               else
11445                 {
11446                   vindex = 3;
11447                   prefix = PREFIX_REPNZ;
11448                   last_prefix = last_repnz_prefix;
11449                 }
11450
11451               /* Check if prefix should be ignored.  */
11452               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11453                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11454                    & prefix) != 0)
11455                 vindex = 0;
11456             }
11457
11458           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11459             {
11460               vindex = 2;
11461               prefix = PREFIX_DATA;
11462               last_prefix = last_data_prefix;
11463             }
11464
11465           if (vindex != 0)
11466             {
11467               used_prefixes |= prefix;
11468               all_prefixes[last_prefix] = 0;
11469             }
11470         }
11471       dp = &prefix_table[dp->op[1].bytemode][vindex];
11472       break;
11473
11474     case USE_X86_64_TABLE:
11475       vindex = address_mode == mode_64bit ? 1 : 0;
11476       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11477       break;
11478
11479     case USE_3BYTE_TABLE:
11480       FETCH_DATA (info, codep + 2);
11481       vindex = *codep++;
11482       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11483       end_codep = codep;
11484       modrm.mod = (*codep >> 6) & 3;
11485       modrm.reg = (*codep >> 3) & 7;
11486       modrm.rm = *codep & 7;
11487       break;
11488
11489     case USE_VEX_LEN_TABLE:
11490       if (!need_vex)
11491         abort ();
11492
11493       switch (vex.length)
11494         {
11495         case 128:
11496           vindex = 0;
11497           break;
11498         case 256:
11499           vindex = 1;
11500           break;
11501         default:
11502           abort ();
11503           break;
11504         }
11505
11506       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11507       break;
11508
11509     case USE_EVEX_LEN_TABLE:
11510       if (!vex.evex)
11511         abort ();
11512
11513       switch (vex.length)
11514         {
11515         case 128:
11516           vindex = 0;
11517           break;
11518         case 256:
11519           vindex = 1;
11520           break;
11521         case 512:
11522           vindex = 2;
11523           break;
11524         default:
11525           abort ();
11526           break;
11527         }
11528
11529       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11530       break;
11531
11532     case USE_XOP_8F_TABLE:
11533       FETCH_DATA (info, codep + 3);
11534       /* All bits in the REX prefix are ignored.  */
11535       rex_ignored = rex;
11536       rex = ~(*codep >> 5) & 0x7;
11537
11538       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11539       switch ((*codep & 0x1f))
11540         {
11541         default:
11542           dp = &bad_opcode;
11543           return dp;
11544         case 0x8:
11545           vex_table_index = XOP_08;
11546           break;
11547         case 0x9:
11548           vex_table_index = XOP_09;
11549           break;
11550         case 0xa:
11551           vex_table_index = XOP_0A;
11552           break;
11553         }
11554       codep++;
11555       vex.w = *codep & 0x80;
11556       if (vex.w && address_mode == mode_64bit)
11557         rex |= REX_W;
11558
11559       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11560       if (address_mode != mode_64bit)
11561         {
11562           /* In 16/32-bit mode REX_B is silently ignored.  */
11563           rex &= ~REX_B;
11564         }
11565
11566       vex.length = (*codep & 0x4) ? 256 : 128;
11567       switch ((*codep & 0x3))
11568         {
11569         case 0:
11570           break;
11571         case 1:
11572           vex.prefix = DATA_PREFIX_OPCODE;
11573           break;
11574         case 2:
11575           vex.prefix = REPE_PREFIX_OPCODE;
11576           break;
11577         case 3:
11578           vex.prefix = REPNE_PREFIX_OPCODE;
11579           break;
11580         }
11581       need_vex = 1;
11582       need_vex_reg = 1;
11583       codep++;
11584       vindex = *codep++;
11585       dp = &xop_table[vex_table_index][vindex];
11586
11587       end_codep = codep;
11588       FETCH_DATA (info, codep + 1);
11589       modrm.mod = (*codep >> 6) & 3;
11590       modrm.reg = (*codep >> 3) & 7;
11591       modrm.rm = *codep & 7;
11592       break;
11593
11594     case USE_VEX_C4_TABLE:
11595       /* VEX prefix.  */
11596       FETCH_DATA (info, codep + 3);
11597       /* All bits in the REX prefix are ignored.  */
11598       rex_ignored = rex;
11599       rex = ~(*codep >> 5) & 0x7;
11600       switch ((*codep & 0x1f))
11601         {
11602         default:
11603           dp = &bad_opcode;
11604           return dp;
11605         case 0x1:
11606           vex_table_index = VEX_0F;
11607           break;
11608         case 0x2:
11609           vex_table_index = VEX_0F38;
11610           break;
11611         case 0x3:
11612           vex_table_index = VEX_0F3A;
11613           break;
11614         }
11615       codep++;
11616       vex.w = *codep & 0x80;
11617       if (address_mode == mode_64bit)
11618         {
11619           if (vex.w)
11620             rex |= REX_W;
11621         }
11622       else
11623         {
11624           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11625              is ignored, other REX bits are 0 and the highest bit in
11626              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11627           rex = 0;
11628         }
11629       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11630       vex.length = (*codep & 0x4) ? 256 : 128;
11631       switch ((*codep & 0x3))
11632         {
11633         case 0:
11634           break;
11635         case 1:
11636           vex.prefix = DATA_PREFIX_OPCODE;
11637           break;
11638         case 2:
11639           vex.prefix = REPE_PREFIX_OPCODE;
11640           break;
11641         case 3:
11642           vex.prefix = REPNE_PREFIX_OPCODE;
11643           break;
11644         }
11645       need_vex = 1;
11646       need_vex_reg = 1;
11647       codep++;
11648       vindex = *codep++;
11649       dp = &vex_table[vex_table_index][vindex];
11650       end_codep = codep;
11651       /* There is no MODRM byte for VEX0F 77.  */
11652       if (vex_table_index != VEX_0F || vindex != 0x77)
11653         {
11654           FETCH_DATA (info, codep + 1);
11655           modrm.mod = (*codep >> 6) & 3;
11656           modrm.reg = (*codep >> 3) & 7;
11657           modrm.rm = *codep & 7;
11658         }
11659       break;
11660
11661     case USE_VEX_C5_TABLE:
11662       /* VEX prefix.  */
11663       FETCH_DATA (info, codep + 2);
11664       /* All bits in the REX prefix are ignored.  */
11665       rex_ignored = rex;
11666       rex = (*codep & 0x80) ? 0 : REX_R;
11667
11668       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11669          VEX.vvvv is 1.  */
11670       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11671       vex.length = (*codep & 0x4) ? 256 : 128;
11672       switch ((*codep & 0x3))
11673         {
11674         case 0:
11675           break;
11676         case 1:
11677           vex.prefix = DATA_PREFIX_OPCODE;
11678           break;
11679         case 2:
11680           vex.prefix = REPE_PREFIX_OPCODE;
11681           break;
11682         case 3:
11683           vex.prefix = REPNE_PREFIX_OPCODE;
11684           break;
11685         }
11686       need_vex = 1;
11687       need_vex_reg = 1;
11688       codep++;
11689       vindex = *codep++;
11690       dp = &vex_table[dp->op[1].bytemode][vindex];
11691       end_codep = codep;
11692       /* There is no MODRM byte for VEX 77.  */
11693       if (vindex != 0x77)
11694         {
11695           FETCH_DATA (info, codep + 1);
11696           modrm.mod = (*codep >> 6) & 3;
11697           modrm.reg = (*codep >> 3) & 7;
11698           modrm.rm = *codep & 7;
11699         }
11700       break;
11701
11702     case USE_VEX_W_TABLE:
11703       if (!need_vex)
11704         abort ();
11705
11706       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11707       break;
11708
11709     case USE_EVEX_TABLE:
11710       two_source_ops = 0;
11711       /* EVEX prefix.  */
11712       vex.evex = 1;
11713       FETCH_DATA (info, codep + 4);
11714       /* All bits in the REX prefix are ignored.  */
11715       rex_ignored = rex;
11716       /* The first byte after 0x62.  */
11717       rex = ~(*codep >> 5) & 0x7;
11718       vex.r = *codep & 0x10;
11719       switch ((*codep & 0xf))
11720         {
11721         default:
11722           return &bad_opcode;
11723         case 0x1:
11724           vex_table_index = EVEX_0F;
11725           break;
11726         case 0x2:
11727           vex_table_index = EVEX_0F38;
11728           break;
11729         case 0x3:
11730           vex_table_index = EVEX_0F3A;
11731           break;
11732         }
11733
11734       /* The second byte after 0x62.  */
11735       codep++;
11736       vex.w = *codep & 0x80;
11737       if (vex.w && address_mode == mode_64bit)
11738         rex |= REX_W;
11739
11740       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11741
11742       /* The U bit.  */
11743       if (!(*codep & 0x4))
11744         return &bad_opcode;
11745
11746       switch ((*codep & 0x3))
11747         {
11748         case 0:
11749           break;
11750         case 1:
11751           vex.prefix = DATA_PREFIX_OPCODE;
11752           break;
11753         case 2:
11754           vex.prefix = REPE_PREFIX_OPCODE;
11755           break;
11756         case 3:
11757           vex.prefix = REPNE_PREFIX_OPCODE;
11758           break;
11759         }
11760
11761       /* The third byte after 0x62.  */
11762       codep++;
11763
11764       /* Remember the static rounding bits.  */
11765       vex.ll = (*codep >> 5) & 3;
11766       vex.b = (*codep & 0x10) != 0;
11767
11768       vex.v = *codep & 0x8;
11769       vex.mask_register_specifier = *codep & 0x7;
11770       vex.zeroing = *codep & 0x80;
11771
11772       if (address_mode != mode_64bit)
11773         {
11774           /* In 16/32-bit mode silently ignore following bits.  */
11775           rex &= ~REX_B;
11776           vex.r = 1;
11777           vex.v = 1;
11778         }
11779
11780       need_vex = 1;
11781       need_vex_reg = 1;
11782       codep++;
11783       vindex = *codep++;
11784       dp = &evex_table[vex_table_index][vindex];
11785       end_codep = codep;
11786       FETCH_DATA (info, codep + 1);
11787       modrm.mod = (*codep >> 6) & 3;
11788       modrm.reg = (*codep >> 3) & 7;
11789       modrm.rm = *codep & 7;
11790
11791       /* Set vector length.  */
11792       if (modrm.mod == 3 && vex.b)
11793         vex.length = 512;
11794       else
11795         {
11796           switch (vex.ll)
11797             {
11798             case 0x0:
11799               vex.length = 128;
11800               break;
11801             case 0x1:
11802               vex.length = 256;
11803               break;
11804             case 0x2:
11805               vex.length = 512;
11806               break;
11807             default:
11808               return &bad_opcode;
11809             }
11810         }
11811       break;
11812
11813     case 0:
11814       dp = &bad_opcode;
11815       break;
11816
11817     default:
11818       abort ();
11819     }
11820
11821   if (dp->name != NULL)
11822     return dp;
11823   else
11824     return get_valid_dis386 (dp, info);
11825 }
11826
11827 static void
11828 get_sib (disassemble_info *info, int sizeflag)
11829 {
11830   /* If modrm.mod == 3, operand must be register.  */
11831   if (need_modrm
11832       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11833       && modrm.mod != 3
11834       && modrm.rm == 4)
11835     {
11836       FETCH_DATA (info, codep + 2);
11837       sib.index = (codep [1] >> 3) & 7;
11838       sib.scale = (codep [1] >> 6) & 3;
11839       sib.base = codep [1] & 7;
11840     }
11841 }
11842
11843 static int
11844 print_insn (bfd_vma pc, disassemble_info *info)
11845 {
11846   const struct dis386 *dp;
11847   int i;
11848   char *op_txt[MAX_OPERANDS];
11849   int needcomma;
11850   int sizeflag, orig_sizeflag;
11851   const char *p;
11852   struct dis_private priv;
11853   int prefix_length;
11854
11855   priv.orig_sizeflag = AFLAG | DFLAG;
11856   if ((info->mach & bfd_mach_i386_i386) != 0)
11857     address_mode = mode_32bit;
11858   else if (info->mach == bfd_mach_i386_i8086)
11859     {
11860       address_mode = mode_16bit;
11861       priv.orig_sizeflag = 0;
11862     }
11863   else
11864     address_mode = mode_64bit;
11865
11866   if (intel_syntax == (char) -1)
11867     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11868
11869   for (p = info->disassembler_options; p != NULL; )
11870     {
11871       if (CONST_STRNEQ (p, "amd64"))
11872         isa64 = amd64;
11873       else if (CONST_STRNEQ (p, "intel64"))
11874         isa64 = intel64;
11875       else if (CONST_STRNEQ (p, "x86-64"))
11876         {
11877           address_mode = mode_64bit;
11878           priv.orig_sizeflag = AFLAG | DFLAG;
11879         }
11880       else if (CONST_STRNEQ (p, "i386"))
11881         {
11882           address_mode = mode_32bit;
11883           priv.orig_sizeflag = AFLAG | DFLAG;
11884         }
11885       else if (CONST_STRNEQ (p, "i8086"))
11886         {
11887           address_mode = mode_16bit;
11888           priv.orig_sizeflag = 0;
11889         }
11890       else if (CONST_STRNEQ (p, "intel"))
11891         {
11892           intel_syntax = 1;
11893           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11894             intel_mnemonic = 1;
11895         }
11896       else if (CONST_STRNEQ (p, "att"))
11897         {
11898           intel_syntax = 0;
11899           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11900             intel_mnemonic = 0;
11901         }
11902       else if (CONST_STRNEQ (p, "addr"))
11903         {
11904           if (address_mode == mode_64bit)
11905             {
11906               if (p[4] == '3' && p[5] == '2')
11907                 priv.orig_sizeflag &= ~AFLAG;
11908               else if (p[4] == '6' && p[5] == '4')
11909                 priv.orig_sizeflag |= AFLAG;
11910             }
11911           else
11912             {
11913               if (p[4] == '1' && p[5] == '6')
11914                 priv.orig_sizeflag &= ~AFLAG;
11915               else if (p[4] == '3' && p[5] == '2')
11916                 priv.orig_sizeflag |= AFLAG;
11917             }
11918         }
11919       else if (CONST_STRNEQ (p, "data"))
11920         {
11921           if (p[4] == '1' && p[5] == '6')
11922             priv.orig_sizeflag &= ~DFLAG;
11923           else if (p[4] == '3' && p[5] == '2')
11924             priv.orig_sizeflag |= DFLAG;
11925         }
11926       else if (CONST_STRNEQ (p, "suffix"))
11927         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11928
11929       p = strchr (p, ',');
11930       if (p != NULL)
11931         p++;
11932     }
11933
11934   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11935     {
11936       (*info->fprintf_func) (info->stream,
11937                              _("64-bit address is disabled"));
11938       return -1;
11939     }
11940
11941   if (intel_syntax)
11942     {
11943       names64 = intel_names64;
11944       names32 = intel_names32;
11945       names16 = intel_names16;
11946       names8 = intel_names8;
11947       names8rex = intel_names8rex;
11948       names_seg = intel_names_seg;
11949       names_mm = intel_names_mm;
11950       names_bnd = intel_names_bnd;
11951       names_xmm = intel_names_xmm;
11952       names_ymm = intel_names_ymm;
11953       names_zmm = intel_names_zmm;
11954       index64 = intel_index64;
11955       index32 = intel_index32;
11956       names_mask = intel_names_mask;
11957       index16 = intel_index16;
11958       open_char = '[';
11959       close_char = ']';
11960       separator_char = '+';
11961       scale_char = '*';
11962     }
11963   else
11964     {
11965       names64 = att_names64;
11966       names32 = att_names32;
11967       names16 = att_names16;
11968       names8 = att_names8;
11969       names8rex = att_names8rex;
11970       names_seg = att_names_seg;
11971       names_mm = att_names_mm;
11972       names_bnd = att_names_bnd;
11973       names_xmm = att_names_xmm;
11974       names_ymm = att_names_ymm;
11975       names_zmm = att_names_zmm;
11976       index64 = att_index64;
11977       index32 = att_index32;
11978       names_mask = att_names_mask;
11979       index16 = att_index16;
11980       open_char = '(';
11981       close_char =  ')';
11982       separator_char = ',';
11983       scale_char = ',';
11984     }
11985
11986   /* The output looks better if we put 7 bytes on a line, since that
11987      puts most long word instructions on a single line.  Use 8 bytes
11988      for Intel L1OM.  */
11989   if ((info->mach & bfd_mach_l1om) != 0)
11990     info->bytes_per_line = 8;
11991   else
11992     info->bytes_per_line = 7;
11993
11994   info->private_data = &priv;
11995   priv.max_fetched = priv.the_buffer;
11996   priv.insn_start = pc;
11997
11998   obuf[0] = 0;
11999   for (i = 0; i < MAX_OPERANDS; ++i)
12000     {
12001       op_out[i][0] = 0;
12002       op_index[i] = -1;
12003     }
12004
12005   the_info = info;
12006   start_pc = pc;
12007   start_codep = priv.the_buffer;
12008   codep = priv.the_buffer;
12009
12010   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12011     {
12012       const char *name;
12013
12014       /* Getting here means we tried for data but didn't get it.  That
12015          means we have an incomplete instruction of some sort.  Just
12016          print the first byte as a prefix or a .byte pseudo-op.  */
12017       if (codep > priv.the_buffer)
12018         {
12019           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12020           if (name != NULL)
12021             (*info->fprintf_func) (info->stream, "%s", name);
12022           else
12023             {
12024               /* Just print the first byte as a .byte instruction.  */
12025               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12026                                      (unsigned int) priv.the_buffer[0]);
12027             }
12028
12029           return 1;
12030         }
12031
12032       return -1;
12033     }
12034
12035   obufp = obuf;
12036   sizeflag = priv.orig_sizeflag;
12037
12038   if (!ckprefix () || rex_used)
12039     {
12040       /* Too many prefixes or unused REX prefixes.  */
12041       for (i = 0;
12042            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12043            i++)
12044         (*info->fprintf_func) (info->stream, "%s%s",
12045                                i == 0 ? "" : " ",
12046                                prefix_name (all_prefixes[i], sizeflag));
12047       return i;
12048     }
12049
12050   insn_codep = codep;
12051
12052   FETCH_DATA (info, codep + 1);
12053   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12054
12055   if (((prefixes & PREFIX_FWAIT)
12056        && ((*codep < 0xd8) || (*codep > 0xdf))))
12057     {
12058       /* Handle prefixes before fwait.  */
12059       for (i = 0; i < fwait_prefix && all_prefixes[i];
12060            i++)
12061         (*info->fprintf_func) (info->stream, "%s ",
12062                                prefix_name (all_prefixes[i], sizeflag));
12063       (*info->fprintf_func) (info->stream, "fwait");
12064       return i + 1;
12065     }
12066
12067   if (*codep == 0x0f)
12068     {
12069       unsigned char threebyte;
12070
12071       codep++;
12072       FETCH_DATA (info, codep + 1);
12073       threebyte = *codep;
12074       dp = &dis386_twobyte[threebyte];
12075       need_modrm = twobyte_has_modrm[*codep];
12076       codep++;
12077     }
12078   else
12079     {
12080       dp = &dis386[*codep];
12081       need_modrm = onebyte_has_modrm[*codep];
12082       codep++;
12083     }
12084
12085   /* Save sizeflag for printing the extra prefixes later before updating
12086      it for mnemonic and operand processing.  The prefix names depend
12087      only on the address mode.  */
12088   orig_sizeflag = sizeflag;
12089   if (prefixes & PREFIX_ADDR)
12090     sizeflag ^= AFLAG;
12091   if ((prefixes & PREFIX_DATA))
12092     sizeflag ^= DFLAG;
12093
12094   end_codep = codep;
12095   if (need_modrm)
12096     {
12097       FETCH_DATA (info, codep + 1);
12098       modrm.mod = (*codep >> 6) & 3;
12099       modrm.reg = (*codep >> 3) & 7;
12100       modrm.rm = *codep & 7;
12101     }
12102
12103   need_vex = 0;
12104   need_vex_reg = 0;
12105   vex_w_done = 0;
12106   memset (&vex, 0, sizeof (vex));
12107
12108   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12109     {
12110       get_sib (info, sizeflag);
12111       dofloat (sizeflag);
12112     }
12113   else
12114     {
12115       dp = get_valid_dis386 (dp, info);
12116       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12117         {
12118           get_sib (info, sizeflag);
12119           for (i = 0; i < MAX_OPERANDS; ++i)
12120             {
12121               obufp = op_out[i];
12122               op_ad = MAX_OPERANDS - 1 - i;
12123               if (dp->op[i].rtn)
12124                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12125               /* For EVEX instruction after the last operand masking
12126                  should be printed.  */
12127               if (i == 0 && vex.evex)
12128                 {
12129                   /* Don't print {%k0}.  */
12130                   if (vex.mask_register_specifier)
12131                     {
12132                       oappend ("{");
12133                       oappend (names_mask[vex.mask_register_specifier]);
12134                       oappend ("}");
12135                     }
12136                   if (vex.zeroing)
12137                     oappend ("{z}");
12138                 }
12139             }
12140         }
12141     }
12142
12143   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12144      are all 0s in inverted form.  */
12145   if (need_vex && vex.register_specifier != 0)
12146     {
12147       (*info->fprintf_func) (info->stream, "(bad)");
12148       return end_codep - priv.the_buffer;
12149     }
12150
12151   /* Check if the REX prefix is used.  */
12152   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12153     all_prefixes[last_rex_prefix] = 0;
12154
12155   /* Check if the SEG prefix is used.  */
12156   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12157                    | PREFIX_FS | PREFIX_GS)) != 0
12158       && (used_prefixes & active_seg_prefix) != 0)
12159     all_prefixes[last_seg_prefix] = 0;
12160
12161   /* Check if the ADDR prefix is used.  */
12162   if ((prefixes & PREFIX_ADDR) != 0
12163       && (used_prefixes & PREFIX_ADDR) != 0)
12164     all_prefixes[last_addr_prefix] = 0;
12165
12166   /* Check if the DATA prefix is used.  */
12167   if ((prefixes & PREFIX_DATA) != 0
12168       && (used_prefixes & PREFIX_DATA) != 0)
12169     all_prefixes[last_data_prefix] = 0;
12170
12171   /* Print the extra prefixes.  */
12172   prefix_length = 0;
12173   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12174     if (all_prefixes[i])
12175       {
12176         const char *name;
12177         name = prefix_name (all_prefixes[i], orig_sizeflag);
12178         if (name == NULL)
12179           abort ();
12180         prefix_length += strlen (name) + 1;
12181         (*info->fprintf_func) (info->stream, "%s ", name);
12182       }
12183
12184   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12185      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12186      used by putop and MMX/SSE operand and may be overriden by the
12187      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12188      separately.  */
12189   if (dp->prefix_requirement == PREFIX_OPCODE
12190       && dp != &bad_opcode
12191       && (((prefixes
12192             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12193            && (used_prefixes
12194                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12195           || ((((prefixes
12196                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12197                 == PREFIX_DATA)
12198                && (used_prefixes & PREFIX_DATA) == 0))))
12199     {
12200       (*info->fprintf_func) (info->stream, "(bad)");
12201       return end_codep - priv.the_buffer;
12202     }
12203
12204   /* Check maximum code length.  */
12205   if ((codep - start_codep) > MAX_CODE_LENGTH)
12206     {
12207       (*info->fprintf_func) (info->stream, "(bad)");
12208       return MAX_CODE_LENGTH;
12209     }
12210
12211   obufp = mnemonicendp;
12212   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12213     oappend (" ");
12214   oappend (" ");
12215   (*info->fprintf_func) (info->stream, "%s", obuf);
12216
12217   /* The enter and bound instructions are printed with operands in the same
12218      order as the intel book; everything else is printed in reverse order.  */
12219   if (intel_syntax || two_source_ops)
12220     {
12221       bfd_vma riprel;
12222
12223       for (i = 0; i < MAX_OPERANDS; ++i)
12224         op_txt[i] = op_out[i];
12225
12226       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12227           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12228         {
12229           op_txt[2] = op_out[3];
12230           op_txt[3] = op_out[2];
12231         }
12232
12233       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12234         {
12235           op_ad = op_index[i];
12236           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12237           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12238           riprel = op_riprel[i];
12239           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12240           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12241         }
12242     }
12243   else
12244     {
12245       for (i = 0; i < MAX_OPERANDS; ++i)
12246         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12247     }
12248
12249   needcomma = 0;
12250   for (i = 0; i < MAX_OPERANDS; ++i)
12251     if (*op_txt[i])
12252       {
12253         if (needcomma)
12254           (*info->fprintf_func) (info->stream, ",");
12255         if (op_index[i] != -1 && !op_riprel[i])
12256           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12257         else
12258           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12259         needcomma = 1;
12260       }
12261
12262   for (i = 0; i < MAX_OPERANDS; i++)
12263     if (op_index[i] != -1 && op_riprel[i])
12264       {
12265         (*info->fprintf_func) (info->stream, "        # ");
12266         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12267                                                 + op_address[op_index[i]]), info);
12268         break;
12269       }
12270   return codep - priv.the_buffer;
12271 }
12272
12273 static const char *float_mem[] = {
12274   /* d8 */
12275   "fadd{s|}",
12276   "fmul{s|}",
12277   "fcom{s|}",
12278   "fcomp{s|}",
12279   "fsub{s|}",
12280   "fsubr{s|}",
12281   "fdiv{s|}",
12282   "fdivr{s|}",
12283   /* d9 */
12284   "fld{s|}",
12285   "(bad)",
12286   "fst{s|}",
12287   "fstp{s|}",
12288   "fldenvIC",
12289   "fldcw",
12290   "fNstenvIC",
12291   "fNstcw",
12292   /* da */
12293   "fiadd{l|}",
12294   "fimul{l|}",
12295   "ficom{l|}",
12296   "ficomp{l|}",
12297   "fisub{l|}",
12298   "fisubr{l|}",
12299   "fidiv{l|}",
12300   "fidivr{l|}",
12301   /* db */
12302   "fild{l|}",
12303   "fisttp{l|}",
12304   "fist{l|}",
12305   "fistp{l|}",
12306   "(bad)",
12307   "fld{t||t|}",
12308   "(bad)",
12309   "fstp{t||t|}",
12310   /* dc */
12311   "fadd{l|}",
12312   "fmul{l|}",
12313   "fcom{l|}",
12314   "fcomp{l|}",
12315   "fsub{l|}",
12316   "fsubr{l|}",
12317   "fdiv{l|}",
12318   "fdivr{l|}",
12319   /* dd */
12320   "fld{l|}",
12321   "fisttp{ll|}",
12322   "fst{l||}",
12323   "fstp{l|}",
12324   "frstorIC",
12325   "(bad)",
12326   "fNsaveIC",
12327   "fNstsw",
12328   /* de */
12329   "fiadd{s|}",
12330   "fimul{s|}",
12331   "ficom{s|}",
12332   "ficomp{s|}",
12333   "fisub{s|}",
12334   "fisubr{s|}",
12335   "fidiv{s|}",
12336   "fidivr{s|}",
12337   /* df */
12338   "fild{s|}",
12339   "fisttp{s|}",
12340   "fist{s|}",
12341   "fistp{s|}",
12342   "fbld",
12343   "fild{ll|}",
12344   "fbstp",
12345   "fistp{ll|}",
12346 };
12347
12348 static const unsigned char float_mem_mode[] = {
12349   /* d8 */
12350   d_mode,
12351   d_mode,
12352   d_mode,
12353   d_mode,
12354   d_mode,
12355   d_mode,
12356   d_mode,
12357   d_mode,
12358   /* d9 */
12359   d_mode,
12360   0,
12361   d_mode,
12362   d_mode,
12363   0,
12364   w_mode,
12365   0,
12366   w_mode,
12367   /* da */
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   d_mode,
12374   d_mode,
12375   d_mode,
12376   /* db */
12377   d_mode,
12378   d_mode,
12379   d_mode,
12380   d_mode,
12381   0,
12382   t_mode,
12383   0,
12384   t_mode,
12385   /* dc */
12386   q_mode,
12387   q_mode,
12388   q_mode,
12389   q_mode,
12390   q_mode,
12391   q_mode,
12392   q_mode,
12393   q_mode,
12394   /* dd */
12395   q_mode,
12396   q_mode,
12397   q_mode,
12398   q_mode,
12399   0,
12400   0,
12401   0,
12402   w_mode,
12403   /* de */
12404   w_mode,
12405   w_mode,
12406   w_mode,
12407   w_mode,
12408   w_mode,
12409   w_mode,
12410   w_mode,
12411   w_mode,
12412   /* df */
12413   w_mode,
12414   w_mode,
12415   w_mode,
12416   w_mode,
12417   t_mode,
12418   q_mode,
12419   t_mode,
12420   q_mode
12421 };
12422
12423 #define ST { OP_ST, 0 }
12424 #define STi { OP_STi, 0 }
12425
12426 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12427 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12428 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12429 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12430 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12431 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12432 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12433 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12434 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12435
12436 static const struct dis386 float_reg[][8] = {
12437   /* d8 */
12438   {
12439     { "fadd",   { ST, STi }, 0 },
12440     { "fmul",   { ST, STi }, 0 },
12441     { "fcom",   { STi }, 0 },
12442     { "fcomp",  { STi }, 0 },
12443     { "fsub",   { ST, STi }, 0 },
12444     { "fsubr",  { ST, STi }, 0 },
12445     { "fdiv",   { ST, STi }, 0 },
12446     { "fdivr",  { ST, STi }, 0 },
12447   },
12448   /* d9 */
12449   {
12450     { "fld",    { STi }, 0 },
12451     { "fxch",   { STi }, 0 },
12452     { FGRPd9_2 },
12453     { Bad_Opcode },
12454     { FGRPd9_4 },
12455     { FGRPd9_5 },
12456     { FGRPd9_6 },
12457     { FGRPd9_7 },
12458   },
12459   /* da */
12460   {
12461     { "fcmovb", { ST, STi }, 0 },
12462     { "fcmove", { ST, STi }, 0 },
12463     { "fcmovbe",{ ST, STi }, 0 },
12464     { "fcmovu", { ST, STi }, 0 },
12465     { Bad_Opcode },
12466     { FGRPda_5 },
12467     { Bad_Opcode },
12468     { Bad_Opcode },
12469   },
12470   /* db */
12471   {
12472     { "fcmovnb",{ ST, STi }, 0 },
12473     { "fcmovne",{ ST, STi }, 0 },
12474     { "fcmovnbe",{ ST, STi }, 0 },
12475     { "fcmovnu",{ ST, STi }, 0 },
12476     { FGRPdb_4 },
12477     { "fucomi", { ST, STi }, 0 },
12478     { "fcomi",  { ST, STi }, 0 },
12479     { Bad_Opcode },
12480   },
12481   /* dc */
12482   {
12483     { "fadd",   { STi, ST }, 0 },
12484     { "fmul",   { STi, ST }, 0 },
12485     { Bad_Opcode },
12486     { Bad_Opcode },
12487     { "fsub{!M|r}",     { STi, ST }, 0 },
12488     { "fsub{M|}",       { STi, ST }, 0 },
12489     { "fdiv{!M|r}",     { STi, ST }, 0 },
12490     { "fdiv{M|}",       { STi, ST }, 0 },
12491   },
12492   /* dd */
12493   {
12494     { "ffree",  { STi }, 0 },
12495     { Bad_Opcode },
12496     { "fst",    { STi }, 0 },
12497     { "fstp",   { STi }, 0 },
12498     { "fucom",  { STi }, 0 },
12499     { "fucomp", { STi }, 0 },
12500     { Bad_Opcode },
12501     { Bad_Opcode },
12502   },
12503   /* de */
12504   {
12505     { "faddp",  { STi, ST }, 0 },
12506     { "fmulp",  { STi, ST }, 0 },
12507     { Bad_Opcode },
12508     { FGRPde_3 },
12509     { "fsub{!M|r}p",    { STi, ST }, 0 },
12510     { "fsub{M|}p",      { STi, ST }, 0 },
12511     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12512     { "fdiv{M|}p",      { STi, ST }, 0 },
12513   },
12514   /* df */
12515   {
12516     { "ffreep", { STi }, 0 },
12517     { Bad_Opcode },
12518     { Bad_Opcode },
12519     { Bad_Opcode },
12520     { FGRPdf_4 },
12521     { "fucomip", { ST, STi }, 0 },
12522     { "fcomip", { ST, STi }, 0 },
12523     { Bad_Opcode },
12524   },
12525 };
12526
12527 static char *fgrps[][8] = {
12528   /* Bad opcode 0 */
12529   {
12530     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12531   },
12532
12533   /* d9_2  1 */
12534   {
12535     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12536   },
12537
12538   /* d9_4  2 */
12539   {
12540     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12541   },
12542
12543   /* d9_5  3 */
12544   {
12545     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12546   },
12547
12548   /* d9_6  4 */
12549   {
12550     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12551   },
12552
12553   /* d9_7  5 */
12554   {
12555     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12556   },
12557
12558   /* da_5  6 */
12559   {
12560     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12561   },
12562
12563   /* db_4  7 */
12564   {
12565     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12566     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12567   },
12568
12569   /* de_3  8 */
12570   {
12571     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12572   },
12573
12574   /* df_4  9 */
12575   {
12576     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12577   },
12578 };
12579
12580 static void
12581 swap_operand (void)
12582 {
12583   mnemonicendp[0] = '.';
12584   mnemonicendp[1] = 's';
12585   mnemonicendp += 2;
12586 }
12587
12588 static void
12589 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12590                int sizeflag ATTRIBUTE_UNUSED)
12591 {
12592   /* Skip mod/rm byte.  */
12593   MODRM_CHECK;
12594   codep++;
12595 }
12596
12597 static void
12598 dofloat (int sizeflag)
12599 {
12600   const struct dis386 *dp;
12601   unsigned char floatop;
12602
12603   floatop = codep[-1];
12604
12605   if (modrm.mod != 3)
12606     {
12607       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12608
12609       putop (float_mem[fp_indx], sizeflag);
12610       obufp = op_out[0];
12611       op_ad = 2;
12612       OP_E (float_mem_mode[fp_indx], sizeflag);
12613       return;
12614     }
12615   /* Skip mod/rm byte.  */
12616   MODRM_CHECK;
12617   codep++;
12618
12619   dp = &float_reg[floatop - 0xd8][modrm.reg];
12620   if (dp->name == NULL)
12621     {
12622       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12623
12624       /* Instruction fnstsw is only one with strange arg.  */
12625       if (floatop == 0xdf && codep[-1] == 0xe0)
12626         strcpy (op_out[0], names16[0]);
12627     }
12628   else
12629     {
12630       putop (dp->name, sizeflag);
12631
12632       obufp = op_out[0];
12633       op_ad = 2;
12634       if (dp->op[0].rtn)
12635         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12636
12637       obufp = op_out[1];
12638       op_ad = 1;
12639       if (dp->op[1].rtn)
12640         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12641     }
12642 }
12643
12644 /* Like oappend (below), but S is a string starting with '%'.
12645    In Intel syntax, the '%' is elided.  */
12646 static void
12647 oappend_maybe_intel (const char *s)
12648 {
12649   oappend (s + intel_syntax);
12650 }
12651
12652 static void
12653 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12654 {
12655   oappend_maybe_intel ("%st");
12656 }
12657
12658 static void
12659 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12660 {
12661   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12662   oappend_maybe_intel (scratchbuf);
12663 }
12664
12665 /* Capital letters in template are macros.  */
12666 static int
12667 putop (const char *in_template, int sizeflag)
12668 {
12669   const char *p;
12670   int alt = 0;
12671   int cond = 1;
12672   unsigned int l = 0, len = 1;
12673   char last[4];
12674
12675 #define SAVE_LAST(c)                    \
12676   if (l < len && l < sizeof (last))     \
12677     last[l++] = c;                      \
12678   else                                  \
12679     abort ();
12680
12681   for (p = in_template; *p; p++)
12682     {
12683       switch (*p)
12684         {
12685         default:
12686           *obufp++ = *p;
12687           break;
12688         case '%':
12689           len++;
12690           break;
12691         case '!':
12692           cond = 0;
12693           break;
12694         case '{':
12695           if (intel_syntax)
12696             {
12697               while (*++p != '|')
12698                 if (*p == '}' || *p == '\0')
12699                   abort ();
12700             }
12701           /* Fall through.  */
12702         case 'I':
12703           alt = 1;
12704           continue;
12705         case '|':
12706           while (*++p != '}')
12707             {
12708               if (*p == '\0')
12709                 abort ();
12710             }
12711           break;
12712         case '}':
12713           break;
12714         case 'A':
12715           if (intel_syntax)
12716             break;
12717           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12718             *obufp++ = 'b';
12719           break;
12720         case 'B':
12721           if (l == 0 && len == 1)
12722             {
12723 case_B:
12724               if (intel_syntax)
12725                 break;
12726               if (sizeflag & SUFFIX_ALWAYS)
12727                 *obufp++ = 'b';
12728             }
12729           else
12730             {
12731               if (l != 1
12732                   || len != 2
12733                   || last[0] != 'L')
12734                 {
12735                   SAVE_LAST (*p);
12736                   break;
12737                 }
12738
12739               if (address_mode == mode_64bit
12740                   && !(prefixes & PREFIX_ADDR))
12741                 {
12742                   *obufp++ = 'a';
12743                   *obufp++ = 'b';
12744                   *obufp++ = 's';
12745                 }
12746
12747               goto case_B;
12748             }
12749           break;
12750         case 'C':
12751           if (intel_syntax && !alt)
12752             break;
12753           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12754             {
12755               if (sizeflag & DFLAG)
12756                 *obufp++ = intel_syntax ? 'd' : 'l';
12757               else
12758                 *obufp++ = intel_syntax ? 'w' : 's';
12759               used_prefixes |= (prefixes & PREFIX_DATA);
12760             }
12761           break;
12762         case 'D':
12763           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12764             break;
12765           USED_REX (REX_W);
12766           if (modrm.mod == 3)
12767             {
12768               if (rex & REX_W)
12769                 *obufp++ = 'q';
12770               else
12771                 {
12772                   if (sizeflag & DFLAG)
12773                     *obufp++ = intel_syntax ? 'd' : 'l';
12774                   else
12775                     *obufp++ = 'w';
12776                   used_prefixes |= (prefixes & PREFIX_DATA);
12777                 }
12778             }
12779           else
12780             *obufp++ = 'w';
12781           break;
12782         case 'E':               /* For jcxz/jecxz */
12783           if (address_mode == mode_64bit)
12784             {
12785               if (sizeflag & AFLAG)
12786                 *obufp++ = 'r';
12787               else
12788                 *obufp++ = 'e';
12789             }
12790           else
12791             if (sizeflag & AFLAG)
12792               *obufp++ = 'e';
12793           used_prefixes |= (prefixes & PREFIX_ADDR);
12794           break;
12795         case 'F':
12796           if (intel_syntax)
12797             break;
12798           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12799             {
12800               if (sizeflag & AFLAG)
12801                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12802               else
12803                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12804               used_prefixes |= (prefixes & PREFIX_ADDR);
12805             }
12806           break;
12807         case 'G':
12808           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12809             break;
12810           if ((rex & REX_W) || (sizeflag & DFLAG))
12811             *obufp++ = 'l';
12812           else
12813             *obufp++ = 'w';
12814           if (!(rex & REX_W))
12815             used_prefixes |= (prefixes & PREFIX_DATA);
12816           break;
12817         case 'H':
12818           if (intel_syntax)
12819             break;
12820           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12821               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12822             {
12823               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12824               *obufp++ = ',';
12825               *obufp++ = 'p';
12826               if (prefixes & PREFIX_DS)
12827                 *obufp++ = 't';
12828               else
12829                 *obufp++ = 'n';
12830             }
12831           break;
12832         case 'J':
12833           if (intel_syntax)
12834             break;
12835           *obufp++ = 'l';
12836           break;
12837         case 'K':
12838           USED_REX (REX_W);
12839           if (rex & REX_W)
12840             *obufp++ = 'q';
12841           else
12842             *obufp++ = 'd';
12843           break;
12844         case 'Z':
12845           if (l != 0 || len != 1)
12846             {
12847               if (l != 1 || len != 2 || last[0] != 'X')
12848                 {
12849                   SAVE_LAST (*p);
12850                   break;
12851                 }
12852               if (!need_vex || !vex.evex)
12853                 abort ();
12854               if (intel_syntax
12855                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12856                 break;
12857               switch (vex.length)
12858                 {
12859                 case 128:
12860                   *obufp++ = 'x';
12861                   break;
12862                 case 256:
12863                   *obufp++ = 'y';
12864                   break;
12865                 case 512:
12866                   *obufp++ = 'z';
12867                   break;
12868                 default:
12869                   abort ();
12870                 }
12871               break;
12872             }
12873           if (intel_syntax)
12874             break;
12875           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12876             {
12877               *obufp++ = 'q';
12878               break;
12879             }
12880           /* Fall through.  */
12881           goto case_L;
12882         case 'L':
12883           if (l != 0 || len != 1)
12884             {
12885               SAVE_LAST (*p);
12886               break;
12887             }
12888 case_L:
12889           if (intel_syntax)
12890             break;
12891           if (sizeflag & SUFFIX_ALWAYS)
12892             *obufp++ = 'l';
12893           break;
12894         case 'M':
12895           if (intel_mnemonic != cond)
12896             *obufp++ = 'r';
12897           break;
12898         case 'N':
12899           if ((prefixes & PREFIX_FWAIT) == 0)
12900             *obufp++ = 'n';
12901           else
12902             used_prefixes |= PREFIX_FWAIT;
12903           break;
12904         case 'O':
12905           USED_REX (REX_W);
12906           if (rex & REX_W)
12907             *obufp++ = 'o';
12908           else if (intel_syntax && (sizeflag & DFLAG))
12909             *obufp++ = 'q';
12910           else
12911             *obufp++ = 'd';
12912           if (!(rex & REX_W))
12913             used_prefixes |= (prefixes & PREFIX_DATA);
12914           break;
12915         case '&':
12916           if (!intel_syntax
12917               && address_mode == mode_64bit
12918               && isa64 == intel64)
12919             {
12920               *obufp++ = 'q';
12921               break;
12922             }
12923           /* Fall through.  */
12924         case 'T':
12925           if (!intel_syntax
12926               && address_mode == mode_64bit
12927               && ((sizeflag & DFLAG) || (rex & REX_W)))
12928             {
12929               *obufp++ = 'q';
12930               break;
12931             }
12932           /* Fall through.  */
12933           goto case_P;
12934         case 'P':
12935           if (l == 0 && len == 1)
12936             {
12937 case_P:
12938               if (intel_syntax)
12939                 {
12940                   if ((rex & REX_W) == 0
12941                       && (prefixes & PREFIX_DATA))
12942                     {
12943                       if ((sizeflag & DFLAG) == 0)
12944                         *obufp++ = 'w';
12945                       used_prefixes |= (prefixes & PREFIX_DATA);
12946                     }
12947                   break;
12948                 }
12949               if ((prefixes & PREFIX_DATA)
12950                   || (rex & REX_W)
12951                   || (sizeflag & SUFFIX_ALWAYS))
12952                 {
12953                   USED_REX (REX_W);
12954                   if (rex & REX_W)
12955                     *obufp++ = 'q';
12956                   else
12957                     {
12958                       if (sizeflag & DFLAG)
12959                         *obufp++ = 'l';
12960                       else
12961                         *obufp++ = 'w';
12962                       used_prefixes |= (prefixes & PREFIX_DATA);
12963                     }
12964                 }
12965             }
12966           else
12967             {
12968               if (l != 1 || len != 2 || last[0] != 'L')
12969                 {
12970                   SAVE_LAST (*p);
12971                   break;
12972                 }
12973
12974               if ((prefixes & PREFIX_DATA)
12975                   || (rex & REX_W)
12976                   || (sizeflag & SUFFIX_ALWAYS))
12977                 {
12978                   USED_REX (REX_W);
12979                   if (rex & REX_W)
12980                     *obufp++ = 'q';
12981                   else
12982                     {
12983                       if (sizeflag & DFLAG)
12984                         *obufp++ = intel_syntax ? 'd' : 'l';
12985                       else
12986                         *obufp++ = 'w';
12987                       used_prefixes |= (prefixes & PREFIX_DATA);
12988                     }
12989                 }
12990             }
12991           break;
12992         case 'U':
12993           if (intel_syntax)
12994             break;
12995           if (address_mode == mode_64bit
12996               && ((sizeflag & DFLAG) || (rex & REX_W)))
12997             {
12998               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12999                 *obufp++ = 'q';
13000               break;
13001             }
13002           /* Fall through.  */
13003           goto case_Q;
13004         case 'Q':
13005           if (l == 0 && len == 1)
13006             {
13007 case_Q:
13008               if (intel_syntax && !alt)
13009                 break;
13010               USED_REX (REX_W);
13011               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13012                 {
13013                   if (rex & REX_W)
13014                     *obufp++ = 'q';
13015                   else
13016                     {
13017                       if (sizeflag & DFLAG)
13018                         *obufp++ = intel_syntax ? 'd' : 'l';
13019                       else
13020                         *obufp++ = 'w';
13021                       used_prefixes |= (prefixes & PREFIX_DATA);
13022                     }
13023                 }
13024             }
13025           else
13026             {
13027               if (l != 1 || len != 2 || last[0] != 'L')
13028                 {
13029                   SAVE_LAST (*p);
13030                   break;
13031                 }
13032               if (intel_syntax
13033                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13034                 break;
13035               if ((rex & REX_W))
13036                 {
13037                   USED_REX (REX_W);
13038                   *obufp++ = 'q';
13039                 }
13040               else
13041                 *obufp++ = 'l';
13042             }
13043           break;
13044         case 'R':
13045           USED_REX (REX_W);
13046           if (rex & REX_W)
13047             *obufp++ = 'q';
13048           else if (sizeflag & DFLAG)
13049             {
13050               if (intel_syntax)
13051                   *obufp++ = 'd';
13052               else
13053                   *obufp++ = 'l';
13054             }
13055           else
13056             *obufp++ = 'w';
13057           if (intel_syntax && !p[1]
13058               && ((rex & REX_W) || (sizeflag & DFLAG)))
13059             *obufp++ = 'e';
13060           if (!(rex & REX_W))
13061             used_prefixes |= (prefixes & PREFIX_DATA);
13062           break;
13063         case 'V':
13064           if (l == 0 && len == 1)
13065             {
13066               if (intel_syntax)
13067                 break;
13068               if (address_mode == mode_64bit
13069                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13070                 {
13071                   if (sizeflag & SUFFIX_ALWAYS)
13072                     *obufp++ = 'q';
13073                   break;
13074                 }
13075             }
13076           else
13077             {
13078               if (l != 1
13079                   || len != 2
13080                   || last[0] != 'L')
13081                 {
13082                   SAVE_LAST (*p);
13083                   break;
13084                 }
13085
13086               if (rex & REX_W)
13087                 {
13088                   *obufp++ = 'a';
13089                   *obufp++ = 'b';
13090                   *obufp++ = 's';
13091                 }
13092             }
13093           /* Fall through.  */
13094           goto case_S;
13095         case 'S':
13096           if (l == 0 && len == 1)
13097             {
13098 case_S:
13099               if (intel_syntax)
13100                 break;
13101               if (sizeflag & SUFFIX_ALWAYS)
13102                 {
13103                   if (rex & REX_W)
13104                     *obufp++ = 'q';
13105                   else
13106                     {
13107                       if (sizeflag & DFLAG)
13108                         *obufp++ = 'l';
13109                       else
13110                         *obufp++ = 'w';
13111                       used_prefixes |= (prefixes & PREFIX_DATA);
13112                     }
13113                 }
13114             }
13115           else
13116             {
13117               if (l != 1
13118                   || len != 2
13119                   || last[0] != 'L')
13120                 {
13121                   SAVE_LAST (*p);
13122                   break;
13123                 }
13124
13125               if (address_mode == mode_64bit
13126                   && !(prefixes & PREFIX_ADDR))
13127                 {
13128                   *obufp++ = 'a';
13129                   *obufp++ = 'b';
13130                   *obufp++ = 's';
13131                 }
13132
13133               goto case_S;
13134             }
13135           break;
13136         case 'X':
13137           if (l != 0 || len != 1)
13138             {
13139               SAVE_LAST (*p);
13140               break;
13141             }
13142           if (need_vex && vex.prefix)
13143             {
13144               if (vex.prefix == DATA_PREFIX_OPCODE)
13145                 *obufp++ = 'd';
13146               else
13147                 *obufp++ = 's';
13148             }
13149           else
13150             {
13151               if (prefixes & PREFIX_DATA)
13152                 *obufp++ = 'd';
13153               else
13154                 *obufp++ = 's';
13155               used_prefixes |= (prefixes & PREFIX_DATA);
13156             }
13157           break;
13158         case 'Y':
13159           if (l == 0 && len == 1)
13160             abort ();
13161           else
13162             {
13163               if (l != 1 || len != 2 || last[0] != 'X')
13164                 {
13165                   SAVE_LAST (*p);
13166                   break;
13167                 }
13168               if (!need_vex)
13169                 abort ();
13170               if (intel_syntax
13171                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13172                 break;
13173               switch (vex.length)
13174                 {
13175                 case 128:
13176                   *obufp++ = 'x';
13177                   break;
13178                 case 256:
13179                   *obufp++ = 'y';
13180                   break;
13181                 case 512:
13182                   if (!vex.evex)
13183                 default:
13184                     abort ();
13185                 }
13186             }
13187           break;
13188         case 'W':
13189           if (l == 0 && len == 1)
13190             {
13191               /* operand size flag for cwtl, cbtw */
13192               USED_REX (REX_W);
13193               if (rex & REX_W)
13194                 {
13195                   if (intel_syntax)
13196                     *obufp++ = 'd';
13197                   else
13198                     *obufp++ = 'l';
13199                 }
13200               else if (sizeflag & DFLAG)
13201                 *obufp++ = 'w';
13202               else
13203                 *obufp++ = 'b';
13204               if (!(rex & REX_W))
13205                 used_prefixes |= (prefixes & PREFIX_DATA);
13206             }
13207           else
13208             {
13209               if (l != 1
13210                   || len != 2
13211                   || (last[0] != 'X'
13212                       && last[0] != 'L'))
13213                 {
13214                   SAVE_LAST (*p);
13215                   break;
13216                 }
13217               if (!need_vex)
13218                 abort ();
13219               if (last[0] == 'X')
13220                 *obufp++ = vex.w ? 'd': 's';
13221               else
13222                 *obufp++ = vex.w ? 'q': 'd';
13223             }
13224           break;
13225         case '^':
13226           if (intel_syntax)
13227             break;
13228           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13229             {
13230               if (sizeflag & DFLAG)
13231                 *obufp++ = 'l';
13232               else
13233                 *obufp++ = 'w';
13234               used_prefixes |= (prefixes & PREFIX_DATA);
13235             }
13236           break;
13237         case '@':
13238           if (intel_syntax)
13239             break;
13240           if (address_mode == mode_64bit
13241               && (isa64 == intel64
13242                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13243               *obufp++ = 'q';
13244           else if ((prefixes & PREFIX_DATA))
13245             {
13246               if (!(sizeflag & DFLAG))
13247                 *obufp++ = 'w';
13248               used_prefixes |= (prefixes & PREFIX_DATA);
13249             }
13250           break;
13251         }
13252       alt = 0;
13253     }
13254   *obufp = 0;
13255   mnemonicendp = obufp;
13256   return 0;
13257 }
13258
13259 static void
13260 oappend (const char *s)
13261 {
13262   obufp = stpcpy (obufp, s);
13263 }
13264
13265 static void
13266 append_seg (void)
13267 {
13268   /* Only print the active segment register.  */
13269   if (!active_seg_prefix)
13270     return;
13271
13272   used_prefixes |= active_seg_prefix;
13273   switch (active_seg_prefix)
13274     {
13275     case PREFIX_CS:
13276       oappend_maybe_intel ("%cs:");
13277       break;
13278     case PREFIX_DS:
13279       oappend_maybe_intel ("%ds:");
13280       break;
13281     case PREFIX_SS:
13282       oappend_maybe_intel ("%ss:");
13283       break;
13284     case PREFIX_ES:
13285       oappend_maybe_intel ("%es:");
13286       break;
13287     case PREFIX_FS:
13288       oappend_maybe_intel ("%fs:");
13289       break;
13290     case PREFIX_GS:
13291       oappend_maybe_intel ("%gs:");
13292       break;
13293     default:
13294       break;
13295     }
13296 }
13297
13298 static void
13299 OP_indirE (int bytemode, int sizeflag)
13300 {
13301   if (!intel_syntax)
13302     oappend ("*");
13303   OP_E (bytemode, sizeflag);
13304 }
13305
13306 static void
13307 print_operand_value (char *buf, int hex, bfd_vma disp)
13308 {
13309   if (address_mode == mode_64bit)
13310     {
13311       if (hex)
13312         {
13313           char tmp[30];
13314           int i;
13315           buf[0] = '0';
13316           buf[1] = 'x';
13317           sprintf_vma (tmp, disp);
13318           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13319           strcpy (buf + 2, tmp + i);
13320         }
13321       else
13322         {
13323           bfd_signed_vma v = disp;
13324           char tmp[30];
13325           int i;
13326           if (v < 0)
13327             {
13328               *(buf++) = '-';
13329               v = -disp;
13330               /* Check for possible overflow on 0x8000000000000000.  */
13331               if (v < 0)
13332                 {
13333                   strcpy (buf, "9223372036854775808");
13334                   return;
13335                 }
13336             }
13337           if (!v)
13338             {
13339               strcpy (buf, "0");
13340               return;
13341             }
13342
13343           i = 0;
13344           tmp[29] = 0;
13345           while (v)
13346             {
13347               tmp[28 - i] = (v % 10) + '0';
13348               v /= 10;
13349               i++;
13350             }
13351           strcpy (buf, tmp + 29 - i);
13352         }
13353     }
13354   else
13355     {
13356       if (hex)
13357         sprintf (buf, "0x%x", (unsigned int) disp);
13358       else
13359         sprintf (buf, "%d", (int) disp);
13360     }
13361 }
13362
13363 /* Put DISP in BUF as signed hex number.  */
13364
13365 static void
13366 print_displacement (char *buf, bfd_vma disp)
13367 {
13368   bfd_signed_vma val = disp;
13369   char tmp[30];
13370   int i, j = 0;
13371
13372   if (val < 0)
13373     {
13374       buf[j++] = '-';
13375       val = -disp;
13376
13377       /* Check for possible overflow.  */
13378       if (val < 0)
13379         {
13380           switch (address_mode)
13381             {
13382             case mode_64bit:
13383               strcpy (buf + j, "0x8000000000000000");
13384               break;
13385             case mode_32bit:
13386               strcpy (buf + j, "0x80000000");
13387               break;
13388             case mode_16bit:
13389               strcpy (buf + j, "0x8000");
13390               break;
13391             }
13392           return;
13393         }
13394     }
13395
13396   buf[j++] = '0';
13397   buf[j++] = 'x';
13398
13399   sprintf_vma (tmp, (bfd_vma) val);
13400   for (i = 0; tmp[i] == '0'; i++)
13401     continue;
13402   if (tmp[i] == '\0')
13403     i--;
13404   strcpy (buf + j, tmp + i);
13405 }
13406
13407 static void
13408 intel_operand_size (int bytemode, int sizeflag)
13409 {
13410   if (vex.evex
13411       && vex.b
13412       && (bytemode == x_mode
13413           || bytemode == evex_half_bcst_xmmq_mode))
13414     {
13415       if (vex.w)
13416         oappend ("QWORD PTR ");
13417       else
13418         oappend ("DWORD PTR ");
13419       return;
13420     }
13421   switch (bytemode)
13422     {
13423     case b_mode:
13424     case b_swap_mode:
13425     case dqb_mode:
13426     case db_mode:
13427       oappend ("BYTE PTR ");
13428       break;
13429     case w_mode:
13430     case dw_mode:
13431     case dqw_mode:
13432       oappend ("WORD PTR ");
13433       break;
13434     case indir_v_mode:
13435       if (address_mode == mode_64bit && isa64 == intel64)
13436         {
13437           oappend ("QWORD PTR ");
13438           break;
13439         }
13440       /* Fall through.  */
13441     case stack_v_mode:
13442       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13443         {
13444           oappend ("QWORD PTR ");
13445           break;
13446         }
13447       /* Fall through.  */
13448     case v_mode:
13449     case v_swap_mode:
13450     case dq_mode:
13451       USED_REX (REX_W);
13452       if (rex & REX_W)
13453         oappend ("QWORD PTR ");
13454       else
13455         {
13456           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13457             oappend ("DWORD PTR ");
13458           else
13459             oappend ("WORD PTR ");
13460           used_prefixes |= (prefixes & PREFIX_DATA);
13461         }
13462       break;
13463     case z_mode:
13464       if ((rex & REX_W) || (sizeflag & DFLAG))
13465         *obufp++ = 'D';
13466       oappend ("WORD PTR ");
13467       if (!(rex & REX_W))
13468         used_prefixes |= (prefixes & PREFIX_DATA);
13469       break;
13470     case a_mode:
13471       if (sizeflag & DFLAG)
13472         oappend ("QWORD PTR ");
13473       else
13474         oappend ("DWORD PTR ");
13475       used_prefixes |= (prefixes & PREFIX_DATA);
13476       break;
13477     case d_mode:
13478     case d_scalar_mode:
13479     case d_scalar_swap_mode:
13480     case d_swap_mode:
13481     case dqd_mode:
13482       oappend ("DWORD PTR ");
13483       break;
13484     case q_mode:
13485     case q_scalar_mode:
13486     case q_scalar_swap_mode:
13487     case q_swap_mode:
13488       oappend ("QWORD PTR ");
13489       break;
13490     case m_mode:
13491       if (address_mode == mode_64bit)
13492         oappend ("QWORD PTR ");
13493       else
13494         oappend ("DWORD PTR ");
13495       break;
13496     case f_mode:
13497       if (sizeflag & DFLAG)
13498         oappend ("FWORD PTR ");
13499       else
13500         oappend ("DWORD PTR ");
13501       used_prefixes |= (prefixes & PREFIX_DATA);
13502       break;
13503     case t_mode:
13504       oappend ("TBYTE PTR ");
13505       break;
13506     case x_mode:
13507     case x_swap_mode:
13508     case evex_x_gscat_mode:
13509     case evex_x_nobcst_mode:
13510     case b_scalar_mode:
13511     case w_scalar_mode:
13512       if (need_vex)
13513         {
13514           switch (vex.length)
13515             {
13516             case 128:
13517               oappend ("XMMWORD PTR ");
13518               break;
13519             case 256:
13520               oappend ("YMMWORD PTR ");
13521               break;
13522             case 512:
13523               oappend ("ZMMWORD PTR ");
13524               break;
13525             default:
13526               abort ();
13527             }
13528         }
13529       else
13530         oappend ("XMMWORD PTR ");
13531       break;
13532     case xmm_mode:
13533       oappend ("XMMWORD PTR ");
13534       break;
13535     case ymm_mode:
13536       oappend ("YMMWORD PTR ");
13537       break;
13538     case xmmq_mode:
13539     case evex_half_bcst_xmmq_mode:
13540       if (!need_vex)
13541         abort ();
13542
13543       switch (vex.length)
13544         {
13545         case 128:
13546           oappend ("QWORD PTR ");
13547           break;
13548         case 256:
13549           oappend ("XMMWORD PTR ");
13550           break;
13551         case 512:
13552           oappend ("YMMWORD PTR ");
13553           break;
13554         default:
13555           abort ();
13556         }
13557       break;
13558     case xmm_mb_mode:
13559       if (!need_vex)
13560         abort ();
13561
13562       switch (vex.length)
13563         {
13564         case 128:
13565         case 256:
13566         case 512:
13567           oappend ("BYTE PTR ");
13568           break;
13569         default:
13570           abort ();
13571         }
13572       break;
13573     case xmm_mw_mode:
13574       if (!need_vex)
13575         abort ();
13576
13577       switch (vex.length)
13578         {
13579         case 128:
13580         case 256:
13581         case 512:
13582           oappend ("WORD PTR ");
13583           break;
13584         default:
13585           abort ();
13586         }
13587       break;
13588     case xmm_md_mode:
13589       if (!need_vex)
13590         abort ();
13591
13592       switch (vex.length)
13593         {
13594         case 128:
13595         case 256:
13596         case 512:
13597           oappend ("DWORD PTR ");
13598           break;
13599         default:
13600           abort ();
13601         }
13602       break;
13603     case xmm_mq_mode:
13604       if (!need_vex)
13605         abort ();
13606
13607       switch (vex.length)
13608         {
13609         case 128:
13610         case 256:
13611         case 512:
13612           oappend ("QWORD PTR ");
13613           break;
13614         default:
13615           abort ();
13616         }
13617       break;
13618     case xmmdw_mode:
13619       if (!need_vex)
13620         abort ();
13621
13622       switch (vex.length)
13623         {
13624         case 128:
13625           oappend ("WORD PTR ");
13626           break;
13627         case 256:
13628           oappend ("DWORD PTR ");
13629           break;
13630         case 512:
13631           oappend ("QWORD PTR ");
13632           break;
13633         default:
13634           abort ();
13635         }
13636       break;
13637     case xmmqd_mode:
13638       if (!need_vex)
13639         abort ();
13640
13641       switch (vex.length)
13642         {
13643         case 128:
13644           oappend ("DWORD PTR ");
13645           break;
13646         case 256:
13647           oappend ("QWORD PTR ");
13648           break;
13649         case 512:
13650           oappend ("XMMWORD PTR ");
13651           break;
13652         default:
13653           abort ();
13654         }
13655       break;
13656     case ymmq_mode:
13657       if (!need_vex)
13658         abort ();
13659
13660       switch (vex.length)
13661         {
13662         case 128:
13663           oappend ("QWORD PTR ");
13664           break;
13665         case 256:
13666           oappend ("YMMWORD PTR ");
13667           break;
13668         case 512:
13669           oappend ("ZMMWORD PTR ");
13670           break;
13671         default:
13672           abort ();
13673         }
13674       break;
13675     case ymmxmm_mode:
13676       if (!need_vex)
13677         abort ();
13678
13679       switch (vex.length)
13680         {
13681         case 128:
13682         case 256:
13683           oappend ("XMMWORD PTR ");
13684           break;
13685         default:
13686           abort ();
13687         }
13688       break;
13689     case o_mode:
13690       oappend ("OWORD PTR ");
13691       break;
13692     case xmm_mdq_mode:
13693     case vex_w_dq_mode:
13694     case vex_scalar_w_dq_mode:
13695       if (!need_vex)
13696         abort ();
13697
13698       if (vex.w)
13699         oappend ("QWORD PTR ");
13700       else
13701         oappend ("DWORD PTR ");
13702       break;
13703     case vex_vsib_d_w_dq_mode:
13704     case vex_vsib_q_w_dq_mode:
13705       if (!need_vex)
13706         abort ();
13707
13708       if (!vex.evex)
13709         {
13710           if (vex.w)
13711             oappend ("QWORD PTR ");
13712           else
13713             oappend ("DWORD PTR ");
13714         }
13715       else
13716         {
13717           switch (vex.length)
13718             {
13719             case 128:
13720               oappend ("XMMWORD PTR ");
13721               break;
13722             case 256:
13723               oappend ("YMMWORD PTR ");
13724               break;
13725             case 512:
13726               oappend ("ZMMWORD PTR ");
13727               break;
13728             default:
13729               abort ();
13730             }
13731         }
13732       break;
13733     case vex_vsib_q_w_d_mode:
13734     case vex_vsib_d_w_d_mode:
13735       if (!need_vex || !vex.evex)
13736         abort ();
13737
13738       switch (vex.length)
13739         {
13740         case 128:
13741           oappend ("QWORD PTR ");
13742           break;
13743         case 256:
13744           oappend ("XMMWORD PTR ");
13745           break;
13746         case 512:
13747           oappend ("YMMWORD PTR ");
13748           break;
13749         default:
13750           abort ();
13751         }
13752
13753       break;
13754     case mask_bd_mode:
13755       if (!need_vex || vex.length != 128)
13756         abort ();
13757       if (vex.w)
13758         oappend ("DWORD PTR ");
13759       else
13760         oappend ("BYTE PTR ");
13761       break;
13762     case mask_mode:
13763       if (!need_vex)
13764         abort ();
13765       if (vex.w)
13766         oappend ("QWORD PTR ");
13767       else
13768         oappend ("WORD PTR ");
13769       break;
13770     case v_bnd_mode:
13771     case v_bndmk_mode:
13772     default:
13773       break;
13774     }
13775 }
13776
13777 static void
13778 OP_E_register (int bytemode, int sizeflag)
13779 {
13780   int reg = modrm.rm;
13781   const char **names;
13782
13783   USED_REX (REX_B);
13784   if ((rex & REX_B))
13785     reg += 8;
13786
13787   if ((sizeflag & SUFFIX_ALWAYS)
13788       && (bytemode == b_swap_mode
13789           || bytemode == bnd_swap_mode
13790           || bytemode == v_swap_mode))
13791     swap_operand ();
13792
13793   switch (bytemode)
13794     {
13795     case b_mode:
13796     case b_swap_mode:
13797       USED_REX (0);
13798       if (rex)
13799         names = names8rex;
13800       else
13801         names = names8;
13802       break;
13803     case w_mode:
13804       names = names16;
13805       break;
13806     case d_mode:
13807     case dw_mode:
13808     case db_mode:
13809       names = names32;
13810       break;
13811     case q_mode:
13812       names = names64;
13813       break;
13814     case m_mode:
13815     case v_bnd_mode:
13816       names = address_mode == mode_64bit ? names64 : names32;
13817       break;
13818     case bnd_mode:
13819     case bnd_swap_mode:
13820       if (reg > 0x3)
13821         {
13822           oappend ("(bad)");
13823           return;
13824         }
13825       names = names_bnd;
13826       break;
13827     case indir_v_mode:
13828       if (address_mode == mode_64bit && isa64 == intel64)
13829         {
13830           names = names64;
13831           break;
13832         }
13833       /* Fall through.  */
13834     case stack_v_mode:
13835       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13836         {
13837           names = names64;
13838           break;
13839         }
13840       bytemode = v_mode;
13841       /* Fall through.  */
13842     case v_mode:
13843     case v_swap_mode:
13844     case dq_mode:
13845     case dqb_mode:
13846     case dqd_mode:
13847     case dqw_mode:
13848       USED_REX (REX_W);
13849       if (rex & REX_W)
13850         names = names64;
13851       else
13852         {
13853           if ((sizeflag & DFLAG)
13854               || (bytemode != v_mode
13855                   && bytemode != v_swap_mode))
13856             names = names32;
13857           else
13858             names = names16;
13859           used_prefixes |= (prefixes & PREFIX_DATA);
13860         }
13861       break;
13862     case va_mode:
13863       names = (address_mode == mode_64bit
13864                ? names64 : names32);
13865       if (!(prefixes & PREFIX_ADDR))
13866         names = (address_mode == mode_16bit
13867                      ? names16 : names);
13868       else
13869         {
13870           /* Remove "addr16/addr32".  */
13871           all_prefixes[last_addr_prefix] = 0;
13872           names = (address_mode != mode_32bit
13873                        ? names32 : names16);
13874           used_prefixes |= PREFIX_ADDR;
13875         }
13876       break;
13877     case mask_bd_mode:
13878     case mask_mode:
13879       if (reg > 0x7)
13880         {
13881           oappend ("(bad)");
13882           return;
13883         }
13884       names = names_mask;
13885       break;
13886     case 0:
13887       return;
13888     default:
13889       oappend (INTERNAL_DISASSEMBLER_ERROR);
13890       return;
13891     }
13892   oappend (names[reg]);
13893 }
13894
13895 static void
13896 OP_E_memory (int bytemode, int sizeflag)
13897 {
13898   bfd_vma disp = 0;
13899   int add = (rex & REX_B) ? 8 : 0;
13900   int riprel = 0;
13901   int shift;
13902
13903   if (vex.evex)
13904     {
13905       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13906       if (vex.b
13907           && bytemode != x_mode
13908           && bytemode != xmmq_mode
13909           && bytemode != evex_half_bcst_xmmq_mode)
13910         {
13911           BadOp ();
13912           return;
13913         }
13914       switch (bytemode)
13915         {
13916         case dqw_mode:
13917         case dw_mode:
13918           shift = 1;
13919           break;
13920         case dqb_mode:
13921         case db_mode:
13922           shift = 0;
13923           break;
13924         case dq_mode:
13925           if (address_mode != mode_64bit)
13926             {
13927               shift = 2;
13928               break;
13929             }
13930             /* fall through */
13931         case vex_vsib_d_w_dq_mode:
13932         case vex_vsib_d_w_d_mode:
13933         case vex_vsib_q_w_dq_mode:
13934         case vex_vsib_q_w_d_mode:
13935         case evex_x_gscat_mode:
13936         case xmm_mdq_mode:
13937           shift = vex.w ? 3 : 2;
13938           break;
13939         case x_mode:
13940         case evex_half_bcst_xmmq_mode:
13941         case xmmq_mode:
13942           if (vex.b)
13943             {
13944               shift = vex.w ? 3 : 2;
13945               break;
13946             }
13947           /* Fall through.  */
13948         case xmmqd_mode:
13949         case xmmdw_mode:
13950         case ymmq_mode:
13951         case evex_x_nobcst_mode:
13952         case x_swap_mode:
13953           switch (vex.length)
13954             {
13955             case 128:
13956               shift = 4;
13957               break;
13958             case 256:
13959               shift = 5;
13960               break;
13961             case 512:
13962               shift = 6;
13963               break;
13964             default:
13965               abort ();
13966             }
13967           break;
13968         case ymm_mode:
13969           shift = 5;
13970           break;
13971         case xmm_mode:
13972           shift = 4;
13973           break;
13974         case xmm_mq_mode:
13975         case q_mode:
13976         case q_scalar_mode:
13977         case q_swap_mode:
13978         case q_scalar_swap_mode:
13979           shift = 3;
13980           break;
13981         case dqd_mode:
13982         case xmm_md_mode:
13983         case d_mode:
13984         case d_scalar_mode:
13985         case d_swap_mode:
13986         case d_scalar_swap_mode:
13987           shift = 2;
13988           break;
13989         case w_scalar_mode:
13990         case xmm_mw_mode:
13991           shift = 1;
13992           break;
13993         case b_scalar_mode:
13994         case xmm_mb_mode:
13995           shift = 0;
13996           break;
13997         default:
13998           abort ();
13999         }
14000       /* Make necessary corrections to shift for modes that need it.
14001          For these modes we currently have shift 4, 5 or 6 depending on
14002          vex.length (it corresponds to xmmword, ymmword or zmmword
14003          operand).  We might want to make it 3, 4 or 5 (e.g. for
14004          xmmq_mode).  In case of broadcast enabled the corrections
14005          aren't needed, as element size is always 32 or 64 bits.  */
14006       if (!vex.b
14007           && (bytemode == xmmq_mode
14008               || bytemode == evex_half_bcst_xmmq_mode))
14009         shift -= 1;
14010       else if (bytemode == xmmqd_mode)
14011         shift -= 2;
14012       else if (bytemode == xmmdw_mode)
14013         shift -= 3;
14014       else if (bytemode == ymmq_mode && vex.length == 128)
14015         shift -= 1;
14016     }
14017   else
14018     shift = 0;
14019
14020   USED_REX (REX_B);
14021   if (intel_syntax)
14022     intel_operand_size (bytemode, sizeflag);
14023   append_seg ();
14024
14025   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14026     {
14027       /* 32/64 bit address mode */
14028       int havedisp;
14029       int havesib;
14030       int havebase;
14031       int haveindex;
14032       int needindex;
14033       int needaddr32;
14034       int base, rbase;
14035       int vindex = 0;
14036       int scale = 0;
14037       int addr32flag = !((sizeflag & AFLAG)
14038                          || bytemode == v_bnd_mode
14039                          || bytemode == v_bndmk_mode
14040                          || bytemode == bnd_mode
14041                          || bytemode == bnd_swap_mode);
14042       const char **indexes64 = names64;
14043       const char **indexes32 = names32;
14044
14045       havesib = 0;
14046       havebase = 1;
14047       haveindex = 0;
14048       base = modrm.rm;
14049
14050       if (base == 4)
14051         {
14052           havesib = 1;
14053           vindex = sib.index;
14054           USED_REX (REX_X);
14055           if (rex & REX_X)
14056             vindex += 8;
14057           switch (bytemode)
14058             {
14059             case vex_vsib_d_w_dq_mode:
14060             case vex_vsib_d_w_d_mode:
14061             case vex_vsib_q_w_dq_mode:
14062             case vex_vsib_q_w_d_mode:
14063               if (!need_vex)
14064                 abort ();
14065               if (vex.evex)
14066                 {
14067                   if (!vex.v)
14068                     vindex += 16;
14069                 }
14070
14071               haveindex = 1;
14072               switch (vex.length)
14073                 {
14074                 case 128:
14075                   indexes64 = indexes32 = names_xmm;
14076                   break;
14077                 case 256:
14078                   if (!vex.w
14079                       || bytemode == vex_vsib_q_w_dq_mode
14080                       || bytemode == vex_vsib_q_w_d_mode)
14081                     indexes64 = indexes32 = names_ymm;
14082                   else
14083                     indexes64 = indexes32 = names_xmm;
14084                   break;
14085                 case 512:
14086                   if (!vex.w
14087                       || bytemode == vex_vsib_q_w_dq_mode
14088                       || bytemode == vex_vsib_q_w_d_mode)
14089                     indexes64 = indexes32 = names_zmm;
14090                   else
14091                     indexes64 = indexes32 = names_ymm;
14092                   break;
14093                 default:
14094                   abort ();
14095                 }
14096               break;
14097             default:
14098               haveindex = vindex != 4;
14099               break;
14100             }
14101           scale = sib.scale;
14102           base = sib.base;
14103           codep++;
14104         }
14105       rbase = base + add;
14106
14107       switch (modrm.mod)
14108         {
14109         case 0:
14110           if (base == 5)
14111             {
14112               havebase = 0;
14113               if (address_mode == mode_64bit && !havesib)
14114                 riprel = 1;
14115               disp = get32s ();
14116               if (riprel && bytemode == v_bndmk_mode)
14117                 {
14118                   oappend ("(bad)");
14119                   return;
14120                 }
14121             }
14122           break;
14123         case 1:
14124           FETCH_DATA (the_info, codep + 1);
14125           disp = *codep++;
14126           if ((disp & 0x80) != 0)
14127             disp -= 0x100;
14128           if (vex.evex && shift > 0)
14129             disp <<= shift;
14130           break;
14131         case 2:
14132           disp = get32s ();
14133           break;
14134         }
14135
14136       needindex = 0;
14137       needaddr32 = 0;
14138       if (havesib
14139           && !havebase
14140           && !haveindex
14141           && address_mode != mode_16bit)
14142         {
14143           if (address_mode == mode_64bit)
14144             {
14145               /* Display eiz instead of addr32.  */
14146               needindex = addr32flag;
14147               needaddr32 = 1;
14148             }
14149           else
14150             {
14151               /* In 32-bit mode, we need index register to tell [offset]
14152                  from [eiz*1 + offset].  */
14153               needindex = 1;
14154             }
14155         }
14156
14157       havedisp = (havebase
14158                   || needindex
14159                   || (havesib && (haveindex || scale != 0)));
14160
14161       if (!intel_syntax)
14162         if (modrm.mod != 0 || base == 5)
14163           {
14164             if (havedisp || riprel)
14165               print_displacement (scratchbuf, disp);
14166             else
14167               print_operand_value (scratchbuf, 1, disp);
14168             oappend (scratchbuf);
14169             if (riprel)
14170               {
14171                 set_op (disp, 1);
14172                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14173               }
14174           }
14175
14176       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14177           && (bytemode != v_bnd_mode)
14178           && (bytemode != v_bndmk_mode)
14179           && (bytemode != bnd_mode)
14180           && (bytemode != bnd_swap_mode))
14181         used_prefixes |= PREFIX_ADDR;
14182
14183       if (havedisp || (intel_syntax && riprel))
14184         {
14185           *obufp++ = open_char;
14186           if (intel_syntax && riprel)
14187             {
14188               set_op (disp, 1);
14189               oappend (!addr32flag ? "rip" : "eip");
14190             }
14191           *obufp = '\0';
14192           if (havebase)
14193             oappend (address_mode == mode_64bit && !addr32flag
14194                      ? names64[rbase] : names32[rbase]);
14195           if (havesib)
14196             {
14197               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14198                  print index to tell base + index from base.  */
14199               if (scale != 0
14200                   || needindex
14201                   || haveindex
14202                   || (havebase && base != ESP_REG_NUM))
14203                 {
14204                   if (!intel_syntax || havebase)
14205                     {
14206                       *obufp++ = separator_char;
14207                       *obufp = '\0';
14208                     }
14209                   if (haveindex)
14210                     oappend (address_mode == mode_64bit && !addr32flag
14211                              ? indexes64[vindex] : indexes32[vindex]);
14212                   else
14213                     oappend (address_mode == mode_64bit && !addr32flag
14214                              ? index64 : index32);
14215
14216                   *obufp++ = scale_char;
14217                   *obufp = '\0';
14218                   sprintf (scratchbuf, "%d", 1 << scale);
14219                   oappend (scratchbuf);
14220                 }
14221             }
14222           if (intel_syntax
14223               && (disp || modrm.mod != 0 || base == 5))
14224             {
14225               if (!havedisp || (bfd_signed_vma) disp >= 0)
14226                 {
14227                   *obufp++ = '+';
14228                   *obufp = '\0';
14229                 }
14230               else if (modrm.mod != 1 && disp != -disp)
14231                 {
14232                   *obufp++ = '-';
14233                   *obufp = '\0';
14234                   disp = - (bfd_signed_vma) disp;
14235                 }
14236
14237               if (havedisp)
14238                 print_displacement (scratchbuf, disp);
14239               else
14240                 print_operand_value (scratchbuf, 1, disp);
14241               oappend (scratchbuf);
14242             }
14243
14244           *obufp++ = close_char;
14245           *obufp = '\0';
14246         }
14247       else if (intel_syntax)
14248         {
14249           if (modrm.mod != 0 || base == 5)
14250             {
14251               if (!active_seg_prefix)
14252                 {
14253                   oappend (names_seg[ds_reg - es_reg]);
14254                   oappend (":");
14255                 }
14256               print_operand_value (scratchbuf, 1, disp);
14257               oappend (scratchbuf);
14258             }
14259         }
14260     }
14261   else
14262     {
14263       /* 16 bit address mode */
14264       used_prefixes |= prefixes & PREFIX_ADDR;
14265       switch (modrm.mod)
14266         {
14267         case 0:
14268           if (modrm.rm == 6)
14269             {
14270               disp = get16 ();
14271               if ((disp & 0x8000) != 0)
14272                 disp -= 0x10000;
14273             }
14274           break;
14275         case 1:
14276           FETCH_DATA (the_info, codep + 1);
14277           disp = *codep++;
14278           if ((disp & 0x80) != 0)
14279             disp -= 0x100;
14280           if (vex.evex && shift > 0)
14281             disp <<= shift;
14282           break;
14283         case 2:
14284           disp = get16 ();
14285           if ((disp & 0x8000) != 0)
14286             disp -= 0x10000;
14287           break;
14288         }
14289
14290       if (!intel_syntax)
14291         if (modrm.mod != 0 || modrm.rm == 6)
14292           {
14293             print_displacement (scratchbuf, disp);
14294             oappend (scratchbuf);
14295           }
14296
14297       if (modrm.mod != 0 || modrm.rm != 6)
14298         {
14299           *obufp++ = open_char;
14300           *obufp = '\0';
14301           oappend (index16[modrm.rm]);
14302           if (intel_syntax
14303               && (disp || modrm.mod != 0 || modrm.rm == 6))
14304             {
14305               if ((bfd_signed_vma) disp >= 0)
14306                 {
14307                   *obufp++ = '+';
14308                   *obufp = '\0';
14309                 }
14310               else if (modrm.mod != 1)
14311                 {
14312                   *obufp++ = '-';
14313                   *obufp = '\0';
14314                   disp = - (bfd_signed_vma) disp;
14315                 }
14316
14317               print_displacement (scratchbuf, disp);
14318               oappend (scratchbuf);
14319             }
14320
14321           *obufp++ = close_char;
14322           *obufp = '\0';
14323         }
14324       else if (intel_syntax)
14325         {
14326           if (!active_seg_prefix)
14327             {
14328               oappend (names_seg[ds_reg - es_reg]);
14329               oappend (":");
14330             }
14331           print_operand_value (scratchbuf, 1, disp & 0xffff);
14332           oappend (scratchbuf);
14333         }
14334     }
14335   if (vex.evex && vex.b
14336       && (bytemode == x_mode
14337           || bytemode == xmmq_mode
14338           || bytemode == evex_half_bcst_xmmq_mode))
14339     {
14340       if (vex.w
14341           || bytemode == xmmq_mode
14342           || bytemode == evex_half_bcst_xmmq_mode)
14343         {
14344           switch (vex.length)
14345             {
14346             case 128:
14347               oappend ("{1to2}");
14348               break;
14349             case 256:
14350               oappend ("{1to4}");
14351               break;
14352             case 512:
14353               oappend ("{1to8}");
14354               break;
14355             default:
14356               abort ();
14357             }
14358         }
14359       else
14360         {
14361           switch (vex.length)
14362             {
14363             case 128:
14364               oappend ("{1to4}");
14365               break;
14366             case 256:
14367               oappend ("{1to8}");
14368               break;
14369             case 512:
14370               oappend ("{1to16}");
14371               break;
14372             default:
14373               abort ();
14374             }
14375         }
14376     }
14377 }
14378
14379 static void
14380 OP_E (int bytemode, int sizeflag)
14381 {
14382   /* Skip mod/rm byte.  */
14383   MODRM_CHECK;
14384   codep++;
14385
14386   if (modrm.mod == 3)
14387     OP_E_register (bytemode, sizeflag);
14388   else
14389     OP_E_memory (bytemode, sizeflag);
14390 }
14391
14392 static void
14393 OP_G (int bytemode, int sizeflag)
14394 {
14395   int add = 0;
14396   const char **names;
14397   USED_REX (REX_R);
14398   if (rex & REX_R)
14399     add += 8;
14400   switch (bytemode)
14401     {
14402     case b_mode:
14403       USED_REX (0);
14404       if (rex)
14405         oappend (names8rex[modrm.reg + add]);
14406       else
14407         oappend (names8[modrm.reg + add]);
14408       break;
14409     case w_mode:
14410       oappend (names16[modrm.reg + add]);
14411       break;
14412     case d_mode:
14413     case db_mode:
14414     case dw_mode:
14415       oappend (names32[modrm.reg + add]);
14416       break;
14417     case q_mode:
14418       oappend (names64[modrm.reg + add]);
14419       break;
14420     case bnd_mode:
14421       if (modrm.reg > 0x3)
14422         {
14423           oappend ("(bad)");
14424           return;
14425         }
14426       oappend (names_bnd[modrm.reg]);
14427       break;
14428     case v_mode:
14429     case dq_mode:
14430     case dqb_mode:
14431     case dqd_mode:
14432     case dqw_mode:
14433       USED_REX (REX_W);
14434       if (rex & REX_W)
14435         oappend (names64[modrm.reg + add]);
14436       else
14437         {
14438           if ((sizeflag & DFLAG) || bytemode != v_mode)
14439             oappend (names32[modrm.reg + add]);
14440           else
14441             oappend (names16[modrm.reg + add]);
14442           used_prefixes |= (prefixes & PREFIX_DATA);
14443         }
14444       break;
14445     case va_mode:
14446       names = (address_mode == mode_64bit
14447                ? names64 : names32);
14448       if (!(prefixes & PREFIX_ADDR))
14449         {
14450           if (address_mode == mode_16bit)
14451             names = names16;
14452         }
14453       else
14454         {
14455           /* Remove "addr16/addr32".  */
14456           all_prefixes[last_addr_prefix] = 0;
14457           names = (address_mode != mode_32bit
14458                        ? names32 : names16);
14459           used_prefixes |= PREFIX_ADDR;
14460         }
14461       oappend (names[modrm.reg + add]);
14462       break;
14463     case m_mode:
14464       if (address_mode == mode_64bit)
14465         oappend (names64[modrm.reg + add]);
14466       else
14467         oappend (names32[modrm.reg + add]);
14468       break;
14469     case mask_bd_mode:
14470     case mask_mode:
14471       if ((modrm.reg + add) > 0x7)
14472         {
14473           oappend ("(bad)");
14474           return;
14475         }
14476       oappend (names_mask[modrm.reg + add]);
14477       break;
14478     default:
14479       oappend (INTERNAL_DISASSEMBLER_ERROR);
14480       break;
14481     }
14482 }
14483
14484 static bfd_vma
14485 get64 (void)
14486 {
14487   bfd_vma x;
14488 #ifdef BFD64
14489   unsigned int a;
14490   unsigned int b;
14491
14492   FETCH_DATA (the_info, codep + 8);
14493   a = *codep++ & 0xff;
14494   a |= (*codep++ & 0xff) << 8;
14495   a |= (*codep++ & 0xff) << 16;
14496   a |= (*codep++ & 0xffu) << 24;
14497   b = *codep++ & 0xff;
14498   b |= (*codep++ & 0xff) << 8;
14499   b |= (*codep++ & 0xff) << 16;
14500   b |= (*codep++ & 0xffu) << 24;
14501   x = a + ((bfd_vma) b << 32);
14502 #else
14503   abort ();
14504   x = 0;
14505 #endif
14506   return x;
14507 }
14508
14509 static bfd_signed_vma
14510 get32 (void)
14511 {
14512   bfd_signed_vma x = 0;
14513
14514   FETCH_DATA (the_info, codep + 4);
14515   x = *codep++ & (bfd_signed_vma) 0xff;
14516   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14517   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14518   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14519   return x;
14520 }
14521
14522 static bfd_signed_vma
14523 get32s (void)
14524 {
14525   bfd_signed_vma x = 0;
14526
14527   FETCH_DATA (the_info, codep + 4);
14528   x = *codep++ & (bfd_signed_vma) 0xff;
14529   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14530   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14531   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14532
14533   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14534
14535   return x;
14536 }
14537
14538 static int
14539 get16 (void)
14540 {
14541   int x = 0;
14542
14543   FETCH_DATA (the_info, codep + 2);
14544   x = *codep++ & 0xff;
14545   x |= (*codep++ & 0xff) << 8;
14546   return x;
14547 }
14548
14549 static void
14550 set_op (bfd_vma op, int riprel)
14551 {
14552   op_index[op_ad] = op_ad;
14553   if (address_mode == mode_64bit)
14554     {
14555       op_address[op_ad] = op;
14556       op_riprel[op_ad] = riprel;
14557     }
14558   else
14559     {
14560       /* Mask to get a 32-bit address.  */
14561       op_address[op_ad] = op & 0xffffffff;
14562       op_riprel[op_ad] = riprel & 0xffffffff;
14563     }
14564 }
14565
14566 static void
14567 OP_REG (int code, int sizeflag)
14568 {
14569   const char *s;
14570   int add;
14571
14572   switch (code)
14573     {
14574     case es_reg: case ss_reg: case cs_reg:
14575     case ds_reg: case fs_reg: case gs_reg:
14576       oappend (names_seg[code - es_reg]);
14577       return;
14578     }
14579
14580   USED_REX (REX_B);
14581   if (rex & REX_B)
14582     add = 8;
14583   else
14584     add = 0;
14585
14586   switch (code)
14587     {
14588     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14589     case sp_reg: case bp_reg: case si_reg: case di_reg:
14590       s = names16[code - ax_reg + add];
14591       break;
14592     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14593     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14594       USED_REX (0);
14595       if (rex)
14596         s = names8rex[code - al_reg + add];
14597       else
14598         s = names8[code - al_reg];
14599       break;
14600     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14601     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14602       if (address_mode == mode_64bit
14603           && ((sizeflag & DFLAG) || (rex & REX_W)))
14604         {
14605           s = names64[code - rAX_reg + add];
14606           break;
14607         }
14608       code += eAX_reg - rAX_reg;
14609       /* Fall through.  */
14610     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14611     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14612       USED_REX (REX_W);
14613       if (rex & REX_W)
14614         s = names64[code - eAX_reg + add];
14615       else
14616         {
14617           if (sizeflag & DFLAG)
14618             s = names32[code - eAX_reg + add];
14619           else
14620             s = names16[code - eAX_reg + add];
14621           used_prefixes |= (prefixes & PREFIX_DATA);
14622         }
14623       break;
14624     default:
14625       s = INTERNAL_DISASSEMBLER_ERROR;
14626       break;
14627     }
14628   oappend (s);
14629 }
14630
14631 static void
14632 OP_IMREG (int code, int sizeflag)
14633 {
14634   const char *s;
14635
14636   switch (code)
14637     {
14638     case indir_dx_reg:
14639       if (intel_syntax)
14640         s = "dx";
14641       else
14642         s = "(%dx)";
14643       break;
14644     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14645     case sp_reg: case bp_reg: case si_reg: case di_reg:
14646       s = names16[code - ax_reg];
14647       break;
14648     case es_reg: case ss_reg: case cs_reg:
14649     case ds_reg: case fs_reg: case gs_reg:
14650       s = names_seg[code - es_reg];
14651       break;
14652     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14653     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14654       USED_REX (0);
14655       if (rex)
14656         s = names8rex[code - al_reg];
14657       else
14658         s = names8[code - al_reg];
14659       break;
14660     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14661     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14662       USED_REX (REX_W);
14663       if (rex & REX_W)
14664         s = names64[code - eAX_reg];
14665       else
14666         {
14667           if (sizeflag & DFLAG)
14668             s = names32[code - eAX_reg];
14669           else
14670             s = names16[code - eAX_reg];
14671           used_prefixes |= (prefixes & PREFIX_DATA);
14672         }
14673       break;
14674     case z_mode_ax_reg:
14675       if ((rex & REX_W) || (sizeflag & DFLAG))
14676         s = *names32;
14677       else
14678         s = *names16;
14679       if (!(rex & REX_W))
14680         used_prefixes |= (prefixes & PREFIX_DATA);
14681       break;
14682     default:
14683       s = INTERNAL_DISASSEMBLER_ERROR;
14684       break;
14685     }
14686   oappend (s);
14687 }
14688
14689 static void
14690 OP_I (int bytemode, int sizeflag)
14691 {
14692   bfd_signed_vma op;
14693   bfd_signed_vma mask = -1;
14694
14695   switch (bytemode)
14696     {
14697     case b_mode:
14698       FETCH_DATA (the_info, codep + 1);
14699       op = *codep++;
14700       mask = 0xff;
14701       break;
14702     case v_mode:
14703       USED_REX (REX_W);
14704       if (rex & REX_W)
14705         op = get32s ();
14706       else
14707         {
14708           if (sizeflag & DFLAG)
14709             {
14710               op = get32 ();
14711               mask = 0xffffffff;
14712             }
14713           else
14714             {
14715               op = get16 ();
14716               mask = 0xfffff;
14717             }
14718           used_prefixes |= (prefixes & PREFIX_DATA);
14719         }
14720       break;
14721     case d_mode:
14722       mask = 0xffffffff;
14723       op = get32 ();
14724       break;
14725     case w_mode:
14726       mask = 0xfffff;
14727       op = get16 ();
14728       break;
14729     case const_1_mode:
14730       if (intel_syntax)
14731         oappend ("1");
14732       return;
14733     default:
14734       oappend (INTERNAL_DISASSEMBLER_ERROR);
14735       return;
14736     }
14737
14738   op &= mask;
14739   scratchbuf[0] = '$';
14740   print_operand_value (scratchbuf + 1, 1, op);
14741   oappend_maybe_intel (scratchbuf);
14742   scratchbuf[0] = '\0';
14743 }
14744
14745 static void
14746 OP_I64 (int bytemode, int sizeflag)
14747 {
14748   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14749     {
14750       OP_I (bytemode, sizeflag);
14751       return;
14752     }
14753
14754   USED_REX (REX_W);
14755
14756   scratchbuf[0] = '$';
14757   print_operand_value (scratchbuf + 1, 1, get64 ());
14758   oappend_maybe_intel (scratchbuf);
14759   scratchbuf[0] = '\0';
14760 }
14761
14762 static void
14763 OP_sI (int bytemode, int sizeflag)
14764 {
14765   bfd_signed_vma op;
14766
14767   switch (bytemode)
14768     {
14769     case b_mode:
14770     case b_T_mode:
14771       FETCH_DATA (the_info, codep + 1);
14772       op = *codep++;
14773       if ((op & 0x80) != 0)
14774         op -= 0x100;
14775       if (bytemode == b_T_mode)
14776         {
14777           if (address_mode != mode_64bit
14778               || !((sizeflag & DFLAG) || (rex & REX_W)))
14779             {
14780               /* The operand-size prefix is overridden by a REX prefix.  */
14781               if ((sizeflag & DFLAG) || (rex & REX_W))
14782                 op &= 0xffffffff;
14783               else
14784                 op &= 0xffff;
14785           }
14786         }
14787       else
14788         {
14789           if (!(rex & REX_W))
14790             {
14791               if (sizeflag & DFLAG)
14792                 op &= 0xffffffff;
14793               else
14794                 op &= 0xffff;
14795             }
14796         }
14797       break;
14798     case v_mode:
14799       /* The operand-size prefix is overridden by a REX prefix.  */
14800       if ((sizeflag & DFLAG) || (rex & REX_W))
14801         op = get32s ();
14802       else
14803         op = get16 ();
14804       break;
14805     default:
14806       oappend (INTERNAL_DISASSEMBLER_ERROR);
14807       return;
14808     }
14809
14810   scratchbuf[0] = '$';
14811   print_operand_value (scratchbuf + 1, 1, op);
14812   oappend_maybe_intel (scratchbuf);
14813 }
14814
14815 static void
14816 OP_J (int bytemode, int sizeflag)
14817 {
14818   bfd_vma disp;
14819   bfd_vma mask = -1;
14820   bfd_vma segment = 0;
14821
14822   switch (bytemode)
14823     {
14824     case b_mode:
14825       FETCH_DATA (the_info, codep + 1);
14826       disp = *codep++;
14827       if ((disp & 0x80) != 0)
14828         disp -= 0x100;
14829       break;
14830     case v_mode:
14831       if (isa64 == amd64)
14832         USED_REX (REX_W);
14833       if ((sizeflag & DFLAG)
14834           || (address_mode == mode_64bit
14835               && (isa64 != amd64 || (rex & REX_W))))
14836         disp = get32s ();
14837       else
14838         {
14839           disp = get16 ();
14840           if ((disp & 0x8000) != 0)
14841             disp -= 0x10000;
14842           /* In 16bit mode, address is wrapped around at 64k within
14843              the same segment.  Otherwise, a data16 prefix on a jump
14844              instruction means that the pc is masked to 16 bits after
14845              the displacement is added!  */
14846           mask = 0xffff;
14847           if ((prefixes & PREFIX_DATA) == 0)
14848             segment = ((start_pc + (codep - start_codep))
14849                        & ~((bfd_vma) 0xffff));
14850         }
14851       if (address_mode != mode_64bit
14852           || (isa64 == amd64 && !(rex & REX_W)))
14853         used_prefixes |= (prefixes & PREFIX_DATA);
14854       break;
14855     default:
14856       oappend (INTERNAL_DISASSEMBLER_ERROR);
14857       return;
14858     }
14859   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14860   set_op (disp, 0);
14861   print_operand_value (scratchbuf, 1, disp);
14862   oappend (scratchbuf);
14863 }
14864
14865 static void
14866 OP_SEG (int bytemode, int sizeflag)
14867 {
14868   if (bytemode == w_mode)
14869     oappend (names_seg[modrm.reg]);
14870   else
14871     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14872 }
14873
14874 static void
14875 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14876 {
14877   int seg, offset;
14878
14879   if (sizeflag & DFLAG)
14880     {
14881       offset = get32 ();
14882       seg = get16 ();
14883     }
14884   else
14885     {
14886       offset = get16 ();
14887       seg = get16 ();
14888     }
14889   used_prefixes |= (prefixes & PREFIX_DATA);
14890   if (intel_syntax)
14891     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14892   else
14893     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14894   oappend (scratchbuf);
14895 }
14896
14897 static void
14898 OP_OFF (int bytemode, int sizeflag)
14899 {
14900   bfd_vma off;
14901
14902   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14903     intel_operand_size (bytemode, sizeflag);
14904   append_seg ();
14905
14906   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14907     off = get32 ();
14908   else
14909     off = get16 ();
14910
14911   if (intel_syntax)
14912     {
14913       if (!active_seg_prefix)
14914         {
14915           oappend (names_seg[ds_reg - es_reg]);
14916           oappend (":");
14917         }
14918     }
14919   print_operand_value (scratchbuf, 1, off);
14920   oappend (scratchbuf);
14921 }
14922
14923 static void
14924 OP_OFF64 (int bytemode, int sizeflag)
14925 {
14926   bfd_vma off;
14927
14928   if (address_mode != mode_64bit
14929       || (prefixes & PREFIX_ADDR))
14930     {
14931       OP_OFF (bytemode, sizeflag);
14932       return;
14933     }
14934
14935   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14936     intel_operand_size (bytemode, sizeflag);
14937   append_seg ();
14938
14939   off = get64 ();
14940
14941   if (intel_syntax)
14942     {
14943       if (!active_seg_prefix)
14944         {
14945           oappend (names_seg[ds_reg - es_reg]);
14946           oappend (":");
14947         }
14948     }
14949   print_operand_value (scratchbuf, 1, off);
14950   oappend (scratchbuf);
14951 }
14952
14953 static void
14954 ptr_reg (int code, int sizeflag)
14955 {
14956   const char *s;
14957
14958   *obufp++ = open_char;
14959   used_prefixes |= (prefixes & PREFIX_ADDR);
14960   if (address_mode == mode_64bit)
14961     {
14962       if (!(sizeflag & AFLAG))
14963         s = names32[code - eAX_reg];
14964       else
14965         s = names64[code - eAX_reg];
14966     }
14967   else if (sizeflag & AFLAG)
14968     s = names32[code - eAX_reg];
14969   else
14970     s = names16[code - eAX_reg];
14971   oappend (s);
14972   *obufp++ = close_char;
14973   *obufp = 0;
14974 }
14975
14976 static void
14977 OP_ESreg (int code, int sizeflag)
14978 {
14979   if (intel_syntax)
14980     {
14981       switch (codep[-1])
14982         {
14983         case 0x6d:      /* insw/insl */
14984           intel_operand_size (z_mode, sizeflag);
14985           break;
14986         case 0xa5:      /* movsw/movsl/movsq */
14987         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14988         case 0xab:      /* stosw/stosl */
14989         case 0xaf:      /* scasw/scasl */
14990           intel_operand_size (v_mode, sizeflag);
14991           break;
14992         default:
14993           intel_operand_size (b_mode, sizeflag);
14994         }
14995     }
14996   oappend_maybe_intel ("%es:");
14997   ptr_reg (code, sizeflag);
14998 }
14999
15000 static void
15001 OP_DSreg (int code, int sizeflag)
15002 {
15003   if (intel_syntax)
15004     {
15005       switch (codep[-1])
15006         {
15007         case 0x6f:      /* outsw/outsl */
15008           intel_operand_size (z_mode, sizeflag);
15009           break;
15010         case 0xa5:      /* movsw/movsl/movsq */
15011         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15012         case 0xad:      /* lodsw/lodsl/lodsq */
15013           intel_operand_size (v_mode, sizeflag);
15014           break;
15015         default:
15016           intel_operand_size (b_mode, sizeflag);
15017         }
15018     }
15019   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15020      default segment register DS is printed.  */
15021   if (!active_seg_prefix)
15022     active_seg_prefix = PREFIX_DS;
15023   append_seg ();
15024   ptr_reg (code, sizeflag);
15025 }
15026
15027 static void
15028 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15029 {
15030   int add;
15031   if (rex & REX_R)
15032     {
15033       USED_REX (REX_R);
15034       add = 8;
15035     }
15036   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15037     {
15038       all_prefixes[last_lock_prefix] = 0;
15039       used_prefixes |= PREFIX_LOCK;
15040       add = 8;
15041     }
15042   else
15043     add = 0;
15044   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15045   oappend_maybe_intel (scratchbuf);
15046 }
15047
15048 static void
15049 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15050 {
15051   int add;
15052   USED_REX (REX_R);
15053   if (rex & REX_R)
15054     add = 8;
15055   else
15056     add = 0;
15057   if (intel_syntax)
15058     sprintf (scratchbuf, "db%d", modrm.reg + add);
15059   else
15060     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15061   oappend (scratchbuf);
15062 }
15063
15064 static void
15065 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15066 {
15067   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15068   oappend_maybe_intel (scratchbuf);
15069 }
15070
15071 static void
15072 OP_R (int bytemode, int sizeflag)
15073 {
15074   /* Skip mod/rm byte.  */
15075   MODRM_CHECK;
15076   codep++;
15077   OP_E_register (bytemode, sizeflag);
15078 }
15079
15080 static void
15081 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15082 {
15083   int reg = modrm.reg;
15084   const char **names;
15085
15086   used_prefixes |= (prefixes & PREFIX_DATA);
15087   if (prefixes & PREFIX_DATA)
15088     {
15089       names = names_xmm;
15090       USED_REX (REX_R);
15091       if (rex & REX_R)
15092         reg += 8;
15093     }
15094   else
15095     names = names_mm;
15096   oappend (names[reg]);
15097 }
15098
15099 static void
15100 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15101 {
15102   int reg = modrm.reg;
15103   const char **names;
15104
15105   USED_REX (REX_R);
15106   if (rex & REX_R)
15107     reg += 8;
15108   if (vex.evex)
15109     {
15110       if (!vex.r)
15111         reg += 16;
15112     }
15113
15114   if (need_vex
15115       && bytemode != xmm_mode
15116       && bytemode != xmmq_mode
15117       && bytemode != evex_half_bcst_xmmq_mode
15118       && bytemode != ymm_mode
15119       && bytemode != scalar_mode)
15120     {
15121       switch (vex.length)
15122         {
15123         case 128:
15124           names = names_xmm;
15125           break;
15126         case 256:
15127           if (vex.w
15128               || (bytemode != vex_vsib_q_w_dq_mode
15129                   && bytemode != vex_vsib_q_w_d_mode))
15130             names = names_ymm;
15131           else
15132             names = names_xmm;
15133           break;
15134         case 512:
15135           names = names_zmm;
15136           break;
15137         default:
15138           abort ();
15139         }
15140     }
15141   else if (bytemode == xmmq_mode
15142            || bytemode == evex_half_bcst_xmmq_mode)
15143     {
15144       switch (vex.length)
15145         {
15146         case 128:
15147         case 256:
15148           names = names_xmm;
15149           break;
15150         case 512:
15151           names = names_ymm;
15152           break;
15153         default:
15154           abort ();
15155         }
15156     }
15157   else if (bytemode == ymm_mode)
15158     names = names_ymm;
15159   else
15160     names = names_xmm;
15161   oappend (names[reg]);
15162 }
15163
15164 static void
15165 OP_EM (int bytemode, int sizeflag)
15166 {
15167   int reg;
15168   const char **names;
15169
15170   if (modrm.mod != 3)
15171     {
15172       if (intel_syntax
15173           && (bytemode == v_mode || bytemode == v_swap_mode))
15174         {
15175           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15176           used_prefixes |= (prefixes & PREFIX_DATA);
15177         }
15178       OP_E (bytemode, sizeflag);
15179       return;
15180     }
15181
15182   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15183     swap_operand ();
15184
15185   /* Skip mod/rm byte.  */
15186   MODRM_CHECK;
15187   codep++;
15188   used_prefixes |= (prefixes & PREFIX_DATA);
15189   reg = modrm.rm;
15190   if (prefixes & PREFIX_DATA)
15191     {
15192       names = names_xmm;
15193       USED_REX (REX_B);
15194       if (rex & REX_B)
15195         reg += 8;
15196     }
15197   else
15198     names = names_mm;
15199   oappend (names[reg]);
15200 }
15201
15202 /* cvt* are the only instructions in sse2 which have
15203    both SSE and MMX operands and also have 0x66 prefix
15204    in their opcode. 0x66 was originally used to differentiate
15205    between SSE and MMX instruction(operands). So we have to handle the
15206    cvt* separately using OP_EMC and OP_MXC */
15207 static void
15208 OP_EMC (int bytemode, int sizeflag)
15209 {
15210   if (modrm.mod != 3)
15211     {
15212       if (intel_syntax && bytemode == v_mode)
15213         {
15214           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15215           used_prefixes |= (prefixes & PREFIX_DATA);
15216         }
15217       OP_E (bytemode, sizeflag);
15218       return;
15219     }
15220
15221   /* Skip mod/rm byte.  */
15222   MODRM_CHECK;
15223   codep++;
15224   used_prefixes |= (prefixes & PREFIX_DATA);
15225   oappend (names_mm[modrm.rm]);
15226 }
15227
15228 static void
15229 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15230 {
15231   used_prefixes |= (prefixes & PREFIX_DATA);
15232   oappend (names_mm[modrm.reg]);
15233 }
15234
15235 static void
15236 OP_EX (int bytemode, int sizeflag)
15237 {
15238   int reg;
15239   const char **names;
15240
15241   /* Skip mod/rm byte.  */
15242   MODRM_CHECK;
15243   codep++;
15244
15245   if (modrm.mod != 3)
15246     {
15247       OP_E_memory (bytemode, sizeflag);
15248       return;
15249     }
15250
15251   reg = modrm.rm;
15252   USED_REX (REX_B);
15253   if (rex & REX_B)
15254     reg += 8;
15255   if (vex.evex)
15256     {
15257       USED_REX (REX_X);
15258       if ((rex & REX_X))
15259         reg += 16;
15260     }
15261
15262   if ((sizeflag & SUFFIX_ALWAYS)
15263       && (bytemode == x_swap_mode
15264           || bytemode == d_swap_mode
15265           || bytemode == d_scalar_swap_mode
15266           || bytemode == q_swap_mode
15267           || bytemode == q_scalar_swap_mode))
15268     swap_operand ();
15269
15270   if (need_vex
15271       && bytemode != xmm_mode
15272       && bytemode != xmmdw_mode
15273       && bytemode != xmmqd_mode
15274       && bytemode != xmm_mb_mode
15275       && bytemode != xmm_mw_mode
15276       && bytemode != xmm_md_mode
15277       && bytemode != xmm_mq_mode
15278       && bytemode != xmm_mdq_mode
15279       && bytemode != xmmq_mode
15280       && bytemode != evex_half_bcst_xmmq_mode
15281       && bytemode != ymm_mode
15282       && bytemode != d_scalar_mode
15283       && bytemode != d_scalar_swap_mode
15284       && bytemode != q_scalar_mode
15285       && bytemode != q_scalar_swap_mode
15286       && bytemode != vex_scalar_w_dq_mode)
15287     {
15288       switch (vex.length)
15289         {
15290         case 128:
15291           names = names_xmm;
15292           break;
15293         case 256:
15294           names = names_ymm;
15295           break;
15296         case 512:
15297           names = names_zmm;
15298           break;
15299         default:
15300           abort ();
15301         }
15302     }
15303   else if (bytemode == xmmq_mode
15304            || bytemode == evex_half_bcst_xmmq_mode)
15305     {
15306       switch (vex.length)
15307         {
15308         case 128:
15309         case 256:
15310           names = names_xmm;
15311           break;
15312         case 512:
15313           names = names_ymm;
15314           break;
15315         default:
15316           abort ();
15317         }
15318     }
15319   else if (bytemode == ymm_mode)
15320     names = names_ymm;
15321   else
15322     names = names_xmm;
15323   oappend (names[reg]);
15324 }
15325
15326 static void
15327 OP_MS (int bytemode, int sizeflag)
15328 {
15329   if (modrm.mod == 3)
15330     OP_EM (bytemode, sizeflag);
15331   else
15332     BadOp ();
15333 }
15334
15335 static void
15336 OP_XS (int bytemode, int sizeflag)
15337 {
15338   if (modrm.mod == 3)
15339     OP_EX (bytemode, sizeflag);
15340   else
15341     BadOp ();
15342 }
15343
15344 static void
15345 OP_M (int bytemode, int sizeflag)
15346 {
15347   if (modrm.mod == 3)
15348     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15349     BadOp ();
15350   else
15351     OP_E (bytemode, sizeflag);
15352 }
15353
15354 static void
15355 OP_0f07 (int bytemode, int sizeflag)
15356 {
15357   if (modrm.mod != 3 || modrm.rm != 0)
15358     BadOp ();
15359   else
15360     OP_E (bytemode, sizeflag);
15361 }
15362
15363 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15364    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15365
15366 static void
15367 NOP_Fixup1 (int bytemode, int sizeflag)
15368 {
15369   if ((prefixes & PREFIX_DATA) != 0
15370       || (rex != 0
15371           && rex != 0x48
15372           && address_mode == mode_64bit))
15373     OP_REG (bytemode, sizeflag);
15374   else
15375     strcpy (obuf, "nop");
15376 }
15377
15378 static void
15379 NOP_Fixup2 (int bytemode, int sizeflag)
15380 {
15381   if ((prefixes & PREFIX_DATA) != 0
15382       || (rex != 0
15383           && rex != 0x48
15384           && address_mode == mode_64bit))
15385     OP_IMREG (bytemode, sizeflag);
15386 }
15387
15388 static const char *const Suffix3DNow[] = {
15389 /* 00 */        NULL,           NULL,           NULL,           NULL,
15390 /* 04 */        NULL,           NULL,           NULL,           NULL,
15391 /* 08 */        NULL,           NULL,           NULL,           NULL,
15392 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15393 /* 10 */        NULL,           NULL,           NULL,           NULL,
15394 /* 14 */        NULL,           NULL,           NULL,           NULL,
15395 /* 18 */        NULL,           NULL,           NULL,           NULL,
15396 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15397 /* 20 */        NULL,           NULL,           NULL,           NULL,
15398 /* 24 */        NULL,           NULL,           NULL,           NULL,
15399 /* 28 */        NULL,           NULL,           NULL,           NULL,
15400 /* 2C */        NULL,           NULL,           NULL,           NULL,
15401 /* 30 */        NULL,           NULL,           NULL,           NULL,
15402 /* 34 */        NULL,           NULL,           NULL,           NULL,
15403 /* 38 */        NULL,           NULL,           NULL,           NULL,
15404 /* 3C */        NULL,           NULL,           NULL,           NULL,
15405 /* 40 */        NULL,           NULL,           NULL,           NULL,
15406 /* 44 */        NULL,           NULL,           NULL,           NULL,
15407 /* 48 */        NULL,           NULL,           NULL,           NULL,
15408 /* 4C */        NULL,           NULL,           NULL,           NULL,
15409 /* 50 */        NULL,           NULL,           NULL,           NULL,
15410 /* 54 */        NULL,           NULL,           NULL,           NULL,
15411 /* 58 */        NULL,           NULL,           NULL,           NULL,
15412 /* 5C */        NULL,           NULL,           NULL,           NULL,
15413 /* 60 */        NULL,           NULL,           NULL,           NULL,
15414 /* 64 */        NULL,           NULL,           NULL,           NULL,
15415 /* 68 */        NULL,           NULL,           NULL,           NULL,
15416 /* 6C */        NULL,           NULL,           NULL,           NULL,
15417 /* 70 */        NULL,           NULL,           NULL,           NULL,
15418 /* 74 */        NULL,           NULL,           NULL,           NULL,
15419 /* 78 */        NULL,           NULL,           NULL,           NULL,
15420 /* 7C */        NULL,           NULL,           NULL,           NULL,
15421 /* 80 */        NULL,           NULL,           NULL,           NULL,
15422 /* 84 */        NULL,           NULL,           NULL,           NULL,
15423 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15424 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15425 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15426 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15427 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15428 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15429 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15430 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15431 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15432 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15433 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15434 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15435 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15436 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15437 /* C0 */        NULL,           NULL,           NULL,           NULL,
15438 /* C4 */        NULL,           NULL,           NULL,           NULL,
15439 /* C8 */        NULL,           NULL,           NULL,           NULL,
15440 /* CC */        NULL,           NULL,           NULL,           NULL,
15441 /* D0 */        NULL,           NULL,           NULL,           NULL,
15442 /* D4 */        NULL,           NULL,           NULL,           NULL,
15443 /* D8 */        NULL,           NULL,           NULL,           NULL,
15444 /* DC */        NULL,           NULL,           NULL,           NULL,
15445 /* E0 */        NULL,           NULL,           NULL,           NULL,
15446 /* E4 */        NULL,           NULL,           NULL,           NULL,
15447 /* E8 */        NULL,           NULL,           NULL,           NULL,
15448 /* EC */        NULL,           NULL,           NULL,           NULL,
15449 /* F0 */        NULL,           NULL,           NULL,           NULL,
15450 /* F4 */        NULL,           NULL,           NULL,           NULL,
15451 /* F8 */        NULL,           NULL,           NULL,           NULL,
15452 /* FC */        NULL,           NULL,           NULL,           NULL,
15453 };
15454
15455 static void
15456 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15457 {
15458   const char *mnemonic;
15459
15460   FETCH_DATA (the_info, codep + 1);
15461   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15462      place where an 8-bit immediate would normally go.  ie. the last
15463      byte of the instruction.  */
15464   obufp = mnemonicendp;
15465   mnemonic = Suffix3DNow[*codep++ & 0xff];
15466   if (mnemonic)
15467     oappend (mnemonic);
15468   else
15469     {
15470       /* Since a variable sized modrm/sib chunk is between the start
15471          of the opcode (0x0f0f) and the opcode suffix, we need to do
15472          all the modrm processing first, and don't know until now that
15473          we have a bad opcode.  This necessitates some cleaning up.  */
15474       op_out[0][0] = '\0';
15475       op_out[1][0] = '\0';
15476       BadOp ();
15477     }
15478   mnemonicendp = obufp;
15479 }
15480
15481 static struct op simd_cmp_op[] =
15482 {
15483   { STRING_COMMA_LEN ("eq") },
15484   { STRING_COMMA_LEN ("lt") },
15485   { STRING_COMMA_LEN ("le") },
15486   { STRING_COMMA_LEN ("unord") },
15487   { STRING_COMMA_LEN ("neq") },
15488   { STRING_COMMA_LEN ("nlt") },
15489   { STRING_COMMA_LEN ("nle") },
15490   { STRING_COMMA_LEN ("ord") }
15491 };
15492
15493 static void
15494 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15495 {
15496   unsigned int cmp_type;
15497
15498   FETCH_DATA (the_info, codep + 1);
15499   cmp_type = *codep++ & 0xff;
15500   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15501     {
15502       char suffix [3];
15503       char *p = mnemonicendp - 2;
15504       suffix[0] = p[0];
15505       suffix[1] = p[1];
15506       suffix[2] = '\0';
15507       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15508       mnemonicendp += simd_cmp_op[cmp_type].len;
15509     }
15510   else
15511     {
15512       /* We have a reserved extension byte.  Output it directly.  */
15513       scratchbuf[0] = '$';
15514       print_operand_value (scratchbuf + 1, 1, cmp_type);
15515       oappend_maybe_intel (scratchbuf);
15516       scratchbuf[0] = '\0';
15517     }
15518 }
15519
15520 static void
15521 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15522           int sizeflag ATTRIBUTE_UNUSED)
15523 {
15524   /* mwaitx %eax,%ecx,%ebx */
15525   if (!intel_syntax)
15526     {
15527       const char **names = (address_mode == mode_64bit
15528                             ? names64 : names32);
15529       strcpy (op_out[0], names[0]);
15530       strcpy (op_out[1], names[1]);
15531       strcpy (op_out[2], names[3]);
15532       two_source_ops = 1;
15533     }
15534   /* Skip mod/rm byte.  */
15535   MODRM_CHECK;
15536   codep++;
15537 }
15538
15539 static void
15540 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15541           int sizeflag ATTRIBUTE_UNUSED)
15542 {
15543   /* mwait %eax,%ecx  */
15544   if (!intel_syntax)
15545     {
15546       const char **names = (address_mode == mode_64bit
15547                             ? names64 : names32);
15548       strcpy (op_out[0], names[0]);
15549       strcpy (op_out[1], names[1]);
15550       two_source_ops = 1;
15551     }
15552   /* Skip mod/rm byte.  */
15553   MODRM_CHECK;
15554   codep++;
15555 }
15556
15557 static void
15558 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15559             int sizeflag ATTRIBUTE_UNUSED)
15560 {
15561   /* monitor %eax,%ecx,%edx"  */
15562   if (!intel_syntax)
15563     {
15564       const char **op1_names;
15565       const char **names = (address_mode == mode_64bit
15566                             ? names64 : names32);
15567
15568       if (!(prefixes & PREFIX_ADDR))
15569         op1_names = (address_mode == mode_16bit
15570                      ? names16 : names);
15571       else
15572         {
15573           /* Remove "addr16/addr32".  */
15574           all_prefixes[last_addr_prefix] = 0;
15575           op1_names = (address_mode != mode_32bit
15576                        ? names32 : names16);
15577           used_prefixes |= PREFIX_ADDR;
15578         }
15579       strcpy (op_out[0], op1_names[0]);
15580       strcpy (op_out[1], names[1]);
15581       strcpy (op_out[2], names[2]);
15582       two_source_ops = 1;
15583     }
15584   /* Skip mod/rm byte.  */
15585   MODRM_CHECK;
15586   codep++;
15587 }
15588
15589 static void
15590 BadOp (void)
15591 {
15592   /* Throw away prefixes and 1st. opcode byte.  */
15593   codep = insn_codep + 1;
15594   oappend ("(bad)");
15595 }
15596
15597 static void
15598 REP_Fixup (int bytemode, int sizeflag)
15599 {
15600   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15601      lods and stos.  */
15602   if (prefixes & PREFIX_REPZ)
15603     all_prefixes[last_repz_prefix] = REP_PREFIX;
15604
15605   switch (bytemode)
15606     {
15607     case al_reg:
15608     case eAX_reg:
15609     case indir_dx_reg:
15610       OP_IMREG (bytemode, sizeflag);
15611       break;
15612     case eDI_reg:
15613       OP_ESreg (bytemode, sizeflag);
15614       break;
15615     case eSI_reg:
15616       OP_DSreg (bytemode, sizeflag);
15617       break;
15618     default:
15619       abort ();
15620       break;
15621     }
15622 }
15623
15624 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15625    "bnd".  */
15626
15627 static void
15628 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15629 {
15630   if (prefixes & PREFIX_REPNZ)
15631     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15632 }
15633
15634 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15635    "notrack".  */
15636
15637 static void
15638 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15639                int sizeflag ATTRIBUTE_UNUSED)
15640 {
15641   if (active_seg_prefix == PREFIX_DS
15642       && (address_mode != mode_64bit || last_data_prefix < 0))
15643     {
15644       /* NOTRACK prefix is only valid on indirect branch instructions.
15645          NB: DATA prefix is unsupported for Intel64.  */
15646       active_seg_prefix = 0;
15647       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15648     }
15649 }
15650
15651 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15652    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15653  */
15654
15655 static void
15656 HLE_Fixup1 (int bytemode, int sizeflag)
15657 {
15658   if (modrm.mod != 3
15659       && (prefixes & PREFIX_LOCK) != 0)
15660     {
15661       if (prefixes & PREFIX_REPZ)
15662         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15663       if (prefixes & PREFIX_REPNZ)
15664         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15665     }
15666
15667   OP_E (bytemode, sizeflag);
15668 }
15669
15670 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15671    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15672  */
15673
15674 static void
15675 HLE_Fixup2 (int bytemode, int sizeflag)
15676 {
15677   if (modrm.mod != 3)
15678     {
15679       if (prefixes & PREFIX_REPZ)
15680         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15681       if (prefixes & PREFIX_REPNZ)
15682         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15683     }
15684
15685   OP_E (bytemode, sizeflag);
15686 }
15687
15688 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15689    "xrelease" for memory operand.  No check for LOCK prefix.   */
15690
15691 static void
15692 HLE_Fixup3 (int bytemode, int sizeflag)
15693 {
15694   if (modrm.mod != 3
15695       && last_repz_prefix > last_repnz_prefix
15696       && (prefixes & PREFIX_REPZ) != 0)
15697     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15698
15699   OP_E (bytemode, sizeflag);
15700 }
15701
15702 static void
15703 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15704 {
15705   USED_REX (REX_W);
15706   if (rex & REX_W)
15707     {
15708       /* Change cmpxchg8b to cmpxchg16b.  */
15709       char *p = mnemonicendp - 2;
15710       mnemonicendp = stpcpy (p, "16b");
15711       bytemode = o_mode;
15712     }
15713   else if ((prefixes & PREFIX_LOCK) != 0)
15714     {
15715       if (prefixes & PREFIX_REPZ)
15716         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15717       if (prefixes & PREFIX_REPNZ)
15718         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15719     }
15720
15721   OP_M (bytemode, sizeflag);
15722 }
15723
15724 static void
15725 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15726 {
15727   const char **names;
15728
15729   if (need_vex)
15730     {
15731       switch (vex.length)
15732         {
15733         case 128:
15734           names = names_xmm;
15735           break;
15736         case 256:
15737           names = names_ymm;
15738           break;
15739         default:
15740           abort ();
15741         }
15742     }
15743   else
15744     names = names_xmm;
15745   oappend (names[reg]);
15746 }
15747
15748 static void
15749 CRC32_Fixup (int bytemode, int sizeflag)
15750 {
15751   /* Add proper suffix to "crc32".  */
15752   char *p = mnemonicendp;
15753
15754   switch (bytemode)
15755     {
15756     case b_mode:
15757       if (intel_syntax)
15758         goto skip;
15759
15760       *p++ = 'b';
15761       break;
15762     case v_mode:
15763       if (intel_syntax)
15764         goto skip;
15765
15766       USED_REX (REX_W);
15767       if (rex & REX_W)
15768         *p++ = 'q';
15769       else
15770         {
15771           if (sizeflag & DFLAG)
15772             *p++ = 'l';
15773           else
15774             *p++ = 'w';
15775           used_prefixes |= (prefixes & PREFIX_DATA);
15776         }
15777       break;
15778     default:
15779       oappend (INTERNAL_DISASSEMBLER_ERROR);
15780       break;
15781     }
15782   mnemonicendp = p;
15783   *p = '\0';
15784
15785 skip:
15786   if (modrm.mod == 3)
15787     {
15788       int add;
15789
15790       /* Skip mod/rm byte.  */
15791       MODRM_CHECK;
15792       codep++;
15793
15794       USED_REX (REX_B);
15795       add = (rex & REX_B) ? 8 : 0;
15796       if (bytemode == b_mode)
15797         {
15798           USED_REX (0);
15799           if (rex)
15800             oappend (names8rex[modrm.rm + add]);
15801           else
15802             oappend (names8[modrm.rm + add]);
15803         }
15804       else
15805         {
15806           USED_REX (REX_W);
15807           if (rex & REX_W)
15808             oappend (names64[modrm.rm + add]);
15809           else if ((prefixes & PREFIX_DATA))
15810             oappend (names16[modrm.rm + add]);
15811           else
15812             oappend (names32[modrm.rm + add]);
15813         }
15814     }
15815   else
15816     OP_E (bytemode, sizeflag);
15817 }
15818
15819 static void
15820 FXSAVE_Fixup (int bytemode, int sizeflag)
15821 {
15822   /* Add proper suffix to "fxsave" and "fxrstor".  */
15823   USED_REX (REX_W);
15824   if (rex & REX_W)
15825     {
15826       char *p = mnemonicendp;
15827       *p++ = '6';
15828       *p++ = '4';
15829       *p = '\0';
15830       mnemonicendp = p;
15831     }
15832   OP_M (bytemode, sizeflag);
15833 }
15834
15835 static void
15836 PCMPESTR_Fixup (int bytemode, int sizeflag)
15837 {
15838   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15839   if (!intel_syntax)
15840     {
15841       char *p = mnemonicendp;
15842
15843       USED_REX (REX_W);
15844       if (rex & REX_W)
15845         *p++ = 'q';
15846       else if (sizeflag & SUFFIX_ALWAYS)
15847         *p++ = 'l';
15848
15849       *p = '\0';
15850       mnemonicendp = p;
15851     }
15852
15853   OP_EX (bytemode, sizeflag);
15854 }
15855
15856 /* Display the destination register operand for instructions with
15857    VEX. */
15858
15859 static void
15860 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15861 {
15862   int reg;
15863   const char **names;
15864
15865   if (!need_vex)
15866     abort ();
15867
15868   if (!need_vex_reg)
15869     return;
15870
15871   reg = vex.register_specifier;
15872   vex.register_specifier = 0;
15873   if (address_mode != mode_64bit)
15874     reg &= 7;
15875   else if (vex.evex && !vex.v)
15876     reg += 16;
15877
15878   if (bytemode == vex_scalar_mode)
15879     {
15880       oappend (names_xmm[reg]);
15881       return;
15882     }
15883
15884   switch (vex.length)
15885     {
15886     case 128:
15887       switch (bytemode)
15888         {
15889         case vex_mode:
15890         case vex128_mode:
15891         case vex_vsib_q_w_dq_mode:
15892         case vex_vsib_q_w_d_mode:
15893           names = names_xmm;
15894           break;
15895         case dq_mode:
15896           if (rex & REX_W)
15897             names = names64;
15898           else
15899             names = names32;
15900           break;
15901         case mask_bd_mode:
15902         case mask_mode:
15903           if (reg > 0x7)
15904             {
15905               oappend ("(bad)");
15906               return;
15907             }
15908           names = names_mask;
15909           break;
15910         default:
15911           abort ();
15912           return;
15913         }
15914       break;
15915     case 256:
15916       switch (bytemode)
15917         {
15918         case vex_mode:
15919         case vex256_mode:
15920           names = names_ymm;
15921           break;
15922         case vex_vsib_q_w_dq_mode:
15923         case vex_vsib_q_w_d_mode:
15924           names = vex.w ? names_ymm : names_xmm;
15925           break;
15926         case mask_bd_mode:
15927         case mask_mode:
15928           if (reg > 0x7)
15929             {
15930               oappend ("(bad)");
15931               return;
15932             }
15933           names = names_mask;
15934           break;
15935         default:
15936           /* See PR binutils/20893 for a reproducer.  */
15937           oappend ("(bad)");
15938           return;
15939         }
15940       break;
15941     case 512:
15942       names = names_zmm;
15943       break;
15944     default:
15945       abort ();
15946       break;
15947     }
15948   oappend (names[reg]);
15949 }
15950
15951 /* Get the VEX immediate byte without moving codep.  */
15952
15953 static unsigned char
15954 get_vex_imm8 (int sizeflag, int opnum)
15955 {
15956   int bytes_before_imm = 0;
15957
15958   if (modrm.mod != 3)
15959     {
15960       /* There are SIB/displacement bytes.  */
15961       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15962         {
15963           /* 32/64 bit address mode */
15964           int base = modrm.rm;
15965
15966           /* Check SIB byte.  */
15967           if (base == 4)
15968             {
15969               FETCH_DATA (the_info, codep + 1);
15970               base = *codep & 7;
15971               /* When decoding the third source, don't increase
15972                  bytes_before_imm as this has already been incremented
15973                  by one in OP_E_memory while decoding the second
15974                  source operand.  */
15975               if (opnum == 0)
15976                 bytes_before_imm++;
15977             }
15978
15979           /* Don't increase bytes_before_imm when decoding the third source,
15980              it has already been incremented by OP_E_memory while decoding
15981              the second source operand.  */
15982           if (opnum == 0)
15983             {
15984               switch (modrm.mod)
15985                 {
15986                   case 0:
15987                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15988                        SIB == 5, there is a 4 byte displacement.  */
15989                     if (base != 5)
15990                       /* No displacement. */
15991                       break;
15992                     /* Fall through.  */
15993                   case 2:
15994                     /* 4 byte displacement.  */
15995                     bytes_before_imm += 4;
15996                     break;
15997                   case 1:
15998                     /* 1 byte displacement.  */
15999                     bytes_before_imm++;
16000                     break;
16001                 }
16002             }
16003         }
16004       else
16005         {
16006           /* 16 bit address mode */
16007           /* Don't increase bytes_before_imm when decoding the third source,
16008              it has already been incremented by OP_E_memory while decoding
16009              the second source operand.  */
16010           if (opnum == 0)
16011             {
16012               switch (modrm.mod)
16013                 {
16014                 case 0:
16015                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16016                   if (modrm.rm != 6)
16017                     /* No displacement. */
16018                     break;
16019                   /* Fall through.  */
16020                 case 2:
16021                   /* 2 byte displacement.  */
16022                   bytes_before_imm += 2;
16023                   break;
16024                 case 1:
16025                   /* 1 byte displacement: when decoding the third source,
16026                      don't increase bytes_before_imm as this has already
16027                      been incremented by one in OP_E_memory while decoding
16028                      the second source operand.  */
16029                   if (opnum == 0)
16030                     bytes_before_imm++;
16031
16032                   break;
16033                 }
16034             }
16035         }
16036     }
16037
16038   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16039   return codep [bytes_before_imm];
16040 }
16041
16042 static void
16043 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16044 {
16045   const char **names;
16046
16047   if (reg == -1 && modrm.mod != 3)
16048     {
16049       OP_E_memory (bytemode, sizeflag);
16050       return;
16051     }
16052   else
16053     {
16054       if (reg == -1)
16055         {
16056           reg = modrm.rm;
16057           USED_REX (REX_B);
16058           if (rex & REX_B)
16059             reg += 8;
16060         }
16061       if (address_mode != mode_64bit)
16062         reg &= 7;
16063     }
16064
16065   switch (vex.length)
16066     {
16067     case 128:
16068       names = names_xmm;
16069       break;
16070     case 256:
16071       names = names_ymm;
16072       break;
16073     default:
16074       abort ();
16075     }
16076   oappend (names[reg]);
16077 }
16078
16079 static void
16080 OP_EX_VexImmW (int bytemode, int sizeflag)
16081 {
16082   int reg = -1;
16083   static unsigned char vex_imm8;
16084
16085   if (vex_w_done == 0)
16086     {
16087       vex_w_done = 1;
16088
16089       /* Skip mod/rm byte.  */
16090       MODRM_CHECK;
16091       codep++;
16092
16093       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16094
16095       if (vex.w)
16096           reg = vex_imm8 >> 4;
16097
16098       OP_EX_VexReg (bytemode, sizeflag, reg);
16099     }
16100   else if (vex_w_done == 1)
16101     {
16102       vex_w_done = 2;
16103
16104       if (!vex.w)
16105           reg = vex_imm8 >> 4;
16106
16107       OP_EX_VexReg (bytemode, sizeflag, reg);
16108     }
16109   else
16110     {
16111       /* Output the imm8 directly.  */
16112       scratchbuf[0] = '$';
16113       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16114       oappend_maybe_intel (scratchbuf);
16115       scratchbuf[0] = '\0';
16116       codep++;
16117     }
16118 }
16119
16120 static void
16121 OP_Vex_2src (int bytemode, int sizeflag)
16122 {
16123   if (modrm.mod == 3)
16124     {
16125       int reg = modrm.rm;
16126       USED_REX (REX_B);
16127       if (rex & REX_B)
16128         reg += 8;
16129       oappend (names_xmm[reg]);
16130     }
16131   else
16132     {
16133       if (intel_syntax
16134           && (bytemode == v_mode || bytemode == v_swap_mode))
16135         {
16136           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16137           used_prefixes |= (prefixes & PREFIX_DATA);
16138         }
16139       OP_E (bytemode, sizeflag);
16140     }
16141 }
16142
16143 static void
16144 OP_Vex_2src_1 (int bytemode, int sizeflag)
16145 {
16146   if (modrm.mod == 3)
16147     {
16148       /* Skip mod/rm byte.   */
16149       MODRM_CHECK;
16150       codep++;
16151     }
16152
16153   if (vex.w)
16154     {
16155       unsigned int reg = vex.register_specifier;
16156       vex.register_specifier = 0;
16157
16158       if (address_mode != mode_64bit)
16159         reg &= 7;
16160       oappend (names_xmm[reg]);
16161     }
16162   else
16163     OP_Vex_2src (bytemode, sizeflag);
16164 }
16165
16166 static void
16167 OP_Vex_2src_2 (int bytemode, int sizeflag)
16168 {
16169   if (vex.w)
16170     OP_Vex_2src (bytemode, sizeflag);
16171   else
16172     {
16173       unsigned int reg = vex.register_specifier;
16174       vex.register_specifier = 0;
16175
16176       if (address_mode != mode_64bit)
16177         reg &= 7;
16178       oappend (names_xmm[reg]);
16179     }
16180 }
16181
16182 static void
16183 OP_EX_VexW (int bytemode, int sizeflag)
16184 {
16185   int reg = -1;
16186
16187   if (!vex_w_done)
16188     {
16189       /* Skip mod/rm byte.  */
16190       MODRM_CHECK;
16191       codep++;
16192
16193       if (vex.w)
16194         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16195     }
16196   else
16197     {
16198       if (!vex.w)
16199         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16200     }
16201
16202   OP_EX_VexReg (bytemode, sizeflag, reg);
16203
16204   if (vex_w_done)
16205     codep++;
16206   vex_w_done = 1;
16207 }
16208
16209 static void
16210 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16211 {
16212   int reg;
16213   const char **names;
16214
16215   FETCH_DATA (the_info, codep + 1);
16216   reg = *codep++;
16217
16218   if (bytemode != x_mode)
16219     abort ();
16220
16221   reg >>= 4;
16222   if (address_mode != mode_64bit)
16223     reg &= 7;
16224
16225   switch (vex.length)
16226     {
16227     case 128:
16228       names = names_xmm;
16229       break;
16230     case 256:
16231       names = names_ymm;
16232       break;
16233     default:
16234       abort ();
16235     }
16236   oappend (names[reg]);
16237 }
16238
16239 static void
16240 OP_XMM_VexW (int bytemode, int sizeflag)
16241 {
16242   /* Turn off the REX.W bit since it is used for swapping operands
16243      now.  */
16244   rex &= ~REX_W;
16245   OP_XMM (bytemode, sizeflag);
16246 }
16247
16248 static void
16249 OP_EX_Vex (int bytemode, int sizeflag)
16250 {
16251   if (modrm.mod != 3)
16252     need_vex_reg = 0;
16253   OP_EX (bytemode, sizeflag);
16254 }
16255
16256 static void
16257 OP_XMM_Vex (int bytemode, int sizeflag)
16258 {
16259   if (modrm.mod != 3)
16260     need_vex_reg = 0;
16261   OP_XMM (bytemode, sizeflag);
16262 }
16263
16264 static struct op vex_cmp_op[] =
16265 {
16266   { STRING_COMMA_LEN ("eq") },
16267   { STRING_COMMA_LEN ("lt") },
16268   { STRING_COMMA_LEN ("le") },
16269   { STRING_COMMA_LEN ("unord") },
16270   { STRING_COMMA_LEN ("neq") },
16271   { STRING_COMMA_LEN ("nlt") },
16272   { STRING_COMMA_LEN ("nle") },
16273   { STRING_COMMA_LEN ("ord") },
16274   { STRING_COMMA_LEN ("eq_uq") },
16275   { STRING_COMMA_LEN ("nge") },
16276   { STRING_COMMA_LEN ("ngt") },
16277   { STRING_COMMA_LEN ("false") },
16278   { STRING_COMMA_LEN ("neq_oq") },
16279   { STRING_COMMA_LEN ("ge") },
16280   { STRING_COMMA_LEN ("gt") },
16281   { STRING_COMMA_LEN ("true") },
16282   { STRING_COMMA_LEN ("eq_os") },
16283   { STRING_COMMA_LEN ("lt_oq") },
16284   { STRING_COMMA_LEN ("le_oq") },
16285   { STRING_COMMA_LEN ("unord_s") },
16286   { STRING_COMMA_LEN ("neq_us") },
16287   { STRING_COMMA_LEN ("nlt_uq") },
16288   { STRING_COMMA_LEN ("nle_uq") },
16289   { STRING_COMMA_LEN ("ord_s") },
16290   { STRING_COMMA_LEN ("eq_us") },
16291   { STRING_COMMA_LEN ("nge_uq") },
16292   { STRING_COMMA_LEN ("ngt_uq") },
16293   { STRING_COMMA_LEN ("false_os") },
16294   { STRING_COMMA_LEN ("neq_os") },
16295   { STRING_COMMA_LEN ("ge_oq") },
16296   { STRING_COMMA_LEN ("gt_oq") },
16297   { STRING_COMMA_LEN ("true_us") },
16298 };
16299
16300 static void
16301 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16302 {
16303   unsigned int cmp_type;
16304
16305   FETCH_DATA (the_info, codep + 1);
16306   cmp_type = *codep++ & 0xff;
16307   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16308     {
16309       char suffix [3];
16310       char *p = mnemonicendp - 2;
16311       suffix[0] = p[0];
16312       suffix[1] = p[1];
16313       suffix[2] = '\0';
16314       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16315       mnemonicendp += vex_cmp_op[cmp_type].len;
16316     }
16317   else
16318     {
16319       /* We have a reserved extension byte.  Output it directly.  */
16320       scratchbuf[0] = '$';
16321       print_operand_value (scratchbuf + 1, 1, cmp_type);
16322       oappend_maybe_intel (scratchbuf);
16323       scratchbuf[0] = '\0';
16324     }
16325 }
16326
16327 static void
16328 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16329              int sizeflag ATTRIBUTE_UNUSED)
16330 {
16331   unsigned int cmp_type;
16332
16333   if (!vex.evex)
16334     abort ();
16335
16336   FETCH_DATA (the_info, codep + 1);
16337   cmp_type = *codep++ & 0xff;
16338   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16339      If it's the case, print suffix, otherwise - print the immediate.  */
16340   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16341       && cmp_type != 3
16342       && cmp_type != 7)
16343     {
16344       char suffix [3];
16345       char *p = mnemonicendp - 2;
16346
16347       /* vpcmp* can have both one- and two-lettered suffix.  */
16348       if (p[0] == 'p')
16349         {
16350           p++;
16351           suffix[0] = p[0];
16352           suffix[1] = '\0';
16353         }
16354       else
16355         {
16356           suffix[0] = p[0];
16357           suffix[1] = p[1];
16358           suffix[2] = '\0';
16359         }
16360
16361       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16362       mnemonicendp += simd_cmp_op[cmp_type].len;
16363     }
16364   else
16365     {
16366       /* We have a reserved extension byte.  Output it directly.  */
16367       scratchbuf[0] = '$';
16368       print_operand_value (scratchbuf + 1, 1, cmp_type);
16369       oappend_maybe_intel (scratchbuf);
16370       scratchbuf[0] = '\0';
16371     }
16372 }
16373
16374 static const struct op xop_cmp_op[] =
16375 {
16376   { STRING_COMMA_LEN ("lt") },
16377   { STRING_COMMA_LEN ("le") },
16378   { STRING_COMMA_LEN ("gt") },
16379   { STRING_COMMA_LEN ("ge") },
16380   { STRING_COMMA_LEN ("eq") },
16381   { STRING_COMMA_LEN ("neq") },
16382   { STRING_COMMA_LEN ("false") },
16383   { STRING_COMMA_LEN ("true") }
16384 };
16385
16386 static void
16387 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16388              int sizeflag ATTRIBUTE_UNUSED)
16389 {
16390   unsigned int cmp_type;
16391
16392   FETCH_DATA (the_info, codep + 1);
16393   cmp_type = *codep++ & 0xff;
16394   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16395     {
16396       char suffix[3];
16397       char *p = mnemonicendp - 2;
16398
16399       /* vpcom* can have both one- and two-lettered suffix.  */
16400       if (p[0] == 'm')
16401         {
16402           p++;
16403           suffix[0] = p[0];
16404           suffix[1] = '\0';
16405         }
16406       else
16407         {
16408           suffix[0] = p[0];
16409           suffix[1] = p[1];
16410           suffix[2] = '\0';
16411         }
16412
16413       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16414       mnemonicendp += xop_cmp_op[cmp_type].len;
16415     }
16416   else
16417     {
16418       /* We have a reserved extension byte.  Output it directly.  */
16419       scratchbuf[0] = '$';
16420       print_operand_value (scratchbuf + 1, 1, cmp_type);
16421       oappend_maybe_intel (scratchbuf);
16422       scratchbuf[0] = '\0';
16423     }
16424 }
16425
16426 static const struct op pclmul_op[] =
16427 {
16428   { STRING_COMMA_LEN ("lql") },
16429   { STRING_COMMA_LEN ("hql") },
16430   { STRING_COMMA_LEN ("lqh") },
16431   { STRING_COMMA_LEN ("hqh") }
16432 };
16433
16434 static void
16435 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16436               int sizeflag ATTRIBUTE_UNUSED)
16437 {
16438   unsigned int pclmul_type;
16439
16440   FETCH_DATA (the_info, codep + 1);
16441   pclmul_type = *codep++ & 0xff;
16442   switch (pclmul_type)
16443     {
16444     case 0x10:
16445       pclmul_type = 2;
16446       break;
16447     case 0x11:
16448       pclmul_type = 3;
16449       break;
16450     default:
16451       break;
16452     }
16453   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16454     {
16455       char suffix [4];
16456       char *p = mnemonicendp - 3;
16457       suffix[0] = p[0];
16458       suffix[1] = p[1];
16459       suffix[2] = p[2];
16460       suffix[3] = '\0';
16461       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16462       mnemonicendp += pclmul_op[pclmul_type].len;
16463     }
16464   else
16465     {
16466       /* We have a reserved extension byte.  Output it directly.  */
16467       scratchbuf[0] = '$';
16468       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16469       oappend_maybe_intel (scratchbuf);
16470       scratchbuf[0] = '\0';
16471     }
16472 }
16473
16474 static void
16475 MOVBE_Fixup (int bytemode, int sizeflag)
16476 {
16477   /* Add proper suffix to "movbe".  */
16478   char *p = mnemonicendp;
16479
16480   switch (bytemode)
16481     {
16482     case v_mode:
16483       if (intel_syntax)
16484         goto skip;
16485
16486       USED_REX (REX_W);
16487       if (sizeflag & SUFFIX_ALWAYS)
16488         {
16489           if (rex & REX_W)
16490             *p++ = 'q';
16491           else
16492             {
16493               if (sizeflag & DFLAG)
16494                 *p++ = 'l';
16495               else
16496                 *p++ = 'w';
16497               used_prefixes |= (prefixes & PREFIX_DATA);
16498             }
16499         }
16500       break;
16501     default:
16502       oappend (INTERNAL_DISASSEMBLER_ERROR);
16503       break;
16504     }
16505   mnemonicendp = p;
16506   *p = '\0';
16507
16508 skip:
16509   OP_M (bytemode, sizeflag);
16510 }
16511
16512 static void
16513 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16514 {
16515   int reg;
16516   const char **names;
16517
16518   /* Skip mod/rm byte.  */
16519   MODRM_CHECK;
16520   codep++;
16521
16522   if (rex & REX_W)
16523     names = names64;
16524   else
16525     names = names32;
16526
16527   reg = modrm.rm;
16528   USED_REX (REX_B);
16529   if (rex & REX_B)
16530     reg += 8;
16531
16532   oappend (names[reg]);
16533 }
16534
16535 static void
16536 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16537 {
16538   const char **names;
16539   unsigned int reg = vex.register_specifier;
16540   vex.register_specifier = 0;
16541
16542   if (rex & REX_W)
16543     names = names64;
16544   else
16545     names = names32;
16546
16547   if (address_mode != mode_64bit)
16548     reg &= 7;
16549   oappend (names[reg]);
16550 }
16551
16552 static void
16553 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16554 {
16555   if (!vex.evex
16556       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16557     abort ();
16558
16559   USED_REX (REX_R);
16560   if ((rex & REX_R) != 0 || !vex.r)
16561     {
16562       BadOp ();
16563       return;
16564     }
16565
16566   oappend (names_mask [modrm.reg]);
16567 }
16568
16569 static void
16570 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16571 {
16572   if (!vex.evex
16573       || (bytemode != evex_rounding_mode
16574           && bytemode != evex_rounding_64_mode
16575           && bytemode != evex_sae_mode))
16576     abort ();
16577   if (modrm.mod == 3 && vex.b)
16578     switch (bytemode)
16579       {
16580       case evex_rounding_64_mode:
16581         if (address_mode != mode_64bit)
16582           {
16583             oappend ("(bad)");
16584             break;
16585           }
16586         /* Fall through.  */
16587       case evex_rounding_mode:
16588         oappend (names_rounding[vex.ll]);
16589         break;
16590       case evex_sae_mode:
16591         oappend ("{sae}");
16592         break;
16593       default:
16594         break;
16595       }
16596 }