opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_1,
 849   MOD_0F38F8_PREFIX_2,
 850   MOD_0F38F8_PREFIX_3,
 851   MOD_0F38F9_PREFIX_0,
 852   MOD_62_32BIT,
 853   MOD_C4_32BIT,
 854   MOD_C5_32BIT,
 855   MOD_VEX_0F12_PREFIX_0,
 856   MOD_VEX_0F13,
 857   MOD_VEX_0F16_PREFIX_0,
 858   MOD_VEX_0F17,
 859   MOD_VEX_0F2B,
 860   MOD_VEX_W_0_0F41_P_0_LEN_1,
 861   MOD_VEX_W_1_0F41_P_0_LEN_1,
 862   MOD_VEX_W_0_0F41_P_2_LEN_1,
 863   MOD_VEX_W_1_0F41_P_2_LEN_1,
 864   MOD_VEX_W_0_0F42_P_0_LEN_1,
 865   MOD_VEX_W_1_0F42_P_0_LEN_1,
 866   MOD_VEX_W_0_0F42_P_2_LEN_1,
 867   MOD_VEX_W_1_0F42_P_2_LEN_1,
 868   MOD_VEX_W_0_0F44_P_0_LEN_1,
 869   MOD_VEX_W_1_0F44_P_0_LEN_1,
 870   MOD_VEX_W_0_0F44_P_2_LEN_1,
 871   MOD_VEX_W_1_0F44_P_2_LEN_1,
 872   MOD_VEX_W_0_0F45_P_0_LEN_1,
 873   MOD_VEX_W_1_0F45_P_0_LEN_1,
 874   MOD_VEX_W_0_0F45_P_2_LEN_1,
 875   MOD_VEX_W_1_0F45_P_2_LEN_1,
 876   MOD_VEX_W_0_0F46_P_0_LEN_1,
 877   MOD_VEX_W_1_0F46_P_0_LEN_1,
 878   MOD_VEX_W_0_0F46_P_2_LEN_1,
 879   MOD_VEX_W_1_0F46_P_2_LEN_1,
 880   MOD_VEX_W_0_0F47_P_0_LEN_1,
 881   MOD_VEX_W_1_0F47_P_0_LEN_1,
 882   MOD_VEX_W_0_0F47_P_2_LEN_1,
 883   MOD_VEX_W_1_0F47_P_2_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 886   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 887   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 889   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 890   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 891   MOD_VEX_0F50,
 892   MOD_VEX_0F71_REG_2,
 893   MOD_VEX_0F71_REG_4,
 894   MOD_VEX_0F71_REG_6,
 895   MOD_VEX_0F72_REG_2,
 896   MOD_VEX_0F72_REG_4,
 897   MOD_VEX_0F72_REG_6,
 898   MOD_VEX_0F73_REG_2,
 899   MOD_VEX_0F73_REG_3,
 900   MOD_VEX_0F73_REG_6,
 901   MOD_VEX_0F73_REG_7,
 902   MOD_VEX_W_0_0F91_P_0_LEN_0,
 903   MOD_VEX_W_1_0F91_P_0_LEN_0,
 904   MOD_VEX_W_0_0F91_P_2_LEN_0,
 905   MOD_VEX_W_1_0F91_P_2_LEN_0,
 906   MOD_VEX_W_0_0F92_P_0_LEN_0,
 907   MOD_VEX_W_0_0F92_P_2_LEN_0,
 908   MOD_VEX_0F92_P_3_LEN_0,
 909   MOD_VEX_W_0_0F93_P_0_LEN_0,
 910   MOD_VEX_W_0_0F93_P_2_LEN_0,
 911   MOD_VEX_0F93_P_3_LEN_0,
 912   MOD_VEX_W_0_0F98_P_0_LEN_0,
 913   MOD_VEX_W_1_0F98_P_0_LEN_0,
 914   MOD_VEX_W_0_0F98_P_2_LEN_0,
 915   MOD_VEX_W_1_0F98_P_2_LEN_0,
 916   MOD_VEX_W_0_0F99_P_0_LEN_0,
 917   MOD_VEX_W_1_0F99_P_0_LEN_0,
 918   MOD_VEX_W_0_0F99_P_2_LEN_0,
 919   MOD_VEX_W_1_0F99_P_2_LEN_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7_PREFIX_2,
 923   MOD_VEX_0FE7_PREFIX_2,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A_PREFIX_2,
 926   MOD_VEX_0F382A_PREFIX_2,
 927   MOD_VEX_0F382C_PREFIX_2,
 928   MOD_VEX_0F382D_PREFIX_2,
 929   MOD_VEX_0F382E_PREFIX_2,
 930   MOD_VEX_0F382F_PREFIX_2,
 931   MOD_VEX_0F385A_PREFIX_2,
 932   MOD_VEX_0F388C_PREFIX_2,
 933   MOD_VEX_0F388E_PREFIX_2,
 934   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 940   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 941   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 942
 943   MOD_EVEX_0F10_PREFIX_1,
 944   MOD_EVEX_0F10_PREFIX_3,
 945   MOD_EVEX_0F11_PREFIX_1,
 946   MOD_EVEX_0F11_PREFIX_3,
 947   MOD_EVEX_0F12_PREFIX_0,
 948   MOD_EVEX_0F16_PREFIX_0,
 949   MOD_EVEX_0F38C6_REG_1,
 950   MOD_EVEX_0F38C6_REG_2,
 951   MOD_EVEX_0F38C6_REG_5,
 952   MOD_EVEX_0F38C6_REG_6,
 953   MOD_EVEX_0F38C7_REG_1,
 954   MOD_EVEX_0F38C7_REG_2,
 955   MOD_EVEX_0F38C7_REG_5,
 956   MOD_EVEX_0F38C7_REG_6
 957 };
 958
 959 enum
 960 {
 961   RM_C6_REG_7 = 0,
 962   RM_C7_REG_7,
 963   RM_0F01_REG_0,
 964   RM_0F01_REG_1,
 965   RM_0F01_REG_2,
 966   RM_0F01_REG_3,
 967   RM_0F01_REG_5,
 968   RM_0F01_REG_7,
 969   RM_0F1E_MOD_3_REG_7,
 970   RM_0FAE_REG_6,
 971   RM_0FAE_REG_7
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_MOD_0_0F01_REG_5,
 978   PREFIX_MOD_3_0F01_REG_5_RM_0,
 979   PREFIX_MOD_3_0F01_REG_5_RM_2,
 980   PREFIX_0F09,
 981   PREFIX_0F10,
 982   PREFIX_0F11,
 983   PREFIX_0F12,
 984   PREFIX_0F16,
 985   PREFIX_0F1A,
 986   PREFIX_0F1B,
 987   PREFIX_0F1C,
 988   PREFIX_0F1E,
 989   PREFIX_0F2A,
 990   PREFIX_0F2B,
 991   PREFIX_0F2C,
 992   PREFIX_0F2D,
 993   PREFIX_0F2E,
 994   PREFIX_0F2F,
 995   PREFIX_0F51,
 996   PREFIX_0F52,
 997   PREFIX_0F53,
 998   PREFIX_0F58,
 999   PREFIX_0F59,
1000   PREFIX_0F5A,
1001   PREFIX_0F5B,
1002   PREFIX_0F5C,
1003   PREFIX_0F5D,
1004   PREFIX_0F5E,
1005   PREFIX_0F5F,
1006   PREFIX_0F60,
1007   PREFIX_0F61,
1008   PREFIX_0F62,
1009   PREFIX_0F6C,
1010   PREFIX_0F6D,
1011   PREFIX_0F6F,
1012   PREFIX_0F70,
1013   PREFIX_0F73_REG_3,
1014   PREFIX_0F73_REG_7,
1015   PREFIX_0F78,
1016   PREFIX_0F79,
1017   PREFIX_0F7C,
1018   PREFIX_0F7D,
1019   PREFIX_0F7E,
1020   PREFIX_0F7F,
1021   PREFIX_0FAE_REG_0,
1022   PREFIX_0FAE_REG_1,
1023   PREFIX_0FAE_REG_2,
1024   PREFIX_0FAE_REG_3,
1025   PREFIX_MOD_0_0FAE_REG_4,
1026   PREFIX_MOD_3_0FAE_REG_4,
1027   PREFIX_MOD_0_0FAE_REG_5,
1028   PREFIX_MOD_3_0FAE_REG_5,
1029   PREFIX_MOD_0_0FAE_REG_6,
1030   PREFIX_MOD_1_0FAE_REG_6,
1031   PREFIX_0FAE_REG_7,
1032   PREFIX_0FB8,
1033   PREFIX_0FBC,
1034   PREFIX_0FBD,
1035   PREFIX_0FC2,
1036   PREFIX_MOD_0_0FC3,
1037   PREFIX_MOD_0_0FC7_REG_6,
1038   PREFIX_MOD_3_0FC7_REG_6,
1039   PREFIX_MOD_3_0FC7_REG_7,
1040   PREFIX_0FD0,
1041   PREFIX_0FD6,
1042   PREFIX_0FE6,
1043   PREFIX_0FE7,
1044   PREFIX_0FF0,
1045   PREFIX_0FF7,
1046   PREFIX_0F3810,
1047   PREFIX_0F3814,
1048   PREFIX_0F3815,
1049   PREFIX_0F3817,
1050   PREFIX_0F3820,
1051   PREFIX_0F3821,
1052   PREFIX_0F3822,
1053   PREFIX_0F3823,
1054   PREFIX_0F3824,
1055   PREFIX_0F3825,
1056   PREFIX_0F3828,
1057   PREFIX_0F3829,
1058   PREFIX_0F382A,
1059   PREFIX_0F382B,
1060   PREFIX_0F3830,
1061   PREFIX_0F3831,
1062   PREFIX_0F3832,
1063   PREFIX_0F3833,
1064   PREFIX_0F3834,
1065   PREFIX_0F3835,
1066   PREFIX_0F3837,
1067   PREFIX_0F3838,
1068   PREFIX_0F3839,
1069   PREFIX_0F383A,
1070   PREFIX_0F383B,
1071   PREFIX_0F383C,
1072   PREFIX_0F383D,
1073   PREFIX_0F383E,
1074   PREFIX_0F383F,
1075   PREFIX_0F3840,
1076   PREFIX_0F3841,
1077   PREFIX_0F3880,
1078   PREFIX_0F3881,
1079   PREFIX_0F3882,
1080   PREFIX_0F38C8,
1081   PREFIX_0F38C9,
1082   PREFIX_0F38CA,
1083   PREFIX_0F38CB,
1084   PREFIX_0F38CC,
1085   PREFIX_0F38CD,
1086   PREFIX_0F38CF,
1087   PREFIX_0F38DB,
1088   PREFIX_0F38DC,
1089   PREFIX_0F38DD,
1090   PREFIX_0F38DE,
1091   PREFIX_0F38DF,
1092   PREFIX_0F38F0,
1093   PREFIX_0F38F1,
1094   PREFIX_0F38F5,
1095   PREFIX_0F38F6,
1096   PREFIX_0F38F8,
1097   PREFIX_0F38F9,
1098   PREFIX_0F3A08,
1099   PREFIX_0F3A09,
1100   PREFIX_0F3A0A,
1101   PREFIX_0F3A0B,
1102   PREFIX_0F3A0C,
1103   PREFIX_0F3A0D,
1104   PREFIX_0F3A0E,
1105   PREFIX_0F3A14,
1106   PREFIX_0F3A15,
1107   PREFIX_0F3A16,
1108   PREFIX_0F3A17,
1109   PREFIX_0F3A20,
1110   PREFIX_0F3A21,
1111   PREFIX_0F3A22,
1112   PREFIX_0F3A40,
1113   PREFIX_0F3A41,
1114   PREFIX_0F3A42,
1115   PREFIX_0F3A44,
1116   PREFIX_0F3A60,
1117   PREFIX_0F3A61,
1118   PREFIX_0F3A62,
1119   PREFIX_0F3A63,
1120   PREFIX_0F3ACC,
1121   PREFIX_0F3ACE,
1122   PREFIX_0F3ACF,
1123   PREFIX_0F3ADF,
1124   PREFIX_VEX_0F10,
1125   PREFIX_VEX_0F11,
1126   PREFIX_VEX_0F12,
1127   PREFIX_VEX_0F16,
1128   PREFIX_VEX_0F2A,
1129   PREFIX_VEX_0F2C,
1130   PREFIX_VEX_0F2D,
1131   PREFIX_VEX_0F2E,
1132   PREFIX_VEX_0F2F,
1133   PREFIX_VEX_0F41,
1134   PREFIX_VEX_0F42,
1135   PREFIX_VEX_0F44,
1136   PREFIX_VEX_0F45,
1137   PREFIX_VEX_0F46,
1138   PREFIX_VEX_0F47,
1139   PREFIX_VEX_0F4A,
1140   PREFIX_VEX_0F4B,
1141   PREFIX_VEX_0F51,
1142   PREFIX_VEX_0F52,
1143   PREFIX_VEX_0F53,
1144   PREFIX_VEX_0F58,
1145   PREFIX_VEX_0F59,
1146   PREFIX_VEX_0F5A,
1147   PREFIX_VEX_0F5B,
1148   PREFIX_VEX_0F5C,
1149   PREFIX_VEX_0F5D,
1150   PREFIX_VEX_0F5E,
1151   PREFIX_VEX_0F5F,
1152   PREFIX_VEX_0F60,
1153   PREFIX_VEX_0F61,
1154   PREFIX_VEX_0F62,
1155   PREFIX_VEX_0F63,
1156   PREFIX_VEX_0F64,
1157   PREFIX_VEX_0F65,
1158   PREFIX_VEX_0F66,
1159   PREFIX_VEX_0F67,
1160   PREFIX_VEX_0F68,
1161   PREFIX_VEX_0F69,
1162   PREFIX_VEX_0F6A,
1163   PREFIX_VEX_0F6B,
1164   PREFIX_VEX_0F6C,
1165   PREFIX_VEX_0F6D,
1166   PREFIX_VEX_0F6E,
1167   PREFIX_VEX_0F6F,
1168   PREFIX_VEX_0F70,
1169   PREFIX_VEX_0F71_REG_2,
1170   PREFIX_VEX_0F71_REG_4,
1171   PREFIX_VEX_0F71_REG_6,
1172   PREFIX_VEX_0F72_REG_2,
1173   PREFIX_VEX_0F72_REG_4,
1174   PREFIX_VEX_0F72_REG_6,
1175   PREFIX_VEX_0F73_REG_2,
1176   PREFIX_VEX_0F73_REG_3,
1177   PREFIX_VEX_0F73_REG_6,
1178   PREFIX_VEX_0F73_REG_7,
1179   PREFIX_VEX_0F74,
1180   PREFIX_VEX_0F75,
1181   PREFIX_VEX_0F76,
1182   PREFIX_VEX_0F77,
1183   PREFIX_VEX_0F7C,
1184   PREFIX_VEX_0F7D,
1185   PREFIX_VEX_0F7E,
1186   PREFIX_VEX_0F7F,
1187   PREFIX_VEX_0F90,
1188   PREFIX_VEX_0F91,
1189   PREFIX_VEX_0F92,
1190   PREFIX_VEX_0F93,
1191   PREFIX_VEX_0F98,
1192   PREFIX_VEX_0F99,
1193   PREFIX_VEX_0FC2,
1194   PREFIX_VEX_0FC4,
1195   PREFIX_VEX_0FC5,
1196   PREFIX_VEX_0FD0,
1197   PREFIX_VEX_0FD1,
1198   PREFIX_VEX_0FD2,
1199   PREFIX_VEX_0FD3,
1200   PREFIX_VEX_0FD4,
1201   PREFIX_VEX_0FD5,
1202   PREFIX_VEX_0FD6,
1203   PREFIX_VEX_0FD7,
1204   PREFIX_VEX_0FD8,
1205   PREFIX_VEX_0FD9,
1206   PREFIX_VEX_0FDA,
1207   PREFIX_VEX_0FDB,
1208   PREFIX_VEX_0FDC,
1209   PREFIX_VEX_0FDD,
1210   PREFIX_VEX_0FDE,
1211   PREFIX_VEX_0FDF,
1212   PREFIX_VEX_0FE0,
1213   PREFIX_VEX_0FE1,
1214   PREFIX_VEX_0FE2,
1215   PREFIX_VEX_0FE3,
1216   PREFIX_VEX_0FE4,
1217   PREFIX_VEX_0FE5,
1218   PREFIX_VEX_0FE6,
1219   PREFIX_VEX_0FE7,
1220   PREFIX_VEX_0FE8,
1221   PREFIX_VEX_0FE9,
1222   PREFIX_VEX_0FEA,
1223   PREFIX_VEX_0FEB,
1224   PREFIX_VEX_0FEC,
1225   PREFIX_VEX_0FED,
1226   PREFIX_VEX_0FEE,
1227   PREFIX_VEX_0FEF,
1228   PREFIX_VEX_0FF0,
1229   PREFIX_VEX_0FF1,
1230   PREFIX_VEX_0FF2,
1231   PREFIX_VEX_0FF3,
1232   PREFIX_VEX_0FF4,
1233   PREFIX_VEX_0FF5,
1234   PREFIX_VEX_0FF6,
1235   PREFIX_VEX_0FF7,
1236   PREFIX_VEX_0FF8,
1237   PREFIX_VEX_0FF9,
1238   PREFIX_VEX_0FFA,
1239   PREFIX_VEX_0FFB,
1240   PREFIX_VEX_0FFC,
1241   PREFIX_VEX_0FFD,
1242   PREFIX_VEX_0FFE,
1243   PREFIX_VEX_0F3800,
1244   PREFIX_VEX_0F3801,
1245   PREFIX_VEX_0F3802,
1246   PREFIX_VEX_0F3803,
1247   PREFIX_VEX_0F3804,
1248   PREFIX_VEX_0F3805,
1249   PREFIX_VEX_0F3806,
1250   PREFIX_VEX_0F3807,
1251   PREFIX_VEX_0F3808,
1252   PREFIX_VEX_0F3809,
1253   PREFIX_VEX_0F380A,
1254   PREFIX_VEX_0F380B,
1255   PREFIX_VEX_0F380C,
1256   PREFIX_VEX_0F380D,
1257   PREFIX_VEX_0F380E,
1258   PREFIX_VEX_0F380F,
1259   PREFIX_VEX_0F3813,
1260   PREFIX_VEX_0F3816,
1261   PREFIX_VEX_0F3817,
1262   PREFIX_VEX_0F3818,
1263   PREFIX_VEX_0F3819,
1264   PREFIX_VEX_0F381A,
1265   PREFIX_VEX_0F381C,
1266   PREFIX_VEX_0F381D,
1267   PREFIX_VEX_0F381E,
1268   PREFIX_VEX_0F3820,
1269   PREFIX_VEX_0F3821,
1270   PREFIX_VEX_0F3822,
1271   PREFIX_VEX_0F3823,
1272   PREFIX_VEX_0F3824,
1273   PREFIX_VEX_0F3825,
1274   PREFIX_VEX_0F3828,
1275   PREFIX_VEX_0F3829,
1276   PREFIX_VEX_0F382A,
1277   PREFIX_VEX_0F382B,
1278   PREFIX_VEX_0F382C,
1279   PREFIX_VEX_0F382D,
1280   PREFIX_VEX_0F382E,
1281   PREFIX_VEX_0F382F,
1282   PREFIX_VEX_0F3830,
1283   PREFIX_VEX_0F3831,
1284   PREFIX_VEX_0F3832,
1285   PREFIX_VEX_0F3833,
1286   PREFIX_VEX_0F3834,
1287   PREFIX_VEX_0F3835,
1288   PREFIX_VEX_0F3836,
1289   PREFIX_VEX_0F3837,
1290   PREFIX_VEX_0F3838,
1291   PREFIX_VEX_0F3839,
1292   PREFIX_VEX_0F383A,
1293   PREFIX_VEX_0F383B,
1294   PREFIX_VEX_0F383C,
1295   PREFIX_VEX_0F383D,
1296   PREFIX_VEX_0F383E,
1297   PREFIX_VEX_0F383F,
1298   PREFIX_VEX_0F3840,
1299   PREFIX_VEX_0F3841,
1300   PREFIX_VEX_0F3845,
1301   PREFIX_VEX_0F3846,
1302   PREFIX_VEX_0F3847,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F3878,
1307   PREFIX_VEX_0F3879,
1308   PREFIX_VEX_0F388C,
1309   PREFIX_VEX_0F388E,
1310   PREFIX_VEX_0F3890,
1311   PREFIX_VEX_0F3891,
1312   PREFIX_VEX_0F3892,
1313   PREFIX_VEX_0F3893,
1314   PREFIX_VEX_0F3896,
1315   PREFIX_VEX_0F3897,
1316   PREFIX_VEX_0F3898,
1317   PREFIX_VEX_0F3899,
1318   PREFIX_VEX_0F389A,
1319   PREFIX_VEX_0F389B,
1320   PREFIX_VEX_0F389C,
1321   PREFIX_VEX_0F389D,
1322   PREFIX_VEX_0F389E,
1323   PREFIX_VEX_0F389F,
1324   PREFIX_VEX_0F38A6,
1325   PREFIX_VEX_0F38A7,
1326   PREFIX_VEX_0F38A8,
1327   PREFIX_VEX_0F38A9,
1328   PREFIX_VEX_0F38AA,
1329   PREFIX_VEX_0F38AB,
1330   PREFIX_VEX_0F38AC,
1331   PREFIX_VEX_0F38AD,
1332   PREFIX_VEX_0F38AE,
1333   PREFIX_VEX_0F38AF,
1334   PREFIX_VEX_0F38B6,
1335   PREFIX_VEX_0F38B7,
1336   PREFIX_VEX_0F38B8,
1337   PREFIX_VEX_0F38B9,
1338   PREFIX_VEX_0F38BA,
1339   PREFIX_VEX_0F38BB,
1340   PREFIX_VEX_0F38BC,
1341   PREFIX_VEX_0F38BD,
1342   PREFIX_VEX_0F38BE,
1343   PREFIX_VEX_0F38BF,
1344   PREFIX_VEX_0F38CF,
1345   PREFIX_VEX_0F38DB,
1346   PREFIX_VEX_0F38DC,
1347   PREFIX_VEX_0F38DD,
1348   PREFIX_VEX_0F38DE,
1349   PREFIX_VEX_0F38DF,
1350   PREFIX_VEX_0F38F2,
1351   PREFIX_VEX_0F38F3_REG_1,
1352   PREFIX_VEX_0F38F3_REG_2,
1353   PREFIX_VEX_0F38F3_REG_3,
1354   PREFIX_VEX_0F38F5,
1355   PREFIX_VEX_0F38F6,
1356   PREFIX_VEX_0F38F7,
1357   PREFIX_VEX_0F3A00,
1358   PREFIX_VEX_0F3A01,
1359   PREFIX_VEX_0F3A02,
1360   PREFIX_VEX_0F3A04,
1361   PREFIX_VEX_0F3A05,
1362   PREFIX_VEX_0F3A06,
1363   PREFIX_VEX_0F3A08,
1364   PREFIX_VEX_0F3A09,
1365   PREFIX_VEX_0F3A0A,
1366   PREFIX_VEX_0F3A0B,
1367   PREFIX_VEX_0F3A0C,
1368   PREFIX_VEX_0F3A0D,
1369   PREFIX_VEX_0F3A0E,
1370   PREFIX_VEX_0F3A0F,
1371   PREFIX_VEX_0F3A14,
1372   PREFIX_VEX_0F3A15,
1373   PREFIX_VEX_0F3A16,
1374   PREFIX_VEX_0F3A17,
1375   PREFIX_VEX_0F3A18,
1376   PREFIX_VEX_0F3A19,
1377   PREFIX_VEX_0F3A1D,
1378   PREFIX_VEX_0F3A20,
1379   PREFIX_VEX_0F3A21,
1380   PREFIX_VEX_0F3A22,
1381   PREFIX_VEX_0F3A30,
1382   PREFIX_VEX_0F3A31,
1383   PREFIX_VEX_0F3A32,
1384   PREFIX_VEX_0F3A33,
1385   PREFIX_VEX_0F3A38,
1386   PREFIX_VEX_0F3A39,
1387   PREFIX_VEX_0F3A40,
1388   PREFIX_VEX_0F3A41,
1389   PREFIX_VEX_0F3A42,
1390   PREFIX_VEX_0F3A44,
1391   PREFIX_VEX_0F3A46,
1392   PREFIX_VEX_0F3A48,
1393   PREFIX_VEX_0F3A49,
1394   PREFIX_VEX_0F3A4A,
1395   PREFIX_VEX_0F3A4B,
1396   PREFIX_VEX_0F3A4C,
1397   PREFIX_VEX_0F3A5C,
1398   PREFIX_VEX_0F3A5D,
1399   PREFIX_VEX_0F3A5E,
1400   PREFIX_VEX_0F3A5F,
1401   PREFIX_VEX_0F3A60,
1402   PREFIX_VEX_0F3A61,
1403   PREFIX_VEX_0F3A62,
1404   PREFIX_VEX_0F3A63,
1405   PREFIX_VEX_0F3A68,
1406   PREFIX_VEX_0F3A69,
1407   PREFIX_VEX_0F3A6A,
1408   PREFIX_VEX_0F3A6B,
1409   PREFIX_VEX_0F3A6C,
1410   PREFIX_VEX_0F3A6D,
1411   PREFIX_VEX_0F3A6E,
1412   PREFIX_VEX_0F3A6F,
1413   PREFIX_VEX_0F3A78,
1414   PREFIX_VEX_0F3A79,
1415   PREFIX_VEX_0F3A7A,
1416   PREFIX_VEX_0F3A7B,
1417   PREFIX_VEX_0F3A7C,
1418   PREFIX_VEX_0F3A7D,
1419   PREFIX_VEX_0F3A7E,
1420   PREFIX_VEX_0F3A7F,
1421   PREFIX_VEX_0F3ACE,
1422   PREFIX_VEX_0F3ACF,
1423   PREFIX_VEX_0F3ADF,
1424   PREFIX_VEX_0F3AF0,
1425
1426   PREFIX_EVEX_0F10,
1427   PREFIX_EVEX_0F11,
1428   PREFIX_EVEX_0F12,
1429   PREFIX_EVEX_0F13,
1430   PREFIX_EVEX_0F14,
1431   PREFIX_EVEX_0F15,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F17,
1434   PREFIX_EVEX_0F28,
1435   PREFIX_EVEX_0F29,
1436   PREFIX_EVEX_0F2A,
1437   PREFIX_EVEX_0F2B,
1438   PREFIX_EVEX_0F2C,
1439   PREFIX_EVEX_0F2D,
1440   PREFIX_EVEX_0F2E,
1441   PREFIX_EVEX_0F2F,
1442   PREFIX_EVEX_0F51,
1443   PREFIX_EVEX_0F54,
1444   PREFIX_EVEX_0F55,
1445   PREFIX_EVEX_0F56,
1446   PREFIX_EVEX_0F57,
1447   PREFIX_EVEX_0F58,
1448   PREFIX_EVEX_0F59,
1449   PREFIX_EVEX_0F5A,
1450   PREFIX_EVEX_0F5B,
1451   PREFIX_EVEX_0F5C,
1452   PREFIX_EVEX_0F5D,
1453   PREFIX_EVEX_0F5E,
1454   PREFIX_EVEX_0F5F,
1455   PREFIX_EVEX_0F60,
1456   PREFIX_EVEX_0F61,
1457   PREFIX_EVEX_0F62,
1458   PREFIX_EVEX_0F63,
1459   PREFIX_EVEX_0F64,
1460   PREFIX_EVEX_0F65,
1461   PREFIX_EVEX_0F66,
1462   PREFIX_EVEX_0F67,
1463   PREFIX_EVEX_0F68,
1464   PREFIX_EVEX_0F69,
1465   PREFIX_EVEX_0F6A,
1466   PREFIX_EVEX_0F6B,
1467   PREFIX_EVEX_0F6C,
1468   PREFIX_EVEX_0F6D,
1469   PREFIX_EVEX_0F6E,
1470   PREFIX_EVEX_0F6F,
1471   PREFIX_EVEX_0F70,
1472   PREFIX_EVEX_0F71_REG_2,
1473   PREFIX_EVEX_0F71_REG_4,
1474   PREFIX_EVEX_0F71_REG_6,
1475   PREFIX_EVEX_0F72_REG_0,
1476   PREFIX_EVEX_0F72_REG_1,
1477   PREFIX_EVEX_0F72_REG_2,
1478   PREFIX_EVEX_0F72_REG_4,
1479   PREFIX_EVEX_0F72_REG_6,
1480   PREFIX_EVEX_0F73_REG_2,
1481   PREFIX_EVEX_0F73_REG_3,
1482   PREFIX_EVEX_0F73_REG_6,
1483   PREFIX_EVEX_0F73_REG_7,
1484   PREFIX_EVEX_0F74,
1485   PREFIX_EVEX_0F75,
1486   PREFIX_EVEX_0F76,
1487   PREFIX_EVEX_0F78,
1488   PREFIX_EVEX_0F79,
1489   PREFIX_EVEX_0F7A,
1490   PREFIX_EVEX_0F7B,
1491   PREFIX_EVEX_0F7E,
1492   PREFIX_EVEX_0F7F,
1493   PREFIX_EVEX_0FC2,
1494   PREFIX_EVEX_0FC4,
1495   PREFIX_EVEX_0FC5,
1496   PREFIX_EVEX_0FC6,
1497   PREFIX_EVEX_0FD1,
1498   PREFIX_EVEX_0FD2,
1499   PREFIX_EVEX_0FD3,
1500   PREFIX_EVEX_0FD4,
1501   PREFIX_EVEX_0FD5,
1502   PREFIX_EVEX_0FD6,
1503   PREFIX_EVEX_0FD8,
1504   PREFIX_EVEX_0FD9,
1505   PREFIX_EVEX_0FDA,
1506   PREFIX_EVEX_0FDB,
1507   PREFIX_EVEX_0FDC,
1508   PREFIX_EVEX_0FDD,
1509   PREFIX_EVEX_0FDE,
1510   PREFIX_EVEX_0FDF,
1511   PREFIX_EVEX_0FE0,
1512   PREFIX_EVEX_0FE1,
1513   PREFIX_EVEX_0FE2,
1514   PREFIX_EVEX_0FE3,
1515   PREFIX_EVEX_0FE4,
1516   PREFIX_EVEX_0FE5,
1517   PREFIX_EVEX_0FE6,
1518   PREFIX_EVEX_0FE7,
1519   PREFIX_EVEX_0FE8,
1520   PREFIX_EVEX_0FE9,
1521   PREFIX_EVEX_0FEA,
1522   PREFIX_EVEX_0FEB,
1523   PREFIX_EVEX_0FEC,
1524   PREFIX_EVEX_0FED,
1525   PREFIX_EVEX_0FEE,
1526   PREFIX_EVEX_0FEF,
1527   PREFIX_EVEX_0FF1,
1528   PREFIX_EVEX_0FF2,
1529   PREFIX_EVEX_0FF3,
1530   PREFIX_EVEX_0FF4,
1531   PREFIX_EVEX_0FF5,
1532   PREFIX_EVEX_0FF6,
1533   PREFIX_EVEX_0FF8,
1534   PREFIX_EVEX_0FF9,
1535   PREFIX_EVEX_0FFA,
1536   PREFIX_EVEX_0FFB,
1537   PREFIX_EVEX_0FFC,
1538   PREFIX_EVEX_0FFD,
1539   PREFIX_EVEX_0FFE,
1540   PREFIX_EVEX_0F3800,
1541   PREFIX_EVEX_0F3804,
1542   PREFIX_EVEX_0F380B,
1543   PREFIX_EVEX_0F380C,
1544   PREFIX_EVEX_0F380D,
1545   PREFIX_EVEX_0F3810,
1546   PREFIX_EVEX_0F3811,
1547   PREFIX_EVEX_0F3812,
1548   PREFIX_EVEX_0F3813,
1549   PREFIX_EVEX_0F3814,
1550   PREFIX_EVEX_0F3815,
1551   PREFIX_EVEX_0F3816,
1552   PREFIX_EVEX_0F3818,
1553   PREFIX_EVEX_0F3819,
1554   PREFIX_EVEX_0F381A,
1555   PREFIX_EVEX_0F381B,
1556   PREFIX_EVEX_0F381C,
1557   PREFIX_EVEX_0F381D,
1558   PREFIX_EVEX_0F381E,
1559   PREFIX_EVEX_0F381F,
1560   PREFIX_EVEX_0F3820,
1561   PREFIX_EVEX_0F3821,
1562   PREFIX_EVEX_0F3822,
1563   PREFIX_EVEX_0F3823,
1564   PREFIX_EVEX_0F3824,
1565   PREFIX_EVEX_0F3825,
1566   PREFIX_EVEX_0F3826,
1567   PREFIX_EVEX_0F3827,
1568   PREFIX_EVEX_0F3828,
1569   PREFIX_EVEX_0F3829,
1570   PREFIX_EVEX_0F382A,
1571   PREFIX_EVEX_0F382B,
1572   PREFIX_EVEX_0F382C,
1573   PREFIX_EVEX_0F382D,
1574   PREFIX_EVEX_0F3830,
1575   PREFIX_EVEX_0F3831,
1576   PREFIX_EVEX_0F3832,
1577   PREFIX_EVEX_0F3833,
1578   PREFIX_EVEX_0F3834,
1579   PREFIX_EVEX_0F3835,
1580   PREFIX_EVEX_0F3836,
1581   PREFIX_EVEX_0F3837,
1582   PREFIX_EVEX_0F3838,
1583   PREFIX_EVEX_0F3839,
1584   PREFIX_EVEX_0F383A,
1585   PREFIX_EVEX_0F383B,
1586   PREFIX_EVEX_0F383C,
1587   PREFIX_EVEX_0F383D,
1588   PREFIX_EVEX_0F383E,
1589   PREFIX_EVEX_0F383F,
1590   PREFIX_EVEX_0F3840,
1591   PREFIX_EVEX_0F3842,
1592   PREFIX_EVEX_0F3843,
1593   PREFIX_EVEX_0F3844,
1594   PREFIX_EVEX_0F3845,
1595   PREFIX_EVEX_0F3846,
1596   PREFIX_EVEX_0F3847,
1597   PREFIX_EVEX_0F384C,
1598   PREFIX_EVEX_0F384D,
1599   PREFIX_EVEX_0F384E,
1600   PREFIX_EVEX_0F384F,
1601   PREFIX_EVEX_0F3850,
1602   PREFIX_EVEX_0F3851,
1603   PREFIX_EVEX_0F3852,
1604   PREFIX_EVEX_0F3853,
1605   PREFIX_EVEX_0F3854,
1606   PREFIX_EVEX_0F3855,
1607   PREFIX_EVEX_0F3858,
1608   PREFIX_EVEX_0F3859,
1609   PREFIX_EVEX_0F385A,
1610   PREFIX_EVEX_0F385B,
1611   PREFIX_EVEX_0F3862,
1612   PREFIX_EVEX_0F3863,
1613   PREFIX_EVEX_0F3864,
1614   PREFIX_EVEX_0F3865,
1615   PREFIX_EVEX_0F3866,
1616   PREFIX_EVEX_0F3868,
1617   PREFIX_EVEX_0F3870,
1618   PREFIX_EVEX_0F3871,
1619   PREFIX_EVEX_0F3872,
1620   PREFIX_EVEX_0F3873,
1621   PREFIX_EVEX_0F3875,
1622   PREFIX_EVEX_0F3876,
1623   PREFIX_EVEX_0F3877,
1624   PREFIX_EVEX_0F3878,
1625   PREFIX_EVEX_0F3879,
1626   PREFIX_EVEX_0F387A,
1627   PREFIX_EVEX_0F387B,
1628   PREFIX_EVEX_0F387C,
1629   PREFIX_EVEX_0F387D,
1630   PREFIX_EVEX_0F387E,
1631   PREFIX_EVEX_0F387F,
1632   PREFIX_EVEX_0F3883,
1633   PREFIX_EVEX_0F3888,
1634   PREFIX_EVEX_0F3889,
1635   PREFIX_EVEX_0F388A,
1636   PREFIX_EVEX_0F388B,
1637   PREFIX_EVEX_0F388D,
1638   PREFIX_EVEX_0F388F,
1639   PREFIX_EVEX_0F3890,
1640   PREFIX_EVEX_0F3891,
1641   PREFIX_EVEX_0F3892,
1642   PREFIX_EVEX_0F3893,
1643   PREFIX_EVEX_0F3896,
1644   PREFIX_EVEX_0F3897,
1645   PREFIX_EVEX_0F3898,
1646   PREFIX_EVEX_0F3899,
1647   PREFIX_EVEX_0F389A,
1648   PREFIX_EVEX_0F389B,
1649   PREFIX_EVEX_0F389C,
1650   PREFIX_EVEX_0F389D,
1651   PREFIX_EVEX_0F389E,
1652   PREFIX_EVEX_0F389F,
1653   PREFIX_EVEX_0F38A0,
1654   PREFIX_EVEX_0F38A1,
1655   PREFIX_EVEX_0F38A2,
1656   PREFIX_EVEX_0F38A3,
1657   PREFIX_EVEX_0F38A6,
1658   PREFIX_EVEX_0F38A7,
1659   PREFIX_EVEX_0F38A8,
1660   PREFIX_EVEX_0F38A9,
1661   PREFIX_EVEX_0F38AA,
1662   PREFIX_EVEX_0F38AB,
1663   PREFIX_EVEX_0F38AC,
1664   PREFIX_EVEX_0F38AD,
1665   PREFIX_EVEX_0F38AE,
1666   PREFIX_EVEX_0F38AF,
1667   PREFIX_EVEX_0F38B4,
1668   PREFIX_EVEX_0F38B5,
1669   PREFIX_EVEX_0F38B6,
1670   PREFIX_EVEX_0F38B7,
1671   PREFIX_EVEX_0F38B8,
1672   PREFIX_EVEX_0F38B9,
1673   PREFIX_EVEX_0F38BA,
1674   PREFIX_EVEX_0F38BB,
1675   PREFIX_EVEX_0F38BC,
1676   PREFIX_EVEX_0F38BD,
1677   PREFIX_EVEX_0F38BE,
1678   PREFIX_EVEX_0F38BF,
1679   PREFIX_EVEX_0F38C4,
1680   PREFIX_EVEX_0F38C6_REG_1,
1681   PREFIX_EVEX_0F38C6_REG_2,
1682   PREFIX_EVEX_0F38C6_REG_5,
1683   PREFIX_EVEX_0F38C6_REG_6,
1684   PREFIX_EVEX_0F38C7_REG_1,
1685   PREFIX_EVEX_0F38C7_REG_2,
1686   PREFIX_EVEX_0F38C7_REG_5,
1687   PREFIX_EVEX_0F38C7_REG_6,
1688   PREFIX_EVEX_0F38C8,
1689   PREFIX_EVEX_0F38CA,
1690   PREFIX_EVEX_0F38CB,
1691   PREFIX_EVEX_0F38CC,
1692   PREFIX_EVEX_0F38CD,
1693   PREFIX_EVEX_0F38CF,
1694   PREFIX_EVEX_0F38DC,
1695   PREFIX_EVEX_0F38DD,
1696   PREFIX_EVEX_0F38DE,
1697   PREFIX_EVEX_0F38DF,
1698
1699   PREFIX_EVEX_0F3A00,
1700   PREFIX_EVEX_0F3A01,
1701   PREFIX_EVEX_0F3A03,
1702   PREFIX_EVEX_0F3A04,
1703   PREFIX_EVEX_0F3A05,
1704   PREFIX_EVEX_0F3A08,
1705   PREFIX_EVEX_0F3A09,
1706   PREFIX_EVEX_0F3A0A,
1707   PREFIX_EVEX_0F3A0B,
1708   PREFIX_EVEX_0F3A0F,
1709   PREFIX_EVEX_0F3A14,
1710   PREFIX_EVEX_0F3A15,
1711   PREFIX_EVEX_0F3A16,
1712   PREFIX_EVEX_0F3A17,
1713   PREFIX_EVEX_0F3A18,
1714   PREFIX_EVEX_0F3A19,
1715   PREFIX_EVEX_0F3A1A,
1716   PREFIX_EVEX_0F3A1B,
1717   PREFIX_EVEX_0F3A1D,
1718   PREFIX_EVEX_0F3A1E,
1719   PREFIX_EVEX_0F3A1F,
1720   PREFIX_EVEX_0F3A20,
1721   PREFIX_EVEX_0F3A21,
1722   PREFIX_EVEX_0F3A22,
1723   PREFIX_EVEX_0F3A23,
1724   PREFIX_EVEX_0F3A25,
1725   PREFIX_EVEX_0F3A26,
1726   PREFIX_EVEX_0F3A27,
1727   PREFIX_EVEX_0F3A38,
1728   PREFIX_EVEX_0F3A39,
1729   PREFIX_EVEX_0F3A3A,
1730   PREFIX_EVEX_0F3A3B,
1731   PREFIX_EVEX_0F3A3E,
1732   PREFIX_EVEX_0F3A3F,
1733   PREFIX_EVEX_0F3A42,
1734   PREFIX_EVEX_0F3A43,
1735   PREFIX_EVEX_0F3A44,
1736   PREFIX_EVEX_0F3A50,
1737   PREFIX_EVEX_0F3A51,
1738   PREFIX_EVEX_0F3A54,
1739   PREFIX_EVEX_0F3A55,
1740   PREFIX_EVEX_0F3A56,
1741   PREFIX_EVEX_0F3A57,
1742   PREFIX_EVEX_0F3A66,
1743   PREFIX_EVEX_0F3A67,
1744   PREFIX_EVEX_0F3A70,
1745   PREFIX_EVEX_0F3A71,
1746   PREFIX_EVEX_0F3A72,
1747   PREFIX_EVEX_0F3A73,
1748   PREFIX_EVEX_0F3ACE,
1749   PREFIX_EVEX_0F3ACF
1750 };
1751
1752 enum
1753 {
1754   X86_64_06 = 0,
1755   X86_64_07,
1756   X86_64_0D,
1757   X86_64_16,
1758   X86_64_17,
1759   X86_64_1E,
1760   X86_64_1F,
1761   X86_64_27,
1762   X86_64_2F,
1763   X86_64_37,
1764   X86_64_3F,
1765   X86_64_60,
1766   X86_64_61,
1767   X86_64_62,
1768   X86_64_63,
1769   X86_64_6D,
1770   X86_64_6F,
1771   X86_64_82,
1772   X86_64_9A,
1773   X86_64_C4,
1774   X86_64_C5,
1775   X86_64_CE,
1776   X86_64_D4,
1777   X86_64_D5,
1778   X86_64_E8,
1779   X86_64_E9,
1780   X86_64_EA,
1781   X86_64_0F01_REG_0,
1782   X86_64_0F01_REG_1,
1783   X86_64_0F01_REG_2,
1784   X86_64_0F01_REG_3
1785 };
1786
1787 enum
1788 {
1789   THREE_BYTE_0F38 = 0,
1790   THREE_BYTE_0F3A
1791 };
1792
1793 enum
1794 {
1795   XOP_08 = 0,
1796   XOP_09,
1797   XOP_0A
1798 };
1799
1800 enum
1801 {
1802   VEX_0F = 0,
1803   VEX_0F38,
1804   VEX_0F3A
1805 };
1806
1807 enum
1808 {
1809   EVEX_0F = 0,
1810   EVEX_0F38,
1811   EVEX_0F3A
1812 };
1813
1814 enum
1815 {
1816   VEX_LEN_0F12_P_0_M_0 = 0,
1817   VEX_LEN_0F12_P_0_M_1,
1818   VEX_LEN_0F12_P_2,
1819   VEX_LEN_0F13_M_0,
1820   VEX_LEN_0F16_P_0_M_0,
1821   VEX_LEN_0F16_P_0_M_1,
1822   VEX_LEN_0F16_P_2,
1823   VEX_LEN_0F17_M_0,
1824   VEX_LEN_0F2A_P_1,
1825   VEX_LEN_0F2A_P_3,
1826   VEX_LEN_0F2C_P_1,
1827   VEX_LEN_0F2C_P_3,
1828   VEX_LEN_0F2D_P_1,
1829   VEX_LEN_0F2D_P_3,
1830   VEX_LEN_0F41_P_0,
1831   VEX_LEN_0F41_P_2,
1832   VEX_LEN_0F42_P_0,
1833   VEX_LEN_0F42_P_2,
1834   VEX_LEN_0F44_P_0,
1835   VEX_LEN_0F44_P_2,
1836   VEX_LEN_0F45_P_0,
1837   VEX_LEN_0F45_P_2,
1838   VEX_LEN_0F46_P_0,
1839   VEX_LEN_0F46_P_2,
1840   VEX_LEN_0F47_P_0,
1841   VEX_LEN_0F47_P_2,
1842   VEX_LEN_0F4A_P_0,
1843   VEX_LEN_0F4A_P_2,
1844   VEX_LEN_0F4B_P_0,
1845   VEX_LEN_0F4B_P_2,
1846   VEX_LEN_0F6E_P_2,
1847   VEX_LEN_0F77_P_0,
1848   VEX_LEN_0F7E_P_1,
1849   VEX_LEN_0F7E_P_2,
1850   VEX_LEN_0F90_P_0,
1851   VEX_LEN_0F90_P_2,
1852   VEX_LEN_0F91_P_0,
1853   VEX_LEN_0F91_P_2,
1854   VEX_LEN_0F92_P_0,
1855   VEX_LEN_0F92_P_2,
1856   VEX_LEN_0F92_P_3,
1857   VEX_LEN_0F93_P_0,
1858   VEX_LEN_0F93_P_2,
1859   VEX_LEN_0F93_P_3,
1860   VEX_LEN_0F98_P_0,
1861   VEX_LEN_0F98_P_2,
1862   VEX_LEN_0F99_P_0,
1863   VEX_LEN_0F99_P_2,
1864   VEX_LEN_0FAE_R_2_M_0,
1865   VEX_LEN_0FAE_R_3_M_0,
1866   VEX_LEN_0FC4_P_2,
1867   VEX_LEN_0FC5_P_2,
1868   VEX_LEN_0FD6_P_2,
1869   VEX_LEN_0FF7_P_2,
1870   VEX_LEN_0F3816_P_2,
1871   VEX_LEN_0F3819_P_2,
1872   VEX_LEN_0F381A_P_2_M_0,
1873   VEX_LEN_0F3836_P_2,
1874   VEX_LEN_0F3841_P_2,
1875   VEX_LEN_0F385A_P_2_M_0,
1876   VEX_LEN_0F38DB_P_2,
1877   VEX_LEN_0F38F2_P_0,
1878   VEX_LEN_0F38F3_R_1_P_0,
1879   VEX_LEN_0F38F3_R_2_P_0,
1880   VEX_LEN_0F38F3_R_3_P_0,
1881   VEX_LEN_0F38F5_P_0,
1882   VEX_LEN_0F38F5_P_1,
1883   VEX_LEN_0F38F5_P_3,
1884   VEX_LEN_0F38F6_P_3,
1885   VEX_LEN_0F38F7_P_0,
1886   VEX_LEN_0F38F7_P_1,
1887   VEX_LEN_0F38F7_P_2,
1888   VEX_LEN_0F38F7_P_3,
1889   VEX_LEN_0F3A00_P_2,
1890   VEX_LEN_0F3A01_P_2,
1891   VEX_LEN_0F3A06_P_2,
1892   VEX_LEN_0F3A14_P_2,
1893   VEX_LEN_0F3A15_P_2,
1894   VEX_LEN_0F3A16_P_2,
1895   VEX_LEN_0F3A17_P_2,
1896   VEX_LEN_0F3A18_P_2,
1897   VEX_LEN_0F3A19_P_2,
1898   VEX_LEN_0F3A20_P_2,
1899   VEX_LEN_0F3A21_P_2,
1900   VEX_LEN_0F3A22_P_2,
1901   VEX_LEN_0F3A30_P_2,
1902   VEX_LEN_0F3A31_P_2,
1903   VEX_LEN_0F3A32_P_2,
1904   VEX_LEN_0F3A33_P_2,
1905   VEX_LEN_0F3A38_P_2,
1906   VEX_LEN_0F3A39_P_2,
1907   VEX_LEN_0F3A41_P_2,
1908   VEX_LEN_0F3A46_P_2,
1909   VEX_LEN_0F3A60_P_2,
1910   VEX_LEN_0F3A61_P_2,
1911   VEX_LEN_0F3A62_P_2,
1912   VEX_LEN_0F3A63_P_2,
1913   VEX_LEN_0F3A6A_P_2,
1914   VEX_LEN_0F3A6B_P_2,
1915   VEX_LEN_0F3A6E_P_2,
1916   VEX_LEN_0F3A6F_P_2,
1917   VEX_LEN_0F3A7A_P_2,
1918   VEX_LEN_0F3A7B_P_2,
1919   VEX_LEN_0F3A7E_P_2,
1920   VEX_LEN_0F3A7F_P_2,
1921   VEX_LEN_0F3ADF_P_2,
1922   VEX_LEN_0F3AF0_P_3,
1923   VEX_LEN_0FXOP_08_CC,
1924   VEX_LEN_0FXOP_08_CD,
1925   VEX_LEN_0FXOP_08_CE,
1926   VEX_LEN_0FXOP_08_CF,
1927   VEX_LEN_0FXOP_08_EC,
1928   VEX_LEN_0FXOP_08_ED,
1929   VEX_LEN_0FXOP_08_EE,
1930   VEX_LEN_0FXOP_08_EF,
1931   VEX_LEN_0FXOP_09_80,
1932   VEX_LEN_0FXOP_09_81
1933 };
1934
1935 enum
1936 {
1937   EVEX_LEN_0F6E_P_2 = 0,
1938   EVEX_LEN_0F7E_P_1,
1939   EVEX_LEN_0F7E_P_2,
1940   EVEX_LEN_0FD6_P_2,
1941   EVEX_LEN_0F3819_P_2_W_0,
1942   EVEX_LEN_0F3819_P_2_W_1,
1943   EVEX_LEN_0F381A_P_2_W_0,
1944   EVEX_LEN_0F381A_P_2_W_1,
1945   EVEX_LEN_0F381B_P_2_W_0,
1946   EVEX_LEN_0F381B_P_2_W_1,
1947   EVEX_LEN_0F385A_P_2_W_0,
1948   EVEX_LEN_0F385A_P_2_W_1,
1949   EVEX_LEN_0F385B_P_2_W_0,
1950   EVEX_LEN_0F385B_P_2_W_1,
1951   EVEX_LEN_0F3A18_P_2_W_0,
1952   EVEX_LEN_0F3A18_P_2_W_1,
1953   EVEX_LEN_0F3A19_P_2_W_0,
1954   EVEX_LEN_0F3A19_P_2_W_1,
1955   EVEX_LEN_0F3A1A_P_2_W_0,
1956   EVEX_LEN_0F3A1A_P_2_W_1,
1957   EVEX_LEN_0F3A1B_P_2_W_0,
1958   EVEX_LEN_0F3A1B_P_2_W_1,
1959   EVEX_LEN_0F3A23_P_2_W_0,
1960   EVEX_LEN_0F3A23_P_2_W_1,
1961   EVEX_LEN_0F3A38_P_2_W_0,
1962   EVEX_LEN_0F3A38_P_2_W_1,
1963   EVEX_LEN_0F3A39_P_2_W_0,
1964   EVEX_LEN_0F3A39_P_2_W_1,
1965   EVEX_LEN_0F3A3A_P_2_W_0,
1966   EVEX_LEN_0F3A3A_P_2_W_1,
1967   EVEX_LEN_0F3A3B_P_2_W_0,
1968   EVEX_LEN_0F3A3B_P_2_W_1,
1969   EVEX_LEN_0F3A43_P_2_W_0,
1970   EVEX_LEN_0F3A43_P_2_W_1
1971 };
1972
1973 enum
1974 {
1975   VEX_W_0F41_P_0_LEN_1 = 0,
1976   VEX_W_0F41_P_2_LEN_1,
1977   VEX_W_0F42_P_0_LEN_1,
1978   VEX_W_0F42_P_2_LEN_1,
1979   VEX_W_0F44_P_0_LEN_0,
1980   VEX_W_0F44_P_2_LEN_0,
1981   VEX_W_0F45_P_0_LEN_1,
1982   VEX_W_0F45_P_2_LEN_1,
1983   VEX_W_0F46_P_0_LEN_1,
1984   VEX_W_0F46_P_2_LEN_1,
1985   VEX_W_0F47_P_0_LEN_1,
1986   VEX_W_0F47_P_2_LEN_1,
1987   VEX_W_0F4A_P_0_LEN_1,
1988   VEX_W_0F4A_P_2_LEN_1,
1989   VEX_W_0F4B_P_0_LEN_1,
1990   VEX_W_0F4B_P_2_LEN_1,
1991   VEX_W_0F90_P_0_LEN_0,
1992   VEX_W_0F90_P_2_LEN_0,
1993   VEX_W_0F91_P_0_LEN_0,
1994   VEX_W_0F91_P_2_LEN_0,
1995   VEX_W_0F92_P_0_LEN_0,
1996   VEX_W_0F92_P_2_LEN_0,
1997   VEX_W_0F93_P_0_LEN_0,
1998   VEX_W_0F93_P_2_LEN_0,
1999   VEX_W_0F98_P_0_LEN_0,
2000   VEX_W_0F98_P_2_LEN_0,
2001   VEX_W_0F99_P_0_LEN_0,
2002   VEX_W_0F99_P_2_LEN_0,
2003   VEX_W_0F380C_P_2,
2004   VEX_W_0F380D_P_2,
2005   VEX_W_0F380E_P_2,
2006   VEX_W_0F380F_P_2,
2007   VEX_W_0F3816_P_2,
2008   VEX_W_0F3818_P_2,
2009   VEX_W_0F3819_P_2,
2010   VEX_W_0F381A_P_2_M_0,
2011   VEX_W_0F382C_P_2_M_0,
2012   VEX_W_0F382D_P_2_M_0,
2013   VEX_W_0F382E_P_2_M_0,
2014   VEX_W_0F382F_P_2_M_0,
2015   VEX_W_0F3836_P_2,
2016   VEX_W_0F3846_P_2,
2017   VEX_W_0F3858_P_2,
2018   VEX_W_0F3859_P_2,
2019   VEX_W_0F385A_P_2_M_0,
2020   VEX_W_0F3878_P_2,
2021   VEX_W_0F3879_P_2,
2022   VEX_W_0F38CF_P_2,
2023   VEX_W_0F3A00_P_2,
2024   VEX_W_0F3A01_P_2,
2025   VEX_W_0F3A02_P_2,
2026   VEX_W_0F3A04_P_2,
2027   VEX_W_0F3A05_P_2,
2028   VEX_W_0F3A06_P_2,
2029   VEX_W_0F3A18_P_2,
2030   VEX_W_0F3A19_P_2,
2031   VEX_W_0F3A30_P_2_LEN_0,
2032   VEX_W_0F3A31_P_2_LEN_0,
2033   VEX_W_0F3A32_P_2_LEN_0,
2034   VEX_W_0F3A33_P_2_LEN_0,
2035   VEX_W_0F3A38_P_2,
2036   VEX_W_0F3A39_P_2,
2037   VEX_W_0F3A46_P_2,
2038   VEX_W_0F3A48_P_2,
2039   VEX_W_0F3A49_P_2,
2040   VEX_W_0F3A4A_P_2,
2041   VEX_W_0F3A4B_P_2,
2042   VEX_W_0F3A4C_P_2,
2043   VEX_W_0F3ACE_P_2,
2044   VEX_W_0F3ACF_P_2,
2045
2046   EVEX_W_0F10_P_0,
2047   EVEX_W_0F10_P_1_M_0,
2048   EVEX_W_0F10_P_1_M_1,
2049   EVEX_W_0F10_P_2,
2050   EVEX_W_0F10_P_3_M_0,
2051   EVEX_W_0F10_P_3_M_1,
2052   EVEX_W_0F11_P_0,
2053   EVEX_W_0F11_P_1_M_0,
2054   EVEX_W_0F11_P_1_M_1,
2055   EVEX_W_0F11_P_2,
2056   EVEX_W_0F11_P_3_M_0,
2057   EVEX_W_0F11_P_3_M_1,
2058   EVEX_W_0F12_P_0_M_0,
2059   EVEX_W_0F12_P_0_M_1,
2060   EVEX_W_0F12_P_1,
2061   EVEX_W_0F12_P_2,
2062   EVEX_W_0F12_P_3,
2063   EVEX_W_0F13_P_0,
2064   EVEX_W_0F13_P_2,
2065   EVEX_W_0F14_P_0,
2066   EVEX_W_0F14_P_2,
2067   EVEX_W_0F15_P_0,
2068   EVEX_W_0F15_P_2,
2069   EVEX_W_0F16_P_0_M_0,
2070   EVEX_W_0F16_P_0_M_1,
2071   EVEX_W_0F16_P_1,
2072   EVEX_W_0F16_P_2,
2073   EVEX_W_0F17_P_0,
2074   EVEX_W_0F17_P_2,
2075   EVEX_W_0F28_P_0,
2076   EVEX_W_0F28_P_2,
2077   EVEX_W_0F29_P_0,
2078   EVEX_W_0F29_P_2,
2079   EVEX_W_0F2A_P_1,
2080   EVEX_W_0F2A_P_3,
2081   EVEX_W_0F2B_P_0,
2082   EVEX_W_0F2B_P_2,
2083   EVEX_W_0F2E_P_0,
2084   EVEX_W_0F2E_P_2,
2085   EVEX_W_0F2F_P_0,
2086   EVEX_W_0F2F_P_2,
2087   EVEX_W_0F51_P_0,
2088   EVEX_W_0F51_P_1,
2089   EVEX_W_0F51_P_2,
2090   EVEX_W_0F51_P_3,
2091   EVEX_W_0F54_P_0,
2092   EVEX_W_0F54_P_2,
2093   EVEX_W_0F55_P_0,
2094   EVEX_W_0F55_P_2,
2095   EVEX_W_0F56_P_0,
2096   EVEX_W_0F56_P_2,
2097   EVEX_W_0F57_P_0,
2098   EVEX_W_0F57_P_2,
2099   EVEX_W_0F58_P_0,
2100   EVEX_W_0F58_P_1,
2101   EVEX_W_0F58_P_2,
2102   EVEX_W_0F58_P_3,
2103   EVEX_W_0F59_P_0,
2104   EVEX_W_0F59_P_1,
2105   EVEX_W_0F59_P_2,
2106   EVEX_W_0F59_P_3,
2107   EVEX_W_0F5A_P_0,
2108   EVEX_W_0F5A_P_1,
2109   EVEX_W_0F5A_P_2,
2110   EVEX_W_0F5A_P_3,
2111   EVEX_W_0F5B_P_0,
2112   EVEX_W_0F5B_P_1,
2113   EVEX_W_0F5B_P_2,
2114   EVEX_W_0F5C_P_0,
2115   EVEX_W_0F5C_P_1,
2116   EVEX_W_0F5C_P_2,
2117   EVEX_W_0F5C_P_3,
2118   EVEX_W_0F5D_P_0,
2119   EVEX_W_0F5D_P_1,
2120   EVEX_W_0F5D_P_2,
2121   EVEX_W_0F5D_P_3,
2122   EVEX_W_0F5E_P_0,
2123   EVEX_W_0F5E_P_1,
2124   EVEX_W_0F5E_P_2,
2125   EVEX_W_0F5E_P_3,
2126   EVEX_W_0F5F_P_0,
2127   EVEX_W_0F5F_P_1,
2128   EVEX_W_0F5F_P_2,
2129   EVEX_W_0F5F_P_3,
2130   EVEX_W_0F62_P_2,
2131   EVEX_W_0F66_P_2,
2132   EVEX_W_0F6A_P_2,
2133   EVEX_W_0F6B_P_2,
2134   EVEX_W_0F6C_P_2,
2135   EVEX_W_0F6D_P_2,
2136   EVEX_W_0F6F_P_1,
2137   EVEX_W_0F6F_P_2,
2138   EVEX_W_0F6F_P_3,
2139   EVEX_W_0F70_P_2,
2140   EVEX_W_0F72_R_2_P_2,
2141   EVEX_W_0F72_R_6_P_2,
2142   EVEX_W_0F73_R_2_P_2,
2143   EVEX_W_0F73_R_6_P_2,
2144   EVEX_W_0F76_P_2,
2145   EVEX_W_0F78_P_0,
2146   EVEX_W_0F78_P_2,
2147   EVEX_W_0F79_P_0,
2148   EVEX_W_0F79_P_2,
2149   EVEX_W_0F7A_P_1,
2150   EVEX_W_0F7A_P_2,
2151   EVEX_W_0F7A_P_3,
2152   EVEX_W_0F7B_P_1,
2153   EVEX_W_0F7B_P_2,
2154   EVEX_W_0F7B_P_3,
2155   EVEX_W_0F7E_P_1,
2156   EVEX_W_0F7F_P_1,
2157   EVEX_W_0F7F_P_2,
2158   EVEX_W_0F7F_P_3,
2159   EVEX_W_0FC2_P_0,
2160   EVEX_W_0FC2_P_1,
2161   EVEX_W_0FC2_P_2,
2162   EVEX_W_0FC2_P_3,
2163   EVEX_W_0FC6_P_0,
2164   EVEX_W_0FC6_P_2,
2165   EVEX_W_0FD2_P_2,
2166   EVEX_W_0FD3_P_2,
2167   EVEX_W_0FD4_P_2,
2168   EVEX_W_0FD6_P_2,
2169   EVEX_W_0FE6_P_1,
2170   EVEX_W_0FE6_P_2,
2171   EVEX_W_0FE6_P_3,
2172   EVEX_W_0FE7_P_2,
2173   EVEX_W_0FF2_P_2,
2174   EVEX_W_0FF3_P_2,
2175   EVEX_W_0FF4_P_2,
2176   EVEX_W_0FFA_P_2,
2177   EVEX_W_0FFB_P_2,
2178   EVEX_W_0FFE_P_2,
2179   EVEX_W_0F380C_P_2,
2180   EVEX_W_0F380D_P_2,
2181   EVEX_W_0F3810_P_1,
2182   EVEX_W_0F3810_P_2,
2183   EVEX_W_0F3811_P_1,
2184   EVEX_W_0F3811_P_2,
2185   EVEX_W_0F3812_P_1,
2186   EVEX_W_0F3812_P_2,
2187   EVEX_W_0F3813_P_1,
2188   EVEX_W_0F3813_P_2,
2189   EVEX_W_0F3814_P_1,
2190   EVEX_W_0F3815_P_1,
2191   EVEX_W_0F3818_P_2,
2192   EVEX_W_0F3819_P_2,
2193   EVEX_W_0F381A_P_2,
2194   EVEX_W_0F381B_P_2,
2195   EVEX_W_0F381E_P_2,
2196   EVEX_W_0F381F_P_2,
2197   EVEX_W_0F3820_P_1,
2198   EVEX_W_0F3821_P_1,
2199   EVEX_W_0F3822_P_1,
2200   EVEX_W_0F3823_P_1,
2201   EVEX_W_0F3824_P_1,
2202   EVEX_W_0F3825_P_1,
2203   EVEX_W_0F3825_P_2,
2204   EVEX_W_0F3826_P_1,
2205   EVEX_W_0F3826_P_2,
2206   EVEX_W_0F3828_P_1,
2207   EVEX_W_0F3828_P_2,
2208   EVEX_W_0F3829_P_1,
2209   EVEX_W_0F3829_P_2,
2210   EVEX_W_0F382A_P_1,
2211   EVEX_W_0F382A_P_2,
2212   EVEX_W_0F382B_P_2,
2213   EVEX_W_0F3830_P_1,
2214   EVEX_W_0F3831_P_1,
2215   EVEX_W_0F3832_P_1,
2216   EVEX_W_0F3833_P_1,
2217   EVEX_W_0F3834_P_1,
2218   EVEX_W_0F3835_P_1,
2219   EVEX_W_0F3835_P_2,
2220   EVEX_W_0F3837_P_2,
2221   EVEX_W_0F3838_P_1,
2222   EVEX_W_0F3839_P_1,
2223   EVEX_W_0F383A_P_1,
2224   EVEX_W_0F3840_P_2,
2225   EVEX_W_0F3852_P_1,
2226   EVEX_W_0F3854_P_2,
2227   EVEX_W_0F3855_P_2,
2228   EVEX_W_0F3858_P_2,
2229   EVEX_W_0F3859_P_2,
2230   EVEX_W_0F385A_P_2,
2231   EVEX_W_0F385B_P_2,
2232   EVEX_W_0F3862_P_2,
2233   EVEX_W_0F3863_P_2,
2234   EVEX_W_0F3866_P_2,
2235   EVEX_W_0F3868_P_3,
2236   EVEX_W_0F3870_P_2,
2237   EVEX_W_0F3871_P_2,
2238   EVEX_W_0F3872_P_1,
2239   EVEX_W_0F3872_P_2,
2240   EVEX_W_0F3872_P_3,
2241   EVEX_W_0F3873_P_2,
2242   EVEX_W_0F3875_P_2,
2243   EVEX_W_0F3878_P_2,
2244   EVEX_W_0F3879_P_2,
2245   EVEX_W_0F387A_P_2,
2246   EVEX_W_0F387B_P_2,
2247   EVEX_W_0F387D_P_2,
2248   EVEX_W_0F3883_P_2,
2249   EVEX_W_0F388D_P_2,
2250   EVEX_W_0F3891_P_2,
2251   EVEX_W_0F3893_P_2,
2252   EVEX_W_0F38A1_P_2,
2253   EVEX_W_0F38A3_P_2,
2254   EVEX_W_0F38C7_R_1_P_2,
2255   EVEX_W_0F38C7_R_2_P_2,
2256   EVEX_W_0F38C7_R_5_P_2,
2257   EVEX_W_0F38C7_R_6_P_2,
2258
2259   EVEX_W_0F3A00_P_2,
2260   EVEX_W_0F3A01_P_2,
2261   EVEX_W_0F3A04_P_2,
2262   EVEX_W_0F3A05_P_2,
2263   EVEX_W_0F3A08_P_2,
2264   EVEX_W_0F3A09_P_2,
2265   EVEX_W_0F3A0A_P_2,
2266   EVEX_W_0F3A0B_P_2,
2267   EVEX_W_0F3A18_P_2,
2268   EVEX_W_0F3A19_P_2,
2269   EVEX_W_0F3A1A_P_2,
2270   EVEX_W_0F3A1B_P_2,
2271   EVEX_W_0F3A1D_P_2,
2272   EVEX_W_0F3A21_P_2,
2273   EVEX_W_0F3A23_P_2,
2274   EVEX_W_0F3A38_P_2,
2275   EVEX_W_0F3A39_P_2,
2276   EVEX_W_0F3A3A_P_2,
2277   EVEX_W_0F3A3B_P_2,
2278   EVEX_W_0F3A3E_P_2,
2279   EVEX_W_0F3A3F_P_2,
2280   EVEX_W_0F3A42_P_2,
2281   EVEX_W_0F3A43_P_2,
2282   EVEX_W_0F3A50_P_2,
2283   EVEX_W_0F3A51_P_2,
2284   EVEX_W_0F3A56_P_2,
2285   EVEX_W_0F3A57_P_2,
2286   EVEX_W_0F3A66_P_2,
2287   EVEX_W_0F3A67_P_2,
2288   EVEX_W_0F3A70_P_2,
2289   EVEX_W_0F3A71_P_2,
2290   EVEX_W_0F3A72_P_2,
2291   EVEX_W_0F3A73_P_2,
2292   EVEX_W_0F3ACE_P_2,
2293   EVEX_W_0F3ACF_P_2
2294 };
2295
2296 typedef void (*op_rtn) (int bytemode, int sizeflag);
2297
2298 struct dis386 {
2299   const char *name;
2300   struct
2301     {
2302       op_rtn rtn;
2303       int bytemode;
2304     } op[MAX_OPERANDS];
2305   unsigned int prefix_requirement;
2306 };
2307
2308 /* Upper case letters in the instruction names here are macros.
2309    'A' => print 'b' if no register operands or suffix_always is true
2310    'B' => print 'b' if suffix_always is true
2311    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2312           size prefix
2313    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2314           suffix_always is true
2315    'E' => print 'e' if 32-bit form of jcxz
2316    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2317    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2318    'H' => print ",pt" or ",pn" branch hint
2319    'I' => honor following macro letter even in Intel mode (implemented only
2320           for some of the macro letters)
2321    'J' => print 'l'
2322    'K' => print 'd' or 'q' if rex prefix is present.
2323    'L' => print 'l' if suffix_always is true
2324    'M' => print 'r' if intel_mnemonic is false.
2325    'N' => print 'n' if instruction has no wait "prefix"
2326    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2327    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2328           or suffix_always is true.  print 'q' if rex prefix is present.
2329    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2330           is true
2331    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2332    'S' => print 'w', 'l' or 'q' if suffix_always is true
2333    'T' => print 'q' in 64bit mode if instruction has no operand size
2334           prefix and behave as 'P' otherwise
2335    'U' => print 'q' in 64bit mode if instruction has no operand size
2336           prefix and behave as 'Q' otherwise
2337    'V' => print 'q' in 64bit mode if instruction has no operand size
2338           prefix and behave as 'S' otherwise
2339    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2340    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2341    'Y' unused.
2342    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2343    '!' => change condition from true to false or from false to true.
2344    '%' => add 1 upper case letter to the macro.
2345    '^' => print 'w' or 'l' depending on operand size prefix or
2346           suffix_always is true (lcall/ljmp).
2347    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2348           on operand size prefix.
2349    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2350           has no operand size prefix for AMD64 ISA, behave as 'P'
2351           otherwise
2352
2353    2 upper case letter macros:
2354    "XY" => print 'x' or 'y' if suffix_always is true or no register
2355            operands and no broadcast.
2356    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2357            register operands and no broadcast.
2358    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2359    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2360            or suffix_always is true
2361    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2362    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2363    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2364    "LW" => print 'd', 'q' depending on the VEX.W bit
2365    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2366            an operand size prefix, or suffix_always is true.  print
2367            'q' if rex prefix is present.
2368
2369    Many of the above letters print nothing in Intel mode.  See "putop"
2370    for the details.
2371
2372    Braces '{' and '}', and vertical bars '|', indicate alternative
2373    mnemonic strings for AT&T and Intel.  */
2374
2375 static const struct dis386 dis386[] = {
2376   /* 00 */
2377   { "addB",             { Ebh1, Gb }, 0 },
2378   { "addS",             { Evh1, Gv }, 0 },
2379   { "addB",             { Gb, EbS }, 0 },
2380   { "addS",             { Gv, EvS }, 0 },
2381   { "addB",             { AL, Ib }, 0 },
2382   { "addS",             { eAX, Iv }, 0 },
2383   { X86_64_TABLE (X86_64_06) },
2384   { X86_64_TABLE (X86_64_07) },
2385   /* 08 */
2386   { "orB",              { Ebh1, Gb }, 0 },
2387   { "orS",              { Evh1, Gv }, 0 },
2388   { "orB",              { Gb, EbS }, 0 },
2389   { "orS",              { Gv, EvS }, 0 },
2390   { "orB",              { AL, Ib }, 0 },
2391   { "orS",              { eAX, Iv }, 0 },
2392   { X86_64_TABLE (X86_64_0D) },
2393   { Bad_Opcode },       /* 0x0f extended opcode escape */
2394   /* 10 */
2395   { "adcB",             { Ebh1, Gb }, 0 },
2396   { "adcS",             { Evh1, Gv }, 0 },
2397   { "adcB",             { Gb, EbS }, 0 },
2398   { "adcS",             { Gv, EvS }, 0 },
2399   { "adcB",             { AL, Ib }, 0 },
2400   { "adcS",             { eAX, Iv }, 0 },
2401   { X86_64_TABLE (X86_64_16) },
2402   { X86_64_TABLE (X86_64_17) },
2403   /* 18 */
2404   { "sbbB",             { Ebh1, Gb }, 0 },
2405   { "sbbS",             { Evh1, Gv }, 0 },
2406   { "sbbB",             { Gb, EbS }, 0 },
2407   { "sbbS",             { Gv, EvS }, 0 },
2408   { "sbbB",             { AL, Ib }, 0 },
2409   { "sbbS",             { eAX, Iv }, 0 },
2410   { X86_64_TABLE (X86_64_1E) },
2411   { X86_64_TABLE (X86_64_1F) },
2412   /* 20 */
2413   { "andB",             { Ebh1, Gb }, 0 },
2414   { "andS",             { Evh1, Gv }, 0 },
2415   { "andB",             { Gb, EbS }, 0 },
2416   { "andS",             { Gv, EvS }, 0 },
2417   { "andB",             { AL, Ib }, 0 },
2418   { "andS",             { eAX, Iv }, 0 },
2419   { Bad_Opcode },       /* SEG ES prefix */
2420   { X86_64_TABLE (X86_64_27) },
2421   /* 28 */
2422   { "subB",             { Ebh1, Gb }, 0 },
2423   { "subS",             { Evh1, Gv }, 0 },
2424   { "subB",             { Gb, EbS }, 0 },
2425   { "subS",             { Gv, EvS }, 0 },
2426   { "subB",             { AL, Ib }, 0 },
2427   { "subS",             { eAX, Iv }, 0 },
2428   { Bad_Opcode },       /* SEG CS prefix */
2429   { X86_64_TABLE (X86_64_2F) },
2430   /* 30 */
2431   { "xorB",             { Ebh1, Gb }, 0 },
2432   { "xorS",             { Evh1, Gv }, 0 },
2433   { "xorB",             { Gb, EbS }, 0 },
2434   { "xorS",             { Gv, EvS }, 0 },
2435   { "xorB",             { AL, Ib }, 0 },
2436   { "xorS",             { eAX, Iv }, 0 },
2437   { Bad_Opcode },       /* SEG SS prefix */
2438   { X86_64_TABLE (X86_64_37) },
2439   /* 38 */
2440   { "cmpB",             { Eb, Gb }, 0 },
2441   { "cmpS",             { Ev, Gv }, 0 },
2442   { "cmpB",             { Gb, EbS }, 0 },
2443   { "cmpS",             { Gv, EvS }, 0 },
2444   { "cmpB",             { AL, Ib }, 0 },
2445   { "cmpS",             { eAX, Iv }, 0 },
2446   { Bad_Opcode },       /* SEG DS prefix */
2447   { X86_64_TABLE (X86_64_3F) },
2448   /* 40 */
2449   { "inc{S|}",          { RMeAX }, 0 },
2450   { "inc{S|}",          { RMeCX }, 0 },
2451   { "inc{S|}",          { RMeDX }, 0 },
2452   { "inc{S|}",          { RMeBX }, 0 },
2453   { "inc{S|}",          { RMeSP }, 0 },
2454   { "inc{S|}",          { RMeBP }, 0 },
2455   { "inc{S|}",          { RMeSI }, 0 },
2456   { "inc{S|}",          { RMeDI }, 0 },
2457   /* 48 */
2458   { "dec{S|}",          { RMeAX }, 0 },
2459   { "dec{S|}",          { RMeCX }, 0 },
2460   { "dec{S|}",          { RMeDX }, 0 },
2461   { "dec{S|}",          { RMeBX }, 0 },
2462   { "dec{S|}",          { RMeSP }, 0 },
2463   { "dec{S|}",          { RMeBP }, 0 },
2464   { "dec{S|}",          { RMeSI }, 0 },
2465   { "dec{S|}",          { RMeDI }, 0 },
2466   /* 50 */
2467   { "pushV",            { RMrAX }, 0 },
2468   { "pushV",            { RMrCX }, 0 },
2469   { "pushV",            { RMrDX }, 0 },
2470   { "pushV",            { RMrBX }, 0 },
2471   { "pushV",            { RMrSP }, 0 },
2472   { "pushV",            { RMrBP }, 0 },
2473   { "pushV",            { RMrSI }, 0 },
2474   { "pushV",            { RMrDI }, 0 },
2475   /* 58 */
2476   { "popV",             { RMrAX }, 0 },
2477   { "popV",             { RMrCX }, 0 },
2478   { "popV",             { RMrDX }, 0 },
2479   { "popV",             { RMrBX }, 0 },
2480   { "popV",             { RMrSP }, 0 },
2481   { "popV",             { RMrBP }, 0 },
2482   { "popV",             { RMrSI }, 0 },
2483   { "popV",             { RMrDI }, 0 },
2484   /* 60 */
2485   { X86_64_TABLE (X86_64_60) },
2486   { X86_64_TABLE (X86_64_61) },
2487   { X86_64_TABLE (X86_64_62) },
2488   { X86_64_TABLE (X86_64_63) },
2489   { Bad_Opcode },       /* seg fs */
2490   { Bad_Opcode },       /* seg gs */
2491   { Bad_Opcode },       /* op size prefix */
2492   { Bad_Opcode },       /* adr size prefix */
2493   /* 68 */
2494   { "pushT",            { sIv }, 0 },
2495   { "imulS",            { Gv, Ev, Iv }, 0 },
2496   { "pushT",            { sIbT }, 0 },
2497   { "imulS",            { Gv, Ev, sIb }, 0 },
2498   { "ins{b|}",          { Ybr, indirDX }, 0 },
2499   { X86_64_TABLE (X86_64_6D) },
2500   { "outs{b|}",         { indirDXr, Xb }, 0 },
2501   { X86_64_TABLE (X86_64_6F) },
2502   /* 70 */
2503   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2506   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2508   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2509   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2510   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2511   /* 78 */
2512   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2513   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2514   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2515   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2516   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2517   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2518   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2519   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2520   /* 80 */
2521   { REG_TABLE (REG_80) },
2522   { REG_TABLE (REG_81) },
2523   { X86_64_TABLE (X86_64_82) },
2524   { REG_TABLE (REG_83) },
2525   { "testB",            { Eb, Gb }, 0 },
2526   { "testS",            { Ev, Gv }, 0 },
2527   { "xchgB",            { Ebh2, Gb }, 0 },
2528   { "xchgS",            { Evh2, Gv }, 0 },
2529   /* 88 */
2530   { "movB",             { Ebh3, Gb }, 0 },
2531   { "movS",             { Evh3, Gv }, 0 },
2532   { "movB",             { Gb, EbS }, 0 },
2533   { "movS",             { Gv, EvS }, 0 },
2534   { "movD",             { Sv, Sw }, 0 },
2535   { MOD_TABLE (MOD_8D) },
2536   { "movD",             { Sw, Sv }, 0 },
2537   { REG_TABLE (REG_8F) },
2538   /* 90 */
2539   { PREFIX_TABLE (PREFIX_90) },
2540   { "xchgS",            { RMeCX, eAX }, 0 },
2541   { "xchgS",            { RMeDX, eAX }, 0 },
2542   { "xchgS",            { RMeBX, eAX }, 0 },
2543   { "xchgS",            { RMeSP, eAX }, 0 },
2544   { "xchgS",            { RMeBP, eAX }, 0 },
2545   { "xchgS",            { RMeSI, eAX }, 0 },
2546   { "xchgS",            { RMeDI, eAX }, 0 },
2547   /* 98 */
2548   { "cW{t|}R",          { XX }, 0 },
2549   { "cR{t|}O",          { XX }, 0 },
2550   { X86_64_TABLE (X86_64_9A) },
2551   { Bad_Opcode },       /* fwait */
2552   { "pushfT",           { XX }, 0 },
2553   { "popfT",            { XX }, 0 },
2554   { "sahf",             { XX }, 0 },
2555   { "lahf",             { XX }, 0 },
2556   /* a0 */
2557   { "mov%LB",           { AL, Ob }, 0 },
2558   { "mov%LS",           { eAX, Ov }, 0 },
2559   { "mov%LB",           { Ob, AL }, 0 },
2560   { "mov%LS",           { Ov, eAX }, 0 },
2561   { "movs{b|}",         { Ybr, Xb }, 0 },
2562   { "movs{R|}",         { Yvr, Xv }, 0 },
2563   { "cmps{b|}",         { Xb, Yb }, 0 },
2564   { "cmps{R|}",         { Xv, Yv }, 0 },
2565   /* a8 */
2566   { "testB",            { AL, Ib }, 0 },
2567   { "testS",            { eAX, Iv }, 0 },
2568   { "stosB",            { Ybr, AL }, 0 },
2569   { "stosS",            { Yvr, eAX }, 0 },
2570   { "lodsB",            { ALr, Xb }, 0 },
2571   { "lodsS",            { eAXr, Xv }, 0 },
2572   { "scasB",            { AL, Yb }, 0 },
2573   { "scasS",            { eAX, Yv }, 0 },
2574   /* b0 */
2575   { "movB",             { RMAL, Ib }, 0 },
2576   { "movB",             { RMCL, Ib }, 0 },
2577   { "movB",             { RMDL, Ib }, 0 },
2578   { "movB",             { RMBL, Ib }, 0 },
2579   { "movB",             { RMAH, Ib }, 0 },
2580   { "movB",             { RMCH, Ib }, 0 },
2581   { "movB",             { RMDH, Ib }, 0 },
2582   { "movB",             { RMBH, Ib }, 0 },
2583   /* b8 */
2584   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2585   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2586   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2587   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2588   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2589   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2590   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2591   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2592   /* c0 */
2593   { REG_TABLE (REG_C0) },
2594   { REG_TABLE (REG_C1) },
2595   { "retT",             { Iw, BND }, 0 },
2596   { "retT",             { BND }, 0 },
2597   { X86_64_TABLE (X86_64_C4) },
2598   { X86_64_TABLE (X86_64_C5) },
2599   { REG_TABLE (REG_C6) },
2600   { REG_TABLE (REG_C7) },
2601   /* c8 */
2602   { "enterT",           { Iw, Ib }, 0 },
2603   { "leaveT",           { XX }, 0 },
2604   { "Jret{|f}P",        { Iw }, 0 },
2605   { "Jret{|f}P",        { XX }, 0 },
2606   { "int3",             { XX }, 0 },
2607   { "int",              { Ib }, 0 },
2608   { X86_64_TABLE (X86_64_CE) },
2609   { "iret%LP",          { XX }, 0 },
2610   /* d0 */
2611   { REG_TABLE (REG_D0) },
2612   { REG_TABLE (REG_D1) },
2613   { REG_TABLE (REG_D2) },
2614   { REG_TABLE (REG_D3) },
2615   { X86_64_TABLE (X86_64_D4) },
2616   { X86_64_TABLE (X86_64_D5) },
2617   { Bad_Opcode },
2618   { "xlat",             { DSBX }, 0 },
2619   /* d8 */
2620   { FLOAT },
2621   { FLOAT },
2622   { FLOAT },
2623   { FLOAT },
2624   { FLOAT },
2625   { FLOAT },
2626   { FLOAT },
2627   { FLOAT },
2628   /* e0 */
2629   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2630   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2631   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2632   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2633   { "inB",              { AL, Ib }, 0 },
2634   { "inG",              { zAX, Ib }, 0 },
2635   { "outB",             { Ib, AL }, 0 },
2636   { "outG",             { Ib, zAX }, 0 },
2637   /* e8 */
2638   { X86_64_TABLE (X86_64_E8) },
2639   { X86_64_TABLE (X86_64_E9) },
2640   { X86_64_TABLE (X86_64_EA) },
2641   { "jmp",              { Jb, BND }, 0 },
2642   { "inB",              { AL, indirDX }, 0 },
2643   { "inG",              { zAX, indirDX }, 0 },
2644   { "outB",             { indirDX, AL }, 0 },
2645   { "outG",             { indirDX, zAX }, 0 },
2646   /* f0 */
2647   { Bad_Opcode },       /* lock prefix */
2648   { "icebp",            { XX }, 0 },
2649   { Bad_Opcode },       /* repne */
2650   { Bad_Opcode },       /* repz */
2651   { "hlt",              { XX }, 0 },
2652   { "cmc",              { XX }, 0 },
2653   { REG_TABLE (REG_F6) },
2654   { REG_TABLE (REG_F7) },
2655   /* f8 */
2656   { "clc",              { XX }, 0 },
2657   { "stc",              { XX }, 0 },
2658   { "cli",              { XX }, 0 },
2659   { "sti",              { XX }, 0 },
2660   { "cld",              { XX }, 0 },
2661   { "std",              { XX }, 0 },
2662   { REG_TABLE (REG_FE) },
2663   { REG_TABLE (REG_FF) },
2664 };
2665
2666 static const struct dis386 dis386_twobyte[] = {
2667   /* 00 */
2668   { REG_TABLE (REG_0F00 ) },
2669   { REG_TABLE (REG_0F01 ) },
2670   { "larS",             { Gv, Ew }, 0 },
2671   { "lslS",             { Gv, Ew }, 0 },
2672   { Bad_Opcode },
2673   { "syscall",          { XX }, 0 },
2674   { "clts",             { XX }, 0 },
2675   { "sysret%LP",                { XX }, 0 },
2676   /* 08 */
2677   { "invd",             { XX }, 0 },
2678   { PREFIX_TABLE (PREFIX_0F09) },
2679   { Bad_Opcode },
2680   { "ud2",              { XX }, 0 },
2681   { Bad_Opcode },
2682   { REG_TABLE (REG_0F0D) },
2683   { "femms",            { XX }, 0 },
2684   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2685   /* 10 */
2686   { PREFIX_TABLE (PREFIX_0F10) },
2687   { PREFIX_TABLE (PREFIX_0F11) },
2688   { PREFIX_TABLE (PREFIX_0F12) },
2689   { MOD_TABLE (MOD_0F13) },
2690   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2691   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2692   { PREFIX_TABLE (PREFIX_0F16) },
2693   { MOD_TABLE (MOD_0F17) },
2694   /* 18 */
2695   { REG_TABLE (REG_0F18) },
2696   { "nopQ",             { Ev }, 0 },
2697   { PREFIX_TABLE (PREFIX_0F1A) },
2698   { PREFIX_TABLE (PREFIX_0F1B) },
2699   { PREFIX_TABLE (PREFIX_0F1C) },
2700   { "nopQ",             { Ev }, 0 },
2701   { PREFIX_TABLE (PREFIX_0F1E) },
2702   { "nopQ",             { Ev }, 0 },
2703   /* 20 */
2704   { "movZ",             { Rm, Cm }, 0 },
2705   { "movZ",             { Rm, Dm }, 0 },
2706   { "movZ",             { Cm, Rm }, 0 },
2707   { "movZ",             { Dm, Rm }, 0 },
2708   { MOD_TABLE (MOD_0F24) },
2709   { Bad_Opcode },
2710   { MOD_TABLE (MOD_0F26) },
2711   { Bad_Opcode },
2712   /* 28 */
2713   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2714   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2715   { PREFIX_TABLE (PREFIX_0F2A) },
2716   { PREFIX_TABLE (PREFIX_0F2B) },
2717   { PREFIX_TABLE (PREFIX_0F2C) },
2718   { PREFIX_TABLE (PREFIX_0F2D) },
2719   { PREFIX_TABLE (PREFIX_0F2E) },
2720   { PREFIX_TABLE (PREFIX_0F2F) },
2721   /* 30 */
2722   { "wrmsr",            { XX }, 0 },
2723   { "rdtsc",            { XX }, 0 },
2724   { "rdmsr",            { XX }, 0 },
2725   { "rdpmc",            { XX }, 0 },
2726   { "sysenter",         { XX }, 0 },
2727   { "sysexit",          { XX }, 0 },
2728   { Bad_Opcode },
2729   { "getsec",           { XX }, 0 },
2730   /* 38 */
2731   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2732   { Bad_Opcode },
2733   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2734   { Bad_Opcode },
2735   { Bad_Opcode },
2736   { Bad_Opcode },
2737   { Bad_Opcode },
2738   { Bad_Opcode },
2739   /* 40 */
2740   { "cmovoS",           { Gv, Ev }, 0 },
2741   { "cmovnoS",          { Gv, Ev }, 0 },
2742   { "cmovbS",           { Gv, Ev }, 0 },
2743   { "cmovaeS",          { Gv, Ev }, 0 },
2744   { "cmoveS",           { Gv, Ev }, 0 },
2745   { "cmovneS",          { Gv, Ev }, 0 },
2746   { "cmovbeS",          { Gv, Ev }, 0 },
2747   { "cmovaS",           { Gv, Ev }, 0 },
2748   /* 48 */
2749   { "cmovsS",           { Gv, Ev }, 0 },
2750   { "cmovnsS",          { Gv, Ev }, 0 },
2751   { "cmovpS",           { Gv, Ev }, 0 },
2752   { "cmovnpS",          { Gv, Ev }, 0 },
2753   { "cmovlS",           { Gv, Ev }, 0 },
2754   { "cmovgeS",          { Gv, Ev }, 0 },
2755   { "cmovleS",          { Gv, Ev }, 0 },
2756   { "cmovgS",           { Gv, Ev }, 0 },
2757   /* 50 */
2758   { MOD_TABLE (MOD_0F51) },
2759   { PREFIX_TABLE (PREFIX_0F51) },
2760   { PREFIX_TABLE (PREFIX_0F52) },
2761   { PREFIX_TABLE (PREFIX_0F53) },
2762   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2763   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2764   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2765   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2766   /* 58 */
2767   { PREFIX_TABLE (PREFIX_0F58) },
2768   { PREFIX_TABLE (PREFIX_0F59) },
2769   { PREFIX_TABLE (PREFIX_0F5A) },
2770   { PREFIX_TABLE (PREFIX_0F5B) },
2771   { PREFIX_TABLE (PREFIX_0F5C) },
2772   { PREFIX_TABLE (PREFIX_0F5D) },
2773   { PREFIX_TABLE (PREFIX_0F5E) },
2774   { PREFIX_TABLE (PREFIX_0F5F) },
2775   /* 60 */
2776   { PREFIX_TABLE (PREFIX_0F60) },
2777   { PREFIX_TABLE (PREFIX_0F61) },
2778   { PREFIX_TABLE (PREFIX_0F62) },
2779   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2780   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2781   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2782   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2783   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2784   /* 68 */
2785   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2786   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2787   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2788   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2789   { PREFIX_TABLE (PREFIX_0F6C) },
2790   { PREFIX_TABLE (PREFIX_0F6D) },
2791   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2792   { PREFIX_TABLE (PREFIX_0F6F) },
2793   /* 70 */
2794   { PREFIX_TABLE (PREFIX_0F70) },
2795   { REG_TABLE (REG_0F71) },
2796   { REG_TABLE (REG_0F72) },
2797   { REG_TABLE (REG_0F73) },
2798   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2799   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2800   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2801   { "emms",             { XX }, PREFIX_OPCODE },
2802   /* 78 */
2803   { PREFIX_TABLE (PREFIX_0F78) },
2804   { PREFIX_TABLE (PREFIX_0F79) },
2805   { Bad_Opcode },
2806   { Bad_Opcode },
2807   { PREFIX_TABLE (PREFIX_0F7C) },
2808   { PREFIX_TABLE (PREFIX_0F7D) },
2809   { PREFIX_TABLE (PREFIX_0F7E) },
2810   { PREFIX_TABLE (PREFIX_0F7F) },
2811   /* 80 */
2812   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2815   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2817   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2818   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2819   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2820   /* 88 */
2821   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2822   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2823   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2824   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2825   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2826   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2827   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2828   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2829   /* 90 */
2830   { "seto",             { Eb }, 0 },
2831   { "setno",            { Eb }, 0 },
2832   { "setb",             { Eb }, 0 },
2833   { "setae",            { Eb }, 0 },
2834   { "sete",             { Eb }, 0 },
2835   { "setne",            { Eb }, 0 },
2836   { "setbe",            { Eb }, 0 },
2837   { "seta",             { Eb }, 0 },
2838   /* 98 */
2839   { "sets",             { Eb }, 0 },
2840   { "setns",            { Eb }, 0 },
2841   { "setp",             { Eb }, 0 },
2842   { "setnp",            { Eb }, 0 },
2843   { "setl",             { Eb }, 0 },
2844   { "setge",            { Eb }, 0 },
2845   { "setle",            { Eb }, 0 },
2846   { "setg",             { Eb }, 0 },
2847   /* a0 */
2848   { "pushT",            { fs }, 0 },
2849   { "popT",             { fs }, 0 },
2850   { "cpuid",            { XX }, 0 },
2851   { "btS",              { Ev, Gv }, 0 },
2852   { "shldS",            { Ev, Gv, Ib }, 0 },
2853   { "shldS",            { Ev, Gv, CL }, 0 },
2854   { REG_TABLE (REG_0FA6) },
2855   { REG_TABLE (REG_0FA7) },
2856   /* a8 */
2857   { "pushT",            { gs }, 0 },
2858   { "popT",             { gs }, 0 },
2859   { "rsm",              { XX }, 0 },
2860   { "btsS",             { Evh1, Gv }, 0 },
2861   { "shrdS",            { Ev, Gv, Ib }, 0 },
2862   { "shrdS",            { Ev, Gv, CL }, 0 },
2863   { REG_TABLE (REG_0FAE) },
2864   { "imulS",            { Gv, Ev }, 0 },
2865   /* b0 */
2866   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2867   { "cmpxchgS",         { Evh1, Gv }, 0 },
2868   { MOD_TABLE (MOD_0FB2) },
2869   { "btrS",             { Evh1, Gv }, 0 },
2870   { MOD_TABLE (MOD_0FB4) },
2871   { MOD_TABLE (MOD_0FB5) },
2872   { "movz{bR|x}",       { Gv, Eb }, 0 },
2873   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2874   /* b8 */
2875   { PREFIX_TABLE (PREFIX_0FB8) },
2876   { "ud1S",             { Gv, Ev }, 0 },
2877   { REG_TABLE (REG_0FBA) },
2878   { "btcS",             { Evh1, Gv }, 0 },
2879   { PREFIX_TABLE (PREFIX_0FBC) },
2880   { PREFIX_TABLE (PREFIX_0FBD) },
2881   { "movs{bR|x}",       { Gv, Eb }, 0 },
2882   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2883   /* c0 */
2884   { "xaddB",            { Ebh1, Gb }, 0 },
2885   { "xaddS",            { Evh1, Gv }, 0 },
2886   { PREFIX_TABLE (PREFIX_0FC2) },
2887   { MOD_TABLE (MOD_0FC3) },
2888   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2889   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2890   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2891   { REG_TABLE (REG_0FC7) },
2892   /* c8 */
2893   { "bswap",            { RMeAX }, 0 },
2894   { "bswap",            { RMeCX }, 0 },
2895   { "bswap",            { RMeDX }, 0 },
2896   { "bswap",            { RMeBX }, 0 },
2897   { "bswap",            { RMeSP }, 0 },
2898   { "bswap",            { RMeBP }, 0 },
2899   { "bswap",            { RMeSI }, 0 },
2900   { "bswap",            { RMeDI }, 0 },
2901   /* d0 */
2902   { PREFIX_TABLE (PREFIX_0FD0) },
2903   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2904   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2905   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2906   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2907   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2908   { PREFIX_TABLE (PREFIX_0FD6) },
2909   { MOD_TABLE (MOD_0FD7) },
2910   /* d8 */
2911   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2912   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2913   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2914   { "pand",             { MX, EM }, PREFIX_OPCODE },
2915   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2916   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2917   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2918   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2919   /* e0 */
2920   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2921   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2922   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2923   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2924   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2925   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2926   { PREFIX_TABLE (PREFIX_0FE6) },
2927   { PREFIX_TABLE (PREFIX_0FE7) },
2928   /* e8 */
2929   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2930   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2931   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2932   { "por",              { MX, EM }, PREFIX_OPCODE },
2933   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2934   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2935   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2936   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2937   /* f0 */
2938   { PREFIX_TABLE (PREFIX_0FF0) },
2939   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2940   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2941   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2942   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2943   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2944   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2945   { PREFIX_TABLE (PREFIX_0FF7) },
2946   /* f8 */
2947   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2948   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2949   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2950   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2951   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2952   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2953   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2954   { "ud0S",             { Gv, Ev }, 0 },
2955 };
2956
2957 static const unsigned char onebyte_has_modrm[256] = {
2958   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2959   /*       -------------------------------        */
2960   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2961   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2962   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2963   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2964   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2965   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2966   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2967   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2968   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2969   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2970   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2971   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2972   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2973   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2974   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2975   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2976   /*       -------------------------------        */
2977   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2978 };
2979
2980 static const unsigned char twobyte_has_modrm[256] = {
2981   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2982   /*       -------------------------------        */
2983   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2984   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2985   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2986   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2987   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2988   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2989   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2990   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2991   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2992   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2993   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2994   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2995   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2996   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2997   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2998   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2999   /*       -------------------------------        */
3000   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3001 };
3002
3003 static char obuf[100];
3004 static char *obufp;
3005 static char *mnemonicendp;
3006 static char scratchbuf[100];
3007 static unsigned char *start_codep;
3008 static unsigned char *insn_codep;
3009 static unsigned char *codep;
3010 static unsigned char *end_codep;
3011 static int last_lock_prefix;
3012 static int last_repz_prefix;
3013 static int last_repnz_prefix;
3014 static int last_data_prefix;
3015 static int last_addr_prefix;
3016 static int last_rex_prefix;
3017 static int last_seg_prefix;
3018 static int fwait_prefix;
3019 /* The active segment register prefix.  */
3020 static int active_seg_prefix;
3021 #define MAX_CODE_LENGTH 15
3022 /* We can up to 14 prefixes since the maximum instruction length is
3023    15bytes.  */
3024 static int all_prefixes[MAX_CODE_LENGTH - 1];
3025 static disassemble_info *the_info;
3026 static struct
3027   {
3028     int mod;
3029     int reg;
3030     int rm;
3031   }
3032 modrm;
3033 static unsigned char need_modrm;
3034 static struct
3035   {
3036     int scale;
3037     int index;
3038     int base;
3039   }
3040 sib;
3041 static struct
3042   {
3043     int register_specifier;
3044     int length;
3045     int prefix;
3046     int w;
3047     int evex;
3048     int r;
3049     int v;
3050     int mask_register_specifier;
3051     int zeroing;
3052     int ll;
3053     int b;
3054   }
3055 vex;
3056 static unsigned char need_vex;
3057 static unsigned char need_vex_reg;
3058 static unsigned char vex_w_done;
3059
3060 struct op
3061   {
3062     const char *name;
3063     unsigned int len;
3064   };
3065
3066 /* If we are accessing mod/rm/reg without need_modrm set, then the
3067    values are stale.  Hitting this abort likely indicates that you
3068    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3069 #define MODRM_CHECK  if (!need_modrm) abort ()
3070
3071 static const char **names64;
3072 static const char **names32;
3073 static const char **names16;
3074 static const char **names8;
3075 static const char **names8rex;
3076 static const char **names_seg;
3077 static const char *index64;
3078 static const char *index32;
3079 static const char **index16;
3080 static const char **names_bnd;
3081
3082 static const char *intel_names64[] = {
3083   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3084   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3085 };
3086 static const char *intel_names32[] = {
3087   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3088   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3089 };
3090 static const char *intel_names16[] = {
3091   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3092   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3093 };
3094 static const char *intel_names8[] = {
3095   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3096 };
3097 static const char *intel_names8rex[] = {
3098   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3099   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3100 };
3101 static const char *intel_names_seg[] = {
3102   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3103 };
3104 static const char *intel_index64 = "riz";
3105 static const char *intel_index32 = "eiz";
3106 static const char *intel_index16[] = {
3107   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3108 };
3109
3110 static const char *att_names64[] = {
3111   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3112   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3113 };
3114 static const char *att_names32[] = {
3115   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3116   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3117 };
3118 static const char *att_names16[] = {
3119   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3120   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3121 };
3122 static const char *att_names8[] = {
3123   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3124 };
3125 static const char *att_names8rex[] = {
3126   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3127   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3128 };
3129 static const char *att_names_seg[] = {
3130   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3131 };
3132 static const char *att_index64 = "%riz";
3133 static const char *att_index32 = "%eiz";
3134 static const char *att_index16[] = {
3135   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3136 };
3137
3138 static const char **names_mm;
3139 static const char *intel_names_mm[] = {
3140   "mm0", "mm1", "mm2", "mm3",
3141   "mm4", "mm5", "mm6", "mm7"
3142 };
3143 static const char *att_names_mm[] = {
3144   "%mm0", "%mm1", "%mm2", "%mm3",
3145   "%mm4", "%mm5", "%mm6", "%mm7"
3146 };
3147
3148 static const char *intel_names_bnd[] = {
3149   "bnd0", "bnd1", "bnd2", "bnd3"
3150 };
3151
3152 static const char *att_names_bnd[] = {
3153   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3154 };
3155
3156 static const char **names_xmm;
3157 static const char *intel_names_xmm[] = {
3158   "xmm0", "xmm1", "xmm2", "xmm3",
3159   "xmm4", "xmm5", "xmm6", "xmm7",
3160   "xmm8", "xmm9", "xmm10", "xmm11",
3161   "xmm12", "xmm13", "xmm14", "xmm15",
3162   "xmm16", "xmm17", "xmm18", "xmm19",
3163   "xmm20", "xmm21", "xmm22", "xmm23",
3164   "xmm24", "xmm25", "xmm26", "xmm27",
3165   "xmm28", "xmm29", "xmm30", "xmm31"
3166 };
3167 static const char *att_names_xmm[] = {
3168   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3169   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3170   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3171   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3172   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3173   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3174   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3175   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3176 };
3177
3178 static const char **names_ymm;
3179 static const char *intel_names_ymm[] = {
3180   "ymm0", "ymm1", "ymm2", "ymm3",
3181   "ymm4", "ymm5", "ymm6", "ymm7",
3182   "ymm8", "ymm9", "ymm10", "ymm11",
3183   "ymm12", "ymm13", "ymm14", "ymm15",
3184   "ymm16", "ymm17", "ymm18", "ymm19",
3185   "ymm20", "ymm21", "ymm22", "ymm23",
3186   "ymm24", "ymm25", "ymm26", "ymm27",
3187   "ymm28", "ymm29", "ymm30", "ymm31"
3188 };
3189 static const char *att_names_ymm[] = {
3190   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3191   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3192   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3193   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3194   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3195   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3196   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3197   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3198 };
3199
3200 static const char **names_zmm;
3201 static const char *intel_names_zmm[] = {
3202   "zmm0", "zmm1", "zmm2", "zmm3",
3203   "zmm4", "zmm5", "zmm6", "zmm7",
3204   "zmm8", "zmm9", "zmm10", "zmm11",
3205   "zmm12", "zmm13", "zmm14", "zmm15",
3206   "zmm16", "zmm17", "zmm18", "zmm19",
3207   "zmm20", "zmm21", "zmm22", "zmm23",
3208   "zmm24", "zmm25", "zmm26", "zmm27",
3209   "zmm28", "zmm29", "zmm30", "zmm31"
3210 };
3211 static const char *att_names_zmm[] = {
3212   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3213   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3214   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3215   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3216   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3217   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3218   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3219   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3220 };
3221
3222 static const char **names_mask;
3223 static const char *intel_names_mask[] = {
3224   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3225 };
3226 static const char *att_names_mask[] = {
3227   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3228 };
3229
3230 static const char *names_rounding[] =
3231 {
3232   "{rn-sae}",
3233   "{rd-sae}",
3234   "{ru-sae}",
3235   "{rz-sae}"
3236 };
3237
3238 static const struct dis386 reg_table[][8] = {
3239   /* REG_80 */
3240   {
3241     { "addA",   { Ebh1, Ib }, 0 },
3242     { "orA",    { Ebh1, Ib }, 0 },
3243     { "adcA",   { Ebh1, Ib }, 0 },
3244     { "sbbA",   { Ebh1, Ib }, 0 },
3245     { "andA",   { Ebh1, Ib }, 0 },
3246     { "subA",   { Ebh1, Ib }, 0 },
3247     { "xorA",   { Ebh1, Ib }, 0 },
3248     { "cmpA",   { Eb, Ib }, 0 },
3249   },
3250   /* REG_81 */
3251   {
3252     { "addQ",   { Evh1, Iv }, 0 },
3253     { "orQ",    { Evh1, Iv }, 0 },
3254     { "adcQ",   { Evh1, Iv }, 0 },
3255     { "sbbQ",   { Evh1, Iv }, 0 },
3256     { "andQ",   { Evh1, Iv }, 0 },
3257     { "subQ",   { Evh1, Iv }, 0 },
3258     { "xorQ",   { Evh1, Iv }, 0 },
3259     { "cmpQ",   { Ev, Iv }, 0 },
3260   },
3261   /* REG_83 */
3262   {
3263     { "addQ",   { Evh1, sIb }, 0 },
3264     { "orQ",    { Evh1, sIb }, 0 },
3265     { "adcQ",   { Evh1, sIb }, 0 },
3266     { "sbbQ",   { Evh1, sIb }, 0 },
3267     { "andQ",   { Evh1, sIb }, 0 },
3268     { "subQ",   { Evh1, sIb }, 0 },
3269     { "xorQ",   { Evh1, sIb }, 0 },
3270     { "cmpQ",   { Ev, sIb }, 0 },
3271   },
3272   /* REG_8F */
3273   {
3274     { "popU",   { stackEv }, 0 },
3275     { XOP_8F_TABLE (XOP_09) },
3276     { Bad_Opcode },
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { XOP_8F_TABLE (XOP_09) },
3280   },
3281   /* REG_C0 */
3282   {
3283     { "rolA",   { Eb, Ib }, 0 },
3284     { "rorA",   { Eb, Ib }, 0 },
3285     { "rclA",   { Eb, Ib }, 0 },
3286     { "rcrA",   { Eb, Ib }, 0 },
3287     { "shlA",   { Eb, Ib }, 0 },
3288     { "shrA",   { Eb, Ib }, 0 },
3289     { "shlA",   { Eb, Ib }, 0 },
3290     { "sarA",   { Eb, Ib }, 0 },
3291   },
3292   /* REG_C1 */
3293   {
3294     { "rolQ",   { Ev, Ib }, 0 },
3295     { "rorQ",   { Ev, Ib }, 0 },
3296     { "rclQ",   { Ev, Ib }, 0 },
3297     { "rcrQ",   { Ev, Ib }, 0 },
3298     { "shlQ",   { Ev, Ib }, 0 },
3299     { "shrQ",   { Ev, Ib }, 0 },
3300     { "shlQ",   { Ev, Ib }, 0 },
3301     { "sarQ",   { Ev, Ib }, 0 },
3302   },
3303   /* REG_C6 */
3304   {
3305     { "movA",   { Ebh3, Ib }, 0 },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_C6_REG_7) },
3313   },
3314   /* REG_C7 */
3315   {
3316     { "movQ",   { Evh3, Iv }, 0 },
3317     { Bad_Opcode },
3318     { Bad_Opcode },
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { Bad_Opcode },
3322     { Bad_Opcode },
3323     { MOD_TABLE (MOD_C7_REG_7) },
3324   },
3325   /* REG_D0 */
3326   {
3327     { "rolA",   { Eb, I1 }, 0 },
3328     { "rorA",   { Eb, I1 }, 0 },
3329     { "rclA",   { Eb, I1 }, 0 },
3330     { "rcrA",   { Eb, I1 }, 0 },
3331     { "shlA",   { Eb, I1 }, 0 },
3332     { "shrA",   { Eb, I1 }, 0 },
3333     { "shlA",   { Eb, I1 }, 0 },
3334     { "sarA",   { Eb, I1 }, 0 },
3335   },
3336   /* REG_D1 */
3337   {
3338     { "rolQ",   { Ev, I1 }, 0 },
3339     { "rorQ",   { Ev, I1 }, 0 },
3340     { "rclQ",   { Ev, I1 }, 0 },
3341     { "rcrQ",   { Ev, I1 }, 0 },
3342     { "shlQ",   { Ev, I1 }, 0 },
3343     { "shrQ",   { Ev, I1 }, 0 },
3344     { "shlQ",   { Ev, I1 }, 0 },
3345     { "sarQ",   { Ev, I1 }, 0 },
3346   },
3347   /* REG_D2 */
3348   {
3349     { "rolA",   { Eb, CL }, 0 },
3350     { "rorA",   { Eb, CL }, 0 },
3351     { "rclA",   { Eb, CL }, 0 },
3352     { "rcrA",   { Eb, CL }, 0 },
3353     { "shlA",   { Eb, CL }, 0 },
3354     { "shrA",   { Eb, CL }, 0 },
3355     { "shlA",   { Eb, CL }, 0 },
3356     { "sarA",   { Eb, CL }, 0 },
3357   },
3358   /* REG_D3 */
3359   {
3360     { "rolQ",   { Ev, CL }, 0 },
3361     { "rorQ",   { Ev, CL }, 0 },
3362     { "rclQ",   { Ev, CL }, 0 },
3363     { "rcrQ",   { Ev, CL }, 0 },
3364     { "shlQ",   { Ev, CL }, 0 },
3365     { "shrQ",   { Ev, CL }, 0 },
3366     { "shlQ",   { Ev, CL }, 0 },
3367     { "sarQ",   { Ev, CL }, 0 },
3368   },
3369   /* REG_F6 */
3370   {
3371     { "testA",  { Eb, Ib }, 0 },
3372     { "testA",  { Eb, Ib }, 0 },
3373     { "notA",   { Ebh1 }, 0 },
3374     { "negA",   { Ebh1 }, 0 },
3375     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3376     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3377     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3378     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3379   },
3380   /* REG_F7 */
3381   {
3382     { "testQ",  { Ev, Iv }, 0 },
3383     { "testQ",  { Ev, Iv }, 0 },
3384     { "notQ",   { Evh1 }, 0 },
3385     { "negQ",   { Evh1 }, 0 },
3386     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3387     { "imulQ",  { Ev }, 0 },
3388     { "divQ",   { Ev }, 0 },
3389     { "idivQ",  { Ev }, 0 },
3390   },
3391   /* REG_FE */
3392   {
3393     { "incA",   { Ebh1 }, 0 },
3394     { "decA",   { Ebh1 }, 0 },
3395   },
3396   /* REG_FF */
3397   {
3398     { "incQ",   { Evh1 }, 0 },
3399     { "decQ",   { Evh1 }, 0 },
3400     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3401     { MOD_TABLE (MOD_FF_REG_3) },
3402     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3403     { MOD_TABLE (MOD_FF_REG_5) },
3404     { "pushU",  { stackEv }, 0 },
3405     { Bad_Opcode },
3406   },
3407   /* REG_0F00 */
3408   {
3409     { "sldtD",  { Sv }, 0 },
3410     { "strD",   { Sv }, 0 },
3411     { "lldt",   { Ew }, 0 },
3412     { "ltr",    { Ew }, 0 },
3413     { "verr",   { Ew }, 0 },
3414     { "verw",   { Ew }, 0 },
3415     { Bad_Opcode },
3416     { Bad_Opcode },
3417   },
3418   /* REG_0F01 */
3419   {
3420     { MOD_TABLE (MOD_0F01_REG_0) },
3421     { MOD_TABLE (MOD_0F01_REG_1) },
3422     { MOD_TABLE (MOD_0F01_REG_2) },
3423     { MOD_TABLE (MOD_0F01_REG_3) },
3424     { "smswD",  { Sv }, 0 },
3425     { MOD_TABLE (MOD_0F01_REG_5) },
3426     { "lmsw",   { Ew }, 0 },
3427     { MOD_TABLE (MOD_0F01_REG_7) },
3428   },
3429   /* REG_0F0D */
3430   {
3431     { "prefetch",       { Mb }, 0 },
3432     { "prefetchw",      { Mb }, 0 },
3433     { "prefetchwt1",    { Mb }, 0 },
3434     { "prefetch",       { Mb }, 0 },
3435     { "prefetch",       { Mb }, 0 },
3436     { "prefetch",       { Mb }, 0 },
3437     { "prefetch",       { Mb }, 0 },
3438     { "prefetch",       { Mb }, 0 },
3439   },
3440   /* REG_0F18 */
3441   {
3442     { MOD_TABLE (MOD_0F18_REG_0) },
3443     { MOD_TABLE (MOD_0F18_REG_1) },
3444     { MOD_TABLE (MOD_0F18_REG_2) },
3445     { MOD_TABLE (MOD_0F18_REG_3) },
3446     { MOD_TABLE (MOD_0F18_REG_4) },
3447     { MOD_TABLE (MOD_0F18_REG_5) },
3448     { MOD_TABLE (MOD_0F18_REG_6) },
3449     { MOD_TABLE (MOD_0F18_REG_7) },
3450   },
3451   /* REG_0F1C_MOD_0 */
3452   {
3453     { "cldemote",       { Mb }, 0 },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461   },
3462   /* REG_0F1E_MOD_3 */
3463   {
3464     { "nopQ",           { Ev }, 0 },
3465     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3466     { "nopQ",           { Ev }, 0 },
3467     { "nopQ",           { Ev }, 0 },
3468     { "nopQ",           { Ev }, 0 },
3469     { "nopQ",           { Ev }, 0 },
3470     { "nopQ",           { Ev }, 0 },
3471     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3472   },
3473   /* REG_0F71 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F71_REG_2) },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F71_REG_4) },
3480     { Bad_Opcode },
3481     { MOD_TABLE (MOD_0F71_REG_6) },
3482   },
3483   /* REG_0F72 */
3484   {
3485     { Bad_Opcode },
3486     { Bad_Opcode },
3487     { MOD_TABLE (MOD_0F72_REG_2) },
3488     { Bad_Opcode },
3489     { MOD_TABLE (MOD_0F72_REG_4) },
3490     { Bad_Opcode },
3491     { MOD_TABLE (MOD_0F72_REG_6) },
3492   },
3493   /* REG_0F73 */
3494   {
3495     { Bad_Opcode },
3496     { Bad_Opcode },
3497     { MOD_TABLE (MOD_0F73_REG_2) },
3498     { MOD_TABLE (MOD_0F73_REG_3) },
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { MOD_TABLE (MOD_0F73_REG_6) },
3502     { MOD_TABLE (MOD_0F73_REG_7) },
3503   },
3504   /* REG_0FA6 */
3505   {
3506     { "montmul",        { { OP_0f07, 0 } }, 0 },
3507     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3508     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3509   },
3510   /* REG_0FA7 */
3511   {
3512     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3513     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3514     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3515     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3516     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3517     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3518   },
3519   /* REG_0FAE */
3520   {
3521     { MOD_TABLE (MOD_0FAE_REG_0) },
3522     { MOD_TABLE (MOD_0FAE_REG_1) },
3523     { MOD_TABLE (MOD_0FAE_REG_2) },
3524     { MOD_TABLE (MOD_0FAE_REG_3) },
3525     { MOD_TABLE (MOD_0FAE_REG_4) },
3526     { MOD_TABLE (MOD_0FAE_REG_5) },
3527     { MOD_TABLE (MOD_0FAE_REG_6) },
3528     { MOD_TABLE (MOD_0FAE_REG_7) },
3529   },
3530   /* REG_0FBA */
3531   {
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { "btQ",    { Ev, Ib }, 0 },
3537     { "btsQ",   { Evh1, Ib }, 0 },
3538     { "btrQ",   { Evh1, Ib }, 0 },
3539     { "btcQ",   { Evh1, Ib }, 0 },
3540   },
3541   /* REG_0FC7 */
3542   {
3543     { Bad_Opcode },
3544     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_0FC7_REG_3) },
3547     { MOD_TABLE (MOD_0FC7_REG_4) },
3548     { MOD_TABLE (MOD_0FC7_REG_5) },
3549     { MOD_TABLE (MOD_0FC7_REG_6) },
3550     { MOD_TABLE (MOD_0FC7_REG_7) },
3551   },
3552   /* REG_VEX_0F71 */
3553   {
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3559     { Bad_Opcode },
3560     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3561   },
3562   /* REG_VEX_0F72 */
3563   {
3564     { Bad_Opcode },
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3567     { Bad_Opcode },
3568     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3569     { Bad_Opcode },
3570     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3571   },
3572   /* REG_VEX_0F73 */
3573   {
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3577     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3578     { Bad_Opcode },
3579     { Bad_Opcode },
3580     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3581     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3582   },
3583   /* REG_VEX_0FAE */
3584   {
3585     { Bad_Opcode },
3586     { Bad_Opcode },
3587     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3588     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3589   },
3590   /* REG_VEX_0F38F3 */
3591   {
3592     { Bad_Opcode },
3593     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3594     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3595     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3596   },
3597   /* REG_XOP_LWPCB */
3598   {
3599     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3600     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3601   },
3602   /* REG_XOP_LWP */
3603   {
3604     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3605     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3606   },
3607   /* REG_XOP_TBM_01 */
3608   {
3609     { Bad_Opcode },
3610     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3611     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3612     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3613     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3614     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3615     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3616     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3617   },
3618   /* REG_XOP_TBM_02 */
3619   {
3620     { Bad_Opcode },
3621     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3622     { Bad_Opcode },
3623     { Bad_Opcode },
3624     { Bad_Opcode },
3625     { Bad_Opcode },
3626     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3627   },
3628 #define NEED_REG_TABLE
3629 #include "i386-dis-evex.h"
3630 #undef NEED_REG_TABLE
3631 };
3632
3633 static const struct dis386 prefix_table[][4] = {
3634   /* PREFIX_90 */
3635   {
3636     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3637     { "pause", { XX }, 0 },
3638     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3639     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3640   },
3641
3642   /* PREFIX_MOD_0_0F01_REG_5 */
3643   {
3644     { Bad_Opcode },
3645     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3649   {
3650     { Bad_Opcode },
3651     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3655   {
3656     { Bad_Opcode },
3657     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3658   },
3659
3660   /* PREFIX_0F09 */
3661   {
3662     { "wbinvd",   { XX }, 0 },
3663     { "wbnoinvd", { XX }, 0 },
3664   },
3665
3666   /* PREFIX_0F10 */
3667   {
3668     { "movups", { XM, EXx }, PREFIX_OPCODE },
3669     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3670     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3671     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3672   },
3673
3674   /* PREFIX_0F11 */
3675   {
3676     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3677     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3678     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3679     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3680   },
3681
3682   /* PREFIX_0F12 */
3683   {
3684     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3685     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3686     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3687     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3688   },
3689
3690   /* PREFIX_0F16 */
3691   {
3692     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3693     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3694     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F1A */
3698   {
3699     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3700     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3701     { "bndmov", { Gbnd, Ebnd }, 0 },
3702     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3703   },
3704
3705   /* PREFIX_0F1B */
3706   {
3707     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3708     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3709     { "bndmov", { EbndS, Gbnd }, 0 },
3710     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3711   },
3712
3713   /* PREFIX_0F1C */
3714   {
3715     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3716     { "nopQ",   { Ev }, PREFIX_OPCODE },
3717     { "nopQ",   { Ev }, PREFIX_OPCODE },
3718     { "nopQ",   { Ev }, PREFIX_OPCODE },
3719   },
3720
3721   /* PREFIX_0F1E */
3722   {
3723     { "nopQ",   { Ev }, PREFIX_OPCODE },
3724     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3725     { "nopQ",   { Ev }, PREFIX_OPCODE },
3726     { "nopQ",   { Ev }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F2A */
3730   {
3731     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3732     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3733     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3734     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3735   },
3736
3737   /* PREFIX_0F2B */
3738   {
3739     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3741     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3742     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3743   },
3744
3745   /* PREFIX_0F2C */
3746   {
3747     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3748     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3749     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3750     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3751   },
3752
3753   /* PREFIX_0F2D */
3754   {
3755     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3756     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3757     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3758     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3759   },
3760
3761   /* PREFIX_0F2E */
3762   {
3763     { "ucomiss",{ XM, EXd }, 0 },
3764     { Bad_Opcode },
3765     { "ucomisd",{ XM, EXq }, 0 },
3766   },
3767
3768   /* PREFIX_0F2F */
3769   {
3770     { "comiss", { XM, EXd }, 0 },
3771     { Bad_Opcode },
3772     { "comisd", { XM, EXq }, 0 },
3773   },
3774
3775   /* PREFIX_0F51 */
3776   {
3777     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3778     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3779     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3780     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F52 */
3784   {
3785     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3786     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F53 */
3790   {
3791     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3792     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F58 */
3796   {
3797     { "addps", { XM, EXx }, PREFIX_OPCODE },
3798     { "addss", { XM, EXd }, PREFIX_OPCODE },
3799     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3800     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F59 */
3804   {
3805     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3806     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3807     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3808     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F5A */
3812   {
3813     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3814     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3815     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3816     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F5B */
3820   {
3821     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3823     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F5C */
3827   {
3828     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3829     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3830     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3831     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F5D */
3835   {
3836     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3837     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3838     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3839     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F5E */
3843   {
3844     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3845     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3846     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3847     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F5F */
3851   {
3852     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3853     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3854     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3855     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F60 */
3859   {
3860     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3861     { Bad_Opcode },
3862     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F61 */
3866   {
3867     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3868     { Bad_Opcode },
3869     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3870   },
3871
3872   /* PREFIX_0F62 */
3873   {
3874     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3875     { Bad_Opcode },
3876     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F6C */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F6D */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3891   },
3892
3893   /* PREFIX_0F6F */
3894   {
3895     { "movq",   { MX, EM }, PREFIX_OPCODE },
3896     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3897     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3898   },
3899
3900   /* PREFIX_0F70 */
3901   {
3902     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3903     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3905     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F73_REG_3 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "psrldq", { XS, Ib }, 0 },
3913   },
3914
3915   /* PREFIX_0F73_REG_7 */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "pslldq", { XS, Ib }, 0 },
3920   },
3921
3922   /* PREFIX_0F78 */
3923   {
3924     {"vmread",  { Em, Gm }, 0 },
3925     { Bad_Opcode },
3926     {"extrq",   { XS, Ib, Ib }, 0 },
3927     {"insertq", { XM, XS, Ib, Ib }, 0 },
3928   },
3929
3930   /* PREFIX_0F79 */
3931   {
3932     {"vmwrite", { Gm, Em }, 0 },
3933     { Bad_Opcode },
3934     {"extrq",   { XM, XS }, 0 },
3935     {"insertq", { XM, XS }, 0 },
3936   },
3937
3938   /* PREFIX_0F7C */
3939   {
3940     { Bad_Opcode },
3941     { Bad_Opcode },
3942     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3943     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0F7D */
3947   {
3948     { Bad_Opcode },
3949     { Bad_Opcode },
3950     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3951     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0F7E */
3955   {
3956     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3957     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3958     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3959   },
3960
3961   /* PREFIX_0F7F */
3962   {
3963     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3964     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3965     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3966   },
3967
3968   /* PREFIX_0FAE_REG_0 */
3969   {
3970     { Bad_Opcode },
3971     { "rdfsbase", { Ev }, 0 },
3972   },
3973
3974   /* PREFIX_0FAE_REG_1 */
3975   {
3976     { Bad_Opcode },
3977     { "rdgsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_2 */
3981   {
3982     { Bad_Opcode },
3983     { "wrfsbase", { Ev }, 0 },
3984   },
3985
3986   /* PREFIX_0FAE_REG_3 */
3987   {
3988     { Bad_Opcode },
3989     { "wrgsbase", { Ev }, 0 },
3990   },
3991
3992   /* PREFIX_MOD_0_0FAE_REG_4 */
3993   {
3994     { "xsave",  { FXSAVE }, 0 },
3995     { "ptwrite%LQ", { Edq }, 0 },
3996   },
3997
3998   /* PREFIX_MOD_3_0FAE_REG_4 */
3999   {
4000     { Bad_Opcode },
4001     { "ptwrite%LQ", { Edq }, 0 },
4002   },
4003
4004   /* PREFIX_MOD_0_0FAE_REG_5 */
4005   {
4006     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4007   },
4008
4009   /* PREFIX_MOD_3_0FAE_REG_5 */
4010   {
4011     { "lfence",         { Skip_MODRM }, 0 },
4012     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_MOD_0_0FAE_REG_6 */
4016   {
4017     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4018     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4019     { "clwb",   { Mb }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_MOD_1_0FAE_REG_6 */
4023   {
4024     { RM_TABLE (RM_0FAE_REG_6) },
4025     { "umonitor",       { Eva }, PREFIX_OPCODE },
4026     { "tpause", { Edq }, PREFIX_OPCODE },
4027     { "umwait", { Edq }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0FAE_REG_7 */
4031   {
4032     { "clflush",        { Mb }, 0 },
4033     { Bad_Opcode },
4034     { "clflushopt",     { Mb }, 0 },
4035   },
4036
4037   /* PREFIX_0FB8 */
4038   {
4039     { Bad_Opcode },
4040     { "popcntS", { Gv, Ev }, 0 },
4041   },
4042
4043   /* PREFIX_0FBC */
4044   {
4045     { "bsfS",   { Gv, Ev }, 0 },
4046     { "tzcntS", { Gv, Ev }, 0 },
4047     { "bsfS",   { Gv, Ev }, 0 },
4048   },
4049
4050   /* PREFIX_0FBD */
4051   {
4052     { "bsrS",   { Gv, Ev }, 0 },
4053     { "lzcntS", { Gv, Ev }, 0 },
4054     { "bsrS",   { Gv, Ev }, 0 },
4055   },
4056
4057   /* PREFIX_0FC2 */
4058   {
4059     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4060     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4061     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4062     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4063   },
4064
4065   /* PREFIX_MOD_0_0FC3 */
4066   {
4067     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4068   },
4069
4070   /* PREFIX_MOD_0_0FC7_REG_6 */
4071   {
4072     { "vmptrld",{ Mq }, 0 },
4073     { "vmxon",  { Mq }, 0 },
4074     { "vmclear",{ Mq }, 0 },
4075   },
4076
4077   /* PREFIX_MOD_3_0FC7_REG_6 */
4078   {
4079     { "rdrand", { Ev }, 0 },
4080     { Bad_Opcode },
4081     { "rdrand", { Ev }, 0 }
4082   },
4083
4084   /* PREFIX_MOD_3_0FC7_REG_7 */
4085   {
4086     { "rdseed", { Ev }, 0 },
4087     { "rdpid",  { Em }, 0 },
4088     { "rdseed", { Ev }, 0 },
4089   },
4090
4091   /* PREFIX_0FD0 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "addsubpd", { XM, EXx }, 0 },
4096     { "addsubps", { XM, EXx }, 0 },
4097   },
4098
4099   /* PREFIX_0FD6 */
4100   {
4101     { Bad_Opcode },
4102     { "movq2dq",{ XM, MS }, 0 },
4103     { "movq",   { EXqS, XM }, 0 },
4104     { "movdq2q",{ MX, XS }, 0 },
4105   },
4106
4107   /* PREFIX_0FE6 */
4108   {
4109     { Bad_Opcode },
4110     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4111     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4112     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0FE7 */
4116   {
4117     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4118     { Bad_Opcode },
4119     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4120   },
4121
4122   /* PREFIX_0FF0 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4128   },
4129
4130   /* PREFIX_0FF7 */
4131   {
4132     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4133     { Bad_Opcode },
4134     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F3810 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0F3814 */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0F3815 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4156   },
4157
4158   /* PREFIX_0F3817 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4163   },
4164
4165   /* PREFIX_0F3820 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4170   },
4171
4172   /* PREFIX_0F3821 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4177   },
4178
4179   /* PREFIX_0F3822 */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_0F3823 */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4191   },
4192
4193   /* PREFIX_0F3824 */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4198   },
4199
4200   /* PREFIX_0F3825 */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4205   },
4206
4207   /* PREFIX_0F3828 */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4212   },
4213
4214   /* PREFIX_0F3829 */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4219   },
4220
4221   /* PREFIX_0F382A */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4226   },
4227
4228   /* PREFIX_0F382B */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0F3830 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4240   },
4241
4242   /* PREFIX_0F3831 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F3832 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4254   },
4255
4256   /* PREFIX_0F3833 */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4261   },
4262
4263   /* PREFIX_0F3834 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4268   },
4269
4270   /* PREFIX_0F3835 */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4275   },
4276
4277   /* PREFIX_0F3837 */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4282   },
4283
4284   /* PREFIX_0F3838 */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4289   },
4290
4291   /* PREFIX_0F3839 */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F383A */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F383B */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F383C */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F383D */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F383E */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F383F */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3840 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3841 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3880 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F3881 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F3882 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38C8 */
4376   {
4377     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38C9 */
4381   {
4382     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F38CA */
4386   {
4387     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38CB */
4391   {
4392     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38CC */
4396   {
4397     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F38CD */
4401   {
4402     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F38CF */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F38DB */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F38DC */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F38DD */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38DE */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F38DF */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F38F0 */
4448   {
4449     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4450     { Bad_Opcode },
4451     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4452     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F38F1 */
4456   {
4457     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4458     { Bad_Opcode },
4459     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4460     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4461   },
4462
4463   /* PREFIX_0F38F5 */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4468   },
4469
4470   /* PREFIX_0F38F6 */
4471   {
4472     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4473     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4474     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4475     { Bad_Opcode },
4476   },
4477
4478   /* PREFIX_0F38F8 */
4479   {
4480     { Bad_Opcode },
4481     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4482     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4483     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4484   },
4485
4486   /* PREFIX_0F38F9 */
4487   {
4488     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4489   },
4490
4491   /* PREFIX_0F3A08 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F3A09 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F3A0A */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3A0B */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A0C */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3A0D */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A0E */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A14 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A15 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A16 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A17 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A20 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A21 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A22 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A40 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A41 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3A42 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3A44 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_0F3A60 */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F3A61 */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F3A62 */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F3A63 */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F3ACC */
4646   {
4647     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3ACE */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3ACF */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3ADF */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_VEX_0F10 */
4672   {
4673     { "vmovups",        { XM, EXx }, 0 },
4674     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4675     { "vmovupd",        { XM, EXx }, 0 },
4676     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4677   },
4678
4679   /* PREFIX_VEX_0F11 */
4680   {
4681     { "vmovups",        { EXxS, XM }, 0 },
4682     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4683     { "vmovupd",        { EXxS, XM }, 0 },
4684     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4685   },
4686
4687   /* PREFIX_VEX_0F12 */
4688   {
4689     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4690     { "vmovsldup",      { XM, EXx }, 0 },
4691     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4692     { "vmovddup",       { XM, EXymmq }, 0 },
4693   },
4694
4695   /* PREFIX_VEX_0F16 */
4696   {
4697     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4698     { "vmovshdup",      { XM, EXx }, 0 },
4699     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4700   },
4701
4702   /* PREFIX_VEX_0F2A */
4703   {
4704     { Bad_Opcode },
4705     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4708   },
4709
4710   /* PREFIX_VEX_0F2C */
4711   {
4712     { Bad_Opcode },
4713     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4714     { Bad_Opcode },
4715     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4716   },
4717
4718   /* PREFIX_VEX_0F2D */
4719   {
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4722     { Bad_Opcode },
4723     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4724   },
4725
4726   /* PREFIX_VEX_0F2E */
4727   {
4728     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4729     { Bad_Opcode },
4730     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4731   },
4732
4733   /* PREFIX_VEX_0F2F */
4734   {
4735     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4736     { Bad_Opcode },
4737     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4738   },
4739
4740   /* PREFIX_VEX_0F41 */
4741   {
4742     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F42 */
4748   {
4749     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F44 */
4755   {
4756     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F45 */
4762   {
4763     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F46 */
4769   {
4770     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4771     { Bad_Opcode },
4772     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F47 */
4776   {
4777     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4778     { Bad_Opcode },
4779     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F4A */
4783   {
4784     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4785     { Bad_Opcode },
4786     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F4B */
4790   {
4791     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4792     { Bad_Opcode },
4793     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4794   },
4795
4796   /* PREFIX_VEX_0F51 */
4797   {
4798     { "vsqrtps",        { XM, EXx }, 0 },
4799     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4800     { "vsqrtpd",        { XM, EXx }, 0 },
4801     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F52 */
4805   {
4806     { "vrsqrtps",       { XM, EXx }, 0 },
4807     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F53 */
4811   {
4812     { "vrcpps",         { XM, EXx }, 0 },
4813     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4814   },
4815
4816   /* PREFIX_VEX_0F58 */
4817   {
4818     { "vaddps",         { XM, Vex, EXx }, 0 },
4819     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4820     { "vaddpd",         { XM, Vex, EXx }, 0 },
4821     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4822   },
4823
4824   /* PREFIX_VEX_0F59 */
4825   {
4826     { "vmulps",         { XM, Vex, EXx }, 0 },
4827     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4828     { "vmulpd",         { XM, Vex, EXx }, 0 },
4829     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4830   },
4831
4832   /* PREFIX_VEX_0F5A */
4833   {
4834     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4835     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4836     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4837     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4838   },
4839
4840   /* PREFIX_VEX_0F5B */
4841   {
4842     { "vcvtdq2ps",      { XM, EXx }, 0 },
4843     { "vcvttps2dq",     { XM, EXx }, 0 },
4844     { "vcvtps2dq",      { XM, EXx }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F5C */
4848   {
4849     { "vsubps",         { XM, Vex, EXx }, 0 },
4850     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4851     { "vsubpd",         { XM, Vex, EXx }, 0 },
4852     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F5D */
4856   {
4857     { "vminps",         { XM, Vex, EXx }, 0 },
4858     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4859     { "vminpd",         { XM, Vex, EXx }, 0 },
4860     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F5E */
4864   {
4865     { "vdivps",         { XM, Vex, EXx }, 0 },
4866     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4867     { "vdivpd",         { XM, Vex, EXx }, 0 },
4868     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F5F */
4872   {
4873     { "vmaxps",         { XM, Vex, EXx }, 0 },
4874     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4875     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4876     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F60 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4884   },
4885
4886   /* PREFIX_VEX_0F61 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4891   },
4892
4893   /* PREFIX_VEX_0F62 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4898   },
4899
4900   /* PREFIX_VEX_0F63 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4905   },
4906
4907   /* PREFIX_VEX_0F64 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4912   },
4913
4914   /* PREFIX_VEX_0F65 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4919   },
4920
4921   /* PREFIX_VEX_0F66 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4926   },
4927
4928   /* PREFIX_VEX_0F67 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4933   },
4934
4935   /* PREFIX_VEX_0F68 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4940   },
4941
4942   /* PREFIX_VEX_0F69 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4947   },
4948
4949   /* PREFIX_VEX_0F6A */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F6B */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F6C */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F6D */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F6E */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F6F */
4985   {
4986     { Bad_Opcode },
4987     { "vmovdqu",        { XM, EXx }, 0 },
4988     { "vmovdqa",        { XM, EXx }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F70 */
4992   {
4993     { Bad_Opcode },
4994     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4995     { "vpshufd",        { XM, EXx, Ib }, 0 },
4996     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4997   },
4998
4999   /* PREFIX_VEX_0F71_REG_2 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5004   },
5005
5006   /* PREFIX_VEX_0F71_REG_4 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { "vpsraw",         { Vex, XS, Ib }, 0 },
5011   },
5012
5013   /* PREFIX_VEX_0F71_REG_6 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { "vpsllw",         { Vex, XS, Ib }, 0 },
5018   },
5019
5020   /* PREFIX_VEX_0F72_REG_2 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { "vpsrld",         { Vex, XS, Ib }, 0 },
5025   },
5026
5027   /* PREFIX_VEX_0F72_REG_4 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { "vpsrad",         { Vex, XS, Ib }, 0 },
5032   },
5033
5034   /* PREFIX_VEX_0F72_REG_6 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { "vpslld",         { Vex, XS, Ib }, 0 },
5039   },
5040
5041   /* PREFIX_VEX_0F73_REG_2 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5046   },
5047
5048   /* PREFIX_VEX_0F73_REG_3 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5053   },
5054
5055   /* PREFIX_VEX_0F73_REG_6 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { "vpsllq",         { Vex, XS, Ib }, 0 },
5060   },
5061
5062   /* PREFIX_VEX_0F73_REG_7 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { "vpslldq",        { Vex, XS, Ib }, 0 },
5067   },
5068
5069   /* PREFIX_VEX_0F74 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5074   },
5075
5076   /* PREFIX_VEX_0F75 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5081   },
5082
5083   /* PREFIX_VEX_0F76 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5088   },
5089
5090   /* PREFIX_VEX_0F77 */
5091   {
5092     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5093   },
5094
5095   /* PREFIX_VEX_0F7C */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5100     { "vhaddps",        { XM, Vex, EXx }, 0 },
5101   },
5102
5103   /* PREFIX_VEX_0F7D */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5108     { "vhsubps",        { XM, Vex, EXx }, 0 },
5109   },
5110
5111   /* PREFIX_VEX_0F7E */
5112   {
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5115     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F7F */
5119   {
5120     { Bad_Opcode },
5121     { "vmovdqu",        { EXxS, XM }, 0 },
5122     { "vmovdqa",        { EXxS, XM }, 0 },
5123   },
5124
5125   /* PREFIX_VEX_0F90 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F91 */
5133   {
5134     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F92 */
5140   {
5141     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5144     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5145   },
5146
5147   /* PREFIX_VEX_0F93 */
5148   {
5149     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5152     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5153   },
5154
5155   /* PREFIX_VEX_0F98 */
5156   {
5157     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5158     { Bad_Opcode },
5159     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0F99 */
5163   {
5164     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5165     { Bad_Opcode },
5166     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0FC2 */
5170   {
5171     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5172     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5173     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5174     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FC4 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0FC5 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FD0 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5196     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5197   },
5198
5199   /* PREFIX_VEX_0FD1 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5204   },
5205
5206   /* PREFIX_VEX_0FD2 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5211   },
5212
5213   /* PREFIX_VEX_0FD3 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5218   },
5219
5220   /* PREFIX_VEX_0FD4 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { "vpaddq",         { XM, Vex, EXx }, 0 },
5225   },
5226
5227   /* PREFIX_VEX_0FD5 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { "vpmullw",        { XM, Vex, EXx }, 0 },
5232   },
5233
5234   /* PREFIX_VEX_0FD6 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0FD7 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5246   },
5247
5248   /* PREFIX_VEX_0FD8 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5253   },
5254
5255   /* PREFIX_VEX_0FD9 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5260   },
5261
5262   /* PREFIX_VEX_0FDA */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { "vpminub",        { XM, Vex, EXx }, 0 },
5267   },
5268
5269   /* PREFIX_VEX_0FDB */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { "vpand",          { XM, Vex, EXx }, 0 },
5274   },
5275
5276   /* PREFIX_VEX_0FDC */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5281   },
5282
5283   /* PREFIX_VEX_0FDD */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5288   },
5289
5290   /* PREFIX_VEX_0FDE */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5295   },
5296
5297   /* PREFIX_VEX_0FDF */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { "vpandn",         { XM, Vex, EXx }, 0 },
5302   },
5303
5304   /* PREFIX_VEX_0FE0 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { "vpavgb",         { XM, Vex, EXx }, 0 },
5309   },
5310
5311   /* PREFIX_VEX_0FE1 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5316   },
5317
5318   /* PREFIX_VEX_0FE2 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5323   },
5324
5325   /* PREFIX_VEX_0FE3 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpavgw",         { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FE4 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5337   },
5338
5339   /* PREFIX_VEX_0FE5 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FE6 */
5347   {
5348     { Bad_Opcode },
5349     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5350     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5351     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FE7 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FE8 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5366   },
5367
5368   /* PREFIX_VEX_0FE9 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5373   },
5374
5375   /* PREFIX_VEX_0FEA */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vpminsw",        { XM, Vex, EXx }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0FEB */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vpor",           { XM, Vex, EXx }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0FEC */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FED */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FEE */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FEF */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpxor",          { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF0 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5423   },
5424
5425   /* PREFIX_VEX_0FF1 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5430   },
5431
5432   /* PREFIX_VEX_0FF2 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5437   },
5438
5439   /* PREFIX_VEX_0FF3 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5444   },
5445
5446   /* PREFIX_VEX_0FF4 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5451   },
5452
5453   /* PREFIX_VEX_0FF5 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5458   },
5459
5460   /* PREFIX_VEX_0FF6 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5465   },
5466
5467   /* PREFIX_VEX_0FF7 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0FF8 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { "vpsubb",         { XM, Vex, EXx }, 0 },
5479   },
5480
5481   /* PREFIX_VEX_0FF9 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { "vpsubw",         { XM, Vex, EXx }, 0 },
5486   },
5487
5488   /* PREFIX_VEX_0FFA */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { "vpsubd",         { XM, Vex, EXx }, 0 },
5493   },
5494
5495   /* PREFIX_VEX_0FFB */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { "vpsubq",         { XM, Vex, EXx }, 0 },
5500   },
5501
5502   /* PREFIX_VEX_0FFC */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { "vpaddb",         { XM, Vex, EXx }, 0 },
5507   },
5508
5509   /* PREFIX_VEX_0FFD */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { "vpaddw",         { XM, Vex, EXx }, 0 },
5514   },
5515
5516   /* PREFIX_VEX_0FFE */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { "vpaddd",         { XM, Vex, EXx }, 0 },
5521   },
5522
5523   /* PREFIX_VEX_0F3800 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { "vpshufb",        { XM, Vex, EXx }, 0 },
5528   },
5529
5530   /* PREFIX_VEX_0F3801 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { "vphaddw",        { XM, Vex, EXx }, 0 },
5535   },
5536
5537   /* PREFIX_VEX_0F3802 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { "vphaddd",        { XM, Vex, EXx }, 0 },
5542   },
5543
5544   /* PREFIX_VEX_0F3803 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5549   },
5550
5551   /* PREFIX_VEX_0F3804 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5556   },
5557
5558   /* PREFIX_VEX_0F3805 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { "vphsubw",        { XM, Vex, EXx }, 0 },
5563   },
5564
5565   /* PREFIX_VEX_0F3806 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { "vphsubd",        { XM, Vex, EXx }, 0 },
5570   },
5571
5572   /* PREFIX_VEX_0F3807 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5577   },
5578
5579   /* PREFIX_VEX_0F3808 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { "vpsignb",        { XM, Vex, EXx }, 0 },
5584   },
5585
5586   /* PREFIX_VEX_0F3809 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { "vpsignw",        { XM, Vex, EXx }, 0 },
5591   },
5592
5593   /* PREFIX_VEX_0F380A */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { "vpsignd",        { XM, Vex, EXx }, 0 },
5598   },
5599
5600   /* PREFIX_VEX_0F380B */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5605   },
5606
5607   /* PREFIX_VEX_0F380C */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F380D */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F380E */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F380F */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F3813 */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5640   },
5641
5642   /* PREFIX_VEX_0F3816 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5647   },
5648
5649   /* PREFIX_VEX_0F3817 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { "vptest",         { XM, EXx }, 0 },
5654   },
5655
5656   /* PREFIX_VEX_0F3818 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F3819 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F381A */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F381C */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { "vpabsb",         { XM, EXx }, 0 },
5682   },
5683
5684   /* PREFIX_VEX_0F381D */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { "vpabsw",         { XM, EXx }, 0 },
5689   },
5690
5691   /* PREFIX_VEX_0F381E */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { "vpabsd",         { XM, EXx }, 0 },
5696   },
5697
5698   /* PREFIX_VEX_0F3820 */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5703   },
5704
5705   /* PREFIX_VEX_0F3821 */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5710   },
5711
5712   /* PREFIX_VEX_0F3822 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5717   },
5718
5719   /* PREFIX_VEX_0F3823 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5724   },
5725
5726   /* PREFIX_VEX_0F3824 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5731   },
5732
5733   /* PREFIX_VEX_0F3825 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5738   },
5739
5740   /* PREFIX_VEX_0F3828 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5745   },
5746
5747   /* PREFIX_VEX_0F3829 */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5752   },
5753
5754   /* PREFIX_VEX_0F382A */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F382B */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5766   },
5767
5768   /* PREFIX_VEX_0F382C */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F382D */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F382E */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5787   },
5788
5789   /* PREFIX_VEX_0F382F */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5794   },
5795
5796   /* PREFIX_VEX_0F3830 */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5801   },
5802
5803   /* PREFIX_VEX_0F3831 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5808   },
5809
5810   /* PREFIX_VEX_0F3832 */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5815   },
5816
5817   /* PREFIX_VEX_0F3833 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5822   },
5823
5824   /* PREFIX_VEX_0F3834 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5829   },
5830
5831   /* PREFIX_VEX_0F3835 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5836   },
5837
5838   /* PREFIX_VEX_0F3836 */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5843   },
5844
5845   /* PREFIX_VEX_0F3837 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5850   },
5851
5852   /* PREFIX_VEX_0F3838 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { "vpminsb",        { XM, Vex, EXx }, 0 },
5857   },
5858
5859   /* PREFIX_VEX_0F3839 */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { "vpminsd",        { XM, Vex, EXx }, 0 },
5864   },
5865
5866   /* PREFIX_VEX_0F383A */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { "vpminuw",        { XM, Vex, EXx }, 0 },
5871   },
5872
5873   /* PREFIX_VEX_0F383B */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { "vpminud",        { XM, Vex, EXx }, 0 },
5878   },
5879
5880   /* PREFIX_VEX_0F383C */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5885   },
5886
5887   /* PREFIX_VEX_0F383D */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5892   },
5893
5894   /* PREFIX_VEX_0F383E */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5899   },
5900
5901   /* PREFIX_VEX_0F383F */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5906   },
5907
5908   /* PREFIX_VEX_0F3840 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { "vpmulld",        { XM, Vex, EXx }, 0 },
5913   },
5914
5915   /* PREFIX_VEX_0F3841 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F3845 */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5927   },
5928
5929   /* PREFIX_VEX_0F3846 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5934   },
5935
5936   /* PREFIX_VEX_0F3847 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5941   },
5942
5943   /* PREFIX_VEX_0F3858 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5948   },
5949
5950   /* PREFIX_VEX_0F3859 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F385A */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5962   },
5963
5964   /* PREFIX_VEX_0F3878 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F3879 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F388C */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F388E */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F3890 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F3891 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3892 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F3893 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3896 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3897 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F3898 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F3899 */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F389A */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F389B */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F389C */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389D */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F389E */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F389F */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38A6 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6095     { Bad_Opcode },
6096   },
6097
6098   /* PREFIX_VEX_0F38A7 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38A8 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38A9 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38AA */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38AB */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38AC */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AD */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38AE */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38AF */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38B6 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38B7 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38B8 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38B9 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38BA */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38BB */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38BC */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BD */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38BE */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38BF */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F38CF */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6236   },
6237
6238   /* PREFIX_VEX_0F38DB */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6243   },
6244
6245   /* PREFIX_VEX_0F38DC */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vaesenc",        { XM, Vex, EXx }, 0 },
6250   },
6251
6252   /* PREFIX_VEX_0F38DD */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6257   },
6258
6259   /* PREFIX_VEX_0F38DE */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { "vaesdec",        { XM, Vex, EXx }, 0 },
6264   },
6265
6266   /* PREFIX_VEX_0F38DF */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6271   },
6272
6273   /* PREFIX_VEX_0F38F2 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6276   },
6277
6278   /* PREFIX_VEX_0F38F3_REG_1 */
6279   {
6280     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6281   },
6282
6283   /* PREFIX_VEX_0F38F3_REG_2 */
6284   {
6285     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6286   },
6287
6288   /* PREFIX_VEX_0F38F3_REG_3 */
6289   {
6290     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6291   },
6292
6293   /* PREFIX_VEX_0F38F5 */
6294   {
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6297     { Bad_Opcode },
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6299   },
6300
6301   /* PREFIX_VEX_0F38F6 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6307   },
6308
6309   /* PREFIX_VEX_0F38F7 */
6310   {
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A00 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A01 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A02 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A04 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A05 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A06 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A08 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { "vroundps",       { XM, EXx, Ib }, 0 },
6364   },
6365
6366   /* PREFIX_VEX_0F3A09 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vroundpd",       { XM, EXx, Ib }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F3A0A */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F3A0B */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0C */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0D */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F3A0E */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6406   },
6407
6408   /* PREFIX_VEX_0F3A0F */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6413   },
6414
6415   /* PREFIX_VEX_0F3A14 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A15 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A16 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A17 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A18 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A19 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A1D */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6462   },
6463
6464   /* PREFIX_VEX_0F3A20 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A21 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A22 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A30 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A31 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A32 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A33 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A38 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A39 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A40 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6532   },
6533
6534   /* PREFIX_VEX_0F3A41 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A42 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6546   },
6547
6548   /* PREFIX_VEX_0F3A44 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6553   },
6554
6555   /* PREFIX_VEX_0F3A46 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A48 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A49 */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A4A */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A4B */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A4C */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A5C */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6602   },
6603
6604   /* PREFIX_VEX_0F3A5D */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6609   },
6610
6611   /* PREFIX_VEX_0F3A5E */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A5F */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A60 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6630     { Bad_Opcode },
6631   },
6632
6633   /* PREFIX_VEX_0F3A61 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A62 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A63 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A68 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6659   },
6660
6661   /* PREFIX_VEX_0F3A69 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6666   },
6667
6668   /* PREFIX_VEX_0F3A6A */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A6B */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6C */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6D */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6694   },
6695
6696   /* PREFIX_VEX_0F3A6E */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A6F */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6708   },
6709
6710   /* PREFIX_VEX_0F3A78 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A79 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7A */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7B */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7C */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6743     { Bad_Opcode },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7D */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6751   },
6752
6753   /* PREFIX_VEX_0F3A7E */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6758   },
6759
6760   /* PREFIX_VEX_0F3A7F */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6765   },
6766
6767   /* PREFIX_VEX_0F3ACE */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3ACF */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3ADF */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3AF0 */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6794   },
6795
6796 #define NEED_PREFIX_TABLE
6797 #include "i386-dis-evex.h"
6798 #undef NEED_PREFIX_TABLE
6799 };
6800
6801 static const struct dis386 x86_64_table[][2] = {
6802   /* X86_64_06 */
6803   {
6804     { "pushP", { es }, 0 },
6805   },
6806
6807   /* X86_64_07 */
6808   {
6809     { "popP", { es }, 0 },
6810   },
6811
6812   /* X86_64_0D */
6813   {
6814     { "pushP", { cs }, 0 },
6815   },
6816
6817   /* X86_64_16 */
6818   {
6819     { "pushP", { ss }, 0 },
6820   },
6821
6822   /* X86_64_17 */
6823   {
6824     { "popP", { ss }, 0 },
6825   },
6826
6827   /* X86_64_1E */
6828   {
6829     { "pushP", { ds }, 0 },
6830   },
6831
6832   /* X86_64_1F */
6833   {
6834     { "popP", { ds }, 0 },
6835   },
6836
6837   /* X86_64_27 */
6838   {
6839     { "daa", { XX }, 0 },
6840   },
6841
6842   /* X86_64_2F */
6843   {
6844     { "das", { XX }, 0 },
6845   },
6846
6847   /* X86_64_37 */
6848   {
6849     { "aaa", { XX }, 0 },
6850   },
6851
6852   /* X86_64_3F */
6853   {
6854     { "aas", { XX }, 0 },
6855   },
6856
6857   /* X86_64_60 */
6858   {
6859     { "pushaP", { XX }, 0 },
6860   },
6861
6862   /* X86_64_61 */
6863   {
6864     { "popaP", { XX }, 0 },
6865   },
6866
6867   /* X86_64_62 */
6868   {
6869     { MOD_TABLE (MOD_62_32BIT) },
6870     { EVEX_TABLE (EVEX_0F) },
6871   },
6872
6873   /* X86_64_63 */
6874   {
6875     { "arpl", { Ew, Gw }, 0 },
6876     { "movs{lq|xd}", { Gv, Ed }, 0 },
6877   },
6878
6879   /* X86_64_6D */
6880   {
6881     { "ins{R|}", { Yzr, indirDX }, 0 },
6882     { "ins{G|}", { Yzr, indirDX }, 0 },
6883   },
6884
6885   /* X86_64_6F */
6886   {
6887     { "outs{R|}", { indirDXr, Xz }, 0 },
6888     { "outs{G|}", { indirDXr, Xz }, 0 },
6889   },
6890
6891   /* X86_64_82 */
6892   {
6893     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6894     { REG_TABLE (REG_80) },
6895   },
6896
6897   /* X86_64_9A */
6898   {
6899     { "Jcall{T|}", { Ap }, 0 },
6900   },
6901
6902   /* X86_64_C4 */
6903   {
6904     { MOD_TABLE (MOD_C4_32BIT) },
6905     { VEX_C4_TABLE (VEX_0F) },
6906   },
6907
6908   /* X86_64_C5 */
6909   {
6910     { MOD_TABLE (MOD_C5_32BIT) },
6911     { VEX_C5_TABLE (VEX_0F) },
6912   },
6913
6914   /* X86_64_CE */
6915   {
6916     { "into", { XX }, 0 },
6917   },
6918
6919   /* X86_64_D4 */
6920   {
6921     { "aam", { Ib }, 0 },
6922   },
6923
6924   /* X86_64_D5 */
6925   {
6926     { "aad", { Ib }, 0 },
6927   },
6928
6929   /* X86_64_E8 */
6930   {
6931     { "callP",          { Jv, BND }, 0 },
6932     { "call@",          { Jv, BND }, 0 }
6933   },
6934
6935   /* X86_64_E9 */
6936   {
6937     { "jmpP",           { Jv, BND }, 0 },
6938     { "jmp@",           { Jv, BND }, 0 }
6939   },
6940
6941   /* X86_64_EA */
6942   {
6943     { "Jjmp{T|}", { Ap }, 0 },
6944   },
6945
6946   /* X86_64_0F01_REG_0 */
6947   {
6948     { "sgdt{Q|IQ}", { M }, 0 },
6949     { "sgdt", { M }, 0 },
6950   },
6951
6952   /* X86_64_0F01_REG_1 */
6953   {
6954     { "sidt{Q|IQ}", { M }, 0 },
6955     { "sidt", { M }, 0 },
6956   },
6957
6958   /* X86_64_0F01_REG_2 */
6959   {
6960     { "lgdt{Q|Q}", { M }, 0 },
6961     { "lgdt", { M }, 0 },
6962   },
6963
6964   /* X86_64_0F01_REG_3 */
6965   {
6966     { "lidt{Q|Q}", { M }, 0 },
6967     { "lidt", { M }, 0 },
6968   },
6969 };
6970
6971 static const struct dis386 three_byte_table[][256] = {
6972
6973   /* THREE_BYTE_0F38 */
6974   {
6975     /* 00 */
6976     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6978     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6979     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6980     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6981     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6982     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6983     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6984     /* 08 */
6985     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6986     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6987     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6988     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 10 */
6994     { PREFIX_TABLE (PREFIX_0F3810) },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { PREFIX_TABLE (PREFIX_0F3814) },
6999     { PREFIX_TABLE (PREFIX_0F3815) },
7000     { Bad_Opcode },
7001     { PREFIX_TABLE (PREFIX_0F3817) },
7002     /* 18 */
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7008     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7009     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7010     { Bad_Opcode },
7011     /* 20 */
7012     { PREFIX_TABLE (PREFIX_0F3820) },
7013     { PREFIX_TABLE (PREFIX_0F3821) },
7014     { PREFIX_TABLE (PREFIX_0F3822) },
7015     { PREFIX_TABLE (PREFIX_0F3823) },
7016     { PREFIX_TABLE (PREFIX_0F3824) },
7017     { PREFIX_TABLE (PREFIX_0F3825) },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 28 */
7021     { PREFIX_TABLE (PREFIX_0F3828) },
7022     { PREFIX_TABLE (PREFIX_0F3829) },
7023     { PREFIX_TABLE (PREFIX_0F382A) },
7024     { PREFIX_TABLE (PREFIX_0F382B) },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 30 */
7030     { PREFIX_TABLE (PREFIX_0F3830) },
7031     { PREFIX_TABLE (PREFIX_0F3831) },
7032     { PREFIX_TABLE (PREFIX_0F3832) },
7033     { PREFIX_TABLE (PREFIX_0F3833) },
7034     { PREFIX_TABLE (PREFIX_0F3834) },
7035     { PREFIX_TABLE (PREFIX_0F3835) },
7036     { Bad_Opcode },
7037     { PREFIX_TABLE (PREFIX_0F3837) },
7038     /* 38 */
7039     { PREFIX_TABLE (PREFIX_0F3838) },
7040     { PREFIX_TABLE (PREFIX_0F3839) },
7041     { PREFIX_TABLE (PREFIX_0F383A) },
7042     { PREFIX_TABLE (PREFIX_0F383B) },
7043     { PREFIX_TABLE (PREFIX_0F383C) },
7044     { PREFIX_TABLE (PREFIX_0F383D) },
7045     { PREFIX_TABLE (PREFIX_0F383E) },
7046     { PREFIX_TABLE (PREFIX_0F383F) },
7047     /* 40 */
7048     { PREFIX_TABLE (PREFIX_0F3840) },
7049     { PREFIX_TABLE (PREFIX_0F3841) },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 48 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 50 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 58 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 60 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 68 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 70 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 78 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 80 */
7120     { PREFIX_TABLE (PREFIX_0F3880) },
7121     { PREFIX_TABLE (PREFIX_0F3881) },
7122     { PREFIX_TABLE (PREFIX_0F3882) },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 88 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 90 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 98 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* a0 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* a8 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* b0 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* b8 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* c0 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* c8 */
7201     { PREFIX_TABLE (PREFIX_0F38C8) },
7202     { PREFIX_TABLE (PREFIX_0F38C9) },
7203     { PREFIX_TABLE (PREFIX_0F38CA) },
7204     { PREFIX_TABLE (PREFIX_0F38CB) },
7205     { PREFIX_TABLE (PREFIX_0F38CC) },
7206     { PREFIX_TABLE (PREFIX_0F38CD) },
7207     { Bad_Opcode },
7208     { PREFIX_TABLE (PREFIX_0F38CF) },
7209     /* d0 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* d8 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { PREFIX_TABLE (PREFIX_0F38DB) },
7223     { PREFIX_TABLE (PREFIX_0F38DC) },
7224     { PREFIX_TABLE (PREFIX_0F38DD) },
7225     { PREFIX_TABLE (PREFIX_0F38DE) },
7226     { PREFIX_TABLE (PREFIX_0F38DF) },
7227     /* e0 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* e8 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* f0 */
7246     { PREFIX_TABLE (PREFIX_0F38F0) },
7247     { PREFIX_TABLE (PREFIX_0F38F1) },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { PREFIX_TABLE (PREFIX_0F38F5) },
7252     { PREFIX_TABLE (PREFIX_0F38F6) },
7253     { Bad_Opcode },
7254     /* f8 */
7255     { PREFIX_TABLE (PREFIX_0F38F8) },
7256     { PREFIX_TABLE (PREFIX_0F38F9) },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263   },
7264   /* THREE_BYTE_0F3A */
7265   {
7266     /* 00 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 08 */
7276     { PREFIX_TABLE (PREFIX_0F3A08) },
7277     { PREFIX_TABLE (PREFIX_0F3A09) },
7278     { PREFIX_TABLE (PREFIX_0F3A0A) },
7279     { PREFIX_TABLE (PREFIX_0F3A0B) },
7280     { PREFIX_TABLE (PREFIX_0F3A0C) },
7281     { PREFIX_TABLE (PREFIX_0F3A0D) },
7282     { PREFIX_TABLE (PREFIX_0F3A0E) },
7283     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7284     /* 10 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { PREFIX_TABLE (PREFIX_0F3A14) },
7290     { PREFIX_TABLE (PREFIX_0F3A15) },
7291     { PREFIX_TABLE (PREFIX_0F3A16) },
7292     { PREFIX_TABLE (PREFIX_0F3A17) },
7293     /* 18 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 20 */
7303     { PREFIX_TABLE (PREFIX_0F3A20) },
7304     { PREFIX_TABLE (PREFIX_0F3A21) },
7305     { PREFIX_TABLE (PREFIX_0F3A22) },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 28 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 30 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 38 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 40 */
7339     { PREFIX_TABLE (PREFIX_0F3A40) },
7340     { PREFIX_TABLE (PREFIX_0F3A41) },
7341     { PREFIX_TABLE (PREFIX_0F3A42) },
7342     { Bad_Opcode },
7343     { PREFIX_TABLE (PREFIX_0F3A44) },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 48 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 50 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 58 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 60 */
7375     { PREFIX_TABLE (PREFIX_0F3A60) },
7376     { PREFIX_TABLE (PREFIX_0F3A61) },
7377     { PREFIX_TABLE (PREFIX_0F3A62) },
7378     { PREFIX_TABLE (PREFIX_0F3A63) },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 68 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 70 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 78 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 80 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 88 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 90 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* 98 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* a0 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* a8 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* b0 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* b8 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* c0 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* c8 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { PREFIX_TABLE (PREFIX_0F3ACC) },
7497     { Bad_Opcode },
7498     { PREFIX_TABLE (PREFIX_0F3ACE) },
7499     { PREFIX_TABLE (PREFIX_0F3ACF) },
7500     /* d0 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* d8 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { PREFIX_TABLE (PREFIX_0F3ADF) },
7518     /* e0 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* e8 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* f0 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* f8 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554   },
7555 };
7556
7557 static const struct dis386 xop_table[][256] = {
7558   /* XOP_08 */
7559   {
7560     /* 00 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 08 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 10 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 18 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 20 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 28 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 30 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 38 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 40 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 48 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* 50 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* 58 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* 60 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* 68 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* 70 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* 78 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* 80 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7711     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7712     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     /* 88 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7721     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722     /* 90 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7730     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7731     /* 98 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7739     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     /* a0 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7748     { Bad_Opcode },
7749     /* a8 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* b0 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7766     { Bad_Opcode },
7767     /* b8 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* c0 */
7777     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7778     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7779     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7780     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* c8 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7793     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7794     /* d0 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* d8 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* e0 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* e8 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7827     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7828     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7829     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7830     /* f0 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* f8 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848   },
7849   /* XOP_09 */
7850   {
7851     /* 00 */
7852     { Bad_Opcode },
7853     { REG_TABLE (REG_XOP_TBM_01) },
7854     { REG_TABLE (REG_XOP_TBM_02) },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 08 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 10 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { REG_TABLE (REG_XOP_LWPCB) },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 18 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 20 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 28 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 30 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 38 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 40 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 48 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 50 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 58 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 60 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 68 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 70 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 78 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 80 */
7996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7997     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7998     { "vfrczss",        { XM, EXd }, 0 },
7999     { "vfrczsd",        { XM, EXq }, 0 },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 88 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 90 */
8014     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     /* 98 */
8023     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8026     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* a0 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* a8 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* b0 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* b8 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* c0 */
8068     { Bad_Opcode },
8069     { "vphaddbw",       { XM, EXxmm }, 0 },
8070     { "vphaddbd",       { XM, EXxmm }, 0 },
8071     { "vphaddbq",       { XM, EXxmm }, 0 },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { "vphaddwd",       { XM, EXxmm }, 0 },
8075     { "vphaddwq",       { XM, EXxmm }, 0 },
8076     /* c8 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { "vphadddq",       { XM, EXxmm }, 0 },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* d0 */
8086     { Bad_Opcode },
8087     { "vphaddubw",      { XM, EXxmm }, 0 },
8088     { "vphaddubd",      { XM, EXxmm }, 0 },
8089     { "vphaddubq",      { XM, EXxmm }, 0 },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { "vphadduwd",      { XM, EXxmm }, 0 },
8093     { "vphadduwq",      { XM, EXxmm }, 0 },
8094     /* d8 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { "vphaddudq",      { XM, EXxmm }, 0 },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* e0 */
8104     { Bad_Opcode },
8105     { "vphsubbw",       { XM, EXxmm }, 0 },
8106     { "vphsubwd",       { XM, EXxmm }, 0 },
8107     { "vphsubdq",       { XM, EXxmm }, 0 },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* e8 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* f0 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* f8 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139   },
8140   /* XOP_0A */
8141   {
8142     /* 00 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 08 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 10 */
8161     { "bextr",  { Gv, Ev, Iq }, 0 },
8162     { Bad_Opcode },
8163     { REG_TABLE (REG_XOP_LWP) },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 18 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 20 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 28 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 30 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 38 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 40 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 48 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 50 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 58 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 60 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 68 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 70 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 78 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 80 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 88 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 90 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 98 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* a0 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* a8 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* b0 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* b8 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* c0 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* c8 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* d0 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* d8 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* e0 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* e8 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* f0 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* f8 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430   },
8431 };
8432
8433 static const struct dis386 vex_table[][256] = {
8434   /* VEX_0F */
8435   {
8436     /* 00 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* 08 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* 10 */
8455     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8458     { MOD_TABLE (MOD_VEX_0F13) },
8459     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8460     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8461     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8462     { MOD_TABLE (MOD_VEX_0F17) },
8463     /* 18 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 20 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* 28 */
8482     { "vmovapX",        { XM, EXx }, 0 },
8483     { "vmovapX",        { EXxS, XM }, 0 },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8485     { MOD_TABLE (MOD_VEX_0F2B) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8490     /* 30 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* 38 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     /* 40 */
8509     { Bad_Opcode },
8510     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8512     { Bad_Opcode },
8513     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8517     /* 48 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* 50 */
8527     { MOD_TABLE (MOD_VEX_0F50) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8531     { "vandpX",         { XM, Vex, EXx }, 0 },
8532     { "vandnpX",        { XM, Vex, EXx }, 0 },
8533     { "vorpX",          { XM, Vex, EXx }, 0 },
8534     { "vxorpX",         { XM, Vex, EXx }, 0 },
8535     /* 58 */
8536     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8544     /* 60 */
8545     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8553     /* 68 */
8554     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8562     /* 70 */
8563     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8564     { REG_TABLE (REG_VEX_0F71) },
8565     { REG_TABLE (REG_VEX_0F72) },
8566     { REG_TABLE (REG_VEX_0F73) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8571     /* 78 */
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8580     /* 80 */
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     /* 88 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     /* 90 */
8599     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     /* 98 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* a0 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* a8 */
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { REG_TABLE (REG_VEX_0FAE) },
8633     { Bad_Opcode },
8634     /* b0 */
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* b8 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* c0 */
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8656     { Bad_Opcode },
8657     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8659     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8660     { Bad_Opcode },
8661     /* c8 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     /* d0 */
8671     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8679     /* d8 */
8680     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8688     /* e0 */
8689     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8697     /* e8 */
8698     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8706     /* f0 */
8707     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8715     /* f8 */
8716     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8723     { Bad_Opcode },
8724   },
8725   /* VEX_0F38 */
8726   {
8727     /* 00 */
8728     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8736     /* 08 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8745     /* 10 */
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8754     /* 18 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8758     { Bad_Opcode },
8759     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8762     { Bad_Opcode },
8763     /* 20 */
8764     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     /* 28 */
8773     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8781     /* 30 */
8782     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8790     /* 38 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8799     /* 40 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8808     /* 48 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* 50 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     /* 58 */
8827     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* 60 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 68 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     /* 70 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     /* 78 */
8863     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     /* 80 */
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     /* 88 */
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8886     { Bad_Opcode },
8887     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8888     { Bad_Opcode },
8889     /* 90 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8898     /* 98 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8907     /* a0 */
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8916     /* a8 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8925     /* b0 */
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8934     /* b8 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8943     /* c0 */
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     /* c8 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8961     /* d0 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* d8 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8979     /* e0 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* e8 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* f0 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9001     { REG_TABLE (REG_VEX_0F38F3) },
9002     { Bad_Opcode },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9006     /* f8 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015   },
9016   /* VEX_0F3A */
9017   {
9018     /* 00 */
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9022     { Bad_Opcode },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9026     { Bad_Opcode },
9027     /* 08 */
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9036     /* 10 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9045     /* 18 */
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* 20 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 28 */
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* 30 */
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* 38 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     /* 40 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9094     { Bad_Opcode },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9096     { Bad_Opcode },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9098     { Bad_Opcode },
9099     /* 48 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     /* 50 */
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* 58 */
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9126     /* 60 */
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     /* 68 */
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9144     /* 70 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* 78 */
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9162     /* 80 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* 88 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* 90 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* 98 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* a0 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* a8 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* b0 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* b8 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* c0 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* c8 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9251     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9252     /* d0 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* d8 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9270     /* e0 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     /* e8 */
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* f0 */
9289     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     /* f8 */
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306   },
9307 };
9308
9309 #define NEED_OPCODE_TABLE
9310 #include "i386-dis-evex.h"
9311 #undef NEED_OPCODE_TABLE
9312 static const struct dis386 vex_len_table[][2] = {
9313   /* VEX_LEN_0F12_P_0_M_0 */
9314   {
9315     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9316   },
9317
9318   /* VEX_LEN_0F12_P_0_M_1 */
9319   {
9320     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F12_P_2 */
9324   {
9325     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9326   },
9327
9328   /* VEX_LEN_0F13_M_0 */
9329   {
9330     { "vmovlpX",        { EXq, XM }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F16_P_0_M_0 */
9334   {
9335     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9336   },
9337
9338   /* VEX_LEN_0F16_P_0_M_1 */
9339   {
9340     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9341   },
9342
9343   /* VEX_LEN_0F16_P_2 */
9344   {
9345     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9346   },
9347
9348   /* VEX_LEN_0F17_M_0 */
9349   {
9350     { "vmovhpX",        { EXq, XM }, 0 },
9351   },
9352
9353   /* VEX_LEN_0F2A_P_1 */
9354   {
9355     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9356     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9357   },
9358
9359   /* VEX_LEN_0F2A_P_3 */
9360   {
9361     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9362     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9363   },
9364
9365   /* VEX_LEN_0F2C_P_1 */
9366   {
9367     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9368     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9369   },
9370
9371   /* VEX_LEN_0F2C_P_3 */
9372   {
9373     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9374     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9375   },
9376
9377   /* VEX_LEN_0F2D_P_1 */
9378   {
9379     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9380     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9381   },
9382
9383   /* VEX_LEN_0F2D_P_3 */
9384   {
9385     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9386     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9387   },
9388
9389   /* VEX_LEN_0F41_P_0 */
9390   {
9391     { Bad_Opcode },
9392     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9393   },
9394   /* VEX_LEN_0F41_P_2 */
9395   {
9396     { Bad_Opcode },
9397     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9398   },
9399   /* VEX_LEN_0F42_P_0 */
9400   {
9401     { Bad_Opcode },
9402     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9403   },
9404   /* VEX_LEN_0F42_P_2 */
9405   {
9406     { Bad_Opcode },
9407     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9408   },
9409   /* VEX_LEN_0F44_P_0 */
9410   {
9411     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9412   },
9413   /* VEX_LEN_0F44_P_2 */
9414   {
9415     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9416   },
9417   /* VEX_LEN_0F45_P_0 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9421   },
9422   /* VEX_LEN_0F45_P_2 */
9423   {
9424     { Bad_Opcode },
9425     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9426   },
9427   /* VEX_LEN_0F46_P_0 */
9428   {
9429     { Bad_Opcode },
9430     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9431   },
9432   /* VEX_LEN_0F46_P_2 */
9433   {
9434     { Bad_Opcode },
9435     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9436   },
9437   /* VEX_LEN_0F47_P_0 */
9438   {
9439     { Bad_Opcode },
9440     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9441   },
9442   /* VEX_LEN_0F47_P_2 */
9443   {
9444     { Bad_Opcode },
9445     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9446   },
9447   /* VEX_LEN_0F4A_P_0 */
9448   {
9449     { Bad_Opcode },
9450     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9451   },
9452   /* VEX_LEN_0F4A_P_2 */
9453   {
9454     { Bad_Opcode },
9455     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9456   },
9457   /* VEX_LEN_0F4B_P_0 */
9458   {
9459     { Bad_Opcode },
9460     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9461   },
9462   /* VEX_LEN_0F4B_P_2 */
9463   {
9464     { Bad_Opcode },
9465     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9466   },
9467
9468   /* VEX_LEN_0F6E_P_2 */
9469   {
9470     { "vmovK",          { XMScalar, Edq }, 0 },
9471   },
9472
9473   /* VEX_LEN_0F77_P_1 */
9474   {
9475     { "vzeroupper",     { XX }, 0 },
9476     { "vzeroall",       { XX }, 0 },
9477   },
9478
9479   /* VEX_LEN_0F7E_P_1 */
9480   {
9481     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9482   },
9483
9484   /* VEX_LEN_0F7E_P_2 */
9485   {
9486     { "vmovK",          { Edq, XMScalar }, 0 },
9487   },
9488
9489   /* VEX_LEN_0F90_P_0 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0F90_P_2 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9497   },
9498
9499   /* VEX_LEN_0F91_P_0 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9502   },
9503
9504   /* VEX_LEN_0F91_P_2 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9507   },
9508
9509   /* VEX_LEN_0F92_P_0 */
9510   {
9511     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9512   },
9513
9514   /* VEX_LEN_0F92_P_2 */
9515   {
9516     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9517   },
9518
9519   /* VEX_LEN_0F92_P_3 */
9520   {
9521     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9522   },
9523
9524   /* VEX_LEN_0F93_P_0 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9527   },
9528
9529   /* VEX_LEN_0F93_P_2 */
9530   {
9531     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9532   },
9533
9534   /* VEX_LEN_0F93_P_3 */
9535   {
9536     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9537   },
9538
9539   /* VEX_LEN_0F98_P_0 */
9540   {
9541     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9542   },
9543
9544   /* VEX_LEN_0F98_P_2 */
9545   {
9546     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9547   },
9548
9549   /* VEX_LEN_0F99_P_0 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9552   },
9553
9554   /* VEX_LEN_0F99_P_2 */
9555   {
9556     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9557   },
9558
9559   /* VEX_LEN_0FAE_R_2_M_0 */
9560   {
9561     { "vldmxcsr",       { Md }, 0 },
9562   },
9563
9564   /* VEX_LEN_0FAE_R_3_M_0 */
9565   {
9566     { "vstmxcsr",       { Md }, 0 },
9567   },
9568
9569   /* VEX_LEN_0FC4_P_2 */
9570   {
9571     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9572   },
9573
9574   /* VEX_LEN_0FC5_P_2 */
9575   {
9576     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9577   },
9578
9579   /* VEX_LEN_0FD6_P_2 */
9580   {
9581     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9582   },
9583
9584   /* VEX_LEN_0FF7_P_2 */
9585   {
9586     { "vmaskmovdqu",    { XM, XS }, 0 },
9587   },
9588
9589   /* VEX_LEN_0F3816_P_2 */
9590   {
9591     { Bad_Opcode },
9592     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9593   },
9594
9595   /* VEX_LEN_0F3819_P_2 */
9596   {
9597     { Bad_Opcode },
9598     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9599   },
9600
9601   /* VEX_LEN_0F381A_P_2_M_0 */
9602   {
9603     { Bad_Opcode },
9604     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9605   },
9606
9607   /* VEX_LEN_0F3836_P_2 */
9608   {
9609     { Bad_Opcode },
9610     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9611   },
9612
9613   /* VEX_LEN_0F3841_P_2 */
9614   {
9615     { "vphminposuw",    { XM, EXx }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F385A_P_2_M_0 */
9619   {
9620     { Bad_Opcode },
9621     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9622   },
9623
9624   /* VEX_LEN_0F38DB_P_2 */
9625   {
9626     { "vaesimc",        { XM, EXx }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F38F2_P_0 */
9630   {
9631     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9632   },
9633
9634   /* VEX_LEN_0F38F3_R_1_P_0 */
9635   {
9636     { "blsrS",          { VexGdq, Edq }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F38F3_R_2_P_0 */
9640   {
9641     { "blsmskS",        { VexGdq, Edq }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F38F3_R_3_P_0 */
9645   {
9646     { "blsiS",          { VexGdq, Edq }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F38F5_P_0 */
9650   {
9651     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F38F5_P_1 */
9655   {
9656     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F38F5_P_3 */
9660   {
9661     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F38F6_P_3 */
9665   {
9666     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9667   },
9668
9669   /* VEX_LEN_0F38F7_P_0 */
9670   {
9671     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F38F7_P_1 */
9675   {
9676     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F38F7_P_2 */
9680   {
9681     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9682   },
9683
9684   /* VEX_LEN_0F38F7_P_3 */
9685   {
9686     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9687   },
9688
9689   /* VEX_LEN_0F3A00_P_2 */
9690   {
9691     { Bad_Opcode },
9692     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9693   },
9694
9695   /* VEX_LEN_0F3A01_P_2 */
9696   {
9697     { Bad_Opcode },
9698     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9699   },
9700
9701   /* VEX_LEN_0F3A06_P_2 */
9702   {
9703     { Bad_Opcode },
9704     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9705   },
9706
9707   /* VEX_LEN_0F3A14_P_2 */
9708   {
9709     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9710   },
9711
9712   /* VEX_LEN_0F3A15_P_2 */
9713   {
9714     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9715   },
9716
9717   /* VEX_LEN_0F3A16_P_2  */
9718   {
9719     { "vpextrK",        { Edq, XM, Ib }, 0 },
9720   },
9721
9722   /* VEX_LEN_0F3A17_P_2 */
9723   {
9724     { "vextractps",     { Edqd, XM, Ib }, 0 },
9725   },
9726
9727   /* VEX_LEN_0F3A18_P_2 */
9728   {
9729     { Bad_Opcode },
9730     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9731   },
9732
9733   /* VEX_LEN_0F3A19_P_2 */
9734   {
9735     { Bad_Opcode },
9736     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9737   },
9738
9739   /* VEX_LEN_0F3A20_P_2 */
9740   {
9741     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9742   },
9743
9744   /* VEX_LEN_0F3A21_P_2 */
9745   {
9746     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9747   },
9748
9749   /* VEX_LEN_0F3A22_P_2 */
9750   {
9751     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9752   },
9753
9754   /* VEX_LEN_0F3A30_P_2 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9757   },
9758
9759   /* VEX_LEN_0F3A31_P_2 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9762   },
9763
9764   /* VEX_LEN_0F3A32_P_2 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9767   },
9768
9769   /* VEX_LEN_0F3A33_P_2 */
9770   {
9771     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9772   },
9773
9774   /* VEX_LEN_0F3A38_P_2 */
9775   {
9776     { Bad_Opcode },
9777     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9778   },
9779
9780   /* VEX_LEN_0F3A39_P_2 */
9781   {
9782     { Bad_Opcode },
9783     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9784   },
9785
9786   /* VEX_LEN_0F3A41_P_2 */
9787   {
9788     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9789   },
9790
9791   /* VEX_LEN_0F3A46_P_2 */
9792   {
9793     { Bad_Opcode },
9794     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9795   },
9796
9797   /* VEX_LEN_0F3A60_P_2 */
9798   {
9799     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9800   },
9801
9802   /* VEX_LEN_0F3A61_P_2 */
9803   {
9804     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9805   },
9806
9807   /* VEX_LEN_0F3A62_P_2 */
9808   {
9809     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9810   },
9811
9812   /* VEX_LEN_0F3A63_P_2 */
9813   {
9814     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9815   },
9816
9817   /* VEX_LEN_0F3A6A_P_2 */
9818   {
9819     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F3A6B_P_2 */
9823   {
9824     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9825   },
9826
9827   /* VEX_LEN_0F3A6E_P_2 */
9828   {
9829     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9830   },
9831
9832   /* VEX_LEN_0F3A6F_P_2 */
9833   {
9834     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9835   },
9836
9837   /* VEX_LEN_0F3A7A_P_2 */
9838   {
9839     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9840   },
9841
9842   /* VEX_LEN_0F3A7B_P_2 */
9843   {
9844     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9845   },
9846
9847   /* VEX_LEN_0F3A7E_P_2 */
9848   {
9849     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9850   },
9851
9852   /* VEX_LEN_0F3A7F_P_2 */
9853   {
9854     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9855   },
9856
9857   /* VEX_LEN_0F3ADF_P_2 */
9858   {
9859     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9860   },
9861
9862   /* VEX_LEN_0F3AF0_P_3 */
9863   {
9864     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9865   },
9866
9867   /* VEX_LEN_0FXOP_08_CC */
9868   {
9869      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9870   },
9871
9872   /* VEX_LEN_0FXOP_08_CD */
9873   {
9874      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9875   },
9876
9877   /* VEX_LEN_0FXOP_08_CE */
9878   {
9879      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9880   },
9881
9882   /* VEX_LEN_0FXOP_08_CF */
9883   {
9884      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9885   },
9886
9887   /* VEX_LEN_0FXOP_08_EC */
9888   {
9889      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9890   },
9891
9892   /* VEX_LEN_0FXOP_08_ED */
9893   {
9894      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9895   },
9896
9897   /* VEX_LEN_0FXOP_08_EE */
9898   {
9899      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9900   },
9901
9902   /* VEX_LEN_0FXOP_08_EF */
9903   {
9904      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9905   },
9906
9907   /* VEX_LEN_0FXOP_09_80 */
9908   {
9909     { "vfrczps",        { XM, EXxmm }, 0 },
9910     { "vfrczps",        { XM, EXymmq }, 0 },
9911   },
9912
9913   /* VEX_LEN_0FXOP_09_81 */
9914   {
9915     { "vfrczpd",        { XM, EXxmm }, 0 },
9916     { "vfrczpd",        { XM, EXymmq }, 0 },
9917   },
9918 };
9919
9920 static const struct dis386 evex_len_table[][3] = {
9921 #define NEED_EVEX_LEN_TABLE
9922 #include "i386-dis-evex.h"
9923 #undef NEED_EVEX_LEN_TABLE
9924 };
9925
9926 static const struct dis386 vex_w_table[][2] = {
9927   {
9928     /* VEX_W_0F41_P_0_LEN_1 */
9929     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9930     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9931   },
9932   {
9933     /* VEX_W_0F41_P_2_LEN_1 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9936   },
9937   {
9938     /* VEX_W_0F42_P_0_LEN_1 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9941   },
9942   {
9943     /* VEX_W_0F42_P_2_LEN_1 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9946   },
9947   {
9948     /* VEX_W_0F44_P_0_LEN_0 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9950     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9951   },
9952   {
9953     /* VEX_W_0F44_P_2_LEN_0 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9955     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9956   },
9957   {
9958     /* VEX_W_0F45_P_0_LEN_1 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9960     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9961   },
9962   {
9963     /* VEX_W_0F45_P_2_LEN_1 */
9964     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9965     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9966   },
9967   {
9968     /* VEX_W_0F46_P_0_LEN_1 */
9969     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9970     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9971   },
9972   {
9973     /* VEX_W_0F46_P_2_LEN_1 */
9974     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9975     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9976   },
9977   {
9978     /* VEX_W_0F47_P_0_LEN_1 */
9979     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9980     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9981   },
9982   {
9983     /* VEX_W_0F47_P_2_LEN_1 */
9984     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9985     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9986   },
9987   {
9988     /* VEX_W_0F4A_P_0_LEN_1 */
9989     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9990     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9991   },
9992   {
9993     /* VEX_W_0F4A_P_2_LEN_1 */
9994     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9995     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9996   },
9997   {
9998     /* VEX_W_0F4B_P_0_LEN_1 */
9999     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10000     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10001   },
10002   {
10003     /* VEX_W_0F4B_P_2_LEN_1 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10005   },
10006   {
10007     /* VEX_W_0F90_P_0_LEN_0 */
10008     { "kmovw",          { MaskG, MaskE }, 0 },
10009     { "kmovq",          { MaskG, MaskE }, 0 },
10010   },
10011   {
10012     /* VEX_W_0F90_P_2_LEN_0 */
10013     { "kmovb",          { MaskG, MaskBDE }, 0 },
10014     { "kmovd",          { MaskG, MaskBDE }, 0 },
10015   },
10016   {
10017     /* VEX_W_0F91_P_0_LEN_0 */
10018     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10019     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10020   },
10021   {
10022     /* VEX_W_0F91_P_2_LEN_0 */
10023     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10024     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10025   },
10026   {
10027     /* VEX_W_0F92_P_0_LEN_0 */
10028     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10029   },
10030   {
10031     /* VEX_W_0F92_P_2_LEN_0 */
10032     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10033   },
10034   {
10035     /* VEX_W_0F93_P_0_LEN_0 */
10036     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10037   },
10038   {
10039     /* VEX_W_0F93_P_2_LEN_0 */
10040     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10041   },
10042   {
10043     /* VEX_W_0F98_P_0_LEN_0 */
10044     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10045     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10046   },
10047   {
10048     /* VEX_W_0F98_P_2_LEN_0 */
10049     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10050     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10051   },
10052   {
10053     /* VEX_W_0F99_P_0_LEN_0 */
10054     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10055     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10056   },
10057   {
10058     /* VEX_W_0F99_P_2_LEN_0 */
10059     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10060     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10061   },
10062   {
10063     /* VEX_W_0F380C_P_2  */
10064     { "vpermilps",      { XM, Vex, EXx }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F380D_P_2  */
10068     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F380E_P_2  */
10072     { "vtestps",        { XM, EXx }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F380F_P_2  */
10076     { "vtestpd",        { XM, EXx }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F3816_P_2  */
10080     { "vpermps",        { XM, Vex, EXx }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F3818_P_2 */
10084     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F3819_P_2 */
10088     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F381A_P_2_M_0 */
10092     { "vbroadcastf128", { XM, Mxmm }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F382C_P_2_M_0 */
10096     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F382D_P_2_M_0 */
10100     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F382E_P_2_M_0 */
10104     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F382F_P_2_M_0 */
10108     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10109   },
10110   {
10111     /* VEX_W_0F3836_P_2  */
10112     { "vpermd",         { XM, Vex, EXx }, 0 },
10113   },
10114   {
10115     /* VEX_W_0F3846_P_2 */
10116     { "vpsravd",        { XM, Vex, EXx }, 0 },
10117   },
10118   {
10119     /* VEX_W_0F3858_P_2 */
10120     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3859_P_2 */
10124     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F385A_P_2_M_0 */
10128     { "vbroadcasti128", { XM, Mxmm }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3878_P_2 */
10132     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3879_P_2 */
10136     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10137   },
10138   {
10139     /* VEX_W_0F38CF_P_2 */
10140     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10141   },
10142   {
10143     /* VEX_W_0F3A00_P_2 */
10144     { Bad_Opcode },
10145     { "vpermq",         { XM, EXx, Ib }, 0 },
10146   },
10147   {
10148     /* VEX_W_0F3A01_P_2 */
10149     { Bad_Opcode },
10150     { "vpermpd",        { XM, EXx, Ib }, 0 },
10151   },
10152   {
10153     /* VEX_W_0F3A02_P_2 */
10154     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10155   },
10156   {
10157     /* VEX_W_0F3A04_P_2 */
10158     { "vpermilps",      { XM, EXx, Ib }, 0 },
10159   },
10160   {
10161     /* VEX_W_0F3A05_P_2 */
10162     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10163   },
10164   {
10165     /* VEX_W_0F3A06_P_2 */
10166     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10167   },
10168   {
10169     /* VEX_W_0F3A18_P_2 */
10170     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10171   },
10172   {
10173     /* VEX_W_0F3A19_P_2 */
10174     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10175   },
10176   {
10177     /* VEX_W_0F3A30_P_2_LEN_0 */
10178     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10179     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10180   },
10181   {
10182     /* VEX_W_0F3A31_P_2_LEN_0 */
10183     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10184     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10185   },
10186   {
10187     /* VEX_W_0F3A32_P_2_LEN_0 */
10188     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10189     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10190   },
10191   {
10192     /* VEX_W_0F3A33_P_2_LEN_0 */
10193     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10194     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10195   },
10196   {
10197     /* VEX_W_0F3A38_P_2 */
10198     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10199   },
10200   {
10201     /* VEX_W_0F3A39_P_2 */
10202     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10203   },
10204   {
10205     /* VEX_W_0F3A46_P_2 */
10206     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10207   },
10208   {
10209     /* VEX_W_0F3A48_P_2 */
10210     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10211     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10212   },
10213   {
10214     /* VEX_W_0F3A49_P_2 */
10215     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10216     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10217   },
10218   {
10219     /* VEX_W_0F3A4A_P_2 */
10220     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10221   },
10222   {
10223     /* VEX_W_0F3A4B_P_2 */
10224     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10225   },
10226   {
10227     /* VEX_W_0F3A4C_P_2 */
10228     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10229   },
10230   {
10231     /* VEX_W_0F3ACE_P_2 */
10232     { Bad_Opcode },
10233     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10234   },
10235   {
10236     /* VEX_W_0F3ACF_P_2 */
10237     { Bad_Opcode },
10238     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10239   },
10240 #define NEED_VEX_W_TABLE
10241 #include "i386-dis-evex.h"
10242 #undef NEED_VEX_W_TABLE
10243 };
10244
10245 static const struct dis386 mod_table[][2] = {
10246   {
10247     /* MOD_8D */
10248     { "leaS",           { Gv, M }, 0 },
10249   },
10250   {
10251     /* MOD_C6_REG_7 */
10252     { Bad_Opcode },
10253     { RM_TABLE (RM_C6_REG_7) },
10254   },
10255   {
10256     /* MOD_C7_REG_7 */
10257     { Bad_Opcode },
10258     { RM_TABLE (RM_C7_REG_7) },
10259   },
10260   {
10261     /* MOD_FF_REG_3 */
10262     { "Jcall^", { indirEp }, 0 },
10263   },
10264   {
10265     /* MOD_FF_REG_5 */
10266     { "Jjmp^", { indirEp }, 0 },
10267   },
10268   {
10269     /* MOD_0F01_REG_0 */
10270     { X86_64_TABLE (X86_64_0F01_REG_0) },
10271     { RM_TABLE (RM_0F01_REG_0) },
10272   },
10273   {
10274     /* MOD_0F01_REG_1 */
10275     { X86_64_TABLE (X86_64_0F01_REG_1) },
10276     { RM_TABLE (RM_0F01_REG_1) },
10277   },
10278   {
10279     /* MOD_0F01_REG_2 */
10280     { X86_64_TABLE (X86_64_0F01_REG_2) },
10281     { RM_TABLE (RM_0F01_REG_2) },
10282   },
10283   {
10284     /* MOD_0F01_REG_3 */
10285     { X86_64_TABLE (X86_64_0F01_REG_3) },
10286     { RM_TABLE (RM_0F01_REG_3) },
10287   },
10288   {
10289     /* MOD_0F01_REG_5 */
10290     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10291     { RM_TABLE (RM_0F01_REG_5) },
10292   },
10293   {
10294     /* MOD_0F01_REG_7 */
10295     { "invlpg",         { Mb }, 0 },
10296     { RM_TABLE (RM_0F01_REG_7) },
10297   },
10298   {
10299     /* MOD_0F12_PREFIX_0 */
10300     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10301     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10302   },
10303   {
10304     /* MOD_0F13 */
10305     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10306   },
10307   {
10308     /* MOD_0F16_PREFIX_0 */
10309     { "movhps",         { XM, EXq }, 0 },
10310     { "movlhps",        { XM, EXq }, 0 },
10311   },
10312   {
10313     /* MOD_0F17 */
10314     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10315   },
10316   {
10317     /* MOD_0F18_REG_0 */
10318     { "prefetchnta",    { Mb }, 0 },
10319   },
10320   {
10321     /* MOD_0F18_REG_1 */
10322     { "prefetcht0",     { Mb }, 0 },
10323   },
10324   {
10325     /* MOD_0F18_REG_2 */
10326     { "prefetcht1",     { Mb }, 0 },
10327   },
10328   {
10329     /* MOD_0F18_REG_3 */
10330     { "prefetcht2",     { Mb }, 0 },
10331   },
10332   {
10333     /* MOD_0F18_REG_4 */
10334     { "nop/reserved",   { Mb }, 0 },
10335   },
10336   {
10337     /* MOD_0F18_REG_5 */
10338     { "nop/reserved",   { Mb }, 0 },
10339   },
10340   {
10341     /* MOD_0F18_REG_6 */
10342     { "nop/reserved",   { Mb }, 0 },
10343   },
10344   {
10345     /* MOD_0F18_REG_7 */
10346     { "nop/reserved",   { Mb }, 0 },
10347   },
10348   {
10349     /* MOD_0F1A_PREFIX_0 */
10350     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10351     { "nopQ",           { Ev }, 0 },
10352   },
10353   {
10354     /* MOD_0F1B_PREFIX_0 */
10355     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10356     { "nopQ",           { Ev }, 0 },
10357   },
10358   {
10359     /* MOD_0F1B_PREFIX_1 */
10360     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10361     { "nopQ",           { Ev }, 0 },
10362   },
10363   {
10364     /* MOD_0F1C_PREFIX_0 */
10365     { REG_TABLE (REG_0F1C_MOD_0) },
10366     { "nopQ",           { Ev }, 0 },
10367   },
10368   {
10369     /* MOD_0F1E_PREFIX_1 */
10370     { "nopQ",           { Ev }, 0 },
10371     { REG_TABLE (REG_0F1E_MOD_3) },
10372   },
10373   {
10374     /* MOD_0F24 */
10375     { Bad_Opcode },
10376     { "movL",           { Rd, Td }, 0 },
10377   },
10378   {
10379     /* MOD_0F26 */
10380     { Bad_Opcode },
10381     { "movL",           { Td, Rd }, 0 },
10382   },
10383   {
10384     /* MOD_0F2B_PREFIX_0 */
10385     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10386   },
10387   {
10388     /* MOD_0F2B_PREFIX_1 */
10389     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10390   },
10391   {
10392     /* MOD_0F2B_PREFIX_2 */
10393     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10394   },
10395   {
10396     /* MOD_0F2B_PREFIX_3 */
10397     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10398   },
10399   {
10400     /* MOD_0F51 */
10401     { Bad_Opcode },
10402     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10403   },
10404   {
10405     /* MOD_0F71_REG_2 */
10406     { Bad_Opcode },
10407     { "psrlw",          { MS, Ib }, 0 },
10408   },
10409   {
10410     /* MOD_0F71_REG_4 */
10411     { Bad_Opcode },
10412     { "psraw",          { MS, Ib }, 0 },
10413   },
10414   {
10415     /* MOD_0F71_REG_6 */
10416     { Bad_Opcode },
10417     { "psllw",          { MS, Ib }, 0 },
10418   },
10419   {
10420     /* MOD_0F72_REG_2 */
10421     { Bad_Opcode },
10422     { "psrld",          { MS, Ib }, 0 },
10423   },
10424   {
10425     /* MOD_0F72_REG_4 */
10426     { Bad_Opcode },
10427     { "psrad",          { MS, Ib }, 0 },
10428   },
10429   {
10430     /* MOD_0F72_REG_6 */
10431     { Bad_Opcode },
10432     { "pslld",          { MS, Ib }, 0 },
10433   },
10434   {
10435     /* MOD_0F73_REG_2 */
10436     { Bad_Opcode },
10437     { "psrlq",          { MS, Ib }, 0 },
10438   },
10439   {
10440     /* MOD_0F73_REG_3 */
10441     { Bad_Opcode },
10442     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10443   },
10444   {
10445     /* MOD_0F73_REG_6 */
10446     { Bad_Opcode },
10447     { "psllq",          { MS, Ib }, 0 },
10448   },
10449   {
10450     /* MOD_0F73_REG_7 */
10451     { Bad_Opcode },
10452     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10453   },
10454   {
10455     /* MOD_0FAE_REG_0 */
10456     { "fxsave",         { FXSAVE }, 0 },
10457     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10458   },
10459   {
10460     /* MOD_0FAE_REG_1 */
10461     { "fxrstor",        { FXSAVE }, 0 },
10462     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10463   },
10464   {
10465     /* MOD_0FAE_REG_2 */
10466     { "ldmxcsr",        { Md }, 0 },
10467     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10468   },
10469   {
10470     /* MOD_0FAE_REG_3 */
10471     { "stmxcsr",        { Md }, 0 },
10472     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10473   },
10474   {
10475     /* MOD_0FAE_REG_4 */
10476     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10477     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10478   },
10479   {
10480     /* MOD_0FAE_REG_5 */
10481     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10482     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10483   },
10484   {
10485     /* MOD_0FAE_REG_6 */
10486     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10487     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10488   },
10489   {
10490     /* MOD_0FAE_REG_7 */
10491     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10492     { RM_TABLE (RM_0FAE_REG_7) },
10493   },
10494   {
10495     /* MOD_0FB2 */
10496     { "lssS",           { Gv, Mp }, 0 },
10497   },
10498   {
10499     /* MOD_0FB4 */
10500     { "lfsS",           { Gv, Mp }, 0 },
10501   },
10502   {
10503     /* MOD_0FB5 */
10504     { "lgsS",           { Gv, Mp }, 0 },
10505   },
10506   {
10507     /* MOD_0FC3 */
10508     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10509   },
10510   {
10511     /* MOD_0FC7_REG_3 */
10512     { "xrstors",        { FXSAVE }, 0 },
10513   },
10514   {
10515     /* MOD_0FC7_REG_4 */
10516     { "xsavec",         { FXSAVE }, 0 },
10517   },
10518   {
10519     /* MOD_0FC7_REG_5 */
10520     { "xsaves",         { FXSAVE }, 0 },
10521   },
10522   {
10523     /* MOD_0FC7_REG_6 */
10524     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10525     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10526   },
10527   {
10528     /* MOD_0FC7_REG_7 */
10529     { "vmptrst",        { Mq }, 0 },
10530     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10531   },
10532   {
10533     /* MOD_0FD7 */
10534     { Bad_Opcode },
10535     { "pmovmskb",       { Gdq, MS }, 0 },
10536   },
10537   {
10538     /* MOD_0FE7_PREFIX_2 */
10539     { "movntdq",        { Mx, XM }, 0 },
10540   },
10541   {
10542     /* MOD_0FF0_PREFIX_3 */
10543     { "lddqu",          { XM, M }, 0 },
10544   },
10545   {
10546     /* MOD_0F382A_PREFIX_2 */
10547     { "movntdqa",       { XM, Mx }, 0 },
10548   },
10549   {
10550     /* MOD_0F38F5_PREFIX_2 */
10551     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10552   },
10553   {
10554     /* MOD_0F38F6_PREFIX_0 */
10555     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10556   },
10557   {
10558     /* MOD_0F38F8_PREFIX_1 */
10559     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10560   },
10561   {
10562     /* MOD_0F38F8_PREFIX_2 */
10563     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10564   },
10565   {
10566     /* MOD_0F38F8_PREFIX_3 */
10567     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10568   },
10569   {
10570     /* MOD_0F38F9_PREFIX_0 */
10571     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10572   },
10573   {
10574     /* MOD_62_32BIT */
10575     { "bound{S|}",      { Gv, Ma }, 0 },
10576     { EVEX_TABLE (EVEX_0F) },
10577   },
10578   {
10579     /* MOD_C4_32BIT */
10580     { "lesS",           { Gv, Mp }, 0 },
10581     { VEX_C4_TABLE (VEX_0F) },
10582   },
10583   {
10584     /* MOD_C5_32BIT */
10585     { "ldsS",           { Gv, Mp }, 0 },
10586     { VEX_C5_TABLE (VEX_0F) },
10587   },
10588   {
10589     /* MOD_VEX_0F12_PREFIX_0 */
10590     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10591     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10592   },
10593   {
10594     /* MOD_VEX_0F13 */
10595     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10596   },
10597   {
10598     /* MOD_VEX_0F16_PREFIX_0 */
10599     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10600     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10601   },
10602   {
10603     /* MOD_VEX_0F17 */
10604     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10605   },
10606   {
10607     /* MOD_VEX_0F2B */
10608     { "vmovntpX",       { Mx, XM }, 0 },
10609   },
10610   {
10611     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10612     { Bad_Opcode },
10613     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10614   },
10615   {
10616     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10617     { Bad_Opcode },
10618     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10619   },
10620   {
10621     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10622     { Bad_Opcode },
10623     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10624   },
10625   {
10626     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10627     { Bad_Opcode },
10628     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10629   },
10630   {
10631     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10632     { Bad_Opcode },
10633     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10634   },
10635   {
10636     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10637     { Bad_Opcode },
10638     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10639   },
10640   {
10641     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10642     { Bad_Opcode },
10643     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10644   },
10645   {
10646     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10647     { Bad_Opcode },
10648     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10649   },
10650   {
10651     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10652     { Bad_Opcode },
10653     { "knotw",          { MaskG, MaskR }, 0 },
10654   },
10655   {
10656     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10657     { Bad_Opcode },
10658     { "knotq",          { MaskG, MaskR }, 0 },
10659   },
10660   {
10661     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10662     { Bad_Opcode },
10663     { "knotb",          { MaskG, MaskR }, 0 },
10664   },
10665   {
10666     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10667     { Bad_Opcode },
10668     { "knotd",          { MaskG, MaskR }, 0 },
10669   },
10670   {
10671     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10672     { Bad_Opcode },
10673     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10674   },
10675   {
10676     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10677     { Bad_Opcode },
10678     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10679   },
10680   {
10681     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10682     { Bad_Opcode },
10683     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10684   },
10685   {
10686     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10687     { Bad_Opcode },
10688     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10689   },
10690  {
10691     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10692     { Bad_Opcode },
10693     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10694   },
10695   {
10696     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10697     { Bad_Opcode },
10698     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10699   },
10700   {
10701     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10702     { Bad_Opcode },
10703     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10704   },
10705   {
10706     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10707     { Bad_Opcode },
10708     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10709   },
10710   {
10711     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10712     { Bad_Opcode },
10713     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10714   },
10715   {
10716     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10717     { Bad_Opcode },
10718     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10719   },
10720   {
10721     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10722     { Bad_Opcode },
10723     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10724   },
10725   {
10726     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10727     { Bad_Opcode },
10728     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10729   },
10730   {
10731     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10732     { Bad_Opcode },
10733     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10734   },
10735   {
10736     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10737     { Bad_Opcode },
10738     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10739   },
10740   {
10741     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10742     { Bad_Opcode },
10743     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10744   },
10745   {
10746     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10747     { Bad_Opcode },
10748     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10749   },
10750   {
10751     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10752     { Bad_Opcode },
10753     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10754   },
10755   {
10756     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10757     { Bad_Opcode },
10758     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10759   },
10760   {
10761     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10762     { Bad_Opcode },
10763     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10764   },
10765   {
10766     /* MOD_VEX_0F50 */
10767     { Bad_Opcode },
10768     { "vmovmskpX",      { Gdq, XS }, 0 },
10769   },
10770   {
10771     /* MOD_VEX_0F71_REG_2 */
10772     { Bad_Opcode },
10773     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10774   },
10775   {
10776     /* MOD_VEX_0F71_REG_4 */
10777     { Bad_Opcode },
10778     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10779   },
10780   {
10781     /* MOD_VEX_0F71_REG_6 */
10782     { Bad_Opcode },
10783     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10784   },
10785   {
10786     /* MOD_VEX_0F72_REG_2 */
10787     { Bad_Opcode },
10788     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10789   },
10790   {
10791     /* MOD_VEX_0F72_REG_4 */
10792     { Bad_Opcode },
10793     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10794   },
10795   {
10796     /* MOD_VEX_0F72_REG_6 */
10797     { Bad_Opcode },
10798     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10799   },
10800   {
10801     /* MOD_VEX_0F73_REG_2 */
10802     { Bad_Opcode },
10803     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10804   },
10805   {
10806     /* MOD_VEX_0F73_REG_3 */
10807     { Bad_Opcode },
10808     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10809   },
10810   {
10811     /* MOD_VEX_0F73_REG_6 */
10812     { Bad_Opcode },
10813     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10814   },
10815   {
10816     /* MOD_VEX_0F73_REG_7 */
10817     { Bad_Opcode },
10818     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10819   },
10820   {
10821     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10822     { "kmovw",          { Ew, MaskG }, 0 },
10823     { Bad_Opcode },
10824   },
10825   {
10826     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10827     { "kmovq",          { Eq, MaskG }, 0 },
10828     { Bad_Opcode },
10829   },
10830   {
10831     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10832     { "kmovb",          { Eb, MaskG }, 0 },
10833     { Bad_Opcode },
10834   },
10835   {
10836     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10837     { "kmovd",          { Ed, MaskG }, 0 },
10838     { Bad_Opcode },
10839   },
10840   {
10841     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10842     { Bad_Opcode },
10843     { "kmovw",          { MaskG, Rdq }, 0 },
10844   },
10845   {
10846     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10847     { Bad_Opcode },
10848     { "kmovb",          { MaskG, Rdq }, 0 },
10849   },
10850   {
10851     /* MOD_VEX_0F92_P_3_LEN_0 */
10852     { Bad_Opcode },
10853     { "kmovK",          { MaskG, Rdq }, 0 },
10854   },
10855   {
10856     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10857     { Bad_Opcode },
10858     { "kmovw",          { Gdq, MaskR }, 0 },
10859   },
10860   {
10861     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10862     { Bad_Opcode },
10863     { "kmovb",          { Gdq, MaskR }, 0 },
10864   },
10865   {
10866     /* MOD_VEX_0F93_P_3_LEN_0 */
10867     { Bad_Opcode },
10868     { "kmovK",          { Gdq, MaskR }, 0 },
10869   },
10870   {
10871     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10872     { Bad_Opcode },
10873     { "kortestw", { MaskG, MaskR }, 0 },
10874   },
10875   {
10876     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10877     { Bad_Opcode },
10878     { "kortestq", { MaskG, MaskR }, 0 },
10879   },
10880   {
10881     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10882     { Bad_Opcode },
10883     { "kortestb", { MaskG, MaskR }, 0 },
10884   },
10885   {
10886     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10887     { Bad_Opcode },
10888     { "kortestd", { MaskG, MaskR }, 0 },
10889   },
10890   {
10891     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10892     { Bad_Opcode },
10893     { "ktestw", { MaskG, MaskR }, 0 },
10894   },
10895   {
10896     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10897     { Bad_Opcode },
10898     { "ktestq", { MaskG, MaskR }, 0 },
10899   },
10900   {
10901     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10902     { Bad_Opcode },
10903     { "ktestb", { MaskG, MaskR }, 0 },
10904   },
10905   {
10906     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10907     { Bad_Opcode },
10908     { "ktestd", { MaskG, MaskR }, 0 },
10909   },
10910   {
10911     /* MOD_VEX_0FAE_REG_2 */
10912     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10913   },
10914   {
10915     /* MOD_VEX_0FAE_REG_3 */
10916     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10917   },
10918   {
10919     /* MOD_VEX_0FD7_PREFIX_2 */
10920     { Bad_Opcode },
10921     { "vpmovmskb",      { Gdq, XS }, 0 },
10922   },
10923   {
10924     /* MOD_VEX_0FE7_PREFIX_2 */
10925     { "vmovntdq",       { Mx, XM }, 0 },
10926   },
10927   {
10928     /* MOD_VEX_0FF0_PREFIX_3 */
10929     { "vlddqu",         { XM, M }, 0 },
10930   },
10931   {
10932     /* MOD_VEX_0F381A_PREFIX_2 */
10933     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10934   },
10935   {
10936     /* MOD_VEX_0F382A_PREFIX_2 */
10937     { "vmovntdqa",      { XM, Mx }, 0 },
10938   },
10939   {
10940     /* MOD_VEX_0F382C_PREFIX_2 */
10941     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10942   },
10943   {
10944     /* MOD_VEX_0F382D_PREFIX_2 */
10945     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10946   },
10947   {
10948     /* MOD_VEX_0F382E_PREFIX_2 */
10949     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10950   },
10951   {
10952     /* MOD_VEX_0F382F_PREFIX_2 */
10953     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10954   },
10955   {
10956     /* MOD_VEX_0F385A_PREFIX_2 */
10957     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10958   },
10959   {
10960     /* MOD_VEX_0F388C_PREFIX_2 */
10961     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10962   },
10963   {
10964     /* MOD_VEX_0F388E_PREFIX_2 */
10965     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10966   },
10967   {
10968     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10969     { Bad_Opcode },
10970     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10971   },
10972   {
10973     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10974     { Bad_Opcode },
10975     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10976   },
10977   {
10978     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10979     { Bad_Opcode },
10980     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10981   },
10982   {
10983     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10984     { Bad_Opcode },
10985     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10986   },
10987   {
10988     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10989     { Bad_Opcode },
10990     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10991   },
10992   {
10993     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10994     { Bad_Opcode },
10995     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10996   },
10997   {
10998     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10999     { Bad_Opcode },
11000     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11001   },
11002   {
11003     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11004     { Bad_Opcode },
11005     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11006   },
11007 #define NEED_MOD_TABLE
11008 #include "i386-dis-evex.h"
11009 #undef NEED_MOD_TABLE
11010 };
11011
11012 static const struct dis386 rm_table[][8] = {
11013   {
11014     /* RM_C6_REG_7 */
11015     { "xabort",         { Skip_MODRM, Ib }, 0 },
11016   },
11017   {
11018     /* RM_C7_REG_7 */
11019     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
11020   },
11021   {
11022     /* RM_0F01_REG_0 */
11023     { "enclv",          { Skip_MODRM }, 0 },
11024     { "vmcall",         { Skip_MODRM }, 0 },
11025     { "vmlaunch",       { Skip_MODRM }, 0 },
11026     { "vmresume",       { Skip_MODRM }, 0 },
11027     { "vmxoff",         { Skip_MODRM }, 0 },
11028     { "pconfig",        { Skip_MODRM }, 0 },
11029   },
11030   {
11031     /* RM_0F01_REG_1 */
11032     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11033     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11034     { "clac",           { Skip_MODRM }, 0 },
11035     { "stac",           { Skip_MODRM }, 0 },
11036     { Bad_Opcode },
11037     { Bad_Opcode },
11038     { Bad_Opcode },
11039     { "encls",          { Skip_MODRM }, 0 },
11040   },
11041   {
11042     /* RM_0F01_REG_2 */
11043     { "xgetbv",         { Skip_MODRM }, 0 },
11044     { "xsetbv",         { Skip_MODRM }, 0 },
11045     { Bad_Opcode },
11046     { Bad_Opcode },
11047     { "vmfunc",         { Skip_MODRM }, 0 },
11048     { "xend",           { Skip_MODRM }, 0 },
11049     { "xtest",          { Skip_MODRM }, 0 },
11050     { "enclu",          { Skip_MODRM }, 0 },
11051   },
11052   {
11053     /* RM_0F01_REG_3 */
11054     { "vmrun",          { Skip_MODRM }, 0 },
11055     { "vmmcall",        { Skip_MODRM }, 0 },
11056     { "vmload",         { Skip_MODRM }, 0 },
11057     { "vmsave",         { Skip_MODRM }, 0 },
11058     { "stgi",           { Skip_MODRM }, 0 },
11059     { "clgi",           { Skip_MODRM }, 0 },
11060     { "skinit",         { Skip_MODRM }, 0 },
11061     { "invlpga",        { Skip_MODRM }, 0 },
11062   },
11063   {
11064     /* RM_0F01_REG_5 */
11065     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11066     { Bad_Opcode },
11067     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11068     { Bad_Opcode },
11069     { Bad_Opcode },
11070     { Bad_Opcode },
11071     { "rdpkru",         { Skip_MODRM }, 0 },
11072     { "wrpkru",         { Skip_MODRM }, 0 },
11073   },
11074   {
11075     /* RM_0F01_REG_7 */
11076     { "swapgs",         { Skip_MODRM }, 0  },
11077     { "rdtscp",         { Skip_MODRM }, 0  },
11078     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11079     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11080     { "clzero",         { Skip_MODRM }, 0  },
11081   },
11082   {
11083     /* RM_0F1E_MOD_3_REG_7 */
11084     { "nopQ",           { Ev }, 0 },
11085     { "nopQ",           { Ev }, 0 },
11086     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11087     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11088     { "nopQ",           { Ev }, 0 },
11089     { "nopQ",           { Ev }, 0 },
11090     { "nopQ",           { Ev }, 0 },
11091     { "nopQ",           { Ev }, 0 },
11092   },
11093   {
11094     /* RM_0FAE_REG_6 */
11095     { "mfence",         { Skip_MODRM }, 0 },
11096   },
11097   {
11098     /* RM_0FAE_REG_7 */
11099     { "sfence",         { Skip_MODRM }, 0 },
11100
11101   },
11102 };
11103
11104 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11105
11106 /* We use the high bit to indicate different name for the same
11107    prefix.  */
11108 #define REP_PREFIX      (0xf3 | 0x100)
11109 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11110 #define XRELEASE_PREFIX (0xf3 | 0x400)
11111 #define BND_PREFIX      (0xf2 | 0x400)
11112 #define NOTRACK_PREFIX  (0x3e | 0x100)
11113
11114 static int
11115 ckprefix (void)
11116 {
11117   int newrex, i, length;
11118   rex = 0;
11119   rex_ignored = 0;
11120   prefixes = 0;
11121   used_prefixes = 0;
11122   rex_used = 0;
11123   last_lock_prefix = -1;
11124   last_repz_prefix = -1;
11125   last_repnz_prefix = -1;
11126   last_data_prefix = -1;
11127   last_addr_prefix = -1;
11128   last_rex_prefix = -1;
11129   last_seg_prefix = -1;
11130   fwait_prefix = -1;
11131   active_seg_prefix = 0;
11132   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11133     all_prefixes[i] = 0;
11134   i = 0;
11135   length = 0;
11136   /* The maximum instruction length is 15bytes.  */
11137   while (length < MAX_CODE_LENGTH - 1)
11138     {
11139       FETCH_DATA (the_info, codep + 1);
11140       newrex = 0;
11141       switch (*codep)
11142         {
11143         /* REX prefixes family.  */
11144         case 0x40:
11145         case 0x41:
11146         case 0x42:
11147         case 0x43:
11148         case 0x44:
11149         case 0x45:
11150         case 0x46:
11151         case 0x47:
11152         case 0x48:
11153         case 0x49:
11154         case 0x4a:
11155         case 0x4b:
11156         case 0x4c:
11157         case 0x4d:
11158         case 0x4e:
11159         case 0x4f:
11160           if (address_mode == mode_64bit)
11161             newrex = *codep;
11162           else
11163             return 1;
11164           last_rex_prefix = i;
11165           break;
11166         case 0xf3:
11167           prefixes |= PREFIX_REPZ;
11168           last_repz_prefix = i;
11169           break;
11170         case 0xf2:
11171           prefixes |= PREFIX_REPNZ;
11172           last_repnz_prefix = i;
11173           break;
11174         case 0xf0:
11175           prefixes |= PREFIX_LOCK;
11176           last_lock_prefix = i;
11177           break;
11178         case 0x2e:
11179           prefixes |= PREFIX_CS;
11180           last_seg_prefix = i;
11181           active_seg_prefix = PREFIX_CS;
11182           break;
11183         case 0x36:
11184           prefixes |= PREFIX_SS;
11185           last_seg_prefix = i;
11186           active_seg_prefix = PREFIX_SS;
11187           break;
11188         case 0x3e:
11189           prefixes |= PREFIX_DS;
11190           last_seg_prefix = i;
11191           active_seg_prefix = PREFIX_DS;
11192           break;
11193         case 0x26:
11194           prefixes |= PREFIX_ES;
11195           last_seg_prefix = i;
11196           active_seg_prefix = PREFIX_ES;
11197           break;
11198         case 0x64:
11199           prefixes |= PREFIX_FS;
11200           last_seg_prefix = i;
11201           active_seg_prefix = PREFIX_FS;
11202           break;
11203         case 0x65:
11204           prefixes |= PREFIX_GS;
11205           last_seg_prefix = i;
11206           active_seg_prefix = PREFIX_GS;
11207           break;
11208         case 0x66:
11209           prefixes |= PREFIX_DATA;
11210           last_data_prefix = i;
11211           break;
11212         case 0x67:
11213           prefixes |= PREFIX_ADDR;
11214           last_addr_prefix = i;
11215           break;
11216         case FWAIT_OPCODE:
11217           /* fwait is really an instruction.  If there are prefixes
11218              before the fwait, they belong to the fwait, *not* to the
11219              following instruction.  */
11220           fwait_prefix = i;
11221           if (prefixes || rex)
11222             {
11223               prefixes |= PREFIX_FWAIT;
11224               codep++;
11225               /* This ensures that the previous REX prefixes are noticed
11226                  as unused prefixes, as in the return case below.  */
11227               rex_used = rex;
11228               return 1;
11229             }
11230           prefixes = PREFIX_FWAIT;
11231           break;
11232         default:
11233           return 1;
11234         }
11235       /* Rex is ignored when followed by another prefix.  */
11236       if (rex)
11237         {
11238           rex_used = rex;
11239           return 1;
11240         }
11241       if (*codep != FWAIT_OPCODE)
11242         all_prefixes[i++] = *codep;
11243       rex = newrex;
11244       codep++;
11245       length++;
11246     }
11247   return 0;
11248 }
11249
11250 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11251    prefix byte.  */
11252
11253 static const char *
11254 prefix_name (int pref, int sizeflag)
11255 {
11256   static const char *rexes [16] =
11257     {
11258       "rex",            /* 0x40 */
11259       "rex.B",          /* 0x41 */
11260       "rex.X",          /* 0x42 */
11261       "rex.XB",         /* 0x43 */
11262       "rex.R",          /* 0x44 */
11263       "rex.RB",         /* 0x45 */
11264       "rex.RX",         /* 0x46 */
11265       "rex.RXB",        /* 0x47 */
11266       "rex.W",          /* 0x48 */
11267       "rex.WB",         /* 0x49 */
11268       "rex.WX",         /* 0x4a */
11269       "rex.WXB",        /* 0x4b */
11270       "rex.WR",         /* 0x4c */
11271       "rex.WRB",        /* 0x4d */
11272       "rex.WRX",        /* 0x4e */
11273       "rex.WRXB",       /* 0x4f */
11274     };
11275
11276   switch (pref)
11277     {
11278     /* REX prefixes family.  */
11279     case 0x40:
11280     case 0x41:
11281     case 0x42:
11282     case 0x43:
11283     case 0x44:
11284     case 0x45:
11285     case 0x46:
11286     case 0x47:
11287     case 0x48:
11288     case 0x49:
11289     case 0x4a:
11290     case 0x4b:
11291     case 0x4c:
11292     case 0x4d:
11293     case 0x4e:
11294     case 0x4f:
11295       return rexes [pref - 0x40];
11296     case 0xf3:
11297       return "repz";
11298     case 0xf2:
11299       return "repnz";
11300     case 0xf0:
11301       return "lock";
11302     case 0x2e:
11303       return "cs";
11304     case 0x36:
11305       return "ss";
11306     case 0x3e:
11307       return "ds";
11308     case 0x26:
11309       return "es";
11310     case 0x64:
11311       return "fs";
11312     case 0x65:
11313       return "gs";
11314     case 0x66:
11315       return (sizeflag & DFLAG) ? "data16" : "data32";
11316     case 0x67:
11317       if (address_mode == mode_64bit)
11318         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11319       else
11320         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11321     case FWAIT_OPCODE:
11322       return "fwait";
11323     case REP_PREFIX:
11324       return "rep";
11325     case XACQUIRE_PREFIX:
11326       return "xacquire";
11327     case XRELEASE_PREFIX:
11328       return "xrelease";
11329     case BND_PREFIX:
11330       return "bnd";
11331     case NOTRACK_PREFIX:
11332       return "notrack";
11333     default:
11334       return NULL;
11335     }
11336 }
11337
11338 static char op_out[MAX_OPERANDS][100];
11339 static int op_ad, op_index[MAX_OPERANDS];
11340 static int two_source_ops;
11341 static bfd_vma op_address[MAX_OPERANDS];
11342 static bfd_vma op_riprel[MAX_OPERANDS];
11343 static bfd_vma start_pc;
11344
11345 /*
11346  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11347  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11348  *   section of the "Virtual 8086 Mode" chapter.)
11349  * 'pc' should be the address of this instruction, it will
11350  *   be used to print the target address if this is a relative jump or call
11351  * The function returns the length of this instruction in bytes.
11352  */
11353
11354 static char intel_syntax;
11355 static char intel_mnemonic = !SYSV386_COMPAT;
11356 static char open_char;
11357 static char close_char;
11358 static char separator_char;
11359 static char scale_char;
11360
11361 enum x86_64_isa
11362 {
11363   amd64 = 0,
11364   intel64
11365 };
11366
11367 static enum x86_64_isa isa64;
11368
11369 /* Here for backwards compatibility.  When gdb stops using
11370    print_insn_i386_att and print_insn_i386_intel these functions can
11371    disappear, and print_insn_i386 be merged into print_insn.  */
11372 int
11373 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11374 {
11375   intel_syntax = 0;
11376
11377   return print_insn (pc, info);
11378 }
11379
11380 int
11381 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11382 {
11383   intel_syntax = 1;
11384
11385   return print_insn (pc, info);
11386 }
11387
11388 int
11389 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11390 {
11391   intel_syntax = -1;
11392
11393   return print_insn (pc, info);
11394 }
11395
11396 void
11397 print_i386_disassembler_options (FILE *stream)
11398 {
11399   fprintf (stream, _("\n\
11400 The following i386/x86-64 specific disassembler options are supported for use\n\
11401 with the -M switch (multiple options should be separated by commas):\n"));
11402
11403   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11404   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11405   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11406   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11407   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11408   fprintf (stream, _("  att-mnemonic\n"
11409                      "              Display instruction in AT&T mnemonic\n"));
11410   fprintf (stream, _("  intel-mnemonic\n"
11411                      "              Display instruction in Intel mnemonic\n"));
11412   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11413   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11414   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11415   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11416   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11417   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11418   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11419   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11420 }
11421
11422 /* Bad opcode.  */
11423 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11424
11425 /* Get a pointer to struct dis386 with a valid name.  */
11426
11427 static const struct dis386 *
11428 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11429 {
11430   int vindex, vex_table_index;
11431
11432   if (dp->name != NULL)
11433     return dp;
11434
11435   switch (dp->op[0].bytemode)
11436     {
11437     case USE_REG_TABLE:
11438       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11439       break;
11440
11441     case USE_MOD_TABLE:
11442       vindex = modrm.mod == 0x3 ? 1 : 0;
11443       dp = &mod_table[dp->op[1].bytemode][vindex];
11444       break;
11445
11446     case USE_RM_TABLE:
11447       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11448       break;
11449
11450     case USE_PREFIX_TABLE:
11451       if (need_vex)
11452         {
11453           /* The prefix in VEX is implicit.  */
11454           switch (vex.prefix)
11455             {
11456             case 0:
11457               vindex = 0;
11458               break;
11459             case REPE_PREFIX_OPCODE:
11460               vindex = 1;
11461               break;
11462             case DATA_PREFIX_OPCODE:
11463               vindex = 2;
11464               break;
11465             case REPNE_PREFIX_OPCODE:
11466               vindex = 3;
11467               break;
11468             default:
11469               abort ();
11470               break;
11471             }
11472         }
11473       else
11474         {
11475           int last_prefix = -1;
11476           int prefix = 0;
11477           vindex = 0;
11478           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11479              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11480              last one wins.  */
11481           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11482             {
11483               if (last_repz_prefix > last_repnz_prefix)
11484                 {
11485                   vindex = 1;
11486                   prefix = PREFIX_REPZ;
11487                   last_prefix = last_repz_prefix;
11488                 }
11489               else
11490                 {
11491                   vindex = 3;
11492                   prefix = PREFIX_REPNZ;
11493                   last_prefix = last_repnz_prefix;
11494                 }
11495
11496               /* Check if prefix should be ignored.  */
11497               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11498                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11499                    & prefix) != 0)
11500                 vindex = 0;
11501             }
11502
11503           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11504             {
11505               vindex = 2;
11506               prefix = PREFIX_DATA;
11507               last_prefix = last_data_prefix;
11508             }
11509
11510           if (vindex != 0)
11511             {
11512               used_prefixes |= prefix;
11513               all_prefixes[last_prefix] = 0;
11514             }
11515         }
11516       dp = &prefix_table[dp->op[1].bytemode][vindex];
11517       break;
11518
11519     case USE_X86_64_TABLE:
11520       vindex = address_mode == mode_64bit ? 1 : 0;
11521       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11522       break;
11523
11524     case USE_3BYTE_TABLE:
11525       FETCH_DATA (info, codep + 2);
11526       vindex = *codep++;
11527       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11528       end_codep = codep;
11529       modrm.mod = (*codep >> 6) & 3;
11530       modrm.reg = (*codep >> 3) & 7;
11531       modrm.rm = *codep & 7;
11532       break;
11533
11534     case USE_VEX_LEN_TABLE:
11535       if (!need_vex)
11536         abort ();
11537
11538       switch (vex.length)
11539         {
11540         case 128:
11541           vindex = 0;
11542           break;
11543         case 256:
11544           vindex = 1;
11545           break;
11546         default:
11547           abort ();
11548           break;
11549         }
11550
11551       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11552       break;
11553
11554     case USE_EVEX_LEN_TABLE:
11555       if (!vex.evex)
11556         abort ();
11557
11558       switch (vex.length)
11559         {
11560         case 128:
11561           vindex = 0;
11562           break;
11563         case 256:
11564           vindex = 1;
11565           break;
11566         case 512:
11567           vindex = 2;
11568           break;
11569         default:
11570           abort ();
11571           break;
11572         }
11573
11574       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11575       break;
11576
11577     case USE_XOP_8F_TABLE:
11578       FETCH_DATA (info, codep + 3);
11579       /* All bits in the REX prefix are ignored.  */
11580       rex_ignored = rex;
11581       rex = ~(*codep >> 5) & 0x7;
11582
11583       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11584       switch ((*codep & 0x1f))
11585         {
11586         default:
11587           dp = &bad_opcode;
11588           return dp;
11589         case 0x8:
11590           vex_table_index = XOP_08;
11591           break;
11592         case 0x9:
11593           vex_table_index = XOP_09;
11594           break;
11595         case 0xa:
11596           vex_table_index = XOP_0A;
11597           break;
11598         }
11599       codep++;
11600       vex.w = *codep & 0x80;
11601       if (vex.w && address_mode == mode_64bit)
11602         rex |= REX_W;
11603
11604       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11605       if (address_mode != mode_64bit)
11606         {
11607           /* In 16/32-bit mode REX_B is silently ignored.  */
11608           rex &= ~REX_B;
11609         }
11610
11611       vex.length = (*codep & 0x4) ? 256 : 128;
11612       switch ((*codep & 0x3))
11613         {
11614         case 0:
11615           break;
11616         case 1:
11617           vex.prefix = DATA_PREFIX_OPCODE;
11618           break;
11619         case 2:
11620           vex.prefix = REPE_PREFIX_OPCODE;
11621           break;
11622         case 3:
11623           vex.prefix = REPNE_PREFIX_OPCODE;
11624           break;
11625         }
11626       need_vex = 1;
11627       need_vex_reg = 1;
11628       codep++;
11629       vindex = *codep++;
11630       dp = &xop_table[vex_table_index][vindex];
11631
11632       end_codep = codep;
11633       FETCH_DATA (info, codep + 1);
11634       modrm.mod = (*codep >> 6) & 3;
11635       modrm.reg = (*codep >> 3) & 7;
11636       modrm.rm = *codep & 7;
11637       break;
11638
11639     case USE_VEX_C4_TABLE:
11640       /* VEX prefix.  */
11641       FETCH_DATA (info, codep + 3);
11642       /* All bits in the REX prefix are ignored.  */
11643       rex_ignored = rex;
11644       rex = ~(*codep >> 5) & 0x7;
11645       switch ((*codep & 0x1f))
11646         {
11647         default:
11648           dp = &bad_opcode;
11649           return dp;
11650         case 0x1:
11651           vex_table_index = VEX_0F;
11652           break;
11653         case 0x2:
11654           vex_table_index = VEX_0F38;
11655           break;
11656         case 0x3:
11657           vex_table_index = VEX_0F3A;
11658           break;
11659         }
11660       codep++;
11661       vex.w = *codep & 0x80;
11662       if (address_mode == mode_64bit)
11663         {
11664           if (vex.w)
11665             rex |= REX_W;
11666         }
11667       else
11668         {
11669           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11670              is ignored, other REX bits are 0 and the highest bit in
11671              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11672           rex = 0;
11673         }
11674       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11675       vex.length = (*codep & 0x4) ? 256 : 128;
11676       switch ((*codep & 0x3))
11677         {
11678         case 0:
11679           break;
11680         case 1:
11681           vex.prefix = DATA_PREFIX_OPCODE;
11682           break;
11683         case 2:
11684           vex.prefix = REPE_PREFIX_OPCODE;
11685           break;
11686         case 3:
11687           vex.prefix = REPNE_PREFIX_OPCODE;
11688           break;
11689         }
11690       need_vex = 1;
11691       need_vex_reg = 1;
11692       codep++;
11693       vindex = *codep++;
11694       dp = &vex_table[vex_table_index][vindex];
11695       end_codep = codep;
11696       /* There is no MODRM byte for VEX0F 77.  */
11697       if (vex_table_index != VEX_0F || vindex != 0x77)
11698         {
11699           FETCH_DATA (info, codep + 1);
11700           modrm.mod = (*codep >> 6) & 3;
11701           modrm.reg = (*codep >> 3) & 7;
11702           modrm.rm = *codep & 7;
11703         }
11704       break;
11705
11706     case USE_VEX_C5_TABLE:
11707       /* VEX prefix.  */
11708       FETCH_DATA (info, codep + 2);
11709       /* All bits in the REX prefix are ignored.  */
11710       rex_ignored = rex;
11711       rex = (*codep & 0x80) ? 0 : REX_R;
11712
11713       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11714          VEX.vvvv is 1.  */
11715       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11716       vex.length = (*codep & 0x4) ? 256 : 128;
11717       switch ((*codep & 0x3))
11718         {
11719         case 0:
11720           break;
11721         case 1:
11722           vex.prefix = DATA_PREFIX_OPCODE;
11723           break;
11724         case 2:
11725           vex.prefix = REPE_PREFIX_OPCODE;
11726           break;
11727         case 3:
11728           vex.prefix = REPNE_PREFIX_OPCODE;
11729           break;
11730         }
11731       need_vex = 1;
11732       need_vex_reg = 1;
11733       codep++;
11734       vindex = *codep++;
11735       dp = &vex_table[dp->op[1].bytemode][vindex];
11736       end_codep = codep;
11737       /* There is no MODRM byte for VEX 77.  */
11738       if (vindex != 0x77)
11739         {
11740           FETCH_DATA (info, codep + 1);
11741           modrm.mod = (*codep >> 6) & 3;
11742           modrm.reg = (*codep >> 3) & 7;
11743           modrm.rm = *codep & 7;
11744         }
11745       break;
11746
11747     case USE_VEX_W_TABLE:
11748       if (!need_vex)
11749         abort ();
11750
11751       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11752       break;
11753
11754     case USE_EVEX_TABLE:
11755       two_source_ops = 0;
11756       /* EVEX prefix.  */
11757       vex.evex = 1;
11758       FETCH_DATA (info, codep + 4);
11759       /* All bits in the REX prefix are ignored.  */
11760       rex_ignored = rex;
11761       /* The first byte after 0x62.  */
11762       rex = ~(*codep >> 5) & 0x7;
11763       vex.r = *codep & 0x10;
11764       switch ((*codep & 0xf))
11765         {
11766         default:
11767           return &bad_opcode;
11768         case 0x1:
11769           vex_table_index = EVEX_0F;
11770           break;
11771         case 0x2:
11772           vex_table_index = EVEX_0F38;
11773           break;
11774         case 0x3:
11775           vex_table_index = EVEX_0F3A;
11776           break;
11777         }
11778
11779       /* The second byte after 0x62.  */
11780       codep++;
11781       vex.w = *codep & 0x80;
11782       if (vex.w && address_mode == mode_64bit)
11783         rex |= REX_W;
11784
11785       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11786
11787       /* The U bit.  */
11788       if (!(*codep & 0x4))
11789         return &bad_opcode;
11790
11791       switch ((*codep & 0x3))
11792         {
11793         case 0:
11794           break;
11795         case 1:
11796           vex.prefix = DATA_PREFIX_OPCODE;
11797           break;
11798         case 2:
11799           vex.prefix = REPE_PREFIX_OPCODE;
11800           break;
11801         case 3:
11802           vex.prefix = REPNE_PREFIX_OPCODE;
11803           break;
11804         }
11805
11806       /* The third byte after 0x62.  */
11807       codep++;
11808
11809       /* Remember the static rounding bits.  */
11810       vex.ll = (*codep >> 5) & 3;
11811       vex.b = (*codep & 0x10) != 0;
11812
11813       vex.v = *codep & 0x8;
11814       vex.mask_register_specifier = *codep & 0x7;
11815       vex.zeroing = *codep & 0x80;
11816
11817       if (address_mode != mode_64bit)
11818         {
11819           /* In 16/32-bit mode silently ignore following bits.  */
11820           rex &= ~REX_B;
11821           vex.r = 1;
11822           vex.v = 1;
11823         }
11824
11825       need_vex = 1;
11826       need_vex_reg = 1;
11827       codep++;
11828       vindex = *codep++;
11829       dp = &evex_table[vex_table_index][vindex];
11830       end_codep = codep;
11831       FETCH_DATA (info, codep + 1);
11832       modrm.mod = (*codep >> 6) & 3;
11833       modrm.reg = (*codep >> 3) & 7;
11834       modrm.rm = *codep & 7;
11835
11836       /* Set vector length.  */
11837       if (modrm.mod == 3 && vex.b)
11838         vex.length = 512;
11839       else
11840         {
11841           switch (vex.ll)
11842             {
11843             case 0x0:
11844               vex.length = 128;
11845               break;
11846             case 0x1:
11847               vex.length = 256;
11848               break;
11849             case 0x2:
11850               vex.length = 512;
11851               break;
11852             default:
11853               return &bad_opcode;
11854             }
11855         }
11856       break;
11857
11858     case 0:
11859       dp = &bad_opcode;
11860       break;
11861
11862     default:
11863       abort ();
11864     }
11865
11866   if (dp->name != NULL)
11867     return dp;
11868   else
11869     return get_valid_dis386 (dp, info);
11870 }
11871
11872 static void
11873 get_sib (disassemble_info *info, int sizeflag)
11874 {
11875   /* If modrm.mod == 3, operand must be register.  */
11876   if (need_modrm
11877       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11878       && modrm.mod != 3
11879       && modrm.rm == 4)
11880     {
11881       FETCH_DATA (info, codep + 2);
11882       sib.index = (codep [1] >> 3) & 7;
11883       sib.scale = (codep [1] >> 6) & 3;
11884       sib.base = codep [1] & 7;
11885     }
11886 }
11887
11888 static int
11889 print_insn (bfd_vma pc, disassemble_info *info)
11890 {
11891   const struct dis386 *dp;
11892   int i;
11893   char *op_txt[MAX_OPERANDS];
11894   int needcomma;
11895   int sizeflag, orig_sizeflag;
11896   const char *p;
11897   struct dis_private priv;
11898   int prefix_length;
11899
11900   priv.orig_sizeflag = AFLAG | DFLAG;
11901   if ((info->mach & bfd_mach_i386_i386) != 0)
11902     address_mode = mode_32bit;
11903   else if (info->mach == bfd_mach_i386_i8086)
11904     {
11905       address_mode = mode_16bit;
11906       priv.orig_sizeflag = 0;
11907     }
11908   else
11909     address_mode = mode_64bit;
11910
11911   if (intel_syntax == (char) -1)
11912     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11913
11914   for (p = info->disassembler_options; p != NULL; )
11915     {
11916       if (CONST_STRNEQ (p, "amd64"))
11917         isa64 = amd64;
11918       else if (CONST_STRNEQ (p, "intel64"))
11919         isa64 = intel64;
11920       else if (CONST_STRNEQ (p, "x86-64"))
11921         {
11922           address_mode = mode_64bit;
11923           priv.orig_sizeflag = AFLAG | DFLAG;
11924         }
11925       else if (CONST_STRNEQ (p, "i386"))
11926         {
11927           address_mode = mode_32bit;
11928           priv.orig_sizeflag = AFLAG | DFLAG;
11929         }
11930       else if (CONST_STRNEQ (p, "i8086"))
11931         {
11932           address_mode = mode_16bit;
11933           priv.orig_sizeflag = 0;
11934         }
11935       else if (CONST_STRNEQ (p, "intel"))
11936         {
11937           intel_syntax = 1;
11938           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11939             intel_mnemonic = 1;
11940         }
11941       else if (CONST_STRNEQ (p, "att"))
11942         {
11943           intel_syntax = 0;
11944           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11945             intel_mnemonic = 0;
11946         }
11947       else if (CONST_STRNEQ (p, "addr"))
11948         {
11949           if (address_mode == mode_64bit)
11950             {
11951               if (p[4] == '3' && p[5] == '2')
11952                 priv.orig_sizeflag &= ~AFLAG;
11953               else if (p[4] == '6' && p[5] == '4')
11954                 priv.orig_sizeflag |= AFLAG;
11955             }
11956           else
11957             {
11958               if (p[4] == '1' && p[5] == '6')
11959                 priv.orig_sizeflag &= ~AFLAG;
11960               else if (p[4] == '3' && p[5] == '2')
11961                 priv.orig_sizeflag |= AFLAG;
11962             }
11963         }
11964       else if (CONST_STRNEQ (p, "data"))
11965         {
11966           if (p[4] == '1' && p[5] == '6')
11967             priv.orig_sizeflag &= ~DFLAG;
11968           else if (p[4] == '3' && p[5] == '2')
11969             priv.orig_sizeflag |= DFLAG;
11970         }
11971       else if (CONST_STRNEQ (p, "suffix"))
11972         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11973
11974       p = strchr (p, ',');
11975       if (p != NULL)
11976         p++;
11977     }
11978
11979   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11980     {
11981       (*info->fprintf_func) (info->stream,
11982                              _("64-bit address is disabled"));
11983       return -1;
11984     }
11985
11986   if (intel_syntax)
11987     {
11988       names64 = intel_names64;
11989       names32 = intel_names32;
11990       names16 = intel_names16;
11991       names8 = intel_names8;
11992       names8rex = intel_names8rex;
11993       names_seg = intel_names_seg;
11994       names_mm = intel_names_mm;
11995       names_bnd = intel_names_bnd;
11996       names_xmm = intel_names_xmm;
11997       names_ymm = intel_names_ymm;
11998       names_zmm = intel_names_zmm;
11999       index64 = intel_index64;
12000       index32 = intel_index32;
12001       names_mask = intel_names_mask;
12002       index16 = intel_index16;
12003       open_char = '[';
12004       close_char = ']';
12005       separator_char = '+';
12006       scale_char = '*';
12007     }
12008   else
12009     {
12010       names64 = att_names64;
12011       names32 = att_names32;
12012       names16 = att_names16;
12013       names8 = att_names8;
12014       names8rex = att_names8rex;
12015       names_seg = att_names_seg;
12016       names_mm = att_names_mm;
12017       names_bnd = att_names_bnd;
12018       names_xmm = att_names_xmm;
12019       names_ymm = att_names_ymm;
12020       names_zmm = att_names_zmm;
12021       index64 = att_index64;
12022       index32 = att_index32;
12023       names_mask = att_names_mask;
12024       index16 = att_index16;
12025       open_char = '(';
12026       close_char =  ')';
12027       separator_char = ',';
12028       scale_char = ',';
12029     }
12030
12031   /* The output looks better if we put 7 bytes on a line, since that
12032      puts most long word instructions on a single line.  Use 8 bytes
12033      for Intel L1OM.  */
12034   if ((info->mach & bfd_mach_l1om) != 0)
12035     info->bytes_per_line = 8;
12036   else
12037     info->bytes_per_line = 7;
12038
12039   info->private_data = &priv;
12040   priv.max_fetched = priv.the_buffer;
12041   priv.insn_start = pc;
12042
12043   obuf[0] = 0;
12044   for (i = 0; i < MAX_OPERANDS; ++i)
12045     {
12046       op_out[i][0] = 0;
12047       op_index[i] = -1;
12048     }
12049
12050   the_info = info;
12051   start_pc = pc;
12052   start_codep = priv.the_buffer;
12053   codep = priv.the_buffer;
12054
12055   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12056     {
12057       const char *name;
12058
12059       /* Getting here means we tried for data but didn't get it.  That
12060          means we have an incomplete instruction of some sort.  Just
12061          print the first byte as a prefix or a .byte pseudo-op.  */
12062       if (codep > priv.the_buffer)
12063         {
12064           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12065           if (name != NULL)
12066             (*info->fprintf_func) (info->stream, "%s", name);
12067           else
12068             {
12069               /* Just print the first byte as a .byte instruction.  */
12070               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12071                                      (unsigned int) priv.the_buffer[0]);
12072             }
12073
12074           return 1;
12075         }
12076
12077       return -1;
12078     }
12079
12080   obufp = obuf;
12081   sizeflag = priv.orig_sizeflag;
12082
12083   if (!ckprefix () || rex_used)
12084     {
12085       /* Too many prefixes or unused REX prefixes.  */
12086       for (i = 0;
12087            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12088            i++)
12089         (*info->fprintf_func) (info->stream, "%s%s",
12090                                i == 0 ? "" : " ",
12091                                prefix_name (all_prefixes[i], sizeflag));
12092       return i;
12093     }
12094
12095   insn_codep = codep;
12096
12097   FETCH_DATA (info, codep + 1);
12098   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12099
12100   if (((prefixes & PREFIX_FWAIT)
12101        && ((*codep < 0xd8) || (*codep > 0xdf))))
12102     {
12103       /* Handle prefixes before fwait.  */
12104       for (i = 0; i < fwait_prefix && all_prefixes[i];
12105            i++)
12106         (*info->fprintf_func) (info->stream, "%s ",
12107                                prefix_name (all_prefixes[i], sizeflag));
12108       (*info->fprintf_func) (info->stream, "fwait");
12109       return i + 1;
12110     }
12111
12112   if (*codep == 0x0f)
12113     {
12114       unsigned char threebyte;
12115
12116       codep++;
12117       FETCH_DATA (info, codep + 1);
12118       threebyte = *codep;
12119       dp = &dis386_twobyte[threebyte];
12120       need_modrm = twobyte_has_modrm[*codep];
12121       codep++;
12122     }
12123   else
12124     {
12125       dp = &dis386[*codep];
12126       need_modrm = onebyte_has_modrm[*codep];
12127       codep++;
12128     }
12129
12130   /* Save sizeflag for printing the extra prefixes later before updating
12131      it for mnemonic and operand processing.  The prefix names depend
12132      only on the address mode.  */
12133   orig_sizeflag = sizeflag;
12134   if (prefixes & PREFIX_ADDR)
12135     sizeflag ^= AFLAG;
12136   if ((prefixes & PREFIX_DATA))
12137     sizeflag ^= DFLAG;
12138
12139   end_codep = codep;
12140   if (need_modrm)
12141     {
12142       FETCH_DATA (info, codep + 1);
12143       modrm.mod = (*codep >> 6) & 3;
12144       modrm.reg = (*codep >> 3) & 7;
12145       modrm.rm = *codep & 7;
12146     }
12147
12148   need_vex = 0;
12149   need_vex_reg = 0;
12150   vex_w_done = 0;
12151   memset (&vex, 0, sizeof (vex));
12152
12153   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12154     {
12155       get_sib (info, sizeflag);
12156       dofloat (sizeflag);
12157     }
12158   else
12159     {
12160       dp = get_valid_dis386 (dp, info);
12161       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12162         {
12163           get_sib (info, sizeflag);
12164           for (i = 0; i < MAX_OPERANDS; ++i)
12165             {
12166               obufp = op_out[i];
12167               op_ad = MAX_OPERANDS - 1 - i;
12168               if (dp->op[i].rtn)
12169                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12170               /* For EVEX instruction after the last operand masking
12171                  should be printed.  */
12172               if (i == 0 && vex.evex)
12173                 {
12174                   /* Don't print {%k0}.  */
12175                   if (vex.mask_register_specifier)
12176                     {
12177                       oappend ("{");
12178                       oappend (names_mask[vex.mask_register_specifier]);
12179                       oappend ("}");
12180                     }
12181                   if (vex.zeroing)
12182                     oappend ("{z}");
12183                 }
12184             }
12185         }
12186     }
12187
12188   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12189      are all 0s in inverted form.  */
12190   if (need_vex && vex.register_specifier != 0)
12191     {
12192       (*info->fprintf_func) (info->stream, "(bad)");
12193       return end_codep - priv.the_buffer;
12194     }
12195
12196   /* Check if the REX prefix is used.  */
12197   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12198     all_prefixes[last_rex_prefix] = 0;
12199
12200   /* Check if the SEG prefix is used.  */
12201   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12202                    | PREFIX_FS | PREFIX_GS)) != 0
12203       && (used_prefixes & active_seg_prefix) != 0)
12204     all_prefixes[last_seg_prefix] = 0;
12205
12206   /* Check if the ADDR prefix is used.  */
12207   if ((prefixes & PREFIX_ADDR) != 0
12208       && (used_prefixes & PREFIX_ADDR) != 0)
12209     all_prefixes[last_addr_prefix] = 0;
12210
12211   /* Check if the DATA prefix is used.  */
12212   if ((prefixes & PREFIX_DATA) != 0
12213       && (used_prefixes & PREFIX_DATA) != 0)
12214     all_prefixes[last_data_prefix] = 0;
12215
12216   /* Print the extra prefixes.  */
12217   prefix_length = 0;
12218   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12219     if (all_prefixes[i])
12220       {
12221         const char *name;
12222         name = prefix_name (all_prefixes[i], orig_sizeflag);
12223         if (name == NULL)
12224           abort ();
12225         prefix_length += strlen (name) + 1;
12226         (*info->fprintf_func) (info->stream, "%s ", name);
12227       }
12228
12229   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12230      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12231      used by putop and MMX/SSE operand and may be overriden by the
12232      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12233      separately.  */
12234   if (dp->prefix_requirement == PREFIX_OPCODE
12235       && dp != &bad_opcode
12236       && (((prefixes
12237             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12238            && (used_prefixes
12239                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12240           || ((((prefixes
12241                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12242                 == PREFIX_DATA)
12243                && (used_prefixes & PREFIX_DATA) == 0))))
12244     {
12245       (*info->fprintf_func) (info->stream, "(bad)");
12246       return end_codep - priv.the_buffer;
12247     }
12248
12249   /* Check maximum code length.  */
12250   if ((codep - start_codep) > MAX_CODE_LENGTH)
12251     {
12252       (*info->fprintf_func) (info->stream, "(bad)");
12253       return MAX_CODE_LENGTH;
12254     }
12255
12256   obufp = mnemonicendp;
12257   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12258     oappend (" ");
12259   oappend (" ");
12260   (*info->fprintf_func) (info->stream, "%s", obuf);
12261
12262   /* The enter and bound instructions are printed with operands in the same
12263      order as the intel book; everything else is printed in reverse order.  */
12264   if (intel_syntax || two_source_ops)
12265     {
12266       bfd_vma riprel;
12267
12268       for (i = 0; i < MAX_OPERANDS; ++i)
12269         op_txt[i] = op_out[i];
12270
12271       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12272           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12273         {
12274           op_txt[2] = op_out[3];
12275           op_txt[3] = op_out[2];
12276         }
12277
12278       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12279         {
12280           op_ad = op_index[i];
12281           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12282           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12283           riprel = op_riprel[i];
12284           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12285           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12286         }
12287     }
12288   else
12289     {
12290       for (i = 0; i < MAX_OPERANDS; ++i)
12291         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12292     }
12293
12294   needcomma = 0;
12295   for (i = 0; i < MAX_OPERANDS; ++i)
12296     if (*op_txt[i])
12297       {
12298         if (needcomma)
12299           (*info->fprintf_func) (info->stream, ",");
12300         if (op_index[i] != -1 && !op_riprel[i])
12301           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12302         else
12303           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12304         needcomma = 1;
12305       }
12306
12307   for (i = 0; i < MAX_OPERANDS; i++)
12308     if (op_index[i] != -1 && op_riprel[i])
12309       {
12310         (*info->fprintf_func) (info->stream, "        # ");
12311         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12312                                                 + op_address[op_index[i]]), info);
12313         break;
12314       }
12315   return codep - priv.the_buffer;
12316 }
12317
12318 static const char *float_mem[] = {
12319   /* d8 */
12320   "fadd{s|}",
12321   "fmul{s|}",
12322   "fcom{s|}",
12323   "fcomp{s|}",
12324   "fsub{s|}",
12325   "fsubr{s|}",
12326   "fdiv{s|}",
12327   "fdivr{s|}",
12328   /* d9 */
12329   "fld{s|}",
12330   "(bad)",
12331   "fst{s|}",
12332   "fstp{s|}",
12333   "fldenvIC",
12334   "fldcw",
12335   "fNstenvIC",
12336   "fNstcw",
12337   /* da */
12338   "fiadd{l|}",
12339   "fimul{l|}",
12340   "ficom{l|}",
12341   "ficomp{l|}",
12342   "fisub{l|}",
12343   "fisubr{l|}",
12344   "fidiv{l|}",
12345   "fidivr{l|}",
12346   /* db */
12347   "fild{l|}",
12348   "fisttp{l|}",
12349   "fist{l|}",
12350   "fistp{l|}",
12351   "(bad)",
12352   "fld{t||t|}",
12353   "(bad)",
12354   "fstp{t||t|}",
12355   /* dc */
12356   "fadd{l|}",
12357   "fmul{l|}",
12358   "fcom{l|}",
12359   "fcomp{l|}",
12360   "fsub{l|}",
12361   "fsubr{l|}",
12362   "fdiv{l|}",
12363   "fdivr{l|}",
12364   /* dd */
12365   "fld{l|}",
12366   "fisttp{ll|}",
12367   "fst{l||}",
12368   "fstp{l|}",
12369   "frstorIC",
12370   "(bad)",
12371   "fNsaveIC",
12372   "fNstsw",
12373   /* de */
12374   "fiadd{s|}",
12375   "fimul{s|}",
12376   "ficom{s|}",
12377   "ficomp{s|}",
12378   "fisub{s|}",
12379   "fisubr{s|}",
12380   "fidiv{s|}",
12381   "fidivr{s|}",
12382   /* df */
12383   "fild{s|}",
12384   "fisttp{s|}",
12385   "fist{s|}",
12386   "fistp{s|}",
12387   "fbld",
12388   "fild{ll|}",
12389   "fbstp",
12390   "fistp{ll|}",
12391 };
12392
12393 static const unsigned char float_mem_mode[] = {
12394   /* d8 */
12395   d_mode,
12396   d_mode,
12397   d_mode,
12398   d_mode,
12399   d_mode,
12400   d_mode,
12401   d_mode,
12402   d_mode,
12403   /* d9 */
12404   d_mode,
12405   0,
12406   d_mode,
12407   d_mode,
12408   0,
12409   w_mode,
12410   0,
12411   w_mode,
12412   /* da */
12413   d_mode,
12414   d_mode,
12415   d_mode,
12416   d_mode,
12417   d_mode,
12418   d_mode,
12419   d_mode,
12420   d_mode,
12421   /* db */
12422   d_mode,
12423   d_mode,
12424   d_mode,
12425   d_mode,
12426   0,
12427   t_mode,
12428   0,
12429   t_mode,
12430   /* dc */
12431   q_mode,
12432   q_mode,
12433   q_mode,
12434   q_mode,
12435   q_mode,
12436   q_mode,
12437   q_mode,
12438   q_mode,
12439   /* dd */
12440   q_mode,
12441   q_mode,
12442   q_mode,
12443   q_mode,
12444   0,
12445   0,
12446   0,
12447   w_mode,
12448   /* de */
12449   w_mode,
12450   w_mode,
12451   w_mode,
12452   w_mode,
12453   w_mode,
12454   w_mode,
12455   w_mode,
12456   w_mode,
12457   /* df */
12458   w_mode,
12459   w_mode,
12460   w_mode,
12461   w_mode,
12462   t_mode,
12463   q_mode,
12464   t_mode,
12465   q_mode
12466 };
12467
12468 #define ST { OP_ST, 0 }
12469 #define STi { OP_STi, 0 }
12470
12471 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12472 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12473 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12474 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12475 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12476 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12477 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12478 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12479 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12480
12481 static const struct dis386 float_reg[][8] = {
12482   /* d8 */
12483   {
12484     { "fadd",   { ST, STi }, 0 },
12485     { "fmul",   { ST, STi }, 0 },
12486     { "fcom",   { STi }, 0 },
12487     { "fcomp",  { STi }, 0 },
12488     { "fsub",   { ST, STi }, 0 },
12489     { "fsubr",  { ST, STi }, 0 },
12490     { "fdiv",   { ST, STi }, 0 },
12491     { "fdivr",  { ST, STi }, 0 },
12492   },
12493   /* d9 */
12494   {
12495     { "fld",    { STi }, 0 },
12496     { "fxch",   { STi }, 0 },
12497     { FGRPd9_2 },
12498     { Bad_Opcode },
12499     { FGRPd9_4 },
12500     { FGRPd9_5 },
12501     { FGRPd9_6 },
12502     { FGRPd9_7 },
12503   },
12504   /* da */
12505   {
12506     { "fcmovb", { ST, STi }, 0 },
12507     { "fcmove", { ST, STi }, 0 },
12508     { "fcmovbe",{ ST, STi }, 0 },
12509     { "fcmovu", { ST, STi }, 0 },
12510     { Bad_Opcode },
12511     { FGRPda_5 },
12512     { Bad_Opcode },
12513     { Bad_Opcode },
12514   },
12515   /* db */
12516   {
12517     { "fcmovnb",{ ST, STi }, 0 },
12518     { "fcmovne",{ ST, STi }, 0 },
12519     { "fcmovnbe",{ ST, STi }, 0 },
12520     { "fcmovnu",{ ST, STi }, 0 },
12521     { FGRPdb_4 },
12522     { "fucomi", { ST, STi }, 0 },
12523     { "fcomi",  { ST, STi }, 0 },
12524     { Bad_Opcode },
12525   },
12526   /* dc */
12527   {
12528     { "fadd",   { STi, ST }, 0 },
12529     { "fmul",   { STi, ST }, 0 },
12530     { Bad_Opcode },
12531     { Bad_Opcode },
12532     { "fsub{!M|r}",     { STi, ST }, 0 },
12533     { "fsub{M|}",       { STi, ST }, 0 },
12534     { "fdiv{!M|r}",     { STi, ST }, 0 },
12535     { "fdiv{M|}",       { STi, ST }, 0 },
12536   },
12537   /* dd */
12538   {
12539     { "ffree",  { STi }, 0 },
12540     { Bad_Opcode },
12541     { "fst",    { STi }, 0 },
12542     { "fstp",   { STi }, 0 },
12543     { "fucom",  { STi }, 0 },
12544     { "fucomp", { STi }, 0 },
12545     { Bad_Opcode },
12546     { Bad_Opcode },
12547   },
12548   /* de */
12549   {
12550     { "faddp",  { STi, ST }, 0 },
12551     { "fmulp",  { STi, ST }, 0 },
12552     { Bad_Opcode },
12553     { FGRPde_3 },
12554     { "fsub{!M|r}p",    { STi, ST }, 0 },
12555     { "fsub{M|}p",      { STi, ST }, 0 },
12556     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12557     { "fdiv{M|}p",      { STi, ST }, 0 },
12558   },
12559   /* df */
12560   {
12561     { "ffreep", { STi }, 0 },
12562     { Bad_Opcode },
12563     { Bad_Opcode },
12564     { Bad_Opcode },
12565     { FGRPdf_4 },
12566     { "fucomip", { ST, STi }, 0 },
12567     { "fcomip", { ST, STi }, 0 },
12568     { Bad_Opcode },
12569   },
12570 };
12571
12572 static char *fgrps[][8] = {
12573   /* Bad opcode 0 */
12574   {
12575     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12576   },
12577
12578   /* d9_2  1 */
12579   {
12580     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12581   },
12582
12583   /* d9_4  2 */
12584   {
12585     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12586   },
12587
12588   /* d9_5  3 */
12589   {
12590     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12591   },
12592
12593   /* d9_6  4 */
12594   {
12595     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12596   },
12597
12598   /* d9_7  5 */
12599   {
12600     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12601   },
12602
12603   /* da_5  6 */
12604   {
12605     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12606   },
12607
12608   /* db_4  7 */
12609   {
12610     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12611     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12612   },
12613
12614   /* de_3  8 */
12615   {
12616     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12617   },
12618
12619   /* df_4  9 */
12620   {
12621     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12622   },
12623 };
12624
12625 static void
12626 swap_operand (void)
12627 {
12628   mnemonicendp[0] = '.';
12629   mnemonicendp[1] = 's';
12630   mnemonicendp += 2;
12631 }
12632
12633 static void
12634 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12635                int sizeflag ATTRIBUTE_UNUSED)
12636 {
12637   /* Skip mod/rm byte.  */
12638   MODRM_CHECK;
12639   codep++;
12640 }
12641
12642 static void
12643 dofloat (int sizeflag)
12644 {
12645   const struct dis386 *dp;
12646   unsigned char floatop;
12647
12648   floatop = codep[-1];
12649
12650   if (modrm.mod != 3)
12651     {
12652       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12653
12654       putop (float_mem[fp_indx], sizeflag);
12655       obufp = op_out[0];
12656       op_ad = 2;
12657       OP_E (float_mem_mode[fp_indx], sizeflag);
12658       return;
12659     }
12660   /* Skip mod/rm byte.  */
12661   MODRM_CHECK;
12662   codep++;
12663
12664   dp = &float_reg[floatop - 0xd8][modrm.reg];
12665   if (dp->name == NULL)
12666     {
12667       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12668
12669       /* Instruction fnstsw is only one with strange arg.  */
12670       if (floatop == 0xdf && codep[-1] == 0xe0)
12671         strcpy (op_out[0], names16[0]);
12672     }
12673   else
12674     {
12675       putop (dp->name, sizeflag);
12676
12677       obufp = op_out[0];
12678       op_ad = 2;
12679       if (dp->op[0].rtn)
12680         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12681
12682       obufp = op_out[1];
12683       op_ad = 1;
12684       if (dp->op[1].rtn)
12685         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12686     }
12687 }
12688
12689 /* Like oappend (below), but S is a string starting with '%'.
12690    In Intel syntax, the '%' is elided.  */
12691 static void
12692 oappend_maybe_intel (const char *s)
12693 {
12694   oappend (s + intel_syntax);
12695 }
12696
12697 static void
12698 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12699 {
12700   oappend_maybe_intel ("%st");
12701 }
12702
12703 static void
12704 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12705 {
12706   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12707   oappend_maybe_intel (scratchbuf);
12708 }
12709
12710 /* Capital letters in template are macros.  */
12711 static int
12712 putop (const char *in_template, int sizeflag)
12713 {
12714   const char *p;
12715   int alt = 0;
12716   int cond = 1;
12717   unsigned int l = 0, len = 1;
12718   char last[4];
12719
12720 #define SAVE_LAST(c)                    \
12721   if (l < len && l < sizeof (last))     \
12722     last[l++] = c;                      \
12723   else                                  \
12724     abort ();
12725
12726   for (p = in_template; *p; p++)
12727     {
12728       switch (*p)
12729         {
12730         default:
12731           *obufp++ = *p;
12732           break;
12733         case '%':
12734           len++;
12735           break;
12736         case '!':
12737           cond = 0;
12738           break;
12739         case '{':
12740           if (intel_syntax)
12741             {
12742               while (*++p != '|')
12743                 if (*p == '}' || *p == '\0')
12744                   abort ();
12745             }
12746           /* Fall through.  */
12747         case 'I':
12748           alt = 1;
12749           continue;
12750         case '|':
12751           while (*++p != '}')
12752             {
12753               if (*p == '\0')
12754                 abort ();
12755             }
12756           break;
12757         case '}':
12758           break;
12759         case 'A':
12760           if (intel_syntax)
12761             break;
12762           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12763             *obufp++ = 'b';
12764           break;
12765         case 'B':
12766           if (l == 0 && len == 1)
12767             {
12768 case_B:
12769               if (intel_syntax)
12770                 break;
12771               if (sizeflag & SUFFIX_ALWAYS)
12772                 *obufp++ = 'b';
12773             }
12774           else
12775             {
12776               if (l != 1
12777                   || len != 2
12778                   || last[0] != 'L')
12779                 {
12780                   SAVE_LAST (*p);
12781                   break;
12782                 }
12783
12784               if (address_mode == mode_64bit
12785                   && !(prefixes & PREFIX_ADDR))
12786                 {
12787                   *obufp++ = 'a';
12788                   *obufp++ = 'b';
12789                   *obufp++ = 's';
12790                 }
12791
12792               goto case_B;
12793             }
12794           break;
12795         case 'C':
12796           if (intel_syntax && !alt)
12797             break;
12798           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12799             {
12800               if (sizeflag & DFLAG)
12801                 *obufp++ = intel_syntax ? 'd' : 'l';
12802               else
12803                 *obufp++ = intel_syntax ? 'w' : 's';
12804               used_prefixes |= (prefixes & PREFIX_DATA);
12805             }
12806           break;
12807         case 'D':
12808           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12809             break;
12810           USED_REX (REX_W);
12811           if (modrm.mod == 3)
12812             {
12813               if (rex & REX_W)
12814                 *obufp++ = 'q';
12815               else
12816                 {
12817                   if (sizeflag & DFLAG)
12818                     *obufp++ = intel_syntax ? 'd' : 'l';
12819                   else
12820                     *obufp++ = 'w';
12821                   used_prefixes |= (prefixes & PREFIX_DATA);
12822                 }
12823             }
12824           else
12825             *obufp++ = 'w';
12826           break;
12827         case 'E':               /* For jcxz/jecxz */
12828           if (address_mode == mode_64bit)
12829             {
12830               if (sizeflag & AFLAG)
12831                 *obufp++ = 'r';
12832               else
12833                 *obufp++ = 'e';
12834             }
12835           else
12836             if (sizeflag & AFLAG)
12837               *obufp++ = 'e';
12838           used_prefixes |= (prefixes & PREFIX_ADDR);
12839           break;
12840         case 'F':
12841           if (intel_syntax)
12842             break;
12843           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12844             {
12845               if (sizeflag & AFLAG)
12846                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12847               else
12848                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12849               used_prefixes |= (prefixes & PREFIX_ADDR);
12850             }
12851           break;
12852         case 'G':
12853           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12854             break;
12855           if ((rex & REX_W) || (sizeflag & DFLAG))
12856             *obufp++ = 'l';
12857           else
12858             *obufp++ = 'w';
12859           if (!(rex & REX_W))
12860             used_prefixes |= (prefixes & PREFIX_DATA);
12861           break;
12862         case 'H':
12863           if (intel_syntax)
12864             break;
12865           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12866               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12867             {
12868               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12869               *obufp++ = ',';
12870               *obufp++ = 'p';
12871               if (prefixes & PREFIX_DS)
12872                 *obufp++ = 't';
12873               else
12874                 *obufp++ = 'n';
12875             }
12876           break;
12877         case 'J':
12878           if (intel_syntax)
12879             break;
12880           *obufp++ = 'l';
12881           break;
12882         case 'K':
12883           USED_REX (REX_W);
12884           if (rex & REX_W)
12885             *obufp++ = 'q';
12886           else
12887             *obufp++ = 'd';
12888           break;
12889         case 'Z':
12890           if (l != 0 || len != 1)
12891             {
12892               if (l != 1 || len != 2 || last[0] != 'X')
12893                 {
12894                   SAVE_LAST (*p);
12895                   break;
12896                 }
12897               if (!need_vex || !vex.evex)
12898                 abort ();
12899               if (intel_syntax
12900                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12901                 break;
12902               switch (vex.length)
12903                 {
12904                 case 128:
12905                   *obufp++ = 'x';
12906                   break;
12907                 case 256:
12908                   *obufp++ = 'y';
12909                   break;
12910                 case 512:
12911                   *obufp++ = 'z';
12912                   break;
12913                 default:
12914                   abort ();
12915                 }
12916               break;
12917             }
12918           if (intel_syntax)
12919             break;
12920           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12921             {
12922               *obufp++ = 'q';
12923               break;
12924             }
12925           /* Fall through.  */
12926           goto case_L;
12927         case 'L':
12928           if (l != 0 || len != 1)
12929             {
12930               SAVE_LAST (*p);
12931               break;
12932             }
12933 case_L:
12934           if (intel_syntax)
12935             break;
12936           if (sizeflag & SUFFIX_ALWAYS)
12937             *obufp++ = 'l';
12938           break;
12939         case 'M':
12940           if (intel_mnemonic != cond)
12941             *obufp++ = 'r';
12942           break;
12943         case 'N':
12944           if ((prefixes & PREFIX_FWAIT) == 0)
12945             *obufp++ = 'n';
12946           else
12947             used_prefixes |= PREFIX_FWAIT;
12948           break;
12949         case 'O':
12950           USED_REX (REX_W);
12951           if (rex & REX_W)
12952             *obufp++ = 'o';
12953           else if (intel_syntax && (sizeflag & DFLAG))
12954             *obufp++ = 'q';
12955           else
12956             *obufp++ = 'd';
12957           if (!(rex & REX_W))
12958             used_prefixes |= (prefixes & PREFIX_DATA);
12959           break;
12960         case '&':
12961           if (!intel_syntax
12962               && address_mode == mode_64bit
12963               && isa64 == intel64)
12964             {
12965               *obufp++ = 'q';
12966               break;
12967             }
12968           /* Fall through.  */
12969         case 'T':
12970           if (!intel_syntax
12971               && address_mode == mode_64bit
12972               && ((sizeflag & DFLAG) || (rex & REX_W)))
12973             {
12974               *obufp++ = 'q';
12975               break;
12976             }
12977           /* Fall through.  */
12978           goto case_P;
12979         case 'P':
12980           if (l == 0 && len == 1)
12981             {
12982 case_P:
12983               if (intel_syntax)
12984                 {
12985                   if ((rex & REX_W) == 0
12986                       && (prefixes & PREFIX_DATA))
12987                     {
12988                       if ((sizeflag & DFLAG) == 0)
12989                         *obufp++ = 'w';
12990                       used_prefixes |= (prefixes & PREFIX_DATA);
12991                     }
12992                   break;
12993                 }
12994               if ((prefixes & PREFIX_DATA)
12995                   || (rex & REX_W)
12996                   || (sizeflag & SUFFIX_ALWAYS))
12997                 {
12998                   USED_REX (REX_W);
12999                   if (rex & REX_W)
13000                     *obufp++ = 'q';
13001                   else
13002                     {
13003                       if (sizeflag & DFLAG)
13004                         *obufp++ = 'l';
13005                       else
13006                         *obufp++ = 'w';
13007                       used_prefixes |= (prefixes & PREFIX_DATA);
13008                     }
13009                 }
13010             }
13011           else
13012             {
13013               if (l != 1 || len != 2 || last[0] != 'L')
13014                 {
13015                   SAVE_LAST (*p);
13016                   break;
13017                 }
13018
13019               if ((prefixes & PREFIX_DATA)
13020                   || (rex & REX_W)
13021                   || (sizeflag & SUFFIX_ALWAYS))
13022                 {
13023                   USED_REX (REX_W);
13024                   if (rex & REX_W)
13025                     *obufp++ = 'q';
13026                   else
13027                     {
13028                       if (sizeflag & DFLAG)
13029                         *obufp++ = intel_syntax ? 'd' : 'l';
13030                       else
13031                         *obufp++ = 'w';
13032                       used_prefixes |= (prefixes & PREFIX_DATA);
13033                     }
13034                 }
13035             }
13036           break;
13037         case 'U':
13038           if (intel_syntax)
13039             break;
13040           if (address_mode == mode_64bit
13041               && ((sizeflag & DFLAG) || (rex & REX_W)))
13042             {
13043               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13044                 *obufp++ = 'q';
13045               break;
13046             }
13047           /* Fall through.  */
13048           goto case_Q;
13049         case 'Q':
13050           if (l == 0 && len == 1)
13051             {
13052 case_Q:
13053               if (intel_syntax && !alt)
13054                 break;
13055               USED_REX (REX_W);
13056               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13057                 {
13058                   if (rex & REX_W)
13059                     *obufp++ = 'q';
13060                   else
13061                     {
13062                       if (sizeflag & DFLAG)
13063                         *obufp++ = intel_syntax ? 'd' : 'l';
13064                       else
13065                         *obufp++ = 'w';
13066                       used_prefixes |= (prefixes & PREFIX_DATA);
13067                     }
13068                 }
13069             }
13070           else
13071             {
13072               if (l != 1 || len != 2 || last[0] != 'L')
13073                 {
13074                   SAVE_LAST (*p);
13075                   break;
13076                 }
13077               if (intel_syntax
13078                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13079                 break;
13080               if ((rex & REX_W))
13081                 {
13082                   USED_REX (REX_W);
13083                   *obufp++ = 'q';
13084                 }
13085               else
13086                 *obufp++ = 'l';
13087             }
13088           break;
13089         case 'R':
13090           USED_REX (REX_W);
13091           if (rex & REX_W)
13092             *obufp++ = 'q';
13093           else if (sizeflag & DFLAG)
13094             {
13095               if (intel_syntax)
13096                   *obufp++ = 'd';
13097               else
13098                   *obufp++ = 'l';
13099             }
13100           else
13101             *obufp++ = 'w';
13102           if (intel_syntax && !p[1]
13103               && ((rex & REX_W) || (sizeflag & DFLAG)))
13104             *obufp++ = 'e';
13105           if (!(rex & REX_W))
13106             used_prefixes |= (prefixes & PREFIX_DATA);
13107           break;
13108         case 'V':
13109           if (l == 0 && len == 1)
13110             {
13111               if (intel_syntax)
13112                 break;
13113               if (address_mode == mode_64bit
13114                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13115                 {
13116                   if (sizeflag & SUFFIX_ALWAYS)
13117                     *obufp++ = 'q';
13118                   break;
13119                 }
13120             }
13121           else
13122             {
13123               if (l != 1
13124                   || len != 2
13125                   || last[0] != 'L')
13126                 {
13127                   SAVE_LAST (*p);
13128                   break;
13129                 }
13130
13131               if (rex & REX_W)
13132                 {
13133                   *obufp++ = 'a';
13134                   *obufp++ = 'b';
13135                   *obufp++ = 's';
13136                 }
13137             }
13138           /* Fall through.  */
13139           goto case_S;
13140         case 'S':
13141           if (l == 0 && len == 1)
13142             {
13143 case_S:
13144               if (intel_syntax)
13145                 break;
13146               if (sizeflag & SUFFIX_ALWAYS)
13147                 {
13148                   if (rex & REX_W)
13149                     *obufp++ = 'q';
13150                   else
13151                     {
13152                       if (sizeflag & DFLAG)
13153                         *obufp++ = 'l';
13154                       else
13155                         *obufp++ = 'w';
13156                       used_prefixes |= (prefixes & PREFIX_DATA);
13157                     }
13158                 }
13159             }
13160           else
13161             {
13162               if (l != 1
13163                   || len != 2
13164                   || last[0] != 'L')
13165                 {
13166                   SAVE_LAST (*p);
13167                   break;
13168                 }
13169
13170               if (address_mode == mode_64bit
13171                   && !(prefixes & PREFIX_ADDR))
13172                 {
13173                   *obufp++ = 'a';
13174                   *obufp++ = 'b';
13175                   *obufp++ = 's';
13176                 }
13177
13178               goto case_S;
13179             }
13180           break;
13181         case 'X':
13182           if (l != 0 || len != 1)
13183             {
13184               SAVE_LAST (*p);
13185               break;
13186             }
13187           if (need_vex && vex.prefix)
13188             {
13189               if (vex.prefix == DATA_PREFIX_OPCODE)
13190                 *obufp++ = 'd';
13191               else
13192                 *obufp++ = 's';
13193             }
13194           else
13195             {
13196               if (prefixes & PREFIX_DATA)
13197                 *obufp++ = 'd';
13198               else
13199                 *obufp++ = 's';
13200               used_prefixes |= (prefixes & PREFIX_DATA);
13201             }
13202           break;
13203         case 'Y':
13204           if (l == 0 && len == 1)
13205             abort ();
13206           else
13207             {
13208               if (l != 1 || len != 2 || last[0] != 'X')
13209                 {
13210                   SAVE_LAST (*p);
13211                   break;
13212                 }
13213               if (!need_vex)
13214                 abort ();
13215               if (intel_syntax
13216                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13217                 break;
13218               switch (vex.length)
13219                 {
13220                 case 128:
13221                   *obufp++ = 'x';
13222                   break;
13223                 case 256:
13224                   *obufp++ = 'y';
13225                   break;
13226                 case 512:
13227                   if (!vex.evex)
13228                 default:
13229                     abort ();
13230                 }
13231             }
13232           break;
13233         case 'W':
13234           if (l == 0 && len == 1)
13235             {
13236               /* operand size flag for cwtl, cbtw */
13237               USED_REX (REX_W);
13238               if (rex & REX_W)
13239                 {
13240                   if (intel_syntax)
13241                     *obufp++ = 'd';
13242                   else
13243                     *obufp++ = 'l';
13244                 }
13245               else if (sizeflag & DFLAG)
13246                 *obufp++ = 'w';
13247               else
13248                 *obufp++ = 'b';
13249               if (!(rex & REX_W))
13250                 used_prefixes |= (prefixes & PREFIX_DATA);
13251             }
13252           else
13253             {
13254               if (l != 1
13255                   || len != 2
13256                   || (last[0] != 'X'
13257                       && last[0] != 'L'))
13258                 {
13259                   SAVE_LAST (*p);
13260                   break;
13261                 }
13262               if (!need_vex)
13263                 abort ();
13264               if (last[0] == 'X')
13265                 *obufp++ = vex.w ? 'd': 's';
13266               else
13267                 *obufp++ = vex.w ? 'q': 'd';
13268             }
13269           break;
13270         case '^':
13271           if (intel_syntax)
13272             break;
13273           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13274             {
13275               if (sizeflag & DFLAG)
13276                 *obufp++ = 'l';
13277               else
13278                 *obufp++ = 'w';
13279               used_prefixes |= (prefixes & PREFIX_DATA);
13280             }
13281           break;
13282         case '@':
13283           if (intel_syntax)
13284             break;
13285           if (address_mode == mode_64bit
13286               && (isa64 == intel64
13287                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13288               *obufp++ = 'q';
13289           else if ((prefixes & PREFIX_DATA))
13290             {
13291               if (!(sizeflag & DFLAG))
13292                 *obufp++ = 'w';
13293               used_prefixes |= (prefixes & PREFIX_DATA);
13294             }
13295           break;
13296         }
13297       alt = 0;
13298     }
13299   *obufp = 0;
13300   mnemonicendp = obufp;
13301   return 0;
13302 }
13303
13304 static void
13305 oappend (const char *s)
13306 {
13307   obufp = stpcpy (obufp, s);
13308 }
13309
13310 static void
13311 append_seg (void)
13312 {
13313   /* Only print the active segment register.  */
13314   if (!active_seg_prefix)
13315     return;
13316
13317   used_prefixes |= active_seg_prefix;
13318   switch (active_seg_prefix)
13319     {
13320     case PREFIX_CS:
13321       oappend_maybe_intel ("%cs:");
13322       break;
13323     case PREFIX_DS:
13324       oappend_maybe_intel ("%ds:");
13325       break;
13326     case PREFIX_SS:
13327       oappend_maybe_intel ("%ss:");
13328       break;
13329     case PREFIX_ES:
13330       oappend_maybe_intel ("%es:");
13331       break;
13332     case PREFIX_FS:
13333       oappend_maybe_intel ("%fs:");
13334       break;
13335     case PREFIX_GS:
13336       oappend_maybe_intel ("%gs:");
13337       break;
13338     default:
13339       break;
13340     }
13341 }
13342
13343 static void
13344 OP_indirE (int bytemode, int sizeflag)
13345 {
13346   if (!intel_syntax)
13347     oappend ("*");
13348   OP_E (bytemode, sizeflag);
13349 }
13350
13351 static void
13352 print_operand_value (char *buf, int hex, bfd_vma disp)
13353 {
13354   if (address_mode == mode_64bit)
13355     {
13356       if (hex)
13357         {
13358           char tmp[30];
13359           int i;
13360           buf[0] = '0';
13361           buf[1] = 'x';
13362           sprintf_vma (tmp, disp);
13363           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13364           strcpy (buf + 2, tmp + i);
13365         }
13366       else
13367         {
13368           bfd_signed_vma v = disp;
13369           char tmp[30];
13370           int i;
13371           if (v < 0)
13372             {
13373               *(buf++) = '-';
13374               v = -disp;
13375               /* Check for possible overflow on 0x8000000000000000.  */
13376               if (v < 0)
13377                 {
13378                   strcpy (buf, "9223372036854775808");
13379                   return;
13380                 }
13381             }
13382           if (!v)
13383             {
13384               strcpy (buf, "0");
13385               return;
13386             }
13387
13388           i = 0;
13389           tmp[29] = 0;
13390           while (v)
13391             {
13392               tmp[28 - i] = (v % 10) + '0';
13393               v /= 10;
13394               i++;
13395             }
13396           strcpy (buf, tmp + 29 - i);
13397         }
13398     }
13399   else
13400     {
13401       if (hex)
13402         sprintf (buf, "0x%x", (unsigned int) disp);
13403       else
13404         sprintf (buf, "%d", (int) disp);
13405     }
13406 }
13407
13408 /* Put DISP in BUF as signed hex number.  */
13409
13410 static void
13411 print_displacement (char *buf, bfd_vma disp)
13412 {
13413   bfd_signed_vma val = disp;
13414   char tmp[30];
13415   int i, j = 0;
13416
13417   if (val < 0)
13418     {
13419       buf[j++] = '-';
13420       val = -disp;
13421
13422       /* Check for possible overflow.  */
13423       if (val < 0)
13424         {
13425           switch (address_mode)
13426             {
13427             case mode_64bit:
13428               strcpy (buf + j, "0x8000000000000000");
13429               break;
13430             case mode_32bit:
13431               strcpy (buf + j, "0x80000000");
13432               break;
13433             case mode_16bit:
13434               strcpy (buf + j, "0x8000");
13435               break;
13436             }
13437           return;
13438         }
13439     }
13440
13441   buf[j++] = '0';
13442   buf[j++] = 'x';
13443
13444   sprintf_vma (tmp, (bfd_vma) val);
13445   for (i = 0; tmp[i] == '0'; i++)
13446     continue;
13447   if (tmp[i] == '\0')
13448     i--;
13449   strcpy (buf + j, tmp + i);
13450 }
13451
13452 static void
13453 intel_operand_size (int bytemode, int sizeflag)
13454 {
13455   if (vex.evex
13456       && vex.b
13457       && (bytemode == x_mode
13458           || bytemode == evex_half_bcst_xmmq_mode))
13459     {
13460       if (vex.w)
13461         oappend ("QWORD PTR ");
13462       else
13463         oappend ("DWORD PTR ");
13464       return;
13465     }
13466   switch (bytemode)
13467     {
13468     case b_mode:
13469     case b_swap_mode:
13470     case dqb_mode:
13471     case db_mode:
13472       oappend ("BYTE PTR ");
13473       break;
13474     case w_mode:
13475     case dw_mode:
13476     case dqw_mode:
13477       oappend ("WORD PTR ");
13478       break;
13479     case indir_v_mode:
13480       if (address_mode == mode_64bit && isa64 == intel64)
13481         {
13482           oappend ("QWORD PTR ");
13483           break;
13484         }
13485       /* Fall through.  */
13486     case stack_v_mode:
13487       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13488         {
13489           oappend ("QWORD PTR ");
13490           break;
13491         }
13492       /* Fall through.  */
13493     case v_mode:
13494     case v_swap_mode:
13495     case dq_mode:
13496       USED_REX (REX_W);
13497       if (rex & REX_W)
13498         oappend ("QWORD PTR ");
13499       else
13500         {
13501           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13502             oappend ("DWORD PTR ");
13503           else
13504             oappend ("WORD PTR ");
13505           used_prefixes |= (prefixes & PREFIX_DATA);
13506         }
13507       break;
13508     case z_mode:
13509       if ((rex & REX_W) || (sizeflag & DFLAG))
13510         *obufp++ = 'D';
13511       oappend ("WORD PTR ");
13512       if (!(rex & REX_W))
13513         used_prefixes |= (prefixes & PREFIX_DATA);
13514       break;
13515     case a_mode:
13516       if (sizeflag & DFLAG)
13517         oappend ("QWORD PTR ");
13518       else
13519         oappend ("DWORD PTR ");
13520       used_prefixes |= (prefixes & PREFIX_DATA);
13521       break;
13522     case d_mode:
13523     case d_scalar_mode:
13524     case d_scalar_swap_mode:
13525     case d_swap_mode:
13526     case dqd_mode:
13527       oappend ("DWORD PTR ");
13528       break;
13529     case q_mode:
13530     case q_scalar_mode:
13531     case q_scalar_swap_mode:
13532     case q_swap_mode:
13533       oappend ("QWORD PTR ");
13534       break;
13535     case dqa_mode:
13536     case m_mode:
13537       if (address_mode == mode_64bit)
13538         oappend ("QWORD PTR ");
13539       else
13540         oappend ("DWORD PTR ");
13541       break;
13542     case f_mode:
13543       if (sizeflag & DFLAG)
13544         oappend ("FWORD PTR ");
13545       else
13546         oappend ("DWORD PTR ");
13547       used_prefixes |= (prefixes & PREFIX_DATA);
13548       break;
13549     case t_mode:
13550       oappend ("TBYTE PTR ");
13551       break;
13552     case x_mode:
13553     case x_swap_mode:
13554     case evex_x_gscat_mode:
13555     case evex_x_nobcst_mode:
13556     case b_scalar_mode:
13557     case w_scalar_mode:
13558       if (need_vex)
13559         {
13560           switch (vex.length)
13561             {
13562             case 128:
13563               oappend ("XMMWORD PTR ");
13564               break;
13565             case 256:
13566               oappend ("YMMWORD PTR ");
13567               break;
13568             case 512:
13569               oappend ("ZMMWORD PTR ");
13570               break;
13571             default:
13572               abort ();
13573             }
13574         }
13575       else
13576         oappend ("XMMWORD PTR ");
13577       break;
13578     case xmm_mode:
13579       oappend ("XMMWORD PTR ");
13580       break;
13581     case ymm_mode:
13582       oappend ("YMMWORD PTR ");
13583       break;
13584     case xmmq_mode:
13585     case evex_half_bcst_xmmq_mode:
13586       if (!need_vex)
13587         abort ();
13588
13589       switch (vex.length)
13590         {
13591         case 128:
13592           oappend ("QWORD PTR ");
13593           break;
13594         case 256:
13595           oappend ("XMMWORD PTR ");
13596           break;
13597         case 512:
13598           oappend ("YMMWORD PTR ");
13599           break;
13600         default:
13601           abort ();
13602         }
13603       break;
13604     case xmm_mb_mode:
13605       if (!need_vex)
13606         abort ();
13607
13608       switch (vex.length)
13609         {
13610         case 128:
13611         case 256:
13612         case 512:
13613           oappend ("BYTE PTR ");
13614           break;
13615         default:
13616           abort ();
13617         }
13618       break;
13619     case xmm_mw_mode:
13620       if (!need_vex)
13621         abort ();
13622
13623       switch (vex.length)
13624         {
13625         case 128:
13626         case 256:
13627         case 512:
13628           oappend ("WORD PTR ");
13629           break;
13630         default:
13631           abort ();
13632         }
13633       break;
13634     case xmm_md_mode:
13635       if (!need_vex)
13636         abort ();
13637
13638       switch (vex.length)
13639         {
13640         case 128:
13641         case 256:
13642         case 512:
13643           oappend ("DWORD PTR ");
13644           break;
13645         default:
13646           abort ();
13647         }
13648       break;
13649     case xmm_mq_mode:
13650       if (!need_vex)
13651         abort ();
13652
13653       switch (vex.length)
13654         {
13655         case 128:
13656         case 256:
13657         case 512:
13658           oappend ("QWORD PTR ");
13659           break;
13660         default:
13661           abort ();
13662         }
13663       break;
13664     case xmmdw_mode:
13665       if (!need_vex)
13666         abort ();
13667
13668       switch (vex.length)
13669         {
13670         case 128:
13671           oappend ("WORD PTR ");
13672           break;
13673         case 256:
13674           oappend ("DWORD PTR ");
13675           break;
13676         case 512:
13677           oappend ("QWORD PTR ");
13678           break;
13679         default:
13680           abort ();
13681         }
13682       break;
13683     case xmmqd_mode:
13684       if (!need_vex)
13685         abort ();
13686
13687       switch (vex.length)
13688         {
13689         case 128:
13690           oappend ("DWORD PTR ");
13691           break;
13692         case 256:
13693           oappend ("QWORD PTR ");
13694           break;
13695         case 512:
13696           oappend ("XMMWORD PTR ");
13697           break;
13698         default:
13699           abort ();
13700         }
13701       break;
13702     case ymmq_mode:
13703       if (!need_vex)
13704         abort ();
13705
13706       switch (vex.length)
13707         {
13708         case 128:
13709           oappend ("QWORD PTR ");
13710           break;
13711         case 256:
13712           oappend ("YMMWORD PTR ");
13713           break;
13714         case 512:
13715           oappend ("ZMMWORD PTR ");
13716           break;
13717         default:
13718           abort ();
13719         }
13720       break;
13721     case ymmxmm_mode:
13722       if (!need_vex)
13723         abort ();
13724
13725       switch (vex.length)
13726         {
13727         case 128:
13728         case 256:
13729           oappend ("XMMWORD PTR ");
13730           break;
13731         default:
13732           abort ();
13733         }
13734       break;
13735     case o_mode:
13736       oappend ("OWORD PTR ");
13737       break;
13738     case xmm_mdq_mode:
13739     case vex_w_dq_mode:
13740     case vex_scalar_w_dq_mode:
13741       if (!need_vex)
13742         abort ();
13743
13744       if (vex.w)
13745         oappend ("QWORD PTR ");
13746       else
13747         oappend ("DWORD PTR ");
13748       break;
13749     case vex_vsib_d_w_dq_mode:
13750     case vex_vsib_q_w_dq_mode:
13751       if (!need_vex)
13752         abort ();
13753
13754       if (!vex.evex)
13755         {
13756           if (vex.w)
13757             oappend ("QWORD PTR ");
13758           else
13759             oappend ("DWORD PTR ");
13760         }
13761       else
13762         {
13763           switch (vex.length)
13764             {
13765             case 128:
13766               oappend ("XMMWORD PTR ");
13767               break;
13768             case 256:
13769               oappend ("YMMWORD PTR ");
13770               break;
13771             case 512:
13772               oappend ("ZMMWORD PTR ");
13773               break;
13774             default:
13775               abort ();
13776             }
13777         }
13778       break;
13779     case vex_vsib_q_w_d_mode:
13780     case vex_vsib_d_w_d_mode:
13781       if (!need_vex || !vex.evex)
13782         abort ();
13783
13784       switch (vex.length)
13785         {
13786         case 128:
13787           oappend ("QWORD PTR ");
13788           break;
13789         case 256:
13790           oappend ("XMMWORD PTR ");
13791           break;
13792         case 512:
13793           oappend ("YMMWORD PTR ");
13794           break;
13795         default:
13796           abort ();
13797         }
13798
13799       break;
13800     case mask_bd_mode:
13801       if (!need_vex || vex.length != 128)
13802         abort ();
13803       if (vex.w)
13804         oappend ("DWORD PTR ");
13805       else
13806         oappend ("BYTE PTR ");
13807       break;
13808     case mask_mode:
13809       if (!need_vex)
13810         abort ();
13811       if (vex.w)
13812         oappend ("QWORD PTR ");
13813       else
13814         oappend ("WORD PTR ");
13815       break;
13816     case v_bnd_mode:
13817     case v_bndmk_mode:
13818     default:
13819       break;
13820     }
13821 }
13822
13823 static void
13824 OP_E_register (int bytemode, int sizeflag)
13825 {
13826   int reg = modrm.rm;
13827   const char **names;
13828
13829   USED_REX (REX_B);
13830   if ((rex & REX_B))
13831     reg += 8;
13832
13833   if ((sizeflag & SUFFIX_ALWAYS)
13834       && (bytemode == b_swap_mode
13835           || bytemode == bnd_swap_mode
13836           || bytemode == v_swap_mode))
13837     swap_operand ();
13838
13839   switch (bytemode)
13840     {
13841     case b_mode:
13842     case b_swap_mode:
13843       USED_REX (0);
13844       if (rex)
13845         names = names8rex;
13846       else
13847         names = names8;
13848       break;
13849     case w_mode:
13850       names = names16;
13851       break;
13852     case d_mode:
13853     case dw_mode:
13854     case db_mode:
13855       names = names32;
13856       break;
13857     case q_mode:
13858       names = names64;
13859       break;
13860     case m_mode:
13861     case v_bnd_mode:
13862       names = address_mode == mode_64bit ? names64 : names32;
13863       break;
13864     case bnd_mode:
13865     case bnd_swap_mode:
13866       if (reg > 0x3)
13867         {
13868           oappend ("(bad)");
13869           return;
13870         }
13871       names = names_bnd;
13872       break;
13873     case indir_v_mode:
13874       if (address_mode == mode_64bit && isa64 == intel64)
13875         {
13876           names = names64;
13877           break;
13878         }
13879       /* Fall through.  */
13880     case stack_v_mode:
13881       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13882         {
13883           names = names64;
13884           break;
13885         }
13886       bytemode = v_mode;
13887       /* Fall through.  */
13888     case v_mode:
13889     case v_swap_mode:
13890     case dq_mode:
13891     case dqb_mode:
13892     case dqd_mode:
13893     case dqw_mode:
13894     case dqa_mode:
13895       USED_REX (REX_W);
13896       if (rex & REX_W)
13897         names = names64;
13898       else
13899         {
13900           if ((sizeflag & DFLAG)
13901               || (bytemode != v_mode
13902                   && bytemode != v_swap_mode))
13903             names = names32;
13904           else
13905             names = names16;
13906           used_prefixes |= (prefixes & PREFIX_DATA);
13907         }
13908       break;
13909     case va_mode:
13910       names = (address_mode == mode_64bit
13911                ? names64 : names32);
13912       if (!(prefixes & PREFIX_ADDR))
13913         names = (address_mode == mode_16bit
13914                      ? names16 : names);
13915       else
13916         {
13917           /* Remove "addr16/addr32".  */
13918           all_prefixes[last_addr_prefix] = 0;
13919           names = (address_mode != mode_32bit
13920                        ? names32 : names16);
13921           used_prefixes |= PREFIX_ADDR;
13922         }
13923       break;
13924     case mask_bd_mode:
13925     case mask_mode:
13926       if (reg > 0x7)
13927         {
13928           oappend ("(bad)");
13929           return;
13930         }
13931       names = names_mask;
13932       break;
13933     case 0:
13934       return;
13935     default:
13936       oappend (INTERNAL_DISASSEMBLER_ERROR);
13937       return;
13938     }
13939   oappend (names[reg]);
13940 }
13941
13942 static void
13943 OP_E_memory (int bytemode, int sizeflag)
13944 {
13945   bfd_vma disp = 0;
13946   int add = (rex & REX_B) ? 8 : 0;
13947   int riprel = 0;
13948   int shift;
13949
13950   if (vex.evex)
13951     {
13952       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13953       if (vex.b
13954           && bytemode != x_mode
13955           && bytemode != xmmq_mode
13956           && bytemode != evex_half_bcst_xmmq_mode)
13957         {
13958           BadOp ();
13959           return;
13960         }
13961       switch (bytemode)
13962         {
13963         case dqw_mode:
13964         case dw_mode:
13965           shift = 1;
13966           break;
13967         case dqb_mode:
13968         case db_mode:
13969           shift = 0;
13970           break;
13971         case dq_mode:
13972           if (address_mode != mode_64bit)
13973             {
13974               shift = 2;
13975               break;
13976             }
13977             /* fall through */
13978         case vex_vsib_d_w_dq_mode:
13979         case vex_vsib_d_w_d_mode:
13980         case vex_vsib_q_w_dq_mode:
13981         case vex_vsib_q_w_d_mode:
13982         case evex_x_gscat_mode:
13983         case xmm_mdq_mode:
13984           shift = vex.w ? 3 : 2;
13985           break;
13986         case x_mode:
13987         case evex_half_bcst_xmmq_mode:
13988         case xmmq_mode:
13989           if (vex.b)
13990             {
13991               shift = vex.w ? 3 : 2;
13992               break;
13993             }
13994           /* Fall through.  */
13995         case xmmqd_mode:
13996         case xmmdw_mode:
13997         case ymmq_mode:
13998         case evex_x_nobcst_mode:
13999         case x_swap_mode:
14000           switch (vex.length)
14001             {
14002             case 128:
14003               shift = 4;
14004               break;
14005             case 256:
14006               shift = 5;
14007               break;
14008             case 512:
14009               shift = 6;
14010               break;
14011             default:
14012               abort ();
14013             }
14014           break;
14015         case ymm_mode:
14016           shift = 5;
14017           break;
14018         case xmm_mode:
14019           shift = 4;
14020           break;
14021         case xmm_mq_mode:
14022         case q_mode:
14023         case q_scalar_mode:
14024         case q_swap_mode:
14025         case q_scalar_swap_mode:
14026           shift = 3;
14027           break;
14028         case dqd_mode:
14029         case xmm_md_mode:
14030         case d_mode:
14031         case d_scalar_mode:
14032         case d_swap_mode:
14033         case d_scalar_swap_mode:
14034           shift = 2;
14035           break;
14036         case w_scalar_mode:
14037         case xmm_mw_mode:
14038           shift = 1;
14039           break;
14040         case b_scalar_mode:
14041         case xmm_mb_mode:
14042           shift = 0;
14043           break;
14044         case dqa_mode:
14045           shift = address_mode == mode_64bit ? 3 : 2;
14046           break;
14047         default:
14048           abort ();
14049         }
14050       /* Make necessary corrections to shift for modes that need it.
14051          For these modes we currently have shift 4, 5 or 6 depending on
14052          vex.length (it corresponds to xmmword, ymmword or zmmword
14053          operand).  We might want to make it 3, 4 or 5 (e.g. for
14054          xmmq_mode).  In case of broadcast enabled the corrections
14055          aren't needed, as element size is always 32 or 64 bits.  */
14056       if (!vex.b
14057           && (bytemode == xmmq_mode
14058               || bytemode == evex_half_bcst_xmmq_mode))
14059         shift -= 1;
14060       else if (bytemode == xmmqd_mode)
14061         shift -= 2;
14062       else if (bytemode == xmmdw_mode)
14063         shift -= 3;
14064       else if (bytemode == ymmq_mode && vex.length == 128)
14065         shift -= 1;
14066     }
14067   else
14068     shift = 0;
14069
14070   USED_REX (REX_B);
14071   if (intel_syntax)
14072     intel_operand_size (bytemode, sizeflag);
14073   append_seg ();
14074
14075   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14076     {
14077       /* 32/64 bit address mode */
14078       int havedisp;
14079       int havesib;
14080       int havebase;
14081       int haveindex;
14082       int needindex;
14083       int needaddr32;
14084       int base, rbase;
14085       int vindex = 0;
14086       int scale = 0;
14087       int addr32flag = !((sizeflag & AFLAG)
14088                          || bytemode == v_bnd_mode
14089                          || bytemode == v_bndmk_mode
14090                          || bytemode == bnd_mode
14091                          || bytemode == bnd_swap_mode);
14092       const char **indexes64 = names64;
14093       const char **indexes32 = names32;
14094
14095       havesib = 0;
14096       havebase = 1;
14097       haveindex = 0;
14098       base = modrm.rm;
14099
14100       if (base == 4)
14101         {
14102           havesib = 1;
14103           vindex = sib.index;
14104           USED_REX (REX_X);
14105           if (rex & REX_X)
14106             vindex += 8;
14107           switch (bytemode)
14108             {
14109             case vex_vsib_d_w_dq_mode:
14110             case vex_vsib_d_w_d_mode:
14111             case vex_vsib_q_w_dq_mode:
14112             case vex_vsib_q_w_d_mode:
14113               if (!need_vex)
14114                 abort ();
14115               if (vex.evex)
14116                 {
14117                   if (!vex.v)
14118                     vindex += 16;
14119                 }
14120
14121               haveindex = 1;
14122               switch (vex.length)
14123                 {
14124                 case 128:
14125                   indexes64 = indexes32 = names_xmm;
14126                   break;
14127                 case 256:
14128                   if (!vex.w
14129                       || bytemode == vex_vsib_q_w_dq_mode
14130                       || bytemode == vex_vsib_q_w_d_mode)
14131                     indexes64 = indexes32 = names_ymm;
14132                   else
14133                     indexes64 = indexes32 = names_xmm;
14134                   break;
14135                 case 512:
14136                   if (!vex.w
14137                       || bytemode == vex_vsib_q_w_dq_mode
14138                       || bytemode == vex_vsib_q_w_d_mode)
14139                     indexes64 = indexes32 = names_zmm;
14140                   else
14141                     indexes64 = indexes32 = names_ymm;
14142                   break;
14143                 default:
14144                   abort ();
14145                 }
14146               break;
14147             default:
14148               haveindex = vindex != 4;
14149               break;
14150             }
14151           scale = sib.scale;
14152           base = sib.base;
14153           codep++;
14154         }
14155       rbase = base + add;
14156
14157       switch (modrm.mod)
14158         {
14159         case 0:
14160           if (base == 5)
14161             {
14162               havebase = 0;
14163               if (address_mode == mode_64bit && !havesib)
14164                 riprel = 1;
14165               disp = get32s ();
14166               if (riprel && bytemode == v_bndmk_mode)
14167                 {
14168                   oappend ("(bad)");
14169                   return;
14170                 }
14171             }
14172           break;
14173         case 1:
14174           FETCH_DATA (the_info, codep + 1);
14175           disp = *codep++;
14176           if ((disp & 0x80) != 0)
14177             disp -= 0x100;
14178           if (vex.evex && shift > 0)
14179             disp <<= shift;
14180           break;
14181         case 2:
14182           disp = get32s ();
14183           break;
14184         }
14185
14186       needindex = 0;
14187       needaddr32 = 0;
14188       if (havesib
14189           && !havebase
14190           && !haveindex
14191           && address_mode != mode_16bit)
14192         {
14193           if (address_mode == mode_64bit)
14194             {
14195               /* Display eiz instead of addr32.  */
14196               needindex = addr32flag;
14197               needaddr32 = 1;
14198             }
14199           else
14200             {
14201               /* In 32-bit mode, we need index register to tell [offset]
14202                  from [eiz*1 + offset].  */
14203               needindex = 1;
14204             }
14205         }
14206
14207       havedisp = (havebase
14208                   || needindex
14209                   || (havesib && (haveindex || scale != 0)));
14210
14211       if (!intel_syntax)
14212         if (modrm.mod != 0 || base == 5)
14213           {
14214             if (havedisp || riprel)
14215               print_displacement (scratchbuf, disp);
14216             else
14217               print_operand_value (scratchbuf, 1, disp);
14218             oappend (scratchbuf);
14219             if (riprel)
14220               {
14221                 set_op (disp, 1);
14222                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14223               }
14224           }
14225
14226       if ((havebase || haveindex || needaddr32 || riprel)
14227           && (bytemode != v_bnd_mode)
14228           && (bytemode != v_bndmk_mode)
14229           && (bytemode != bnd_mode)
14230           && (bytemode != bnd_swap_mode))
14231         used_prefixes |= PREFIX_ADDR;
14232
14233       if (havedisp || (intel_syntax && riprel))
14234         {
14235           *obufp++ = open_char;
14236           if (intel_syntax && riprel)
14237             {
14238               set_op (disp, 1);
14239               oappend (!addr32flag ? "rip" : "eip");
14240             }
14241           *obufp = '\0';
14242           if (havebase)
14243             oappend (address_mode == mode_64bit && !addr32flag
14244                      ? names64[rbase] : names32[rbase]);
14245           if (havesib)
14246             {
14247               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14248                  print index to tell base + index from base.  */
14249               if (scale != 0
14250                   || needindex
14251                   || haveindex
14252                   || (havebase && base != ESP_REG_NUM))
14253                 {
14254                   if (!intel_syntax || havebase)
14255                     {
14256                       *obufp++ = separator_char;
14257                       *obufp = '\0';
14258                     }
14259                   if (haveindex)
14260                     oappend (address_mode == mode_64bit && !addr32flag
14261                              ? indexes64[vindex] : indexes32[vindex]);
14262                   else
14263                     oappend (address_mode == mode_64bit && !addr32flag
14264                              ? index64 : index32);
14265
14266                   *obufp++ = scale_char;
14267                   *obufp = '\0';
14268                   sprintf (scratchbuf, "%d", 1 << scale);
14269                   oappend (scratchbuf);
14270                 }
14271             }
14272           if (intel_syntax
14273               && (disp || modrm.mod != 0 || base == 5))
14274             {
14275               if (!havedisp || (bfd_signed_vma) disp >= 0)
14276                 {
14277                   *obufp++ = '+';
14278                   *obufp = '\0';
14279                 }
14280               else if (modrm.mod != 1 && disp != -disp)
14281                 {
14282                   *obufp++ = '-';
14283                   *obufp = '\0';
14284                   disp = - (bfd_signed_vma) disp;
14285                 }
14286
14287               if (havedisp)
14288                 print_displacement (scratchbuf, disp);
14289               else
14290                 print_operand_value (scratchbuf, 1, disp);
14291               oappend (scratchbuf);
14292             }
14293
14294           *obufp++ = close_char;
14295           *obufp = '\0';
14296         }
14297       else if (intel_syntax)
14298         {
14299           if (modrm.mod != 0 || base == 5)
14300             {
14301               if (!active_seg_prefix)
14302                 {
14303                   oappend (names_seg[ds_reg - es_reg]);
14304                   oappend (":");
14305                 }
14306               print_operand_value (scratchbuf, 1, disp);
14307               oappend (scratchbuf);
14308             }
14309         }
14310     }
14311   else
14312     {
14313       /* 16 bit address mode */
14314       used_prefixes |= prefixes & PREFIX_ADDR;
14315       switch (modrm.mod)
14316         {
14317         case 0:
14318           if (modrm.rm == 6)
14319             {
14320               disp = get16 ();
14321               if ((disp & 0x8000) != 0)
14322                 disp -= 0x10000;
14323             }
14324           break;
14325         case 1:
14326           FETCH_DATA (the_info, codep + 1);
14327           disp = *codep++;
14328           if ((disp & 0x80) != 0)
14329             disp -= 0x100;
14330           if (vex.evex && shift > 0)
14331             disp <<= shift;
14332           break;
14333         case 2:
14334           disp = get16 ();
14335           if ((disp & 0x8000) != 0)
14336             disp -= 0x10000;
14337           break;
14338         }
14339
14340       if (!intel_syntax)
14341         if (modrm.mod != 0 || modrm.rm == 6)
14342           {
14343             print_displacement (scratchbuf, disp);
14344             oappend (scratchbuf);
14345           }
14346
14347       if (modrm.mod != 0 || modrm.rm != 6)
14348         {
14349           *obufp++ = open_char;
14350           *obufp = '\0';
14351           oappend (index16[modrm.rm]);
14352           if (intel_syntax
14353               && (disp || modrm.mod != 0 || modrm.rm == 6))
14354             {
14355               if ((bfd_signed_vma) disp >= 0)
14356                 {
14357                   *obufp++ = '+';
14358                   *obufp = '\0';
14359                 }
14360               else if (modrm.mod != 1)
14361                 {
14362                   *obufp++ = '-';
14363                   *obufp = '\0';
14364                   disp = - (bfd_signed_vma) disp;
14365                 }
14366
14367               print_displacement (scratchbuf, disp);
14368               oappend (scratchbuf);
14369             }
14370
14371           *obufp++ = close_char;
14372           *obufp = '\0';
14373         }
14374       else if (intel_syntax)
14375         {
14376           if (!active_seg_prefix)
14377             {
14378               oappend (names_seg[ds_reg - es_reg]);
14379               oappend (":");
14380             }
14381           print_operand_value (scratchbuf, 1, disp & 0xffff);
14382           oappend (scratchbuf);
14383         }
14384     }
14385   if (vex.evex && vex.b
14386       && (bytemode == x_mode
14387           || bytemode == xmmq_mode
14388           || bytemode == evex_half_bcst_xmmq_mode))
14389     {
14390       if (vex.w
14391           || bytemode == xmmq_mode
14392           || bytemode == evex_half_bcst_xmmq_mode)
14393         {
14394           switch (vex.length)
14395             {
14396             case 128:
14397               oappend ("{1to2}");
14398               break;
14399             case 256:
14400               oappend ("{1to4}");
14401               break;
14402             case 512:
14403               oappend ("{1to8}");
14404               break;
14405             default:
14406               abort ();
14407             }
14408         }
14409       else
14410         {
14411           switch (vex.length)
14412             {
14413             case 128:
14414               oappend ("{1to4}");
14415               break;
14416             case 256:
14417               oappend ("{1to8}");
14418               break;
14419             case 512:
14420               oappend ("{1to16}");
14421               break;
14422             default:
14423               abort ();
14424             }
14425         }
14426     }
14427 }
14428
14429 static void
14430 OP_E (int bytemode, int sizeflag)
14431 {
14432   /* Skip mod/rm byte.  */
14433   MODRM_CHECK;
14434   codep++;
14435
14436   if (modrm.mod == 3)
14437     OP_E_register (bytemode, sizeflag);
14438   else
14439     OP_E_memory (bytemode, sizeflag);
14440 }
14441
14442 static void
14443 OP_G (int bytemode, int sizeflag)
14444 {
14445   int add = 0;
14446   const char **names;
14447   USED_REX (REX_R);
14448   if (rex & REX_R)
14449     add += 8;
14450   switch (bytemode)
14451     {
14452     case b_mode:
14453       USED_REX (0);
14454       if (rex)
14455         oappend (names8rex[modrm.reg + add]);
14456       else
14457         oappend (names8[modrm.reg + add]);
14458       break;
14459     case w_mode:
14460       oappend (names16[modrm.reg + add]);
14461       break;
14462     case d_mode:
14463     case db_mode:
14464     case dw_mode:
14465       oappend (names32[modrm.reg + add]);
14466       break;
14467     case q_mode:
14468       oappend (names64[modrm.reg + add]);
14469       break;
14470     case bnd_mode:
14471       if (modrm.reg > 0x3)
14472         {
14473           oappend ("(bad)");
14474           return;
14475         }
14476       oappend (names_bnd[modrm.reg]);
14477       break;
14478     case v_mode:
14479     case dq_mode:
14480     case dqb_mode:
14481     case dqd_mode:
14482     case dqw_mode:
14483       USED_REX (REX_W);
14484       if (rex & REX_W)
14485         oappend (names64[modrm.reg + add]);
14486       else
14487         {
14488           if ((sizeflag & DFLAG) || bytemode != v_mode)
14489             oappend (names32[modrm.reg + add]);
14490           else
14491             oappend (names16[modrm.reg + add]);
14492           used_prefixes |= (prefixes & PREFIX_DATA);
14493         }
14494       break;
14495     case va_mode:
14496       names = (address_mode == mode_64bit
14497                ? names64 : names32);
14498       if (!(prefixes & PREFIX_ADDR))
14499         {
14500           if (address_mode == mode_16bit)
14501             names = names16;
14502         }
14503       else
14504         {
14505           /* Remove "addr16/addr32".  */
14506           all_prefixes[last_addr_prefix] = 0;
14507           names = (address_mode != mode_32bit
14508                        ? names32 : names16);
14509           used_prefixes |= PREFIX_ADDR;
14510         }
14511       oappend (names[modrm.reg + add]);
14512       break;
14513     case m_mode:
14514       if (address_mode == mode_64bit)
14515         oappend (names64[modrm.reg + add]);
14516       else
14517         oappend (names32[modrm.reg + add]);
14518       break;
14519     case mask_bd_mode:
14520     case mask_mode:
14521       if ((modrm.reg + add) > 0x7)
14522         {
14523           oappend ("(bad)");
14524           return;
14525         }
14526       oappend (names_mask[modrm.reg + add]);
14527       break;
14528     default:
14529       oappend (INTERNAL_DISASSEMBLER_ERROR);
14530       break;
14531     }
14532 }
14533
14534 static bfd_vma
14535 get64 (void)
14536 {
14537   bfd_vma x;
14538 #ifdef BFD64
14539   unsigned int a;
14540   unsigned int b;
14541
14542   FETCH_DATA (the_info, codep + 8);
14543   a = *codep++ & 0xff;
14544   a |= (*codep++ & 0xff) << 8;
14545   a |= (*codep++ & 0xff) << 16;
14546   a |= (*codep++ & 0xffu) << 24;
14547   b = *codep++ & 0xff;
14548   b |= (*codep++ & 0xff) << 8;
14549   b |= (*codep++ & 0xff) << 16;
14550   b |= (*codep++ & 0xffu) << 24;
14551   x = a + ((bfd_vma) b << 32);
14552 #else
14553   abort ();
14554   x = 0;
14555 #endif
14556   return x;
14557 }
14558
14559 static bfd_signed_vma
14560 get32 (void)
14561 {
14562   bfd_signed_vma x = 0;
14563
14564   FETCH_DATA (the_info, codep + 4);
14565   x = *codep++ & (bfd_signed_vma) 0xff;
14566   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14567   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14568   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14569   return x;
14570 }
14571
14572 static bfd_signed_vma
14573 get32s (void)
14574 {
14575   bfd_signed_vma x = 0;
14576
14577   FETCH_DATA (the_info, codep + 4);
14578   x = *codep++ & (bfd_signed_vma) 0xff;
14579   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14580   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14581   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14582
14583   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14584
14585   return x;
14586 }
14587
14588 static int
14589 get16 (void)
14590 {
14591   int x = 0;
14592
14593   FETCH_DATA (the_info, codep + 2);
14594   x = *codep++ & 0xff;
14595   x |= (*codep++ & 0xff) << 8;
14596   return x;
14597 }
14598
14599 static void
14600 set_op (bfd_vma op, int riprel)
14601 {
14602   op_index[op_ad] = op_ad;
14603   if (address_mode == mode_64bit)
14604     {
14605       op_address[op_ad] = op;
14606       op_riprel[op_ad] = riprel;
14607     }
14608   else
14609     {
14610       /* Mask to get a 32-bit address.  */
14611       op_address[op_ad] = op & 0xffffffff;
14612       op_riprel[op_ad] = riprel & 0xffffffff;
14613     }
14614 }
14615
14616 static void
14617 OP_REG (int code, int sizeflag)
14618 {
14619   const char *s;
14620   int add;
14621
14622   switch (code)
14623     {
14624     case es_reg: case ss_reg: case cs_reg:
14625     case ds_reg: case fs_reg: case gs_reg:
14626       oappend (names_seg[code - es_reg]);
14627       return;
14628     }
14629
14630   USED_REX (REX_B);
14631   if (rex & REX_B)
14632     add = 8;
14633   else
14634     add = 0;
14635
14636   switch (code)
14637     {
14638     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14639     case sp_reg: case bp_reg: case si_reg: case di_reg:
14640       s = names16[code - ax_reg + add];
14641       break;
14642     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14643     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14644       USED_REX (0);
14645       if (rex)
14646         s = names8rex[code - al_reg + add];
14647       else
14648         s = names8[code - al_reg];
14649       break;
14650     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14651     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14652       if (address_mode == mode_64bit
14653           && ((sizeflag & DFLAG) || (rex & REX_W)))
14654         {
14655           s = names64[code - rAX_reg + add];
14656           break;
14657         }
14658       code += eAX_reg - rAX_reg;
14659       /* Fall through.  */
14660     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14661     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14662       USED_REX (REX_W);
14663       if (rex & REX_W)
14664         s = names64[code - eAX_reg + add];
14665       else
14666         {
14667           if (sizeflag & DFLAG)
14668             s = names32[code - eAX_reg + add];
14669           else
14670             s = names16[code - eAX_reg + add];
14671           used_prefixes |= (prefixes & PREFIX_DATA);
14672         }
14673       break;
14674     default:
14675       s = INTERNAL_DISASSEMBLER_ERROR;
14676       break;
14677     }
14678   oappend (s);
14679 }
14680
14681 static void
14682 OP_IMREG (int code, int sizeflag)
14683 {
14684   const char *s;
14685
14686   switch (code)
14687     {
14688     case indir_dx_reg:
14689       if (intel_syntax)
14690         s = "dx";
14691       else
14692         s = "(%dx)";
14693       break;
14694     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14695     case sp_reg: case bp_reg: case si_reg: case di_reg:
14696       s = names16[code - ax_reg];
14697       break;
14698     case es_reg: case ss_reg: case cs_reg:
14699     case ds_reg: case fs_reg: case gs_reg:
14700       s = names_seg[code - es_reg];
14701       break;
14702     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14703     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14704       USED_REX (0);
14705       if (rex)
14706         s = names8rex[code - al_reg];
14707       else
14708         s = names8[code - al_reg];
14709       break;
14710     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14711     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14712       USED_REX (REX_W);
14713       if (rex & REX_W)
14714         s = names64[code - eAX_reg];
14715       else
14716         {
14717           if (sizeflag & DFLAG)
14718             s = names32[code - eAX_reg];
14719           else
14720             s = names16[code - eAX_reg];
14721           used_prefixes |= (prefixes & PREFIX_DATA);
14722         }
14723       break;
14724     case z_mode_ax_reg:
14725       if ((rex & REX_W) || (sizeflag & DFLAG))
14726         s = *names32;
14727       else
14728         s = *names16;
14729       if (!(rex & REX_W))
14730         used_prefixes |= (prefixes & PREFIX_DATA);
14731       break;
14732     default:
14733       s = INTERNAL_DISASSEMBLER_ERROR;
14734       break;
14735     }
14736   oappend (s);
14737 }
14738
14739 static void
14740 OP_I (int bytemode, int sizeflag)
14741 {
14742   bfd_signed_vma op;
14743   bfd_signed_vma mask = -1;
14744
14745   switch (bytemode)
14746     {
14747     case b_mode:
14748       FETCH_DATA (the_info, codep + 1);
14749       op = *codep++;
14750       mask = 0xff;
14751       break;
14752     case q_mode:
14753       if (address_mode == mode_64bit)
14754         {
14755           op = get32s ();
14756           break;
14757         }
14758       /* Fall through.  */
14759     case v_mode:
14760       USED_REX (REX_W);
14761       if (rex & REX_W)
14762         op = get32s ();
14763       else
14764         {
14765           if (sizeflag & DFLAG)
14766             {
14767               op = get32 ();
14768               mask = 0xffffffff;
14769             }
14770           else
14771             {
14772               op = get16 ();
14773               mask = 0xfffff;
14774             }
14775           used_prefixes |= (prefixes & PREFIX_DATA);
14776         }
14777       break;
14778     case w_mode:
14779       mask = 0xfffff;
14780       op = get16 ();
14781       break;
14782     case const_1_mode:
14783       if (intel_syntax)
14784         oappend ("1");
14785       return;
14786     default:
14787       oappend (INTERNAL_DISASSEMBLER_ERROR);
14788       return;
14789     }
14790
14791   op &= mask;
14792   scratchbuf[0] = '$';
14793   print_operand_value (scratchbuf + 1, 1, op);
14794   oappend_maybe_intel (scratchbuf);
14795   scratchbuf[0] = '\0';
14796 }
14797
14798 static void
14799 OP_I64 (int bytemode, int sizeflag)
14800 {
14801   bfd_signed_vma op;
14802   bfd_signed_vma mask = -1;
14803
14804   if (address_mode != mode_64bit)
14805     {
14806       OP_I (bytemode, sizeflag);
14807       return;
14808     }
14809
14810   switch (bytemode)
14811     {
14812     case b_mode:
14813       FETCH_DATA (the_info, codep + 1);
14814       op = *codep++;
14815       mask = 0xff;
14816       break;
14817     case v_mode:
14818       USED_REX (REX_W);
14819       if (rex & REX_W)
14820         op = get64 ();
14821       else
14822         {
14823           if (sizeflag & DFLAG)
14824             {
14825               op = get32 ();
14826               mask = 0xffffffff;
14827             }
14828           else
14829             {
14830               op = get16 ();
14831               mask = 0xfffff;
14832             }
14833           used_prefixes |= (prefixes & PREFIX_DATA);
14834         }
14835       break;
14836     case w_mode:
14837       mask = 0xfffff;
14838       op = get16 ();
14839       break;
14840     default:
14841       oappend (INTERNAL_DISASSEMBLER_ERROR);
14842       return;
14843     }
14844
14845   op &= mask;
14846   scratchbuf[0] = '$';
14847   print_operand_value (scratchbuf + 1, 1, op);
14848   oappend_maybe_intel (scratchbuf);
14849   scratchbuf[0] = '\0';
14850 }
14851
14852 static void
14853 OP_sI (int bytemode, int sizeflag)
14854 {
14855   bfd_signed_vma op;
14856
14857   switch (bytemode)
14858     {
14859     case b_mode:
14860     case b_T_mode:
14861       FETCH_DATA (the_info, codep + 1);
14862       op = *codep++;
14863       if ((op & 0x80) != 0)
14864         op -= 0x100;
14865       if (bytemode == b_T_mode)
14866         {
14867           if (address_mode != mode_64bit
14868               || !((sizeflag & DFLAG) || (rex & REX_W)))
14869             {
14870               /* The operand-size prefix is overridden by a REX prefix.  */
14871               if ((sizeflag & DFLAG) || (rex & REX_W))
14872                 op &= 0xffffffff;
14873               else
14874                 op &= 0xffff;
14875           }
14876         }
14877       else
14878         {
14879           if (!(rex & REX_W))
14880             {
14881               if (sizeflag & DFLAG)
14882                 op &= 0xffffffff;
14883               else
14884                 op &= 0xffff;
14885             }
14886         }
14887       break;
14888     case v_mode:
14889       /* The operand-size prefix is overridden by a REX prefix.  */
14890       if ((sizeflag & DFLAG) || (rex & REX_W))
14891         op = get32s ();
14892       else
14893         op = get16 ();
14894       break;
14895     default:
14896       oappend (INTERNAL_DISASSEMBLER_ERROR);
14897       return;
14898     }
14899
14900   scratchbuf[0] = '$';
14901   print_operand_value (scratchbuf + 1, 1, op);
14902   oappend_maybe_intel (scratchbuf);
14903 }
14904
14905 static void
14906 OP_J (int bytemode, int sizeflag)
14907 {
14908   bfd_vma disp;
14909   bfd_vma mask = -1;
14910   bfd_vma segment = 0;
14911
14912   switch (bytemode)
14913     {
14914     case b_mode:
14915       FETCH_DATA (the_info, codep + 1);
14916       disp = *codep++;
14917       if ((disp & 0x80) != 0)
14918         disp -= 0x100;
14919       break;
14920     case v_mode:
14921       if (isa64 == amd64)
14922         USED_REX (REX_W);
14923       if ((sizeflag & DFLAG)
14924           || (address_mode == mode_64bit
14925               && (isa64 != amd64 || (rex & REX_W))))
14926         disp = get32s ();
14927       else
14928         {
14929           disp = get16 ();
14930           if ((disp & 0x8000) != 0)
14931             disp -= 0x10000;
14932           /* In 16bit mode, address is wrapped around at 64k within
14933              the same segment.  Otherwise, a data16 prefix on a jump
14934              instruction means that the pc is masked to 16 bits after
14935              the displacement is added!  */
14936           mask = 0xffff;
14937           if ((prefixes & PREFIX_DATA) == 0)
14938             segment = ((start_pc + (codep - start_codep))
14939                        & ~((bfd_vma) 0xffff));
14940         }
14941       if (address_mode != mode_64bit
14942           || (isa64 == amd64 && !(rex & REX_W)))
14943         used_prefixes |= (prefixes & PREFIX_DATA);
14944       break;
14945     default:
14946       oappend (INTERNAL_DISASSEMBLER_ERROR);
14947       return;
14948     }
14949   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14950   set_op (disp, 0);
14951   print_operand_value (scratchbuf, 1, disp);
14952   oappend (scratchbuf);
14953 }
14954
14955 static void
14956 OP_SEG (int bytemode, int sizeflag)
14957 {
14958   if (bytemode == w_mode)
14959     oappend (names_seg[modrm.reg]);
14960   else
14961     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14962 }
14963
14964 static void
14965 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14966 {
14967   int seg, offset;
14968
14969   if (sizeflag & DFLAG)
14970     {
14971       offset = get32 ();
14972       seg = get16 ();
14973     }
14974   else
14975     {
14976       offset = get16 ();
14977       seg = get16 ();
14978     }
14979   used_prefixes |= (prefixes & PREFIX_DATA);
14980   if (intel_syntax)
14981     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14982   else
14983     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14984   oappend (scratchbuf);
14985 }
14986
14987 static void
14988 OP_OFF (int bytemode, int sizeflag)
14989 {
14990   bfd_vma off;
14991
14992   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14993     intel_operand_size (bytemode, sizeflag);
14994   append_seg ();
14995
14996   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14997     off = get32 ();
14998   else
14999     off = get16 ();
15000
15001   if (intel_syntax)
15002     {
15003       if (!active_seg_prefix)
15004         {
15005           oappend (names_seg[ds_reg - es_reg]);
15006           oappend (":");
15007         }
15008     }
15009   print_operand_value (scratchbuf, 1, off);
15010   oappend (scratchbuf);
15011 }
15012
15013 static void
15014 OP_OFF64 (int bytemode, int sizeflag)
15015 {
15016   bfd_vma off;
15017
15018   if (address_mode != mode_64bit
15019       || (prefixes & PREFIX_ADDR))
15020     {
15021       OP_OFF (bytemode, sizeflag);
15022       return;
15023     }
15024
15025   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15026     intel_operand_size (bytemode, sizeflag);
15027   append_seg ();
15028
15029   off = get64 ();
15030
15031   if (intel_syntax)
15032     {
15033       if (!active_seg_prefix)
15034         {
15035           oappend (names_seg[ds_reg - es_reg]);
15036           oappend (":");
15037         }
15038     }
15039   print_operand_value (scratchbuf, 1, off);
15040   oappend (scratchbuf);
15041 }
15042
15043 static void
15044 ptr_reg (int code, int sizeflag)
15045 {
15046   const char *s;
15047
15048   *obufp++ = open_char;
15049   used_prefixes |= (prefixes & PREFIX_ADDR);
15050   if (address_mode == mode_64bit)
15051     {
15052       if (!(sizeflag & AFLAG))
15053         s = names32[code - eAX_reg];
15054       else
15055         s = names64[code - eAX_reg];
15056     }
15057   else if (sizeflag & AFLAG)
15058     s = names32[code - eAX_reg];
15059   else
15060     s = names16[code - eAX_reg];
15061   oappend (s);
15062   *obufp++ = close_char;
15063   *obufp = 0;
15064 }
15065
15066 static void
15067 OP_ESreg (int code, int sizeflag)
15068 {
15069   if (intel_syntax)
15070     {
15071       switch (codep[-1])
15072         {
15073         case 0x6d:      /* insw/insl */
15074           intel_operand_size (z_mode, sizeflag);
15075           break;
15076         case 0xa5:      /* movsw/movsl/movsq */
15077         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15078         case 0xab:      /* stosw/stosl */
15079         case 0xaf:      /* scasw/scasl */
15080           intel_operand_size (v_mode, sizeflag);
15081           break;
15082         default:
15083           intel_operand_size (b_mode, sizeflag);
15084         }
15085     }
15086   oappend_maybe_intel ("%es:");
15087   ptr_reg (code, sizeflag);
15088 }
15089
15090 static void
15091 OP_DSreg (int code, int sizeflag)
15092 {
15093   if (intel_syntax)
15094     {
15095       switch (codep[-1])
15096         {
15097         case 0x6f:      /* outsw/outsl */
15098           intel_operand_size (z_mode, sizeflag);
15099           break;
15100         case 0xa5:      /* movsw/movsl/movsq */
15101         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15102         case 0xad:      /* lodsw/lodsl/lodsq */
15103           intel_operand_size (v_mode, sizeflag);
15104           break;
15105         default:
15106           intel_operand_size (b_mode, sizeflag);
15107         }
15108     }
15109   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15110      default segment register DS is printed.  */
15111   if (!active_seg_prefix)
15112     active_seg_prefix = PREFIX_DS;
15113   append_seg ();
15114   ptr_reg (code, sizeflag);
15115 }
15116
15117 static void
15118 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15119 {
15120   int add;
15121   if (rex & REX_R)
15122     {
15123       USED_REX (REX_R);
15124       add = 8;
15125     }
15126   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15127     {
15128       all_prefixes[last_lock_prefix] = 0;
15129       used_prefixes |= PREFIX_LOCK;
15130       add = 8;
15131     }
15132   else
15133     add = 0;
15134   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15135   oappend_maybe_intel (scratchbuf);
15136 }
15137
15138 static void
15139 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15140 {
15141   int add;
15142   USED_REX (REX_R);
15143   if (rex & REX_R)
15144     add = 8;
15145   else
15146     add = 0;
15147   if (intel_syntax)
15148     sprintf (scratchbuf, "db%d", modrm.reg + add);
15149   else
15150     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15151   oappend (scratchbuf);
15152 }
15153
15154 static void
15155 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15156 {
15157   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15158   oappend_maybe_intel (scratchbuf);
15159 }
15160
15161 static void
15162 OP_R (int bytemode, int sizeflag)
15163 {
15164   /* Skip mod/rm byte.  */
15165   MODRM_CHECK;
15166   codep++;
15167   OP_E_register (bytemode, sizeflag);
15168 }
15169
15170 static void
15171 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15172 {
15173   int reg = modrm.reg;
15174   const char **names;
15175
15176   used_prefixes |= (prefixes & PREFIX_DATA);
15177   if (prefixes & PREFIX_DATA)
15178     {
15179       names = names_xmm;
15180       USED_REX (REX_R);
15181       if (rex & REX_R)
15182         reg += 8;
15183     }
15184   else
15185     names = names_mm;
15186   oappend (names[reg]);
15187 }
15188
15189 static void
15190 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15191 {
15192   int reg = modrm.reg;
15193   const char **names;
15194
15195   USED_REX (REX_R);
15196   if (rex & REX_R)
15197     reg += 8;
15198   if (vex.evex)
15199     {
15200       if (!vex.r)
15201         reg += 16;
15202     }
15203
15204   if (need_vex
15205       && bytemode != xmm_mode
15206       && bytemode != xmmq_mode
15207       && bytemode != evex_half_bcst_xmmq_mode
15208       && bytemode != ymm_mode
15209       && bytemode != scalar_mode)
15210     {
15211       switch (vex.length)
15212         {
15213         case 128:
15214           names = names_xmm;
15215           break;
15216         case 256:
15217           if (vex.w
15218               || (bytemode != vex_vsib_q_w_dq_mode
15219                   && bytemode != vex_vsib_q_w_d_mode))
15220             names = names_ymm;
15221           else
15222             names = names_xmm;
15223           break;
15224         case 512:
15225           names = names_zmm;
15226           break;
15227         default:
15228           abort ();
15229         }
15230     }
15231   else if (bytemode == xmmq_mode
15232            || bytemode == evex_half_bcst_xmmq_mode)
15233     {
15234       switch (vex.length)
15235         {
15236         case 128:
15237         case 256:
15238           names = names_xmm;
15239           break;
15240         case 512:
15241           names = names_ymm;
15242           break;
15243         default:
15244           abort ();
15245         }
15246     }
15247   else if (bytemode == ymm_mode)
15248     names = names_ymm;
15249   else
15250     names = names_xmm;
15251   oappend (names[reg]);
15252 }
15253
15254 static void
15255 OP_EM (int bytemode, int sizeflag)
15256 {
15257   int reg;
15258   const char **names;
15259
15260   if (modrm.mod != 3)
15261     {
15262       if (intel_syntax
15263           && (bytemode == v_mode || bytemode == v_swap_mode))
15264         {
15265           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15266           used_prefixes |= (prefixes & PREFIX_DATA);
15267         }
15268       OP_E (bytemode, sizeflag);
15269       return;
15270     }
15271
15272   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15273     swap_operand ();
15274
15275   /* Skip mod/rm byte.  */
15276   MODRM_CHECK;
15277   codep++;
15278   used_prefixes |= (prefixes & PREFIX_DATA);
15279   reg = modrm.rm;
15280   if (prefixes & PREFIX_DATA)
15281     {
15282       names = names_xmm;
15283       USED_REX (REX_B);
15284       if (rex & REX_B)
15285         reg += 8;
15286     }
15287   else
15288     names = names_mm;
15289   oappend (names[reg]);
15290 }
15291
15292 /* cvt* are the only instructions in sse2 which have
15293    both SSE and MMX operands and also have 0x66 prefix
15294    in their opcode. 0x66 was originally used to differentiate
15295    between SSE and MMX instruction(operands). So we have to handle the
15296    cvt* separately using OP_EMC and OP_MXC */
15297 static void
15298 OP_EMC (int bytemode, int sizeflag)
15299 {
15300   if (modrm.mod != 3)
15301     {
15302       if (intel_syntax && bytemode == v_mode)
15303         {
15304           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15305           used_prefixes |= (prefixes & PREFIX_DATA);
15306         }
15307       OP_E (bytemode, sizeflag);
15308       return;
15309     }
15310
15311   /* Skip mod/rm byte.  */
15312   MODRM_CHECK;
15313   codep++;
15314   used_prefixes |= (prefixes & PREFIX_DATA);
15315   oappend (names_mm[modrm.rm]);
15316 }
15317
15318 static void
15319 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15320 {
15321   used_prefixes |= (prefixes & PREFIX_DATA);
15322   oappend (names_mm[modrm.reg]);
15323 }
15324
15325 static void
15326 OP_EX (int bytemode, int sizeflag)
15327 {
15328   int reg;
15329   const char **names;
15330
15331   /* Skip mod/rm byte.  */
15332   MODRM_CHECK;
15333   codep++;
15334
15335   if (modrm.mod != 3)
15336     {
15337       OP_E_memory (bytemode, sizeflag);
15338       return;
15339     }
15340
15341   reg = modrm.rm;
15342   USED_REX (REX_B);
15343   if (rex & REX_B)
15344     reg += 8;
15345   if (vex.evex)
15346     {
15347       USED_REX (REX_X);
15348       if ((rex & REX_X))
15349         reg += 16;
15350     }
15351
15352   if ((sizeflag & SUFFIX_ALWAYS)
15353       && (bytemode == x_swap_mode
15354           || bytemode == d_swap_mode
15355           || bytemode == d_scalar_swap_mode
15356           || bytemode == q_swap_mode
15357           || bytemode == q_scalar_swap_mode))
15358     swap_operand ();
15359
15360   if (need_vex
15361       && bytemode != xmm_mode
15362       && bytemode != xmmdw_mode
15363       && bytemode != xmmqd_mode
15364       && bytemode != xmm_mb_mode
15365       && bytemode != xmm_mw_mode
15366       && bytemode != xmm_md_mode
15367       && bytemode != xmm_mq_mode
15368       && bytemode != xmm_mdq_mode
15369       && bytemode != xmmq_mode
15370       && bytemode != evex_half_bcst_xmmq_mode
15371       && bytemode != ymm_mode
15372       && bytemode != d_scalar_mode
15373       && bytemode != d_scalar_swap_mode
15374       && bytemode != q_scalar_mode
15375       && bytemode != q_scalar_swap_mode
15376       && bytemode != vex_scalar_w_dq_mode)
15377     {
15378       switch (vex.length)
15379         {
15380         case 128:
15381           names = names_xmm;
15382           break;
15383         case 256:
15384           names = names_ymm;
15385           break;
15386         case 512:
15387           names = names_zmm;
15388           break;
15389         default:
15390           abort ();
15391         }
15392     }
15393   else if (bytemode == xmmq_mode
15394            || bytemode == evex_half_bcst_xmmq_mode)
15395     {
15396       switch (vex.length)
15397         {
15398         case 128:
15399         case 256:
15400           names = names_xmm;
15401           break;
15402         case 512:
15403           names = names_ymm;
15404           break;
15405         default:
15406           abort ();
15407         }
15408     }
15409   else if (bytemode == ymm_mode)
15410     names = names_ymm;
15411   else
15412     names = names_xmm;
15413   oappend (names[reg]);
15414 }
15415
15416 static void
15417 OP_MS (int bytemode, int sizeflag)
15418 {
15419   if (modrm.mod == 3)
15420     OP_EM (bytemode, sizeflag);
15421   else
15422     BadOp ();
15423 }
15424
15425 static void
15426 OP_XS (int bytemode, int sizeflag)
15427 {
15428   if (modrm.mod == 3)
15429     OP_EX (bytemode, sizeflag);
15430   else
15431     BadOp ();
15432 }
15433
15434 static void
15435 OP_M (int bytemode, int sizeflag)
15436 {
15437   if (modrm.mod == 3)
15438     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15439     BadOp ();
15440   else
15441     OP_E (bytemode, sizeflag);
15442 }
15443
15444 static void
15445 OP_0f07 (int bytemode, int sizeflag)
15446 {
15447   if (modrm.mod != 3 || modrm.rm != 0)
15448     BadOp ();
15449   else
15450     OP_E (bytemode, sizeflag);
15451 }
15452
15453 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15454    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15455
15456 static void
15457 NOP_Fixup1 (int bytemode, int sizeflag)
15458 {
15459   if ((prefixes & PREFIX_DATA) != 0
15460       || (rex != 0
15461           && rex != 0x48
15462           && address_mode == mode_64bit))
15463     OP_REG (bytemode, sizeflag);
15464   else
15465     strcpy (obuf, "nop");
15466 }
15467
15468 static void
15469 NOP_Fixup2 (int bytemode, int sizeflag)
15470 {
15471   if ((prefixes & PREFIX_DATA) != 0
15472       || (rex != 0
15473           && rex != 0x48
15474           && address_mode == mode_64bit))
15475     OP_IMREG (bytemode, sizeflag);
15476 }
15477
15478 static const char *const Suffix3DNow[] = {
15479 /* 00 */        NULL,           NULL,           NULL,           NULL,
15480 /* 04 */        NULL,           NULL,           NULL,           NULL,
15481 /* 08 */        NULL,           NULL,           NULL,           NULL,
15482 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15483 /* 10 */        NULL,           NULL,           NULL,           NULL,
15484 /* 14 */        NULL,           NULL,           NULL,           NULL,
15485 /* 18 */        NULL,           NULL,           NULL,           NULL,
15486 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15487 /* 20 */        NULL,           NULL,           NULL,           NULL,
15488 /* 24 */        NULL,           NULL,           NULL,           NULL,
15489 /* 28 */        NULL,           NULL,           NULL,           NULL,
15490 /* 2C */        NULL,           NULL,           NULL,           NULL,
15491 /* 30 */        NULL,           NULL,           NULL,           NULL,
15492 /* 34 */        NULL,           NULL,           NULL,           NULL,
15493 /* 38 */        NULL,           NULL,           NULL,           NULL,
15494 /* 3C */        NULL,           NULL,           NULL,           NULL,
15495 /* 40 */        NULL,           NULL,           NULL,           NULL,
15496 /* 44 */        NULL,           NULL,           NULL,           NULL,
15497 /* 48 */        NULL,           NULL,           NULL,           NULL,
15498 /* 4C */        NULL,           NULL,           NULL,           NULL,
15499 /* 50 */        NULL,           NULL,           NULL,           NULL,
15500 /* 54 */        NULL,           NULL,           NULL,           NULL,
15501 /* 58 */        NULL,           NULL,           NULL,           NULL,
15502 /* 5C */        NULL,           NULL,           NULL,           NULL,
15503 /* 60 */        NULL,           NULL,           NULL,           NULL,
15504 /* 64 */        NULL,           NULL,           NULL,           NULL,
15505 /* 68 */        NULL,           NULL,           NULL,           NULL,
15506 /* 6C */        NULL,           NULL,           NULL,           NULL,
15507 /* 70 */        NULL,           NULL,           NULL,           NULL,
15508 /* 74 */        NULL,           NULL,           NULL,           NULL,
15509 /* 78 */        NULL,           NULL,           NULL,           NULL,
15510 /* 7C */        NULL,           NULL,           NULL,           NULL,
15511 /* 80 */        NULL,           NULL,           NULL,           NULL,
15512 /* 84 */        NULL,           NULL,           NULL,           NULL,
15513 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15514 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15515 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15516 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15517 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15518 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15519 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15520 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15521 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15522 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15523 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15524 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15525 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15526 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15527 /* C0 */        NULL,           NULL,           NULL,           NULL,
15528 /* C4 */        NULL,           NULL,           NULL,           NULL,
15529 /* C8 */        NULL,           NULL,           NULL,           NULL,
15530 /* CC */        NULL,           NULL,           NULL,           NULL,
15531 /* D0 */        NULL,           NULL,           NULL,           NULL,
15532 /* D4 */        NULL,           NULL,           NULL,           NULL,
15533 /* D8 */        NULL,           NULL,           NULL,           NULL,
15534 /* DC */        NULL,           NULL,           NULL,           NULL,
15535 /* E0 */        NULL,           NULL,           NULL,           NULL,
15536 /* E4 */        NULL,           NULL,           NULL,           NULL,
15537 /* E8 */        NULL,           NULL,           NULL,           NULL,
15538 /* EC */        NULL,           NULL,           NULL,           NULL,
15539 /* F0 */        NULL,           NULL,           NULL,           NULL,
15540 /* F4 */        NULL,           NULL,           NULL,           NULL,
15541 /* F8 */        NULL,           NULL,           NULL,           NULL,
15542 /* FC */        NULL,           NULL,           NULL,           NULL,
15543 };
15544
15545 static void
15546 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15547 {
15548   const char *mnemonic;
15549
15550   FETCH_DATA (the_info, codep + 1);
15551   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15552      place where an 8-bit immediate would normally go.  ie. the last
15553      byte of the instruction.  */
15554   obufp = mnemonicendp;
15555   mnemonic = Suffix3DNow[*codep++ & 0xff];
15556   if (mnemonic)
15557     oappend (mnemonic);
15558   else
15559     {
15560       /* Since a variable sized modrm/sib chunk is between the start
15561          of the opcode (0x0f0f) and the opcode suffix, we need to do
15562          all the modrm processing first, and don't know until now that
15563          we have a bad opcode.  This necessitates some cleaning up.  */
15564       op_out[0][0] = '\0';
15565       op_out[1][0] = '\0';
15566       BadOp ();
15567     }
15568   mnemonicendp = obufp;
15569 }
15570
15571 static struct op simd_cmp_op[] =
15572 {
15573   { STRING_COMMA_LEN ("eq") },
15574   { STRING_COMMA_LEN ("lt") },
15575   { STRING_COMMA_LEN ("le") },
15576   { STRING_COMMA_LEN ("unord") },
15577   { STRING_COMMA_LEN ("neq") },
15578   { STRING_COMMA_LEN ("nlt") },
15579   { STRING_COMMA_LEN ("nle") },
15580   { STRING_COMMA_LEN ("ord") }
15581 };
15582
15583 static void
15584 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15585 {
15586   unsigned int cmp_type;
15587
15588   FETCH_DATA (the_info, codep + 1);
15589   cmp_type = *codep++ & 0xff;
15590   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15591     {
15592       char suffix [3];
15593       char *p = mnemonicendp - 2;
15594       suffix[0] = p[0];
15595       suffix[1] = p[1];
15596       suffix[2] = '\0';
15597       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15598       mnemonicendp += simd_cmp_op[cmp_type].len;
15599     }
15600   else
15601     {
15602       /* We have a reserved extension byte.  Output it directly.  */
15603       scratchbuf[0] = '$';
15604       print_operand_value (scratchbuf + 1, 1, cmp_type);
15605       oappend_maybe_intel (scratchbuf);
15606       scratchbuf[0] = '\0';
15607     }
15608 }
15609
15610 static void
15611 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15612           int sizeflag ATTRIBUTE_UNUSED)
15613 {
15614   /* mwaitx %eax,%ecx,%ebx */
15615   if (!intel_syntax)
15616     {
15617       const char **names = (address_mode == mode_64bit
15618                             ? names64 : names32);
15619       strcpy (op_out[0], names[0]);
15620       strcpy (op_out[1], names[1]);
15621       strcpy (op_out[2], names[3]);
15622       two_source_ops = 1;
15623     }
15624   /* Skip mod/rm byte.  */
15625   MODRM_CHECK;
15626   codep++;
15627 }
15628
15629 static void
15630 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15631           int sizeflag ATTRIBUTE_UNUSED)
15632 {
15633   /* mwait %eax,%ecx  */
15634   if (!intel_syntax)
15635     {
15636       const char **names = (address_mode == mode_64bit
15637                             ? names64 : names32);
15638       strcpy (op_out[0], names[0]);
15639       strcpy (op_out[1], names[1]);
15640       two_source_ops = 1;
15641     }
15642   /* Skip mod/rm byte.  */
15643   MODRM_CHECK;
15644   codep++;
15645 }
15646
15647 static void
15648 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15649             int sizeflag ATTRIBUTE_UNUSED)
15650 {
15651   /* monitor %eax,%ecx,%edx"  */
15652   if (!intel_syntax)
15653     {
15654       const char **op1_names;
15655       const char **names = (address_mode == mode_64bit
15656                             ? names64 : names32);
15657
15658       if (!(prefixes & PREFIX_ADDR))
15659         op1_names = (address_mode == mode_16bit
15660                      ? names16 : names);
15661       else
15662         {
15663           /* Remove "addr16/addr32".  */
15664           all_prefixes[last_addr_prefix] = 0;
15665           op1_names = (address_mode != mode_32bit
15666                        ? names32 : names16);
15667           used_prefixes |= PREFIX_ADDR;
15668         }
15669       strcpy (op_out[0], op1_names[0]);
15670       strcpy (op_out[1], names[1]);
15671       strcpy (op_out[2], names[2]);
15672       two_source_ops = 1;
15673     }
15674   /* Skip mod/rm byte.  */
15675   MODRM_CHECK;
15676   codep++;
15677 }
15678
15679 static void
15680 BadOp (void)
15681 {
15682   /* Throw away prefixes and 1st. opcode byte.  */
15683   codep = insn_codep + 1;
15684   oappend ("(bad)");
15685 }
15686
15687 static void
15688 REP_Fixup (int bytemode, int sizeflag)
15689 {
15690   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15691      lods and stos.  */
15692   if (prefixes & PREFIX_REPZ)
15693     all_prefixes[last_repz_prefix] = REP_PREFIX;
15694
15695   switch (bytemode)
15696     {
15697     case al_reg:
15698     case eAX_reg:
15699     case indir_dx_reg:
15700       OP_IMREG (bytemode, sizeflag);
15701       break;
15702     case eDI_reg:
15703       OP_ESreg (bytemode, sizeflag);
15704       break;
15705     case eSI_reg:
15706       OP_DSreg (bytemode, sizeflag);
15707       break;
15708     default:
15709       abort ();
15710       break;
15711     }
15712 }
15713
15714 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15715    "bnd".  */
15716
15717 static void
15718 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15719 {
15720   if (prefixes & PREFIX_REPNZ)
15721     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15722 }
15723
15724 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15725    "notrack".  */
15726
15727 static void
15728 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15729                int sizeflag ATTRIBUTE_UNUSED)
15730 {
15731   if (active_seg_prefix == PREFIX_DS
15732       && (address_mode != mode_64bit || last_data_prefix < 0))
15733     {
15734       /* NOTRACK prefix is only valid on indirect branch instructions.
15735          NB: DATA prefix is unsupported for Intel64.  */
15736       active_seg_prefix = 0;
15737       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15738     }
15739 }
15740
15741 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15742    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15743  */
15744
15745 static void
15746 HLE_Fixup1 (int bytemode, int sizeflag)
15747 {
15748   if (modrm.mod != 3
15749       && (prefixes & PREFIX_LOCK) != 0)
15750     {
15751       if (prefixes & PREFIX_REPZ)
15752         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15753       if (prefixes & PREFIX_REPNZ)
15754         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15755     }
15756
15757   OP_E (bytemode, sizeflag);
15758 }
15759
15760 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15761    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15762  */
15763
15764 static void
15765 HLE_Fixup2 (int bytemode, int sizeflag)
15766 {
15767   if (modrm.mod != 3)
15768     {
15769       if (prefixes & PREFIX_REPZ)
15770         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15771       if (prefixes & PREFIX_REPNZ)
15772         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15773     }
15774
15775   OP_E (bytemode, sizeflag);
15776 }
15777
15778 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15779    "xrelease" for memory operand.  No check for LOCK prefix.   */
15780
15781 static void
15782 HLE_Fixup3 (int bytemode, int sizeflag)
15783 {
15784   if (modrm.mod != 3
15785       && last_repz_prefix > last_repnz_prefix
15786       && (prefixes & PREFIX_REPZ) != 0)
15787     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15788
15789   OP_E (bytemode, sizeflag);
15790 }
15791
15792 static void
15793 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15794 {
15795   USED_REX (REX_W);
15796   if (rex & REX_W)
15797     {
15798       /* Change cmpxchg8b to cmpxchg16b.  */
15799       char *p = mnemonicendp - 2;
15800       mnemonicendp = stpcpy (p, "16b");
15801       bytemode = o_mode;
15802     }
15803   else if ((prefixes & PREFIX_LOCK) != 0)
15804     {
15805       if (prefixes & PREFIX_REPZ)
15806         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15807       if (prefixes & PREFIX_REPNZ)
15808         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15809     }
15810
15811   OP_M (bytemode, sizeflag);
15812 }
15813
15814 static void
15815 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15816 {
15817   const char **names;
15818
15819   if (need_vex)
15820     {
15821       switch (vex.length)
15822         {
15823         case 128:
15824           names = names_xmm;
15825           break;
15826         case 256:
15827           names = names_ymm;
15828           break;
15829         default:
15830           abort ();
15831         }
15832     }
15833   else
15834     names = names_xmm;
15835   oappend (names[reg]);
15836 }
15837
15838 static void
15839 CRC32_Fixup (int bytemode, int sizeflag)
15840 {
15841   /* Add proper suffix to "crc32".  */
15842   char *p = mnemonicendp;
15843
15844   switch (bytemode)
15845     {
15846     case b_mode:
15847       if (intel_syntax)
15848         goto skip;
15849
15850       *p++ = 'b';
15851       break;
15852     case v_mode:
15853       if (intel_syntax)
15854         goto skip;
15855
15856       USED_REX (REX_W);
15857       if (rex & REX_W)
15858         *p++ = 'q';
15859       else
15860         {
15861           if (sizeflag & DFLAG)
15862             *p++ = 'l';
15863           else
15864             *p++ = 'w';
15865           used_prefixes |= (prefixes & PREFIX_DATA);
15866         }
15867       break;
15868     default:
15869       oappend (INTERNAL_DISASSEMBLER_ERROR);
15870       break;
15871     }
15872   mnemonicendp = p;
15873   *p = '\0';
15874
15875 skip:
15876   if (modrm.mod == 3)
15877     {
15878       int add;
15879
15880       /* Skip mod/rm byte.  */
15881       MODRM_CHECK;
15882       codep++;
15883
15884       USED_REX (REX_B);
15885       add = (rex & REX_B) ? 8 : 0;
15886       if (bytemode == b_mode)
15887         {
15888           USED_REX (0);
15889           if (rex)
15890             oappend (names8rex[modrm.rm + add]);
15891           else
15892             oappend (names8[modrm.rm + add]);
15893         }
15894       else
15895         {
15896           USED_REX (REX_W);
15897           if (rex & REX_W)
15898             oappend (names64[modrm.rm + add]);
15899           else if ((prefixes & PREFIX_DATA))
15900             oappend (names16[modrm.rm + add]);
15901           else
15902             oappend (names32[modrm.rm + add]);
15903         }
15904     }
15905   else
15906     OP_E (bytemode, sizeflag);
15907 }
15908
15909 static void
15910 FXSAVE_Fixup (int bytemode, int sizeflag)
15911 {
15912   /* Add proper suffix to "fxsave" and "fxrstor".  */
15913   USED_REX (REX_W);
15914   if (rex & REX_W)
15915     {
15916       char *p = mnemonicendp;
15917       *p++ = '6';
15918       *p++ = '4';
15919       *p = '\0';
15920       mnemonicendp = p;
15921     }
15922   OP_M (bytemode, sizeflag);
15923 }
15924
15925 static void
15926 PCMPESTR_Fixup (int bytemode, int sizeflag)
15927 {
15928   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15929   if (!intel_syntax)
15930     {
15931       char *p = mnemonicendp;
15932
15933       USED_REX (REX_W);
15934       if (rex & REX_W)
15935         *p++ = 'q';
15936       else if (sizeflag & SUFFIX_ALWAYS)
15937         *p++ = 'l';
15938
15939       *p = '\0';
15940       mnemonicendp = p;
15941     }
15942
15943   OP_EX (bytemode, sizeflag);
15944 }
15945
15946 /* Display the destination register operand for instructions with
15947    VEX. */
15948
15949 static void
15950 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15951 {
15952   int reg;
15953   const char **names;
15954
15955   if (!need_vex)
15956     abort ();
15957
15958   if (!need_vex_reg)
15959     return;
15960
15961   reg = vex.register_specifier;
15962   vex.register_specifier = 0;
15963   if (address_mode != mode_64bit)
15964     reg &= 7;
15965   else if (vex.evex && !vex.v)
15966     reg += 16;
15967
15968   if (bytemode == vex_scalar_mode)
15969     {
15970       oappend (names_xmm[reg]);
15971       return;
15972     }
15973
15974   switch (vex.length)
15975     {
15976     case 128:
15977       switch (bytemode)
15978         {
15979         case vex_mode:
15980         case vex128_mode:
15981         case vex_vsib_q_w_dq_mode:
15982         case vex_vsib_q_w_d_mode:
15983           names = names_xmm;
15984           break;
15985         case dq_mode:
15986           if (rex & REX_W)
15987             names = names64;
15988           else
15989             names = names32;
15990           break;
15991         case mask_bd_mode:
15992         case mask_mode:
15993           if (reg > 0x7)
15994             {
15995               oappend ("(bad)");
15996               return;
15997             }
15998           names = names_mask;
15999           break;
16000         default:
16001           abort ();
16002           return;
16003         }
16004       break;
16005     case 256:
16006       switch (bytemode)
16007         {
16008         case vex_mode:
16009         case vex256_mode:
16010           names = names_ymm;
16011           break;
16012         case vex_vsib_q_w_dq_mode:
16013         case vex_vsib_q_w_d_mode:
16014           names = vex.w ? names_ymm : names_xmm;
16015           break;
16016         case mask_bd_mode:
16017         case mask_mode:
16018           if (reg > 0x7)
16019             {
16020               oappend ("(bad)");
16021               return;
16022             }
16023           names = names_mask;
16024           break;
16025         default:
16026           /* See PR binutils/20893 for a reproducer.  */
16027           oappend ("(bad)");
16028           return;
16029         }
16030       break;
16031     case 512:
16032       names = names_zmm;
16033       break;
16034     default:
16035       abort ();
16036       break;
16037     }
16038   oappend (names[reg]);
16039 }
16040
16041 /* Get the VEX immediate byte without moving codep.  */
16042
16043 static unsigned char
16044 get_vex_imm8 (int sizeflag, int opnum)
16045 {
16046   int bytes_before_imm = 0;
16047
16048   if (modrm.mod != 3)
16049     {
16050       /* There are SIB/displacement bytes.  */
16051       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16052         {
16053           /* 32/64 bit address mode */
16054           int base = modrm.rm;
16055
16056           /* Check SIB byte.  */
16057           if (base == 4)
16058             {
16059               FETCH_DATA (the_info, codep + 1);
16060               base = *codep & 7;
16061               /* When decoding the third source, don't increase
16062                  bytes_before_imm as this has already been incremented
16063                  by one in OP_E_memory while decoding the second
16064                  source operand.  */
16065               if (opnum == 0)
16066                 bytes_before_imm++;
16067             }
16068
16069           /* Don't increase bytes_before_imm when decoding the third source,
16070              it has already been incremented by OP_E_memory while decoding
16071              the second source operand.  */
16072           if (opnum == 0)
16073             {
16074               switch (modrm.mod)
16075                 {
16076                   case 0:
16077                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16078                        SIB == 5, there is a 4 byte displacement.  */
16079                     if (base != 5)
16080                       /* No displacement. */
16081                       break;
16082                     /* Fall through.  */
16083                   case 2:
16084                     /* 4 byte displacement.  */
16085                     bytes_before_imm += 4;
16086                     break;
16087                   case 1:
16088                     /* 1 byte displacement.  */
16089                     bytes_before_imm++;
16090                     break;
16091                 }
16092             }
16093         }
16094       else
16095         {
16096           /* 16 bit address mode */
16097           /* Don't increase bytes_before_imm when decoding the third source,
16098              it has already been incremented by OP_E_memory while decoding
16099              the second source operand.  */
16100           if (opnum == 0)
16101             {
16102               switch (modrm.mod)
16103                 {
16104                 case 0:
16105                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16106                   if (modrm.rm != 6)
16107                     /* No displacement. */
16108                     break;
16109                   /* Fall through.  */
16110                 case 2:
16111                   /* 2 byte displacement.  */
16112                   bytes_before_imm += 2;
16113                   break;
16114                 case 1:
16115                   /* 1 byte displacement: when decoding the third source,
16116                      don't increase bytes_before_imm as this has already
16117                      been incremented by one in OP_E_memory while decoding
16118                      the second source operand.  */
16119                   if (opnum == 0)
16120                     bytes_before_imm++;
16121
16122                   break;
16123                 }
16124             }
16125         }
16126     }
16127
16128   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16129   return codep [bytes_before_imm];
16130 }
16131
16132 static void
16133 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16134 {
16135   const char **names;
16136
16137   if (reg == -1 && modrm.mod != 3)
16138     {
16139       OP_E_memory (bytemode, sizeflag);
16140       return;
16141     }
16142   else
16143     {
16144       if (reg == -1)
16145         {
16146           reg = modrm.rm;
16147           USED_REX (REX_B);
16148           if (rex & REX_B)
16149             reg += 8;
16150         }
16151       if (address_mode != mode_64bit)
16152         reg &= 7;
16153     }
16154
16155   switch (vex.length)
16156     {
16157     case 128:
16158       names = names_xmm;
16159       break;
16160     case 256:
16161       names = names_ymm;
16162       break;
16163     default:
16164       abort ();
16165     }
16166   oappend (names[reg]);
16167 }
16168
16169 static void
16170 OP_EX_VexImmW (int bytemode, int sizeflag)
16171 {
16172   int reg = -1;
16173   static unsigned char vex_imm8;
16174
16175   if (vex_w_done == 0)
16176     {
16177       vex_w_done = 1;
16178
16179       /* Skip mod/rm byte.  */
16180       MODRM_CHECK;
16181       codep++;
16182
16183       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16184
16185       if (vex.w)
16186           reg = vex_imm8 >> 4;
16187
16188       OP_EX_VexReg (bytemode, sizeflag, reg);
16189     }
16190   else if (vex_w_done == 1)
16191     {
16192       vex_w_done = 2;
16193
16194       if (!vex.w)
16195           reg = vex_imm8 >> 4;
16196
16197       OP_EX_VexReg (bytemode, sizeflag, reg);
16198     }
16199   else
16200     {
16201       /* Output the imm8 directly.  */
16202       scratchbuf[0] = '$';
16203       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16204       oappend_maybe_intel (scratchbuf);
16205       scratchbuf[0] = '\0';
16206       codep++;
16207     }
16208 }
16209
16210 static void
16211 OP_Vex_2src (int bytemode, int sizeflag)
16212 {
16213   if (modrm.mod == 3)
16214     {
16215       int reg = modrm.rm;
16216       USED_REX (REX_B);
16217       if (rex & REX_B)
16218         reg += 8;
16219       oappend (names_xmm[reg]);
16220     }
16221   else
16222     {
16223       if (intel_syntax
16224           && (bytemode == v_mode || bytemode == v_swap_mode))
16225         {
16226           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16227           used_prefixes |= (prefixes & PREFIX_DATA);
16228         }
16229       OP_E (bytemode, sizeflag);
16230     }
16231 }
16232
16233 static void
16234 OP_Vex_2src_1 (int bytemode, int sizeflag)
16235 {
16236   if (modrm.mod == 3)
16237     {
16238       /* Skip mod/rm byte.   */
16239       MODRM_CHECK;
16240       codep++;
16241     }
16242
16243   if (vex.w)
16244     {
16245       unsigned int reg = vex.register_specifier;
16246       vex.register_specifier = 0;
16247
16248       if (address_mode != mode_64bit)
16249         reg &= 7;
16250       oappend (names_xmm[reg]);
16251     }
16252   else
16253     OP_Vex_2src (bytemode, sizeflag);
16254 }
16255
16256 static void
16257 OP_Vex_2src_2 (int bytemode, int sizeflag)
16258 {
16259   if (vex.w)
16260     OP_Vex_2src (bytemode, sizeflag);
16261   else
16262     {
16263       unsigned int reg = vex.register_specifier;
16264       vex.register_specifier = 0;
16265
16266       if (address_mode != mode_64bit)
16267         reg &= 7;
16268       oappend (names_xmm[reg]);
16269     }
16270 }
16271
16272 static void
16273 OP_EX_VexW (int bytemode, int sizeflag)
16274 {
16275   int reg = -1;
16276
16277   if (!vex_w_done)
16278     {
16279       /* Skip mod/rm byte.  */
16280       MODRM_CHECK;
16281       codep++;
16282
16283       if (vex.w)
16284         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16285     }
16286   else
16287     {
16288       if (!vex.w)
16289         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16290     }
16291
16292   OP_EX_VexReg (bytemode, sizeflag, reg);
16293
16294   if (vex_w_done)
16295     codep++;
16296   vex_w_done = 1;
16297 }
16298
16299 static void
16300 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16301 {
16302   int reg;
16303   const char **names;
16304
16305   FETCH_DATA (the_info, codep + 1);
16306   reg = *codep++;
16307
16308   if (bytemode != x_mode)
16309     abort ();
16310
16311   reg >>= 4;
16312   if (address_mode != mode_64bit)
16313     reg &= 7;
16314
16315   switch (vex.length)
16316     {
16317     case 128:
16318       names = names_xmm;
16319       break;
16320     case 256:
16321       names = names_ymm;
16322       break;
16323     default:
16324       abort ();
16325     }
16326   oappend (names[reg]);
16327 }
16328
16329 static void
16330 OP_XMM_VexW (int bytemode, int sizeflag)
16331 {
16332   /* Turn off the REX.W bit since it is used for swapping operands
16333      now.  */
16334   rex &= ~REX_W;
16335   OP_XMM (bytemode, sizeflag);
16336 }
16337
16338 static void
16339 OP_EX_Vex (int bytemode, int sizeflag)
16340 {
16341   if (modrm.mod != 3)
16342     need_vex_reg = 0;
16343   OP_EX (bytemode, sizeflag);
16344 }
16345
16346 static void
16347 OP_XMM_Vex (int bytemode, int sizeflag)
16348 {
16349   if (modrm.mod != 3)
16350     need_vex_reg = 0;
16351   OP_XMM (bytemode, sizeflag);
16352 }
16353
16354 static struct op vex_cmp_op[] =
16355 {
16356   { STRING_COMMA_LEN ("eq") },
16357   { STRING_COMMA_LEN ("lt") },
16358   { STRING_COMMA_LEN ("le") },
16359   { STRING_COMMA_LEN ("unord") },
16360   { STRING_COMMA_LEN ("neq") },
16361   { STRING_COMMA_LEN ("nlt") },
16362   { STRING_COMMA_LEN ("nle") },
16363   { STRING_COMMA_LEN ("ord") },
16364   { STRING_COMMA_LEN ("eq_uq") },
16365   { STRING_COMMA_LEN ("nge") },
16366   { STRING_COMMA_LEN ("ngt") },
16367   { STRING_COMMA_LEN ("false") },
16368   { STRING_COMMA_LEN ("neq_oq") },
16369   { STRING_COMMA_LEN ("ge") },
16370   { STRING_COMMA_LEN ("gt") },
16371   { STRING_COMMA_LEN ("true") },
16372   { STRING_COMMA_LEN ("eq_os") },
16373   { STRING_COMMA_LEN ("lt_oq") },
16374   { STRING_COMMA_LEN ("le_oq") },
16375   { STRING_COMMA_LEN ("unord_s") },
16376   { STRING_COMMA_LEN ("neq_us") },
16377   { STRING_COMMA_LEN ("nlt_uq") },
16378   { STRING_COMMA_LEN ("nle_uq") },
16379   { STRING_COMMA_LEN ("ord_s") },
16380   { STRING_COMMA_LEN ("eq_us") },
16381   { STRING_COMMA_LEN ("nge_uq") },
16382   { STRING_COMMA_LEN ("ngt_uq") },
16383   { STRING_COMMA_LEN ("false_os") },
16384   { STRING_COMMA_LEN ("neq_os") },
16385   { STRING_COMMA_LEN ("ge_oq") },
16386   { STRING_COMMA_LEN ("gt_oq") },
16387   { STRING_COMMA_LEN ("true_us") },
16388 };
16389
16390 static void
16391 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16392 {
16393   unsigned int cmp_type;
16394
16395   FETCH_DATA (the_info, codep + 1);
16396   cmp_type = *codep++ & 0xff;
16397   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16398     {
16399       char suffix [3];
16400       char *p = mnemonicendp - 2;
16401       suffix[0] = p[0];
16402       suffix[1] = p[1];
16403       suffix[2] = '\0';
16404       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16405       mnemonicendp += vex_cmp_op[cmp_type].len;
16406     }
16407   else
16408     {
16409       /* We have a reserved extension byte.  Output it directly.  */
16410       scratchbuf[0] = '$';
16411       print_operand_value (scratchbuf + 1, 1, cmp_type);
16412       oappend_maybe_intel (scratchbuf);
16413       scratchbuf[0] = '\0';
16414     }
16415 }
16416
16417 static void
16418 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16419              int sizeflag ATTRIBUTE_UNUSED)
16420 {
16421   unsigned int cmp_type;
16422
16423   if (!vex.evex)
16424     abort ();
16425
16426   FETCH_DATA (the_info, codep + 1);
16427   cmp_type = *codep++ & 0xff;
16428   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16429      If it's the case, print suffix, otherwise - print the immediate.  */
16430   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16431       && cmp_type != 3
16432       && cmp_type != 7)
16433     {
16434       char suffix [3];
16435       char *p = mnemonicendp - 2;
16436
16437       /* vpcmp* can have both one- and two-lettered suffix.  */
16438       if (p[0] == 'p')
16439         {
16440           p++;
16441           suffix[0] = p[0];
16442           suffix[1] = '\0';
16443         }
16444       else
16445         {
16446           suffix[0] = p[0];
16447           suffix[1] = p[1];
16448           suffix[2] = '\0';
16449         }
16450
16451       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16452       mnemonicendp += simd_cmp_op[cmp_type].len;
16453     }
16454   else
16455     {
16456       /* We have a reserved extension byte.  Output it directly.  */
16457       scratchbuf[0] = '$';
16458       print_operand_value (scratchbuf + 1, 1, cmp_type);
16459       oappend_maybe_intel (scratchbuf);
16460       scratchbuf[0] = '\0';
16461     }
16462 }
16463
16464 static const struct op xop_cmp_op[] =
16465 {
16466   { STRING_COMMA_LEN ("lt") },
16467   { STRING_COMMA_LEN ("le") },
16468   { STRING_COMMA_LEN ("gt") },
16469   { STRING_COMMA_LEN ("ge") },
16470   { STRING_COMMA_LEN ("eq") },
16471   { STRING_COMMA_LEN ("neq") },
16472   { STRING_COMMA_LEN ("false") },
16473   { STRING_COMMA_LEN ("true") }
16474 };
16475
16476 static void
16477 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16478              int sizeflag ATTRIBUTE_UNUSED)
16479 {
16480   unsigned int cmp_type;
16481
16482   FETCH_DATA (the_info, codep + 1);
16483   cmp_type = *codep++ & 0xff;
16484   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16485     {
16486       char suffix[3];
16487       char *p = mnemonicendp - 2;
16488
16489       /* vpcom* can have both one- and two-lettered suffix.  */
16490       if (p[0] == 'm')
16491         {
16492           p++;
16493           suffix[0] = p[0];
16494           suffix[1] = '\0';
16495         }
16496       else
16497         {
16498           suffix[0] = p[0];
16499           suffix[1] = p[1];
16500           suffix[2] = '\0';
16501         }
16502
16503       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16504       mnemonicendp += xop_cmp_op[cmp_type].len;
16505     }
16506   else
16507     {
16508       /* We have a reserved extension byte.  Output it directly.  */
16509       scratchbuf[0] = '$';
16510       print_operand_value (scratchbuf + 1, 1, cmp_type);
16511       oappend_maybe_intel (scratchbuf);
16512       scratchbuf[0] = '\0';
16513     }
16514 }
16515
16516 static const struct op pclmul_op[] =
16517 {
16518   { STRING_COMMA_LEN ("lql") },
16519   { STRING_COMMA_LEN ("hql") },
16520   { STRING_COMMA_LEN ("lqh") },
16521   { STRING_COMMA_LEN ("hqh") }
16522 };
16523
16524 static void
16525 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16526               int sizeflag ATTRIBUTE_UNUSED)
16527 {
16528   unsigned int pclmul_type;
16529
16530   FETCH_DATA (the_info, codep + 1);
16531   pclmul_type = *codep++ & 0xff;
16532   switch (pclmul_type)
16533     {
16534     case 0x10:
16535       pclmul_type = 2;
16536       break;
16537     case 0x11:
16538       pclmul_type = 3;
16539       break;
16540     default:
16541       break;
16542     }
16543   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16544     {
16545       char suffix [4];
16546       char *p = mnemonicendp - 3;
16547       suffix[0] = p[0];
16548       suffix[1] = p[1];
16549       suffix[2] = p[2];
16550       suffix[3] = '\0';
16551       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16552       mnemonicendp += pclmul_op[pclmul_type].len;
16553     }
16554   else
16555     {
16556       /* We have a reserved extension byte.  Output it directly.  */
16557       scratchbuf[0] = '$';
16558       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16559       oappend_maybe_intel (scratchbuf);
16560       scratchbuf[0] = '\0';
16561     }
16562 }
16563
16564 static void
16565 MOVBE_Fixup (int bytemode, int sizeflag)
16566 {
16567   /* Add proper suffix to "movbe".  */
16568   char *p = mnemonicendp;
16569
16570   switch (bytemode)
16571     {
16572     case v_mode:
16573       if (intel_syntax)
16574         goto skip;
16575
16576       USED_REX (REX_W);
16577       if (sizeflag & SUFFIX_ALWAYS)
16578         {
16579           if (rex & REX_W)
16580             *p++ = 'q';
16581           else
16582             {
16583               if (sizeflag & DFLAG)
16584                 *p++ = 'l';
16585               else
16586                 *p++ = 'w';
16587               used_prefixes |= (prefixes & PREFIX_DATA);
16588             }
16589         }
16590       break;
16591     default:
16592       oappend (INTERNAL_DISASSEMBLER_ERROR);
16593       break;
16594     }
16595   mnemonicendp = p;
16596   *p = '\0';
16597
16598 skip:
16599   OP_M (bytemode, sizeflag);
16600 }
16601
16602 static void
16603 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16604 {
16605   int reg;
16606   const char **names;
16607
16608   /* Skip mod/rm byte.  */
16609   MODRM_CHECK;
16610   codep++;
16611
16612   if (rex & REX_W)
16613     names = names64;
16614   else
16615     names = names32;
16616
16617   reg = modrm.rm;
16618   USED_REX (REX_B);
16619   if (rex & REX_B)
16620     reg += 8;
16621
16622   oappend (names[reg]);
16623 }
16624
16625 static void
16626 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16627 {
16628   const char **names;
16629   unsigned int reg = vex.register_specifier;
16630   vex.register_specifier = 0;
16631
16632   if (rex & REX_W)
16633     names = names64;
16634   else
16635     names = names32;
16636
16637   if (address_mode != mode_64bit)
16638     reg &= 7;
16639   oappend (names[reg]);
16640 }
16641
16642 static void
16643 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16644 {
16645   if (!vex.evex
16646       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16647     abort ();
16648
16649   USED_REX (REX_R);
16650   if ((rex & REX_R) != 0 || !vex.r)
16651     {
16652       BadOp ();
16653       return;
16654     }
16655
16656   oappend (names_mask [modrm.reg]);
16657 }
16658
16659 static void
16660 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16661 {
16662   if (!vex.evex
16663       || (bytemode != evex_rounding_mode
16664           && bytemode != evex_rounding_64_mode
16665           && bytemode != evex_sae_mode))
16666     abort ();
16667   if (modrm.mod == 3 && vex.b)
16668     switch (bytemode)
16669       {
16670       case evex_rounding_64_mode:
16671         if (address_mode != mode_64bit)
16672           {
16673             oappend ("(bad)");
16674             break;
16675           }
16676         /* Fall through.  */
16677       case evex_rounding_mode:
16678         oappend (names_rounding[vex.ll]);
16679         break;
16680       case evex_sae_mode:
16681         oappend ("{sae}");
16682         break;
16683       default:
16684         break;
16685       }
16686 }