opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void HLE_Fixup1 (int, int);
 112 static void HLE_Fixup2 (int, int);
 113 static void HLE_Fixup3 (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void CRC32_Fixup (int, int);
 117 static void FXSAVE_Fixup (int, int);
 118 static void OP_LWPCB_E (int, int);
 119 static void OP_LWP_E (int, int);
 120 static void OP_Vex_2src_1 (int, int);
 121 static void OP_Vex_2src_2 (int, int);
 122
 123 static void MOVBE_Fixup (int, int);
 124
 125 struct dis_private {
 126   /* Points to first byte not fetched.  */
 127   bfd_byte *max_fetched;
 128   bfd_byte the_buffer[MAX_MNEM_SIZE];
 129   bfd_vma insn_start;
 130   int orig_sizeflag;
 131   jmp_buf bailout;
 132 };
 133
 134 enum address_mode
 135 {
 136   mode_16bit,
 137   mode_32bit,
 138   mode_64bit
 139 };
 140
 141 enum address_mode address_mode;
 142
 143 /* Flags for the prefixes for the current instruction.  See below.  */
 144 static int prefixes;
 145
 146 /* REX prefix the current instruction.  See below.  */
 147 static int rex;
 148 /* Bits of REX we've already used.  */
 149 static int rex_used;
 150 /* REX bits in original REX prefix ignored.  */
 151 static int rex_ignored;
 152 /* Mark parts used in the REX prefix.  When we are testing for
 153    empty prefix (for 8bit register REX extension), just mask it
 154    out.  Otherwise test for REX bit is excuse for existence of REX
 155    only in case value is nonzero.  */
 156 #define USED_REX(value)                                 \
 157   {                                                     \
 158     if (value)                                          \
 159       {                                                 \
 160         if ((rex & value))                              \
 161           rex_used |= (value) | REX_OPCODE;             \
 162       }                                                 \
 163     else                                                \
 164       rex_used |= REX_OPCODE;                           \
 165   }
 166
 167 /* Flags for prefixes which we somehow handled when printing the
 168    current instruction.  */
 169 static int used_prefixes;
 170
 171 /* Flags stored in PREFIXES.  */
 172 #define PREFIX_REPZ 1
 173 #define PREFIX_REPNZ 2
 174 #define PREFIX_LOCK 4
 175 #define PREFIX_CS 8
 176 #define PREFIX_SS 0x10
 177 #define PREFIX_DS 0x20
 178 #define PREFIX_ES 0x40
 179 #define PREFIX_FS 0x80
 180 #define PREFIX_GS 0x100
 181 #define PREFIX_DATA 0x200
 182 #define PREFIX_ADDR 0x400
 183 #define PREFIX_FWAIT 0x800
 184
 185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 186    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 187    on error.  */
 188 #define FETCH_DATA(info, addr) \
 189   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 190    ? 1 : fetch_data ((info), (addr)))
 191
 192 static int
 193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 194 {
 195   int status;
 196   struct dis_private *priv = (struct dis_private *) info->private_data;
 197   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 198
 199   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 200     status = (*info->read_memory_func) (start,
 201                                         priv->max_fetched,
 202                                         addr - priv->max_fetched,
 203                                         info);
 204   else
 205     status = -1;
 206   if (status != 0)
 207     {
 208       /* If we did manage to read at least one byte, then
 209          print_insn_i386 will do something sensible.  Otherwise, print
 210          an error.  We do that here because this is where we know
 211          STATUS.  */
 212       if (priv->max_fetched == priv->the_buffer)
 213         (*info->memory_error_func) (status, start, info);
 214       longjmp (priv->bailout, 1);
 215     }
 216   else
 217     priv->max_fetched = addr;
 218   return 1;
 219 }
 220
 221 #define XX { NULL, 0 }
 222 #define Bad_Opcode NULL, { { NULL, 0 } }
 223
 224 #define Eb { OP_E, b_mode }
 225 #define EbS { OP_E, b_swap_mode }
 226 #define Ev { OP_E, v_mode }
 227 #define EvS { OP_E, v_swap_mode }
 228 #define Ed { OP_E, d_mode }
 229 #define Edq { OP_E, dq_mode }
 230 #define Edqw { OP_E, dqw_mode }
 231 #define Edqb { OP_E, dqb_mode }
 232 #define Edqd { OP_E, dqd_mode }
 233 #define Eq { OP_E, q_mode }
 234 #define indirEv { OP_indirE, stack_v_mode }
 235 #define indirEp { OP_indirE, f_mode }
 236 #define stackEv { OP_E, stack_v_mode }
 237 #define Em { OP_E, m_mode }
 238 #define Ew { OP_E, w_mode }
 239 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 240 #define Ma { OP_M, a_mode }
 241 #define Mb { OP_M, b_mode }
 242 #define Md { OP_M, d_mode }
 243 #define Mo { OP_M, o_mode }
 244 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 245 #define Mq { OP_M, q_mode }
 246 #define Mx { OP_M, x_mode }
 247 #define Mxmm { OP_M, xmm_mode }
 248 #define Gb { OP_G, b_mode }
 249 #define Gv { OP_G, v_mode }
 250 #define Gd { OP_G, d_mode }
 251 #define Gdq { OP_G, dq_mode }
 252 #define Gm { OP_G, m_mode }
 253 #define Gw { OP_G, w_mode }
 254 #define Rd { OP_R, d_mode }
 255 #define Rm { OP_R, m_mode }
 256 #define Ib { OP_I, b_mode }
 257 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 258 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 259 #define Iv { OP_I, v_mode }
 260 #define sIv { OP_sI, v_mode }
 261 #define Iq { OP_I, q_mode }
 262 #define Iv64 { OP_I64, v_mode }
 263 #define Iw { OP_I, w_mode }
 264 #define I1 { OP_I, const_1_mode }
 265 #define Jb { OP_J, b_mode }
 266 #define Jv { OP_J, v_mode }
 267 #define Cm { OP_C, m_mode }
 268 #define Dm { OP_D, m_mode }
 269 #define Td { OP_T, d_mode }
 270 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 271
 272 #define RMeAX { OP_REG, eAX_reg }
 273 #define RMeBX { OP_REG, eBX_reg }
 274 #define RMeCX { OP_REG, eCX_reg }
 275 #define RMeDX { OP_REG, eDX_reg }
 276 #define RMeSP { OP_REG, eSP_reg }
 277 #define RMeBP { OP_REG, eBP_reg }
 278 #define RMeSI { OP_REG, eSI_reg }
 279 #define RMeDI { OP_REG, eDI_reg }
 280 #define RMrAX { OP_REG, rAX_reg }
 281 #define RMrBX { OP_REG, rBX_reg }
 282 #define RMrCX { OP_REG, rCX_reg }
 283 #define RMrDX { OP_REG, rDX_reg }
 284 #define RMrSP { OP_REG, rSP_reg }
 285 #define RMrBP { OP_REG, rBP_reg }
 286 #define RMrSI { OP_REG, rSI_reg }
 287 #define RMrDI { OP_REG, rDI_reg }
 288 #define RMAL { OP_REG, al_reg }
 289 #define RMCL { OP_REG, cl_reg }
 290 #define RMDL { OP_REG, dl_reg }
 291 #define RMBL { OP_REG, bl_reg }
 292 #define RMAH { OP_REG, ah_reg }
 293 #define RMCH { OP_REG, ch_reg }
 294 #define RMDH { OP_REG, dh_reg }
 295 #define RMBH { OP_REG, bh_reg }
 296 #define RMAX { OP_REG, ax_reg }
 297 #define RMDX { OP_REG, dx_reg }
 298
 299 #define eAX { OP_IMREG, eAX_reg }
 300 #define eBX { OP_IMREG, eBX_reg }
 301 #define eCX { OP_IMREG, eCX_reg }
 302 #define eDX { OP_IMREG, eDX_reg }
 303 #define eSP { OP_IMREG, eSP_reg }
 304 #define eBP { OP_IMREG, eBP_reg }
 305 #define eSI { OP_IMREG, eSI_reg }
 306 #define eDI { OP_IMREG, eDI_reg }
 307 #define AL { OP_IMREG, al_reg }
 308 #define CL { OP_IMREG, cl_reg }
 309 #define DL { OP_IMREG, dl_reg }
 310 #define BL { OP_IMREG, bl_reg }
 311 #define AH { OP_IMREG, ah_reg }
 312 #define CH { OP_IMREG, ch_reg }
 313 #define DH { OP_IMREG, dh_reg }
 314 #define BH { OP_IMREG, bh_reg }
 315 #define AX { OP_IMREG, ax_reg }
 316 #define DX { OP_IMREG, dx_reg }
 317 #define zAX { OP_IMREG, z_mode_ax_reg }
 318 #define indirDX { OP_IMREG, indir_dx_reg }
 319
 320 #define Sw { OP_SEG, w_mode }
 321 #define Sv { OP_SEG, v_mode }
 322 #define Ap { OP_DIR, 0 }
 323 #define Ob { OP_OFF64, b_mode }
 324 #define Ov { OP_OFF64, v_mode }
 325 #define Xb { OP_DSreg, eSI_reg }
 326 #define Xv { OP_DSreg, eSI_reg }
 327 #define Xz { OP_DSreg, eSI_reg }
 328 #define Yb { OP_ESreg, eDI_reg }
 329 #define Yv { OP_ESreg, eDI_reg }
 330 #define DSBX { OP_DSreg, eBX_reg }
 331
 332 #define es { OP_REG, es_reg }
 333 #define ss { OP_REG, ss_reg }
 334 #define cs { OP_REG, cs_reg }
 335 #define ds { OP_REG, ds_reg }
 336 #define fs { OP_REG, fs_reg }
 337 #define gs { OP_REG, gs_reg }
 338
 339 #define MX { OP_MMX, 0 }
 340 #define XM { OP_XMM, 0 }
 341 #define XMScalar { OP_XMM, scalar_mode }
 342 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 343 #define XMM { OP_XMM, xmm_mode }
 344 #define EM { OP_EM, v_mode }
 345 #define EMS { OP_EM, v_swap_mode }
 346 #define EMd { OP_EM, d_mode }
 347 #define EMx { OP_EM, x_mode }
 348 #define EXw { OP_EX, w_mode }
 349 #define EXd { OP_EX, d_mode }
 350 #define EXdScalar { OP_EX, d_scalar_mode }
 351 #define EXdS { OP_EX, d_swap_mode }
 352 #define EXq { OP_EX, q_mode }
 353 #define EXqScalar { OP_EX, q_scalar_mode }
 354 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 355 #define EXqS { OP_EX, q_swap_mode }
 356 #define EXx { OP_EX, x_mode }
 357 #define EXxS { OP_EX, x_swap_mode }
 358 #define EXxmm { OP_EX, xmm_mode }
 359 #define EXxmmq { OP_EX, xmmq_mode }
 360 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 361 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 362 #define EXxmm_md { OP_EX, xmm_md_mode }
 363 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 364 #define EXxmmdw { OP_EX, xmmdw_mode }
 365 #define EXxmmqd { OP_EX, xmmqd_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 368 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 369 #define MS { OP_MS, v_mode }
 370 #define XS { OP_XS, v_mode }
 371 #define EMCq { OP_EMC, q_mode }
 372 #define MXC { OP_MXC, 0 }
 373 #define OPSUF { OP_3DNowSuffix, 0 }
 374 #define CMP { CMP_Fixup, 0 }
 375 #define XMM0 { XMM_Fixup, 0 }
 376 #define FXSAVE { FXSAVE_Fixup, 0 }
 377 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 378 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 379
 380 #define Vex { OP_VEX, vex_mode }
 381 #define VexScalar { OP_VEX, vex_scalar_mode }
 382 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 383 #define Vex128 { OP_VEX, vex128_mode }
 384 #define Vex256 { OP_VEX, vex256_mode }
 385 #define VexGdq { OP_VEX, dq_mode }
 386 #define VexI4 { VEXI4_Fixup, 0}
 387 #define EXdVex { OP_EX_Vex, d_mode }
 388 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 389 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 390 #define EXqVex { OP_EX_Vex, q_mode }
 391 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 392 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 393 #define EXVexW { OP_EX_VexW, x_mode }
 394 #define EXdVexW { OP_EX_VexW, d_mode }
 395 #define EXqVexW { OP_EX_VexW, q_mode }
 396 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 397 #define XMVex { OP_XMM_Vex, 0 }
 398 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 399 #define XMVexW { OP_XMM_VexW, 0 }
 400 #define XMVexI4 { OP_REG_VexI4, x_mode }
 401 #define PCLMUL { PCLMUL_Fixup, 0 }
 402 #define VZERO { VZERO_Fixup, 0 }
 403 #define VCMP { VCMP_Fixup, 0 }
 404
 405 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 406 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 407
 408 /* Used handle "rep" prefix for string instructions.  */
 409 #define Xbr { REP_Fixup, eSI_reg }
 410 #define Xvr { REP_Fixup, eSI_reg }
 411 #define Ybr { REP_Fixup, eDI_reg }
 412 #define Yvr { REP_Fixup, eDI_reg }
 413 #define Yzr { REP_Fixup, eDI_reg }
 414 #define indirDXr { REP_Fixup, indir_dx_reg }
 415 #define ALr { REP_Fixup, al_reg }
 416 #define eAXr { REP_Fixup, eAX_reg }
 417
 418 /* Used handle HLE prefix for lockable instructions.  */
 419 #define Ebh1 { HLE_Fixup1, b_mode }
 420 #define Evh1 { HLE_Fixup1, v_mode }
 421 #define Ebh2 { HLE_Fixup2, b_mode }
 422 #define Evh2 { HLE_Fixup2, v_mode }
 423 #define Ebh3 { HLE_Fixup3, b_mode }
 424 #define Evh3 { HLE_Fixup3, v_mode }
 425
 426 #define cond_jump_flag { NULL, cond_jump_mode }
 427 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 428
 429 /* bits in sizeflag */
 430 #define SUFFIX_ALWAYS 4
 431 #define AFLAG 2
 432 #define DFLAG 1
 433
 434 enum
 435 {
 436   /* byte operand */
 437   b_mode = 1,
 438   /* byte operand with operand swapped */
 439   b_swap_mode,
 440   /* byte operand, sign extend like 'T' suffix */
 441   b_T_mode,
 442   /* operand size depends on prefixes */
 443   v_mode,
 444   /* operand size depends on prefixes with operand swapped */
 445   v_swap_mode,
 446   /* word operand */
 447   w_mode,
 448   /* double word operand  */
 449   d_mode,
 450   /* double word operand with operand swapped */
 451   d_swap_mode,
 452   /* quad word operand */
 453   q_mode,
 454   /* quad word operand with operand swapped */
 455   q_swap_mode,
 456   /* ten-byte operand */
 457   t_mode,
 458   /* 16-byte XMM or 32-byte YMM operand */
 459   x_mode,
 460   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 461   x_swap_mode,
 462   /* 16-byte XMM operand */
 463   xmm_mode,
 464   /* 16-byte XMM or quad word operand */
 465   xmmq_mode,
 466   /* XMM register or byte memory operand */
 467   xmm_mb_mode,
 468   /* XMM register or word memory operand */
 469   xmm_mw_mode,
 470   /* XMM register or double word memory operand */
 471   xmm_md_mode,
 472   /* XMM register or quad word memory operand */
 473   xmm_mq_mode,
 474   /* 16-byte XMM, word or double word operand  */
 475   xmmdw_mode,
 476   /* 16-byte XMM, double word or quad word operand */
 477   xmmqd_mode,
 478   /* 32-byte YMM or quad word operand */
 479   ymmq_mode,
 480   /* 32-byte YMM or 16-byte word operand */
 481   ymmxmm_mode,
 482   /* d_mode in 32bit, q_mode in 64bit mode.  */
 483   m_mode,
 484   /* pair of v_mode operands */
 485   a_mode,
 486   cond_jump_mode,
 487   loop_jcxz_mode,
 488   /* operand size depends on REX prefixes.  */
 489   dq_mode,
 490   /* registers like dq_mode, memory like w_mode.  */
 491   dqw_mode,
 492   /* 4- or 6-byte pointer operand */
 493   f_mode,
 494   const_1_mode,
 495   /* v_mode for stack-related opcodes.  */
 496   stack_v_mode,
 497   /* non-quad operand size depends on prefixes */
 498   z_mode,
 499   /* 16-byte operand */
 500   o_mode,
 501   /* registers like dq_mode, memory like b_mode.  */
 502   dqb_mode,
 503   /* registers like dq_mode, memory like d_mode.  */
 504   dqd_mode,
 505   /* normal vex mode */
 506   vex_mode,
 507   /* 128bit vex mode */
 508   vex128_mode,
 509   /* 256bit vex mode */
 510   vex256_mode,
 511   /* operand size depends on the VEX.W bit.  */
 512   vex_w_dq_mode,
 513
 514   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 515   vex_vsib_d_w_dq_mode,
 516   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 517   vex_vsib_q_w_dq_mode,
 518
 519   /* scalar, ignore vector length.  */
 520   scalar_mode,
 521   /* like d_mode, ignore vector length.  */
 522   d_scalar_mode,
 523   /* like d_swap_mode, ignore vector length.  */
 524   d_scalar_swap_mode,
 525   /* like q_mode, ignore vector length.  */
 526   q_scalar_mode,
 527   /* like q_swap_mode, ignore vector length.  */
 528   q_scalar_swap_mode,
 529   /* like vex_mode, ignore vector length.  */
 530   vex_scalar_mode,
 531   /* like vex_w_dq_mode, ignore vector length.  */
 532   vex_scalar_w_dq_mode,
 533
 534   es_reg,
 535   cs_reg,
 536   ss_reg,
 537   ds_reg,
 538   fs_reg,
 539   gs_reg,
 540
 541   eAX_reg,
 542   eCX_reg,
 543   eDX_reg,
 544   eBX_reg,
 545   eSP_reg,
 546   eBP_reg,
 547   eSI_reg,
 548   eDI_reg,
 549
 550   al_reg,
 551   cl_reg,
 552   dl_reg,
 553   bl_reg,
 554   ah_reg,
 555   ch_reg,
 556   dh_reg,
 557   bh_reg,
 558
 559   ax_reg,
 560   cx_reg,
 561   dx_reg,
 562   bx_reg,
 563   sp_reg,
 564   bp_reg,
 565   si_reg,
 566   di_reg,
 567
 568   rAX_reg,
 569   rCX_reg,
 570   rDX_reg,
 571   rBX_reg,
 572   rSP_reg,
 573   rBP_reg,
 574   rSI_reg,
 575   rDI_reg,
 576
 577   z_mode_ax_reg,
 578   indir_dx_reg
 579 };
 580
 581 enum
 582 {
 583   FLOATCODE = 1,
 584   USE_REG_TABLE,
 585   USE_MOD_TABLE,
 586   USE_RM_TABLE,
 587   USE_PREFIX_TABLE,
 588   USE_X86_64_TABLE,
 589   USE_3BYTE_TABLE,
 590   USE_XOP_8F_TABLE,
 591   USE_VEX_C4_TABLE,
 592   USE_VEX_C5_TABLE,
 593   USE_VEX_LEN_TABLE,
 594   USE_VEX_W_TABLE
 595 };
 596
 597 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 598
 599 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 600 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 601 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 602 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 603 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 604 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 605 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 606 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 607 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 608 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 609 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 610 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 611
 612 enum
 613 {
 614   REG_80 = 0,
 615   REG_81,
 616   REG_82,
 617   REG_8F,
 618   REG_C0,
 619   REG_C1,
 620   REG_C6,
 621   REG_C7,
 622   REG_D0,
 623   REG_D1,
 624   REG_D2,
 625   REG_D3,
 626   REG_F6,
 627   REG_F7,
 628   REG_FE,
 629   REG_FF,
 630   REG_0F00,
 631   REG_0F01,
 632   REG_0F0D,
 633   REG_0F18,
 634   REG_0F71,
 635   REG_0F72,
 636   REG_0F73,
 637   REG_0FA6,
 638   REG_0FA7,
 639   REG_0FAE,
 640   REG_0FBA,
 641   REG_0FC7,
 642   REG_VEX_0F71,
 643   REG_VEX_0F72,
 644   REG_VEX_0F73,
 645   REG_VEX_0FAE,
 646   REG_VEX_0F38F3,
 647   REG_XOP_LWPCB,
 648   REG_XOP_LWP,
 649   REG_XOP_TBM_01,
 650   REG_XOP_TBM_02
 651 };
 652
 653 enum
 654 {
 655   MOD_8D = 0,
 656   MOD_C6_REG_7,
 657   MOD_C7_REG_7,
 658   MOD_0F01_REG_0,
 659   MOD_0F01_REG_1,
 660   MOD_0F01_REG_2,
 661   MOD_0F01_REG_3,
 662   MOD_0F01_REG_7,
 663   MOD_0F12_PREFIX_0,
 664   MOD_0F13,
 665   MOD_0F16_PREFIX_0,
 666   MOD_0F17,
 667   MOD_0F18_REG_0,
 668   MOD_0F18_REG_1,
 669   MOD_0F18_REG_2,
 670   MOD_0F18_REG_3,
 671   MOD_0F20,
 672   MOD_0F21,
 673   MOD_0F22,
 674   MOD_0F23,
 675   MOD_0F24,
 676   MOD_0F26,
 677   MOD_0F2B_PREFIX_0,
 678   MOD_0F2B_PREFIX_1,
 679   MOD_0F2B_PREFIX_2,
 680   MOD_0F2B_PREFIX_3,
 681   MOD_0F51,
 682   MOD_0F71_REG_2,
 683   MOD_0F71_REG_4,
 684   MOD_0F71_REG_6,
 685   MOD_0F72_REG_2,
 686   MOD_0F72_REG_4,
 687   MOD_0F72_REG_6,
 688   MOD_0F73_REG_2,
 689   MOD_0F73_REG_3,
 690   MOD_0F73_REG_6,
 691   MOD_0F73_REG_7,
 692   MOD_0FAE_REG_0,
 693   MOD_0FAE_REG_1,
 694   MOD_0FAE_REG_2,
 695   MOD_0FAE_REG_3,
 696   MOD_0FAE_REG_4,
 697   MOD_0FAE_REG_5,
 698   MOD_0FAE_REG_6,
 699   MOD_0FAE_REG_7,
 700   MOD_0FB2,
 701   MOD_0FB4,
 702   MOD_0FB5,
 703   MOD_0FC7_REG_6,
 704   MOD_0FC7_REG_7,
 705   MOD_0FD7,
 706   MOD_0FE7_PREFIX_2,
 707   MOD_0FF0_PREFIX_3,
 708   MOD_0F382A_PREFIX_2,
 709   MOD_62_32BIT,
 710   MOD_C4_32BIT,
 711   MOD_C5_32BIT,
 712   MOD_VEX_0F12_PREFIX_0,
 713   MOD_VEX_0F13,
 714   MOD_VEX_0F16_PREFIX_0,
 715   MOD_VEX_0F17,
 716   MOD_VEX_0F2B,
 717   MOD_VEX_0F50,
 718   MOD_VEX_0F71_REG_2,
 719   MOD_VEX_0F71_REG_4,
 720   MOD_VEX_0F71_REG_6,
 721   MOD_VEX_0F72_REG_2,
 722   MOD_VEX_0F72_REG_4,
 723   MOD_VEX_0F72_REG_6,
 724   MOD_VEX_0F73_REG_2,
 725   MOD_VEX_0F73_REG_3,
 726   MOD_VEX_0F73_REG_6,
 727   MOD_VEX_0F73_REG_7,
 728   MOD_VEX_0FAE_REG_2,
 729   MOD_VEX_0FAE_REG_3,
 730   MOD_VEX_0FD7_PREFIX_2,
 731   MOD_VEX_0FE7_PREFIX_2,
 732   MOD_VEX_0FF0_PREFIX_3,
 733   MOD_VEX_0F381A_PREFIX_2,
 734   MOD_VEX_0F382A_PREFIX_2,
 735   MOD_VEX_0F382C_PREFIX_2,
 736   MOD_VEX_0F382D_PREFIX_2,
 737   MOD_VEX_0F382E_PREFIX_2,
 738   MOD_VEX_0F382F_PREFIX_2,
 739   MOD_VEX_0F385A_PREFIX_2,
 740   MOD_VEX_0F388C_PREFIX_2,
 741   MOD_VEX_0F388E_PREFIX_2,
 742 };
 743
 744 enum
 745 {
 746   RM_C6_REG_7 = 0,
 747   RM_C7_REG_7,
 748   RM_0F01_REG_0,
 749   RM_0F01_REG_1,
 750   RM_0F01_REG_2,
 751   RM_0F01_REG_3,
 752   RM_0F01_REG_7,
 753   RM_0FAE_REG_5,
 754   RM_0FAE_REG_6,
 755   RM_0FAE_REG_7
 756 };
 757
 758 enum
 759 {
 760   PREFIX_90 = 0,
 761   PREFIX_0F10,
 762   PREFIX_0F11,
 763   PREFIX_0F12,
 764   PREFIX_0F16,
 765   PREFIX_0F2A,
 766   PREFIX_0F2B,
 767   PREFIX_0F2C,
 768   PREFIX_0F2D,
 769   PREFIX_0F2E,
 770   PREFIX_0F2F,
 771   PREFIX_0F51,
 772   PREFIX_0F52,
 773   PREFIX_0F53,
 774   PREFIX_0F58,
 775   PREFIX_0F59,
 776   PREFIX_0F5A,
 777   PREFIX_0F5B,
 778   PREFIX_0F5C,
 779   PREFIX_0F5D,
 780   PREFIX_0F5E,
 781   PREFIX_0F5F,
 782   PREFIX_0F60,
 783   PREFIX_0F61,
 784   PREFIX_0F62,
 785   PREFIX_0F6C,
 786   PREFIX_0F6D,
 787   PREFIX_0F6F,
 788   PREFIX_0F70,
 789   PREFIX_0F73_REG_3,
 790   PREFIX_0F73_REG_7,
 791   PREFIX_0F78,
 792   PREFIX_0F79,
 793   PREFIX_0F7C,
 794   PREFIX_0F7D,
 795   PREFIX_0F7E,
 796   PREFIX_0F7F,
 797   PREFIX_0FAE_REG_0,
 798   PREFIX_0FAE_REG_1,
 799   PREFIX_0FAE_REG_2,
 800   PREFIX_0FAE_REG_3,
 801   PREFIX_0FB8,
 802   PREFIX_0FBC,
 803   PREFIX_0FBD,
 804   PREFIX_0FC2,
 805   PREFIX_0FC3,
 806   PREFIX_0FC7_REG_6,
 807   PREFIX_0FD0,
 808   PREFIX_0FD6,
 809   PREFIX_0FE6,
 810   PREFIX_0FE7,
 811   PREFIX_0FF0,
 812   PREFIX_0FF7,
 813   PREFIX_0F3810,
 814   PREFIX_0F3814,
 815   PREFIX_0F3815,
 816   PREFIX_0F3817,
 817   PREFIX_0F3820,
 818   PREFIX_0F3821,
 819   PREFIX_0F3822,
 820   PREFIX_0F3823,
 821   PREFIX_0F3824,
 822   PREFIX_0F3825,
 823   PREFIX_0F3828,
 824   PREFIX_0F3829,
 825   PREFIX_0F382A,
 826   PREFIX_0F382B,
 827   PREFIX_0F3830,
 828   PREFIX_0F3831,
 829   PREFIX_0F3832,
 830   PREFIX_0F3833,
 831   PREFIX_0F3834,
 832   PREFIX_0F3835,
 833   PREFIX_0F3837,
 834   PREFIX_0F3838,
 835   PREFIX_0F3839,
 836   PREFIX_0F383A,
 837   PREFIX_0F383B,
 838   PREFIX_0F383C,
 839   PREFIX_0F383D,
 840   PREFIX_0F383E,
 841   PREFIX_0F383F,
 842   PREFIX_0F3840,
 843   PREFIX_0F3841,
 844   PREFIX_0F3880,
 845   PREFIX_0F3881,
 846   PREFIX_0F3882,
 847   PREFIX_0F38DB,
 848   PREFIX_0F38DC,
 849   PREFIX_0F38DD,
 850   PREFIX_0F38DE,
 851   PREFIX_0F38DF,
 852   PREFIX_0F38F0,
 853   PREFIX_0F38F1,
 854   PREFIX_0F38F6,
 855   PREFIX_0F3A08,
 856   PREFIX_0F3A09,
 857   PREFIX_0F3A0A,
 858   PREFIX_0F3A0B,
 859   PREFIX_0F3A0C,
 860   PREFIX_0F3A0D,
 861   PREFIX_0F3A0E,
 862   PREFIX_0F3A14,
 863   PREFIX_0F3A15,
 864   PREFIX_0F3A16,
 865   PREFIX_0F3A17,
 866   PREFIX_0F3A20,
 867   PREFIX_0F3A21,
 868   PREFIX_0F3A22,
 869   PREFIX_0F3A40,
 870   PREFIX_0F3A41,
 871   PREFIX_0F3A42,
 872   PREFIX_0F3A44,
 873   PREFIX_0F3A60,
 874   PREFIX_0F3A61,
 875   PREFIX_0F3A62,
 876   PREFIX_0F3A63,
 877   PREFIX_0F3ADF,
 878   PREFIX_VEX_0F10,
 879   PREFIX_VEX_0F11,
 880   PREFIX_VEX_0F12,
 881   PREFIX_VEX_0F16,
 882   PREFIX_VEX_0F2A,
 883   PREFIX_VEX_0F2C,
 884   PREFIX_VEX_0F2D,
 885   PREFIX_VEX_0F2E,
 886   PREFIX_VEX_0F2F,
 887   PREFIX_VEX_0F51,
 888   PREFIX_VEX_0F52,
 889   PREFIX_VEX_0F53,
 890   PREFIX_VEX_0F58,
 891   PREFIX_VEX_0F59,
 892   PREFIX_VEX_0F5A,
 893   PREFIX_VEX_0F5B,
 894   PREFIX_VEX_0F5C,
 895   PREFIX_VEX_0F5D,
 896   PREFIX_VEX_0F5E,
 897   PREFIX_VEX_0F5F,
 898   PREFIX_VEX_0F60,
 899   PREFIX_VEX_0F61,
 900   PREFIX_VEX_0F62,
 901   PREFIX_VEX_0F63,
 902   PREFIX_VEX_0F64,
 903   PREFIX_VEX_0F65,
 904   PREFIX_VEX_0F66,
 905   PREFIX_VEX_0F67,
 906   PREFIX_VEX_0F68,
 907   PREFIX_VEX_0F69,
 908   PREFIX_VEX_0F6A,
 909   PREFIX_VEX_0F6B,
 910   PREFIX_VEX_0F6C,
 911   PREFIX_VEX_0F6D,
 912   PREFIX_VEX_0F6E,
 913   PREFIX_VEX_0F6F,
 914   PREFIX_VEX_0F70,
 915   PREFIX_VEX_0F71_REG_2,
 916   PREFIX_VEX_0F71_REG_4,
 917   PREFIX_VEX_0F71_REG_6,
 918   PREFIX_VEX_0F72_REG_2,
 919   PREFIX_VEX_0F72_REG_4,
 920   PREFIX_VEX_0F72_REG_6,
 921   PREFIX_VEX_0F73_REG_2,
 922   PREFIX_VEX_0F73_REG_3,
 923   PREFIX_VEX_0F73_REG_6,
 924   PREFIX_VEX_0F73_REG_7,
 925   PREFIX_VEX_0F74,
 926   PREFIX_VEX_0F75,
 927   PREFIX_VEX_0F76,
 928   PREFIX_VEX_0F77,
 929   PREFIX_VEX_0F7C,
 930   PREFIX_VEX_0F7D,
 931   PREFIX_VEX_0F7E,
 932   PREFIX_VEX_0F7F,
 933   PREFIX_VEX_0FC2,
 934   PREFIX_VEX_0FC4,
 935   PREFIX_VEX_0FC5,
 936   PREFIX_VEX_0FD0,
 937   PREFIX_VEX_0FD1,
 938   PREFIX_VEX_0FD2,
 939   PREFIX_VEX_0FD3,
 940   PREFIX_VEX_0FD4,
 941   PREFIX_VEX_0FD5,
 942   PREFIX_VEX_0FD6,
 943   PREFIX_VEX_0FD7,
 944   PREFIX_VEX_0FD8,
 945   PREFIX_VEX_0FD9,
 946   PREFIX_VEX_0FDA,
 947   PREFIX_VEX_0FDB,
 948   PREFIX_VEX_0FDC,
 949   PREFIX_VEX_0FDD,
 950   PREFIX_VEX_0FDE,
 951   PREFIX_VEX_0FDF,
 952   PREFIX_VEX_0FE0,
 953   PREFIX_VEX_0FE1,
 954   PREFIX_VEX_0FE2,
 955   PREFIX_VEX_0FE3,
 956   PREFIX_VEX_0FE4,
 957   PREFIX_VEX_0FE5,
 958   PREFIX_VEX_0FE6,
 959   PREFIX_VEX_0FE7,
 960   PREFIX_VEX_0FE8,
 961   PREFIX_VEX_0FE9,
 962   PREFIX_VEX_0FEA,
 963   PREFIX_VEX_0FEB,
 964   PREFIX_VEX_0FEC,
 965   PREFIX_VEX_0FED,
 966   PREFIX_VEX_0FEE,
 967   PREFIX_VEX_0FEF,
 968   PREFIX_VEX_0FF0,
 969   PREFIX_VEX_0FF1,
 970   PREFIX_VEX_0FF2,
 971   PREFIX_VEX_0FF3,
 972   PREFIX_VEX_0FF4,
 973   PREFIX_VEX_0FF5,
 974   PREFIX_VEX_0FF6,
 975   PREFIX_VEX_0FF7,
 976   PREFIX_VEX_0FF8,
 977   PREFIX_VEX_0FF9,
 978   PREFIX_VEX_0FFA,
 979   PREFIX_VEX_0FFB,
 980   PREFIX_VEX_0FFC,
 981   PREFIX_VEX_0FFD,
 982   PREFIX_VEX_0FFE,
 983   PREFIX_VEX_0F3800,
 984   PREFIX_VEX_0F3801,
 985   PREFIX_VEX_0F3802,
 986   PREFIX_VEX_0F3803,
 987   PREFIX_VEX_0F3804,
 988   PREFIX_VEX_0F3805,
 989   PREFIX_VEX_0F3806,
 990   PREFIX_VEX_0F3807,
 991   PREFIX_VEX_0F3808,
 992   PREFIX_VEX_0F3809,
 993   PREFIX_VEX_0F380A,
 994   PREFIX_VEX_0F380B,
 995   PREFIX_VEX_0F380C,
 996   PREFIX_VEX_0F380D,
 997   PREFIX_VEX_0F380E,
 998   PREFIX_VEX_0F380F,
 999   PREFIX_VEX_0F3813,
1000   PREFIX_VEX_0F3816,
1001   PREFIX_VEX_0F3817,
1002   PREFIX_VEX_0F3818,
1003   PREFIX_VEX_0F3819,
1004   PREFIX_VEX_0F381A,
1005   PREFIX_VEX_0F381C,
1006   PREFIX_VEX_0F381D,
1007   PREFIX_VEX_0F381E,
1008   PREFIX_VEX_0F3820,
1009   PREFIX_VEX_0F3821,
1010   PREFIX_VEX_0F3822,
1011   PREFIX_VEX_0F3823,
1012   PREFIX_VEX_0F3824,
1013   PREFIX_VEX_0F3825,
1014   PREFIX_VEX_0F3828,
1015   PREFIX_VEX_0F3829,
1016   PREFIX_VEX_0F382A,
1017   PREFIX_VEX_0F382B,
1018   PREFIX_VEX_0F382C,
1019   PREFIX_VEX_0F382D,
1020   PREFIX_VEX_0F382E,
1021   PREFIX_VEX_0F382F,
1022   PREFIX_VEX_0F3830,
1023   PREFIX_VEX_0F3831,
1024   PREFIX_VEX_0F3832,
1025   PREFIX_VEX_0F3833,
1026   PREFIX_VEX_0F3834,
1027   PREFIX_VEX_0F3835,
1028   PREFIX_VEX_0F3836,
1029   PREFIX_VEX_0F3837,
1030   PREFIX_VEX_0F3838,
1031   PREFIX_VEX_0F3839,
1032   PREFIX_VEX_0F383A,
1033   PREFIX_VEX_0F383B,
1034   PREFIX_VEX_0F383C,
1035   PREFIX_VEX_0F383D,
1036   PREFIX_VEX_0F383E,
1037   PREFIX_VEX_0F383F,
1038   PREFIX_VEX_0F3840,
1039   PREFIX_VEX_0F3841,
1040   PREFIX_VEX_0F3845,
1041   PREFIX_VEX_0F3846,
1042   PREFIX_VEX_0F3847,
1043   PREFIX_VEX_0F3858,
1044   PREFIX_VEX_0F3859,
1045   PREFIX_VEX_0F385A,
1046   PREFIX_VEX_0F3878,
1047   PREFIX_VEX_0F3879,
1048   PREFIX_VEX_0F388C,
1049   PREFIX_VEX_0F388E,
1050   PREFIX_VEX_0F3890,
1051   PREFIX_VEX_0F3891,
1052   PREFIX_VEX_0F3892,
1053   PREFIX_VEX_0F3893,
1054   PREFIX_VEX_0F3896,
1055   PREFIX_VEX_0F3897,
1056   PREFIX_VEX_0F3898,
1057   PREFIX_VEX_0F3899,
1058   PREFIX_VEX_0F389A,
1059   PREFIX_VEX_0F389B,
1060   PREFIX_VEX_0F389C,
1061   PREFIX_VEX_0F389D,
1062   PREFIX_VEX_0F389E,
1063   PREFIX_VEX_0F389F,
1064   PREFIX_VEX_0F38A6,
1065   PREFIX_VEX_0F38A7,
1066   PREFIX_VEX_0F38A8,
1067   PREFIX_VEX_0F38A9,
1068   PREFIX_VEX_0F38AA,
1069   PREFIX_VEX_0F38AB,
1070   PREFIX_VEX_0F38AC,
1071   PREFIX_VEX_0F38AD,
1072   PREFIX_VEX_0F38AE,
1073   PREFIX_VEX_0F38AF,
1074   PREFIX_VEX_0F38B6,
1075   PREFIX_VEX_0F38B7,
1076   PREFIX_VEX_0F38B8,
1077   PREFIX_VEX_0F38B9,
1078   PREFIX_VEX_0F38BA,
1079   PREFIX_VEX_0F38BB,
1080   PREFIX_VEX_0F38BC,
1081   PREFIX_VEX_0F38BD,
1082   PREFIX_VEX_0F38BE,
1083   PREFIX_VEX_0F38BF,
1084   PREFIX_VEX_0F38DB,
1085   PREFIX_VEX_0F38DC,
1086   PREFIX_VEX_0F38DD,
1087   PREFIX_VEX_0F38DE,
1088   PREFIX_VEX_0F38DF,
1089   PREFIX_VEX_0F38F2,
1090   PREFIX_VEX_0F38F3_REG_1,
1091   PREFIX_VEX_0F38F3_REG_2,
1092   PREFIX_VEX_0F38F3_REG_3,
1093   PREFIX_VEX_0F38F5,
1094   PREFIX_VEX_0F38F6,
1095   PREFIX_VEX_0F38F7,
1096   PREFIX_VEX_0F3A00,
1097   PREFIX_VEX_0F3A01,
1098   PREFIX_VEX_0F3A02,
1099   PREFIX_VEX_0F3A04,
1100   PREFIX_VEX_0F3A05,
1101   PREFIX_VEX_0F3A06,
1102   PREFIX_VEX_0F3A08,
1103   PREFIX_VEX_0F3A09,
1104   PREFIX_VEX_0F3A0A,
1105   PREFIX_VEX_0F3A0B,
1106   PREFIX_VEX_0F3A0C,
1107   PREFIX_VEX_0F3A0D,
1108   PREFIX_VEX_0F3A0E,
1109   PREFIX_VEX_0F3A0F,
1110   PREFIX_VEX_0F3A14,
1111   PREFIX_VEX_0F3A15,
1112   PREFIX_VEX_0F3A16,
1113   PREFIX_VEX_0F3A17,
1114   PREFIX_VEX_0F3A18,
1115   PREFIX_VEX_0F3A19,
1116   PREFIX_VEX_0F3A1D,
1117   PREFIX_VEX_0F3A20,
1118   PREFIX_VEX_0F3A21,
1119   PREFIX_VEX_0F3A22,
1120   PREFIX_VEX_0F3A38,
1121   PREFIX_VEX_0F3A39,
1122   PREFIX_VEX_0F3A40,
1123   PREFIX_VEX_0F3A41,
1124   PREFIX_VEX_0F3A42,
1125   PREFIX_VEX_0F3A44,
1126   PREFIX_VEX_0F3A46,
1127   PREFIX_VEX_0F3A48,
1128   PREFIX_VEX_0F3A49,
1129   PREFIX_VEX_0F3A4A,
1130   PREFIX_VEX_0F3A4B,
1131   PREFIX_VEX_0F3A4C,
1132   PREFIX_VEX_0F3A5C,
1133   PREFIX_VEX_0F3A5D,
1134   PREFIX_VEX_0F3A5E,
1135   PREFIX_VEX_0F3A5F,
1136   PREFIX_VEX_0F3A60,
1137   PREFIX_VEX_0F3A61,
1138   PREFIX_VEX_0F3A62,
1139   PREFIX_VEX_0F3A63,
1140   PREFIX_VEX_0F3A68,
1141   PREFIX_VEX_0F3A69,
1142   PREFIX_VEX_0F3A6A,
1143   PREFIX_VEX_0F3A6B,
1144   PREFIX_VEX_0F3A6C,
1145   PREFIX_VEX_0F3A6D,
1146   PREFIX_VEX_0F3A6E,
1147   PREFIX_VEX_0F3A6F,
1148   PREFIX_VEX_0F3A78,
1149   PREFIX_VEX_0F3A79,
1150   PREFIX_VEX_0F3A7A,
1151   PREFIX_VEX_0F3A7B,
1152   PREFIX_VEX_0F3A7C,
1153   PREFIX_VEX_0F3A7D,
1154   PREFIX_VEX_0F3A7E,
1155   PREFIX_VEX_0F3A7F,
1156   PREFIX_VEX_0F3ADF,
1157   PREFIX_VEX_0F3AF0
1158 };
1159
1160 enum
1161 {
1162   X86_64_06 = 0,
1163   X86_64_07,
1164   X86_64_0D,
1165   X86_64_16,
1166   X86_64_17,
1167   X86_64_1E,
1168   X86_64_1F,
1169   X86_64_27,
1170   X86_64_2F,
1171   X86_64_37,
1172   X86_64_3F,
1173   X86_64_60,
1174   X86_64_61,
1175   X86_64_62,
1176   X86_64_63,
1177   X86_64_6D,
1178   X86_64_6F,
1179   X86_64_9A,
1180   X86_64_C4,
1181   X86_64_C5,
1182   X86_64_CE,
1183   X86_64_D4,
1184   X86_64_D5,
1185   X86_64_EA,
1186   X86_64_0F01_REG_0,
1187   X86_64_0F01_REG_1,
1188   X86_64_0F01_REG_2,
1189   X86_64_0F01_REG_3
1190 };
1191
1192 enum
1193 {
1194   THREE_BYTE_0F38 = 0,
1195   THREE_BYTE_0F3A,
1196   THREE_BYTE_0F7A
1197 };
1198
1199 enum
1200 {
1201   XOP_08 = 0,
1202   XOP_09,
1203   XOP_0A
1204 };
1205
1206 enum
1207 {
1208   VEX_0F = 0,
1209   VEX_0F38,
1210   VEX_0F3A
1211 };
1212
1213 enum
1214 {
1215   VEX_LEN_0F10_P_1 = 0,
1216   VEX_LEN_0F10_P_3,
1217   VEX_LEN_0F11_P_1,
1218   VEX_LEN_0F11_P_3,
1219   VEX_LEN_0F12_P_0_M_0,
1220   VEX_LEN_0F12_P_0_M_1,
1221   VEX_LEN_0F12_P_2,
1222   VEX_LEN_0F13_M_0,
1223   VEX_LEN_0F16_P_0_M_0,
1224   VEX_LEN_0F16_P_0_M_1,
1225   VEX_LEN_0F16_P_2,
1226   VEX_LEN_0F17_M_0,
1227   VEX_LEN_0F2A_P_1,
1228   VEX_LEN_0F2A_P_3,
1229   VEX_LEN_0F2C_P_1,
1230   VEX_LEN_0F2C_P_3,
1231   VEX_LEN_0F2D_P_1,
1232   VEX_LEN_0F2D_P_3,
1233   VEX_LEN_0F2E_P_0,
1234   VEX_LEN_0F2E_P_2,
1235   VEX_LEN_0F2F_P_0,
1236   VEX_LEN_0F2F_P_2,
1237   VEX_LEN_0F51_P_1,
1238   VEX_LEN_0F51_P_3,
1239   VEX_LEN_0F52_P_1,
1240   VEX_LEN_0F53_P_1,
1241   VEX_LEN_0F58_P_1,
1242   VEX_LEN_0F58_P_3,
1243   VEX_LEN_0F59_P_1,
1244   VEX_LEN_0F59_P_3,
1245   VEX_LEN_0F5A_P_1,
1246   VEX_LEN_0F5A_P_3,
1247   VEX_LEN_0F5C_P_1,
1248   VEX_LEN_0F5C_P_3,
1249   VEX_LEN_0F5D_P_1,
1250   VEX_LEN_0F5D_P_3,
1251   VEX_LEN_0F5E_P_1,
1252   VEX_LEN_0F5E_P_3,
1253   VEX_LEN_0F5F_P_1,
1254   VEX_LEN_0F5F_P_3,
1255   VEX_LEN_0F6E_P_2,
1256   VEX_LEN_0F7E_P_1,
1257   VEX_LEN_0F7E_P_2,
1258   VEX_LEN_0FAE_R_2_M_0,
1259   VEX_LEN_0FAE_R_3_M_0,
1260   VEX_LEN_0FC2_P_1,
1261   VEX_LEN_0FC2_P_3,
1262   VEX_LEN_0FC4_P_2,
1263   VEX_LEN_0FC5_P_2,
1264   VEX_LEN_0FD6_P_2,
1265   VEX_LEN_0FF7_P_2,
1266   VEX_LEN_0F3816_P_2,
1267   VEX_LEN_0F3819_P_2,
1268   VEX_LEN_0F381A_P_2_M_0,
1269   VEX_LEN_0F3836_P_2,
1270   VEX_LEN_0F3841_P_2,
1271   VEX_LEN_0F385A_P_2_M_0,
1272   VEX_LEN_0F38DB_P_2,
1273   VEX_LEN_0F38DC_P_2,
1274   VEX_LEN_0F38DD_P_2,
1275   VEX_LEN_0F38DE_P_2,
1276   VEX_LEN_0F38DF_P_2,
1277   VEX_LEN_0F38F2_P_0,
1278   VEX_LEN_0F38F3_R_1_P_0,
1279   VEX_LEN_0F38F3_R_2_P_0,
1280   VEX_LEN_0F38F3_R_3_P_0,
1281   VEX_LEN_0F38F5_P_0,
1282   VEX_LEN_0F38F5_P_1,
1283   VEX_LEN_0F38F5_P_3,
1284   VEX_LEN_0F38F6_P_3,
1285   VEX_LEN_0F38F7_P_0,
1286   VEX_LEN_0F38F7_P_1,
1287   VEX_LEN_0F38F7_P_2,
1288   VEX_LEN_0F38F7_P_3,
1289   VEX_LEN_0F3A00_P_2,
1290   VEX_LEN_0F3A01_P_2,
1291   VEX_LEN_0F3A06_P_2,
1292   VEX_LEN_0F3A0A_P_2,
1293   VEX_LEN_0F3A0B_P_2,
1294   VEX_LEN_0F3A14_P_2,
1295   VEX_LEN_0F3A15_P_2,
1296   VEX_LEN_0F3A16_P_2,
1297   VEX_LEN_0F3A17_P_2,
1298   VEX_LEN_0F3A18_P_2,
1299   VEX_LEN_0F3A19_P_2,
1300   VEX_LEN_0F3A20_P_2,
1301   VEX_LEN_0F3A21_P_2,
1302   VEX_LEN_0F3A22_P_2,
1303   VEX_LEN_0F3A38_P_2,
1304   VEX_LEN_0F3A39_P_2,
1305   VEX_LEN_0F3A41_P_2,
1306   VEX_LEN_0F3A44_P_2,
1307   VEX_LEN_0F3A46_P_2,
1308   VEX_LEN_0F3A60_P_2,
1309   VEX_LEN_0F3A61_P_2,
1310   VEX_LEN_0F3A62_P_2,
1311   VEX_LEN_0F3A63_P_2,
1312   VEX_LEN_0F3A6A_P_2,
1313   VEX_LEN_0F3A6B_P_2,
1314   VEX_LEN_0F3A6E_P_2,
1315   VEX_LEN_0F3A6F_P_2,
1316   VEX_LEN_0F3A7A_P_2,
1317   VEX_LEN_0F3A7B_P_2,
1318   VEX_LEN_0F3A7E_P_2,
1319   VEX_LEN_0F3A7F_P_2,
1320   VEX_LEN_0F3ADF_P_2,
1321   VEX_LEN_0F3AF0_P_3,
1322   VEX_LEN_0FXOP_08_CC,
1323   VEX_LEN_0FXOP_08_CD,
1324   VEX_LEN_0FXOP_08_CE,
1325   VEX_LEN_0FXOP_08_CF,
1326   VEX_LEN_0FXOP_08_EC,
1327   VEX_LEN_0FXOP_08_ED,
1328   VEX_LEN_0FXOP_08_EE,
1329   VEX_LEN_0FXOP_08_EF,
1330   VEX_LEN_0FXOP_09_80,
1331   VEX_LEN_0FXOP_09_81
1332 };
1333
1334 enum
1335 {
1336   VEX_W_0F10_P_0 = 0,
1337   VEX_W_0F10_P_1,
1338   VEX_W_0F10_P_2,
1339   VEX_W_0F10_P_3,
1340   VEX_W_0F11_P_0,
1341   VEX_W_0F11_P_1,
1342   VEX_W_0F11_P_2,
1343   VEX_W_0F11_P_3,
1344   VEX_W_0F12_P_0_M_0,
1345   VEX_W_0F12_P_0_M_1,
1346   VEX_W_0F12_P_1,
1347   VEX_W_0F12_P_2,
1348   VEX_W_0F12_P_3,
1349   VEX_W_0F13_M_0,
1350   VEX_W_0F14,
1351   VEX_W_0F15,
1352   VEX_W_0F16_P_0_M_0,
1353   VEX_W_0F16_P_0_M_1,
1354   VEX_W_0F16_P_1,
1355   VEX_W_0F16_P_2,
1356   VEX_W_0F17_M_0,
1357   VEX_W_0F28,
1358   VEX_W_0F29,
1359   VEX_W_0F2B_M_0,
1360   VEX_W_0F2E_P_0,
1361   VEX_W_0F2E_P_2,
1362   VEX_W_0F2F_P_0,
1363   VEX_W_0F2F_P_2,
1364   VEX_W_0F50_M_0,
1365   VEX_W_0F51_P_0,
1366   VEX_W_0F51_P_1,
1367   VEX_W_0F51_P_2,
1368   VEX_W_0F51_P_3,
1369   VEX_W_0F52_P_0,
1370   VEX_W_0F52_P_1,
1371   VEX_W_0F53_P_0,
1372   VEX_W_0F53_P_1,
1373   VEX_W_0F58_P_0,
1374   VEX_W_0F58_P_1,
1375   VEX_W_0F58_P_2,
1376   VEX_W_0F58_P_3,
1377   VEX_W_0F59_P_0,
1378   VEX_W_0F59_P_1,
1379   VEX_W_0F59_P_2,
1380   VEX_W_0F59_P_3,
1381   VEX_W_0F5A_P_0,
1382   VEX_W_0F5A_P_1,
1383   VEX_W_0F5A_P_3,
1384   VEX_W_0F5B_P_0,
1385   VEX_W_0F5B_P_1,
1386   VEX_W_0F5B_P_2,
1387   VEX_W_0F5C_P_0,
1388   VEX_W_0F5C_P_1,
1389   VEX_W_0F5C_P_2,
1390   VEX_W_0F5C_P_3,
1391   VEX_W_0F5D_P_0,
1392   VEX_W_0F5D_P_1,
1393   VEX_W_0F5D_P_2,
1394   VEX_W_0F5D_P_3,
1395   VEX_W_0F5E_P_0,
1396   VEX_W_0F5E_P_1,
1397   VEX_W_0F5E_P_2,
1398   VEX_W_0F5E_P_3,
1399   VEX_W_0F5F_P_0,
1400   VEX_W_0F5F_P_1,
1401   VEX_W_0F5F_P_2,
1402   VEX_W_0F5F_P_3,
1403   VEX_W_0F60_P_2,
1404   VEX_W_0F61_P_2,
1405   VEX_W_0F62_P_2,
1406   VEX_W_0F63_P_2,
1407   VEX_W_0F64_P_2,
1408   VEX_W_0F65_P_2,
1409   VEX_W_0F66_P_2,
1410   VEX_W_0F67_P_2,
1411   VEX_W_0F68_P_2,
1412   VEX_W_0F69_P_2,
1413   VEX_W_0F6A_P_2,
1414   VEX_W_0F6B_P_2,
1415   VEX_W_0F6C_P_2,
1416   VEX_W_0F6D_P_2,
1417   VEX_W_0F6F_P_1,
1418   VEX_W_0F6F_P_2,
1419   VEX_W_0F70_P_1,
1420   VEX_W_0F70_P_2,
1421   VEX_W_0F70_P_3,
1422   VEX_W_0F71_R_2_P_2,
1423   VEX_W_0F71_R_4_P_2,
1424   VEX_W_0F71_R_6_P_2,
1425   VEX_W_0F72_R_2_P_2,
1426   VEX_W_0F72_R_4_P_2,
1427   VEX_W_0F72_R_6_P_2,
1428   VEX_W_0F73_R_2_P_2,
1429   VEX_W_0F73_R_3_P_2,
1430   VEX_W_0F73_R_6_P_2,
1431   VEX_W_0F73_R_7_P_2,
1432   VEX_W_0F74_P_2,
1433   VEX_W_0F75_P_2,
1434   VEX_W_0F76_P_2,
1435   VEX_W_0F77_P_0,
1436   VEX_W_0F7C_P_2,
1437   VEX_W_0F7C_P_3,
1438   VEX_W_0F7D_P_2,
1439   VEX_W_0F7D_P_3,
1440   VEX_W_0F7E_P_1,
1441   VEX_W_0F7F_P_1,
1442   VEX_W_0F7F_P_2,
1443   VEX_W_0FAE_R_2_M_0,
1444   VEX_W_0FAE_R_3_M_0,
1445   VEX_W_0FC2_P_0,
1446   VEX_W_0FC2_P_1,
1447   VEX_W_0FC2_P_2,
1448   VEX_W_0FC2_P_3,
1449   VEX_W_0FC4_P_2,
1450   VEX_W_0FC5_P_2,
1451   VEX_W_0FD0_P_2,
1452   VEX_W_0FD0_P_3,
1453   VEX_W_0FD1_P_2,
1454   VEX_W_0FD2_P_2,
1455   VEX_W_0FD3_P_2,
1456   VEX_W_0FD4_P_2,
1457   VEX_W_0FD5_P_2,
1458   VEX_W_0FD6_P_2,
1459   VEX_W_0FD7_P_2_M_1,
1460   VEX_W_0FD8_P_2,
1461   VEX_W_0FD9_P_2,
1462   VEX_W_0FDA_P_2,
1463   VEX_W_0FDB_P_2,
1464   VEX_W_0FDC_P_2,
1465   VEX_W_0FDD_P_2,
1466   VEX_W_0FDE_P_2,
1467   VEX_W_0FDF_P_2,
1468   VEX_W_0FE0_P_2,
1469   VEX_W_0FE1_P_2,
1470   VEX_W_0FE2_P_2,
1471   VEX_W_0FE3_P_2,
1472   VEX_W_0FE4_P_2,
1473   VEX_W_0FE5_P_2,
1474   VEX_W_0FE6_P_1,
1475   VEX_W_0FE6_P_2,
1476   VEX_W_0FE6_P_3,
1477   VEX_W_0FE7_P_2_M_0,
1478   VEX_W_0FE8_P_2,
1479   VEX_W_0FE9_P_2,
1480   VEX_W_0FEA_P_2,
1481   VEX_W_0FEB_P_2,
1482   VEX_W_0FEC_P_2,
1483   VEX_W_0FED_P_2,
1484   VEX_W_0FEE_P_2,
1485   VEX_W_0FEF_P_2,
1486   VEX_W_0FF0_P_3_M_0,
1487   VEX_W_0FF1_P_2,
1488   VEX_W_0FF2_P_2,
1489   VEX_W_0FF3_P_2,
1490   VEX_W_0FF4_P_2,
1491   VEX_W_0FF5_P_2,
1492   VEX_W_0FF6_P_2,
1493   VEX_W_0FF7_P_2,
1494   VEX_W_0FF8_P_2,
1495   VEX_W_0FF9_P_2,
1496   VEX_W_0FFA_P_2,
1497   VEX_W_0FFB_P_2,
1498   VEX_W_0FFC_P_2,
1499   VEX_W_0FFD_P_2,
1500   VEX_W_0FFE_P_2,
1501   VEX_W_0F3800_P_2,
1502   VEX_W_0F3801_P_2,
1503   VEX_W_0F3802_P_2,
1504   VEX_W_0F3803_P_2,
1505   VEX_W_0F3804_P_2,
1506   VEX_W_0F3805_P_2,
1507   VEX_W_0F3806_P_2,
1508   VEX_W_0F3807_P_2,
1509   VEX_W_0F3808_P_2,
1510   VEX_W_0F3809_P_2,
1511   VEX_W_0F380A_P_2,
1512   VEX_W_0F380B_P_2,
1513   VEX_W_0F380C_P_2,
1514   VEX_W_0F380D_P_2,
1515   VEX_W_0F380E_P_2,
1516   VEX_W_0F380F_P_2,
1517   VEX_W_0F3816_P_2,
1518   VEX_W_0F3817_P_2,
1519   VEX_W_0F3818_P_2,
1520   VEX_W_0F3819_P_2,
1521   VEX_W_0F381A_P_2_M_0,
1522   VEX_W_0F381C_P_2,
1523   VEX_W_0F381D_P_2,
1524   VEX_W_0F381E_P_2,
1525   VEX_W_0F3820_P_2,
1526   VEX_W_0F3821_P_2,
1527   VEX_W_0F3822_P_2,
1528   VEX_W_0F3823_P_2,
1529   VEX_W_0F3824_P_2,
1530   VEX_W_0F3825_P_2,
1531   VEX_W_0F3828_P_2,
1532   VEX_W_0F3829_P_2,
1533   VEX_W_0F382A_P_2_M_0,
1534   VEX_W_0F382B_P_2,
1535   VEX_W_0F382C_P_2_M_0,
1536   VEX_W_0F382D_P_2_M_0,
1537   VEX_W_0F382E_P_2_M_0,
1538   VEX_W_0F382F_P_2_M_0,
1539   VEX_W_0F3830_P_2,
1540   VEX_W_0F3831_P_2,
1541   VEX_W_0F3832_P_2,
1542   VEX_W_0F3833_P_2,
1543   VEX_W_0F3834_P_2,
1544   VEX_W_0F3835_P_2,
1545   VEX_W_0F3836_P_2,
1546   VEX_W_0F3837_P_2,
1547   VEX_W_0F3838_P_2,
1548   VEX_W_0F3839_P_2,
1549   VEX_W_0F383A_P_2,
1550   VEX_W_0F383B_P_2,
1551   VEX_W_0F383C_P_2,
1552   VEX_W_0F383D_P_2,
1553   VEX_W_0F383E_P_2,
1554   VEX_W_0F383F_P_2,
1555   VEX_W_0F3840_P_2,
1556   VEX_W_0F3841_P_2,
1557   VEX_W_0F3846_P_2,
1558   VEX_W_0F3858_P_2,
1559   VEX_W_0F3859_P_2,
1560   VEX_W_0F385A_P_2_M_0,
1561   VEX_W_0F3878_P_2,
1562   VEX_W_0F3879_P_2,
1563   VEX_W_0F38DB_P_2,
1564   VEX_W_0F38DC_P_2,
1565   VEX_W_0F38DD_P_2,
1566   VEX_W_0F38DE_P_2,
1567   VEX_W_0F38DF_P_2,
1568   VEX_W_0F3A00_P_2,
1569   VEX_W_0F3A01_P_2,
1570   VEX_W_0F3A02_P_2,
1571   VEX_W_0F3A04_P_2,
1572   VEX_W_0F3A05_P_2,
1573   VEX_W_0F3A06_P_2,
1574   VEX_W_0F3A08_P_2,
1575   VEX_W_0F3A09_P_2,
1576   VEX_W_0F3A0A_P_2,
1577   VEX_W_0F3A0B_P_2,
1578   VEX_W_0F3A0C_P_2,
1579   VEX_W_0F3A0D_P_2,
1580   VEX_W_0F3A0E_P_2,
1581   VEX_W_0F3A0F_P_2,
1582   VEX_W_0F3A14_P_2,
1583   VEX_W_0F3A15_P_2,
1584   VEX_W_0F3A18_P_2,
1585   VEX_W_0F3A19_P_2,
1586   VEX_W_0F3A20_P_2,
1587   VEX_W_0F3A21_P_2,
1588   VEX_W_0F3A38_P_2,
1589   VEX_W_0F3A39_P_2,
1590   VEX_W_0F3A40_P_2,
1591   VEX_W_0F3A41_P_2,
1592   VEX_W_0F3A42_P_2,
1593   VEX_W_0F3A44_P_2,
1594   VEX_W_0F3A46_P_2,
1595   VEX_W_0F3A48_P_2,
1596   VEX_W_0F3A49_P_2,
1597   VEX_W_0F3A4A_P_2,
1598   VEX_W_0F3A4B_P_2,
1599   VEX_W_0F3A4C_P_2,
1600   VEX_W_0F3A60_P_2,
1601   VEX_W_0F3A61_P_2,
1602   VEX_W_0F3A62_P_2,
1603   VEX_W_0F3A63_P_2,
1604   VEX_W_0F3ADF_P_2
1605 };
1606
1607 typedef void (*op_rtn) (int bytemode, int sizeflag);
1608
1609 struct dis386 {
1610   const char *name;
1611   struct
1612     {
1613       op_rtn rtn;
1614       int bytemode;
1615     } op[MAX_OPERANDS];
1616 };
1617
1618 /* Upper case letters in the instruction names here are macros.
1619    'A' => print 'b' if no register operands or suffix_always is true
1620    'B' => print 'b' if suffix_always is true
1621    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1622           size prefix
1623    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1624           suffix_always is true
1625    'E' => print 'e' if 32-bit form of jcxz
1626    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1627    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1628    'H' => print ",pt" or ",pn" branch hint
1629    'I' => honor following macro letter even in Intel mode (implemented only
1630           for some of the macro letters)
1631    'J' => print 'l'
1632    'K' => print 'd' or 'q' if rex prefix is present.
1633    'L' => print 'l' if suffix_always is true
1634    'M' => print 'r' if intel_mnemonic is false.
1635    'N' => print 'n' if instruction has no wait "prefix"
1636    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1637    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1638           or suffix_always is true.  print 'q' if rex prefix is present.
1639    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1640           is true
1641    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1642    'S' => print 'w', 'l' or 'q' if suffix_always is true
1643    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1644    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1645    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1646    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1647    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1648    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1649           suffix_always is true.
1650    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1651    '!' => change condition from true to false or from false to true.
1652    '%' => add 1 upper case letter to the macro.
1653
1654    2 upper case letter macros:
1655    "XY" => print 'x' or 'y' if no register operands or suffix_always
1656            is true.
1657    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1658    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1659            or suffix_always is true
1660    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1661    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1662    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1663    "LW" => print 'd', 'q' depending on the VEX.W bit
1664
1665    Many of the above letters print nothing in Intel mode.  See "putop"
1666    for the details.
1667
1668    Braces '{' and '}', and vertical bars '|', indicate alternative
1669    mnemonic strings for AT&T and Intel.  */
1670
1671 static const struct dis386 dis386[] = {
1672   /* 00 */
1673   { "addB",             { Ebh1, Gb } },
1674   { "addS",             { Evh1, Gv } },
1675   { "addB",             { Gb, EbS } },
1676   { "addS",             { Gv, EvS } },
1677   { "addB",             { AL, Ib } },
1678   { "addS",             { eAX, Iv } },
1679   { X86_64_TABLE (X86_64_06) },
1680   { X86_64_TABLE (X86_64_07) },
1681   /* 08 */
1682   { "orB",              { Ebh1, Gb } },
1683   { "orS",              { Evh1, Gv } },
1684   { "orB",              { Gb, EbS } },
1685   { "orS",              { Gv, EvS } },
1686   { "orB",              { AL, Ib } },
1687   { "orS",              { eAX, Iv } },
1688   { X86_64_TABLE (X86_64_0D) },
1689   { Bad_Opcode },       /* 0x0f extended opcode escape */
1690   /* 10 */
1691   { "adcB",             { Ebh1, Gb } },
1692   { "adcS",             { Evh1, Gv } },
1693   { "adcB",             { Gb, EbS } },
1694   { "adcS",             { Gv, EvS } },
1695   { "adcB",             { AL, Ib } },
1696   { "adcS",             { eAX, Iv } },
1697   { X86_64_TABLE (X86_64_16) },
1698   { X86_64_TABLE (X86_64_17) },
1699   /* 18 */
1700   { "sbbB",             { Ebh1, Gb } },
1701   { "sbbS",             { Evh1, Gv } },
1702   { "sbbB",             { Gb, EbS } },
1703   { "sbbS",             { Gv, EvS } },
1704   { "sbbB",             { AL, Ib } },
1705   { "sbbS",             { eAX, Iv } },
1706   { X86_64_TABLE (X86_64_1E) },
1707   { X86_64_TABLE (X86_64_1F) },
1708   /* 20 */
1709   { "andB",             { Ebh1, Gb } },
1710   { "andS",             { Evh1, Gv } },
1711   { "andB",             { Gb, EbS } },
1712   { "andS",             { Gv, EvS } },
1713   { "andB",             { AL, Ib } },
1714   { "andS",             { eAX, Iv } },
1715   { Bad_Opcode },       /* SEG ES prefix */
1716   { X86_64_TABLE (X86_64_27) },
1717   /* 28 */
1718   { "subB",             { Ebh1, Gb } },
1719   { "subS",             { Evh1, Gv } },
1720   { "subB",             { Gb, EbS } },
1721   { "subS",             { Gv, EvS } },
1722   { "subB",             { AL, Ib } },
1723   { "subS",             { eAX, Iv } },
1724   { Bad_Opcode },       /* SEG CS prefix */
1725   { X86_64_TABLE (X86_64_2F) },
1726   /* 30 */
1727   { "xorB",             { Ebh1, Gb } },
1728   { "xorS",             { Evh1, Gv } },
1729   { "xorB",             { Gb, EbS } },
1730   { "xorS",             { Gv, EvS } },
1731   { "xorB",             { AL, Ib } },
1732   { "xorS",             { eAX, Iv } },
1733   { Bad_Opcode },       /* SEG SS prefix */
1734   { X86_64_TABLE (X86_64_37) },
1735   /* 38 */
1736   { "cmpB",             { Eb, Gb } },
1737   { "cmpS",             { Ev, Gv } },
1738   { "cmpB",             { Gb, EbS } },
1739   { "cmpS",             { Gv, EvS } },
1740   { "cmpB",             { AL, Ib } },
1741   { "cmpS",             { eAX, Iv } },
1742   { Bad_Opcode },       /* SEG DS prefix */
1743   { X86_64_TABLE (X86_64_3F) },
1744   /* 40 */
1745   { "inc{S|}",          { RMeAX } },
1746   { "inc{S|}",          { RMeCX } },
1747   { "inc{S|}",          { RMeDX } },
1748   { "inc{S|}",          { RMeBX } },
1749   { "inc{S|}",          { RMeSP } },
1750   { "inc{S|}",          { RMeBP } },
1751   { "inc{S|}",          { RMeSI } },
1752   { "inc{S|}",          { RMeDI } },
1753   /* 48 */
1754   { "dec{S|}",          { RMeAX } },
1755   { "dec{S|}",          { RMeCX } },
1756   { "dec{S|}",          { RMeDX } },
1757   { "dec{S|}",          { RMeBX } },
1758   { "dec{S|}",          { RMeSP } },
1759   { "dec{S|}",          { RMeBP } },
1760   { "dec{S|}",          { RMeSI } },
1761   { "dec{S|}",          { RMeDI } },
1762   /* 50 */
1763   { "pushV",            { RMrAX } },
1764   { "pushV",            { RMrCX } },
1765   { "pushV",            { RMrDX } },
1766   { "pushV",            { RMrBX } },
1767   { "pushV",            { RMrSP } },
1768   { "pushV",            { RMrBP } },
1769   { "pushV",            { RMrSI } },
1770   { "pushV",            { RMrDI } },
1771   /* 58 */
1772   { "popV",             { RMrAX } },
1773   { "popV",             { RMrCX } },
1774   { "popV",             { RMrDX } },
1775   { "popV",             { RMrBX } },
1776   { "popV",             { RMrSP } },
1777   { "popV",             { RMrBP } },
1778   { "popV",             { RMrSI } },
1779   { "popV",             { RMrDI } },
1780   /* 60 */
1781   { X86_64_TABLE (X86_64_60) },
1782   { X86_64_TABLE (X86_64_61) },
1783   { X86_64_TABLE (X86_64_62) },
1784   { X86_64_TABLE (X86_64_63) },
1785   { Bad_Opcode },       /* seg fs */
1786   { Bad_Opcode },       /* seg gs */
1787   { Bad_Opcode },       /* op size prefix */
1788   { Bad_Opcode },       /* adr size prefix */
1789   /* 68 */
1790   { "pushT",            { sIv } },
1791   { "imulS",            { Gv, Ev, Iv } },
1792   { "pushT",            { sIbT } },
1793   { "imulS",            { Gv, Ev, sIb } },
1794   { "ins{b|}",          { Ybr, indirDX } },
1795   { X86_64_TABLE (X86_64_6D) },
1796   { "outs{b|}",         { indirDXr, Xb } },
1797   { X86_64_TABLE (X86_64_6F) },
1798   /* 70 */
1799   { "joH",              { Jb, XX, cond_jump_flag } },
1800   { "jnoH",             { Jb, XX, cond_jump_flag } },
1801   { "jbH",              { Jb, XX, cond_jump_flag } },
1802   { "jaeH",             { Jb, XX, cond_jump_flag } },
1803   { "jeH",              { Jb, XX, cond_jump_flag } },
1804   { "jneH",             { Jb, XX, cond_jump_flag } },
1805   { "jbeH",             { Jb, XX, cond_jump_flag } },
1806   { "jaH",              { Jb, XX, cond_jump_flag } },
1807   /* 78 */
1808   { "jsH",              { Jb, XX, cond_jump_flag } },
1809   { "jnsH",             { Jb, XX, cond_jump_flag } },
1810   { "jpH",              { Jb, XX, cond_jump_flag } },
1811   { "jnpH",             { Jb, XX, cond_jump_flag } },
1812   { "jlH",              { Jb, XX, cond_jump_flag } },
1813   { "jgeH",             { Jb, XX, cond_jump_flag } },
1814   { "jleH",             { Jb, XX, cond_jump_flag } },
1815   { "jgH",              { Jb, XX, cond_jump_flag } },
1816   /* 80 */
1817   { REG_TABLE (REG_80) },
1818   { REG_TABLE (REG_81) },
1819   { Bad_Opcode },
1820   { REG_TABLE (REG_82) },
1821   { "testB",            { Eb, Gb } },
1822   { "testS",            { Ev, Gv } },
1823   { "xchgB",            { Ebh2, Gb } },
1824   { "xchgS",            { Evh2, Gv } },
1825   /* 88 */
1826   { "movB",             { Ebh3, Gb } },
1827   { "movS",             { Evh3, Gv } },
1828   { "movB",             { Gb, EbS } },
1829   { "movS",             { Gv, EvS } },
1830   { "movD",             { Sv, Sw } },
1831   { MOD_TABLE (MOD_8D) },
1832   { "movD",             { Sw, Sv } },
1833   { REG_TABLE (REG_8F) },
1834   /* 90 */
1835   { PREFIX_TABLE (PREFIX_90) },
1836   { "xchgS",            { RMeCX, eAX } },
1837   { "xchgS",            { RMeDX, eAX } },
1838   { "xchgS",            { RMeBX, eAX } },
1839   { "xchgS",            { RMeSP, eAX } },
1840   { "xchgS",            { RMeBP, eAX } },
1841   { "xchgS",            { RMeSI, eAX } },
1842   { "xchgS",            { RMeDI, eAX } },
1843   /* 98 */
1844   { "cW{t|}R",          { XX } },
1845   { "cR{t|}O",          { XX } },
1846   { X86_64_TABLE (X86_64_9A) },
1847   { Bad_Opcode },       /* fwait */
1848   { "pushfT",           { XX } },
1849   { "popfT",            { XX } },
1850   { "sahf",             { XX } },
1851   { "lahf",             { XX } },
1852   /* a0 */
1853   { "mov%LB",           { AL, Ob } },
1854   { "mov%LS",           { eAX, Ov } },
1855   { "mov%LB",           { Ob, AL } },
1856   { "mov%LS",           { Ov, eAX } },
1857   { "movs{b|}",         { Ybr, Xb } },
1858   { "movs{R|}",         { Yvr, Xv } },
1859   { "cmps{b|}",         { Xb, Yb } },
1860   { "cmps{R|}",         { Xv, Yv } },
1861   /* a8 */
1862   { "testB",            { AL, Ib } },
1863   { "testS",            { eAX, Iv } },
1864   { "stosB",            { Ybr, AL } },
1865   { "stosS",            { Yvr, eAX } },
1866   { "lodsB",            { ALr, Xb } },
1867   { "lodsS",            { eAXr, Xv } },
1868   { "scasB",            { AL, Yb } },
1869   { "scasS",            { eAX, Yv } },
1870   /* b0 */
1871   { "movB",             { RMAL, Ib } },
1872   { "movB",             { RMCL, Ib } },
1873   { "movB",             { RMDL, Ib } },
1874   { "movB",             { RMBL, Ib } },
1875   { "movB",             { RMAH, Ib } },
1876   { "movB",             { RMCH, Ib } },
1877   { "movB",             { RMDH, Ib } },
1878   { "movB",             { RMBH, Ib } },
1879   /* b8 */
1880   { "mov%LV",           { RMeAX, Iv64 } },
1881   { "mov%LV",           { RMeCX, Iv64 } },
1882   { "mov%LV",           { RMeDX, Iv64 } },
1883   { "mov%LV",           { RMeBX, Iv64 } },
1884   { "mov%LV",           { RMeSP, Iv64 } },
1885   { "mov%LV",           { RMeBP, Iv64 } },
1886   { "mov%LV",           { RMeSI, Iv64 } },
1887   { "mov%LV",           { RMeDI, Iv64 } },
1888   /* c0 */
1889   { REG_TABLE (REG_C0) },
1890   { REG_TABLE (REG_C1) },
1891   { "retT",             { Iw } },
1892   { "retT",             { XX } },
1893   { X86_64_TABLE (X86_64_C4) },
1894   { X86_64_TABLE (X86_64_C5) },
1895   { REG_TABLE (REG_C6) },
1896   { REG_TABLE (REG_C7) },
1897   /* c8 */
1898   { "enterT",           { Iw, Ib } },
1899   { "leaveT",           { XX } },
1900   { "Jret{|f}P",        { Iw } },
1901   { "Jret{|f}P",        { XX } },
1902   { "int3",             { XX } },
1903   { "int",              { Ib } },
1904   { X86_64_TABLE (X86_64_CE) },
1905   { "iretP",            { XX } },
1906   /* d0 */
1907   { REG_TABLE (REG_D0) },
1908   { REG_TABLE (REG_D1) },
1909   { REG_TABLE (REG_D2) },
1910   { REG_TABLE (REG_D3) },
1911   { X86_64_TABLE (X86_64_D4) },
1912   { X86_64_TABLE (X86_64_D5) },
1913   { Bad_Opcode },
1914   { "xlat",             { DSBX } },
1915   /* d8 */
1916   { FLOAT },
1917   { FLOAT },
1918   { FLOAT },
1919   { FLOAT },
1920   { FLOAT },
1921   { FLOAT },
1922   { FLOAT },
1923   { FLOAT },
1924   /* e0 */
1925   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1926   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1927   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1928   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1929   { "inB",              { AL, Ib } },
1930   { "inG",              { zAX, Ib } },
1931   { "outB",             { Ib, AL } },
1932   { "outG",             { Ib, zAX } },
1933   /* e8 */
1934   { "callT",            { Jv } },
1935   { "jmpT",             { Jv } },
1936   { X86_64_TABLE (X86_64_EA) },
1937   { "jmp",              { Jb } },
1938   { "inB",              { AL, indirDX } },
1939   { "inG",              { zAX, indirDX } },
1940   { "outB",             { indirDX, AL } },
1941   { "outG",             { indirDX, zAX } },
1942   /* f0 */
1943   { Bad_Opcode },       /* lock prefix */
1944   { "icebp",            { XX } },
1945   { Bad_Opcode },       /* repne */
1946   { Bad_Opcode },       /* repz */
1947   { "hlt",              { XX } },
1948   { "cmc",              { XX } },
1949   { REG_TABLE (REG_F6) },
1950   { REG_TABLE (REG_F7) },
1951   /* f8 */
1952   { "clc",              { XX } },
1953   { "stc",              { XX } },
1954   { "cli",              { XX } },
1955   { "sti",              { XX } },
1956   { "cld",              { XX } },
1957   { "std",              { XX } },
1958   { REG_TABLE (REG_FE) },
1959   { REG_TABLE (REG_FF) },
1960 };
1961
1962 static const struct dis386 dis386_twobyte[] = {
1963   /* 00 */
1964   { REG_TABLE (REG_0F00 ) },
1965   { REG_TABLE (REG_0F01 ) },
1966   { "larS",             { Gv, Ew } },
1967   { "lslS",             { Gv, Ew } },
1968   { Bad_Opcode },
1969   { "syscall",          { XX } },
1970   { "clts",             { XX } },
1971   { "sysretP",          { XX } },
1972   /* 08 */
1973   { "invd",             { XX } },
1974   { "wbinvd",           { XX } },
1975   { Bad_Opcode },
1976   { "ud2",              { XX } },
1977   { Bad_Opcode },
1978   { REG_TABLE (REG_0F0D) },
1979   { "femms",            { XX } },
1980   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1981   /* 10 */
1982   { PREFIX_TABLE (PREFIX_0F10) },
1983   { PREFIX_TABLE (PREFIX_0F11) },
1984   { PREFIX_TABLE (PREFIX_0F12) },
1985   { MOD_TABLE (MOD_0F13) },
1986   { "unpcklpX",         { XM, EXx } },
1987   { "unpckhpX",         { XM, EXx } },
1988   { PREFIX_TABLE (PREFIX_0F16) },
1989   { MOD_TABLE (MOD_0F17) },
1990   /* 18 */
1991   { REG_TABLE (REG_0F18) },
1992   { "nopQ",             { Ev } },
1993   { "nopQ",             { Ev } },
1994   { "nopQ",             { Ev } },
1995   { "nopQ",             { Ev } },
1996   { "nopQ",             { Ev } },
1997   { "nopQ",             { Ev } },
1998   { "nopQ",             { Ev } },
1999   /* 20 */
2000   { MOD_TABLE (MOD_0F20) },
2001   { MOD_TABLE (MOD_0F21) },
2002   { MOD_TABLE (MOD_0F22) },
2003   { MOD_TABLE (MOD_0F23) },
2004   { MOD_TABLE (MOD_0F24) },
2005   { Bad_Opcode },
2006   { MOD_TABLE (MOD_0F26) },
2007   { Bad_Opcode },
2008   /* 28 */
2009   { "movapX",           { XM, EXx } },
2010   { "movapX",           { EXxS, XM } },
2011   { PREFIX_TABLE (PREFIX_0F2A) },
2012   { PREFIX_TABLE (PREFIX_0F2B) },
2013   { PREFIX_TABLE (PREFIX_0F2C) },
2014   { PREFIX_TABLE (PREFIX_0F2D) },
2015   { PREFIX_TABLE (PREFIX_0F2E) },
2016   { PREFIX_TABLE (PREFIX_0F2F) },
2017   /* 30 */
2018   { "wrmsr",            { XX } },
2019   { "rdtsc",            { XX } },
2020   { "rdmsr",            { XX } },
2021   { "rdpmc",            { XX } },
2022   { "sysenter",         { XX } },
2023   { "sysexit",          { XX } },
2024   { Bad_Opcode },
2025   { "getsec",           { XX } },
2026   /* 38 */
2027   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2028   { Bad_Opcode },
2029   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2030   { Bad_Opcode },
2031   { Bad_Opcode },
2032   { Bad_Opcode },
2033   { Bad_Opcode },
2034   { Bad_Opcode },
2035   /* 40 */
2036   { "cmovoS",           { Gv, Ev } },
2037   { "cmovnoS",          { Gv, Ev } },
2038   { "cmovbS",           { Gv, Ev } },
2039   { "cmovaeS",          { Gv, Ev } },
2040   { "cmoveS",           { Gv, Ev } },
2041   { "cmovneS",          { Gv, Ev } },
2042   { "cmovbeS",          { Gv, Ev } },
2043   { "cmovaS",           { Gv, Ev } },
2044   /* 48 */
2045   { "cmovsS",           { Gv, Ev } },
2046   { "cmovnsS",          { Gv, Ev } },
2047   { "cmovpS",           { Gv, Ev } },
2048   { "cmovnpS",          { Gv, Ev } },
2049   { "cmovlS",           { Gv, Ev } },
2050   { "cmovgeS",          { Gv, Ev } },
2051   { "cmovleS",          { Gv, Ev } },
2052   { "cmovgS",           { Gv, Ev } },
2053   /* 50 */
2054   { MOD_TABLE (MOD_0F51) },
2055   { PREFIX_TABLE (PREFIX_0F51) },
2056   { PREFIX_TABLE (PREFIX_0F52) },
2057   { PREFIX_TABLE (PREFIX_0F53) },
2058   { "andpX",            { XM, EXx } },
2059   { "andnpX",           { XM, EXx } },
2060   { "orpX",             { XM, EXx } },
2061   { "xorpX",            { XM, EXx } },
2062   /* 58 */
2063   { PREFIX_TABLE (PREFIX_0F58) },
2064   { PREFIX_TABLE (PREFIX_0F59) },
2065   { PREFIX_TABLE (PREFIX_0F5A) },
2066   { PREFIX_TABLE (PREFIX_0F5B) },
2067   { PREFIX_TABLE (PREFIX_0F5C) },
2068   { PREFIX_TABLE (PREFIX_0F5D) },
2069   { PREFIX_TABLE (PREFIX_0F5E) },
2070   { PREFIX_TABLE (PREFIX_0F5F) },
2071   /* 60 */
2072   { PREFIX_TABLE (PREFIX_0F60) },
2073   { PREFIX_TABLE (PREFIX_0F61) },
2074   { PREFIX_TABLE (PREFIX_0F62) },
2075   { "packsswb",         { MX, EM } },
2076   { "pcmpgtb",          { MX, EM } },
2077   { "pcmpgtw",          { MX, EM } },
2078   { "pcmpgtd",          { MX, EM } },
2079   { "packuswb",         { MX, EM } },
2080   /* 68 */
2081   { "punpckhbw",        { MX, EM } },
2082   { "punpckhwd",        { MX, EM } },
2083   { "punpckhdq",        { MX, EM } },
2084   { "packssdw",         { MX, EM } },
2085   { PREFIX_TABLE (PREFIX_0F6C) },
2086   { PREFIX_TABLE (PREFIX_0F6D) },
2087   { "movK",             { MX, Edq } },
2088   { PREFIX_TABLE (PREFIX_0F6F) },
2089   /* 70 */
2090   { PREFIX_TABLE (PREFIX_0F70) },
2091   { REG_TABLE (REG_0F71) },
2092   { REG_TABLE (REG_0F72) },
2093   { REG_TABLE (REG_0F73) },
2094   { "pcmpeqb",          { MX, EM } },
2095   { "pcmpeqw",          { MX, EM } },
2096   { "pcmpeqd",          { MX, EM } },
2097   { "emms",             { XX } },
2098   /* 78 */
2099   { PREFIX_TABLE (PREFIX_0F78) },
2100   { PREFIX_TABLE (PREFIX_0F79) },
2101   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2102   { Bad_Opcode },
2103   { PREFIX_TABLE (PREFIX_0F7C) },
2104   { PREFIX_TABLE (PREFIX_0F7D) },
2105   { PREFIX_TABLE (PREFIX_0F7E) },
2106   { PREFIX_TABLE (PREFIX_0F7F) },
2107   /* 80 */
2108   { "joH",              { Jv, XX, cond_jump_flag } },
2109   { "jnoH",             { Jv, XX, cond_jump_flag } },
2110   { "jbH",              { Jv, XX, cond_jump_flag } },
2111   { "jaeH",             { Jv, XX, cond_jump_flag } },
2112   { "jeH",              { Jv, XX, cond_jump_flag } },
2113   { "jneH",             { Jv, XX, cond_jump_flag } },
2114   { "jbeH",             { Jv, XX, cond_jump_flag } },
2115   { "jaH",              { Jv, XX, cond_jump_flag } },
2116   /* 88 */
2117   { "jsH",              { Jv, XX, cond_jump_flag } },
2118   { "jnsH",             { Jv, XX, cond_jump_flag } },
2119   { "jpH",              { Jv, XX, cond_jump_flag } },
2120   { "jnpH",             { Jv, XX, cond_jump_flag } },
2121   { "jlH",              { Jv, XX, cond_jump_flag } },
2122   { "jgeH",             { Jv, XX, cond_jump_flag } },
2123   { "jleH",             { Jv, XX, cond_jump_flag } },
2124   { "jgH",              { Jv, XX, cond_jump_flag } },
2125   /* 90 */
2126   { "seto",             { Eb } },
2127   { "setno",            { Eb } },
2128   { "setb",             { Eb } },
2129   { "setae",            { Eb } },
2130   { "sete",             { Eb } },
2131   { "setne",            { Eb } },
2132   { "setbe",            { Eb } },
2133   { "seta",             { Eb } },
2134   /* 98 */
2135   { "sets",             { Eb } },
2136   { "setns",            { Eb } },
2137   { "setp",             { Eb } },
2138   { "setnp",            { Eb } },
2139   { "setl",             { Eb } },
2140   { "setge",            { Eb } },
2141   { "setle",            { Eb } },
2142   { "setg",             { Eb } },
2143   /* a0 */
2144   { "pushT",            { fs } },
2145   { "popT",             { fs } },
2146   { "cpuid",            { XX } },
2147   { "btS",              { Ev, Gv } },
2148   { "shldS",            { Ev, Gv, Ib } },
2149   { "shldS",            { Ev, Gv, CL } },
2150   { REG_TABLE (REG_0FA6) },
2151   { REG_TABLE (REG_0FA7) },
2152   /* a8 */
2153   { "pushT",            { gs } },
2154   { "popT",             { gs } },
2155   { "rsm",              { XX } },
2156   { "btsS",             { Evh1, Gv } },
2157   { "shrdS",            { Ev, Gv, Ib } },
2158   { "shrdS",            { Ev, Gv, CL } },
2159   { REG_TABLE (REG_0FAE) },
2160   { "imulS",            { Gv, Ev } },
2161   /* b0 */
2162   { "cmpxchgB",         { Ebh1, Gb } },
2163   { "cmpxchgS",         { Evh1, Gv } },
2164   { MOD_TABLE (MOD_0FB2) },
2165   { "btrS",             { Evh1, Gv } },
2166   { MOD_TABLE (MOD_0FB4) },
2167   { MOD_TABLE (MOD_0FB5) },
2168   { "movz{bR|x}",       { Gv, Eb } },
2169   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2170   /* b8 */
2171   { PREFIX_TABLE (PREFIX_0FB8) },
2172   { "ud1",              { XX } },
2173   { REG_TABLE (REG_0FBA) },
2174   { "btcS",             { Evh1, Gv } },
2175   { PREFIX_TABLE (PREFIX_0FBC) },
2176   { PREFIX_TABLE (PREFIX_0FBD) },
2177   { "movs{bR|x}",       { Gv, Eb } },
2178   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2179   /* c0 */
2180   { "xaddB",            { Ebh1, Gb } },
2181   { "xaddS",            { Evh1, Gv } },
2182   { PREFIX_TABLE (PREFIX_0FC2) },
2183   { PREFIX_TABLE (PREFIX_0FC3) },
2184   { "pinsrw",           { MX, Edqw, Ib } },
2185   { "pextrw",           { Gdq, MS, Ib } },
2186   { "shufpX",           { XM, EXx, Ib } },
2187   { REG_TABLE (REG_0FC7) },
2188   /* c8 */
2189   { "bswap",            { RMeAX } },
2190   { "bswap",            { RMeCX } },
2191   { "bswap",            { RMeDX } },
2192   { "bswap",            { RMeBX } },
2193   { "bswap",            { RMeSP } },
2194   { "bswap",            { RMeBP } },
2195   { "bswap",            { RMeSI } },
2196   { "bswap",            { RMeDI } },
2197   /* d0 */
2198   { PREFIX_TABLE (PREFIX_0FD0) },
2199   { "psrlw",            { MX, EM } },
2200   { "psrld",            { MX, EM } },
2201   { "psrlq",            { MX, EM } },
2202   { "paddq",            { MX, EM } },
2203   { "pmullw",           { MX, EM } },
2204   { PREFIX_TABLE (PREFIX_0FD6) },
2205   { MOD_TABLE (MOD_0FD7) },
2206   /* d8 */
2207   { "psubusb",          { MX, EM } },
2208   { "psubusw",          { MX, EM } },
2209   { "pminub",           { MX, EM } },
2210   { "pand",             { MX, EM } },
2211   { "paddusb",          { MX, EM } },
2212   { "paddusw",          { MX, EM } },
2213   { "pmaxub",           { MX, EM } },
2214   { "pandn",            { MX, EM } },
2215   /* e0 */
2216   { "pavgb",            { MX, EM } },
2217   { "psraw",            { MX, EM } },
2218   { "psrad",            { MX, EM } },
2219   { "pavgw",            { MX, EM } },
2220   { "pmulhuw",          { MX, EM } },
2221   { "pmulhw",           { MX, EM } },
2222   { PREFIX_TABLE (PREFIX_0FE6) },
2223   { PREFIX_TABLE (PREFIX_0FE7) },
2224   /* e8 */
2225   { "psubsb",           { MX, EM } },
2226   { "psubsw",           { MX, EM } },
2227   { "pminsw",           { MX, EM } },
2228   { "por",              { MX, EM } },
2229   { "paddsb",           { MX, EM } },
2230   { "paddsw",           { MX, EM } },
2231   { "pmaxsw",           { MX, EM } },
2232   { "pxor",             { MX, EM } },
2233   /* f0 */
2234   { PREFIX_TABLE (PREFIX_0FF0) },
2235   { "psllw",            { MX, EM } },
2236   { "pslld",            { MX, EM } },
2237   { "psllq",            { MX, EM } },
2238   { "pmuludq",          { MX, EM } },
2239   { "pmaddwd",          { MX, EM } },
2240   { "psadbw",           { MX, EM } },
2241   { PREFIX_TABLE (PREFIX_0FF7) },
2242   /* f8 */
2243   { "psubb",            { MX, EM } },
2244   { "psubw",            { MX, EM } },
2245   { "psubd",            { MX, EM } },
2246   { "psubq",            { MX, EM } },
2247   { "paddb",            { MX, EM } },
2248   { "paddw",            { MX, EM } },
2249   { "paddd",            { MX, EM } },
2250   { Bad_Opcode },
2251 };
2252
2253 static const unsigned char onebyte_has_modrm[256] = {
2254   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2255   /*       -------------------------------        */
2256   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2257   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2258   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2259   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2260   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2261   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2262   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2263   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2264   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2265   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2266   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2267   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2268   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2269   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2270   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2271   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2272   /*       -------------------------------        */
2273   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2274 };
2275
2276 static const unsigned char twobyte_has_modrm[256] = {
2277   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2278   /*       -------------------------------        */
2279   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2280   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2281   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2282   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2283   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2284   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2285   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2286   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2287   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2288   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2289   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2290   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2291   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2292   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2293   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2294   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2295   /*       -------------------------------        */
2296   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2297 };
2298
2299 static char obuf[100];
2300 static char *obufp;
2301 static char *mnemonicendp;
2302 static char scratchbuf[100];
2303 static unsigned char *start_codep;
2304 static unsigned char *insn_codep;
2305 static unsigned char *codep;
2306 static int last_lock_prefix;
2307 static int last_repz_prefix;
2308 static int last_repnz_prefix;
2309 static int last_data_prefix;
2310 static int last_addr_prefix;
2311 static int last_rex_prefix;
2312 static int last_seg_prefix;
2313 #define MAX_CODE_LENGTH 15
2314 /* We can up to 14 prefixes since the maximum instruction length is
2315    15bytes.  */
2316 static int all_prefixes[MAX_CODE_LENGTH - 1];
2317 static disassemble_info *the_info;
2318 static struct
2319   {
2320     int mod;
2321     int reg;
2322     int rm;
2323   }
2324 modrm;
2325 static unsigned char need_modrm;
2326 static struct
2327   {
2328     int scale;
2329     int index;
2330     int base;
2331   }
2332 sib;
2333 static struct
2334   {
2335     int register_specifier;
2336     int length;
2337     int prefix;
2338     int w;
2339   }
2340 vex;
2341 static unsigned char need_vex;
2342 static unsigned char need_vex_reg;
2343 static unsigned char vex_w_done;
2344
2345 struct op
2346   {
2347     const char *name;
2348     unsigned int len;
2349   };
2350
2351 /* If we are accessing mod/rm/reg without need_modrm set, then the
2352    values are stale.  Hitting this abort likely indicates that you
2353    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2354 #define MODRM_CHECK  if (!need_modrm) abort ()
2355
2356 static const char **names64;
2357 static const char **names32;
2358 static const char **names16;
2359 static const char **names8;
2360 static const char **names8rex;
2361 static const char **names_seg;
2362 static const char *index64;
2363 static const char *index32;
2364 static const char **index16;
2365
2366 static const char *intel_names64[] = {
2367   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2368   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2369 };
2370 static const char *intel_names32[] = {
2371   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2372   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2373 };
2374 static const char *intel_names16[] = {
2375   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2376   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2377 };
2378 static const char *intel_names8[] = {
2379   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2380 };
2381 static const char *intel_names8rex[] = {
2382   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2383   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2384 };
2385 static const char *intel_names_seg[] = {
2386   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2387 };
2388 static const char *intel_index64 = "riz";
2389 static const char *intel_index32 = "eiz";
2390 static const char *intel_index16[] = {
2391   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2392 };
2393
2394 static const char *att_names64[] = {
2395   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2396   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2397 };
2398 static const char *att_names32[] = {
2399   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2400   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2401 };
2402 static const char *att_names16[] = {
2403   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2404   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2405 };
2406 static const char *att_names8[] = {
2407   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2408 };
2409 static const char *att_names8rex[] = {
2410   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2411   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2412 };
2413 static const char *att_names_seg[] = {
2414   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2415 };
2416 static const char *att_index64 = "%riz";
2417 static const char *att_index32 = "%eiz";
2418 static const char *att_index16[] = {
2419   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2420 };
2421
2422 static const char **names_mm;
2423 static const char *intel_names_mm[] = {
2424   "mm0", "mm1", "mm2", "mm3",
2425   "mm4", "mm5", "mm6", "mm7"
2426 };
2427 static const char *att_names_mm[] = {
2428   "%mm0", "%mm1", "%mm2", "%mm3",
2429   "%mm4", "%mm5", "%mm6", "%mm7"
2430 };
2431
2432 static const char **names_xmm;
2433 static const char *intel_names_xmm[] = {
2434   "xmm0", "xmm1", "xmm2", "xmm3",
2435   "xmm4", "xmm5", "xmm6", "xmm7",
2436   "xmm8", "xmm9", "xmm10", "xmm11",
2437   "xmm12", "xmm13", "xmm14", "xmm15"
2438 };
2439 static const char *att_names_xmm[] = {
2440   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2441   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2442   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2443   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2444 };
2445
2446 static const char **names_ymm;
2447 static const char *intel_names_ymm[] = {
2448   "ymm0", "ymm1", "ymm2", "ymm3",
2449   "ymm4", "ymm5", "ymm6", "ymm7",
2450   "ymm8", "ymm9", "ymm10", "ymm11",
2451   "ymm12", "ymm13", "ymm14", "ymm15"
2452 };
2453 static const char *att_names_ymm[] = {
2454   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2455   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2456   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2457   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2458 };
2459
2460 static const struct dis386 reg_table[][8] = {
2461   /* REG_80 */
2462   {
2463     { "addA",   { Ebh1, Ib } },
2464     { "orA",    { Ebh1, Ib } },
2465     { "adcA",   { Ebh1, Ib } },
2466     { "sbbA",   { Ebh1, Ib } },
2467     { "andA",   { Ebh1, Ib } },
2468     { "subA",   { Ebh1, Ib } },
2469     { "xorA",   { Ebh1, Ib } },
2470     { "cmpA",   { Eb, Ib } },
2471   },
2472   /* REG_81 */
2473   {
2474     { "addQ",   { Evh1, Iv } },
2475     { "orQ",    { Evh1, Iv } },
2476     { "adcQ",   { Evh1, Iv } },
2477     { "sbbQ",   { Evh1, Iv } },
2478     { "andQ",   { Evh1, Iv } },
2479     { "subQ",   { Evh1, Iv } },
2480     { "xorQ",   { Evh1, Iv } },
2481     { "cmpQ",   { Ev, Iv } },
2482   },
2483   /* REG_82 */
2484   {
2485     { "addQ",   { Evh1, sIb } },
2486     { "orQ",    { Evh1, sIb } },
2487     { "adcQ",   { Evh1, sIb } },
2488     { "sbbQ",   { Evh1, sIb } },
2489     { "andQ",   { Evh1, sIb } },
2490     { "subQ",   { Evh1, sIb } },
2491     { "xorQ",   { Evh1, sIb } },
2492     { "cmpQ",   { Ev, sIb } },
2493   },
2494   /* REG_8F */
2495   {
2496     { "popU",   { stackEv } },
2497     { XOP_8F_TABLE (XOP_09) },
2498     { Bad_Opcode },
2499     { Bad_Opcode },
2500     { Bad_Opcode },
2501     { XOP_8F_TABLE (XOP_09) },
2502   },
2503   /* REG_C0 */
2504   {
2505     { "rolA",   { Eb, Ib } },
2506     { "rorA",   { Eb, Ib } },
2507     { "rclA",   { Eb, Ib } },
2508     { "rcrA",   { Eb, Ib } },
2509     { "shlA",   { Eb, Ib } },
2510     { "shrA",   { Eb, Ib } },
2511     { Bad_Opcode },
2512     { "sarA",   { Eb, Ib } },
2513   },
2514   /* REG_C1 */
2515   {
2516     { "rolQ",   { Ev, Ib } },
2517     { "rorQ",   { Ev, Ib } },
2518     { "rclQ",   { Ev, Ib } },
2519     { "rcrQ",   { Ev, Ib } },
2520     { "shlQ",   { Ev, Ib } },
2521     { "shrQ",   { Ev, Ib } },
2522     { Bad_Opcode },
2523     { "sarQ",   { Ev, Ib } },
2524   },
2525   /* REG_C6 */
2526   {
2527     { "movA",   { Ebh3, Ib } },
2528     { Bad_Opcode },
2529     { Bad_Opcode },
2530     { Bad_Opcode },
2531     { Bad_Opcode },
2532     { Bad_Opcode },
2533     { Bad_Opcode },
2534     { MOD_TABLE (MOD_C6_REG_7) },
2535   },
2536   /* REG_C7 */
2537   {
2538     { "movQ",   { Evh3, Iv } },
2539     { Bad_Opcode },
2540     { Bad_Opcode },
2541     { Bad_Opcode },
2542     { Bad_Opcode },
2543     { Bad_Opcode },
2544     { Bad_Opcode },
2545     { MOD_TABLE (MOD_C7_REG_7) },
2546   },
2547   /* REG_D0 */
2548   {
2549     { "rolA",   { Eb, I1 } },
2550     { "rorA",   { Eb, I1 } },
2551     { "rclA",   { Eb, I1 } },
2552     { "rcrA",   { Eb, I1 } },
2553     { "shlA",   { Eb, I1 } },
2554     { "shrA",   { Eb, I1 } },
2555     { Bad_Opcode },
2556     { "sarA",   { Eb, I1 } },
2557   },
2558   /* REG_D1 */
2559   {
2560     { "rolQ",   { Ev, I1 } },
2561     { "rorQ",   { Ev, I1 } },
2562     { "rclQ",   { Ev, I1 } },
2563     { "rcrQ",   { Ev, I1 } },
2564     { "shlQ",   { Ev, I1 } },
2565     { "shrQ",   { Ev, I1 } },
2566     { Bad_Opcode },
2567     { "sarQ",   { Ev, I1 } },
2568   },
2569   /* REG_D2 */
2570   {
2571     { "rolA",   { Eb, CL } },
2572     { "rorA",   { Eb, CL } },
2573     { "rclA",   { Eb, CL } },
2574     { "rcrA",   { Eb, CL } },
2575     { "shlA",   { Eb, CL } },
2576     { "shrA",   { Eb, CL } },
2577     { Bad_Opcode },
2578     { "sarA",   { Eb, CL } },
2579   },
2580   /* REG_D3 */
2581   {
2582     { "rolQ",   { Ev, CL } },
2583     { "rorQ",   { Ev, CL } },
2584     { "rclQ",   { Ev, CL } },
2585     { "rcrQ",   { Ev, CL } },
2586     { "shlQ",   { Ev, CL } },
2587     { "shrQ",   { Ev, CL } },
2588     { Bad_Opcode },
2589     { "sarQ",   { Ev, CL } },
2590   },
2591   /* REG_F6 */
2592   {
2593     { "testA",  { Eb, Ib } },
2594     { Bad_Opcode },
2595     { "notA",   { Ebh1 } },
2596     { "negA",   { Ebh1 } },
2597     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2598     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2599     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2600     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2601   },
2602   /* REG_F7 */
2603   {
2604     { "testQ",  { Ev, Iv } },
2605     { Bad_Opcode },
2606     { "notQ",   { Evh1 } },
2607     { "negQ",   { Evh1 } },
2608     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2609     { "imulQ",  { Ev } },
2610     { "divQ",   { Ev } },
2611     { "idivQ",  { Ev } },
2612   },
2613   /* REG_FE */
2614   {
2615     { "incA",   { Ebh1 } },
2616     { "decA",   { Ebh1 } },
2617   },
2618   /* REG_FF */
2619   {
2620     { "incQ",   { Evh1 } },
2621     { "decQ",   { Evh1 } },
2622     { "call{T|}", { indirEv } },
2623     { "Jcall{T|}", { indirEp } },
2624     { "jmp{T|}", { indirEv } },
2625     { "Jjmp{T|}", { indirEp } },
2626     { "pushU",  { stackEv } },
2627     { Bad_Opcode },
2628   },
2629   /* REG_0F00 */
2630   {
2631     { "sldtD",  { Sv } },
2632     { "strD",   { Sv } },
2633     { "lldt",   { Ew } },
2634     { "ltr",    { Ew } },
2635     { "verr",   { Ew } },
2636     { "verw",   { Ew } },
2637     { Bad_Opcode },
2638     { Bad_Opcode },
2639   },
2640   /* REG_0F01 */
2641   {
2642     { MOD_TABLE (MOD_0F01_REG_0) },
2643     { MOD_TABLE (MOD_0F01_REG_1) },
2644     { MOD_TABLE (MOD_0F01_REG_2) },
2645     { MOD_TABLE (MOD_0F01_REG_3) },
2646     { "smswD",  { Sv } },
2647     { Bad_Opcode },
2648     { "lmsw",   { Ew } },
2649     { MOD_TABLE (MOD_0F01_REG_7) },
2650   },
2651   /* REG_0F0D */
2652   {
2653     { "prefetch",       { Mb } },
2654     { "prefetchw",      { Mb } },
2655   },
2656   /* REG_0F18 */
2657   {
2658     { MOD_TABLE (MOD_0F18_REG_0) },
2659     { MOD_TABLE (MOD_0F18_REG_1) },
2660     { MOD_TABLE (MOD_0F18_REG_2) },
2661     { MOD_TABLE (MOD_0F18_REG_3) },
2662   },
2663   /* REG_0F71 */
2664   {
2665     { Bad_Opcode },
2666     { Bad_Opcode },
2667     { MOD_TABLE (MOD_0F71_REG_2) },
2668     { Bad_Opcode },
2669     { MOD_TABLE (MOD_0F71_REG_4) },
2670     { Bad_Opcode },
2671     { MOD_TABLE (MOD_0F71_REG_6) },
2672   },
2673   /* REG_0F72 */
2674   {
2675     { Bad_Opcode },
2676     { Bad_Opcode },
2677     { MOD_TABLE (MOD_0F72_REG_2) },
2678     { Bad_Opcode },
2679     { MOD_TABLE (MOD_0F72_REG_4) },
2680     { Bad_Opcode },
2681     { MOD_TABLE (MOD_0F72_REG_6) },
2682   },
2683   /* REG_0F73 */
2684   {
2685     { Bad_Opcode },
2686     { Bad_Opcode },
2687     { MOD_TABLE (MOD_0F73_REG_2) },
2688     { MOD_TABLE (MOD_0F73_REG_3) },
2689     { Bad_Opcode },
2690     { Bad_Opcode },
2691     { MOD_TABLE (MOD_0F73_REG_6) },
2692     { MOD_TABLE (MOD_0F73_REG_7) },
2693   },
2694   /* REG_0FA6 */
2695   {
2696     { "montmul",        { { OP_0f07, 0 } } },
2697     { "xsha1",          { { OP_0f07, 0 } } },
2698     { "xsha256",        { { OP_0f07, 0 } } },
2699   },
2700   /* REG_0FA7 */
2701   {
2702     { "xstore-rng",     { { OP_0f07, 0 } } },
2703     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2704     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2705     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2706     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2707     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2708   },
2709   /* REG_0FAE */
2710   {
2711     { MOD_TABLE (MOD_0FAE_REG_0) },
2712     { MOD_TABLE (MOD_0FAE_REG_1) },
2713     { MOD_TABLE (MOD_0FAE_REG_2) },
2714     { MOD_TABLE (MOD_0FAE_REG_3) },
2715     { MOD_TABLE (MOD_0FAE_REG_4) },
2716     { MOD_TABLE (MOD_0FAE_REG_5) },
2717     { MOD_TABLE (MOD_0FAE_REG_6) },
2718     { MOD_TABLE (MOD_0FAE_REG_7) },
2719   },
2720   /* REG_0FBA */
2721   {
2722     { Bad_Opcode },
2723     { Bad_Opcode },
2724     { Bad_Opcode },
2725     { Bad_Opcode },
2726     { "btQ",    { Ev, Ib } },
2727     { "btsQ",   { Evh1, Ib } },
2728     { "btrQ",   { Evh1, Ib } },
2729     { "btcQ",   { Evh1, Ib } },
2730   },
2731   /* REG_0FC7 */
2732   {
2733     { Bad_Opcode },
2734     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2735     { Bad_Opcode },
2736     { Bad_Opcode },
2737     { Bad_Opcode },
2738     { Bad_Opcode },
2739     { MOD_TABLE (MOD_0FC7_REG_6) },
2740     { MOD_TABLE (MOD_0FC7_REG_7) },
2741   },
2742   /* REG_VEX_0F71 */
2743   {
2744     { Bad_Opcode },
2745     { Bad_Opcode },
2746     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2747     { Bad_Opcode },
2748     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2749     { Bad_Opcode },
2750     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2751   },
2752   /* REG_VEX_0F72 */
2753   {
2754     { Bad_Opcode },
2755     { Bad_Opcode },
2756     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2757     { Bad_Opcode },
2758     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2759     { Bad_Opcode },
2760     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2761   },
2762   /* REG_VEX_0F73 */
2763   {
2764     { Bad_Opcode },
2765     { Bad_Opcode },
2766     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2767     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2768     { Bad_Opcode },
2769     { Bad_Opcode },
2770     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2771     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2772   },
2773   /* REG_VEX_0FAE */
2774   {
2775     { Bad_Opcode },
2776     { Bad_Opcode },
2777     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2778     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2779   },
2780   /* REG_VEX_0F38F3 */
2781   {
2782     { Bad_Opcode },
2783     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2784     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2785     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2786   },
2787   /* REG_XOP_LWPCB */
2788   {
2789     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2790     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2791   },
2792   /* REG_XOP_LWP */
2793   {
2794     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2795     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2796   },
2797   /* REG_XOP_TBM_01 */
2798   {
2799     { Bad_Opcode },
2800     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
2801     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
2802     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
2803     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
2804     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
2805     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
2806     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2807   },
2808   /* REG_XOP_TBM_02 */
2809   {
2810     { Bad_Opcode },
2811     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2812     { Bad_Opcode },
2813     { Bad_Opcode },
2814     { Bad_Opcode },
2815     { Bad_Opcode },
2816     { "blci",   { { OP_LWP_E, 0 }, Ev } },
2817   },
2818 };
2819
2820 static const struct dis386 prefix_table[][4] = {
2821   /* PREFIX_90 */
2822   {
2823     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2824     { "pause", { XX } },
2825     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2826   },
2827
2828   /* PREFIX_0F10 */
2829   {
2830     { "movups", { XM, EXx } },
2831     { "movss",  { XM, EXd } },
2832     { "movupd", { XM, EXx } },
2833     { "movsd",  { XM, EXq } },
2834   },
2835
2836   /* PREFIX_0F11 */
2837   {
2838     { "movups", { EXxS, XM } },
2839     { "movss",  { EXdS, XM } },
2840     { "movupd", { EXxS, XM } },
2841     { "movsd",  { EXqS, XM } },
2842   },
2843
2844   /* PREFIX_0F12 */
2845   {
2846     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2847     { "movsldup", { XM, EXx } },
2848     { "movlpd", { XM, EXq } },
2849     { "movddup", { XM, EXq } },
2850   },
2851
2852   /* PREFIX_0F16 */
2853   {
2854     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2855     { "movshdup", { XM, EXx } },
2856     { "movhpd", { XM, EXq } },
2857   },
2858
2859   /* PREFIX_0F2A */
2860   {
2861     { "cvtpi2ps", { XM, EMCq } },
2862     { "cvtsi2ss%LQ", { XM, Ev } },
2863     { "cvtpi2pd", { XM, EMCq } },
2864     { "cvtsi2sd%LQ", { XM, Ev } },
2865   },
2866
2867   /* PREFIX_0F2B */
2868   {
2869     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2870     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2871     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2872     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2873   },
2874
2875   /* PREFIX_0F2C */
2876   {
2877     { "cvttps2pi", { MXC, EXq } },
2878     { "cvttss2siY", { Gv, EXd } },
2879     { "cvttpd2pi", { MXC, EXx } },
2880     { "cvttsd2siY", { Gv, EXq } },
2881   },
2882
2883   /* PREFIX_0F2D */
2884   {
2885     { "cvtps2pi", { MXC, EXq } },
2886     { "cvtss2siY", { Gv, EXd } },
2887     { "cvtpd2pi", { MXC, EXx } },
2888     { "cvtsd2siY", { Gv, EXq } },
2889   },
2890
2891   /* PREFIX_0F2E */
2892   {
2893     { "ucomiss",{ XM, EXd } },
2894     { Bad_Opcode },
2895     { "ucomisd",{ XM, EXq } },
2896   },
2897
2898   /* PREFIX_0F2F */
2899   {
2900     { "comiss", { XM, EXd } },
2901     { Bad_Opcode },
2902     { "comisd", { XM, EXq } },
2903   },
2904
2905   /* PREFIX_0F51 */
2906   {
2907     { "sqrtps", { XM, EXx } },
2908     { "sqrtss", { XM, EXd } },
2909     { "sqrtpd", { XM, EXx } },
2910     { "sqrtsd", { XM, EXq } },
2911   },
2912
2913   /* PREFIX_0F52 */
2914   {
2915     { "rsqrtps",{ XM, EXx } },
2916     { "rsqrtss",{ XM, EXd } },
2917   },
2918
2919   /* PREFIX_0F53 */
2920   {
2921     { "rcpps",  { XM, EXx } },
2922     { "rcpss",  { XM, EXd } },
2923   },
2924
2925   /* PREFIX_0F58 */
2926   {
2927     { "addps", { XM, EXx } },
2928     { "addss", { XM, EXd } },
2929     { "addpd", { XM, EXx } },
2930     { "addsd", { XM, EXq } },
2931   },
2932
2933   /* PREFIX_0F59 */
2934   {
2935     { "mulps",  { XM, EXx } },
2936     { "mulss",  { XM, EXd } },
2937     { "mulpd",  { XM, EXx } },
2938     { "mulsd",  { XM, EXq } },
2939   },
2940
2941   /* PREFIX_0F5A */
2942   {
2943     { "cvtps2pd", { XM, EXq } },
2944     { "cvtss2sd", { XM, EXd } },
2945     { "cvtpd2ps", { XM, EXx } },
2946     { "cvtsd2ss", { XM, EXq } },
2947   },
2948
2949   /* PREFIX_0F5B */
2950   {
2951     { "cvtdq2ps", { XM, EXx } },
2952     { "cvttps2dq", { XM, EXx } },
2953     { "cvtps2dq", { XM, EXx } },
2954   },
2955
2956   /* PREFIX_0F5C */
2957   {
2958     { "subps",  { XM, EXx } },
2959     { "subss",  { XM, EXd } },
2960     { "subpd",  { XM, EXx } },
2961     { "subsd",  { XM, EXq } },
2962   },
2963
2964   /* PREFIX_0F5D */
2965   {
2966     { "minps",  { XM, EXx } },
2967     { "minss",  { XM, EXd } },
2968     { "minpd",  { XM, EXx } },
2969     { "minsd",  { XM, EXq } },
2970   },
2971
2972   /* PREFIX_0F5E */
2973   {
2974     { "divps",  { XM, EXx } },
2975     { "divss",  { XM, EXd } },
2976     { "divpd",  { XM, EXx } },
2977     { "divsd",  { XM, EXq } },
2978   },
2979
2980   /* PREFIX_0F5F */
2981   {
2982     { "maxps",  { XM, EXx } },
2983     { "maxss",  { XM, EXd } },
2984     { "maxpd",  { XM, EXx } },
2985     { "maxsd",  { XM, EXq } },
2986   },
2987
2988   /* PREFIX_0F60 */
2989   {
2990     { "punpcklbw",{ MX, EMd } },
2991     { Bad_Opcode },
2992     { "punpcklbw",{ MX, EMx } },
2993   },
2994
2995   /* PREFIX_0F61 */
2996   {
2997     { "punpcklwd",{ MX, EMd } },
2998     { Bad_Opcode },
2999     { "punpcklwd",{ MX, EMx } },
3000   },
3001
3002   /* PREFIX_0F62 */
3003   {
3004     { "punpckldq",{ MX, EMd } },
3005     { Bad_Opcode },
3006     { "punpckldq",{ MX, EMx } },
3007   },
3008
3009   /* PREFIX_0F6C */
3010   {
3011     { Bad_Opcode },
3012     { Bad_Opcode },
3013     { "punpcklqdq", { XM, EXx } },
3014   },
3015
3016   /* PREFIX_0F6D */
3017   {
3018     { Bad_Opcode },
3019     { Bad_Opcode },
3020     { "punpckhqdq", { XM, EXx } },
3021   },
3022
3023   /* PREFIX_0F6F */
3024   {
3025     { "movq",   { MX, EM } },
3026     { "movdqu", { XM, EXx } },
3027     { "movdqa", { XM, EXx } },
3028   },
3029
3030   /* PREFIX_0F70 */
3031   {
3032     { "pshufw", { MX, EM, Ib } },
3033     { "pshufhw",{ XM, EXx, Ib } },
3034     { "pshufd", { XM, EXx, Ib } },
3035     { "pshuflw",{ XM, EXx, Ib } },
3036   },
3037
3038   /* PREFIX_0F73_REG_3 */
3039   {
3040     { Bad_Opcode },
3041     { Bad_Opcode },
3042     { "psrldq", { XS, Ib } },
3043   },
3044
3045   /* PREFIX_0F73_REG_7 */
3046   {
3047     { Bad_Opcode },
3048     { Bad_Opcode },
3049     { "pslldq", { XS, Ib } },
3050   },
3051
3052   /* PREFIX_0F78 */
3053   {
3054     {"vmread",  { Em, Gm } },
3055     { Bad_Opcode },
3056     {"extrq",   { XS, Ib, Ib } },
3057     {"insertq", { XM, XS, Ib, Ib } },
3058   },
3059
3060   /* PREFIX_0F79 */
3061   {
3062     {"vmwrite", { Gm, Em } },
3063     { Bad_Opcode },
3064     {"extrq",   { XM, XS } },
3065     {"insertq", { XM, XS } },
3066   },
3067
3068   /* PREFIX_0F7C */
3069   {
3070     { Bad_Opcode },
3071     { Bad_Opcode },
3072     { "haddpd", { XM, EXx } },
3073     { "haddps", { XM, EXx } },
3074   },
3075
3076   /* PREFIX_0F7D */
3077   {
3078     { Bad_Opcode },
3079     { Bad_Opcode },
3080     { "hsubpd", { XM, EXx } },
3081     { "hsubps", { XM, EXx } },
3082   },
3083
3084   /* PREFIX_0F7E */
3085   {
3086     { "movK",   { Edq, MX } },
3087     { "movq",   { XM, EXq } },
3088     { "movK",   { Edq, XM } },
3089   },
3090
3091   /* PREFIX_0F7F */
3092   {
3093     { "movq",   { EMS, MX } },
3094     { "movdqu", { EXxS, XM } },
3095     { "movdqa", { EXxS, XM } },
3096   },
3097
3098   /* PREFIX_0FAE_REG_0 */
3099   {
3100     { Bad_Opcode },
3101     { "rdfsbase", { Ev } },
3102   },
3103
3104   /* PREFIX_0FAE_REG_1 */
3105   {
3106     { Bad_Opcode },
3107     { "rdgsbase", { Ev } },
3108   },
3109
3110   /* PREFIX_0FAE_REG_2 */
3111   {
3112     { Bad_Opcode },
3113     { "wrfsbase", { Ev } },
3114   },
3115
3116   /* PREFIX_0FAE_REG_3 */
3117   {
3118     { Bad_Opcode },
3119     { "wrgsbase", { Ev } },
3120   },
3121
3122   /* PREFIX_0FB8 */
3123   {
3124     { Bad_Opcode },
3125     { "popcntS", { Gv, Ev } },
3126   },
3127
3128   /* PREFIX_0FBC */
3129   {
3130     { "bsfS",   { Gv, Ev } },
3131     { "tzcntS", { Gv, Ev } },
3132     { "bsfS",   { Gv, Ev } },
3133   },
3134
3135   /* PREFIX_0FBD */
3136   {
3137     { "bsrS",   { Gv, Ev } },
3138     { "lzcntS", { Gv, Ev } },
3139     { "bsrS",   { Gv, Ev } },
3140   },
3141
3142   /* PREFIX_0FC2 */
3143   {
3144     { "cmpps",  { XM, EXx, CMP } },
3145     { "cmpss",  { XM, EXd, CMP } },
3146     { "cmppd",  { XM, EXx, CMP } },
3147     { "cmpsd",  { XM, EXq, CMP } },
3148   },
3149
3150   /* PREFIX_0FC3 */
3151   {
3152     { "movntiS", { Ma, Gv } },
3153   },
3154
3155   /* PREFIX_0FC7_REG_6 */
3156   {
3157     { "vmptrld",{ Mq } },
3158     { "vmxon",  { Mq } },
3159     { "vmclear",{ Mq } },
3160   },
3161
3162   /* PREFIX_0FD0 */
3163   {
3164     { Bad_Opcode },
3165     { Bad_Opcode },
3166     { "addsubpd", { XM, EXx } },
3167     { "addsubps", { XM, EXx } },
3168   },
3169
3170   /* PREFIX_0FD6 */
3171   {
3172     { Bad_Opcode },
3173     { "movq2dq",{ XM, MS } },
3174     { "movq",   { EXqS, XM } },
3175     { "movdq2q",{ MX, XS } },
3176   },
3177
3178   /* PREFIX_0FE6 */
3179   {
3180     { Bad_Opcode },
3181     { "cvtdq2pd", { XM, EXq } },
3182     { "cvttpd2dq", { XM, EXx } },
3183     { "cvtpd2dq", { XM, EXx } },
3184   },
3185
3186   /* PREFIX_0FE7 */
3187   {
3188     { "movntq", { Mq, MX } },
3189     { Bad_Opcode },
3190     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3191   },
3192
3193   /* PREFIX_0FF0 */
3194   {
3195     { Bad_Opcode },
3196     { Bad_Opcode },
3197     { Bad_Opcode },
3198     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3199   },
3200
3201   /* PREFIX_0FF7 */
3202   {
3203     { "maskmovq", { MX, MS } },
3204     { Bad_Opcode },
3205     { "maskmovdqu", { XM, XS } },
3206   },
3207
3208   /* PREFIX_0F3810 */
3209   {
3210     { Bad_Opcode },
3211     { Bad_Opcode },
3212     { "pblendvb", { XM, EXx, XMM0 } },
3213   },
3214
3215   /* PREFIX_0F3814 */
3216   {
3217     { Bad_Opcode },
3218     { Bad_Opcode },
3219     { "blendvps", { XM, EXx, XMM0 } },
3220   },
3221
3222   /* PREFIX_0F3815 */
3223   {
3224     { Bad_Opcode },
3225     { Bad_Opcode },
3226     { "blendvpd", { XM, EXx, XMM0 } },
3227   },
3228
3229   /* PREFIX_0F3817 */
3230   {
3231     { Bad_Opcode },
3232     { Bad_Opcode },
3233     { "ptest",  { XM, EXx } },
3234   },
3235
3236   /* PREFIX_0F3820 */
3237   {
3238     { Bad_Opcode },
3239     { Bad_Opcode },
3240     { "pmovsxbw", { XM, EXq } },
3241   },
3242
3243   /* PREFIX_0F3821 */
3244   {
3245     { Bad_Opcode },
3246     { Bad_Opcode },
3247     { "pmovsxbd", { XM, EXd } },
3248   },
3249
3250   /* PREFIX_0F3822 */
3251   {
3252     { Bad_Opcode },
3253     { Bad_Opcode },
3254     { "pmovsxbq", { XM, EXw } },
3255   },
3256
3257   /* PREFIX_0F3823 */
3258   {
3259     { Bad_Opcode },
3260     { Bad_Opcode },
3261     { "pmovsxwd", { XM, EXq } },
3262   },
3263
3264   /* PREFIX_0F3824 */
3265   {
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { "pmovsxwq", { XM, EXd } },
3269   },
3270
3271   /* PREFIX_0F3825 */
3272   {
3273     { Bad_Opcode },
3274     { Bad_Opcode },
3275     { "pmovsxdq", { XM, EXq } },
3276   },
3277
3278   /* PREFIX_0F3828 */
3279   {
3280     { Bad_Opcode },
3281     { Bad_Opcode },
3282     { "pmuldq", { XM, EXx } },
3283   },
3284
3285   /* PREFIX_0F3829 */
3286   {
3287     { Bad_Opcode },
3288     { Bad_Opcode },
3289     { "pcmpeqq", { XM, EXx } },
3290   },
3291
3292   /* PREFIX_0F382A */
3293   {
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3297   },
3298
3299   /* PREFIX_0F382B */
3300   {
3301     { Bad_Opcode },
3302     { Bad_Opcode },
3303     { "packusdw", { XM, EXx } },
3304   },
3305
3306   /* PREFIX_0F3830 */
3307   {
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { "pmovzxbw", { XM, EXq } },
3311   },
3312
3313   /* PREFIX_0F3831 */
3314   {
3315     { Bad_Opcode },
3316     { Bad_Opcode },
3317     { "pmovzxbd", { XM, EXd } },
3318   },
3319
3320   /* PREFIX_0F3832 */
3321   {
3322     { Bad_Opcode },
3323     { Bad_Opcode },
3324     { "pmovzxbq", { XM, EXw } },
3325   },
3326
3327   /* PREFIX_0F3833 */
3328   {
3329     { Bad_Opcode },
3330     { Bad_Opcode },
3331     { "pmovzxwd", { XM, EXq } },
3332   },
3333
3334   /* PREFIX_0F3834 */
3335   {
3336     { Bad_Opcode },
3337     { Bad_Opcode },
3338     { "pmovzxwq", { XM, EXd } },
3339   },
3340
3341   /* PREFIX_0F3835 */
3342   {
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345     { "pmovzxdq", { XM, EXq } },
3346   },
3347
3348   /* PREFIX_0F3837 */
3349   {
3350     { Bad_Opcode },
3351     { Bad_Opcode },
3352     { "pcmpgtq", { XM, EXx } },
3353   },
3354
3355   /* PREFIX_0F3838 */
3356   {
3357     { Bad_Opcode },
3358     { Bad_Opcode },
3359     { "pminsb", { XM, EXx } },
3360   },
3361
3362   /* PREFIX_0F3839 */
3363   {
3364     { Bad_Opcode },
3365     { Bad_Opcode },
3366     { "pminsd", { XM, EXx } },
3367   },
3368
3369   /* PREFIX_0F383A */
3370   {
3371     { Bad_Opcode },
3372     { Bad_Opcode },
3373     { "pminuw", { XM, EXx } },
3374   },
3375
3376   /* PREFIX_0F383B */
3377   {
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { "pminud", { XM, EXx } },
3381   },
3382
3383   /* PREFIX_0F383C */
3384   {
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { "pmaxsb", { XM, EXx } },
3388   },
3389
3390   /* PREFIX_0F383D */
3391   {
3392     { Bad_Opcode },
3393     { Bad_Opcode },
3394     { "pmaxsd", { XM, EXx } },
3395   },
3396
3397   /* PREFIX_0F383E */
3398   {
3399     { Bad_Opcode },
3400     { Bad_Opcode },
3401     { "pmaxuw", { XM, EXx } },
3402   },
3403
3404   /* PREFIX_0F383F */
3405   {
3406     { Bad_Opcode },
3407     { Bad_Opcode },
3408     { "pmaxud", { XM, EXx } },
3409   },
3410
3411   /* PREFIX_0F3840 */
3412   {
3413     { Bad_Opcode },
3414     { Bad_Opcode },
3415     { "pmulld", { XM, EXx } },
3416   },
3417
3418   /* PREFIX_0F3841 */
3419   {
3420     { Bad_Opcode },
3421     { Bad_Opcode },
3422     { "phminposuw", { XM, EXx } },
3423   },
3424
3425   /* PREFIX_0F3880 */
3426   {
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { "invept", { Gm, Mo } },
3430   },
3431
3432   /* PREFIX_0F3881 */
3433   {
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { "invvpid", { Gm, Mo } },
3437   },
3438
3439   /* PREFIX_0F3882 */
3440   {
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { "invpcid", { Gm, M } },
3444   },
3445
3446   /* PREFIX_0F38DB */
3447   {
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { "aesimc", { XM, EXx } },
3451   },
3452
3453   /* PREFIX_0F38DC */
3454   {
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { "aesenc", { XM, EXx } },
3458   },
3459
3460   /* PREFIX_0F38DD */
3461   {
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { "aesenclast", { XM, EXx } },
3465   },
3466
3467   /* PREFIX_0F38DE */
3468   {
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { "aesdec", { XM, EXx } },
3472   },
3473
3474   /* PREFIX_0F38DF */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { "aesdeclast", { XM, EXx } },
3479   },
3480
3481   /* PREFIX_0F38F0 */
3482   {
3483     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3484     { Bad_Opcode },
3485     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3486     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3487   },
3488
3489   /* PREFIX_0F38F1 */
3490   {
3491     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3492     { Bad_Opcode },
3493     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3494     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3495   },
3496
3497   /* PREFIX_0F38F6 */
3498   {
3499     { Bad_Opcode },
3500     { "adoxS",  { Gdq, Edq} },
3501     { "adcxS",  { Gdq, Edq} },
3502     { Bad_Opcode },
3503   },
3504
3505   /* PREFIX_0F3A08 */
3506   {
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { "roundps", { XM, EXx, Ib } },
3510   },
3511
3512   /* PREFIX_0F3A09 */
3513   {
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { "roundpd", { XM, EXx, Ib } },
3517   },
3518
3519   /* PREFIX_0F3A0A */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { "roundss", { XM, EXd, Ib } },
3524   },
3525
3526   /* PREFIX_0F3A0B */
3527   {
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { "roundsd", { XM, EXq, Ib } },
3531   },
3532
3533   /* PREFIX_0F3A0C */
3534   {
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { "blendps", { XM, EXx, Ib } },
3538   },
3539
3540   /* PREFIX_0F3A0D */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { "blendpd", { XM, EXx, Ib } },
3545   },
3546
3547   /* PREFIX_0F3A0E */
3548   {
3549     { Bad_Opcode },
3550     { Bad_Opcode },
3551     { "pblendw", { XM, EXx, Ib } },
3552   },
3553
3554   /* PREFIX_0F3A14 */
3555   {
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558     { "pextrb", { Edqb, XM, Ib } },
3559   },
3560
3561   /* PREFIX_0F3A15 */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { "pextrw", { Edqw, XM, Ib } },
3566   },
3567
3568   /* PREFIX_0F3A16 */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { "pextrK", { Edq, XM, Ib } },
3573   },
3574
3575   /* PREFIX_0F3A17 */
3576   {
3577     { Bad_Opcode },
3578     { Bad_Opcode },
3579     { "extractps", { Edqd, XM, Ib } },
3580   },
3581
3582   /* PREFIX_0F3A20 */
3583   {
3584     { Bad_Opcode },
3585     { Bad_Opcode },
3586     { "pinsrb", { XM, Edqb, Ib } },
3587   },
3588
3589   /* PREFIX_0F3A21 */
3590   {
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { "insertps", { XM, EXd, Ib } },
3594   },
3595
3596   /* PREFIX_0F3A22 */
3597   {
3598     { Bad_Opcode },
3599     { Bad_Opcode },
3600     { "pinsrK", { XM, Edq, Ib } },
3601   },
3602
3603   /* PREFIX_0F3A40 */
3604   {
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607     { "dpps",   { XM, EXx, Ib } },
3608   },
3609
3610   /* PREFIX_0F3A41 */
3611   {
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { "dppd",   { XM, EXx, Ib } },
3615   },
3616
3617   /* PREFIX_0F3A42 */
3618   {
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { "mpsadbw", { XM, EXx, Ib } },
3622   },
3623
3624   /* PREFIX_0F3A44 */
3625   {
3626     { Bad_Opcode },
3627     { Bad_Opcode },
3628     { "pclmulqdq", { XM, EXx, PCLMUL } },
3629   },
3630
3631   /* PREFIX_0F3A60 */
3632   {
3633     { Bad_Opcode },
3634     { Bad_Opcode },
3635     { "pcmpestrm", { XM, EXx, Ib } },
3636   },
3637
3638   /* PREFIX_0F3A61 */
3639   {
3640     { Bad_Opcode },
3641     { Bad_Opcode },
3642     { "pcmpestri", { XM, EXx, Ib } },
3643   },
3644
3645   /* PREFIX_0F3A62 */
3646   {
3647     { Bad_Opcode },
3648     { Bad_Opcode },
3649     { "pcmpistrm", { XM, EXx, Ib } },
3650   },
3651
3652   /* PREFIX_0F3A63 */
3653   {
3654     { Bad_Opcode },
3655     { Bad_Opcode },
3656     { "pcmpistri", { XM, EXx, Ib } },
3657   },
3658
3659   /* PREFIX_0F3ADF */
3660   {
3661     { Bad_Opcode },
3662     { Bad_Opcode },
3663     { "aeskeygenassist", { XM, EXx, Ib } },
3664   },
3665
3666   /* PREFIX_VEX_0F10 */
3667   {
3668     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3669     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3670     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3671     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3672   },
3673
3674   /* PREFIX_VEX_0F11 */
3675   {
3676     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3677     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3678     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3679     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3680   },
3681
3682   /* PREFIX_VEX_0F12 */
3683   {
3684     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3685     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3686     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3687     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3688   },
3689
3690   /* PREFIX_VEX_0F16 */
3691   {
3692     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3693     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3694     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3695   },
3696
3697   /* PREFIX_VEX_0F2A */
3698   {
3699     { Bad_Opcode },
3700     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3701     { Bad_Opcode },
3702     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3703   },
3704
3705   /* PREFIX_VEX_0F2C */
3706   {
3707     { Bad_Opcode },
3708     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3709     { Bad_Opcode },
3710     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3711   },
3712
3713   /* PREFIX_VEX_0F2D */
3714   {
3715     { Bad_Opcode },
3716     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3717     { Bad_Opcode },
3718     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3719   },
3720
3721   /* PREFIX_VEX_0F2E */
3722   {
3723     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3724     { Bad_Opcode },
3725     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3726   },
3727
3728   /* PREFIX_VEX_0F2F */
3729   {
3730     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3731     { Bad_Opcode },
3732     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3733   },
3734
3735   /* PREFIX_VEX_0F51 */
3736   {
3737     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3738     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3739     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3740     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3741   },
3742
3743   /* PREFIX_VEX_0F52 */
3744   {
3745     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3746     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3747   },
3748
3749   /* PREFIX_VEX_0F53 */
3750   {
3751     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3752     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3753   },
3754
3755   /* PREFIX_VEX_0F58 */
3756   {
3757     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3758     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3759     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3760     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3761   },
3762
3763   /* PREFIX_VEX_0F59 */
3764   {
3765     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3766     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3767     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3768     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3769   },
3770
3771   /* PREFIX_VEX_0F5A */
3772   {
3773     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3774     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3775     { "vcvtpd2ps%XY", { XMM, EXx } },
3776     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3777   },
3778
3779   /* PREFIX_VEX_0F5B */
3780   {
3781     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3782     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3783     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3784   },
3785
3786   /* PREFIX_VEX_0F5C */
3787   {
3788     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3789     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3790     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3791     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3792   },
3793
3794   /* PREFIX_VEX_0F5D */
3795   {
3796     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3797     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3798     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3799     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3800   },
3801
3802   /* PREFIX_VEX_0F5E */
3803   {
3804     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3805     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3806     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3807     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3808   },
3809
3810   /* PREFIX_VEX_0F5F */
3811   {
3812     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3813     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3814     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3815     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3816   },
3817
3818   /* PREFIX_VEX_0F60 */
3819   {
3820     { Bad_Opcode },
3821     { Bad_Opcode },
3822     { VEX_W_TABLE (VEX_W_0F60_P_2) },
3823   },
3824
3825   /* PREFIX_VEX_0F61 */
3826   {
3827     { Bad_Opcode },
3828     { Bad_Opcode },
3829     { VEX_W_TABLE (VEX_W_0F61_P_2) },
3830   },
3831
3832   /* PREFIX_VEX_0F62 */
3833   {
3834     { Bad_Opcode },
3835     { Bad_Opcode },
3836     { VEX_W_TABLE (VEX_W_0F62_P_2) },
3837   },
3838
3839   /* PREFIX_VEX_0F63 */
3840   {
3841     { Bad_Opcode },
3842     { Bad_Opcode },
3843     { VEX_W_TABLE (VEX_W_0F63_P_2) },
3844   },
3845
3846   /* PREFIX_VEX_0F64 */
3847   {
3848     { Bad_Opcode },
3849     { Bad_Opcode },
3850     { VEX_W_TABLE (VEX_W_0F64_P_2) },
3851   },
3852
3853   /* PREFIX_VEX_0F65 */
3854   {
3855     { Bad_Opcode },
3856     { Bad_Opcode },
3857     { VEX_W_TABLE (VEX_W_0F65_P_2) },
3858   },
3859
3860   /* PREFIX_VEX_0F66 */
3861   {
3862     { Bad_Opcode },
3863     { Bad_Opcode },
3864     { VEX_W_TABLE (VEX_W_0F66_P_2) },
3865   },
3866
3867   /* PREFIX_VEX_0F67 */
3868   {
3869     { Bad_Opcode },
3870     { Bad_Opcode },
3871     { VEX_W_TABLE (VEX_W_0F67_P_2) },
3872   },
3873
3874   /* PREFIX_VEX_0F68 */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { VEX_W_TABLE (VEX_W_0F68_P_2) },
3879   },
3880
3881   /* PREFIX_VEX_0F69 */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { VEX_W_TABLE (VEX_W_0F69_P_2) },
3886   },
3887
3888   /* PREFIX_VEX_0F6A */
3889   {
3890     { Bad_Opcode },
3891     { Bad_Opcode },
3892     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3893   },
3894
3895   /* PREFIX_VEX_0F6B */
3896   {
3897     { Bad_Opcode },
3898     { Bad_Opcode },
3899     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3900   },
3901
3902   /* PREFIX_VEX_0F6C */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3907   },
3908
3909   /* PREFIX_VEX_0F6D */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3914   },
3915
3916   /* PREFIX_VEX_0F6E */
3917   {
3918     { Bad_Opcode },
3919     { Bad_Opcode },
3920     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3921   },
3922
3923   /* PREFIX_VEX_0F6F */
3924   {
3925     { Bad_Opcode },
3926     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3927     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3928   },
3929
3930   /* PREFIX_VEX_0F70 */
3931   {
3932     { Bad_Opcode },
3933     { VEX_W_TABLE (VEX_W_0F70_P_1) },
3934     { VEX_W_TABLE (VEX_W_0F70_P_2) },
3935     { VEX_W_TABLE (VEX_W_0F70_P_3) },
3936   },
3937
3938   /* PREFIX_VEX_0F71_REG_2 */
3939   {
3940     { Bad_Opcode },
3941     { Bad_Opcode },
3942     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3943   },
3944
3945   /* PREFIX_VEX_0F71_REG_4 */
3946   {
3947     { Bad_Opcode },
3948     { Bad_Opcode },
3949     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
3950   },
3951
3952   /* PREFIX_VEX_0F71_REG_6 */
3953   {
3954     { Bad_Opcode },
3955     { Bad_Opcode },
3956     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
3957   },
3958
3959   /* PREFIX_VEX_0F72_REG_2 */
3960   {
3961     { Bad_Opcode },
3962     { Bad_Opcode },
3963     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
3964   },
3965
3966   /* PREFIX_VEX_0F72_REG_4 */
3967   {
3968     { Bad_Opcode },
3969     { Bad_Opcode },
3970     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
3971   },
3972
3973   /* PREFIX_VEX_0F72_REG_6 */
3974   {
3975     { Bad_Opcode },
3976     { Bad_Opcode },
3977     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
3978   },
3979
3980   /* PREFIX_VEX_0F73_REG_2 */
3981   {
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
3985   },
3986
3987   /* PREFIX_VEX_0F73_REG_3 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
3992   },
3993
3994   /* PREFIX_VEX_0F73_REG_6 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
3999   },
4000
4001   /* PREFIX_VEX_0F73_REG_7 */
4002   {
4003     { Bad_Opcode },
4004     { Bad_Opcode },
4005     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4006   },
4007
4008   /* PREFIX_VEX_0F74 */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4013   },
4014
4015   /* PREFIX_VEX_0F75 */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4020   },
4021
4022   /* PREFIX_VEX_0F76 */
4023   {
4024     { Bad_Opcode },
4025     { Bad_Opcode },
4026     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4027   },
4028
4029   /* PREFIX_VEX_0F77 */
4030   {
4031     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4032   },
4033
4034   /* PREFIX_VEX_0F7C */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4039     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4040   },
4041
4042   /* PREFIX_VEX_0F7D */
4043   {
4044     { Bad_Opcode },
4045     { Bad_Opcode },
4046     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4047     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4048   },
4049
4050   /* PREFIX_VEX_0F7E */
4051   {
4052     { Bad_Opcode },
4053     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4054     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4055   },
4056
4057   /* PREFIX_VEX_0F7F */
4058   {
4059     { Bad_Opcode },
4060     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4061     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4062   },
4063
4064   /* PREFIX_VEX_0FC2 */
4065   {
4066     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4067     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4068     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4069     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4070   },
4071
4072   /* PREFIX_VEX_0FC4 */
4073   {
4074     { Bad_Opcode },
4075     { Bad_Opcode },
4076     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4077   },
4078
4079   /* PREFIX_VEX_0FC5 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4084   },
4085
4086   /* PREFIX_VEX_0FD0 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4091     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4092   },
4093
4094   /* PREFIX_VEX_0FD1 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4099   },
4100
4101   /* PREFIX_VEX_0FD2 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4106   },
4107
4108   /* PREFIX_VEX_0FD3 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4113   },
4114
4115   /* PREFIX_VEX_0FD4 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4120   },
4121
4122   /* PREFIX_VEX_0FD5 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4127   },
4128
4129   /* PREFIX_VEX_0FD6 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4134   },
4135
4136   /* PREFIX_VEX_0FD7 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4141   },
4142
4143   /* PREFIX_VEX_0FD8 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4148   },
4149
4150   /* PREFIX_VEX_0FD9 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4155   },
4156
4157   /* PREFIX_VEX_0FDA */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4162   },
4163
4164   /* PREFIX_VEX_0FDB */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4169   },
4170
4171   /* PREFIX_VEX_0FDC */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4176   },
4177
4178   /* PREFIX_VEX_0FDD */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4183   },
4184
4185   /* PREFIX_VEX_0FDE */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4190   },
4191
4192   /* PREFIX_VEX_0FDF */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4197   },
4198
4199   /* PREFIX_VEX_0FE0 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4204   },
4205
4206   /* PREFIX_VEX_0FE1 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4211   },
4212
4213   /* PREFIX_VEX_0FE2 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4218   },
4219
4220   /* PREFIX_VEX_0FE3 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4225   },
4226
4227   /* PREFIX_VEX_0FE4 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4232   },
4233
4234   /* PREFIX_VEX_0FE5 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4239   },
4240
4241   /* PREFIX_VEX_0FE6 */
4242   {
4243     { Bad_Opcode },
4244     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4245     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4246     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4247   },
4248
4249   /* PREFIX_VEX_0FE7 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4254   },
4255
4256   /* PREFIX_VEX_0FE8 */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4261   },
4262
4263   /* PREFIX_VEX_0FE9 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4268   },
4269
4270   /* PREFIX_VEX_0FEA */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4275   },
4276
4277   /* PREFIX_VEX_0FEB */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4282   },
4283
4284   /* PREFIX_VEX_0FEC */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4289   },
4290
4291   /* PREFIX_VEX_0FED */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { VEX_W_TABLE (VEX_W_0FED_P_2) },
4296   },
4297
4298   /* PREFIX_VEX_0FEE */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4303   },
4304
4305   /* PREFIX_VEX_0FEF */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4310   },
4311
4312   /* PREFIX_VEX_0FF0 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4318   },
4319
4320   /* PREFIX_VEX_0FF1 */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4325   },
4326
4327   /* PREFIX_VEX_0FF2 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4332   },
4333
4334   /* PREFIX_VEX_0FF3 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4339   },
4340
4341   /* PREFIX_VEX_0FF4 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4346   },
4347
4348   /* PREFIX_VEX_0FF5 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4353   },
4354
4355   /* PREFIX_VEX_0FF6 */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4360   },
4361
4362   /* PREFIX_VEX_0FF7 */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4367   },
4368
4369   /* PREFIX_VEX_0FF8 */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4374   },
4375
4376   /* PREFIX_VEX_0FF9 */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4381   },
4382
4383   /* PREFIX_VEX_0FFA */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4388   },
4389
4390   /* PREFIX_VEX_0FFB */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4395   },
4396
4397   /* PREFIX_VEX_0FFC */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4402   },
4403
4404   /* PREFIX_VEX_0FFD */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4409   },
4410
4411   /* PREFIX_VEX_0FFE */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4416   },
4417
4418   /* PREFIX_VEX_0F3800 */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4423   },
4424
4425   /* PREFIX_VEX_0F3801 */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4430   },
4431
4432   /* PREFIX_VEX_0F3802 */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4437   },
4438
4439   /* PREFIX_VEX_0F3803 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4444   },
4445
4446   /* PREFIX_VEX_0F3804 */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4451   },
4452
4453   /* PREFIX_VEX_0F3805 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4458   },
4459
4460   /* PREFIX_VEX_0F3806 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4465   },
4466
4467   /* PREFIX_VEX_0F3807 */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4472   },
4473
4474   /* PREFIX_VEX_0F3808 */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4479   },
4480
4481   /* PREFIX_VEX_0F3809 */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4486   },
4487
4488   /* PREFIX_VEX_0F380A */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4493   },
4494
4495   /* PREFIX_VEX_0F380B */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4500   },
4501
4502   /* PREFIX_VEX_0F380C */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4507   },
4508
4509   /* PREFIX_VEX_0F380D */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4514   },
4515
4516   /* PREFIX_VEX_0F380E */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4521   },
4522
4523   /* PREFIX_VEX_0F380F */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4528   },
4529
4530   /* PREFIX_VEX_0F3813 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "vcvtph2ps", { XM, EXxmmq } },
4535   },
4536
4537   /* PREFIX_VEX_0F3816 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4542   },
4543
4544   /* PREFIX_VEX_0F3817 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4549   },
4550
4551   /* PREFIX_VEX_0F3818 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4556   },
4557
4558   /* PREFIX_VEX_0F3819 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4563   },
4564
4565   /* PREFIX_VEX_0F381A */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4570   },
4571
4572   /* PREFIX_VEX_0F381C */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4577   },
4578
4579   /* PREFIX_VEX_0F381D */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4584   },
4585
4586   /* PREFIX_VEX_0F381E */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4591   },
4592
4593   /* PREFIX_VEX_0F3820 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4598   },
4599
4600   /* PREFIX_VEX_0F3821 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4605   },
4606
4607   /* PREFIX_VEX_0F3822 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4612   },
4613
4614   /* PREFIX_VEX_0F3823 */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4619   },
4620
4621   /* PREFIX_VEX_0F3824 */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4626   },
4627
4628   /* PREFIX_VEX_0F3825 */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F3828 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4640   },
4641
4642   /* PREFIX_VEX_0F3829 */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4647   },
4648
4649   /* PREFIX_VEX_0F382A */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4654   },
4655
4656   /* PREFIX_VEX_0F382B */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4661   },
4662
4663   /* PREFIX_VEX_0F382C */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F382D */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F382E */
4678   {
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4682   },
4683
4684   /* PREFIX_VEX_0F382F */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4689   },
4690
4691   /* PREFIX_VEX_0F3830 */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4696   },
4697
4698   /* PREFIX_VEX_0F3831 */
4699   {
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4703   },
4704
4705   /* PREFIX_VEX_0F3832 */
4706   {
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4710   },
4711
4712   /* PREFIX_VEX_0F3833 */
4713   {
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4717   },
4718
4719   /* PREFIX_VEX_0F3834 */
4720   {
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4724   },
4725
4726   /* PREFIX_VEX_0F3835 */
4727   {
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4731   },
4732
4733   /* PREFIX_VEX_0F3836 */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4738   },
4739
4740   /* PREFIX_VEX_0F3837 */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F3838 */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F3839 */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F383A */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F383B */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F383C */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F383D */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F383E */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4794   },
4795
4796   /* PREFIX_VEX_0F383F */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4801   },
4802
4803   /* PREFIX_VEX_0F3840 */
4804   {
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4808   },
4809
4810   /* PREFIX_VEX_0F3841 */
4811   {
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4815   },
4816
4817   /* PREFIX_VEX_0F3845 */
4818   {
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { "vpsrlv%LW", { XM, Vex, EXx } },
4822   },
4823
4824   /* PREFIX_VEX_0F3846 */
4825   {
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4829   },
4830
4831   /* PREFIX_VEX_0F3847 */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { "vpsllv%LW", { XM, Vex, EXx } },
4836   },
4837
4838   /* PREFIX_VEX_0F3858 */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4843   },
4844
4845   /* PREFIX_VEX_0F3859 */
4846   {
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4850   },
4851
4852   /* PREFIX_VEX_0F385A */
4853   {
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4857   },
4858
4859   /* PREFIX_VEX_0F3878 */
4860   {
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4864   },
4865
4866   /* PREFIX_VEX_0F3879 */
4867   {
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4871   },
4872
4873   /* PREFIX_VEX_0F388C */
4874   {
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4878   },
4879
4880   /* PREFIX_VEX_0F388E */
4881   {
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4885   },
4886
4887   /* PREFIX_VEX_0F3890 */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4892   },
4893
4894   /* PREFIX_VEX_0F3891 */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4899   },
4900
4901   /* PREFIX_VEX_0F3892 */
4902   {
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4906   },
4907
4908   /* PREFIX_VEX_0F3893 */
4909   {
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4913   },
4914
4915   /* PREFIX_VEX_0F3896 */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4920   },
4921
4922   /* PREFIX_VEX_0F3897 */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4927   },
4928
4929   /* PREFIX_VEX_0F3898 */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { "vfmadd132p%XW", { XM, Vex, EXx } },
4934   },
4935
4936   /* PREFIX_VEX_0F3899 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4941   },
4942
4943   /* PREFIX_VEX_0F389A */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { "vfmsub132p%XW", { XM, Vex, EXx } },
4948   },
4949
4950   /* PREFIX_VEX_0F389B */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4955   },
4956
4957   /* PREFIX_VEX_0F389C */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4962   },
4963
4964   /* PREFIX_VEX_0F389D */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4969   },
4970
4971   /* PREFIX_VEX_0F389E */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4976   },
4977
4978   /* PREFIX_VEX_0F389F */
4979   {
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4983   },
4984
4985   /* PREFIX_VEX_0F38A6 */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4990     { Bad_Opcode },
4991   },
4992
4993   /* PREFIX_VEX_0F38A7 */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4998   },
4999
5000   /* PREFIX_VEX_0F38A8 */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { "vfmadd213p%XW", { XM, Vex, EXx } },
5005   },
5006
5007   /* PREFIX_VEX_0F38A9 */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5012   },
5013
5014   /* PREFIX_VEX_0F38AA */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { "vfmsub213p%XW", { XM, Vex, EXx } },
5019   },
5020
5021   /* PREFIX_VEX_0F38AB */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5026   },
5027
5028   /* PREFIX_VEX_0F38AC */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5033   },
5034
5035   /* PREFIX_VEX_0F38AD */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5040   },
5041
5042   /* PREFIX_VEX_0F38AE */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5047   },
5048
5049   /* PREFIX_VEX_0F38AF */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5054   },
5055
5056   /* PREFIX_VEX_0F38B6 */
5057   {
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5061   },
5062
5063   /* PREFIX_VEX_0F38B7 */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5068   },
5069
5070   /* PREFIX_VEX_0F38B8 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { "vfmadd231p%XW", { XM, Vex, EXx } },
5075   },
5076
5077   /* PREFIX_VEX_0F38B9 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5082   },
5083
5084   /* PREFIX_VEX_0F38BA */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { "vfmsub231p%XW", { XM, Vex, EXx } },
5089   },
5090
5091   /* PREFIX_VEX_0F38BB */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5096   },
5097
5098   /* PREFIX_VEX_0F38BC */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5103   },
5104
5105   /* PREFIX_VEX_0F38BD */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5110   },
5111
5112   /* PREFIX_VEX_0F38BE */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5117   },
5118
5119   /* PREFIX_VEX_0F38BF */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5124   },
5125
5126   /* PREFIX_VEX_0F38DB */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0F38DC */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5138   },
5139
5140   /* PREFIX_VEX_0F38DD */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0F38DE */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0F38DF */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F38F2 */
5162   {
5163     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5164   },
5165
5166   /* PREFIX_VEX_0F38F3_REG_1 */
5167   {
5168     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5169   },
5170
5171   /* PREFIX_VEX_0F38F3_REG_2 */
5172   {
5173     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5174   },
5175
5176   /* PREFIX_VEX_0F38F3_REG_3 */
5177   {
5178     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5179   },
5180
5181   /* PREFIX_VEX_0F38F5 */
5182   {
5183     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5184     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5185     { Bad_Opcode },
5186     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5187   },
5188
5189   /* PREFIX_VEX_0F38F6 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5195   },
5196
5197   /* PREFIX_VEX_0F38F7 */
5198   {
5199     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5200     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5201     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5202     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5203   },
5204
5205   /* PREFIX_VEX_0F3A00 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F3A01 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F3A02 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F3A04 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0F3A05 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0F3A06 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0F3A08 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5252   },
5253
5254   /* PREFIX_VEX_0F3A09 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5259   },
5260
5261   /* PREFIX_VEX_0F3A0A */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5266   },
5267
5268   /* PREFIX_VEX_0F3A0B */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0F3A0C */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0F3A0D */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5287   },
5288
5289   /* PREFIX_VEX_0F3A0E */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5294   },
5295
5296   /* PREFIX_VEX_0F3A0F */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0F3A14 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0F3A15 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0F3A16 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0F3A17 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0F3A18 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0F3A19 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0F3A1D */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5350   },
5351
5352   /* PREFIX_VEX_0F3A20 */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5357   },
5358
5359   /* PREFIX_VEX_0F3A21 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5364   },
5365
5366   /* PREFIX_VEX_0F3A22 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5371   },
5372
5373   /* PREFIX_VEX_0F3A38 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0F3A39 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0F3A40 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0F3A41 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0F3A42 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0F3A44 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0F3A46 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0F3A48 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0F3A49 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0F3A4A */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5441   },
5442
5443   /* PREFIX_VEX_0F3A4B */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0F3A4C */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0F3A5C */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5462   },
5463
5464   /* PREFIX_VEX_0F3A5D */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5469   },
5470
5471   /* PREFIX_VEX_0F3A5E */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5476   },
5477
5478   /* PREFIX_VEX_0F3A5F */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5483   },
5484
5485   /* PREFIX_VEX_0F3A60 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5490     { Bad_Opcode },
5491   },
5492
5493   /* PREFIX_VEX_0F3A61 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0F3A62 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0F3A63 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0F3A68 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5519   },
5520
5521   /* PREFIX_VEX_0F3A69 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5526   },
5527
5528   /* PREFIX_VEX_0F3A6A */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0F3A6B */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0F3A6C */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5547   },
5548
5549   /* PREFIX_VEX_0F3A6D */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5554   },
5555
5556   /* PREFIX_VEX_0F3A6E */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F3A6F */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F3A78 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5575   },
5576
5577   /* PREFIX_VEX_0F3A79 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5582   },
5583
5584   /* PREFIX_VEX_0F3A7A */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3A7B */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3A7C */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5603     { Bad_Opcode },
5604   },
5605
5606   /* PREFIX_VEX_0F3A7D */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5611   },
5612
5613   /* PREFIX_VEX_0F3A7E */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F3A7F */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F3ADF */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F3AF0 */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5640   },
5641 };
5642
5643 static const struct dis386 x86_64_table[][2] = {
5644   /* X86_64_06 */
5645   {
5646     { "pushP", { es } },
5647   },
5648
5649   /* X86_64_07 */
5650   {
5651     { "popP", { es } },
5652   },
5653
5654   /* X86_64_0D */
5655   {
5656     { "pushP", { cs } },
5657   },
5658
5659   /* X86_64_16 */
5660   {
5661     { "pushP", { ss } },
5662   },
5663
5664   /* X86_64_17 */
5665   {
5666     { "popP", { ss } },
5667   },
5668
5669   /* X86_64_1E */
5670   {
5671     { "pushP", { ds } },
5672   },
5673
5674   /* X86_64_1F */
5675   {
5676     { "popP", { ds } },
5677   },
5678
5679   /* X86_64_27 */
5680   {
5681     { "daa", { XX } },
5682   },
5683
5684   /* X86_64_2F */
5685   {
5686     { "das", { XX } },
5687   },
5688
5689   /* X86_64_37 */
5690   {
5691     { "aaa", { XX } },
5692   },
5693
5694   /* X86_64_3F */
5695   {
5696     { "aas", { XX } },
5697   },
5698
5699   /* X86_64_60 */
5700   {
5701     { "pushaP", { XX } },
5702   },
5703
5704   /* X86_64_61 */
5705   {
5706     { "popaP", { XX } },
5707   },
5708
5709   /* X86_64_62 */
5710   {
5711     { MOD_TABLE (MOD_62_32BIT) },
5712   },
5713
5714   /* X86_64_63 */
5715   {
5716     { "arpl", { Ew, Gw } },
5717     { "movs{lq|xd}", { Gv, Ed } },
5718   },
5719
5720   /* X86_64_6D */
5721   {
5722     { "ins{R|}", { Yzr, indirDX } },
5723     { "ins{G|}", { Yzr, indirDX } },
5724   },
5725
5726   /* X86_64_6F */
5727   {
5728     { "outs{R|}", { indirDXr, Xz } },
5729     { "outs{G|}", { indirDXr, Xz } },
5730   },
5731
5732   /* X86_64_9A */
5733   {
5734     { "Jcall{T|}", { Ap } },
5735   },
5736
5737   /* X86_64_C4 */
5738   {
5739     { MOD_TABLE (MOD_C4_32BIT) },
5740     { VEX_C4_TABLE (VEX_0F) },
5741   },
5742
5743   /* X86_64_C5 */
5744   {
5745     { MOD_TABLE (MOD_C5_32BIT) },
5746     { VEX_C5_TABLE (VEX_0F) },
5747   },
5748
5749   /* X86_64_CE */
5750   {
5751     { "into", { XX } },
5752   },
5753
5754   /* X86_64_D4 */
5755   {
5756     { "aam", { Ib } },
5757   },
5758
5759   /* X86_64_D5 */
5760   {
5761     { "aad", { Ib } },
5762   },
5763
5764   /* X86_64_EA */
5765   {
5766     { "Jjmp{T|}", { Ap } },
5767   },
5768
5769   /* X86_64_0F01_REG_0 */
5770   {
5771     { "sgdt{Q|IQ}", { M } },
5772     { "sgdt", { M } },
5773   },
5774
5775   /* X86_64_0F01_REG_1 */
5776   {
5777     { "sidt{Q|IQ}", { M } },
5778     { "sidt", { M } },
5779   },
5780
5781   /* X86_64_0F01_REG_2 */
5782   {
5783     { "lgdt{Q|Q}", { M } },
5784     { "lgdt", { M } },
5785   },
5786
5787   /* X86_64_0F01_REG_3 */
5788   {
5789     { "lidt{Q|Q}", { M } },
5790     { "lidt", { M } },
5791   },
5792 };
5793
5794 static const struct dis386 three_byte_table[][256] = {
5795
5796   /* THREE_BYTE_0F38 */
5797   {
5798     /* 00 */
5799     { "pshufb",         { MX, EM } },
5800     { "phaddw",         { MX, EM } },
5801     { "phaddd",         { MX, EM } },
5802     { "phaddsw",        { MX, EM } },
5803     { "pmaddubsw",      { MX, EM } },
5804     { "phsubw",         { MX, EM } },
5805     { "phsubd",         { MX, EM } },
5806     { "phsubsw",        { MX, EM } },
5807     /* 08 */
5808     { "psignb",         { MX, EM } },
5809     { "psignw",         { MX, EM } },
5810     { "psignd",         { MX, EM } },
5811     { "pmulhrsw",       { MX, EM } },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     /* 10 */
5817     { PREFIX_TABLE (PREFIX_0F3810) },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { PREFIX_TABLE (PREFIX_0F3814) },
5822     { PREFIX_TABLE (PREFIX_0F3815) },
5823     { Bad_Opcode },
5824     { PREFIX_TABLE (PREFIX_0F3817) },
5825     /* 18 */
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { "pabsb",          { MX, EM } },
5831     { "pabsw",          { MX, EM } },
5832     { "pabsd",          { MX, EM } },
5833     { Bad_Opcode },
5834     /* 20 */
5835     { PREFIX_TABLE (PREFIX_0F3820) },
5836     { PREFIX_TABLE (PREFIX_0F3821) },
5837     { PREFIX_TABLE (PREFIX_0F3822) },
5838     { PREFIX_TABLE (PREFIX_0F3823) },
5839     { PREFIX_TABLE (PREFIX_0F3824) },
5840     { PREFIX_TABLE (PREFIX_0F3825) },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     /* 28 */
5844     { PREFIX_TABLE (PREFIX_0F3828) },
5845     { PREFIX_TABLE (PREFIX_0F3829) },
5846     { PREFIX_TABLE (PREFIX_0F382A) },
5847     { PREFIX_TABLE (PREFIX_0F382B) },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     /* 30 */
5853     { PREFIX_TABLE (PREFIX_0F3830) },
5854     { PREFIX_TABLE (PREFIX_0F3831) },
5855     { PREFIX_TABLE (PREFIX_0F3832) },
5856     { PREFIX_TABLE (PREFIX_0F3833) },
5857     { PREFIX_TABLE (PREFIX_0F3834) },
5858     { PREFIX_TABLE (PREFIX_0F3835) },
5859     { Bad_Opcode },
5860     { PREFIX_TABLE (PREFIX_0F3837) },
5861     /* 38 */
5862     { PREFIX_TABLE (PREFIX_0F3838) },
5863     { PREFIX_TABLE (PREFIX_0F3839) },
5864     { PREFIX_TABLE (PREFIX_0F383A) },
5865     { PREFIX_TABLE (PREFIX_0F383B) },
5866     { PREFIX_TABLE (PREFIX_0F383C) },
5867     { PREFIX_TABLE (PREFIX_0F383D) },
5868     { PREFIX_TABLE (PREFIX_0F383E) },
5869     { PREFIX_TABLE (PREFIX_0F383F) },
5870     /* 40 */
5871     { PREFIX_TABLE (PREFIX_0F3840) },
5872     { PREFIX_TABLE (PREFIX_0F3841) },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     /* 48 */
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     /* 50 */
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     /* 58 */
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     /* 60 */
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     /* 68 */
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     /* 70 */
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     /* 78 */
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     /* 80 */
5943     { PREFIX_TABLE (PREFIX_0F3880) },
5944     { PREFIX_TABLE (PREFIX_0F3881) },
5945     { PREFIX_TABLE (PREFIX_0F3882) },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     /* 88 */
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     /* 90 */
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     /* 98 */
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     /* a0 */
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     /* a8 */
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     /* b0 */
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     /* b8 */
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     /* c0 */
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     /* c8 */
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     /* d0 */
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     /* d8 */
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { PREFIX_TABLE (PREFIX_0F38DB) },
6046     { PREFIX_TABLE (PREFIX_0F38DC) },
6047     { PREFIX_TABLE (PREFIX_0F38DD) },
6048     { PREFIX_TABLE (PREFIX_0F38DE) },
6049     { PREFIX_TABLE (PREFIX_0F38DF) },
6050     /* e0 */
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     /* e8 */
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     /* f0 */
6069     { PREFIX_TABLE (PREFIX_0F38F0) },
6070     { PREFIX_TABLE (PREFIX_0F38F1) },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { PREFIX_TABLE (PREFIX_0F38F6) },
6076     { Bad_Opcode },
6077     /* f8 */
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086   },
6087   /* THREE_BYTE_0F3A */
6088   {
6089     /* 00 */
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     /* 08 */
6099     { PREFIX_TABLE (PREFIX_0F3A08) },
6100     { PREFIX_TABLE (PREFIX_0F3A09) },
6101     { PREFIX_TABLE (PREFIX_0F3A0A) },
6102     { PREFIX_TABLE (PREFIX_0F3A0B) },
6103     { PREFIX_TABLE (PREFIX_0F3A0C) },
6104     { PREFIX_TABLE (PREFIX_0F3A0D) },
6105     { PREFIX_TABLE (PREFIX_0F3A0E) },
6106     { "palignr",        { MX, EM, Ib } },
6107     /* 10 */
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { PREFIX_TABLE (PREFIX_0F3A14) },
6113     { PREFIX_TABLE (PREFIX_0F3A15) },
6114     { PREFIX_TABLE (PREFIX_0F3A16) },
6115     { PREFIX_TABLE (PREFIX_0F3A17) },
6116     /* 18 */
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     /* 20 */
6126     { PREFIX_TABLE (PREFIX_0F3A20) },
6127     { PREFIX_TABLE (PREFIX_0F3A21) },
6128     { PREFIX_TABLE (PREFIX_0F3A22) },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     /* 28 */
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     /* 30 */
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     /* 38 */
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     /* 40 */
6162     { PREFIX_TABLE (PREFIX_0F3A40) },
6163     { PREFIX_TABLE (PREFIX_0F3A41) },
6164     { PREFIX_TABLE (PREFIX_0F3A42) },
6165     { Bad_Opcode },
6166     { PREFIX_TABLE (PREFIX_0F3A44) },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     /* 48 */
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     /* 50 */
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     /* 58 */
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     /* 60 */
6198     { PREFIX_TABLE (PREFIX_0F3A60) },
6199     { PREFIX_TABLE (PREFIX_0F3A61) },
6200     { PREFIX_TABLE (PREFIX_0F3A62) },
6201     { PREFIX_TABLE (PREFIX_0F3A63) },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     /* 68 */
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     /* 70 */
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     /* 78 */
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     /* 80 */
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     /* 88 */
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     /* 90 */
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     /* 98 */
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     /* a0 */
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     /* a8 */
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     /* b0 */
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     /* b8 */
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     /* c0 */
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     /* c8 */
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     /* d0 */
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     /* d8 */
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { PREFIX_TABLE (PREFIX_0F3ADF) },
6341     /* e0 */
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     /* e8 */
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     /* f0 */
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     /* f8 */
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377   },
6378
6379   /* THREE_BYTE_0F7A */
6380   {
6381     /* 00 */
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     /* 08 */
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     /* 10 */
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     /* 18 */
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     /* 20 */
6418     { "ptest",          { XX } },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     /* 28 */
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     /* 30 */
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     /* 38 */
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     /* 40 */
6454     { Bad_Opcode },
6455     { "phaddbw",        { XM, EXq } },
6456     { "phaddbd",        { XM, EXq } },
6457     { "phaddbq",        { XM, EXq } },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { "phaddwd",        { XM, EXq } },
6461     { "phaddwq",        { XM, EXq } },
6462     /* 48 */
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { "phadddq",        { XM, EXq } },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     /* 50 */
6472     { Bad_Opcode },
6473     { "phaddubw",       { XM, EXq } },
6474     { "phaddubd",       { XM, EXq } },
6475     { "phaddubq",       { XM, EXq } },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { "phadduwd",       { XM, EXq } },
6479     { "phadduwq",       { XM, EXq } },
6480     /* 58 */
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { "phaddudq",       { XM, EXq } },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     /* 60 */
6490     { Bad_Opcode },
6491     { "phsubbw",        { XM, EXq } },
6492     { "phsubbd",        { XM, EXq } },
6493     { "phsubbq",        { XM, EXq } },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     /* 68 */
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     /* 70 */
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     /* 78 */
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     /* 80 */
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     /* 88 */
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     /* 90 */
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     /* 98 */
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     /* a0 */
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     /* a8 */
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     /* b0 */
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     /* b8 */
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     /* c0 */
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     /* c8 */
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     /* d0 */
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     /* d8 */
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     /* e0 */
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     /* e8 */
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     /* f0 */
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     /* f8 */
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669   },
6670 };
6671
6672 static const struct dis386 xop_table[][256] = {
6673   /* XOP_08 */
6674   {
6675     /* 00 */
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     /* 08 */
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     /* 10 */
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     /* 18 */
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     /* 20 */
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     /* 28 */
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     /* 30 */
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     /* 38 */
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     /* 40 */
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     /* 48 */
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     /* 50 */
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     /* 58 */
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     /* 60 */
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     /* 68 */
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     /* 70 */
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     /* 78 */
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     /* 80 */
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6826     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6827     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6828     /* 88 */
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6836     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6837     /* 90 */
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6844     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6845     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6846     /* 98 */
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6854     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6855     /* a0 */
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6859     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6863     { Bad_Opcode },
6864     /* a8 */
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     /* b0 */
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6881     { Bad_Opcode },
6882     /* b8 */
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     /* c0 */
6892     { "vprotb",         { XM, Vex_2src_1, Ib } },
6893     { "vprotw",         { XM, Vex_2src_1, Ib } },
6894     { "vprotd",         { XM, Vex_2src_1, Ib } },
6895     { "vprotq",         { XM, Vex_2src_1, Ib } },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     /* c8 */
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
6906     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
6907     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
6908     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
6909     /* d0 */
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     /* d8 */
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     /* e0 */
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     /* e8 */
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
6942     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
6943     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
6944     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
6945     /* f0 */
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     /* f8 */
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963   },
6964   /* XOP_09 */
6965   {
6966     /* 00 */
6967     { Bad_Opcode },
6968     { REG_TABLE (REG_XOP_TBM_01) },
6969     { REG_TABLE (REG_XOP_TBM_02) },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     /* 08 */
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     /* 10 */
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { REG_TABLE (REG_XOP_LWPCB) },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 18 */
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     /* 20 */
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     /* 28 */
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 30 */
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 38 */
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     /* 40 */
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     /* 48 */
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 50 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 58 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 60 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 68 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 70 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 78 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 80 */
7111     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7112     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7113     { "vfrczss",        { XM, EXd } },
7114     { "vfrczsd",        { XM, EXq } },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 88 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 90 */
7129     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7130     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7131     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7132     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7133     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7134     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7135     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7136     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7137     /* 98 */
7138     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7139     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7140     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7141     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* a0 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* a8 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* b0 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* b8 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* c0 */
7183     { Bad_Opcode },
7184     { "vphaddbw",       { XM, EXxmm } },
7185     { "vphaddbd",       { XM, EXxmm } },
7186     { "vphaddbq",       { XM, EXxmm } },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { "vphaddwd",       { XM, EXxmm } },
7190     { "vphaddwq",       { XM, EXxmm } },
7191     /* c8 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { "vphadddq",       { XM, EXxmm } },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* d0 */
7201     { Bad_Opcode },
7202     { "vphaddubw",      { XM, EXxmm } },
7203     { "vphaddubd",      { XM, EXxmm } },
7204     { "vphaddubq",      { XM, EXxmm } },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { "vphadduwd",      { XM, EXxmm } },
7208     { "vphadduwq",      { XM, EXxmm } },
7209     /* d8 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { "vphaddudq",      { XM, EXxmm } },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* e0 */
7219     { Bad_Opcode },
7220     { "vphsubbw",       { XM, EXxmm } },
7221     { "vphsubwd",       { XM, EXxmm } },
7222     { "vphsubdq",       { XM, EXxmm } },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* e8 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* f0 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* f8 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254   },
7255   /* XOP_0A */
7256   {
7257     /* 00 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* 08 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 10 */
7276     { "bextr",  { Gv, Ev, Iq } },
7277     { Bad_Opcode },
7278     { REG_TABLE (REG_XOP_LWP) },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 18 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 20 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 28 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 30 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 38 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 40 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 48 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 50 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 58 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 60 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 68 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 70 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 78 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 80 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 88 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 90 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 98 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* a0 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* a8 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* b0 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* b8 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* c0 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* c8 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* d0 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* d8 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* e0 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* e8 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* f0 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* f8 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545   },
7546 };
7547
7548 static const struct dis386 vex_table[][256] = {
7549   /* VEX_0F */
7550   {
7551     /* 00 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* 08 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 10 */
7570     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7571     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7572     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7573     { MOD_TABLE (MOD_VEX_0F13) },
7574     { VEX_W_TABLE (VEX_W_0F14) },
7575     { VEX_W_TABLE (VEX_W_0F15) },
7576     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7577     { MOD_TABLE (MOD_VEX_0F17) },
7578     /* 18 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 20 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 28 */
7597     { VEX_W_TABLE (VEX_W_0F28) },
7598     { VEX_W_TABLE (VEX_W_0F29) },
7599     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7600     { MOD_TABLE (MOD_VEX_0F2B) },
7601     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7602     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7603     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7604     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7605     /* 30 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 38 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 40 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 48 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 50 */
7642     { MOD_TABLE (MOD_VEX_0F50) },
7643     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7644     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7645     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7646     { "vandpX",         { XM, Vex, EXx } },
7647     { "vandnpX",        { XM, Vex, EXx } },
7648     { "vorpX",          { XM, Vex, EXx } },
7649     { "vxorpX",         { XM, Vex, EXx } },
7650     /* 58 */
7651     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7652     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7653     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7654     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7655     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7656     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7657     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7658     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7659     /* 60 */
7660     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7661     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7662     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7663     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7664     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7665     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7666     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7667     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7668     /* 68 */
7669     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7670     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7671     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7672     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7673     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7674     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7675     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7676     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7677     /* 70 */
7678     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7679     { REG_TABLE (REG_VEX_0F71) },
7680     { REG_TABLE (REG_VEX_0F72) },
7681     { REG_TABLE (REG_VEX_0F73) },
7682     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7683     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7684     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7685     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7686     /* 78 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7692     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7693     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7694     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7695     /* 80 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* 88 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* 90 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* 98 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* a0 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* a8 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { REG_TABLE (REG_VEX_0FAE) },
7748     { Bad_Opcode },
7749     /* b0 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* b8 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* c0 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7771     { Bad_Opcode },
7772     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7773     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7774     { "vshufpX",        { XM, Vex, EXx, Ib } },
7775     { Bad_Opcode },
7776     /* c8 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* d0 */
7786     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7787     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7788     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7789     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7790     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7791     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7792     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7793     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7794     /* d8 */
7795     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7796     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7797     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7798     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7799     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7800     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7801     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7802     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7803     /* e0 */
7804     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7805     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7806     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7807     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7808     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7809     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7810     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7811     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7812     /* e8 */
7813     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7814     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7815     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7816     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7817     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7818     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7819     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7820     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7821     /* f0 */
7822     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7823     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7824     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7825     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7826     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7827     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7828     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7829     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7830     /* f8 */
7831     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7832     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7833     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7834     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7835     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7836     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7837     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7838     { Bad_Opcode },
7839   },
7840   /* VEX_0F38 */
7841   {
7842     /* 00 */
7843     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7844     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7845     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7846     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7847     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7848     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7849     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7850     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7851     /* 08 */
7852     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7853     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7854     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7855     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7856     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7857     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7858     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7859     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7860     /* 10 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7868     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7869     /* 18 */
7870     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7871     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7872     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7873     { Bad_Opcode },
7874     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7875     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7876     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7877     { Bad_Opcode },
7878     /* 20 */
7879     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7880     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7881     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7882     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7883     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7884     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 28 */
7888     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7889     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7890     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7891     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7892     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7893     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7894     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7895     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7896     /* 30 */
7897     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7898     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7899     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7900     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7901     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7902     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7903     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7904     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7905     /* 38 */
7906     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7907     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7908     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7909     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7910     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7911     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7912     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7913     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7914     /* 40 */
7915     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7916     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7921     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7922     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7923     /* 48 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 50 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 58 */
7942     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7943     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7944     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 60 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 68 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 70 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 78 */
7978     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
7979     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 80 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 88 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8001     { Bad_Opcode },
8002     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8003     { Bad_Opcode },
8004     /* 90 */
8005     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8006     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8007     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8008     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8012     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8013     /* 98 */
8014     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8015     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8016     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8017     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8018     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8019     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8020     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8021     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8022     /* a0 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8030     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8031     /* a8 */
8032     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8033     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8034     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8035     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8036     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8037     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8038     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8039     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8040     /* b0 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8048     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8049     /* b8 */
8050     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8051     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8052     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8053     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8054     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8055     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8056     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8057     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8058     /* c0 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* c8 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* d0 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* d8 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8090     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8091     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8092     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8093     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8094     /* e0 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* e8 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* f0 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8116     { REG_TABLE (REG_VEX_0F38F3) },
8117     { Bad_Opcode },
8118     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8119     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8120     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8121     /* f8 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130   },
8131   /* VEX_0F3A */
8132   {
8133     /* 00 */
8134     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8135     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8136     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8137     { Bad_Opcode },
8138     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8139     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8140     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8141     { Bad_Opcode },
8142     /* 08 */
8143     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8144     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8145     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8146     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8147     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8148     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8149     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8150     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8151     /* 10 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8157     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8158     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8159     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8160     /* 18 */
8161     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8162     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 20 */
8170     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8171     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8172     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 28 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 30 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 38 */
8197     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8198     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 40 */
8206     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8207     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8208     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8209     { Bad_Opcode },
8210     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8211     { Bad_Opcode },
8212     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8213     { Bad_Opcode },
8214     /* 48 */
8215     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8216     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8217     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8218     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8219     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 50 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 58 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8238     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8239     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8240     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8241     /* 60 */
8242     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8243     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8244     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8245     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 68 */
8251     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8252     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8253     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8254     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8255     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8256     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8257     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8258     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8259     /* 70 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 78 */
8269     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8270     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8271     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8272     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8273     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8274     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8275     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8276     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8277     /* 80 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 88 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 90 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 98 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* a0 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* a8 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* b0 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* b8 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* c0 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* c8 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* d0 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* d8 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8385     /* e0 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* e8 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* f0 */
8404     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* f8 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421   },
8422 };
8423
8424 static const struct dis386 vex_len_table[][2] = {
8425   /* VEX_LEN_0F10_P_1 */
8426   {
8427     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8428     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8429   },
8430
8431   /* VEX_LEN_0F10_P_3 */
8432   {
8433     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8434     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8435   },
8436
8437   /* VEX_LEN_0F11_P_1 */
8438   {
8439     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8440     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8441   },
8442
8443   /* VEX_LEN_0F11_P_3 */
8444   {
8445     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8446     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8447   },
8448
8449   /* VEX_LEN_0F12_P_0_M_0 */
8450   {
8451     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8452   },
8453
8454   /* VEX_LEN_0F12_P_0_M_1 */
8455   {
8456     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8457   },
8458
8459   /* VEX_LEN_0F12_P_2 */
8460   {
8461     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8462   },
8463
8464   /* VEX_LEN_0F13_M_0 */
8465   {
8466     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8467   },
8468
8469   /* VEX_LEN_0F16_P_0_M_0 */
8470   {
8471     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8472   },
8473
8474   /* VEX_LEN_0F16_P_0_M_1 */
8475   {
8476     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8477   },
8478
8479   /* VEX_LEN_0F16_P_2 */
8480   {
8481     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8482   },
8483
8484   /* VEX_LEN_0F17_M_0 */
8485   {
8486     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8487   },
8488
8489   /* VEX_LEN_0F2A_P_1 */
8490   {
8491     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8492     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8493   },
8494
8495   /* VEX_LEN_0F2A_P_3 */
8496   {
8497     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8498     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8499   },
8500
8501   /* VEX_LEN_0F2C_P_1 */
8502   {
8503     { "vcvttss2siY",    { Gv, EXdScalar } },
8504     { "vcvttss2siY",    { Gv, EXdScalar } },
8505   },
8506
8507   /* VEX_LEN_0F2C_P_3 */
8508   {
8509     { "vcvttsd2siY",    { Gv, EXqScalar } },
8510     { "vcvttsd2siY",    { Gv, EXqScalar } },
8511   },
8512
8513   /* VEX_LEN_0F2D_P_1 */
8514   {
8515     { "vcvtss2siY",     { Gv, EXdScalar } },
8516     { "vcvtss2siY",     { Gv, EXdScalar } },
8517   },
8518
8519   /* VEX_LEN_0F2D_P_3 */
8520   {
8521     { "vcvtsd2siY",     { Gv, EXqScalar } },
8522     { "vcvtsd2siY",     { Gv, EXqScalar } },
8523   },
8524
8525   /* VEX_LEN_0F2E_P_0 */
8526   {
8527     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8528     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8529   },
8530
8531   /* VEX_LEN_0F2E_P_2 */
8532   {
8533     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8534     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8535   },
8536
8537   /* VEX_LEN_0F2F_P_0 */
8538   {
8539     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8540     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8541   },
8542
8543   /* VEX_LEN_0F2F_P_2 */
8544   {
8545     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8546     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8547   },
8548
8549   /* VEX_LEN_0F51_P_1 */
8550   {
8551     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8552     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8553   },
8554
8555   /* VEX_LEN_0F51_P_3 */
8556   {
8557     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8558     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8559   },
8560
8561   /* VEX_LEN_0F52_P_1 */
8562   {
8563     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8564     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8565   },
8566
8567   /* VEX_LEN_0F53_P_1 */
8568   {
8569     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8570     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8571   },
8572
8573   /* VEX_LEN_0F58_P_1 */
8574   {
8575     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8576     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8577   },
8578
8579   /* VEX_LEN_0F58_P_3 */
8580   {
8581     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8582     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8583   },
8584
8585   /* VEX_LEN_0F59_P_1 */
8586   {
8587     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8588     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8589   },
8590
8591   /* VEX_LEN_0F59_P_3 */
8592   {
8593     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8594     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8595   },
8596
8597   /* VEX_LEN_0F5A_P_1 */
8598   {
8599     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8600     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8601   },
8602
8603   /* VEX_LEN_0F5A_P_3 */
8604   {
8605     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8606     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8607   },
8608
8609   /* VEX_LEN_0F5C_P_1 */
8610   {
8611     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8612     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8613   },
8614
8615   /* VEX_LEN_0F5C_P_3 */
8616   {
8617     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8618     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8619   },
8620
8621   /* VEX_LEN_0F5D_P_1 */
8622   {
8623     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8624     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8625   },
8626
8627   /* VEX_LEN_0F5D_P_3 */
8628   {
8629     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8630     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8631   },
8632
8633   /* VEX_LEN_0F5E_P_1 */
8634   {
8635     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8636     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8637   },
8638
8639   /* VEX_LEN_0F5E_P_3 */
8640   {
8641     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8642     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8643   },
8644
8645   /* VEX_LEN_0F5F_P_1 */
8646   {
8647     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8648     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8649   },
8650
8651   /* VEX_LEN_0F5F_P_3 */
8652   {
8653     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8654     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8655   },
8656
8657   /* VEX_LEN_0F6E_P_2 */
8658   {
8659     { "vmovK",          { XMScalar, Edq } },
8660     { "vmovK",          { XMScalar, Edq } },
8661   },
8662
8663   /* VEX_LEN_0F7E_P_1 */
8664   {
8665     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8666     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8667   },
8668
8669   /* VEX_LEN_0F7E_P_2 */
8670   {
8671     { "vmovK",          { Edq, XMScalar } },
8672     { "vmovK",          { Edq, XMScalar } },
8673   },
8674
8675   /* VEX_LEN_0FAE_R_2_M_0 */
8676   {
8677     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8678   },
8679
8680   /* VEX_LEN_0FAE_R_3_M_0 */
8681   {
8682     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8683   },
8684
8685   /* VEX_LEN_0FC2_P_1 */
8686   {
8687     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8688     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8689   },
8690
8691   /* VEX_LEN_0FC2_P_3 */
8692   {
8693     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8694     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8695   },
8696
8697   /* VEX_LEN_0FC4_P_2 */
8698   {
8699     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8700   },
8701
8702   /* VEX_LEN_0FC5_P_2 */
8703   {
8704     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8705   },
8706
8707   /* VEX_LEN_0FD6_P_2 */
8708   {
8709     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8710     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8711   },
8712
8713   /* VEX_LEN_0FF7_P_2 */
8714   {
8715     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8716   },
8717
8718   /* VEX_LEN_0F3816_P_2 */
8719   {
8720     { Bad_Opcode },
8721     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8722   },
8723
8724   /* VEX_LEN_0F3819_P_2 */
8725   {
8726     { Bad_Opcode },
8727     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8728   },
8729
8730   /* VEX_LEN_0F381A_P_2_M_0 */
8731   {
8732     { Bad_Opcode },
8733     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8734   },
8735
8736   /* VEX_LEN_0F3836_P_2 */
8737   {
8738     { Bad_Opcode },
8739     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8740   },
8741
8742   /* VEX_LEN_0F3841_P_2 */
8743   {
8744     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8745   },
8746
8747   /* VEX_LEN_0F385A_P_2_M_0 */
8748   {
8749     { Bad_Opcode },
8750     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8751   },
8752
8753   /* VEX_LEN_0F38DB_P_2 */
8754   {
8755     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8756   },
8757
8758   /* VEX_LEN_0F38DC_P_2 */
8759   {
8760     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8761   },
8762
8763   /* VEX_LEN_0F38DD_P_2 */
8764   {
8765     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8766   },
8767
8768   /* VEX_LEN_0F38DE_P_2 */
8769   {
8770     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8771   },
8772
8773   /* VEX_LEN_0F38DF_P_2 */
8774   {
8775     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8776   },
8777
8778   /* VEX_LEN_0F38F2_P_0 */
8779   {
8780     { "andnS",          { Gdq, VexGdq, Edq } },
8781   },
8782
8783   /* VEX_LEN_0F38F3_R_1_P_0 */
8784   {
8785     { "blsrS",          { VexGdq, Edq } },
8786   },
8787
8788   /* VEX_LEN_0F38F3_R_2_P_0 */
8789   {
8790     { "blsmskS",        { VexGdq, Edq } },
8791   },
8792
8793   /* VEX_LEN_0F38F3_R_3_P_0 */
8794   {
8795     { "blsiS",          { VexGdq, Edq } },
8796   },
8797
8798   /* VEX_LEN_0F38F5_P_0 */
8799   {
8800     { "bzhiS",          { Gdq, Edq, VexGdq } },
8801   },
8802
8803   /* VEX_LEN_0F38F5_P_1 */
8804   {
8805     { "pextS",          { Gdq, VexGdq, Edq } },
8806   },
8807
8808   /* VEX_LEN_0F38F5_P_3 */
8809   {
8810     { "pdepS",          { Gdq, VexGdq, Edq } },
8811   },
8812
8813   /* VEX_LEN_0F38F6_P_3 */
8814   {
8815     { "mulxS",          { Gdq, VexGdq, Edq } },
8816   },
8817
8818   /* VEX_LEN_0F38F7_P_0 */
8819   {
8820     { "bextrS",         { Gdq, Edq, VexGdq } },
8821   },
8822
8823   /* VEX_LEN_0F38F7_P_1 */
8824   {
8825     { "sarxS",          { Gdq, Edq, VexGdq } },
8826   },
8827
8828   /* VEX_LEN_0F38F7_P_2 */
8829   {
8830     { "shlxS",          { Gdq, Edq, VexGdq } },
8831   },
8832
8833   /* VEX_LEN_0F38F7_P_3 */
8834   {
8835     { "shrxS",          { Gdq, Edq, VexGdq } },
8836   },
8837
8838   /* VEX_LEN_0F3A00_P_2 */
8839   {
8840     { Bad_Opcode },
8841     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8842   },
8843
8844   /* VEX_LEN_0F3A01_P_2 */
8845   {
8846     { Bad_Opcode },
8847     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8848   },
8849
8850   /* VEX_LEN_0F3A06_P_2 */
8851   {
8852     { Bad_Opcode },
8853     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8854   },
8855
8856   /* VEX_LEN_0F3A0A_P_2 */
8857   {
8858     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8859     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8860   },
8861
8862   /* VEX_LEN_0F3A0B_P_2 */
8863   {
8864     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8865     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8866   },
8867
8868   /* VEX_LEN_0F3A14_P_2 */
8869   {
8870     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8871   },
8872
8873   /* VEX_LEN_0F3A15_P_2 */
8874   {
8875     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8876   },
8877
8878   /* VEX_LEN_0F3A16_P_2  */
8879   {
8880     { "vpextrK",        { Edq, XM, Ib } },
8881   },
8882
8883   /* VEX_LEN_0F3A17_P_2 */
8884   {
8885     { "vextractps",     { Edqd, XM, Ib } },
8886   },
8887
8888   /* VEX_LEN_0F3A18_P_2 */
8889   {
8890     { Bad_Opcode },
8891     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8892   },
8893
8894   /* VEX_LEN_0F3A19_P_2 */
8895   {
8896     { Bad_Opcode },
8897     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8898   },
8899
8900   /* VEX_LEN_0F3A20_P_2 */
8901   {
8902     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8903   },
8904
8905   /* VEX_LEN_0F3A21_P_2 */
8906   {
8907     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8908   },
8909
8910   /* VEX_LEN_0F3A22_P_2 */
8911   {
8912     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8913   },
8914
8915   /* VEX_LEN_0F3A38_P_2 */
8916   {
8917     { Bad_Opcode },
8918     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8919   },
8920
8921   /* VEX_LEN_0F3A39_P_2 */
8922   {
8923     { Bad_Opcode },
8924     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8925   },
8926
8927   /* VEX_LEN_0F3A41_P_2 */
8928   {
8929     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8930   },
8931
8932   /* VEX_LEN_0F3A44_P_2 */
8933   {
8934     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8935   },
8936
8937   /* VEX_LEN_0F3A46_P_2 */
8938   {
8939     { Bad_Opcode },
8940     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8941   },
8942
8943   /* VEX_LEN_0F3A60_P_2 */
8944   {
8945     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8946   },
8947
8948   /* VEX_LEN_0F3A61_P_2 */
8949   {
8950     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
8951   },
8952
8953   /* VEX_LEN_0F3A62_P_2 */
8954   {
8955     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
8956   },
8957
8958   /* VEX_LEN_0F3A63_P_2 */
8959   {
8960     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
8961   },
8962
8963   /* VEX_LEN_0F3A6A_P_2 */
8964   {
8965     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8966   },
8967
8968   /* VEX_LEN_0F3A6B_P_2 */
8969   {
8970     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8971   },
8972
8973   /* VEX_LEN_0F3A6E_P_2 */
8974   {
8975     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8976   },
8977
8978   /* VEX_LEN_0F3A6F_P_2 */
8979   {
8980     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8981   },
8982
8983   /* VEX_LEN_0F3A7A_P_2 */
8984   {
8985     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8986   },
8987
8988   /* VEX_LEN_0F3A7B_P_2 */
8989   {
8990     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8991   },
8992
8993   /* VEX_LEN_0F3A7E_P_2 */
8994   {
8995     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8996   },
8997
8998   /* VEX_LEN_0F3A7F_P_2 */
8999   {
9000     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9001   },
9002
9003   /* VEX_LEN_0F3ADF_P_2 */
9004   {
9005     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9006   },
9007
9008   /* VEX_LEN_0F3AF0_P_3 */
9009   {
9010     { "rorxS",          { Gdq, Edq, Ib } },
9011   },
9012
9013   /* VEX_LEN_0FXOP_08_CC */
9014   {
9015      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9016   },
9017
9018   /* VEX_LEN_0FXOP_08_CD */
9019   {
9020      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9021   },
9022
9023   /* VEX_LEN_0FXOP_08_CE */
9024   {
9025      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9026   },
9027
9028   /* VEX_LEN_0FXOP_08_CF */
9029   {
9030      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9031   },
9032
9033   /* VEX_LEN_0FXOP_08_EC */
9034   {
9035      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9036   },
9037
9038   /* VEX_LEN_0FXOP_08_ED */
9039   {
9040      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9041   },
9042
9043   /* VEX_LEN_0FXOP_08_EE */
9044   {
9045      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9046   },
9047
9048   /* VEX_LEN_0FXOP_08_EF */
9049   {
9050      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9051   },
9052
9053   /* VEX_LEN_0FXOP_09_80 */
9054   {
9055     { "vfrczps",        { XM, EXxmm } },
9056     { "vfrczps",        { XM, EXymmq } },
9057   },
9058
9059   /* VEX_LEN_0FXOP_09_81 */
9060   {
9061     { "vfrczpd",        { XM, EXxmm } },
9062     { "vfrczpd",        { XM, EXymmq } },
9063   },
9064 };
9065
9066 static const struct dis386 vex_w_table[][2] = {
9067   {
9068     /* VEX_W_0F10_P_0 */
9069     { "vmovups",        { XM, EXx } },
9070   },
9071   {
9072     /* VEX_W_0F10_P_1 */
9073     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9074   },
9075   {
9076     /* VEX_W_0F10_P_2 */
9077     { "vmovupd",        { XM, EXx } },
9078   },
9079   {
9080     /* VEX_W_0F10_P_3 */
9081     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9082   },
9083   {
9084     /* VEX_W_0F11_P_0 */
9085     { "vmovups",        { EXxS, XM } },
9086   },
9087   {
9088     /* VEX_W_0F11_P_1 */
9089     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9090   },
9091   {
9092     /* VEX_W_0F11_P_2 */
9093     { "vmovupd",        { EXxS, XM } },
9094   },
9095   {
9096     /* VEX_W_0F11_P_3 */
9097     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9098   },
9099   {
9100     /* VEX_W_0F12_P_0_M_0 */
9101     { "vmovlps",        { XM, Vex128, EXq } },
9102   },
9103   {
9104     /* VEX_W_0F12_P_0_M_1 */
9105     { "vmovhlps",       { XM, Vex128, EXq } },
9106   },
9107   {
9108     /* VEX_W_0F12_P_1 */
9109     { "vmovsldup",      { XM, EXx } },
9110   },
9111   {
9112     /* VEX_W_0F12_P_2 */
9113     { "vmovlpd",        { XM, Vex128, EXq } },
9114   },
9115   {
9116     /* VEX_W_0F12_P_3 */
9117     { "vmovddup",       { XM, EXymmq } },
9118   },
9119   {
9120     /* VEX_W_0F13_M_0 */
9121     { "vmovlpX",        { EXq, XM } },
9122   },
9123   {
9124     /* VEX_W_0F14 */
9125     { "vunpcklpX",      { XM, Vex, EXx } },
9126   },
9127   {
9128     /* VEX_W_0F15 */
9129     { "vunpckhpX",      { XM, Vex, EXx } },
9130   },
9131   {
9132     /* VEX_W_0F16_P_0_M_0 */
9133     { "vmovhps",        { XM, Vex128, EXq } },
9134   },
9135   {
9136     /* VEX_W_0F16_P_0_M_1 */
9137     { "vmovlhps",       { XM, Vex128, EXq } },
9138   },
9139   {
9140     /* VEX_W_0F16_P_1 */
9141     { "vmovshdup",      { XM, EXx } },
9142   },
9143   {
9144     /* VEX_W_0F16_P_2 */
9145     { "vmovhpd",        { XM, Vex128, EXq } },
9146   },
9147   {
9148     /* VEX_W_0F17_M_0 */
9149     { "vmovhpX",        { EXq, XM } },
9150   },
9151   {
9152     /* VEX_W_0F28 */
9153     { "vmovapX",        { XM, EXx } },
9154   },
9155   {
9156     /* VEX_W_0F29 */
9157     { "vmovapX",        { EXxS, XM } },
9158   },
9159   {
9160     /* VEX_W_0F2B_M_0 */
9161     { "vmovntpX",       { Mx, XM } },
9162   },
9163   {
9164     /* VEX_W_0F2E_P_0 */
9165     { "vucomiss",       { XMScalar, EXdScalar } },
9166   },
9167   {
9168     /* VEX_W_0F2E_P_2 */
9169     { "vucomisd",       { XMScalar, EXqScalar } },
9170   },
9171   {
9172     /* VEX_W_0F2F_P_0 */
9173     { "vcomiss",        { XMScalar, EXdScalar } },
9174   },
9175   {
9176     /* VEX_W_0F2F_P_2 */
9177     { "vcomisd",        { XMScalar, EXqScalar } },
9178   },
9179   {
9180     /* VEX_W_0F50_M_0 */
9181     { "vmovmskpX",      { Gdq, XS } },
9182   },
9183   {
9184     /* VEX_W_0F51_P_0 */
9185     { "vsqrtps",        { XM, EXx } },
9186   },
9187   {
9188     /* VEX_W_0F51_P_1 */
9189     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9190   },
9191   {
9192     /* VEX_W_0F51_P_2  */
9193     { "vsqrtpd",        { XM, EXx } },
9194   },
9195   {
9196     /* VEX_W_0F51_P_3 */
9197     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9198   },
9199   {
9200     /* VEX_W_0F52_P_0 */
9201     { "vrsqrtps",       { XM, EXx } },
9202   },
9203   {
9204     /* VEX_W_0F52_P_1 */
9205     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9206   },
9207   {
9208     /* VEX_W_0F53_P_0  */
9209     { "vrcpps",         { XM, EXx } },
9210   },
9211   {
9212     /* VEX_W_0F53_P_1  */
9213     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9214   },
9215   {
9216     /* VEX_W_0F58_P_0  */
9217     { "vaddps",         { XM, Vex, EXx } },
9218   },
9219   {
9220     /* VEX_W_0F58_P_1  */
9221     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9222   },
9223   {
9224     /* VEX_W_0F58_P_2  */
9225     { "vaddpd",         { XM, Vex, EXx } },
9226   },
9227   {
9228     /* VEX_W_0F58_P_3  */
9229     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9230   },
9231   {
9232     /* VEX_W_0F59_P_0  */
9233     { "vmulps",         { XM, Vex, EXx } },
9234   },
9235   {
9236     /* VEX_W_0F59_P_1  */
9237     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9238   },
9239   {
9240     /* VEX_W_0F59_P_2  */
9241     { "vmulpd",         { XM, Vex, EXx } },
9242   },
9243   {
9244     /* VEX_W_0F59_P_3  */
9245     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9246   },
9247   {
9248     /* VEX_W_0F5A_P_0  */
9249     { "vcvtps2pd",      { XM, EXxmmq } },
9250   },
9251   {
9252     /* VEX_W_0F5A_P_1  */
9253     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9254   },
9255   {
9256     /* VEX_W_0F5A_P_3  */
9257     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9258   },
9259   {
9260     /* VEX_W_0F5B_P_0  */
9261     { "vcvtdq2ps",      { XM, EXx } },
9262   },
9263   {
9264     /* VEX_W_0F5B_P_1  */
9265     { "vcvttps2dq",     { XM, EXx } },
9266   },
9267   {
9268     /* VEX_W_0F5B_P_2  */
9269     { "vcvtps2dq",      { XM, EXx } },
9270   },
9271   {
9272     /* VEX_W_0F5C_P_0  */
9273     { "vsubps",         { XM, Vex, EXx } },
9274   },
9275   {
9276     /* VEX_W_0F5C_P_1  */
9277     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9278   },
9279   {
9280     /* VEX_W_0F5C_P_2  */
9281     { "vsubpd",         { XM, Vex, EXx } },
9282   },
9283   {
9284     /* VEX_W_0F5C_P_3  */
9285     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9286   },
9287   {
9288     /* VEX_W_0F5D_P_0  */
9289     { "vminps",         { XM, Vex, EXx } },
9290   },
9291   {
9292     /* VEX_W_0F5D_P_1  */
9293     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9294   },
9295   {
9296     /* VEX_W_0F5D_P_2  */
9297     { "vminpd",         { XM, Vex, EXx } },
9298   },
9299   {
9300     /* VEX_W_0F5D_P_3  */
9301     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9302   },
9303   {
9304     /* VEX_W_0F5E_P_0  */
9305     { "vdivps",         { XM, Vex, EXx } },
9306   },
9307   {
9308     /* VEX_W_0F5E_P_1  */
9309     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9310   },
9311   {
9312     /* VEX_W_0F5E_P_2  */
9313     { "vdivpd",         { XM, Vex, EXx } },
9314   },
9315   {
9316     /* VEX_W_0F5E_P_3  */
9317     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9318   },
9319   {
9320     /* VEX_W_0F5F_P_0  */
9321     { "vmaxps",         { XM, Vex, EXx } },
9322   },
9323   {
9324     /* VEX_W_0F5F_P_1  */
9325     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9326   },
9327   {
9328     /* VEX_W_0F5F_P_2  */
9329     { "vmaxpd",         { XM, Vex, EXx } },
9330   },
9331   {
9332     /* VEX_W_0F5F_P_3  */
9333     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9334   },
9335   {
9336     /* VEX_W_0F60_P_2  */
9337     { "vpunpcklbw",     { XM, Vex, EXx } },
9338   },
9339   {
9340     /* VEX_W_0F61_P_2  */
9341     { "vpunpcklwd",     { XM, Vex, EXx } },
9342   },
9343   {
9344     /* VEX_W_0F62_P_2  */
9345     { "vpunpckldq",     { XM, Vex, EXx } },
9346   },
9347   {
9348     /* VEX_W_0F63_P_2  */
9349     { "vpacksswb",      { XM, Vex, EXx } },
9350   },
9351   {
9352     /* VEX_W_0F64_P_2  */
9353     { "vpcmpgtb",       { XM, Vex, EXx } },
9354   },
9355   {
9356     /* VEX_W_0F65_P_2  */
9357     { "vpcmpgtw",       { XM, Vex, EXx } },
9358   },
9359   {
9360     /* VEX_W_0F66_P_2  */
9361     { "vpcmpgtd",       { XM, Vex, EXx } },
9362   },
9363   {
9364     /* VEX_W_0F67_P_2  */
9365     { "vpackuswb",      { XM, Vex, EXx } },
9366   },
9367   {
9368     /* VEX_W_0F68_P_2  */
9369     { "vpunpckhbw",     { XM, Vex, EXx } },
9370   },
9371   {
9372     /* VEX_W_0F69_P_2  */
9373     { "vpunpckhwd",     { XM, Vex, EXx } },
9374   },
9375   {
9376     /* VEX_W_0F6A_P_2  */
9377     { "vpunpckhdq",     { XM, Vex, EXx } },
9378   },
9379   {
9380     /* VEX_W_0F6B_P_2  */
9381     { "vpackssdw",      { XM, Vex, EXx } },
9382   },
9383   {
9384     /* VEX_W_0F6C_P_2  */
9385     { "vpunpcklqdq",    { XM, Vex, EXx } },
9386   },
9387   {
9388     /* VEX_W_0F6D_P_2  */
9389     { "vpunpckhqdq",    { XM, Vex, EXx } },
9390   },
9391   {
9392     /* VEX_W_0F6F_P_1  */
9393     { "vmovdqu",        { XM, EXx } },
9394   },
9395   {
9396     /* VEX_W_0F6F_P_2  */
9397     { "vmovdqa",        { XM, EXx } },
9398   },
9399   {
9400     /* VEX_W_0F70_P_1 */
9401     { "vpshufhw",       { XM, EXx, Ib } },
9402   },
9403   {
9404     /* VEX_W_0F70_P_2 */
9405     { "vpshufd",        { XM, EXx, Ib } },
9406   },
9407   {
9408     /* VEX_W_0F70_P_3 */
9409     { "vpshuflw",       { XM, EXx, Ib } },
9410   },
9411   {
9412     /* VEX_W_0F71_R_2_P_2  */
9413     { "vpsrlw",         { Vex, XS, Ib } },
9414   },
9415   {
9416     /* VEX_W_0F71_R_4_P_2  */
9417     { "vpsraw",         { Vex, XS, Ib } },
9418   },
9419   {
9420     /* VEX_W_0F71_R_6_P_2  */
9421     { "vpsllw",         { Vex, XS, Ib } },
9422   },
9423   {
9424     /* VEX_W_0F72_R_2_P_2  */
9425     { "vpsrld",         { Vex, XS, Ib } },
9426   },
9427   {
9428     /* VEX_W_0F72_R_4_P_2  */
9429     { "vpsrad",         { Vex, XS, Ib } },
9430   },
9431   {
9432     /* VEX_W_0F72_R_6_P_2  */
9433     { "vpslld",         { Vex, XS, Ib } },
9434   },
9435   {
9436     /* VEX_W_0F73_R_2_P_2  */
9437     { "vpsrlq",         { Vex, XS, Ib } },
9438   },
9439   {
9440     /* VEX_W_0F73_R_3_P_2  */
9441     { "vpsrldq",        { Vex, XS, Ib } },
9442   },
9443   {
9444     /* VEX_W_0F73_R_6_P_2  */
9445     { "vpsllq",         { Vex, XS, Ib } },
9446   },
9447   {
9448     /* VEX_W_0F73_R_7_P_2  */
9449     { "vpslldq",        { Vex, XS, Ib } },
9450   },
9451   {
9452     /* VEX_W_0F74_P_2 */
9453     { "vpcmpeqb",       { XM, Vex, EXx } },
9454   },
9455   {
9456     /* VEX_W_0F75_P_2 */
9457     { "vpcmpeqw",       { XM, Vex, EXx } },
9458   },
9459   {
9460     /* VEX_W_0F76_P_2 */
9461     { "vpcmpeqd",       { XM, Vex, EXx } },
9462   },
9463   {
9464     /* VEX_W_0F77_P_0 */
9465     { "",               { VZERO } },
9466   },
9467   {
9468     /* VEX_W_0F7C_P_2 */
9469     { "vhaddpd",        { XM, Vex, EXx } },
9470   },
9471   {
9472     /* VEX_W_0F7C_P_3 */
9473     { "vhaddps",        { XM, Vex, EXx } },
9474   },
9475   {
9476     /* VEX_W_0F7D_P_2 */
9477     { "vhsubpd",        { XM, Vex, EXx } },
9478   },
9479   {
9480     /* VEX_W_0F7D_P_3 */
9481     { "vhsubps",        { XM, Vex, EXx } },
9482   },
9483   {
9484     /* VEX_W_0F7E_P_1 */
9485     { "vmovq",          { XMScalar, EXqScalar } },
9486   },
9487   {
9488     /* VEX_W_0F7F_P_1 */
9489     { "vmovdqu",        { EXxS, XM } },
9490   },
9491   {
9492     /* VEX_W_0F7F_P_2 */
9493     { "vmovdqa",        { EXxS, XM } },
9494   },
9495   {
9496     /* VEX_W_0FAE_R_2_M_0 */
9497     { "vldmxcsr",       { Md } },
9498   },
9499   {
9500     /* VEX_W_0FAE_R_3_M_0 */
9501     { "vstmxcsr",       { Md } },
9502   },
9503   {
9504     /* VEX_W_0FC2_P_0 */
9505     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9506   },
9507   {
9508     /* VEX_W_0FC2_P_1 */
9509     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9510   },
9511   {
9512     /* VEX_W_0FC2_P_2 */
9513     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9514   },
9515   {
9516     /* VEX_W_0FC2_P_3 */
9517     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9518   },
9519   {
9520     /* VEX_W_0FC4_P_2 */
9521     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9522   },
9523   {
9524     /* VEX_W_0FC5_P_2 */
9525     { "vpextrw",        { Gdq, XS, Ib } },
9526   },
9527   {
9528     /* VEX_W_0FD0_P_2 */
9529     { "vaddsubpd",      { XM, Vex, EXx } },
9530   },
9531   {
9532     /* VEX_W_0FD0_P_3 */
9533     { "vaddsubps",      { XM, Vex, EXx } },
9534   },
9535   {
9536     /* VEX_W_0FD1_P_2 */
9537     { "vpsrlw",         { XM, Vex, EXxmm } },
9538   },
9539   {
9540     /* VEX_W_0FD2_P_2 */
9541     { "vpsrld",         { XM, Vex, EXxmm } },
9542   },
9543   {
9544     /* VEX_W_0FD3_P_2 */
9545     { "vpsrlq",         { XM, Vex, EXxmm } },
9546   },
9547   {
9548     /* VEX_W_0FD4_P_2 */
9549     { "vpaddq",         { XM, Vex, EXx } },
9550   },
9551   {
9552     /* VEX_W_0FD5_P_2 */
9553     { "vpmullw",        { XM, Vex, EXx } },
9554   },
9555   {
9556     /* VEX_W_0FD6_P_2 */
9557     { "vmovq",          { EXqScalarS, XMScalar } },
9558   },
9559   {
9560     /* VEX_W_0FD7_P_2_M_1 */
9561     { "vpmovmskb",      { Gdq, XS } },
9562   },
9563   {
9564     /* VEX_W_0FD8_P_2 */
9565     { "vpsubusb",       { XM, Vex, EXx } },
9566   },
9567   {
9568     /* VEX_W_0FD9_P_2 */
9569     { "vpsubusw",       { XM, Vex, EXx } },
9570   },
9571   {
9572     /* VEX_W_0FDA_P_2 */
9573     { "vpminub",        { XM, Vex, EXx } },
9574   },
9575   {
9576     /* VEX_W_0FDB_P_2 */
9577     { "vpand",          { XM, Vex, EXx } },
9578   },
9579   {
9580     /* VEX_W_0FDC_P_2 */
9581     { "vpaddusb",       { XM, Vex, EXx } },
9582   },
9583   {
9584     /* VEX_W_0FDD_P_2 */
9585     { "vpaddusw",       { XM, Vex, EXx } },
9586   },
9587   {
9588     /* VEX_W_0FDE_P_2 */
9589     { "vpmaxub",        { XM, Vex, EXx } },
9590   },
9591   {
9592     /* VEX_W_0FDF_P_2 */
9593     { "vpandn",         { XM, Vex, EXx } },
9594   },
9595   {
9596     /* VEX_W_0FE0_P_2  */
9597     { "vpavgb",         { XM, Vex, EXx } },
9598   },
9599   {
9600     /* VEX_W_0FE1_P_2  */
9601     { "vpsraw",         { XM, Vex, EXxmm } },
9602   },
9603   {
9604     /* VEX_W_0FE2_P_2  */
9605     { "vpsrad",         { XM, Vex, EXxmm } },
9606   },
9607   {
9608     /* VEX_W_0FE3_P_2  */
9609     { "vpavgw",         { XM, Vex, EXx } },
9610   },
9611   {
9612     /* VEX_W_0FE4_P_2  */
9613     { "vpmulhuw",       { XM, Vex, EXx } },
9614   },
9615   {
9616     /* VEX_W_0FE5_P_2  */
9617     { "vpmulhw",        { XM, Vex, EXx } },
9618   },
9619   {
9620     /* VEX_W_0FE6_P_1  */
9621     { "vcvtdq2pd",      { XM, EXxmmq } },
9622   },
9623   {
9624     /* VEX_W_0FE6_P_2  */
9625     { "vcvttpd2dq%XY",  { XMM, EXx } },
9626   },
9627   {
9628     /* VEX_W_0FE6_P_3  */
9629     { "vcvtpd2dq%XY",   { XMM, EXx } },
9630   },
9631   {
9632     /* VEX_W_0FE7_P_2_M_0 */
9633     { "vmovntdq",       { Mx, XM } },
9634   },
9635   {
9636     /* VEX_W_0FE8_P_2  */
9637     { "vpsubsb",        { XM, Vex, EXx } },
9638   },
9639   {
9640     /* VEX_W_0FE9_P_2  */
9641     { "vpsubsw",        { XM, Vex, EXx } },
9642   },
9643   {
9644     /* VEX_W_0FEA_P_2  */
9645     { "vpminsw",        { XM, Vex, EXx } },
9646   },
9647   {
9648     /* VEX_W_0FEB_P_2  */
9649     { "vpor",           { XM, Vex, EXx } },
9650   },
9651   {
9652     /* VEX_W_0FEC_P_2  */
9653     { "vpaddsb",        { XM, Vex, EXx } },
9654   },
9655   {
9656     /* VEX_W_0FED_P_2  */
9657     { "vpaddsw",        { XM, Vex, EXx } },
9658   },
9659   {
9660     /* VEX_W_0FEE_P_2  */
9661     { "vpmaxsw",        { XM, Vex, EXx } },
9662   },
9663   {
9664     /* VEX_W_0FEF_P_2  */
9665     { "vpxor",          { XM, Vex, EXx } },
9666   },
9667   {
9668     /* VEX_W_0FF0_P_3_M_0 */
9669     { "vlddqu",         { XM, M } },
9670   },
9671   {
9672     /* VEX_W_0FF1_P_2 */
9673     { "vpsllw",         { XM, Vex, EXxmm } },
9674   },
9675   {
9676     /* VEX_W_0FF2_P_2 */
9677     { "vpslld",         { XM, Vex, EXxmm } },
9678   },
9679   {
9680     /* VEX_W_0FF3_P_2 */
9681     { "vpsllq",         { XM, Vex, EXxmm } },
9682   },
9683   {
9684     /* VEX_W_0FF4_P_2 */
9685     { "vpmuludq",       { XM, Vex, EXx } },
9686   },
9687   {
9688     /* VEX_W_0FF5_P_2 */
9689     { "vpmaddwd",       { XM, Vex, EXx } },
9690   },
9691   {
9692     /* VEX_W_0FF6_P_2 */
9693     { "vpsadbw",        { XM, Vex, EXx } },
9694   },
9695   {
9696     /* VEX_W_0FF7_P_2 */
9697     { "vmaskmovdqu",    { XM, XS } },
9698   },
9699   {
9700     /* VEX_W_0FF8_P_2 */
9701     { "vpsubb",         { XM, Vex, EXx } },
9702   },
9703   {
9704     /* VEX_W_0FF9_P_2 */
9705     { "vpsubw",         { XM, Vex, EXx } },
9706   },
9707   {
9708     /* VEX_W_0FFA_P_2 */
9709     { "vpsubd",         { XM, Vex, EXx } },
9710   },
9711   {
9712     /* VEX_W_0FFB_P_2 */
9713     { "vpsubq",         { XM, Vex, EXx } },
9714   },
9715   {
9716     /* VEX_W_0FFC_P_2 */
9717     { "vpaddb",         { XM, Vex, EXx } },
9718   },
9719   {
9720     /* VEX_W_0FFD_P_2 */
9721     { "vpaddw",         { XM, Vex, EXx } },
9722   },
9723   {
9724     /* VEX_W_0FFE_P_2 */
9725     { "vpaddd",         { XM, Vex, EXx } },
9726   },
9727   {
9728     /* VEX_W_0F3800_P_2  */
9729     { "vpshufb",        { XM, Vex, EXx } },
9730   },
9731   {
9732     /* VEX_W_0F3801_P_2  */
9733     { "vphaddw",        { XM, Vex, EXx } },
9734   },
9735   {
9736     /* VEX_W_0F3802_P_2  */
9737     { "vphaddd",        { XM, Vex, EXx } },
9738   },
9739   {
9740     /* VEX_W_0F3803_P_2  */
9741     { "vphaddsw",       { XM, Vex, EXx } },
9742   },
9743   {
9744     /* VEX_W_0F3804_P_2  */
9745     { "vpmaddubsw",     { XM, Vex, EXx } },
9746   },
9747   {
9748     /* VEX_W_0F3805_P_2  */
9749     { "vphsubw",        { XM, Vex, EXx } },
9750   },
9751   {
9752     /* VEX_W_0F3806_P_2  */
9753     { "vphsubd",        { XM, Vex, EXx } },
9754   },
9755   {
9756     /* VEX_W_0F3807_P_2  */
9757     { "vphsubsw",       { XM, Vex, EXx } },
9758   },
9759   {
9760     /* VEX_W_0F3808_P_2  */
9761     { "vpsignb",        { XM, Vex, EXx } },
9762   },
9763   {
9764     /* VEX_W_0F3809_P_2  */
9765     { "vpsignw",        { XM, Vex, EXx } },
9766   },
9767   {
9768     /* VEX_W_0F380A_P_2  */
9769     { "vpsignd",        { XM, Vex, EXx } },
9770   },
9771   {
9772     /* VEX_W_0F380B_P_2  */
9773     { "vpmulhrsw",      { XM, Vex, EXx } },
9774   },
9775   {
9776     /* VEX_W_0F380C_P_2  */
9777     { "vpermilps",      { XM, Vex, EXx } },
9778   },
9779   {
9780     /* VEX_W_0F380D_P_2  */
9781     { "vpermilpd",      { XM, Vex, EXx } },
9782   },
9783   {
9784     /* VEX_W_0F380E_P_2  */
9785     { "vtestps",        { XM, EXx } },
9786   },
9787   {
9788     /* VEX_W_0F380F_P_2  */
9789     { "vtestpd",        { XM, EXx } },
9790   },
9791   {
9792     /* VEX_W_0F3816_P_2  */
9793     { "vpermps",        { XM, Vex, EXx } },
9794   },
9795   {
9796     /* VEX_W_0F3817_P_2 */
9797     { "vptest",         { XM, EXx } },
9798   },
9799   {
9800     /* VEX_W_0F3818_P_2 */
9801     { "vbroadcastss",   { XM, EXxmm_md } },
9802   },
9803   {
9804     /* VEX_W_0F3819_P_2 */
9805     { "vbroadcastsd",   { XM, EXxmm_mq } },
9806   },
9807   {
9808     /* VEX_W_0F381A_P_2_M_0 */
9809     { "vbroadcastf128", { XM, Mxmm } },
9810   },
9811   {
9812     /* VEX_W_0F381C_P_2 */
9813     { "vpabsb",         { XM, EXx } },
9814   },
9815   {
9816     /* VEX_W_0F381D_P_2 */
9817     { "vpabsw",         { XM, EXx } },
9818   },
9819   {
9820     /* VEX_W_0F381E_P_2 */
9821     { "vpabsd",         { XM, EXx } },
9822   },
9823   {
9824     /* VEX_W_0F3820_P_2 */
9825     { "vpmovsxbw",      { XM, EXxmmq } },
9826   },
9827   {
9828     /* VEX_W_0F3821_P_2 */
9829     { "vpmovsxbd",      { XM, EXxmmqd } },
9830   },
9831   {
9832     /* VEX_W_0F3822_P_2 */
9833     { "vpmovsxbq",      { XM, EXxmmdw } },
9834   },
9835   {
9836     /* VEX_W_0F3823_P_2 */
9837     { "vpmovsxwd",      { XM, EXxmmq } },
9838   },
9839   {
9840     /* VEX_W_0F3824_P_2 */
9841     { "vpmovsxwq",      { XM, EXxmmqd } },
9842   },
9843   {
9844     /* VEX_W_0F3825_P_2 */
9845     { "vpmovsxdq",      { XM, EXxmmq } },
9846   },
9847   {
9848     /* VEX_W_0F3828_P_2 */
9849     { "vpmuldq",        { XM, Vex, EXx } },
9850   },
9851   {
9852     /* VEX_W_0F3829_P_2 */
9853     { "vpcmpeqq",       { XM, Vex, EXx } },
9854   },
9855   {
9856     /* VEX_W_0F382A_P_2_M_0 */
9857     { "vmovntdqa",      { XM, Mx } },
9858   },
9859   {
9860     /* VEX_W_0F382B_P_2 */
9861     { "vpackusdw",      { XM, Vex, EXx } },
9862   },
9863   {
9864     /* VEX_W_0F382C_P_2_M_0 */
9865     { "vmaskmovps",     { XM, Vex, Mx } },
9866   },
9867   {
9868     /* VEX_W_0F382D_P_2_M_0 */
9869     { "vmaskmovpd",     { XM, Vex, Mx } },
9870   },
9871   {
9872     /* VEX_W_0F382E_P_2_M_0 */
9873     { "vmaskmovps",     { Mx, Vex, XM } },
9874   },
9875   {
9876     /* VEX_W_0F382F_P_2_M_0 */
9877     { "vmaskmovpd",     { Mx, Vex, XM } },
9878   },
9879   {
9880     /* VEX_W_0F3830_P_2 */
9881     { "vpmovzxbw",      { XM, EXxmmq } },
9882   },
9883   {
9884     /* VEX_W_0F3831_P_2 */
9885     { "vpmovzxbd",      { XM, EXxmmqd } },
9886   },
9887   {
9888     /* VEX_W_0F3832_P_2 */
9889     { "vpmovzxbq",      { XM, EXxmmdw } },
9890   },
9891   {
9892     /* VEX_W_0F3833_P_2 */
9893     { "vpmovzxwd",      { XM, EXxmmq } },
9894   },
9895   {
9896     /* VEX_W_0F3834_P_2 */
9897     { "vpmovzxwq",      { XM, EXxmmqd } },
9898   },
9899   {
9900     /* VEX_W_0F3835_P_2 */
9901     { "vpmovzxdq",      { XM, EXxmmq } },
9902   },
9903   {
9904     /* VEX_W_0F3836_P_2  */
9905     { "vpermd",         { XM, Vex, EXx } },
9906   },
9907   {
9908     /* VEX_W_0F3837_P_2 */
9909     { "vpcmpgtq",       { XM, Vex, EXx } },
9910   },
9911   {
9912     /* VEX_W_0F3838_P_2 */
9913     { "vpminsb",        { XM, Vex, EXx } },
9914   },
9915   {
9916     /* VEX_W_0F3839_P_2 */
9917     { "vpminsd",        { XM, Vex, EXx } },
9918   },
9919   {
9920     /* VEX_W_0F383A_P_2 */
9921     { "vpminuw",        { XM, Vex, EXx } },
9922   },
9923   {
9924     /* VEX_W_0F383B_P_2 */
9925     { "vpminud",        { XM, Vex, EXx } },
9926   },
9927   {
9928     /* VEX_W_0F383C_P_2 */
9929     { "vpmaxsb",        { XM, Vex, EXx } },
9930   },
9931   {
9932     /* VEX_W_0F383D_P_2 */
9933     { "vpmaxsd",        { XM, Vex, EXx } },
9934   },
9935   {
9936     /* VEX_W_0F383E_P_2 */
9937     { "vpmaxuw",        { XM, Vex, EXx } },
9938   },
9939   {
9940     /* VEX_W_0F383F_P_2 */
9941     { "vpmaxud",        { XM, Vex, EXx } },
9942   },
9943   {
9944     /* VEX_W_0F3840_P_2 */
9945     { "vpmulld",        { XM, Vex, EXx } },
9946   },
9947   {
9948     /* VEX_W_0F3841_P_2 */
9949     { "vphminposuw",    { XM, EXx } },
9950   },
9951   {
9952     /* VEX_W_0F3846_P_2 */
9953     { "vpsravd",        { XM, Vex, EXx } },
9954   },
9955   {
9956     /* VEX_W_0F3858_P_2 */
9957     { "vpbroadcastd", { XM, EXxmm_md } },
9958   },
9959   {
9960     /* VEX_W_0F3859_P_2 */
9961     { "vpbroadcastq",   { XM, EXxmm_mq } },
9962   },
9963   {
9964     /* VEX_W_0F385A_P_2_M_0 */
9965     { "vbroadcasti128", { XM, Mxmm } },
9966   },
9967   {
9968     /* VEX_W_0F3878_P_2 */
9969     { "vpbroadcastb",   { XM, EXxmm_mb } },
9970   },
9971   {
9972     /* VEX_W_0F3879_P_2 */
9973     { "vpbroadcastw",   { XM, EXxmm_mw } },
9974   },
9975   {
9976     /* VEX_W_0F38DB_P_2 */
9977     { "vaesimc",        { XM, EXx } },
9978   },
9979   {
9980     /* VEX_W_0F38DC_P_2 */
9981     { "vaesenc",        { XM, Vex128, EXx } },
9982   },
9983   {
9984     /* VEX_W_0F38DD_P_2 */
9985     { "vaesenclast",    { XM, Vex128, EXx } },
9986   },
9987   {
9988     /* VEX_W_0F38DE_P_2 */
9989     { "vaesdec",        { XM, Vex128, EXx } },
9990   },
9991   {
9992     /* VEX_W_0F38DF_P_2 */
9993     { "vaesdeclast",    { XM, Vex128, EXx } },
9994   },
9995   {
9996     /* VEX_W_0F3A00_P_2 */
9997     { Bad_Opcode },
9998     { "vpermq",         { XM, EXx, Ib } },
9999   },
10000   {
10001     /* VEX_W_0F3A01_P_2 */
10002     { Bad_Opcode },
10003     { "vpermpd",        { XM, EXx, Ib } },
10004   },
10005   {
10006     /* VEX_W_0F3A02_P_2 */
10007     { "vpblendd",       { XM, Vex, EXx, Ib } },
10008   },
10009   {
10010     /* VEX_W_0F3A04_P_2 */
10011     { "vpermilps",      { XM, EXx, Ib } },
10012   },
10013   {
10014     /* VEX_W_0F3A05_P_2 */
10015     { "vpermilpd",      { XM, EXx, Ib } },
10016   },
10017   {
10018     /* VEX_W_0F3A06_P_2 */
10019     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10020   },
10021   {
10022     /* VEX_W_0F3A08_P_2 */
10023     { "vroundps",       { XM, EXx, Ib } },
10024   },
10025   {
10026     /* VEX_W_0F3A09_P_2 */
10027     { "vroundpd",       { XM, EXx, Ib } },
10028   },
10029   {
10030     /* VEX_W_0F3A0A_P_2 */
10031     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10032   },
10033   {
10034     /* VEX_W_0F3A0B_P_2 */
10035     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10036   },
10037   {
10038     /* VEX_W_0F3A0C_P_2 */
10039     { "vblendps",       { XM, Vex, EXx, Ib } },
10040   },
10041   {
10042     /* VEX_W_0F3A0D_P_2 */
10043     { "vblendpd",       { XM, Vex, EXx, Ib } },
10044   },
10045   {
10046     /* VEX_W_0F3A0E_P_2 */
10047     { "vpblendw",       { XM, Vex, EXx, Ib } },
10048   },
10049   {
10050     /* VEX_W_0F3A0F_P_2 */
10051     { "vpalignr",       { XM, Vex, EXx, Ib } },
10052   },
10053   {
10054     /* VEX_W_0F3A14_P_2 */
10055     { "vpextrb",        { Edqb, XM, Ib } },
10056   },
10057   {
10058     /* VEX_W_0F3A15_P_2 */
10059     { "vpextrw",        { Edqw, XM, Ib } },
10060   },
10061   {
10062     /* VEX_W_0F3A18_P_2 */
10063     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10064   },
10065   {
10066     /* VEX_W_0F3A19_P_2 */
10067     { "vextractf128",   { EXxmm, XM, Ib } },
10068   },
10069   {
10070     /* VEX_W_0F3A20_P_2 */
10071     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10072   },
10073   {
10074     /* VEX_W_0F3A21_P_2 */
10075     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10076   },
10077   {
10078     /* VEX_W_0F3A38_P_2 */
10079     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10080   },
10081   {
10082     /* VEX_W_0F3A39_P_2 */
10083     { "vextracti128",   { EXxmm, XM, Ib } },
10084   },
10085   {
10086     /* VEX_W_0F3A40_P_2 */
10087     { "vdpps",          { XM, Vex, EXx, Ib } },
10088   },
10089   {
10090     /* VEX_W_0F3A41_P_2 */
10091     { "vdppd",          { XM, Vex128, EXx, Ib } },
10092   },
10093   {
10094     /* VEX_W_0F3A42_P_2 */
10095     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10096   },
10097   {
10098     /* VEX_W_0F3A44_P_2 */
10099     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10100   },
10101   {
10102     /* VEX_W_0F3A46_P_2 */
10103     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10104   },
10105   {
10106     /* VEX_W_0F3A48_P_2 */
10107     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10108     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10109   },
10110   {
10111     /* VEX_W_0F3A49_P_2 */
10112     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10113     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10114   },
10115   {
10116     /* VEX_W_0F3A4A_P_2 */
10117     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10118   },
10119   {
10120     /* VEX_W_0F3A4B_P_2 */
10121     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10122   },
10123   {
10124     /* VEX_W_0F3A4C_P_2 */
10125     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
10126   },
10127   {
10128     /* VEX_W_0F3A60_P_2 */
10129     { "vpcmpestrm",     { XM, EXx, Ib } },
10130   },
10131   {
10132     /* VEX_W_0F3A61_P_2 */
10133     { "vpcmpestri",     { XM, EXx, Ib } },
10134   },
10135   {
10136     /* VEX_W_0F3A62_P_2 */
10137     { "vpcmpistrm",     { XM, EXx, Ib } },
10138   },
10139   {
10140     /* VEX_W_0F3A63_P_2 */
10141     { "vpcmpistri",     { XM, EXx, Ib } },
10142   },
10143   {
10144     /* VEX_W_0F3ADF_P_2 */
10145     { "vaeskeygenassist", { XM, EXx, Ib } },
10146   },
10147 };
10148
10149 static const struct dis386 mod_table[][2] = {
10150   {
10151     /* MOD_8D */
10152     { "leaS",           { Gv, M } },
10153   },
10154   {
10155     /* MOD_C6_REG_7 */
10156     { Bad_Opcode },
10157     { RM_TABLE (RM_C6_REG_7) },
10158   },
10159   {
10160     /* MOD_C7_REG_7 */
10161     { Bad_Opcode },
10162     { RM_TABLE (RM_C7_REG_7) },
10163   },
10164   {
10165     /* MOD_0F01_REG_0 */
10166     { X86_64_TABLE (X86_64_0F01_REG_0) },
10167     { RM_TABLE (RM_0F01_REG_0) },
10168   },
10169   {
10170     /* MOD_0F01_REG_1 */
10171     { X86_64_TABLE (X86_64_0F01_REG_1) },
10172     { RM_TABLE (RM_0F01_REG_1) },
10173   },
10174   {
10175     /* MOD_0F01_REG_2 */
10176     { X86_64_TABLE (X86_64_0F01_REG_2) },
10177     { RM_TABLE (RM_0F01_REG_2) },
10178   },
10179   {
10180     /* MOD_0F01_REG_3 */
10181     { X86_64_TABLE (X86_64_0F01_REG_3) },
10182     { RM_TABLE (RM_0F01_REG_3) },
10183   },
10184   {
10185     /* MOD_0F01_REG_7 */
10186     { "invlpg",         { Mb } },
10187     { RM_TABLE (RM_0F01_REG_7) },
10188   },
10189   {
10190     /* MOD_0F12_PREFIX_0 */
10191     { "movlps",         { XM, EXq } },
10192     { "movhlps",        { XM, EXq } },
10193   },
10194   {
10195     /* MOD_0F13 */
10196     { "movlpX",         { EXq, XM } },
10197   },
10198   {
10199     /* MOD_0F16_PREFIX_0 */
10200     { "movhps",         { XM, EXq } },
10201     { "movlhps",        { XM, EXq } },
10202   },
10203   {
10204     /* MOD_0F17 */
10205     { "movhpX",         { EXq, XM } },
10206   },
10207   {
10208     /* MOD_0F18_REG_0 */
10209     { "prefetchnta",    { Mb } },
10210   },
10211   {
10212     /* MOD_0F18_REG_1 */
10213     { "prefetcht0",     { Mb } },
10214   },
10215   {
10216     /* MOD_0F18_REG_2 */
10217     { "prefetcht1",     { Mb } },
10218   },
10219   {
10220     /* MOD_0F18_REG_3 */
10221     { "prefetcht2",     { Mb } },
10222   },
10223   {
10224     /* MOD_0F20 */
10225     { Bad_Opcode },
10226     { "movZ",           { Rm, Cm } },
10227   },
10228   {
10229     /* MOD_0F21 */
10230     { Bad_Opcode },
10231     { "movZ",           { Rm, Dm } },
10232   },
10233   {
10234     /* MOD_0F22 */
10235     { Bad_Opcode },
10236     { "movZ",           { Cm, Rm } },
10237   },
10238   {
10239     /* MOD_0F23 */
10240     { Bad_Opcode },
10241     { "movZ",           { Dm, Rm } },
10242   },
10243   {
10244     /* MOD_0F24 */
10245     { Bad_Opcode },
10246     { "movL",           { Rd, Td } },
10247   },
10248   {
10249     /* MOD_0F26 */
10250     { Bad_Opcode },
10251     { "movL",           { Td, Rd } },
10252   },
10253   {
10254     /* MOD_0F2B_PREFIX_0 */
10255     {"movntps",         { Mx, XM } },
10256   },
10257   {
10258     /* MOD_0F2B_PREFIX_1 */
10259     {"movntss",         { Md, XM } },
10260   },
10261   {
10262     /* MOD_0F2B_PREFIX_2 */
10263     {"movntpd",         { Mx, XM } },
10264   },
10265   {
10266     /* MOD_0F2B_PREFIX_3 */
10267     {"movntsd",         { Mq, XM } },
10268   },
10269   {
10270     /* MOD_0F51 */
10271     { Bad_Opcode },
10272     { "movmskpX",       { Gdq, XS } },
10273   },
10274   {
10275     /* MOD_0F71_REG_2 */
10276     { Bad_Opcode },
10277     { "psrlw",          { MS, Ib } },
10278   },
10279   {
10280     /* MOD_0F71_REG_4 */
10281     { Bad_Opcode },
10282     { "psraw",          { MS, Ib } },
10283   },
10284   {
10285     /* MOD_0F71_REG_6 */
10286     { Bad_Opcode },
10287     { "psllw",          { MS, Ib } },
10288   },
10289   {
10290     /* MOD_0F72_REG_2 */
10291     { Bad_Opcode },
10292     { "psrld",          { MS, Ib } },
10293   },
10294   {
10295     /* MOD_0F72_REG_4 */
10296     { Bad_Opcode },
10297     { "psrad",          { MS, Ib } },
10298   },
10299   {
10300     /* MOD_0F72_REG_6 */
10301     { Bad_Opcode },
10302     { "pslld",          { MS, Ib } },
10303   },
10304   {
10305     /* MOD_0F73_REG_2 */
10306     { Bad_Opcode },
10307     { "psrlq",          { MS, Ib } },
10308   },
10309   {
10310     /* MOD_0F73_REG_3 */
10311     { Bad_Opcode },
10312     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10313   },
10314   {
10315     /* MOD_0F73_REG_6 */
10316     { Bad_Opcode },
10317     { "psllq",          { MS, Ib } },
10318   },
10319   {
10320     /* MOD_0F73_REG_7 */
10321     { Bad_Opcode },
10322     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10323   },
10324   {
10325     /* MOD_0FAE_REG_0 */
10326     { "fxsave",         { FXSAVE } },
10327     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10328   },
10329   {
10330     /* MOD_0FAE_REG_1 */
10331     { "fxrstor",        { FXSAVE } },
10332     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10333   },
10334   {
10335     /* MOD_0FAE_REG_2 */
10336     { "ldmxcsr",        { Md } },
10337     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10338   },
10339   {
10340     /* MOD_0FAE_REG_3 */
10341     { "stmxcsr",        { Md } },
10342     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10343   },
10344   {
10345     /* MOD_0FAE_REG_4 */
10346     { "xsave",          { FXSAVE } },
10347   },
10348   {
10349     /* MOD_0FAE_REG_5 */
10350     { "xrstor",         { FXSAVE } },
10351     { RM_TABLE (RM_0FAE_REG_5) },
10352   },
10353   {
10354     /* MOD_0FAE_REG_6 */
10355     { "xsaveopt",       { FXSAVE } },
10356     { RM_TABLE (RM_0FAE_REG_6) },
10357   },
10358   {
10359     /* MOD_0FAE_REG_7 */
10360     { "clflush",        { Mb } },
10361     { RM_TABLE (RM_0FAE_REG_7) },
10362   },
10363   {
10364     /* MOD_0FB2 */
10365     { "lssS",           { Gv, Mp } },
10366   },
10367   {
10368     /* MOD_0FB4 */
10369     { "lfsS",           { Gv, Mp } },
10370   },
10371   {
10372     /* MOD_0FB5 */
10373     { "lgsS",           { Gv, Mp } },
10374   },
10375   {
10376     /* MOD_0FC7_REG_6 */
10377     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10378     { "rdrand",         { Ev } },
10379   },
10380   {
10381     /* MOD_0FC7_REG_7 */
10382     { "vmptrst",        { Mq } },
10383     { "rdseed",         { Ev } },
10384   },
10385   {
10386     /* MOD_0FD7 */
10387     { Bad_Opcode },
10388     { "pmovmskb",       { Gdq, MS } },
10389   },
10390   {
10391     /* MOD_0FE7_PREFIX_2 */
10392     { "movntdq",        { Mx, XM } },
10393   },
10394   {
10395     /* MOD_0FF0_PREFIX_3 */
10396     { "lddqu",          { XM, M } },
10397   },
10398   {
10399     /* MOD_0F382A_PREFIX_2 */
10400     { "movntdqa",       { XM, Mx } },
10401   },
10402   {
10403     /* MOD_62_32BIT */
10404     { "bound{S|}",      { Gv, Ma } },
10405   },
10406   {
10407     /* MOD_C4_32BIT */
10408     { "lesS",           { Gv, Mp } },
10409     { VEX_C4_TABLE (VEX_0F) },
10410   },
10411   {
10412     /* MOD_C5_32BIT */
10413     { "ldsS",           { Gv, Mp } },
10414     { VEX_C5_TABLE (VEX_0F) },
10415   },
10416   {
10417     /* MOD_VEX_0F12_PREFIX_0 */
10418     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10419     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10420   },
10421   {
10422     /* MOD_VEX_0F13 */
10423     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10424   },
10425   {
10426     /* MOD_VEX_0F16_PREFIX_0 */
10427     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10428     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10429   },
10430   {
10431     /* MOD_VEX_0F17 */
10432     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10433   },
10434   {
10435     /* MOD_VEX_0F2B */
10436     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10437   },
10438   {
10439     /* MOD_VEX_0F50 */
10440     { Bad_Opcode },
10441     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10442   },
10443   {
10444     /* MOD_VEX_0F71_REG_2 */
10445     { Bad_Opcode },
10446     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10447   },
10448   {
10449     /* MOD_VEX_0F71_REG_4 */
10450     { Bad_Opcode },
10451     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10452   },
10453   {
10454     /* MOD_VEX_0F71_REG_6 */
10455     { Bad_Opcode },
10456     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10457   },
10458   {
10459     /* MOD_VEX_0F72_REG_2 */
10460     { Bad_Opcode },
10461     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10462   },
10463   {
10464     /* MOD_VEX_0F72_REG_4 */
10465     { Bad_Opcode },
10466     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10467   },
10468   {
10469     /* MOD_VEX_0F72_REG_6 */
10470     { Bad_Opcode },
10471     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10472   },
10473   {
10474     /* MOD_VEX_0F73_REG_2 */
10475     { Bad_Opcode },
10476     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10477   },
10478   {
10479     /* MOD_VEX_0F73_REG_3 */
10480     { Bad_Opcode },
10481     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10482   },
10483   {
10484     /* MOD_VEX_0F73_REG_6 */
10485     { Bad_Opcode },
10486     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10487   },
10488   {
10489     /* MOD_VEX_0F73_REG_7 */
10490     { Bad_Opcode },
10491     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10492   },
10493   {
10494     /* MOD_VEX_0FAE_REG_2 */
10495     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10496   },
10497   {
10498     /* MOD_VEX_0FAE_REG_3 */
10499     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10500   },
10501   {
10502     /* MOD_VEX_0FD7_PREFIX_2 */
10503     { Bad_Opcode },
10504     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10505   },
10506   {
10507     /* MOD_VEX_0FE7_PREFIX_2 */
10508     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10509   },
10510   {
10511     /* MOD_VEX_0FF0_PREFIX_3 */
10512     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10513   },
10514   {
10515     /* MOD_VEX_0F381A_PREFIX_2 */
10516     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10517   },
10518   {
10519     /* MOD_VEX_0F382A_PREFIX_2 */
10520     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10521   },
10522   {
10523     /* MOD_VEX_0F382C_PREFIX_2 */
10524     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10525   },
10526   {
10527     /* MOD_VEX_0F382D_PREFIX_2 */
10528     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10529   },
10530   {
10531     /* MOD_VEX_0F382E_PREFIX_2 */
10532     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10533   },
10534   {
10535     /* MOD_VEX_0F382F_PREFIX_2 */
10536     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10537   },
10538   {
10539     /* MOD_VEX_0F385A_PREFIX_2 */
10540     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10541   },
10542   {
10543     /* MOD_VEX_0F388C_PREFIX_2 */
10544     { "vpmaskmov%LW",   { XM, Vex, Mx } },
10545   },
10546   {
10547     /* MOD_VEX_0F388E_PREFIX_2 */
10548     { "vpmaskmov%LW",   { Mx, Vex, XM } },
10549   },
10550 };
10551
10552 static const struct dis386 rm_table[][8] = {
10553   {
10554     /* RM_C6_REG_7 */
10555     { "xabort",         { Skip_MODRM, Ib } },
10556   },
10557   {
10558     /* RM_C7_REG_7 */
10559     { "xbeginT",        { Skip_MODRM, Jv } },
10560   },
10561   {
10562     /* RM_0F01_REG_0 */
10563     { Bad_Opcode },
10564     { "vmcall",         { Skip_MODRM } },
10565     { "vmlaunch",       { Skip_MODRM } },
10566     { "vmresume",       { Skip_MODRM } },
10567     { "vmxoff",         { Skip_MODRM } },
10568   },
10569   {
10570     /* RM_0F01_REG_1 */
10571     { "monitor",        { { OP_Monitor, 0 } } },
10572     { "mwait",          { { OP_Mwait, 0 } } },
10573   },
10574   {
10575     /* RM_0F01_REG_2 */
10576     { "xgetbv",         { Skip_MODRM } },
10577     { "xsetbv",         { Skip_MODRM } },
10578     { Bad_Opcode },
10579     { Bad_Opcode },
10580     { "vmfunc",         { Skip_MODRM } },
10581     { "xend",           { Skip_MODRM } },
10582     { "xtest",          { Skip_MODRM } },
10583     { Bad_Opcode },
10584   },
10585   {
10586     /* RM_0F01_REG_3 */
10587     { "vmrun",          { Skip_MODRM } },
10588     { "vmmcall",        { Skip_MODRM } },
10589     { "vmload",         { Skip_MODRM } },
10590     { "vmsave",         { Skip_MODRM } },
10591     { "stgi",           { Skip_MODRM } },
10592     { "clgi",           { Skip_MODRM } },
10593     { "skinit",         { Skip_MODRM } },
10594     { "invlpga",        { Skip_MODRM } },
10595   },
10596   {
10597     /* RM_0F01_REG_7 */
10598     { "swapgs",         { Skip_MODRM } },
10599     { "rdtscp",         { Skip_MODRM } },
10600   },
10601   {
10602     /* RM_0FAE_REG_5 */
10603     { "lfence",         { Skip_MODRM } },
10604   },
10605   {
10606     /* RM_0FAE_REG_6 */
10607     { "mfence",         { Skip_MODRM } },
10608   },
10609   {
10610     /* RM_0FAE_REG_7 */
10611     { "sfence",         { Skip_MODRM } },
10612   },
10613 };
10614
10615 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10616
10617 /* We use the high bit to indicate different name for the same
10618    prefix.  */
10619 #define ADDR16_PREFIX   (0x67 | 0x100)
10620 #define ADDR32_PREFIX   (0x67 | 0x200)
10621 #define DATA16_PREFIX   (0x66 | 0x100)
10622 #define DATA32_PREFIX   (0x66 | 0x200)
10623 #define REP_PREFIX      (0xf3 | 0x100)
10624 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10625 #define XRELEASE_PREFIX (0xf3 | 0x400)
10626
10627 static int
10628 ckprefix (void)
10629 {
10630   int newrex, i, length;
10631   rex = 0;
10632   rex_ignored = 0;
10633   prefixes = 0;
10634   used_prefixes = 0;
10635   rex_used = 0;
10636   last_lock_prefix = -1;
10637   last_repz_prefix = -1;
10638   last_repnz_prefix = -1;
10639   last_data_prefix = -1;
10640   last_addr_prefix = -1;
10641   last_rex_prefix = -1;
10642   last_seg_prefix = -1;
10643   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10644     all_prefixes[i] = 0;
10645   i = 0;
10646   length = 0;
10647   /* The maximum instruction length is 15bytes.  */
10648   while (length < MAX_CODE_LENGTH - 1)
10649     {
10650       FETCH_DATA (the_info, codep + 1);
10651       newrex = 0;
10652       switch (*codep)
10653         {
10654         /* REX prefixes family.  */
10655         case 0x40:
10656         case 0x41:
10657         case 0x42:
10658         case 0x43:
10659         case 0x44:
10660         case 0x45:
10661         case 0x46:
10662         case 0x47:
10663         case 0x48:
10664         case 0x49:
10665         case 0x4a:
10666         case 0x4b:
10667         case 0x4c:
10668         case 0x4d:
10669         case 0x4e:
10670         case 0x4f:
10671           if (address_mode == mode_64bit)
10672             newrex = *codep;
10673           else
10674             return 1;
10675           last_rex_prefix = i;
10676           break;
10677         case 0xf3:
10678           prefixes |= PREFIX_REPZ;
10679           last_repz_prefix = i;
10680           break;
10681         case 0xf2:
10682           prefixes |= PREFIX_REPNZ;
10683           last_repnz_prefix = i;
10684           break;
10685         case 0xf0:
10686           prefixes |= PREFIX_LOCK;
10687           last_lock_prefix = i;
10688           break;
10689         case 0x2e:
10690           prefixes |= PREFIX_CS;
10691           last_seg_prefix = i;
10692           break;
10693         case 0x36:
10694           prefixes |= PREFIX_SS;
10695           last_seg_prefix = i;
10696           break;
10697         case 0x3e:
10698           prefixes |= PREFIX_DS;
10699           last_seg_prefix = i;
10700           break;
10701         case 0x26:
10702           prefixes |= PREFIX_ES;
10703           last_seg_prefix = i;
10704           break;
10705         case 0x64:
10706           prefixes |= PREFIX_FS;
10707           last_seg_prefix = i;
10708           break;
10709         case 0x65:
10710           prefixes |= PREFIX_GS;
10711           last_seg_prefix = i;
10712           break;
10713         case 0x66:
10714           prefixes |= PREFIX_DATA;
10715           last_data_prefix = i;
10716           break;
10717         case 0x67:
10718           prefixes |= PREFIX_ADDR;
10719           last_addr_prefix = i;
10720           break;
10721         case FWAIT_OPCODE:
10722           /* fwait is really an instruction.  If there are prefixes
10723              before the fwait, they belong to the fwait, *not* to the
10724              following instruction.  */
10725           if (prefixes || rex)
10726             {
10727               prefixes |= PREFIX_FWAIT;
10728               codep++;
10729               return 1;
10730             }
10731           prefixes = PREFIX_FWAIT;
10732           break;
10733         default:
10734           return 1;
10735         }
10736       /* Rex is ignored when followed by another prefix.  */
10737       if (rex)
10738         {
10739           rex_used = rex;
10740           return 1;
10741         }
10742       if (*codep != FWAIT_OPCODE)
10743         all_prefixes[i++] = *codep;
10744       rex = newrex;
10745       codep++;
10746       length++;
10747     }
10748   return 0;
10749 }
10750
10751 static int
10752 seg_prefix (int pref)
10753 {
10754   switch (pref)
10755     {
10756     case 0x2e:
10757       return PREFIX_CS;
10758     case 0x36:
10759       return PREFIX_SS;
10760     case 0x3e:
10761       return PREFIX_DS;
10762     case 0x26:
10763       return PREFIX_ES;
10764     case 0x64:
10765       return PREFIX_FS;
10766     case 0x65:
10767       return PREFIX_GS;
10768     default:
10769       return 0;
10770     }
10771 }
10772
10773 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10774    prefix byte.  */
10775
10776 static const char *
10777 prefix_name (int pref, int sizeflag)
10778 {
10779   static const char *rexes [16] =
10780     {
10781       "rex",            /* 0x40 */
10782       "rex.B",          /* 0x41 */
10783       "rex.X",          /* 0x42 */
10784       "rex.XB",         /* 0x43 */
10785       "rex.R",          /* 0x44 */
10786       "rex.RB",         /* 0x45 */
10787       "rex.RX",         /* 0x46 */
10788       "rex.RXB",        /* 0x47 */
10789       "rex.W",          /* 0x48 */
10790       "rex.WB",         /* 0x49 */
10791       "rex.WX",         /* 0x4a */
10792       "rex.WXB",        /* 0x4b */
10793       "rex.WR",         /* 0x4c */
10794       "rex.WRB",        /* 0x4d */
10795       "rex.WRX",        /* 0x4e */
10796       "rex.WRXB",       /* 0x4f */
10797     };
10798
10799   switch (pref)
10800     {
10801     /* REX prefixes family.  */
10802     case 0x40:
10803     case 0x41:
10804     case 0x42:
10805     case 0x43:
10806     case 0x44:
10807     case 0x45:
10808     case 0x46:
10809     case 0x47:
10810     case 0x48:
10811     case 0x49:
10812     case 0x4a:
10813     case 0x4b:
10814     case 0x4c:
10815     case 0x4d:
10816     case 0x4e:
10817     case 0x4f:
10818       return rexes [pref - 0x40];
10819     case 0xf3:
10820       return "repz";
10821     case 0xf2:
10822       return "repnz";
10823     case 0xf0:
10824       return "lock";
10825     case 0x2e:
10826       return "cs";
10827     case 0x36:
10828       return "ss";
10829     case 0x3e:
10830       return "ds";
10831     case 0x26:
10832       return "es";
10833     case 0x64:
10834       return "fs";
10835     case 0x65:
10836       return "gs";
10837     case 0x66:
10838       return (sizeflag & DFLAG) ? "data16" : "data32";
10839     case 0x67:
10840       if (address_mode == mode_64bit)
10841         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10842       else
10843         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10844     case FWAIT_OPCODE:
10845       return "fwait";
10846     case ADDR16_PREFIX:
10847       return "addr16";
10848     case ADDR32_PREFIX:
10849       return "addr32";
10850     case DATA16_PREFIX:
10851       return "data16";
10852     case DATA32_PREFIX:
10853       return "data32";
10854     case REP_PREFIX:
10855       return "rep";
10856     case XACQUIRE_PREFIX:
10857       return "xacquire";
10858     case XRELEASE_PREFIX:
10859       return "xrelease";
10860     default:
10861       return NULL;
10862     }
10863 }
10864
10865 static char op_out[MAX_OPERANDS][100];
10866 static int op_ad, op_index[MAX_OPERANDS];
10867 static int two_source_ops;
10868 static bfd_vma op_address[MAX_OPERANDS];
10869 static bfd_vma op_riprel[MAX_OPERANDS];
10870 static bfd_vma start_pc;
10871
10872 /*
10873  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10874  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10875  *   section of the "Virtual 8086 Mode" chapter.)
10876  * 'pc' should be the address of this instruction, it will
10877  *   be used to print the target address if this is a relative jump or call
10878  * The function returns the length of this instruction in bytes.
10879  */
10880
10881 static char intel_syntax;
10882 static char intel_mnemonic = !SYSV386_COMPAT;
10883 static char open_char;
10884 static char close_char;
10885 static char separator_char;
10886 static char scale_char;
10887
10888 /* Here for backwards compatibility.  When gdb stops using
10889    print_insn_i386_att and print_insn_i386_intel these functions can
10890    disappear, and print_insn_i386 be merged into print_insn.  */
10891 int
10892 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10893 {
10894   intel_syntax = 0;
10895
10896   return print_insn (pc, info);
10897 }
10898
10899 int
10900 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10901 {
10902   intel_syntax = 1;
10903
10904   return print_insn (pc, info);
10905 }
10906
10907 int
10908 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10909 {
10910   intel_syntax = -1;
10911
10912   return print_insn (pc, info);
10913 }
10914
10915 void
10916 print_i386_disassembler_options (FILE *stream)
10917 {
10918   fprintf (stream, _("\n\
10919 The following i386/x86-64 specific disassembler options are supported for use\n\
10920 with the -M switch (multiple options should be separated by commas):\n"));
10921
10922   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10923   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10924   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10925   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10926   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10927   fprintf (stream, _("  att-mnemonic\n"
10928                      "              Display instruction in AT&T mnemonic\n"));
10929   fprintf (stream, _("  intel-mnemonic\n"
10930                      "              Display instruction in Intel mnemonic\n"));
10931   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10932   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10933   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10934   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10935   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10936   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10937 }
10938
10939 /* Bad opcode.  */
10940 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10941
10942 /* Get a pointer to struct dis386 with a valid name.  */
10943
10944 static const struct dis386 *
10945 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10946 {
10947   int vindex, vex_table_index;
10948
10949   if (dp->name != NULL)
10950     return dp;
10951
10952   switch (dp->op[0].bytemode)
10953     {
10954     case USE_REG_TABLE:
10955       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10956       break;
10957
10958     case USE_MOD_TABLE:
10959       vindex = modrm.mod == 0x3 ? 1 : 0;
10960       dp = &mod_table[dp->op[1].bytemode][vindex];
10961       break;
10962
10963     case USE_RM_TABLE:
10964       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10965       break;
10966
10967     case USE_PREFIX_TABLE:
10968       if (need_vex)
10969         {
10970           /* The prefix in VEX is implicit.  */
10971           switch (vex.prefix)
10972             {
10973             case 0:
10974               vindex = 0;
10975               break;
10976             case REPE_PREFIX_OPCODE:
10977               vindex = 1;
10978               break;
10979             case DATA_PREFIX_OPCODE:
10980               vindex = 2;
10981               break;
10982             case REPNE_PREFIX_OPCODE:
10983               vindex = 3;
10984               break;
10985             default:
10986               abort ();
10987               break;
10988             }
10989         }
10990       else
10991         {
10992           vindex = 0;
10993           used_prefixes |= (prefixes & PREFIX_REPZ);
10994           if (prefixes & PREFIX_REPZ)
10995             {
10996               vindex = 1;
10997               all_prefixes[last_repz_prefix] = 0;
10998             }
10999           else
11000             {
11001               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11002                  PREFIX_DATA.  */
11003               used_prefixes |= (prefixes & PREFIX_REPNZ);
11004               if (prefixes & PREFIX_REPNZ)
11005                 {
11006                   vindex = 3;
11007                   all_prefixes[last_repnz_prefix] = 0;
11008                 }
11009               else
11010                 {
11011                   used_prefixes |= (prefixes & PREFIX_DATA);
11012                   if (prefixes & PREFIX_DATA)
11013                     {
11014                       vindex = 2;
11015                       all_prefixes[last_data_prefix] = 0;
11016                     }
11017                 }
11018             }
11019         }
11020       dp = &prefix_table[dp->op[1].bytemode][vindex];
11021       break;
11022
11023     case USE_X86_64_TABLE:
11024       vindex = address_mode == mode_64bit ? 1 : 0;
11025       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11026       break;
11027
11028     case USE_3BYTE_TABLE:
11029       FETCH_DATA (info, codep + 2);
11030       vindex = *codep++;
11031       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11032       modrm.mod = (*codep >> 6) & 3;
11033       modrm.reg = (*codep >> 3) & 7;
11034       modrm.rm = *codep & 7;
11035       break;
11036
11037     case USE_VEX_LEN_TABLE:
11038       if (!need_vex)
11039         abort ();
11040
11041       switch (vex.length)
11042         {
11043         case 128:
11044           vindex = 0;
11045           break;
11046         case 256:
11047           vindex = 1;
11048           break;
11049         default:
11050           abort ();
11051           break;
11052         }
11053
11054       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11055       break;
11056
11057     case USE_XOP_8F_TABLE:
11058       FETCH_DATA (info, codep + 3);
11059       /* All bits in the REX prefix are ignored.  */
11060       rex_ignored = rex;
11061       rex = ~(*codep >> 5) & 0x7;
11062
11063       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11064       switch ((*codep & 0x1f))
11065         {
11066         default:
11067           dp = &bad_opcode;
11068           return dp;
11069         case 0x8:
11070           vex_table_index = XOP_08;
11071           break;
11072         case 0x9:
11073           vex_table_index = XOP_09;
11074           break;
11075         case 0xa:
11076           vex_table_index = XOP_0A;
11077           break;
11078         }
11079       codep++;
11080       vex.w = *codep & 0x80;
11081       if (vex.w && address_mode == mode_64bit)
11082         rex |= REX_W;
11083
11084       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11085       if (address_mode != mode_64bit
11086           && vex.register_specifier > 0x7)
11087         {
11088           dp = &bad_opcode;
11089           return dp;
11090         }
11091
11092       vex.length = (*codep & 0x4) ? 256 : 128;
11093       switch ((*codep & 0x3))
11094         {
11095         case 0:
11096           vex.prefix = 0;
11097           break;
11098         case 1:
11099           vex.prefix = DATA_PREFIX_OPCODE;
11100           break;
11101         case 2:
11102           vex.prefix = REPE_PREFIX_OPCODE;
11103           break;
11104         case 3:
11105           vex.prefix = REPNE_PREFIX_OPCODE;
11106           break;
11107         }
11108       need_vex = 1;
11109       need_vex_reg = 1;
11110       codep++;
11111       vindex = *codep++;
11112       dp = &xop_table[vex_table_index][vindex];
11113
11114       FETCH_DATA (info, codep + 1);
11115       modrm.mod = (*codep >> 6) & 3;
11116       modrm.reg = (*codep >> 3) & 7;
11117       modrm.rm = *codep & 7;
11118       break;
11119
11120     case USE_VEX_C4_TABLE:
11121       FETCH_DATA (info, codep + 3);
11122       /* All bits in the REX prefix are ignored.  */
11123       rex_ignored = rex;
11124       rex = ~(*codep >> 5) & 0x7;
11125       switch ((*codep & 0x1f))
11126         {
11127         default:
11128           dp = &bad_opcode;
11129           return dp;
11130         case 0x1:
11131           vex_table_index = VEX_0F;
11132           break;
11133         case 0x2:
11134           vex_table_index = VEX_0F38;
11135           break;
11136         case 0x3:
11137           vex_table_index = VEX_0F3A;
11138           break;
11139         }
11140       codep++;
11141       vex.w = *codep & 0x80;
11142       if (vex.w && address_mode == mode_64bit)
11143         rex |= REX_W;
11144
11145       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11146       if (address_mode != mode_64bit
11147           && vex.register_specifier > 0x7)
11148         {
11149           dp = &bad_opcode;
11150           return dp;
11151         }
11152
11153       vex.length = (*codep & 0x4) ? 256 : 128;
11154       switch ((*codep & 0x3))
11155         {
11156         case 0:
11157           vex.prefix = 0;
11158           break;
11159         case 1:
11160           vex.prefix = DATA_PREFIX_OPCODE;
11161           break;
11162         case 2:
11163           vex.prefix = REPE_PREFIX_OPCODE;
11164           break;
11165         case 3:
11166           vex.prefix = REPNE_PREFIX_OPCODE;
11167           break;
11168         }
11169       need_vex = 1;
11170       need_vex_reg = 1;
11171       codep++;
11172       vindex = *codep++;
11173       dp = &vex_table[vex_table_index][vindex];
11174       /* There is no MODRM byte for VEX [82|77].  */
11175       if (vindex != 0x77 && vindex != 0x82)
11176         {
11177           FETCH_DATA (info, codep + 1);
11178           modrm.mod = (*codep >> 6) & 3;
11179           modrm.reg = (*codep >> 3) & 7;
11180           modrm.rm = *codep & 7;
11181         }
11182       break;
11183
11184     case USE_VEX_C5_TABLE:
11185       FETCH_DATA (info, codep + 2);
11186       /* All bits in the REX prefix are ignored.  */
11187       rex_ignored = rex;
11188       rex = (*codep & 0x80) ? 0 : REX_R;
11189
11190       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11191       if (address_mode != mode_64bit
11192           && vex.register_specifier > 0x7)
11193         {
11194           dp = &bad_opcode;
11195           return dp;
11196         }
11197
11198       vex.w = 0;
11199
11200       vex.length = (*codep & 0x4) ? 256 : 128;
11201       switch ((*codep & 0x3))
11202         {
11203         case 0:
11204           vex.prefix = 0;
11205           break;
11206         case 1:
11207           vex.prefix = DATA_PREFIX_OPCODE;
11208           break;
11209         case 2:
11210           vex.prefix = REPE_PREFIX_OPCODE;
11211           break;
11212         case 3:
11213           vex.prefix = REPNE_PREFIX_OPCODE;
11214           break;
11215         }
11216       need_vex = 1;
11217       need_vex_reg = 1;
11218       codep++;
11219       vindex = *codep++;
11220       dp = &vex_table[dp->op[1].bytemode][vindex];
11221       /* There is no MODRM byte for VEX [82|77].  */
11222       if (vindex != 0x77 && vindex != 0x82)
11223         {
11224           FETCH_DATA (info, codep + 1);
11225           modrm.mod = (*codep >> 6) & 3;
11226           modrm.reg = (*codep >> 3) & 7;
11227           modrm.rm = *codep & 7;
11228         }
11229       break;
11230
11231     case USE_VEX_W_TABLE:
11232       if (!need_vex)
11233         abort ();
11234
11235       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11236       break;
11237
11238     case 0:
11239       dp = &bad_opcode;
11240       break;
11241
11242     default:
11243       abort ();
11244     }
11245
11246   if (dp->name != NULL)
11247     return dp;
11248   else
11249     return get_valid_dis386 (dp, info);
11250 }
11251
11252 static void
11253 get_sib (disassemble_info *info)
11254 {
11255   /* If modrm.mod == 3, operand must be register.  */
11256   if (need_modrm
11257       && address_mode != mode_16bit
11258       && modrm.mod != 3
11259       && modrm.rm == 4)
11260     {
11261       FETCH_DATA (info, codep + 2);
11262       sib.index = (codep [1] >> 3) & 7;
11263       sib.scale = (codep [1] >> 6) & 3;
11264       sib.base = codep [1] & 7;
11265     }
11266 }
11267
11268 static int
11269 print_insn (bfd_vma pc, disassemble_info *info)
11270 {
11271   const struct dis386 *dp;
11272   int i;
11273   char *op_txt[MAX_OPERANDS];
11274   int needcomma;
11275   int sizeflag;
11276   const char *p;
11277   struct dis_private priv;
11278   int prefix_length;
11279   int default_prefixes;
11280
11281   priv.orig_sizeflag = AFLAG | DFLAG;
11282   if ((info->mach & bfd_mach_i386_i386) != 0)
11283     address_mode = mode_32bit;
11284   else if (info->mach == bfd_mach_i386_i8086)
11285     {
11286       address_mode = mode_16bit;
11287       priv.orig_sizeflag = 0;
11288     }
11289   else
11290     address_mode = mode_64bit;
11291
11292   if (intel_syntax == (char) -1)
11293     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11294
11295   for (p = info->disassembler_options; p != NULL; )
11296     {
11297       if (CONST_STRNEQ (p, "x86-64"))
11298         {
11299           address_mode = mode_64bit;
11300           priv.orig_sizeflag = AFLAG | DFLAG;
11301         }
11302       else if (CONST_STRNEQ (p, "i386"))
11303         {
11304           address_mode = mode_32bit;
11305           priv.orig_sizeflag = AFLAG | DFLAG;
11306         }
11307       else if (CONST_STRNEQ (p, "i8086"))
11308         {
11309           address_mode = mode_16bit;
11310           priv.orig_sizeflag = 0;
11311         }
11312       else if (CONST_STRNEQ (p, "intel"))
11313         {
11314           intel_syntax = 1;
11315           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11316             intel_mnemonic = 1;
11317         }
11318       else if (CONST_STRNEQ (p, "att"))
11319         {
11320           intel_syntax = 0;
11321           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11322             intel_mnemonic = 0;
11323         }
11324       else if (CONST_STRNEQ (p, "addr"))
11325         {
11326           if (address_mode == mode_64bit)
11327             {
11328               if (p[4] == '3' && p[5] == '2')
11329                 priv.orig_sizeflag &= ~AFLAG;
11330               else if (p[4] == '6' && p[5] == '4')
11331                 priv.orig_sizeflag |= AFLAG;
11332             }
11333           else
11334             {
11335               if (p[4] == '1' && p[5] == '6')
11336                 priv.orig_sizeflag &= ~AFLAG;
11337               else if (p[4] == '3' && p[5] == '2')
11338                 priv.orig_sizeflag |= AFLAG;
11339             }
11340         }
11341       else if (CONST_STRNEQ (p, "data"))
11342         {
11343           if (p[4] == '1' && p[5] == '6')
11344             priv.orig_sizeflag &= ~DFLAG;
11345           else if (p[4] == '3' && p[5] == '2')
11346             priv.orig_sizeflag |= DFLAG;
11347         }
11348       else if (CONST_STRNEQ (p, "suffix"))
11349         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11350
11351       p = strchr (p, ',');
11352       if (p != NULL)
11353         p++;
11354     }
11355
11356   if (intel_syntax)
11357     {
11358       names64 = intel_names64;
11359       names32 = intel_names32;
11360       names16 = intel_names16;
11361       names8 = intel_names8;
11362       names8rex = intel_names8rex;
11363       names_seg = intel_names_seg;
11364       names_mm = intel_names_mm;
11365       names_xmm = intel_names_xmm;
11366       names_ymm = intel_names_ymm;
11367       index64 = intel_index64;
11368       index32 = intel_index32;
11369       index16 = intel_index16;
11370       open_char = '[';
11371       close_char = ']';
11372       separator_char = '+';
11373       scale_char = '*';
11374     }
11375   else
11376     {
11377       names64 = att_names64;
11378       names32 = att_names32;
11379       names16 = att_names16;
11380       names8 = att_names8;
11381       names8rex = att_names8rex;
11382       names_seg = att_names_seg;
11383       names_mm = att_names_mm;
11384       names_xmm = att_names_xmm;
11385       names_ymm = att_names_ymm;
11386       index64 = att_index64;
11387       index32 = att_index32;
11388       index16 = att_index16;
11389       open_char = '(';
11390       close_char =  ')';
11391       separator_char = ',';
11392       scale_char = ',';
11393     }
11394
11395   /* The output looks better if we put 7 bytes on a line, since that
11396      puts most long word instructions on a single line.  Use 8 bytes
11397      for Intel L1OM.  */
11398   if ((info->mach & bfd_mach_l1om) != 0)
11399     info->bytes_per_line = 8;
11400   else
11401     info->bytes_per_line = 7;
11402
11403   info->private_data = &priv;
11404   priv.max_fetched = priv.the_buffer;
11405   priv.insn_start = pc;
11406
11407   obuf[0] = 0;
11408   for (i = 0; i < MAX_OPERANDS; ++i)
11409     {
11410       op_out[i][0] = 0;
11411       op_index[i] = -1;
11412     }
11413
11414   the_info = info;
11415   start_pc = pc;
11416   start_codep = priv.the_buffer;
11417   codep = priv.the_buffer;
11418
11419   if (setjmp (priv.bailout) != 0)
11420     {
11421       const char *name;
11422
11423       /* Getting here means we tried for data but didn't get it.  That
11424          means we have an incomplete instruction of some sort.  Just
11425          print the first byte as a prefix or a .byte pseudo-op.  */
11426       if (codep > priv.the_buffer)
11427         {
11428           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11429           if (name != NULL)
11430             (*info->fprintf_func) (info->stream, "%s", name);
11431           else
11432             {
11433               /* Just print the first byte as a .byte instruction.  */
11434               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11435                                      (unsigned int) priv.the_buffer[0]);
11436             }
11437
11438           return 1;
11439         }
11440
11441       return -1;
11442     }
11443
11444   obufp = obuf;
11445   sizeflag = priv.orig_sizeflag;
11446
11447   if (!ckprefix () || rex_used)
11448     {
11449       /* Too many prefixes or unused REX prefixes.  */
11450       for (i = 0;
11451            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11452            i++)
11453         (*info->fprintf_func) (info->stream, "%s",
11454                                prefix_name (all_prefixes[i], sizeflag));
11455       return 1;
11456     }
11457
11458   insn_codep = codep;
11459
11460   FETCH_DATA (info, codep + 1);
11461   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11462
11463   if (((prefixes & PREFIX_FWAIT)
11464        && ((*codep < 0xd8) || (*codep > 0xdf))))
11465     {
11466       (*info->fprintf_func) (info->stream, "fwait");
11467       return 1;
11468     }
11469
11470   if (*codep == 0x0f)
11471     {
11472       unsigned char threebyte;
11473       FETCH_DATA (info, codep + 2);
11474       threebyte = *++codep;
11475       dp = &dis386_twobyte[threebyte];
11476       need_modrm = twobyte_has_modrm[*codep];
11477       codep++;
11478     }
11479   else
11480     {
11481       dp = &dis386[*codep];
11482       need_modrm = onebyte_has_modrm[*codep];
11483       codep++;
11484     }
11485
11486   if ((prefixes & PREFIX_REPZ))
11487     used_prefixes |= PREFIX_REPZ;
11488   if ((prefixes & PREFIX_REPNZ))
11489     used_prefixes |= PREFIX_REPNZ;
11490   if ((prefixes & PREFIX_LOCK))
11491     used_prefixes |= PREFIX_LOCK;
11492
11493   default_prefixes = 0;
11494   if (prefixes & PREFIX_ADDR)
11495     {
11496       sizeflag ^= AFLAG;
11497       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11498         {
11499           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11500             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11501           else
11502             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11503           default_prefixes |= PREFIX_ADDR;
11504         }
11505     }
11506
11507   if ((prefixes & PREFIX_DATA))
11508     {
11509       sizeflag ^= DFLAG;
11510       if (dp->op[2].bytemode == cond_jump_mode
11511           && dp->op[0].bytemode == v_mode
11512           && !intel_syntax)
11513         {
11514           if (sizeflag & DFLAG)
11515             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11516           else
11517             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11518           default_prefixes |= PREFIX_DATA;
11519         }
11520       else if (rex & REX_W)
11521         {
11522           /* REX_W will override PREFIX_DATA.  */
11523           default_prefixes |= PREFIX_DATA;
11524         }
11525     }
11526
11527   if (need_modrm)
11528     {
11529       FETCH_DATA (info, codep + 1);
11530       modrm.mod = (*codep >> 6) & 3;
11531       modrm.reg = (*codep >> 3) & 7;
11532       modrm.rm = *codep & 7;
11533     }
11534
11535   need_vex = 0;
11536   need_vex_reg = 0;
11537   vex_w_done = 0;
11538
11539   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11540     {
11541       get_sib (info);
11542       dofloat (sizeflag);
11543     }
11544   else
11545     {
11546       dp = get_valid_dis386 (dp, info);
11547       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11548         {
11549           get_sib (info);
11550           for (i = 0; i < MAX_OPERANDS; ++i)
11551             {
11552               obufp = op_out[i];
11553               op_ad = MAX_OPERANDS - 1 - i;
11554               if (dp->op[i].rtn)
11555                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11556             }
11557         }
11558     }
11559
11560   /* See if any prefixes were not used.  If so, print the first one
11561      separately.  If we don't do this, we'll wind up printing an
11562      instruction stream which does not precisely correspond to the
11563      bytes we are disassembling.  */
11564   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11565     {
11566       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11567         if (all_prefixes[i])
11568           {
11569             const char *name;
11570             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11571             if (name == NULL)
11572               name = INTERNAL_DISASSEMBLER_ERROR;
11573             (*info->fprintf_func) (info->stream, "%s", name);
11574             return 1;
11575           }
11576     }
11577
11578   /* Check if the REX prefix is used.  */
11579   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11580     all_prefixes[last_rex_prefix] = 0;
11581
11582   /* Check if the SEG prefix is used.  */
11583   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11584                    | PREFIX_FS | PREFIX_GS)) != 0
11585       && (used_prefixes
11586           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11587     all_prefixes[last_seg_prefix] = 0;
11588
11589   /* Check if the ADDR prefix is used.  */
11590   if ((prefixes & PREFIX_ADDR) != 0
11591       && (used_prefixes & PREFIX_ADDR) != 0)
11592     all_prefixes[last_addr_prefix] = 0;
11593
11594   /* Check if the DATA prefix is used.  */
11595   if ((prefixes & PREFIX_DATA) != 0
11596       && (used_prefixes & PREFIX_DATA) != 0)
11597     all_prefixes[last_data_prefix] = 0;
11598
11599   prefix_length = 0;
11600   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11601     if (all_prefixes[i])
11602       {
11603         const char *name;
11604         name = prefix_name (all_prefixes[i], sizeflag);
11605         if (name == NULL)
11606           abort ();
11607         prefix_length += strlen (name) + 1;
11608         (*info->fprintf_func) (info->stream, "%s ", name);
11609       }
11610
11611   /* Check maximum code length.  */
11612   if ((codep - start_codep) > MAX_CODE_LENGTH)
11613     {
11614       (*info->fprintf_func) (info->stream, "(bad)");
11615       return MAX_CODE_LENGTH;
11616     }
11617
11618   obufp = mnemonicendp;
11619   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11620     oappend (" ");
11621   oappend (" ");
11622   (*info->fprintf_func) (info->stream, "%s", obuf);
11623
11624   /* The enter and bound instructions are printed with operands in the same
11625      order as the intel book; everything else is printed in reverse order.  */
11626   if (intel_syntax || two_source_ops)
11627     {
11628       bfd_vma riprel;
11629
11630       for (i = 0; i < MAX_OPERANDS; ++i)
11631         op_txt[i] = op_out[i];
11632
11633       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11634         {
11635           op_ad = op_index[i];
11636           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11637           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11638           riprel = op_riprel[i];
11639           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11640           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11641         }
11642     }
11643   else
11644     {
11645       for (i = 0; i < MAX_OPERANDS; ++i)
11646         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11647     }
11648
11649   needcomma = 0;
11650   for (i = 0; i < MAX_OPERANDS; ++i)
11651     if (*op_txt[i])
11652       {
11653         if (needcomma)
11654           (*info->fprintf_func) (info->stream, ",");
11655         if (op_index[i] != -1 && !op_riprel[i])
11656           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11657         else
11658           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11659         needcomma = 1;
11660       }
11661
11662   for (i = 0; i < MAX_OPERANDS; i++)
11663     if (op_index[i] != -1 && op_riprel[i])
11664       {
11665         (*info->fprintf_func) (info->stream, "        # ");
11666         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11667                                                 + op_address[op_index[i]]), info);
11668         break;
11669       }
11670   return codep - priv.the_buffer;
11671 }
11672
11673 static const char *float_mem[] = {
11674   /* d8 */
11675   "fadd{s|}",
11676   "fmul{s|}",
11677   "fcom{s|}",
11678   "fcomp{s|}",
11679   "fsub{s|}",
11680   "fsubr{s|}",
11681   "fdiv{s|}",
11682   "fdivr{s|}",
11683   /* d9 */
11684   "fld{s|}",
11685   "(bad)",
11686   "fst{s|}",
11687   "fstp{s|}",
11688   "fldenvIC",
11689   "fldcw",
11690   "fNstenvIC",
11691   "fNstcw",
11692   /* da */
11693   "fiadd{l|}",
11694   "fimul{l|}",
11695   "ficom{l|}",
11696   "ficomp{l|}",
11697   "fisub{l|}",
11698   "fisubr{l|}",
11699   "fidiv{l|}",
11700   "fidivr{l|}",
11701   /* db */
11702   "fild{l|}",
11703   "fisttp{l|}",
11704   "fist{l|}",
11705   "fistp{l|}",
11706   "(bad)",
11707   "fld{t||t|}",
11708   "(bad)",
11709   "fstp{t||t|}",
11710   /* dc */
11711   "fadd{l|}",
11712   "fmul{l|}",
11713   "fcom{l|}",
11714   "fcomp{l|}",
11715   "fsub{l|}",
11716   "fsubr{l|}",
11717   "fdiv{l|}",
11718   "fdivr{l|}",
11719   /* dd */
11720   "fld{l|}",
11721   "fisttp{ll|}",
11722   "fst{l||}",
11723   "fstp{l|}",
11724   "frstorIC",
11725   "(bad)",
11726   "fNsaveIC",
11727   "fNstsw",
11728   /* de */
11729   "fiadd",
11730   "fimul",
11731   "ficom",
11732   "ficomp",
11733   "fisub",
11734   "fisubr",
11735   "fidiv",
11736   "fidivr",
11737   /* df */
11738   "fild",
11739   "fisttp",
11740   "fist",
11741   "fistp",
11742   "fbld",
11743   "fild{ll|}",
11744   "fbstp",
11745   "fistp{ll|}",
11746 };
11747
11748 static const unsigned char float_mem_mode[] = {
11749   /* d8 */
11750   d_mode,
11751   d_mode,
11752   d_mode,
11753   d_mode,
11754   d_mode,
11755   d_mode,
11756   d_mode,
11757   d_mode,
11758   /* d9 */
11759   d_mode,
11760   0,
11761   d_mode,
11762   d_mode,
11763   0,
11764   w_mode,
11765   0,
11766   w_mode,
11767   /* da */
11768   d_mode,
11769   d_mode,
11770   d_mode,
11771   d_mode,
11772   d_mode,
11773   d_mode,
11774   d_mode,
11775   d_mode,
11776   /* db */
11777   d_mode,
11778   d_mode,
11779   d_mode,
11780   d_mode,
11781   0,
11782   t_mode,
11783   0,
11784   t_mode,
11785   /* dc */
11786   q_mode,
11787   q_mode,
11788   q_mode,
11789   q_mode,
11790   q_mode,
11791   q_mode,
11792   q_mode,
11793   q_mode,
11794   /* dd */
11795   q_mode,
11796   q_mode,
11797   q_mode,
11798   q_mode,
11799   0,
11800   0,
11801   0,
11802   w_mode,
11803   /* de */
11804   w_mode,
11805   w_mode,
11806   w_mode,
11807   w_mode,
11808   w_mode,
11809   w_mode,
11810   w_mode,
11811   w_mode,
11812   /* df */
11813   w_mode,
11814   w_mode,
11815   w_mode,
11816   w_mode,
11817   t_mode,
11818   q_mode,
11819   t_mode,
11820   q_mode
11821 };
11822
11823 #define ST { OP_ST, 0 }
11824 #define STi { OP_STi, 0 }
11825
11826 #define FGRPd9_2 NULL, { { NULL, 0 } }
11827 #define FGRPd9_4 NULL, { { NULL, 1 } }
11828 #define FGRPd9_5 NULL, { { NULL, 2 } }
11829 #define FGRPd9_6 NULL, { { NULL, 3 } }
11830 #define FGRPd9_7 NULL, { { NULL, 4 } }
11831 #define FGRPda_5 NULL, { { NULL, 5 } }
11832 #define FGRPdb_4 NULL, { { NULL, 6 } }
11833 #define FGRPde_3 NULL, { { NULL, 7 } }
11834 #define FGRPdf_4 NULL, { { NULL, 8 } }
11835
11836 static const struct dis386 float_reg[][8] = {
11837   /* d8 */
11838   {
11839     { "fadd",   { ST, STi } },
11840     { "fmul",   { ST, STi } },
11841     { "fcom",   { STi } },
11842     { "fcomp",  { STi } },
11843     { "fsub",   { ST, STi } },
11844     { "fsubr",  { ST, STi } },
11845     { "fdiv",   { ST, STi } },
11846     { "fdivr",  { ST, STi } },
11847   },
11848   /* d9 */
11849   {
11850     { "fld",    { STi } },
11851     { "fxch",   { STi } },
11852     { FGRPd9_2 },
11853     { Bad_Opcode },
11854     { FGRPd9_4 },
11855     { FGRPd9_5 },
11856     { FGRPd9_6 },
11857     { FGRPd9_7 },
11858   },
11859   /* da */
11860   {
11861     { "fcmovb", { ST, STi } },
11862     { "fcmove", { ST, STi } },
11863     { "fcmovbe",{ ST, STi } },
11864     { "fcmovu", { ST, STi } },
11865     { Bad_Opcode },
11866     { FGRPda_5 },
11867     { Bad_Opcode },
11868     { Bad_Opcode },
11869   },
11870   /* db */
11871   {
11872     { "fcmovnb",{ ST, STi } },
11873     { "fcmovne",{ ST, STi } },
11874     { "fcmovnbe",{ ST, STi } },
11875     { "fcmovnu",{ ST, STi } },
11876     { FGRPdb_4 },
11877     { "fucomi", { ST, STi } },
11878     { "fcomi",  { ST, STi } },
11879     { Bad_Opcode },
11880   },
11881   /* dc */
11882   {
11883     { "fadd",   { STi, ST } },
11884     { "fmul",   { STi, ST } },
11885     { Bad_Opcode },
11886     { Bad_Opcode },
11887     { "fsub!M", { STi, ST } },
11888     { "fsubM",  { STi, ST } },
11889     { "fdiv!M", { STi, ST } },
11890     { "fdivM",  { STi, ST } },
11891   },
11892   /* dd */
11893   {
11894     { "ffree",  { STi } },
11895     { Bad_Opcode },
11896     { "fst",    { STi } },
11897     { "fstp",   { STi } },
11898     { "fucom",  { STi } },
11899     { "fucomp", { STi } },
11900     { Bad_Opcode },
11901     { Bad_Opcode },
11902   },
11903   /* de */
11904   {
11905     { "faddp",  { STi, ST } },
11906     { "fmulp",  { STi, ST } },
11907     { Bad_Opcode },
11908     { FGRPde_3 },
11909     { "fsub!Mp", { STi, ST } },
11910     { "fsubMp", { STi, ST } },
11911     { "fdiv!Mp", { STi, ST } },
11912     { "fdivMp", { STi, ST } },
11913   },
11914   /* df */
11915   {
11916     { "ffreep", { STi } },
11917     { Bad_Opcode },
11918     { Bad_Opcode },
11919     { Bad_Opcode },
11920     { FGRPdf_4 },
11921     { "fucomip", { ST, STi } },
11922     { "fcomip", { ST, STi } },
11923     { Bad_Opcode },
11924   },
11925 };
11926
11927 static char *fgrps[][8] = {
11928   /* d9_2  0 */
11929   {
11930     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11931   },
11932
11933   /* d9_4  1 */
11934   {
11935     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11936   },
11937
11938   /* d9_5  2 */
11939   {
11940     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11941   },
11942
11943   /* d9_6  3 */
11944   {
11945     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11946   },
11947
11948   /* d9_7  4 */
11949   {
11950     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11951   },
11952
11953   /* da_5  5 */
11954   {
11955     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11956   },
11957
11958   /* db_4  6 */
11959   {
11960     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11961     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11962   },
11963
11964   /* de_3  7 */
11965   {
11966     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11967   },
11968
11969   /* df_4  8 */
11970   {
11971     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11972   },
11973 };
11974
11975 static void
11976 swap_operand (void)
11977 {
11978   mnemonicendp[0] = '.';
11979   mnemonicendp[1] = 's';
11980   mnemonicendp += 2;
11981 }
11982
11983 static void
11984 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11985                int sizeflag ATTRIBUTE_UNUSED)
11986 {
11987   /* Skip mod/rm byte.  */
11988   MODRM_CHECK;
11989   codep++;
11990 }
11991
11992 static void
11993 dofloat (int sizeflag)
11994 {
11995   const struct dis386 *dp;
11996   unsigned char floatop;
11997
11998   floatop = codep[-1];
11999
12000   if (modrm.mod != 3)
12001     {
12002       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12003
12004       putop (float_mem[fp_indx], sizeflag);
12005       obufp = op_out[0];
12006       op_ad = 2;
12007       OP_E (float_mem_mode[fp_indx], sizeflag);
12008       return;
12009     }
12010   /* Skip mod/rm byte.  */
12011   MODRM_CHECK;
12012   codep++;
12013
12014   dp = &float_reg[floatop - 0xd8][modrm.reg];
12015   if (dp->name == NULL)
12016     {
12017       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12018
12019       /* Instruction fnstsw is only one with strange arg.  */
12020       if (floatop == 0xdf && codep[-1] == 0xe0)
12021         strcpy (op_out[0], names16[0]);
12022     }
12023   else
12024     {
12025       putop (dp->name, sizeflag);
12026
12027       obufp = op_out[0];
12028       op_ad = 2;
12029       if (dp->op[0].rtn)
12030         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12031
12032       obufp = op_out[1];
12033       op_ad = 1;
12034       if (dp->op[1].rtn)
12035         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12036     }
12037 }
12038
12039 static void
12040 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12041 {
12042   oappend ("%st" + intel_syntax);
12043 }
12044
12045 static void
12046 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12047 {
12048   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12049   oappend (scratchbuf + intel_syntax);
12050 }
12051
12052 /* Capital letters in template are macros.  */
12053 static int
12054 putop (const char *in_template, int sizeflag)
12055 {
12056   const char *p;
12057   int alt = 0;
12058   int cond = 1;
12059   unsigned int l = 0, len = 1;
12060   char last[4];
12061
12062 #define SAVE_LAST(c)                    \
12063   if (l < len && l < sizeof (last))     \
12064     last[l++] = c;                      \
12065   else                                  \
12066     abort ();
12067
12068   for (p = in_template; *p; p++)
12069     {
12070       switch (*p)
12071         {
12072         default:
12073           *obufp++ = *p;
12074           break;
12075         case '%':
12076           len++;
12077           break;
12078         case '!':
12079           cond = 0;
12080           break;
12081         case '{':
12082           alt = 0;
12083           if (intel_syntax)
12084             {
12085               while (*++p != '|')
12086                 if (*p == '}' || *p == '\0')
12087                   abort ();
12088             }
12089           /* Fall through.  */
12090         case 'I':
12091           alt = 1;
12092           continue;
12093         case '|':
12094           while (*++p != '}')
12095             {
12096               if (*p == '\0')
12097                 abort ();
12098             }
12099           break;
12100         case '}':
12101           break;
12102         case 'A':
12103           if (intel_syntax)
12104             break;
12105           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12106             *obufp++ = 'b';
12107           break;
12108         case 'B':
12109           if (l == 0 && len == 1)
12110             {
12111 case_B:
12112               if (intel_syntax)
12113                 break;
12114               if (sizeflag & SUFFIX_ALWAYS)
12115                 *obufp++ = 'b';
12116             }
12117           else
12118             {
12119               if (l != 1
12120                   || len != 2
12121                   || last[0] != 'L')
12122                 {
12123                   SAVE_LAST (*p);
12124                   break;
12125                 }
12126
12127               if (address_mode == mode_64bit
12128                   && !(prefixes & PREFIX_ADDR))
12129                 {
12130                   *obufp++ = 'a';
12131                   *obufp++ = 'b';
12132                   *obufp++ = 's';
12133                 }
12134
12135               goto case_B;
12136             }
12137           break;
12138         case 'C':
12139           if (intel_syntax && !alt)
12140             break;
12141           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12142             {
12143               if (sizeflag & DFLAG)
12144                 *obufp++ = intel_syntax ? 'd' : 'l';
12145               else
12146                 *obufp++ = intel_syntax ? 'w' : 's';
12147               used_prefixes |= (prefixes & PREFIX_DATA);
12148             }
12149           break;
12150         case 'D':
12151           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12152             break;
12153           USED_REX (REX_W);
12154           if (modrm.mod == 3)
12155             {
12156               if (rex & REX_W)
12157                 *obufp++ = 'q';
12158               else
12159                 {
12160                   if (sizeflag & DFLAG)
12161                     *obufp++ = intel_syntax ? 'd' : 'l';
12162                   else
12163                     *obufp++ = 'w';
12164                   used_prefixes |= (prefixes & PREFIX_DATA);
12165                 }
12166             }
12167           else
12168             *obufp++ = 'w';
12169           break;
12170         case 'E':               /* For jcxz/jecxz */
12171           if (address_mode == mode_64bit)
12172             {
12173               if (sizeflag & AFLAG)
12174                 *obufp++ = 'r';
12175               else
12176                 *obufp++ = 'e';
12177             }
12178           else
12179             if (sizeflag & AFLAG)
12180               *obufp++ = 'e';
12181           used_prefixes |= (prefixes & PREFIX_ADDR);
12182           break;
12183         case 'F':
12184           if (intel_syntax)
12185             break;
12186           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12187             {
12188               if (sizeflag & AFLAG)
12189                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12190               else
12191                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12192               used_prefixes |= (prefixes & PREFIX_ADDR);
12193             }
12194           break;
12195         case 'G':
12196           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12197             break;
12198           if ((rex & REX_W) || (sizeflag & DFLAG))
12199             *obufp++ = 'l';
12200           else
12201             *obufp++ = 'w';
12202           if (!(rex & REX_W))
12203             used_prefixes |= (prefixes & PREFIX_DATA);
12204           break;
12205         case 'H':
12206           if (intel_syntax)
12207             break;
12208           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12209               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12210             {
12211               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12212               *obufp++ = ',';
12213               *obufp++ = 'p';
12214               if (prefixes & PREFIX_DS)
12215                 *obufp++ = 't';
12216               else
12217                 *obufp++ = 'n';
12218             }
12219           break;
12220         case 'J':
12221           if (intel_syntax)
12222             break;
12223           *obufp++ = 'l';
12224           break;
12225         case 'K':
12226           USED_REX (REX_W);
12227           if (rex & REX_W)
12228             *obufp++ = 'q';
12229           else
12230             *obufp++ = 'd';
12231           break;
12232         case 'Z':
12233           if (intel_syntax)
12234             break;
12235           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12236             {
12237               *obufp++ = 'q';
12238               break;
12239             }
12240           /* Fall through.  */
12241           goto case_L;
12242         case 'L':
12243           if (l != 0 || len != 1)
12244             {
12245               SAVE_LAST (*p);
12246               break;
12247             }
12248 case_L:
12249           if (intel_syntax)
12250             break;
12251           if (sizeflag & SUFFIX_ALWAYS)
12252             *obufp++ = 'l';
12253           break;
12254         case 'M':
12255           if (intel_mnemonic != cond)
12256             *obufp++ = 'r';
12257           break;
12258         case 'N':
12259           if ((prefixes & PREFIX_FWAIT) == 0)
12260             *obufp++ = 'n';
12261           else
12262             used_prefixes |= PREFIX_FWAIT;
12263           break;
12264         case 'O':
12265           USED_REX (REX_W);
12266           if (rex & REX_W)
12267             *obufp++ = 'o';
12268           else if (intel_syntax && (sizeflag & DFLAG))
12269             *obufp++ = 'q';
12270           else
12271             *obufp++ = 'd';
12272           if (!(rex & REX_W))
12273             used_prefixes |= (prefixes & PREFIX_DATA);
12274           break;
12275         case 'T':
12276           if (!intel_syntax
12277               && address_mode == mode_64bit
12278               && (sizeflag & DFLAG))
12279             {
12280               *obufp++ = 'q';
12281               break;
12282             }
12283           /* Fall through.  */
12284         case 'P':
12285           if (intel_syntax)
12286             {
12287               if ((rex & REX_W) == 0
12288                   && (prefixes & PREFIX_DATA))
12289                 {
12290                   if ((sizeflag & DFLAG) == 0)
12291                     *obufp++ = 'w';
12292                    used_prefixes |= (prefixes & PREFIX_DATA);
12293                 }
12294               break;
12295             }
12296           if ((prefixes & PREFIX_DATA)
12297               || (rex & REX_W)
12298               || (sizeflag & SUFFIX_ALWAYS))
12299             {
12300               USED_REX (REX_W);
12301               if (rex & REX_W)
12302                 *obufp++ = 'q';
12303               else
12304                 {
12305                    if (sizeflag & DFLAG)
12306                       *obufp++ = 'l';
12307                    else
12308                      *obufp++ = 'w';
12309                    used_prefixes |= (prefixes & PREFIX_DATA);
12310                 }
12311             }
12312           break;
12313         case 'U':
12314           if (intel_syntax)
12315             break;
12316           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12317             {
12318               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12319                 *obufp++ = 'q';
12320               break;
12321             }
12322           /* Fall through.  */
12323           goto case_Q;
12324         case 'Q':
12325           if (l == 0 && len == 1)
12326             {
12327 case_Q:
12328               if (intel_syntax && !alt)
12329                 break;
12330               USED_REX (REX_W);
12331               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12332                 {
12333                   if (rex & REX_W)
12334                     *obufp++ = 'q';
12335                   else
12336                     {
12337                       if (sizeflag & DFLAG)
12338                         *obufp++ = intel_syntax ? 'd' : 'l';
12339                       else
12340                         *obufp++ = 'w';
12341                       used_prefixes |= (prefixes & PREFIX_DATA);
12342                     }
12343                 }
12344             }
12345           else
12346             {
12347               if (l != 1 || len != 2 || last[0] != 'L')
12348                 {
12349                   SAVE_LAST (*p);
12350                   break;
12351                 }
12352               if (intel_syntax
12353                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12354                 break;
12355               if ((rex & REX_W))
12356                 {
12357                   USED_REX (REX_W);
12358                   *obufp++ = 'q';
12359                 }
12360               else
12361                 *obufp++ = 'l';
12362             }
12363           break;
12364         case 'R':
12365           USED_REX (REX_W);
12366           if (rex & REX_W)
12367             *obufp++ = 'q';
12368           else if (sizeflag & DFLAG)
12369             {
12370               if (intel_syntax)
12371                   *obufp++ = 'd';
12372               else
12373                   *obufp++ = 'l';
12374             }
12375           else
12376             *obufp++ = 'w';
12377           if (intel_syntax && !p[1]
12378               && ((rex & REX_W) || (sizeflag & DFLAG)))
12379             *obufp++ = 'e';
12380           if (!(rex & REX_W))
12381             used_prefixes |= (prefixes & PREFIX_DATA);
12382           break;
12383         case 'V':
12384           if (l == 0 && len == 1)
12385             {
12386               if (intel_syntax)
12387                 break;
12388               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12389                 {
12390                   if (sizeflag & SUFFIX_ALWAYS)
12391                     *obufp++ = 'q';
12392                   break;
12393                 }
12394             }
12395           else
12396             {
12397               if (l != 1
12398                   || len != 2
12399                   || last[0] != 'L')
12400                 {
12401                   SAVE_LAST (*p);
12402                   break;
12403                 }
12404
12405               if (rex & REX_W)
12406                 {
12407                   *obufp++ = 'a';
12408                   *obufp++ = 'b';
12409                   *obufp++ = 's';
12410                 }
12411             }
12412           /* Fall through.  */
12413           goto case_S;
12414         case 'S':
12415           if (l == 0 && len == 1)
12416             {
12417 case_S:
12418               if (intel_syntax)
12419                 break;
12420               if (sizeflag & SUFFIX_ALWAYS)
12421                 {
12422                   if (rex & REX_W)
12423                     *obufp++ = 'q';
12424                   else
12425                     {
12426                       if (sizeflag & DFLAG)
12427                         *obufp++ = 'l';
12428                       else
12429                         *obufp++ = 'w';
12430                       used_prefixes |= (prefixes & PREFIX_DATA);
12431                     }
12432                 }
12433             }
12434           else
12435             {
12436               if (l != 1
12437                   || len != 2
12438                   || last[0] != 'L')
12439                 {
12440                   SAVE_LAST (*p);
12441                   break;
12442                 }
12443
12444               if (address_mode == mode_64bit
12445                   && !(prefixes & PREFIX_ADDR))
12446                 {
12447                   *obufp++ = 'a';
12448                   *obufp++ = 'b';
12449                   *obufp++ = 's';
12450                 }
12451
12452               goto case_S;
12453             }
12454           break;
12455         case 'X':
12456           if (l != 0 || len != 1)
12457             {
12458               SAVE_LAST (*p);
12459               break;
12460             }
12461           if (need_vex && vex.prefix)
12462             {
12463               if (vex.prefix == DATA_PREFIX_OPCODE)
12464                 *obufp++ = 'd';
12465               else
12466                 *obufp++ = 's';
12467             }
12468           else
12469             {
12470               if (prefixes & PREFIX_DATA)
12471                 *obufp++ = 'd';
12472               else
12473                 *obufp++ = 's';
12474               used_prefixes |= (prefixes & PREFIX_DATA);
12475             }
12476           break;
12477         case 'Y':
12478           if (l == 0 && len == 1)
12479             {
12480               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12481                 break;
12482               if (rex & REX_W)
12483                 {
12484                   USED_REX (REX_W);
12485                   *obufp++ = 'q';
12486                 }
12487               break;
12488             }
12489           else
12490             {
12491               if (l != 1 || len != 2 || last[0] != 'X')
12492                 {
12493                   SAVE_LAST (*p);
12494                   break;
12495                 }
12496               if (!need_vex)
12497                 abort ();
12498               if (intel_syntax
12499                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12500                 break;
12501               switch (vex.length)
12502                 {
12503                 case 128:
12504                   *obufp++ = 'x';
12505                   break;
12506                 case 256:
12507                   *obufp++ = 'y';
12508                   break;
12509                 default:
12510                   abort ();
12511                 }
12512             }
12513           break;
12514         case 'W':
12515           if (l == 0 && len == 1)
12516             {
12517               /* operand size flag for cwtl, cbtw */
12518               USED_REX (REX_W);
12519               if (rex & REX_W)
12520                 {
12521                   if (intel_syntax)
12522                     *obufp++ = 'd';
12523                   else
12524                     *obufp++ = 'l';
12525                 }
12526               else if (sizeflag & DFLAG)
12527                 *obufp++ = 'w';
12528               else
12529                 *obufp++ = 'b';
12530               if (!(rex & REX_W))
12531                 used_prefixes |= (prefixes & PREFIX_DATA);
12532             }
12533           else
12534             {
12535               if (l != 1
12536                   || len != 2
12537                   || (last[0] != 'X'
12538                       && last[0] != 'L'))
12539                 {
12540                   SAVE_LAST (*p);
12541                   break;
12542                 }
12543               if (!need_vex)
12544                 abort ();
12545               if (last[0] == 'X')
12546                 *obufp++ = vex.w ? 'd': 's';
12547               else
12548                 *obufp++ = vex.w ? 'q': 'd';
12549             }
12550           break;
12551         }
12552       alt = 0;
12553     }
12554   *obufp = 0;
12555   mnemonicendp = obufp;
12556   return 0;
12557 }
12558
12559 static void
12560 oappend (const char *s)
12561 {
12562   obufp = stpcpy (obufp, s);
12563 }
12564
12565 static void
12566 append_seg (void)
12567 {
12568   if (prefixes & PREFIX_CS)
12569     {
12570       used_prefixes |= PREFIX_CS;
12571       oappend ("%cs:" + intel_syntax);
12572     }
12573   if (prefixes & PREFIX_DS)
12574     {
12575       used_prefixes |= PREFIX_DS;
12576       oappend ("%ds:" + intel_syntax);
12577     }
12578   if (prefixes & PREFIX_SS)
12579     {
12580       used_prefixes |= PREFIX_SS;
12581       oappend ("%ss:" + intel_syntax);
12582     }
12583   if (prefixes & PREFIX_ES)
12584     {
12585       used_prefixes |= PREFIX_ES;
12586       oappend ("%es:" + intel_syntax);
12587     }
12588   if (prefixes & PREFIX_FS)
12589     {
12590       used_prefixes |= PREFIX_FS;
12591       oappend ("%fs:" + intel_syntax);
12592     }
12593   if (prefixes & PREFIX_GS)
12594     {
12595       used_prefixes |= PREFIX_GS;
12596       oappend ("%gs:" + intel_syntax);
12597     }
12598 }
12599
12600 static void
12601 OP_indirE (int bytemode, int sizeflag)
12602 {
12603   if (!intel_syntax)
12604     oappend ("*");
12605   OP_E (bytemode, sizeflag);
12606 }
12607
12608 static void
12609 print_operand_value (char *buf, int hex, bfd_vma disp)
12610 {
12611   if (address_mode == mode_64bit)
12612     {
12613       if (hex)
12614         {
12615           char tmp[30];
12616           int i;
12617           buf[0] = '0';
12618           buf[1] = 'x';
12619           sprintf_vma (tmp, disp);
12620           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12621           strcpy (buf + 2, tmp + i);
12622         }
12623       else
12624         {
12625           bfd_signed_vma v = disp;
12626           char tmp[30];
12627           int i;
12628           if (v < 0)
12629             {
12630               *(buf++) = '-';
12631               v = -disp;
12632               /* Check for possible overflow on 0x8000000000000000.  */
12633               if (v < 0)
12634                 {
12635                   strcpy (buf, "9223372036854775808");
12636                   return;
12637                 }
12638             }
12639           if (!v)
12640             {
12641               strcpy (buf, "0");
12642               return;
12643             }
12644
12645           i = 0;
12646           tmp[29] = 0;
12647           while (v)
12648             {
12649               tmp[28 - i] = (v % 10) + '0';
12650               v /= 10;
12651               i++;
12652             }
12653           strcpy (buf, tmp + 29 - i);
12654         }
12655     }
12656   else
12657     {
12658       if (hex)
12659         sprintf (buf, "0x%x", (unsigned int) disp);
12660       else
12661         sprintf (buf, "%d", (int) disp);
12662     }
12663 }
12664
12665 /* Put DISP in BUF as signed hex number.  */
12666
12667 static void
12668 print_displacement (char *buf, bfd_vma disp)
12669 {
12670   bfd_signed_vma val = disp;
12671   char tmp[30];
12672   int i, j = 0;
12673
12674   if (val < 0)
12675     {
12676       buf[j++] = '-';
12677       val = -disp;
12678
12679       /* Check for possible overflow.  */
12680       if (val < 0)
12681         {
12682           switch (address_mode)
12683             {
12684             case mode_64bit:
12685               strcpy (buf + j, "0x8000000000000000");
12686               break;
12687             case mode_32bit:
12688               strcpy (buf + j, "0x80000000");
12689               break;
12690             case mode_16bit:
12691               strcpy (buf + j, "0x8000");
12692               break;
12693             }
12694           return;
12695         }
12696     }
12697
12698   buf[j++] = '0';
12699   buf[j++] = 'x';
12700
12701   sprintf_vma (tmp, (bfd_vma) val);
12702   for (i = 0; tmp[i] == '0'; i++)
12703     continue;
12704   if (tmp[i] == '\0')
12705     i--;
12706   strcpy (buf + j, tmp + i);
12707 }
12708
12709 static void
12710 intel_operand_size (int bytemode, int sizeflag)
12711 {
12712   switch (bytemode)
12713     {
12714     case b_mode:
12715     case b_swap_mode:
12716     case dqb_mode:
12717       oappend ("BYTE PTR ");
12718       break;
12719     case w_mode:
12720     case dqw_mode:
12721       oappend ("WORD PTR ");
12722       break;
12723     case stack_v_mode:
12724       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12725         {
12726           oappend ("QWORD PTR ");
12727           break;
12728         }
12729       /* FALLTHRU */
12730     case v_mode:
12731     case v_swap_mode:
12732     case dq_mode:
12733       USED_REX (REX_W);
12734       if (rex & REX_W)
12735         oappend ("QWORD PTR ");
12736       else
12737         {
12738           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12739             oappend ("DWORD PTR ");
12740           else
12741             oappend ("WORD PTR ");
12742           used_prefixes |= (prefixes & PREFIX_DATA);
12743         }
12744       break;
12745     case z_mode:
12746       if ((rex & REX_W) || (sizeflag & DFLAG))
12747         *obufp++ = 'D';
12748       oappend ("WORD PTR ");
12749       if (!(rex & REX_W))
12750         used_prefixes |= (prefixes & PREFIX_DATA);
12751       break;
12752     case a_mode:
12753       if (sizeflag & DFLAG)
12754         oappend ("QWORD PTR ");
12755       else
12756         oappend ("DWORD PTR ");
12757       used_prefixes |= (prefixes & PREFIX_DATA);
12758       break;
12759     case d_mode:
12760     case d_scalar_mode:
12761     case d_scalar_swap_mode:
12762     case d_swap_mode:
12763     case dqd_mode:
12764       oappend ("DWORD PTR ");
12765       break;
12766     case q_mode:
12767     case q_scalar_mode:
12768     case q_scalar_swap_mode:
12769     case q_swap_mode:
12770       oappend ("QWORD PTR ");
12771       break;
12772     case m_mode:
12773       if (address_mode == mode_64bit)
12774         oappend ("QWORD PTR ");
12775       else
12776         oappend ("DWORD PTR ");
12777       break;
12778     case f_mode:
12779       if (sizeflag & DFLAG)
12780         oappend ("FWORD PTR ");
12781       else
12782         oappend ("DWORD PTR ");
12783       used_prefixes |= (prefixes & PREFIX_DATA);
12784       break;
12785     case t_mode:
12786       oappend ("TBYTE PTR ");
12787       break;
12788     case x_mode:
12789     case x_swap_mode:
12790       if (need_vex)
12791         {
12792           switch (vex.length)
12793             {
12794             case 128:
12795               oappend ("XMMWORD PTR ");
12796               break;
12797             case 256:
12798               oappend ("YMMWORD PTR ");
12799               break;
12800             default:
12801               abort ();
12802             }
12803         }
12804       else
12805         oappend ("XMMWORD PTR ");
12806       break;
12807     case xmm_mode:
12808       oappend ("XMMWORD PTR ");
12809       break;
12810     case xmmq_mode:
12811       if (!need_vex)
12812         abort ();
12813
12814       switch (vex.length)
12815         {
12816         case 128:
12817           oappend ("QWORD PTR ");
12818           break;
12819         case 256:
12820           oappend ("XMMWORD PTR ");
12821           break;
12822         default:
12823           abort ();
12824         }
12825       break;
12826     case xmm_mb_mode:
12827       if (!need_vex)
12828         abort ();
12829
12830       switch (vex.length)
12831         {
12832         case 128:
12833         case 256:
12834           oappend ("BYTE PTR ");
12835           break;
12836         default:
12837           abort ();
12838         }
12839       break;
12840     case xmm_mw_mode:
12841       if (!need_vex)
12842         abort ();
12843
12844       switch (vex.length)
12845         {
12846         case 128:
12847         case 256:
12848           oappend ("WORD PTR ");
12849           break;
12850         default:
12851           abort ();
12852         }
12853       break;
12854     case xmm_md_mode:
12855       if (!need_vex)
12856         abort ();
12857
12858       switch (vex.length)
12859         {
12860         case 128:
12861         case 256:
12862           oappend ("DWORD PTR ");
12863           break;
12864         default:
12865           abort ();
12866         }
12867       break;
12868     case xmm_mq_mode:
12869       if (!need_vex)
12870         abort ();
12871
12872       switch (vex.length)
12873         {
12874         case 128:
12875         case 256:
12876           oappend ("QWORD PTR ");
12877           break;
12878         default:
12879           abort ();
12880         }
12881       break;
12882     case xmmdw_mode:
12883       if (!need_vex)
12884         abort ();
12885
12886       switch (vex.length)
12887         {
12888         case 128:
12889           oappend ("WORD PTR ");
12890           break;
12891         case 256:
12892           oappend ("DWORD PTR ");
12893           break;
12894         default:
12895           abort ();
12896         }
12897       break;
12898     case xmmqd_mode:
12899       if (!need_vex)
12900         abort ();
12901
12902       switch (vex.length)
12903         {
12904         case 128:
12905           oappend ("DWORD PTR ");
12906           break;
12907         case 256:
12908           oappend ("QWORD PTR ");
12909           break;
12910         default:
12911           abort ();
12912         }
12913       break;
12914     case ymmq_mode:
12915       if (!need_vex)
12916         abort ();
12917
12918       switch (vex.length)
12919         {
12920         case 128:
12921           oappend ("QWORD PTR ");
12922           break;
12923         case 256:
12924           oappend ("YMMWORD PTR ");
12925           break;
12926         default:
12927           abort ();
12928         }
12929       break;
12930     case ymmxmm_mode:
12931       if (!need_vex)
12932         abort ();
12933
12934       switch (vex.length)
12935         {
12936         case 128:
12937         case 256:
12938           oappend ("XMMWORD PTR ");
12939           break;
12940         default:
12941           abort ();
12942         }
12943       break;
12944     case o_mode:
12945       oappend ("OWORD PTR ");
12946       break;
12947     case vex_w_dq_mode:
12948     case vex_scalar_w_dq_mode:
12949     case vex_vsib_d_w_dq_mode:
12950     case vex_vsib_q_w_dq_mode:
12951       if (!need_vex)
12952         abort ();
12953
12954       if (vex.w)
12955         oappend ("QWORD PTR ");
12956       else
12957         oappend ("DWORD PTR ");
12958       break;
12959     default:
12960       break;
12961     }
12962 }
12963
12964 static void
12965 OP_E_register (int bytemode, int sizeflag)
12966 {
12967   int reg = modrm.rm;
12968   const char **names;
12969
12970   USED_REX (REX_B);
12971   if ((rex & REX_B))
12972     reg += 8;
12973
12974   if ((sizeflag & SUFFIX_ALWAYS)
12975       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12976     swap_operand ();
12977
12978   switch (bytemode)
12979     {
12980     case b_mode:
12981     case b_swap_mode:
12982       USED_REX (0);
12983       if (rex)
12984         names = names8rex;
12985       else
12986         names = names8;
12987       break;
12988     case w_mode:
12989       names = names16;
12990       break;
12991     case d_mode:
12992       names = names32;
12993       break;
12994     case q_mode:
12995       names = names64;
12996       break;
12997     case m_mode:
12998       names = address_mode == mode_64bit ? names64 : names32;
12999       break;
13000     case stack_v_mode:
13001       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13002         {
13003           names = names64;
13004           break;
13005         }
13006       bytemode = v_mode;
13007       /* FALLTHRU */
13008     case v_mode:
13009     case v_swap_mode:
13010     case dq_mode:
13011     case dqb_mode:
13012     case dqd_mode:
13013     case dqw_mode:
13014       USED_REX (REX_W);
13015       if (rex & REX_W)
13016         names = names64;
13017       else
13018         {
13019           if ((sizeflag & DFLAG)
13020               || (bytemode != v_mode
13021                   && bytemode != v_swap_mode))
13022             names = names32;
13023           else
13024             names = names16;
13025           used_prefixes |= (prefixes & PREFIX_DATA);
13026         }
13027       break;
13028     case 0:
13029       return;
13030     default:
13031       oappend (INTERNAL_DISASSEMBLER_ERROR);
13032       return;
13033     }
13034   oappend (names[reg]);
13035 }
13036
13037 static void
13038 OP_E_memory (int bytemode, int sizeflag)
13039 {
13040   bfd_vma disp = 0;
13041   int add = (rex & REX_B) ? 8 : 0;
13042   int riprel = 0;
13043
13044   USED_REX (REX_B);
13045   if (intel_syntax)
13046     intel_operand_size (bytemode, sizeflag);
13047   append_seg ();
13048
13049   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13050     {
13051       /* 32/64 bit address mode */
13052       int havedisp;
13053       int havesib;
13054       int havebase;
13055       int haveindex;
13056       int needindex;
13057       int base, rbase;
13058       int vindex = 0;
13059       int scale = 0;
13060       const char **indexes64 = names64;
13061       const char **indexes32 = names32;
13062
13063       havesib = 0;
13064       havebase = 1;
13065       haveindex = 0;
13066       base = modrm.rm;
13067
13068       if (base == 4)
13069         {
13070           havesib = 1;
13071           vindex = sib.index;
13072           USED_REX (REX_X);
13073           if (rex & REX_X)
13074             vindex += 8;
13075           switch (bytemode)
13076             {
13077             case vex_vsib_d_w_dq_mode:
13078             case vex_vsib_q_w_dq_mode:
13079               if (!need_vex)
13080                 abort ();
13081
13082               haveindex = 1;
13083               switch (vex.length)
13084                 {
13085                 case 128:
13086                   indexes64 = indexes32 = names_xmm;
13087                   break;
13088                 case 256:
13089                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
13090                     indexes64 = indexes32 = names_ymm;
13091                   else
13092                     indexes64 = indexes32 = names_xmm;
13093                   break;
13094                 default:
13095                   abort ();
13096                 }
13097               break;
13098             default:
13099               haveindex = vindex != 4;
13100               break;
13101             }
13102           scale = sib.scale;
13103           base = sib.base;
13104           codep++;
13105         }
13106       rbase = base + add;
13107
13108       switch (modrm.mod)
13109         {
13110         case 0:
13111           if (base == 5)
13112             {
13113               havebase = 0;
13114               if (address_mode == mode_64bit && !havesib)
13115                 riprel = 1;
13116               disp = get32s ();
13117             }
13118           break;
13119         case 1:
13120           FETCH_DATA (the_info, codep + 1);
13121           disp = *codep++;
13122           if ((disp & 0x80) != 0)
13123             disp -= 0x100;
13124           break;
13125         case 2:
13126           disp = get32s ();
13127           break;
13128         }
13129
13130       /* In 32bit mode, we need index register to tell [offset] from
13131          [eiz*1 + offset].  */
13132       needindex = (havesib
13133                    && !havebase
13134                    && !haveindex
13135                    && address_mode == mode_32bit);
13136       havedisp = (havebase
13137                   || needindex
13138                   || (havesib && (haveindex || scale != 0)));
13139
13140       if (!intel_syntax)
13141         if (modrm.mod != 0 || base == 5)
13142           {
13143             if (havedisp || riprel)
13144               print_displacement (scratchbuf, disp);
13145             else
13146               print_operand_value (scratchbuf, 1, disp);
13147             oappend (scratchbuf);
13148             if (riprel)
13149               {
13150                 set_op (disp, 1);
13151                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13152               }
13153           }
13154
13155       if (havebase || haveindex || riprel)
13156         used_prefixes |= PREFIX_ADDR;
13157
13158       if (havedisp || (intel_syntax && riprel))
13159         {
13160           *obufp++ = open_char;
13161           if (intel_syntax && riprel)
13162             {
13163               set_op (disp, 1);
13164               oappend (sizeflag & AFLAG ? "rip" : "eip");
13165             }
13166           *obufp = '\0';
13167           if (havebase)
13168             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13169                      ? names64[rbase] : names32[rbase]);
13170           if (havesib)
13171             {
13172               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13173                  print index to tell base + index from base.  */
13174               if (scale != 0
13175                   || needindex
13176                   || haveindex
13177                   || (havebase && base != ESP_REG_NUM))
13178                 {
13179                   if (!intel_syntax || havebase)
13180                     {
13181                       *obufp++ = separator_char;
13182                       *obufp = '\0';
13183                     }
13184                   if (haveindex)
13185                     oappend (address_mode == mode_64bit
13186                              && (sizeflag & AFLAG)
13187                              ? indexes64[vindex] : indexes32[vindex]);
13188                   else
13189                     oappend (address_mode == mode_64bit
13190                              && (sizeflag & AFLAG)
13191                              ? index64 : index32);
13192
13193                   *obufp++ = scale_char;
13194                   *obufp = '\0';
13195                   sprintf (scratchbuf, "%d", 1 << scale);
13196                   oappend (scratchbuf);
13197                 }
13198             }
13199           if (intel_syntax
13200               && (disp || modrm.mod != 0 || base == 5))
13201             {
13202               if (!havedisp || (bfd_signed_vma) disp >= 0)
13203                 {
13204                   *obufp++ = '+';
13205                   *obufp = '\0';
13206                 }
13207               else if (modrm.mod != 1 && disp != -disp)
13208                 {
13209                   *obufp++ = '-';
13210                   *obufp = '\0';
13211                   disp = - (bfd_signed_vma) disp;
13212                 }
13213
13214               if (havedisp)
13215                 print_displacement (scratchbuf, disp);
13216               else
13217                 print_operand_value (scratchbuf, 1, disp);
13218               oappend (scratchbuf);
13219             }
13220
13221           *obufp++ = close_char;
13222           *obufp = '\0';
13223         }
13224       else if (intel_syntax)
13225         {
13226           if (modrm.mod != 0 || base == 5)
13227             {
13228               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13229                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13230                 ;
13231               else
13232                 {
13233                   oappend (names_seg[ds_reg - es_reg]);
13234                   oappend (":");
13235                 }
13236               print_operand_value (scratchbuf, 1, disp);
13237               oappend (scratchbuf);
13238             }
13239         }
13240     }
13241   else
13242     {
13243       /* 16 bit address mode */
13244       used_prefixes |= prefixes & PREFIX_ADDR;
13245       switch (modrm.mod)
13246         {
13247         case 0:
13248           if (modrm.rm == 6)
13249             {
13250               disp = get16 ();
13251               if ((disp & 0x8000) != 0)
13252                 disp -= 0x10000;
13253             }
13254           break;
13255         case 1:
13256           FETCH_DATA (the_info, codep + 1);
13257           disp = *codep++;
13258           if ((disp & 0x80) != 0)
13259             disp -= 0x100;
13260           break;
13261         case 2:
13262           disp = get16 ();
13263           if ((disp & 0x8000) != 0)
13264             disp -= 0x10000;
13265           break;
13266         }
13267
13268       if (!intel_syntax)
13269         if (modrm.mod != 0 || modrm.rm == 6)
13270           {
13271             print_displacement (scratchbuf, disp);
13272             oappend (scratchbuf);
13273           }
13274
13275       if (modrm.mod != 0 || modrm.rm != 6)
13276         {
13277           *obufp++ = open_char;
13278           *obufp = '\0';
13279           oappend (index16[modrm.rm]);
13280           if (intel_syntax
13281               && (disp || modrm.mod != 0 || modrm.rm == 6))
13282             {
13283               if ((bfd_signed_vma) disp >= 0)
13284                 {
13285                   *obufp++ = '+';
13286                   *obufp = '\0';
13287                 }
13288               else if (modrm.mod != 1)
13289                 {
13290                   *obufp++ = '-';
13291                   *obufp = '\0';
13292                   disp = - (bfd_signed_vma) disp;
13293                 }
13294
13295               print_displacement (scratchbuf, disp);
13296               oappend (scratchbuf);
13297             }
13298
13299           *obufp++ = close_char;
13300           *obufp = '\0';
13301         }
13302       else if (intel_syntax)
13303         {
13304           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13305                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13306             ;
13307           else
13308             {
13309               oappend (names_seg[ds_reg - es_reg]);
13310               oappend (":");
13311             }
13312           print_operand_value (scratchbuf, 1, disp & 0xffff);
13313           oappend (scratchbuf);
13314         }
13315     }
13316 }
13317
13318 static void
13319 OP_E (int bytemode, int sizeflag)
13320 {
13321   /* Skip mod/rm byte.  */
13322   MODRM_CHECK;
13323   codep++;
13324
13325   if (modrm.mod == 3)
13326     OP_E_register (bytemode, sizeflag);
13327   else
13328     OP_E_memory (bytemode, sizeflag);
13329 }
13330
13331 static void
13332 OP_G (int bytemode, int sizeflag)
13333 {
13334   int add = 0;
13335   USED_REX (REX_R);
13336   if (rex & REX_R)
13337     add += 8;
13338   switch (bytemode)
13339     {
13340     case b_mode:
13341       USED_REX (0);
13342       if (rex)
13343         oappend (names8rex[modrm.reg + add]);
13344       else
13345         oappend (names8[modrm.reg + add]);
13346       break;
13347     case w_mode:
13348       oappend (names16[modrm.reg + add]);
13349       break;
13350     case d_mode:
13351       oappend (names32[modrm.reg + add]);
13352       break;
13353     case q_mode:
13354       oappend (names64[modrm.reg + add]);
13355       break;
13356     case v_mode:
13357     case dq_mode:
13358     case dqb_mode:
13359     case dqd_mode:
13360     case dqw_mode:
13361       USED_REX (REX_W);
13362       if (rex & REX_W)
13363         oappend (names64[modrm.reg + add]);
13364       else
13365         {
13366           if ((sizeflag & DFLAG) || bytemode != v_mode)
13367             oappend (names32[modrm.reg + add]);
13368           else
13369             oappend (names16[modrm.reg + add]);
13370           used_prefixes |= (prefixes & PREFIX_DATA);
13371         }
13372       break;
13373     case m_mode:
13374       if (address_mode == mode_64bit)
13375         oappend (names64[modrm.reg + add]);
13376       else
13377         oappend (names32[modrm.reg + add]);
13378       break;
13379     default:
13380       oappend (INTERNAL_DISASSEMBLER_ERROR);
13381       break;
13382     }
13383 }
13384
13385 static bfd_vma
13386 get64 (void)
13387 {
13388   bfd_vma x;
13389 #ifdef BFD64
13390   unsigned int a;
13391   unsigned int b;
13392
13393   FETCH_DATA (the_info, codep + 8);
13394   a = *codep++ & 0xff;
13395   a |= (*codep++ & 0xff) << 8;
13396   a |= (*codep++ & 0xff) << 16;
13397   a |= (*codep++ & 0xff) << 24;
13398   b = *codep++ & 0xff;
13399   b |= (*codep++ & 0xff) << 8;
13400   b |= (*codep++ & 0xff) << 16;
13401   b |= (*codep++ & 0xff) << 24;
13402   x = a + ((bfd_vma) b << 32);
13403 #else
13404   abort ();
13405   x = 0;
13406 #endif
13407   return x;
13408 }
13409
13410 static bfd_signed_vma
13411 get32 (void)
13412 {
13413   bfd_signed_vma x = 0;
13414
13415   FETCH_DATA (the_info, codep + 4);
13416   x = *codep++ & (bfd_signed_vma) 0xff;
13417   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13418   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13419   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13420   return x;
13421 }
13422
13423 static bfd_signed_vma
13424 get32s (void)
13425 {
13426   bfd_signed_vma x = 0;
13427
13428   FETCH_DATA (the_info, codep + 4);
13429   x = *codep++ & (bfd_signed_vma) 0xff;
13430   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13431   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13432   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13433
13434   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13435
13436   return x;
13437 }
13438
13439 static int
13440 get16 (void)
13441 {
13442   int x = 0;
13443
13444   FETCH_DATA (the_info, codep + 2);
13445   x = *codep++ & 0xff;
13446   x |= (*codep++ & 0xff) << 8;
13447   return x;
13448 }
13449
13450 static void
13451 set_op (bfd_vma op, int riprel)
13452 {
13453   op_index[op_ad] = op_ad;
13454   if (address_mode == mode_64bit)
13455     {
13456       op_address[op_ad] = op;
13457       op_riprel[op_ad] = riprel;
13458     }
13459   else
13460     {
13461       /* Mask to get a 32-bit address.  */
13462       op_address[op_ad] = op & 0xffffffff;
13463       op_riprel[op_ad] = riprel & 0xffffffff;
13464     }
13465 }
13466
13467 static void
13468 OP_REG (int code, int sizeflag)
13469 {
13470   const char *s;
13471   int add;
13472   USED_REX (REX_B);
13473   if (rex & REX_B)
13474     add = 8;
13475   else
13476     add = 0;
13477
13478   switch (code)
13479     {
13480     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13481     case sp_reg: case bp_reg: case si_reg: case di_reg:
13482       s = names16[code - ax_reg + add];
13483       break;
13484     case es_reg: case ss_reg: case cs_reg:
13485     case ds_reg: case fs_reg: case gs_reg:
13486       s = names_seg[code - es_reg + add];
13487       break;
13488     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13489     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13490       USED_REX (0);
13491       if (rex)
13492         s = names8rex[code - al_reg + add];
13493       else
13494         s = names8[code - al_reg];
13495       break;
13496     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13497     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13498       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13499         {
13500           s = names64[code - rAX_reg + add];
13501           break;
13502         }
13503       code += eAX_reg - rAX_reg;
13504       /* Fall through.  */
13505     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13506     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13507       USED_REX (REX_W);
13508       if (rex & REX_W)
13509         s = names64[code - eAX_reg + add];
13510       else
13511         {
13512           if (sizeflag & DFLAG)
13513             s = names32[code - eAX_reg + add];
13514           else
13515             s = names16[code - eAX_reg + add];
13516           used_prefixes |= (prefixes & PREFIX_DATA);
13517         }
13518       break;
13519     default:
13520       s = INTERNAL_DISASSEMBLER_ERROR;
13521       break;
13522     }
13523   oappend (s);
13524 }
13525
13526 static void
13527 OP_IMREG (int code, int sizeflag)
13528 {
13529   const char *s;
13530
13531   switch (code)
13532     {
13533     case indir_dx_reg:
13534       if (intel_syntax)
13535         s = "dx";
13536       else
13537         s = "(%dx)";
13538       break;
13539     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13540     case sp_reg: case bp_reg: case si_reg: case di_reg:
13541       s = names16[code - ax_reg];
13542       break;
13543     case es_reg: case ss_reg: case cs_reg:
13544     case ds_reg: case fs_reg: case gs_reg:
13545       s = names_seg[code - es_reg];
13546       break;
13547     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13548     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13549       USED_REX (0);
13550       if (rex)
13551         s = names8rex[code - al_reg];
13552       else
13553         s = names8[code - al_reg];
13554       break;
13555     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13556     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13557       USED_REX (REX_W);
13558       if (rex & REX_W)
13559         s = names64[code - eAX_reg];
13560       else
13561         {
13562           if (sizeflag & DFLAG)
13563             s = names32[code - eAX_reg];
13564           else
13565             s = names16[code - eAX_reg];
13566           used_prefixes |= (prefixes & PREFIX_DATA);
13567         }
13568       break;
13569     case z_mode_ax_reg:
13570       if ((rex & REX_W) || (sizeflag & DFLAG))
13571         s = *names32;
13572       else
13573         s = *names16;
13574       if (!(rex & REX_W))
13575         used_prefixes |= (prefixes & PREFIX_DATA);
13576       break;
13577     default:
13578       s = INTERNAL_DISASSEMBLER_ERROR;
13579       break;
13580     }
13581   oappend (s);
13582 }
13583
13584 static void
13585 OP_I (int bytemode, int sizeflag)
13586 {
13587   bfd_signed_vma op;
13588   bfd_signed_vma mask = -1;
13589
13590   switch (bytemode)
13591     {
13592     case b_mode:
13593       FETCH_DATA (the_info, codep + 1);
13594       op = *codep++;
13595       mask = 0xff;
13596       break;
13597     case q_mode:
13598       if (address_mode == mode_64bit)
13599         {
13600           op = get32s ();
13601           break;
13602         }
13603       /* Fall through.  */
13604     case v_mode:
13605       USED_REX (REX_W);
13606       if (rex & REX_W)
13607         op = get32s ();
13608       else
13609         {
13610           if (sizeflag & DFLAG)
13611             {
13612               op = get32 ();
13613               mask = 0xffffffff;
13614             }
13615           else
13616             {
13617               op = get16 ();
13618               mask = 0xfffff;
13619             }
13620           used_prefixes |= (prefixes & PREFIX_DATA);
13621         }
13622       break;
13623     case w_mode:
13624       mask = 0xfffff;
13625       op = get16 ();
13626       break;
13627     case const_1_mode:
13628       if (intel_syntax)
13629         oappend ("1");
13630       return;
13631     default:
13632       oappend (INTERNAL_DISASSEMBLER_ERROR);
13633       return;
13634     }
13635
13636   op &= mask;
13637   scratchbuf[0] = '$';
13638   print_operand_value (scratchbuf + 1, 1, op);
13639   oappend (scratchbuf + intel_syntax);
13640   scratchbuf[0] = '\0';
13641 }
13642
13643 static void
13644 OP_I64 (int bytemode, int sizeflag)
13645 {
13646   bfd_signed_vma op;
13647   bfd_signed_vma mask = -1;
13648
13649   if (address_mode != mode_64bit)
13650     {
13651       OP_I (bytemode, sizeflag);
13652       return;
13653     }
13654
13655   switch (bytemode)
13656     {
13657     case b_mode:
13658       FETCH_DATA (the_info, codep + 1);
13659       op = *codep++;
13660       mask = 0xff;
13661       break;
13662     case v_mode:
13663       USED_REX (REX_W);
13664       if (rex & REX_W)
13665         op = get64 ();
13666       else
13667         {
13668           if (sizeflag & DFLAG)
13669             {
13670               op = get32 ();
13671               mask = 0xffffffff;
13672             }
13673           else
13674             {
13675               op = get16 ();
13676               mask = 0xfffff;
13677             }
13678           used_prefixes |= (prefixes & PREFIX_DATA);
13679         }
13680       break;
13681     case w_mode:
13682       mask = 0xfffff;
13683       op = get16 ();
13684       break;
13685     default:
13686       oappend (INTERNAL_DISASSEMBLER_ERROR);
13687       return;
13688     }
13689
13690   op &= mask;
13691   scratchbuf[0] = '$';
13692   print_operand_value (scratchbuf + 1, 1, op);
13693   oappend (scratchbuf + intel_syntax);
13694   scratchbuf[0] = '\0';
13695 }
13696
13697 static void
13698 OP_sI (int bytemode, int sizeflag)
13699 {
13700   bfd_signed_vma op;
13701
13702   switch (bytemode)
13703     {
13704     case b_mode:
13705     case b_T_mode:
13706       FETCH_DATA (the_info, codep + 1);
13707       op = *codep++;
13708       if ((op & 0x80) != 0)
13709         op -= 0x100;
13710       if (bytemode == b_T_mode)
13711         {
13712           if (address_mode != mode_64bit
13713               || !(sizeflag & DFLAG))
13714             {
13715               if (sizeflag & DFLAG)
13716                 op &= 0xffffffff;
13717               else
13718                 op &= 0xffff;
13719           }
13720         }
13721       else
13722         {
13723           if (!(rex & REX_W))
13724             {
13725               if (sizeflag & DFLAG)
13726                 op &= 0xffffffff;
13727               else
13728                 op &= 0xffff;
13729             }
13730         }
13731       break;
13732     case v_mode:
13733       if (sizeflag & DFLAG)
13734         op = get32s ();
13735       else
13736         op = get16 ();
13737       break;
13738     default:
13739       oappend (INTERNAL_DISASSEMBLER_ERROR);
13740       return;
13741     }
13742
13743   scratchbuf[0] = '$';
13744   print_operand_value (scratchbuf + 1, 1, op);
13745   oappend (scratchbuf + intel_syntax);
13746 }
13747
13748 static void
13749 OP_J (int bytemode, int sizeflag)
13750 {
13751   bfd_vma disp;
13752   bfd_vma mask = -1;
13753   bfd_vma segment = 0;
13754
13755   switch (bytemode)
13756     {
13757     case b_mode:
13758       FETCH_DATA (the_info, codep + 1);
13759       disp = *codep++;
13760       if ((disp & 0x80) != 0)
13761         disp -= 0x100;
13762       break;
13763     case v_mode:
13764       USED_REX (REX_W);
13765       if ((sizeflag & DFLAG) || (rex & REX_W))
13766         disp = get32s ();
13767       else
13768         {
13769           disp = get16 ();
13770           if ((disp & 0x8000) != 0)
13771             disp -= 0x10000;
13772           /* In 16bit mode, address is wrapped around at 64k within
13773              the same segment.  Otherwise, a data16 prefix on a jump
13774              instruction means that the pc is masked to 16 bits after
13775              the displacement is added!  */
13776           mask = 0xffff;
13777           if ((prefixes & PREFIX_DATA) == 0)
13778             segment = ((start_pc + codep - start_codep)
13779                        & ~((bfd_vma) 0xffff));
13780         }
13781       if (!(rex & REX_W))
13782         used_prefixes |= (prefixes & PREFIX_DATA);
13783       break;
13784     default:
13785       oappend (INTERNAL_DISASSEMBLER_ERROR);
13786       return;
13787     }
13788   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13789   set_op (disp, 0);
13790   print_operand_value (scratchbuf, 1, disp);
13791   oappend (scratchbuf);
13792 }
13793
13794 static void
13795 OP_SEG (int bytemode, int sizeflag)
13796 {
13797   if (bytemode == w_mode)
13798     oappend (names_seg[modrm.reg]);
13799   else
13800     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13801 }
13802
13803 static void
13804 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13805 {
13806   int seg, offset;
13807
13808   if (sizeflag & DFLAG)
13809     {
13810       offset = get32 ();
13811       seg = get16 ();
13812     }
13813   else
13814     {
13815       offset = get16 ();
13816       seg = get16 ();
13817     }
13818   used_prefixes |= (prefixes & PREFIX_DATA);
13819   if (intel_syntax)
13820     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13821   else
13822     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13823   oappend (scratchbuf);
13824 }
13825
13826 static void
13827 OP_OFF (int bytemode, int sizeflag)
13828 {
13829   bfd_vma off;
13830
13831   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13832     intel_operand_size (bytemode, sizeflag);
13833   append_seg ();
13834
13835   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13836     off = get32 ();
13837   else
13838     off = get16 ();
13839
13840   if (intel_syntax)
13841     {
13842       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13843                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13844         {
13845           oappend (names_seg[ds_reg - es_reg]);
13846           oappend (":");
13847         }
13848     }
13849   print_operand_value (scratchbuf, 1, off);
13850   oappend (scratchbuf);
13851 }
13852
13853 static void
13854 OP_OFF64 (int bytemode, int sizeflag)
13855 {
13856   bfd_vma off;
13857
13858   if (address_mode != mode_64bit
13859       || (prefixes & PREFIX_ADDR))
13860     {
13861       OP_OFF (bytemode, sizeflag);
13862       return;
13863     }
13864
13865   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13866     intel_operand_size (bytemode, sizeflag);
13867   append_seg ();
13868
13869   off = get64 ();
13870
13871   if (intel_syntax)
13872     {
13873       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13874                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13875         {
13876           oappend (names_seg[ds_reg - es_reg]);
13877           oappend (":");
13878         }
13879     }
13880   print_operand_value (scratchbuf, 1, off);
13881   oappend (scratchbuf);
13882 }
13883
13884 static void
13885 ptr_reg (int code, int sizeflag)
13886 {
13887   const char *s;
13888
13889   *obufp++ = open_char;
13890   used_prefixes |= (prefixes & PREFIX_ADDR);
13891   if (address_mode == mode_64bit)
13892     {
13893       if (!(sizeflag & AFLAG))
13894         s = names32[code - eAX_reg];
13895       else
13896         s = names64[code - eAX_reg];
13897     }
13898   else if (sizeflag & AFLAG)
13899     s = names32[code - eAX_reg];
13900   else
13901     s = names16[code - eAX_reg];
13902   oappend (s);
13903   *obufp++ = close_char;
13904   *obufp = 0;
13905 }
13906
13907 static void
13908 OP_ESreg (int code, int sizeflag)
13909 {
13910   if (intel_syntax)
13911     {
13912       switch (codep[-1])
13913         {
13914         case 0x6d:      /* insw/insl */
13915           intel_operand_size (z_mode, sizeflag);
13916           break;
13917         case 0xa5:      /* movsw/movsl/movsq */
13918         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13919         case 0xab:      /* stosw/stosl */
13920         case 0xaf:      /* scasw/scasl */
13921           intel_operand_size (v_mode, sizeflag);
13922           break;
13923         default:
13924           intel_operand_size (b_mode, sizeflag);
13925         }
13926     }
13927   oappend ("%es:" + intel_syntax);
13928   ptr_reg (code, sizeflag);
13929 }
13930
13931 static void
13932 OP_DSreg (int code, int sizeflag)
13933 {
13934   if (intel_syntax)
13935     {
13936       switch (codep[-1])
13937         {
13938         case 0x6f:      /* outsw/outsl */
13939           intel_operand_size (z_mode, sizeflag);
13940           break;
13941         case 0xa5:      /* movsw/movsl/movsq */
13942         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13943         case 0xad:      /* lodsw/lodsl/lodsq */
13944           intel_operand_size (v_mode, sizeflag);
13945           break;
13946         default:
13947           intel_operand_size (b_mode, sizeflag);
13948         }
13949     }
13950   if ((prefixes
13951        & (PREFIX_CS
13952           | PREFIX_DS
13953           | PREFIX_SS
13954           | PREFIX_ES
13955           | PREFIX_FS
13956           | PREFIX_GS)) == 0)
13957     prefixes |= PREFIX_DS;
13958   append_seg ();
13959   ptr_reg (code, sizeflag);
13960 }
13961
13962 static void
13963 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13964 {
13965   int add;
13966   if (rex & REX_R)
13967     {
13968       USED_REX (REX_R);
13969       add = 8;
13970     }
13971   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13972     {
13973       all_prefixes[last_lock_prefix] = 0;
13974       used_prefixes |= PREFIX_LOCK;
13975       add = 8;
13976     }
13977   else
13978     add = 0;
13979   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13980   oappend (scratchbuf + intel_syntax);
13981 }
13982
13983 static void
13984 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13985 {
13986   int add;
13987   USED_REX (REX_R);
13988   if (rex & REX_R)
13989     add = 8;
13990   else
13991     add = 0;
13992   if (intel_syntax)
13993     sprintf (scratchbuf, "db%d", modrm.reg + add);
13994   else
13995     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13996   oappend (scratchbuf);
13997 }
13998
13999 static void
14000 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14001 {
14002   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14003   oappend (scratchbuf + intel_syntax);
14004 }
14005
14006 static void
14007 OP_R (int bytemode, int sizeflag)
14008 {
14009   if (modrm.mod == 3)
14010     OP_E (bytemode, sizeflag);
14011   else
14012     BadOp ();
14013 }
14014
14015 static void
14016 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14017 {
14018   int reg = modrm.reg;
14019   const char **names;
14020
14021   used_prefixes |= (prefixes & PREFIX_DATA);
14022   if (prefixes & PREFIX_DATA)
14023     {
14024       names = names_xmm;
14025       USED_REX (REX_R);
14026       if (rex & REX_R)
14027         reg += 8;
14028     }
14029   else
14030     names = names_mm;
14031   oappend (names[reg]);
14032 }
14033
14034 static void
14035 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14036 {
14037   int reg = modrm.reg;
14038   const char **names;
14039
14040   USED_REX (REX_R);
14041   if (rex & REX_R)
14042     reg += 8;
14043   if (need_vex
14044       && bytemode != xmm_mode
14045       && bytemode != scalar_mode)
14046     {
14047       switch (vex.length)
14048         {
14049         case 128:
14050           names = names_xmm;
14051           break;
14052         case 256:
14053           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
14054             names = names_ymm;
14055           else
14056             names = names_xmm;
14057           break;
14058         default:
14059           abort ();
14060         }
14061     }
14062   else
14063     names = names_xmm;
14064   oappend (names[reg]);
14065 }
14066
14067 static void
14068 OP_EM (int bytemode, int sizeflag)
14069 {
14070   int reg;
14071   const char **names;
14072
14073   if (modrm.mod != 3)
14074     {
14075       if (intel_syntax
14076           && (bytemode == v_mode || bytemode == v_swap_mode))
14077         {
14078           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14079           used_prefixes |= (prefixes & PREFIX_DATA);
14080         }
14081       OP_E (bytemode, sizeflag);
14082       return;
14083     }
14084
14085   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14086     swap_operand ();
14087
14088   /* Skip mod/rm byte.  */
14089   MODRM_CHECK;
14090   codep++;
14091   used_prefixes |= (prefixes & PREFIX_DATA);
14092   reg = modrm.rm;
14093   if (prefixes & PREFIX_DATA)
14094     {
14095       names = names_xmm;
14096       USED_REX (REX_B);
14097       if (rex & REX_B)
14098         reg += 8;
14099     }
14100   else
14101     names = names_mm;
14102   oappend (names[reg]);
14103 }
14104
14105 /* cvt* are the only instructions in sse2 which have
14106    both SSE and MMX operands and also have 0x66 prefix
14107    in their opcode. 0x66 was originally used to differentiate
14108    between SSE and MMX instruction(operands). So we have to handle the
14109    cvt* separately using OP_EMC and OP_MXC */
14110 static void
14111 OP_EMC (int bytemode, int sizeflag)
14112 {
14113   if (modrm.mod != 3)
14114     {
14115       if (intel_syntax && bytemode == v_mode)
14116         {
14117           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14118           used_prefixes |= (prefixes & PREFIX_DATA);
14119         }
14120       OP_E (bytemode, sizeflag);
14121       return;
14122     }
14123
14124   /* Skip mod/rm byte.  */
14125   MODRM_CHECK;
14126   codep++;
14127   used_prefixes |= (prefixes & PREFIX_DATA);
14128   oappend (names_mm[modrm.rm]);
14129 }
14130
14131 static void
14132 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14133 {
14134   used_prefixes |= (prefixes & PREFIX_DATA);
14135   oappend (names_mm[modrm.reg]);
14136 }
14137
14138 static void
14139 OP_EX (int bytemode, int sizeflag)
14140 {
14141   int reg;
14142   const char **names;
14143
14144   /* Skip mod/rm byte.  */
14145   MODRM_CHECK;
14146   codep++;
14147
14148   if (modrm.mod != 3)
14149     {
14150       OP_E_memory (bytemode, sizeflag);
14151       return;
14152     }
14153
14154   reg = modrm.rm;
14155   USED_REX (REX_B);
14156   if (rex & REX_B)
14157     reg += 8;
14158
14159   if ((sizeflag & SUFFIX_ALWAYS)
14160       && (bytemode == x_swap_mode
14161           || bytemode == d_swap_mode
14162           || bytemode == d_scalar_swap_mode
14163           || bytemode == q_swap_mode
14164           || bytemode == q_scalar_swap_mode))
14165     swap_operand ();
14166
14167   if (need_vex
14168       && bytemode != xmm_mode
14169       && bytemode != xmmdw_mode
14170       && bytemode != xmmqd_mode
14171       && bytemode != xmm_mb_mode
14172       && bytemode != xmm_mw_mode
14173       && bytemode != xmm_md_mode
14174       && bytemode != xmm_mq_mode
14175       && bytemode != xmmq_mode
14176       && bytemode != d_scalar_mode
14177       && bytemode != d_scalar_swap_mode
14178       && bytemode != q_scalar_mode
14179       && bytemode != q_scalar_swap_mode
14180       && bytemode != vex_scalar_w_dq_mode)
14181     {
14182       switch (vex.length)
14183         {
14184         case 128:
14185           names = names_xmm;
14186           break;
14187         case 256:
14188           names = names_ymm;
14189           break;
14190         default:
14191           abort ();
14192         }
14193     }
14194   else
14195     names = names_xmm;
14196   oappend (names[reg]);
14197 }
14198
14199 static void
14200 OP_MS (int bytemode, int sizeflag)
14201 {
14202   if (modrm.mod == 3)
14203     OP_EM (bytemode, sizeflag);
14204   else
14205     BadOp ();
14206 }
14207
14208 static void
14209 OP_XS (int bytemode, int sizeflag)
14210 {
14211   if (modrm.mod == 3)
14212     OP_EX (bytemode, sizeflag);
14213   else
14214     BadOp ();
14215 }
14216
14217 static void
14218 OP_M (int bytemode, int sizeflag)
14219 {
14220   if (modrm.mod == 3)
14221     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14222     BadOp ();
14223   else
14224     OP_E (bytemode, sizeflag);
14225 }
14226
14227 static void
14228 OP_0f07 (int bytemode, int sizeflag)
14229 {
14230   if (modrm.mod != 3 || modrm.rm != 0)
14231     BadOp ();
14232   else
14233     OP_E (bytemode, sizeflag);
14234 }
14235
14236 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14237    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14238
14239 static void
14240 NOP_Fixup1 (int bytemode, int sizeflag)
14241 {
14242   if ((prefixes & PREFIX_DATA) != 0
14243       || (rex != 0
14244           && rex != 0x48
14245           && address_mode == mode_64bit))
14246     OP_REG (bytemode, sizeflag);
14247   else
14248     strcpy (obuf, "nop");
14249 }
14250
14251 static void
14252 NOP_Fixup2 (int bytemode, int sizeflag)
14253 {
14254   if ((prefixes & PREFIX_DATA) != 0
14255       || (rex != 0
14256           && rex != 0x48
14257           && address_mode == mode_64bit))
14258     OP_IMREG (bytemode, sizeflag);
14259 }
14260
14261 static const char *const Suffix3DNow[] = {
14262 /* 00 */        NULL,           NULL,           NULL,           NULL,
14263 /* 04 */        NULL,           NULL,           NULL,           NULL,
14264 /* 08 */        NULL,           NULL,           NULL,           NULL,
14265 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14266 /* 10 */        NULL,           NULL,           NULL,           NULL,
14267 /* 14 */        NULL,           NULL,           NULL,           NULL,
14268 /* 18 */        NULL,           NULL,           NULL,           NULL,
14269 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14270 /* 20 */        NULL,           NULL,           NULL,           NULL,
14271 /* 24 */        NULL,           NULL,           NULL,           NULL,
14272 /* 28 */        NULL,           NULL,           NULL,           NULL,
14273 /* 2C */        NULL,           NULL,           NULL,           NULL,
14274 /* 30 */        NULL,           NULL,           NULL,           NULL,
14275 /* 34 */        NULL,           NULL,           NULL,           NULL,
14276 /* 38 */        NULL,           NULL,           NULL,           NULL,
14277 /* 3C */        NULL,           NULL,           NULL,           NULL,
14278 /* 40 */        NULL,           NULL,           NULL,           NULL,
14279 /* 44 */        NULL,           NULL,           NULL,           NULL,
14280 /* 48 */        NULL,           NULL,           NULL,           NULL,
14281 /* 4C */        NULL,           NULL,           NULL,           NULL,
14282 /* 50 */        NULL,           NULL,           NULL,           NULL,
14283 /* 54 */        NULL,           NULL,           NULL,           NULL,
14284 /* 58 */        NULL,           NULL,           NULL,           NULL,
14285 /* 5C */        NULL,           NULL,           NULL,           NULL,
14286 /* 60 */        NULL,           NULL,           NULL,           NULL,
14287 /* 64 */        NULL,           NULL,           NULL,           NULL,
14288 /* 68 */        NULL,           NULL,           NULL,           NULL,
14289 /* 6C */        NULL,           NULL,           NULL,           NULL,
14290 /* 70 */        NULL,           NULL,           NULL,           NULL,
14291 /* 74 */        NULL,           NULL,           NULL,           NULL,
14292 /* 78 */        NULL,           NULL,           NULL,           NULL,
14293 /* 7C */        NULL,           NULL,           NULL,           NULL,
14294 /* 80 */        NULL,           NULL,           NULL,           NULL,
14295 /* 84 */        NULL,           NULL,           NULL,           NULL,
14296 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14297 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14298 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14299 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14300 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14301 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14302 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14303 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14304 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14305 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14306 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14307 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14308 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14309 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14310 /* C0 */        NULL,           NULL,           NULL,           NULL,
14311 /* C4 */        NULL,           NULL,           NULL,           NULL,
14312 /* C8 */        NULL,           NULL,           NULL,           NULL,
14313 /* CC */        NULL,           NULL,           NULL,           NULL,
14314 /* D0 */        NULL,           NULL,           NULL,           NULL,
14315 /* D4 */        NULL,           NULL,           NULL,           NULL,
14316 /* D8 */        NULL,           NULL,           NULL,           NULL,
14317 /* DC */        NULL,           NULL,           NULL,           NULL,
14318 /* E0 */        NULL,           NULL,           NULL,           NULL,
14319 /* E4 */        NULL,           NULL,           NULL,           NULL,
14320 /* E8 */        NULL,           NULL,           NULL,           NULL,
14321 /* EC */        NULL,           NULL,           NULL,           NULL,
14322 /* F0 */        NULL,           NULL,           NULL,           NULL,
14323 /* F4 */        NULL,           NULL,           NULL,           NULL,
14324 /* F8 */        NULL,           NULL,           NULL,           NULL,
14325 /* FC */        NULL,           NULL,           NULL,           NULL,
14326 };
14327
14328 static void
14329 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14330 {
14331   const char *mnemonic;
14332
14333   FETCH_DATA (the_info, codep + 1);
14334   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14335      place where an 8-bit immediate would normally go.  ie. the last
14336      byte of the instruction.  */
14337   obufp = mnemonicendp;
14338   mnemonic = Suffix3DNow[*codep++ & 0xff];
14339   if (mnemonic)
14340     oappend (mnemonic);
14341   else
14342     {
14343       /* Since a variable sized modrm/sib chunk is between the start
14344          of the opcode (0x0f0f) and the opcode suffix, we need to do
14345          all the modrm processing first, and don't know until now that
14346          we have a bad opcode.  This necessitates some cleaning up.  */
14347       op_out[0][0] = '\0';
14348       op_out[1][0] = '\0';
14349       BadOp ();
14350     }
14351   mnemonicendp = obufp;
14352 }
14353
14354 static struct op simd_cmp_op[] =
14355 {
14356   { STRING_COMMA_LEN ("eq") },
14357   { STRING_COMMA_LEN ("lt") },
14358   { STRING_COMMA_LEN ("le") },
14359   { STRING_COMMA_LEN ("unord") },
14360   { STRING_COMMA_LEN ("neq") },
14361   { STRING_COMMA_LEN ("nlt") },
14362   { STRING_COMMA_LEN ("nle") },
14363   { STRING_COMMA_LEN ("ord") }
14364 };
14365
14366 static void
14367 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14368 {
14369   unsigned int cmp_type;
14370
14371   FETCH_DATA (the_info, codep + 1);
14372   cmp_type = *codep++ & 0xff;
14373   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14374     {
14375       char suffix [3];
14376       char *p = mnemonicendp - 2;
14377       suffix[0] = p[0];
14378       suffix[1] = p[1];
14379       suffix[2] = '\0';
14380       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14381       mnemonicendp += simd_cmp_op[cmp_type].len;
14382     }
14383   else
14384     {
14385       /* We have a reserved extension byte.  Output it directly.  */
14386       scratchbuf[0] = '$';
14387       print_operand_value (scratchbuf + 1, 1, cmp_type);
14388       oappend (scratchbuf + intel_syntax);
14389       scratchbuf[0] = '\0';
14390     }
14391 }
14392
14393 static void
14394 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14395           int sizeflag ATTRIBUTE_UNUSED)
14396 {
14397   /* mwait %eax,%ecx  */
14398   if (!intel_syntax)
14399     {
14400       const char **names = (address_mode == mode_64bit
14401                             ? names64 : names32);
14402       strcpy (op_out[0], names[0]);
14403       strcpy (op_out[1], names[1]);
14404       two_source_ops = 1;
14405     }
14406   /* Skip mod/rm byte.  */
14407   MODRM_CHECK;
14408   codep++;
14409 }
14410
14411 static void
14412 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14413             int sizeflag ATTRIBUTE_UNUSED)
14414 {
14415   /* monitor %eax,%ecx,%edx"  */
14416   if (!intel_syntax)
14417     {
14418       const char **op1_names;
14419       const char **names = (address_mode == mode_64bit
14420                             ? names64 : names32);
14421
14422       if (!(prefixes & PREFIX_ADDR))
14423         op1_names = (address_mode == mode_16bit
14424                      ? names16 : names);
14425       else
14426         {
14427           /* Remove "addr16/addr32".  */
14428           all_prefixes[last_addr_prefix] = 0;
14429           op1_names = (address_mode != mode_32bit
14430                        ? names32 : names16);
14431           used_prefixes |= PREFIX_ADDR;
14432         }
14433       strcpy (op_out[0], op1_names[0]);
14434       strcpy (op_out[1], names[1]);
14435       strcpy (op_out[2], names[2]);
14436       two_source_ops = 1;
14437     }
14438   /* Skip mod/rm byte.  */
14439   MODRM_CHECK;
14440   codep++;
14441 }
14442
14443 static void
14444 BadOp (void)
14445 {
14446   /* Throw away prefixes and 1st. opcode byte.  */
14447   codep = insn_codep + 1;
14448   oappend ("(bad)");
14449 }
14450
14451 static void
14452 REP_Fixup (int bytemode, int sizeflag)
14453 {
14454   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14455      lods and stos.  */
14456   if (prefixes & PREFIX_REPZ)
14457     all_prefixes[last_repz_prefix] = REP_PREFIX;
14458
14459   switch (bytemode)
14460     {
14461     case al_reg:
14462     case eAX_reg:
14463     case indir_dx_reg:
14464       OP_IMREG (bytemode, sizeflag);
14465       break;
14466     case eDI_reg:
14467       OP_ESreg (bytemode, sizeflag);
14468       break;
14469     case eSI_reg:
14470       OP_DSreg (bytemode, sizeflag);
14471       break;
14472     default:
14473       abort ();
14474       break;
14475     }
14476 }
14477
14478 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14479    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14480  */
14481
14482 static void
14483 HLE_Fixup1 (int bytemode, int sizeflag)
14484 {
14485   if (modrm.mod != 3
14486       && (prefixes & PREFIX_LOCK) != 0)
14487     {
14488       if (prefixes & PREFIX_REPZ)
14489         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14490       if (prefixes & PREFIX_REPNZ)
14491         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14492     }
14493
14494   OP_E (bytemode, sizeflag);
14495 }
14496
14497 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14498    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
14499  */
14500
14501 static void
14502 HLE_Fixup2 (int bytemode, int sizeflag)
14503 {
14504   if (modrm.mod != 3)
14505     {
14506       if (prefixes & PREFIX_REPZ)
14507         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14508       if (prefixes & PREFIX_REPNZ)
14509         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14510     }
14511
14512   OP_E (bytemode, sizeflag);
14513 }
14514
14515 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
14516    "xrelease" for memory operand.  No check for LOCK prefix.   */
14517
14518 static void
14519 HLE_Fixup3 (int bytemode, int sizeflag)
14520 {
14521   if (modrm.mod != 3
14522       && last_repz_prefix > last_repnz_prefix
14523       && (prefixes & PREFIX_REPZ) != 0)
14524     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14525
14526   OP_E (bytemode, sizeflag);
14527 }
14528
14529 static void
14530 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14531 {
14532   USED_REX (REX_W);
14533   if (rex & REX_W)
14534     {
14535       /* Change cmpxchg8b to cmpxchg16b.  */
14536       char *p = mnemonicendp - 2;
14537       mnemonicendp = stpcpy (p, "16b");
14538       bytemode = o_mode;
14539     }
14540   else if ((prefixes & PREFIX_LOCK) != 0)
14541     {
14542       if (prefixes & PREFIX_REPZ)
14543         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14544       if (prefixes & PREFIX_REPNZ)
14545         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14546     }
14547
14548   OP_M (bytemode, sizeflag);
14549 }
14550
14551 static void
14552 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14553 {
14554   const char **names;
14555
14556   if (need_vex)
14557     {
14558       switch (vex.length)
14559         {
14560         case 128:
14561           names = names_xmm;
14562           break;
14563         case 256:
14564           names = names_ymm;
14565           break;
14566         default:
14567           abort ();
14568         }
14569     }
14570   else
14571     names = names_xmm;
14572   oappend (names[reg]);
14573 }
14574
14575 static void
14576 CRC32_Fixup (int bytemode, int sizeflag)
14577 {
14578   /* Add proper suffix to "crc32".  */
14579   char *p = mnemonicendp;
14580
14581   switch (bytemode)
14582     {
14583     case b_mode:
14584       if (intel_syntax)
14585         goto skip;
14586
14587       *p++ = 'b';
14588       break;
14589     case v_mode:
14590       if (intel_syntax)
14591         goto skip;
14592
14593       USED_REX (REX_W);
14594       if (rex & REX_W)
14595         *p++ = 'q';
14596       else
14597         {
14598           if (sizeflag & DFLAG)
14599             *p++ = 'l';
14600           else
14601             *p++ = 'w';
14602           used_prefixes |= (prefixes & PREFIX_DATA);
14603         }
14604       break;
14605     default:
14606       oappend (INTERNAL_DISASSEMBLER_ERROR);
14607       break;
14608     }
14609   mnemonicendp = p;
14610   *p = '\0';
14611
14612 skip:
14613   if (modrm.mod == 3)
14614     {
14615       int add;
14616
14617       /* Skip mod/rm byte.  */
14618       MODRM_CHECK;
14619       codep++;
14620
14621       USED_REX (REX_B);
14622       add = (rex & REX_B) ? 8 : 0;
14623       if (bytemode == b_mode)
14624         {
14625           USED_REX (0);
14626           if (rex)
14627             oappend (names8rex[modrm.rm + add]);
14628           else
14629             oappend (names8[modrm.rm + add]);
14630         }
14631       else
14632         {
14633           USED_REX (REX_W);
14634           if (rex & REX_W)
14635             oappend (names64[modrm.rm + add]);
14636           else if ((prefixes & PREFIX_DATA))
14637             oappend (names16[modrm.rm + add]);
14638           else
14639             oappend (names32[modrm.rm + add]);
14640         }
14641     }
14642   else
14643     OP_E (bytemode, sizeflag);
14644 }
14645
14646 static void
14647 FXSAVE_Fixup (int bytemode, int sizeflag)
14648 {
14649   /* Add proper suffix to "fxsave" and "fxrstor".  */
14650   USED_REX (REX_W);
14651   if (rex & REX_W)
14652     {
14653       char *p = mnemonicendp;
14654       *p++ = '6';
14655       *p++ = '4';
14656       *p = '\0';
14657       mnemonicendp = p;
14658     }
14659   OP_M (bytemode, sizeflag);
14660 }
14661
14662 /* Display the destination register operand for instructions with
14663    VEX. */
14664
14665 static void
14666 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14667 {
14668   int reg;
14669   const char **names;
14670
14671   if (!need_vex)
14672     abort ();
14673
14674   if (!need_vex_reg)
14675     return;
14676
14677   reg = vex.register_specifier;
14678   if (bytemode == vex_scalar_mode)
14679     {
14680       oappend (names_xmm[reg]);
14681       return;
14682     }
14683
14684   switch (vex.length)
14685     {
14686     case 128:
14687       switch (bytemode)
14688         {
14689         case vex_mode:
14690         case vex128_mode:
14691         case vex_vsib_q_w_dq_mode:
14692           names = names_xmm;
14693           break;
14694         case dq_mode:
14695           if (vex.w)
14696             names = names64;
14697           else
14698             names = names32;
14699           break;
14700         default:
14701           abort ();
14702           return;
14703         }
14704       break;
14705     case 256:
14706       switch (bytemode)
14707         {
14708         case vex_mode:
14709         case vex256_mode:
14710           names = names_ymm;
14711           break;
14712         case vex_vsib_q_w_dq_mode:
14713           names = vex.w ? names_ymm : names_xmm;
14714           break;
14715         default:
14716           abort ();
14717           return;
14718         }
14719       break;
14720     default:
14721       abort ();
14722       break;
14723     }
14724   oappend (names[reg]);
14725 }
14726
14727 /* Get the VEX immediate byte without moving codep.  */
14728
14729 static unsigned char
14730 get_vex_imm8 (int sizeflag, int opnum)
14731 {
14732   int bytes_before_imm = 0;
14733
14734   if (modrm.mod != 3)
14735     {
14736       /* There are SIB/displacement bytes.  */
14737       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14738         {
14739           /* 32/64 bit address mode */
14740           int base = modrm.rm;
14741
14742           /* Check SIB byte.  */
14743           if (base == 4)
14744             {
14745               FETCH_DATA (the_info, codep + 1);
14746               base = *codep & 7;
14747               /* When decoding the third source, don't increase
14748                  bytes_before_imm as this has already been incremented
14749                  by one in OP_E_memory while decoding the second
14750                  source operand.  */
14751               if (opnum == 0)
14752                 bytes_before_imm++;
14753             }
14754
14755           /* Don't increase bytes_before_imm when decoding the third source,
14756              it has already been incremented by OP_E_memory while decoding
14757              the second source operand.  */
14758           if (opnum == 0)
14759             {
14760               switch (modrm.mod)
14761                 {
14762                   case 0:
14763                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14764                        SIB == 5, there is a 4 byte displacement.  */
14765                     if (base != 5)
14766                       /* No displacement. */
14767                       break;
14768                   case 2:
14769                     /* 4 byte displacement.  */
14770                     bytes_before_imm += 4;
14771                     break;
14772                   case 1:
14773                     /* 1 byte displacement.  */
14774                     bytes_before_imm++;
14775                     break;
14776                 }
14777             }
14778         }
14779       else
14780         {
14781           /* 16 bit address mode */
14782           /* Don't increase bytes_before_imm when decoding the third source,
14783              it has already been incremented by OP_E_memory while decoding
14784              the second source operand.  */
14785           if (opnum == 0)
14786             {
14787               switch (modrm.mod)
14788                 {
14789                 case 0:
14790                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14791                   if (modrm.rm != 6)
14792                     /* No displacement. */
14793                     break;
14794                 case 2:
14795                   /* 2 byte displacement.  */
14796                   bytes_before_imm += 2;
14797                   break;
14798                 case 1:
14799                   /* 1 byte displacement: when decoding the third source,
14800                      don't increase bytes_before_imm as this has already
14801                      been incremented by one in OP_E_memory while decoding
14802                      the second source operand.  */
14803                   if (opnum == 0)
14804                     bytes_before_imm++;
14805
14806                   break;
14807                 }
14808             }
14809         }
14810     }
14811
14812   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14813   return codep [bytes_before_imm];
14814 }
14815
14816 static void
14817 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14818 {
14819   const char **names;
14820
14821   if (reg == -1 && modrm.mod != 3)
14822     {
14823       OP_E_memory (bytemode, sizeflag);
14824       return;
14825     }
14826   else
14827     {
14828       if (reg == -1)
14829         {
14830           reg = modrm.rm;
14831           USED_REX (REX_B);
14832           if (rex & REX_B)
14833             reg += 8;
14834         }
14835       else if (reg > 7 && address_mode != mode_64bit)
14836         BadOp ();
14837     }
14838
14839   switch (vex.length)
14840     {
14841     case 128:
14842       names = names_xmm;
14843       break;
14844     case 256:
14845       names = names_ymm;
14846       break;
14847     default:
14848       abort ();
14849     }
14850   oappend (names[reg]);
14851 }
14852
14853 static void
14854 OP_EX_VexImmW (int bytemode, int sizeflag)
14855 {
14856   int reg = -1;
14857   static unsigned char vex_imm8;
14858
14859   if (vex_w_done == 0)
14860     {
14861       vex_w_done = 1;
14862
14863       /* Skip mod/rm byte.  */
14864       MODRM_CHECK;
14865       codep++;
14866
14867       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14868
14869       if (vex.w)
14870           reg = vex_imm8 >> 4;
14871
14872       OP_EX_VexReg (bytemode, sizeflag, reg);
14873     }
14874   else if (vex_w_done == 1)
14875     {
14876       vex_w_done = 2;
14877
14878       if (!vex.w)
14879           reg = vex_imm8 >> 4;
14880
14881       OP_EX_VexReg (bytemode, sizeflag, reg);
14882     }
14883   else
14884     {
14885       /* Output the imm8 directly.  */
14886       scratchbuf[0] = '$';
14887       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14888       oappend (scratchbuf + intel_syntax);
14889       scratchbuf[0] = '\0';
14890       codep++;
14891     }
14892 }
14893
14894 static void
14895 OP_Vex_2src (int bytemode, int sizeflag)
14896 {
14897   if (modrm.mod == 3)
14898     {
14899       int reg = modrm.rm;
14900       USED_REX (REX_B);
14901       if (rex & REX_B)
14902         reg += 8;
14903       oappend (names_xmm[reg]);
14904     }
14905   else
14906     {
14907       if (intel_syntax
14908           && (bytemode == v_mode || bytemode == v_swap_mode))
14909         {
14910           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14911           used_prefixes |= (prefixes & PREFIX_DATA);
14912         }
14913       OP_E (bytemode, sizeflag);
14914     }
14915 }
14916
14917 static void
14918 OP_Vex_2src_1 (int bytemode, int sizeflag)
14919 {
14920   if (modrm.mod == 3)
14921     {
14922       /* Skip mod/rm byte.   */
14923       MODRM_CHECK;
14924       codep++;
14925     }
14926
14927   if (vex.w)
14928     oappend (names_xmm[vex.register_specifier]);
14929   else
14930     OP_Vex_2src (bytemode, sizeflag);
14931 }
14932
14933 static void
14934 OP_Vex_2src_2 (int bytemode, int sizeflag)
14935 {
14936   if (vex.w)
14937     OP_Vex_2src (bytemode, sizeflag);
14938   else
14939     oappend (names_xmm[vex.register_specifier]);
14940 }
14941
14942 static void
14943 OP_EX_VexW (int bytemode, int sizeflag)
14944 {
14945   int reg = -1;
14946
14947   if (!vex_w_done)
14948     {
14949       vex_w_done = 1;
14950
14951       /* Skip mod/rm byte.  */
14952       MODRM_CHECK;
14953       codep++;
14954
14955       if (vex.w)
14956         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14957     }
14958   else
14959     {
14960       if (!vex.w)
14961         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14962     }
14963
14964   OP_EX_VexReg (bytemode, sizeflag, reg);
14965 }
14966
14967 static void
14968 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14969              int sizeflag ATTRIBUTE_UNUSED)
14970 {
14971   /* Skip the immediate byte and check for invalid bits.  */
14972   FETCH_DATA (the_info, codep + 1);
14973   if (*codep++ & 0xf)
14974     BadOp ();
14975 }
14976
14977 static void
14978 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14979 {
14980   int reg;
14981   const char **names;
14982
14983   FETCH_DATA (the_info, codep + 1);
14984   reg = *codep++;
14985
14986   if (bytemode != x_mode)
14987     abort ();
14988
14989   if (reg & 0xf)
14990       BadOp ();
14991
14992   reg >>= 4;
14993   if (reg > 7 && address_mode != mode_64bit)
14994     BadOp ();
14995
14996   switch (vex.length)
14997     {
14998     case 128:
14999       names = names_xmm;
15000       break;
15001     case 256:
15002       names = names_ymm;
15003       break;
15004     default:
15005       abort ();
15006     }
15007   oappend (names[reg]);
15008 }
15009
15010 static void
15011 OP_XMM_VexW (int bytemode, int sizeflag)
15012 {
15013   /* Turn off the REX.W bit since it is used for swapping operands
15014      now.  */
15015   rex &= ~REX_W;
15016   OP_XMM (bytemode, sizeflag);
15017 }
15018
15019 static void
15020 OP_EX_Vex (int bytemode, int sizeflag)
15021 {
15022   if (modrm.mod != 3)
15023     {
15024       if (vex.register_specifier != 0)
15025         BadOp ();
15026       need_vex_reg = 0;
15027     }
15028   OP_EX (bytemode, sizeflag);
15029 }
15030
15031 static void
15032 OP_XMM_Vex (int bytemode, int sizeflag)
15033 {
15034   if (modrm.mod != 3)
15035     {
15036       if (vex.register_specifier != 0)
15037         BadOp ();
15038       need_vex_reg = 0;
15039     }
15040   OP_XMM (bytemode, sizeflag);
15041 }
15042
15043 static void
15044 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15045 {
15046   switch (vex.length)
15047     {
15048     case 128:
15049       mnemonicendp = stpcpy (obuf, "vzeroupper");
15050       break;
15051     case 256:
15052       mnemonicendp = stpcpy (obuf, "vzeroall");
15053       break;
15054     default:
15055       abort ();
15056     }
15057 }
15058
15059 static struct op vex_cmp_op[] =
15060 {
15061   { STRING_COMMA_LEN ("eq") },
15062   { STRING_COMMA_LEN ("lt") },
15063   { STRING_COMMA_LEN ("le") },
15064   { STRING_COMMA_LEN ("unord") },
15065   { STRING_COMMA_LEN ("neq") },
15066   { STRING_COMMA_LEN ("nlt") },
15067   { STRING_COMMA_LEN ("nle") },
15068   { STRING_COMMA_LEN ("ord") },
15069   { STRING_COMMA_LEN ("eq_uq") },
15070   { STRING_COMMA_LEN ("nge") },
15071   { STRING_COMMA_LEN ("ngt") },
15072   { STRING_COMMA_LEN ("false") },
15073   { STRING_COMMA_LEN ("neq_oq") },
15074   { STRING_COMMA_LEN ("ge") },
15075   { STRING_COMMA_LEN ("gt") },
15076   { STRING_COMMA_LEN ("true") },
15077   { STRING_COMMA_LEN ("eq_os") },
15078   { STRING_COMMA_LEN ("lt_oq") },
15079   { STRING_COMMA_LEN ("le_oq") },
15080   { STRING_COMMA_LEN ("unord_s") },
15081   { STRING_COMMA_LEN ("neq_us") },
15082   { STRING_COMMA_LEN ("nlt_uq") },
15083   { STRING_COMMA_LEN ("nle_uq") },
15084   { STRING_COMMA_LEN ("ord_s") },
15085   { STRING_COMMA_LEN ("eq_us") },
15086   { STRING_COMMA_LEN ("nge_uq") },
15087   { STRING_COMMA_LEN ("ngt_uq") },
15088   { STRING_COMMA_LEN ("false_os") },
15089   { STRING_COMMA_LEN ("neq_os") },
15090   { STRING_COMMA_LEN ("ge_oq") },
15091   { STRING_COMMA_LEN ("gt_oq") },
15092   { STRING_COMMA_LEN ("true_us") },
15093 };
15094
15095 static void
15096 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15097 {
15098   unsigned int cmp_type;
15099
15100   FETCH_DATA (the_info, codep + 1);
15101   cmp_type = *codep++ & 0xff;
15102   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15103     {
15104       char suffix [3];
15105       char *p = mnemonicendp - 2;
15106       suffix[0] = p[0];
15107       suffix[1] = p[1];
15108       suffix[2] = '\0';
15109       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15110       mnemonicendp += vex_cmp_op[cmp_type].len;
15111     }
15112   else
15113     {
15114       /* We have a reserved extension byte.  Output it directly.  */
15115       scratchbuf[0] = '$';
15116       print_operand_value (scratchbuf + 1, 1, cmp_type);
15117       oappend (scratchbuf + intel_syntax);
15118       scratchbuf[0] = '\0';
15119     }
15120 }
15121
15122 static const struct op pclmul_op[] =
15123 {
15124   { STRING_COMMA_LEN ("lql") },
15125   { STRING_COMMA_LEN ("hql") },
15126   { STRING_COMMA_LEN ("lqh") },
15127   { STRING_COMMA_LEN ("hqh") }
15128 };
15129
15130 static void
15131 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15132               int sizeflag ATTRIBUTE_UNUSED)
15133 {
15134   unsigned int pclmul_type;
15135
15136   FETCH_DATA (the_info, codep + 1);
15137   pclmul_type = *codep++ & 0xff;
15138   switch (pclmul_type)
15139     {
15140     case 0x10:
15141       pclmul_type = 2;
15142       break;
15143     case 0x11:
15144       pclmul_type = 3;
15145       break;
15146     default:
15147       break;
15148     }
15149   if (pclmul_type < ARRAY_SIZE (pclmul_op))
15150     {
15151       char suffix [4];
15152       char *p = mnemonicendp - 3;
15153       suffix[0] = p[0];
15154       suffix[1] = p[1];
15155       suffix[2] = p[2];
15156       suffix[3] = '\0';
15157       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15158       mnemonicendp += pclmul_op[pclmul_type].len;
15159     }
15160   else
15161     {
15162       /* We have a reserved extension byte.  Output it directly.  */
15163       scratchbuf[0] = '$';
15164       print_operand_value (scratchbuf + 1, 1, pclmul_type);
15165       oappend (scratchbuf + intel_syntax);
15166       scratchbuf[0] = '\0';
15167     }
15168 }
15169
15170 static void
15171 MOVBE_Fixup (int bytemode, int sizeflag)
15172 {
15173   /* Add proper suffix to "movbe".  */
15174   char *p = mnemonicendp;
15175
15176   switch (bytemode)
15177     {
15178     case v_mode:
15179       if (intel_syntax)
15180         goto skip;
15181
15182       USED_REX (REX_W);
15183       if (sizeflag & SUFFIX_ALWAYS)
15184         {
15185           if (rex & REX_W)
15186             *p++ = 'q';
15187           else
15188             {
15189               if (sizeflag & DFLAG)
15190                 *p++ = 'l';
15191               else
15192                 *p++ = 'w';
15193               used_prefixes |= (prefixes & PREFIX_DATA);
15194             }
15195         }
15196       break;
15197     default:
15198       oappend (INTERNAL_DISASSEMBLER_ERROR);
15199       break;
15200     }
15201   mnemonicendp = p;
15202   *p = '\0';
15203
15204 skip:
15205   OP_M (bytemode, sizeflag);
15206 }
15207
15208 static void
15209 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15210 {
15211   int reg;
15212   const char **names;
15213
15214   /* Skip mod/rm byte.  */
15215   MODRM_CHECK;
15216   codep++;
15217
15218   if (vex.w)
15219     names = names64;
15220   else
15221     names = names32;
15222
15223   reg = modrm.rm;
15224   USED_REX (REX_B);
15225   if (rex & REX_B)
15226     reg += 8;
15227
15228   oappend (names[reg]);
15229 }
15230
15231 static void
15232 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15233 {
15234   const char **names;
15235
15236   if (vex.w)
15237     names = names64;
15238   else
15239     names = names32;
15240
15241   oappend (names[vex.register_specifier]);
15242 }
15243