opcodes/i386-opc.c

   1 /* Intel 80386 opcode table
   2    Copyright 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  20
  21 #include "sysdep.h"
  22 #include "i386-opc.h"
  23
  24 const template i386_optab[] =
  25 {
  26
  27 #define X None
  28 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
  29 #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
  30 #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
  31 #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf)
  32 #define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
  33 #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf)
  34 #define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf)
  35 #define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf)
  36 #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf)
  37 #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
  38 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
  39 #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
  40 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
  41 #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
  42 #define bwlq_Suf (No_sSuf|No_xSuf)
  43 #define FP (NoSuf)
  44 #define l_FP (l_Suf)
  45 #define q_FP (q_Suf|NoRex64)
  46 #define x_FP (x_Suf|FloatMF)
  47 #define sl_FP (sl_Suf|FloatMF)
  48
  49 /* Move instructions.  */
  50 /* We put the 64bit displacement first and we only mark constants
  51    larger than 32bit as Disp64.  */
  52 { "mov",   2,   0xa0, X, Cpu64,  bwlq_Suf|D|W,                  { Disp64, Acc, 0 } },
  53 { "mov",   2,   0xa0, X, CpuNo64,bwl_Suf|D|W,                   { Disp16|Disp32, Acc, 0 } },
  54 { "mov",   2,   0x88, X, 0,      bwlq_Suf|D|W|Modrm,            { Reg, Reg|AnyMem, 0} },
  55 /* In the 64bit mode the short form mov immediate is redefined to have
  56    64bit value.  */
  57 { "mov",   2,   0xb0, X, 0,      bwl_Suf|W|ShortForm,           { EncImm, Reg8|Reg16|Reg32, 0 } },
  58 { "mov",   2,   0xc6, 0, 0,      bwlq_Suf|W|Modrm,              { EncImm, Reg|AnyMem, 0 } },
  59 { "mov",   2,   0xb0, X, Cpu64,  q_Suf|W|ShortForm,             { Imm64, Reg64, 0 } },
  60 /* The segment register moves accept WordReg so that a segment register
  61    can be copied to a 32 bit register, and vice versa, without using a
  62    size prefix.  When moving to a 32 bit register, the upper 16 bits
  63    are set to an implementation defined value (on the Pentium Pro,
  64    the implementation defined value is zero).  */
  65 { "mov",   2,   0x8c, X, 0,      wl_Suf|Modrm,                  { SReg2, WordReg|InvMem, 0 } },
  66 { "mov",   2,   0x8c, X, 0,      w_Suf|Modrm|IgnoreSize,        { SReg2, WordMem, 0 } },
  67 { "mov",   2,   0x8c, X, Cpu386, wl_Suf|Modrm,                  { SReg3, WordReg|InvMem, 0 } },
  68 { "mov",   2,   0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize,        { SReg3, WordMem, 0 } },
  69 { "mov",   2,   0x8e, X, 0,      wl_Suf|Modrm|IgnoreSize,       { WordReg, SReg2, 0 } },
  70 { "mov",   2,   0x8e, X, 0,      w_Suf|Modrm|IgnoreSize,        { WordMem, SReg2, 0 } },
  71 { "mov",   2,   0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize,       { WordReg, SReg3, 0 } },
  72 { "mov",   2,   0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize,        { WordMem, SReg3, 0 } },
  73 /* Move to/from control debug registers.  In the 16 or 32bit modes they are 32bit.  In the 64bit
  74    mode they are 64bit.*/
  75 { "mov",   2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} },
  76 { "mov",   2, 0x0f20, X, Cpu64,  q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
  77 { "mov",   2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },
  78 { "mov",   2, 0x0f21, X, Cpu64,  q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
  79 { "mov",   2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,      { Test, Reg32|InvMem, 0} },
  80 { "movabs",2,   0xa0, X, Cpu64, bwlq_Suf|D|W,                   { Disp64, Acc, 0 } },
  81 { "movabs",2,   0xb0, X, Cpu64, q_Suf|W|ShortForm,              { Imm64, Reg64, 0 } },
  82
  83 /* Move with sign extend.  */
  84 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
  85    conflict with the "movs" string move instruction.  */
  86 {"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm,                   { Reg8|ByteMem, Reg32, 0} },
  87 {"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm,                   { Reg8|ByteMem, Reg16, 0} },
  88 {"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm,                   { Reg16|ShortMem,Reg32, 0} },
  89 {"movsbq", 2, 0x0fbe, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg8|ByteMem, Reg64, 0} },
  90 {"movswq", 2, 0x0fbf, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg16|ShortMem,Reg64, 0} },
  91 {"movslq", 2,   0x63, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg32|WordMem, Reg64, 0} },
  92 /* Intel Syntax next 3 insns */
  93 {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },
  94 {"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32|Reg64, 0} },
  95 {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,             { Reg32|WordMem, Reg64, 0} },
  96
  97 /* Move with zero extend.  We can't remove "movzb" since existing
  98    assembly codes may use it.  */
  99 {"movzb",  2, 0x0fb6, X, Cpu386, wl_Suf|Modrm,                  { Reg8|ByteMem, WordReg, 0} },
 100 /* "movzbl" & "movzbw" should not be unified into "movzb" for
 101    consistency with the sign extending moves above.  */
 102 {"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,                   { Reg8|ByteMem, Reg32, 0} },
 103 {"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,                   { Reg8|ByteMem, Reg16, 0} },
 104 {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm,                   { Reg16|ShortMem, Reg32, 0} },
 105 /* These instructions are not particulary useful, since the zero extend
 106    32->64 is implicit, but we can encode them.  */
 107 {"movzbq", 2, 0x0fb6, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg8|ByteMem,   Reg64, 0} },
 108 {"movzwq", 2, 0x0fb7, X, Cpu64,  NoSuf|Modrm|Rex64,             { Reg16|ShortMem, Reg64, 0} },
 109 /* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful,
 110    since the zero extend 32->64 is implicit, but we can encode them).  */
 111 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },
 112 {"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32|Reg64, 0} },
 113
 114 /* Push instructions.  */
 115 {"push",   1,   0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
 116 {"push",   1,   0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem, 0, 0 } },
 117 {"push",   1,   0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm8S, 0, 0} },
 118 {"push",   1,   0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm16|Imm32, 0, 0} },
 119 {"push",   1,   0x06, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { SReg2, 0, 0 } },
 120 {"push",   1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|ShortForm|DefaultSize, { SReg3, 0, 0 } },
 121 /* In 64bit mode, the operand size is implicitly 64bit.  */
 122 {"push",   1,   0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } },
 123 {"push",   1,   0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
 124 {"push",   1,   0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
 125 {"push",   1,   0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
 126 {"push",   1, 0x0fa0, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 127
 128 {"pusha",  0,   0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { 0, 0, 0 } },
 129
 130 /* Pop instructions.  */
 131 {"pop",    1,   0x58, X, CpuNo64,        wl_Suf|ShortForm|DefaultSize,  { WordReg, 0, 0 } },
 132 {"pop",    1,   0x8f, 0, CpuNo64,        wl_Suf|Modrm|DefaultSize,      { WordReg|WordMem, 0, 0 } },
 133 {"pop",    1,   0x07, X, CpuNo64,        wl_Suf|ShortForm|DefaultSize,  { SReg2, 0, 0 } },
 134 {"pop",    1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|ShortForm|DefaultSize,  { SReg3, 0, 0 } },
 135 /* In 64bit mode, the operand size is implicitly 64bit.  */
 136 {"pop",    1,   0x58, X, Cpu64,  wq_Suf|ShortForm|DefaultSize|NoRex64,  { Reg16|Reg64, 0, 0 } },
 137 {"pop",    1,   0x8f, 0, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,      { Reg16|Reg64|WordMem, 0, 0 } },
 138 {"pop",    1, 0x0fa1, X, Cpu64,  wq_Suf|ShortForm|DefaultSize|NoRex64,  { SReg3, 0, 0 } },
 139
 140 {"popa",   0,   0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,            { 0, 0, 0 } },
 141
 142 /* Exchange instructions.
 143    xchg commutes:  we allow both operand orders.
 144
 145    In the 64bit code, xchg rax, rax is reused for new nop instruction.  */
 146 {"xchg",   2,   0x90, X, CpuNo64, wl_Suf|ShortForm,     { WordReg, Acc, 0 } },
 147 {"xchg",   2,   0x90, X, CpuNo64, wl_Suf|ShortForm,     { Acc, WordReg, 0 } },
 148 {"xchg",   2,   0x90, X, Cpu64, wq_Suf|ShortForm,       { Reg16|Reg64, Acc, 0 } },
 149 {"xchg",   2,   0x90, X, Cpu64, wq_Suf|ShortForm,       { Acc, Reg16|Reg64, 0 } },
 150 {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg, Reg|AnyMem, 0 } },
 151 {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Reg, 0 } },
 152
 153 /* In/out from ports.  */
 154 /* XXX should reject %rax */
 155 {"in",     2,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, Acc, 0 } },
 156 {"in",     2,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, Acc, 0 } },
 157 {"in",     1,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },
 158 {"in",     1,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, 0, 0 } },
 159 {"out",    2,   0xe6, X, 0,      bwl_Suf|W,             { Acc, Imm8, 0 } },
 160 {"out",    2,   0xee, X, 0,      bwl_Suf|W,             { Acc, InOutPortReg, 0 } },
 161 {"out",    1,   0xe6, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },
 162 {"out",    1,   0xee, X, 0,      bwl_Suf|W,             { InOutPortReg, 0, 0 } },
 163
 164 /* Load effective address.  */
 165 {"lea",    2, 0x8d,   X, 0,      wlq_Suf|Modrm,         { WordMem, WordReg, 0 } },
 166
 167 /* Load segment registers from memory.  */
 168 {"lds",    2,   0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
 169 {"les",    2,   0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} },
 170 {"lfs",    2, 0x0fb4, X, Cpu386, wl_Suf|Modrm,          { WordMem, WordReg, 0} },
 171 {"lgs",    2, 0x0fb5, X, Cpu386, wl_Suf|Modrm,          { WordMem, WordReg, 0} },
 172 {"lss",    2, 0x0fb2, X, Cpu386, wl_Suf|Modrm,          { WordMem, WordReg, 0} },
 173
 174 /* Flags register instructions.  */
 175 {"clc",    0,   0xf8, X, 0,      NoSuf,                 { 0, 0, 0} },
 176 {"cld",    0,   0xfc, X, 0,      NoSuf,                 { 0, 0, 0} },
 177 {"cli",    0,   0xfa, X, 0,      NoSuf,                 { 0, 0, 0} },
 178 {"clts",   0, 0x0f06, X, Cpu286, NoSuf,                 { 0, 0, 0} },
 179 {"cmc",    0,   0xf5, X, 0,      NoSuf,                 { 0, 0, 0} },
 180 {"lahf",   0,   0x9f, X, 0,      NoSuf,                 { 0, 0, 0} },
 181 {"sahf",   0,   0x9e, X, 0,      NoSuf,                 { 0, 0, 0} },
 182 {"pushf",  0,   0x9c, X, CpuNo64,wl_Suf|DefaultSize,    { 0, 0, 0} },
 183 {"pushf",  0,   0x9c, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 184 {"popf",   0,   0x9d, X, CpuNo64,wl_Suf|DefaultSize,    { 0, 0, 0} },
 185 {"popf",   0,   0x9d, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 186 {"stc",    0,   0xf9, X, 0,      NoSuf,                 { 0, 0, 0} },
 187 {"std",    0,   0xfd, X, 0,      NoSuf,                 { 0, 0, 0} },
 188 {"sti",    0,   0xfb, X, 0,      NoSuf,                 { 0, 0, 0} },
 189
 190 /* Arithmetic.  */
 191 {"add",    2,   0x00, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 192 {"add",    2,   0x83, 0, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 193 {"add",    2,   0x04, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 194 {"add",    2,   0x80, 0, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 195
 196 {"inc",    1,   0x40, X, CpuNo64,wl_Suf|ShortForm,      { WordReg, 0, 0} },
 197 {"inc",    1,   0xfe, 0, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 198
 199 {"sub",    2,   0x28, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 200 {"sub",    2,   0x83, 5, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 201 {"sub",    2,   0x2c, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 202 {"sub",    2,   0x80, 5, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 203
 204 {"dec",    1,   0x48, X, CpuNo64, wl_Suf|ShortForm,     { WordReg, 0, 0} },
 205 {"dec",    1,   0xfe, 1, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 206
 207 {"sbb",    2,   0x18, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 208 {"sbb",    2,   0x83, 3, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 209 {"sbb",    2,   0x1c, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 210 {"sbb",    2,   0x80, 3, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 211
 212 {"cmp",    2,   0x38, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 213 {"cmp",    2,   0x83, 7, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 214 {"cmp",    2,   0x3c, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 215 {"cmp",    2,   0x80, 7, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 216
 217 {"test",   2,   0x84, X, 0,      bwlq_Suf|W|Modrm,      { Reg, Reg|AnyMem, 0} },
 218 {"test",   2,   0x84, X, 0,      bwlq_Suf|W|Modrm,      { AnyMem, Reg, 0} },
 219 {"test",   2,   0xa8, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 220 {"test",   2,   0xf6, 0, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 221
 222 {"and",    2,   0x20, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 223 {"and",    2,   0x83, 4, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 224 {"and",    2,   0x24, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 225 {"and",    2,   0x80, 4, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 226
 227 {"or",     2,   0x08, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 228 {"or",     2,   0x83, 1, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 229 {"or",     2,   0x0c, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 230 {"or",     2,   0x80, 1, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 231
 232 {"xor",    2,   0x30, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 233 {"xor",    2,   0x83, 6, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 234 {"xor",    2,   0x34, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 235 {"xor",    2,   0x80, 6, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 236
 237 /* clr with 1 operand is really xor with 2 operands.  */
 238 {"clr",    1,   0x30, X, 0,      bwlq_Suf|W|Modrm|regKludge,    { Reg, 0, 0 } },
 239
 240 {"adc",    2,   0x10, X, 0,      bwlq_Suf|D|W|Modrm,    { Reg, Reg|AnyMem, 0} },
 241 {"adc",    2,   0x83, 2, 0,      wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, 0} },
 242 {"adc",    2,   0x14, X, 0,      bwlq_Suf|W,            { EncImm, Acc, 0} },
 243 {"adc",    2,   0x80, 2, 0,      bwlq_Suf|W|Modrm,      { EncImm, Reg|AnyMem, 0} },
 244
 245 {"neg",    1,   0xf6, 3, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 246 {"not",    1,   0xf6, 2, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 247
 248 {"aaa",    0,   0x37, X, CpuNo64,        NoSuf,                 { 0, 0, 0} },
 249 {"aas",    0,   0x3f, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
 250 {"daa",    0,   0x27, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
 251 {"das",    0,   0x2f, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
 252 {"aad",    0, 0xd50a, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
 253 {"aad",    1,   0xd5, X, CpuNo64,       NoSuf,                  { Imm8, 0, 0} },
 254 {"aam",    0, 0xd40a, X, CpuNo64,       NoSuf,                  { 0, 0, 0} },
 255 {"aam",    1,   0xd4, X, CpuNo64,       NoSuf,                  { Imm8, 0, 0} },
 256
 257 /* Conversion insns.  */
 258 /* Intel naming */
 259 {"cbw",    0,   0x98, X, 0,      NoSuf|Size16,          { 0, 0, 0} },
 260 {"cdqe",   0,   0x98, X, Cpu64,  NoSuf|Size64,          { 0, 0, 0} },
 261 {"cwde",   0,   0x98, X, 0,      NoSuf|Size32,          { 0, 0, 0} },
 262 {"cwd",    0,   0x99, X, 0,      NoSuf|Size16,          { 0, 0, 0} },
 263 {"cdq",    0,   0x99, X, 0,      NoSuf|Size32,          { 0, 0, 0} },
 264 {"cqo",    0,   0x99, X, Cpu64,  NoSuf|Size64,          { 0, 0, 0} },
 265 /* AT&T naming */
 266 {"cbtw",   0,   0x98, X, 0,      NoSuf|Size16,          { 0, 0, 0} },
 267 {"cltq",   0,   0x98, X, Cpu64,  NoSuf|Size64,          { 0, 0, 0} },
 268 {"cwtl",   0,   0x98, X, 0,      NoSuf|Size32,          { 0, 0, 0} },
 269 {"cwtd",   0,   0x99, X, 0,      NoSuf|Size16,          { 0, 0, 0} },
 270 {"cltd",   0,   0x99, X, 0,      NoSuf|Size32,          { 0, 0, 0} },
 271 {"cqto",   0,   0x99, X, Cpu64,  NoSuf|Size64,          { 0, 0, 0} },
 272
 273 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
 274    expanding 64-bit multiplies, and *cannot* be selected to accomplish
 275    'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
 276    These multiplies can only be selected with single operand forms.  */
 277 {"mul",    1,   0xf6, 4, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 278 {"imul",   1,   0xf6, 5, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 279 {"imul",   2, 0x0faf, X, Cpu386, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
 280 {"imul",   3,   0x6b, X, Cpu186, wlq_Suf|Modrm,         { Imm8S, WordReg|WordMem, WordReg} },
 281 {"imul",   3,   0x69, X, Cpu186, wlq_Suf|Modrm,         { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} },
 282 /* imul with 2 operands mimics imul with 3 by putting the register in
 283    both i.rm.reg & i.rm.regmem fields.  regKludge enables this
 284    transformation.  */
 285 {"imul",   2,   0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
 286 {"imul",   2,   0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
 287
 288 {"div",    1,   0xf6, 6, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 289 {"div",    2,   0xf6, 6, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Acc, 0} },
 290 {"idiv",   1,   0xf6, 7, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 291 {"idiv",   2,   0xf6, 7, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Acc, 0} },
 292
 293 {"rol",    2,   0xd0, 0, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 294 {"rol",    2,   0xc0, 0, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 295 {"rol",    2,   0xd2, 0, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 296 {"rol",    1,   0xd0, 0, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 297
 298 {"ror",    2,   0xd0, 1, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 299 {"ror",    2,   0xc0, 1, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 300 {"ror",    2,   0xd2, 1, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 301 {"ror",    1,   0xd0, 1, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 302
 303 {"rcl",    2,   0xd0, 2, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 304 {"rcl",    2,   0xc0, 2, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 305 {"rcl",    2,   0xd2, 2, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 306 {"rcl",    1,   0xd0, 2, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 307
 308 {"rcr",    2,   0xd0, 3, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 309 {"rcr",    2,   0xc0, 3, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 310 {"rcr",    2,   0xd2, 3, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 311 {"rcr",    1,   0xd0, 3, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 312
 313 {"sal",    2,   0xd0, 4, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 314 {"sal",    2,   0xc0, 4, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 315 {"sal",    2,   0xd2, 4, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 316 {"sal",    1,   0xd0, 4, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 317
 318 {"shl",    2,   0xd0, 4, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 319 {"shl",    2,   0xc0, 4, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 320 {"shl",    2,   0xd2, 4, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 321 {"shl",    1,   0xd0, 4, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 322
 323 {"shr",    2,   0xd0, 5, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 324 {"shr",    2,   0xc0, 5, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 325 {"shr",    2,   0xd2, 5, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 326 {"shr",    1,   0xd0, 5, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 327
 328 {"sar",    2,   0xd0, 7, 0,      bwlq_Suf|W|Modrm,      { Imm1, Reg|AnyMem, 0} },
 329 {"sar",    2,   0xc0, 7, Cpu186, bwlq_Suf|W|Modrm,      { Imm8, Reg|AnyMem, 0} },
 330 {"sar",    2,   0xd2, 7, 0,      bwlq_Suf|W|Modrm,      { ShiftCount, Reg|AnyMem, 0} },
 331 {"sar",    1,   0xd0, 7, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, 0, 0} },
 332
 333 {"shld",   3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg, WordReg|WordMem} },
 334 {"shld",   3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm,         { ShiftCount, WordReg, WordReg|WordMem} },
 335 {"shld",   2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
 336
 337 {"shrd",   3, 0x0fac, X, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg, WordReg|WordMem} },
 338 {"shrd",   3, 0x0fad, X, Cpu386, wlq_Suf|Modrm,         { ShiftCount, WordReg, WordReg|WordMem} },
 339 {"shrd",   2, 0x0fad, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
 340
 341 /* Control transfer instructions.  */
 342 {"call",   1,   0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
 343 {"call",   1,   0xe8, X, Cpu64,  wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} },
 344 {"call",   1,   0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem|JumpAbsolute, 0, 0} },
 345 {"call",   1,   0xff, 2, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} },
 346 /* Intel Syntax */
 347 {"call",   2,   0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
 348 /* Intel Syntax */
 349 {"call",   1,   0xff, 3, 0,      x_Suf|Modrm|DefaultSize,       {WordMem|JumpAbsolute, 0, 0} },
 350 {"lcall",  2,   0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} },
 351 {"lcall",  1,   0xff, 3, 0,      wl_Suf|Modrm|DefaultSize,      {WordMem|JumpAbsolute, 0, 0} },
 352
 353 {"jmp",    1,   0xeb, X, 0,      NoSuf|Jump,            { Disp,0, 0} },
 354 {"jmp",    1,   0xff, 4, CpuNo64, wl_Suf|Modrm,         { WordReg|WordMem|JumpAbsolute, 0, 0} },
 355 {"jmp",    1,   0xff, 4, Cpu64,  wq_Suf|Modrm|NoRex64,  { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} },
 356 /* Intel Syntax.  */
 357 {"jmp",    2,   0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
 358 /* Intel Syntax.  */
 359 {"jmp",    1,   0xff, 5, 0,      x_Suf|Modrm,           { WordMem|JumpAbsolute, 0, 0} },
 360 {"ljmp",   2,   0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
 361 {"ljmp",   1,   0xff, 5, 0,      wl_Suf|Modrm,          { WordMem|JumpAbsolute, 0, 0} },
 362
 363 {"ret",    0,   0xc3, X, CpuNo64,wl_Suf|DefaultSize,    { 0, 0, 0} },
 364 {"ret",    1,   0xc2, X, CpuNo64,wl_Suf|DefaultSize,    { Imm16, 0, 0} },
 365 {"ret",    0,   0xc3, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 366 {"ret",    1,   0xc2, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
 367 {"lret",   0,   0xcb, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
 368 {"lret",   1,   0xca, X, 0,      wlq_Suf|DefaultSize,   { Imm16, 0, 0} },
 369 {"enter",  2,   0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { Imm16, Imm8, 0} },
 370 {"enter",  2,   0xc8, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,    { Imm16, Imm8, 0} },
 371 {"leave",  0,   0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { 0, 0, 0} },
 372 {"leave",  0,   0xc9, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,    { 0, 0, 0} },
 373
 374 /* Conditional jumps.  */
 375 {"jo",     1,   0x70, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 376 {"jno",    1,   0x71, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 377 {"jb",     1,   0x72, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 378 {"jc",     1,   0x72, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 379 {"jnae",   1,   0x72, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 380 {"jnb",    1,   0x73, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 381 {"jnc",    1,   0x73, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 382 {"jae",    1,   0x73, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 383 {"je",     1,   0x74, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 384 {"jz",     1,   0x74, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 385 {"jne",    1,   0x75, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 386 {"jnz",    1,   0x75, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 387 {"jbe",    1,   0x76, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 388 {"jna",    1,   0x76, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 389 {"jnbe",   1,   0x77, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 390 {"ja",     1,   0x77, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 391 {"js",     1,   0x78, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 392 {"jns",    1,   0x79, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 393 {"jp",     1,   0x7a, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 394 {"jpe",    1,   0x7a, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 395 {"jnp",    1,   0x7b, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 396 {"jpo",    1,   0x7b, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 397 {"jl",     1,   0x7c, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 398 {"jnge",   1,   0x7c, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 399 {"jnl",    1,   0x7d, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 400 {"jge",    1,   0x7d, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 401 {"jle",    1,   0x7e, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 402 {"jng",    1,   0x7e, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 403 {"jnle",   1,   0x7f, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 404 {"jg",     1,   0x7f, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
 405
 406 /* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
 407 {"jcxz",  1,    0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} },
 408 {"jecxz",  1,   0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
 409 {"jecxz",  1,   0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
 410 {"jrcxz",  1,   0xe3, X, Cpu64,  NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} },
 411
 412 /* The loop instructions also use the address size prefix to select
 413    %cx rather than %ecx for the loop count, so the `w' form of these
 414    instructions emit an address size prefix rather than a data size
 415    prefix.  */
 416 {"loop",   1,   0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
 417 {"loop",   1,   0xe2, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 418 {"loopz",  1,   0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
 419 {"loopz",  1,   0xe1, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 420 {"loope",  1,   0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
 421 {"loope",  1,   0xe1, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 422 {"loopnz", 1,   0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
 423 {"loopnz", 1,   0xe0, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 424 {"loopne", 1,   0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
 425 {"loopne", 1,   0xe0, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 426
 427 /* Set byte on flag instructions.  */
 428 {"seto",   1, 0x0f90, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 429 {"setno",  1, 0x0f91, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 430 {"setb",   1, 0x0f92, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 431 {"setc",   1, 0x0f92, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 432 {"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 433 {"setnb",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 434 {"setnc",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 435 {"setae",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 436 {"sete",   1, 0x0f94, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 437 {"setz",   1, 0x0f94, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 438 {"setne",  1, 0x0f95, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 439 {"setnz",  1, 0x0f95, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 440 {"setbe",  1, 0x0f96, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 441 {"setna",  1, 0x0f96, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 442 {"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 443 {"seta",   1, 0x0f97, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 444 {"sets",   1, 0x0f98, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 445 {"setns",  1, 0x0f99, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 446 {"setp",   1, 0x0f9a, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 447 {"setpe",  1, 0x0f9a, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 448 {"setnp",  1, 0x0f9b, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 449 {"setpo",  1, 0x0f9b, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 450 {"setl",   1, 0x0f9c, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 451 {"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 452 {"setnl",  1, 0x0f9d, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 453 {"setge",  1, 0x0f9d, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 454 {"setle",  1, 0x0f9e, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 455 {"setng",  1, 0x0f9e, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 456 {"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 457 {"setg",   1, 0x0f9f, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
 458
 459 /* String manipulation.  */
 460 {"cmps",   0,   0xa6, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 461 {"cmps",   2,   0xa6, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, AnyMem, 0} },
 462 {"scmp",   0,   0xa6, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 463 {"scmp",   2,   0xa6, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, AnyMem, 0} },
 464 {"ins",    0,   0x6c, X, Cpu186, bwl_Suf|W|IsString,    { 0, 0, 0} },
 465 {"ins",    2,   0x6c, X, Cpu186, bwl_Suf|W|IsString,    { InOutPortReg, AnyMem|EsSeg, 0} },
 466 {"outs",   0,   0x6e, X, Cpu186, bwl_Suf|W|IsString,    { 0, 0, 0} },
 467 {"outs",   2,   0x6e, X, Cpu186, bwl_Suf|W|IsString,    { AnyMem, InOutPortReg, 0} },
 468 {"lods",   0,   0xac, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 469 {"lods",   1,   0xac, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, 0, 0} },
 470 {"lods",   2,   0xac, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, Acc, 0} },
 471 {"slod",   0,   0xac, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 472 {"slod",   1,   0xac, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, 0, 0} },
 473 {"slod",   2,   0xac, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, Acc, 0} },
 474 {"movs",   0,   0xa4, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 475 {"movs",   2,   0xa4, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, AnyMem|EsSeg, 0} },
 476 {"smov",   0,   0xa4, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 477 {"smov",   2,   0xa4, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, AnyMem|EsSeg, 0} },
 478 {"scas",   0,   0xae, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 479 {"scas",   1,   0xae, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, 0, 0} },
 480 {"scas",   2,   0xae, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, Acc, 0} },
 481 {"ssca",   0,   0xae, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 482 {"ssca",   1,   0xae, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, 0, 0} },
 483 {"ssca",   2,   0xae, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, Acc, 0} },
 484 {"stos",   0,   0xaa, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 485 {"stos",   1,   0xaa, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, 0, 0} },
 486 {"stos",   2,   0xaa, X, 0,      bwlq_Suf|W|IsString,   { Acc, AnyMem|EsSeg, 0} },
 487 {"ssto",   0,   0xaa, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 488 {"ssto",   1,   0xaa, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, 0, 0} },
 489 {"ssto",   2,   0xaa, X, 0,      bwlq_Suf|W|IsString,   { Acc, AnyMem|EsSeg, 0} },
 490 {"xlat",   0,   0xd7, X, 0,      b_Suf|IsString,        { 0, 0, 0} },
 491 {"xlat",   1,   0xd7, X, 0,      b_Suf|IsString,        { AnyMem, 0, 0} },
 492
 493 /* Bit manipulation.  */
 494 {"bsf",    2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
 495 {"bsr",    2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
 496 {"bt",     2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
 497 {"bt",     2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg|WordMem, 0} },
 498 {"btc",    2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
 499 {"btc",    2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg|WordMem, 0} },
 500 {"btr",    2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
 501 {"btr",    2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg|WordMem, 0} },
 502 {"bts",    2, 0x0fab, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
 503 {"bts",    2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg|WordMem, 0} },
 504
 505 /* Interrupts & op. sys insns.  */
 506 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
 507    int 3 insn.  */
 508 {"int",    1,   0xcd, X, 0,      NoSuf,                 { Imm8, 0, 0} },
 509 {"int3",   0,   0xcc, X, 0,      NoSuf,                 { 0, 0, 0} },
 510 {"into",   0,   0xce, X, CpuNo64,        NoSuf,                 { 0, 0, 0} },
 511 {"iret",   0,   0xcf, X, 0,      wlq_Suf|DefaultSize,   { 0, 0, 0} },
 512 /* i386sl, i486sl, later 486, and Pentium.  */
 513 {"rsm",    0, 0x0faa, X, Cpu386, NoSuf,                 { 0, 0, 0} },
 514
 515 {"bound",  2,   0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm,          { WordReg, WordMem, 0} },
 516
 517 {"hlt",    0,   0xf4, X, 0,      NoSuf,                 { 0, 0, 0} },
 518
 519 {"nop",    1, 0x0f1f, X, Cpu686, wl_Suf|Modrm,          { WordMem, 0, 0} },
 520
 521 /* nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
 522    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
 523 {"nop",    0,   0x90, X, 0,      NoSuf,                 { 0, 0, 0} },
 524
 525 /* Protection control.  */
 526 {"arpl",   2,   0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
 527 {"lar",    2, 0x0f02, X, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
 528 {"lgdt",   1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
 529 {"lgdt",   1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
 530 {"lidt",   1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
 531 {"lidt",   1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
 532 {"lldt",   1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
 533 {"lmsw",   1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
 534 {"lsl",    2, 0x0f03, X, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
 535 {"ltr",    1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
 536
 537 {"sgdt",   1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
 538 {"sgdt",   1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
 539 {"sidt",   1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm,          { WordMem, 0, 0} },
 540 {"sidt",   1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64,            { LLongMem, 0, 0} },
 541 {"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
 542 {"sldt",   1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
 543 {"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
 544 {"smsw",   1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
 545 {"str",    1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
 546 {"str",    1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
 547
 548 {"verr",   1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
 549 {"verw",   1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
 550
 551 /* Floating point instructions.  */
 552
 553 /* load */
 554 {"fld",    1, 0xd9c0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 555 {"fld",    1,   0xd9, 0, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 556 {"fld",    1, 0xd9c0, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
 557 /* Intel Syntax */
 558 {"fld",    1,   0xdb, 5, 0,      x_FP|Modrm,            { LLongMem, 0, 0} },
 559 {"fild",   1,   0xdf, 0, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 560 {"fild",   1,   0xdf, 5, 0,      q_FP|Modrm,            { LLongMem, 0, 0} },
 561 {"fildll", 1,   0xdf, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },
 562 {"fldt",   1,   0xdb, 5, 0,      FP|Modrm,              { LLongMem, 0, 0} },
 563 {"fbld",   1,   0xdf, 4, 0,      x_Suf|Modrm,           { LLongMem, 0, 0} },
 564
 565 /* store (no pop) */
 566 {"fst",    1, 0xddd0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 567 {"fst",    1,   0xd9, 2, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 568 {"fst",    1, 0xddd0, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
 569 {"fist",   1,   0xdf, 2, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 570
 571 /* store (with pop) */
 572 {"fstp",   1, 0xddd8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 573 {"fstp",   1,   0xd9, 3, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 574 {"fstp",   1, 0xddd8, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
 575 /* Intel Syntax */
 576 {"fstp",   1,   0xdb, 7, 0,      x_FP|Modrm,            { LLongMem, 0, 0} },
 577 {"fistp",  1,   0xdf, 3, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 578 {"fistp",  1,   0xdf, 7, 0,      q_FP|Modrm,            { LLongMem, 0, 0} },
 579 {"fistpll",1,   0xdf, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },
 580 {"fstpt",  1,   0xdb, 7, 0,      FP|Modrm,              { LLongMem, 0, 0} },
 581 {"fbstp",  1,   0xdf, 6, 0,      x_Suf|Modrm,           { LLongMem, 0, 0} },
 582
 583 /* exchange %st<n> with %st0 */
 584 {"fxch",   1, 0xd9c8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 585 /* alias for fxch %st(1) */
 586 {"fxch",   0, 0xd9c9, X, 0,      FP,                    { 0, 0, 0} },
 587
 588 /* comparison (without pop) */
 589 {"fcom",   1, 0xd8d0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 590 /* alias for fcom %st(1) */
 591 {"fcom",   0, 0xd8d1, X, 0,      FP,                    { 0, 0, 0} },
 592 {"fcom",   1,   0xd8, 2, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 593 {"fcom",   1, 0xd8d0, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
 594 {"ficom",  1,   0xde, 2, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 595
 596 /* comparison (with pop) */
 597 {"fcomp",  1, 0xd8d8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 598 /* alias for fcomp %st(1) */
 599 {"fcomp",  0, 0xd8d9, X, 0,      FP,                    { 0, 0, 0} },
 600 {"fcomp",  1,   0xd8, 3, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 601 {"fcomp",  1, 0xd8d8, X, 0,      l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
 602 {"ficomp", 1,   0xde, 3, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 603 {"fcompp", 0, 0xded9, X, 0,      FP,                    { 0, 0, 0} },
 604
 605 /* unordered comparison (with pop) */
 606 {"fucom",  1, 0xdde0, X, Cpu286, FP|ShortForm,          { FloatReg, 0, 0} },
 607 /* alias for fucom %st(1) */
 608 {"fucom",  0, 0xdde1, X, Cpu286, FP,                    { 0, 0, 0} },
 609 {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm,          { FloatReg, 0, 0} },
 610 /* alias for fucomp %st(1) */
 611 {"fucomp", 0, 0xdde9, X, Cpu286, FP,                    { 0, 0, 0} },
 612 {"fucompp",0, 0xdae9, X, Cpu286, FP,                    { 0, 0, 0} },
 613
 614 {"ftst",   0, 0xd9e4, X, 0,      FP,                    { 0, 0, 0} },
 615 {"fxam",   0, 0xd9e5, X, 0,      FP,                    { 0, 0, 0} },
 616
 617 /* load constants into %st0 */
 618 {"fld1",   0, 0xd9e8, X, 0,      FP,                    { 0, 0, 0} },
 619 {"fldl2t", 0, 0xd9e9, X, 0,      FP,                    { 0, 0, 0} },
 620 {"fldl2e", 0, 0xd9ea, X, 0,      FP,                    { 0, 0, 0} },
 621 {"fldpi",  0, 0xd9eb, X, 0,      FP,                    { 0, 0, 0} },
 622 {"fldlg2", 0, 0xd9ec, X, 0,      FP,                    { 0, 0, 0} },
 623 {"fldln2", 0, 0xd9ed, X, 0,      FP,                    { 0, 0, 0} },
 624 {"fldz",   0, 0xd9ee, X, 0,      FP,                    { 0, 0, 0} },
 625
 626 /* Arithmetic.  */
 627
 628 /* add */
 629 {"fadd",   2, 0xd8c0, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },
 630 /* alias for fadd %st(i), %st */
 631 {"fadd",   1, 0xd8c0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 632 #if SYSV386_COMPAT
 633 /* alias for faddp */
 634 {"fadd",   0, 0xdec1, X, 0,      FP|Ugh,                { 0, 0, 0} },
 635 #endif
 636 {"fadd",   1,   0xd8, 0, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 637 {"fiadd",  1,   0xde, 0, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 638
 639 {"faddp",  2, 0xdec0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 640 {"faddp",  1, 0xdec0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 641 /* alias for faddp %st, %st(1) */
 642 {"faddp",  0, 0xdec1, X, 0,      FP,                    { 0, 0, 0} },
 643 {"faddp",  2, 0xdec0, X, 0,      FP|ShortForm|Ugh,      { FloatReg, FloatAcc, 0} },
 644
 645 /* subtract */
 646 {"fsub",   1, 0xd8e0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 647 #if SYSV386_COMPAT
 648 {"fsub",   2, 0xd8e0, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },
 649 /* alias for fsubp */
 650 {"fsub",   0, 0xdee1, X, 0,      FP|Ugh,                { 0, 0, 0} },
 651 #else
 652 {"fsub",   2, 0xd8e0, X, 0,      FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
 653 #endif
 654 {"fsub",   1,   0xd8, 4, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 655 {"fisub",  1,   0xde, 4, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 656
 657 #if SYSV386_COMPAT
 658 {"fsubp",  2, 0xdee0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 659 {"fsubp",  1, 0xdee0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 660 {"fsubp",  0, 0xdee1, X, 0,      FP,                    { 0, 0, 0} },
 661 #if OLDGCC_COMPAT
 662 {"fsubp",  2, 0xdee0, X, 0,      FP|ShortForm|Ugh,      { FloatReg, FloatAcc, 0} },
 663 #endif
 664 #else
 665 {"fsubp",  2, 0xdee8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 666 {"fsubp",  1, 0xdee8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 667 {"fsubp",  0, 0xdee9, X, 0,      FP,                    { 0, 0, 0} },
 668 #endif
 669
 670 /* subtract reverse */
 671 {"fsubr",  1, 0xd8e8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 672 #if SYSV386_COMPAT
 673 {"fsubr",  2, 0xd8e8, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },
 674 /* alias for fsubrp */
 675 {"fsubr",  0, 0xdee9, X, 0,      FP|Ugh,                { 0, 0, 0} },
 676 #else
 677 {"fsubr",  2, 0xd8e8, X, 0,      FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
 678 #endif
 679 {"fsubr",  1,   0xd8, 5, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 680 {"fisubr", 1,   0xde, 5, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 681
 682 #if SYSV386_COMPAT
 683 {"fsubrp", 2, 0xdee8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 684 {"fsubrp", 1, 0xdee8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 685 {"fsubrp", 0, 0xdee9, X, 0,      FP,                    { 0, 0, 0} },
 686 #if OLDGCC_COMPAT
 687 {"fsubrp", 2, 0xdee8, X, 0,      FP|ShortForm|Ugh,      { FloatReg, FloatAcc, 0} },
 688 #endif
 689 #else
 690 {"fsubrp", 2, 0xdee0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 691 {"fsubrp", 1, 0xdee0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 692 {"fsubrp", 0, 0xdee1, X, 0,      FP,                    { 0, 0, 0} },
 693 #endif
 694
 695 /* multiply */
 696 {"fmul",   2, 0xd8c8, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },
 697 {"fmul",   1, 0xd8c8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 698 #if SYSV386_COMPAT
 699 /* alias for fmulp */
 700 {"fmul",   0, 0xdec9, X, 0,      FP|Ugh,                { 0, 0, 0} },
 701 #endif
 702 {"fmul",   1,   0xd8, 1, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 703 {"fimul",  1,   0xde, 1, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 704
 705 {"fmulp",  2, 0xdec8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 706 {"fmulp",  1, 0xdec8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 707 {"fmulp",  0, 0xdec9, X, 0,      FP,                    { 0, 0, 0} },
 708 {"fmulp",  2, 0xdec8, X, 0,      FP|ShortForm|Ugh,      { FloatReg, FloatAcc, 0} },
 709
 710 /* divide */
 711 {"fdiv",   1, 0xd8f0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 712 #if SYSV386_COMPAT
 713 {"fdiv",   2, 0xd8f0, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },
 714 /* alias for fdivp */
 715 {"fdiv",   0, 0xdef1, X, 0,      FP|Ugh,                { 0, 0, 0} },
 716 #else
 717 {"fdiv",   2, 0xd8f0, X, 0,      FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
 718 #endif
 719 {"fdiv",   1,   0xd8, 6, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 720 {"fidiv",  1,   0xde, 6, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 721
 722 #if SYSV386_COMPAT
 723 {"fdivp",  2, 0xdef0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 724 {"fdivp",  1, 0xdef0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 725 {"fdivp",  0, 0xdef1, X, 0,      FP,                    { 0, 0, 0} },
 726 #if OLDGCC_COMPAT
 727 {"fdivp",  2, 0xdef0, X, 0,      FP|ShortForm|Ugh,      { FloatReg, FloatAcc, 0} },
 728 #endif
 729 #else
 730 {"fdivp",  2, 0xdef8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 731 {"fdivp",  1, 0xdef8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 732 {"fdivp",  0, 0xdef9, X, 0,      FP,                    { 0, 0, 0} },
 733 #endif
 734
 735 /* divide reverse */
 736 {"fdivr",  1, 0xd8f8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 737 #if SYSV386_COMPAT
 738 {"fdivr",  2, 0xd8f8, X, 0,      FP|ShortForm|FloatD,   { FloatReg, FloatAcc, 0} },
 739 /* alias for fdivrp */
 740 {"fdivr",  0, 0xdef9, X, 0,      FP|Ugh,                { 0, 0, 0} },
 741 #else
 742 {"fdivr",  2, 0xd8f8, X, 0,      FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
 743 #endif
 744 {"fdivr",  1,   0xd8, 7, 0,      sl_FP|Modrm,           { LongMem|LLongMem, 0, 0} },
 745 {"fidivr", 1,   0xde, 7, 0,      sl_FP|Modrm,           { ShortMem|LongMem, 0, 0} },
 746
 747 #if SYSV386_COMPAT
 748 {"fdivrp", 2, 0xdef8, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 749 {"fdivrp", 1, 0xdef8, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 750 {"fdivrp", 0, 0xdef9, X, 0,      FP,                    { 0, 0, 0} },
 751 #if OLDGCC_COMPAT
 752 {"fdivrp", 2, 0xdef8, X, 0,      FP|ShortForm|Ugh,      { FloatReg, FloatAcc, 0} },
 753 #endif
 754 #else
 755 {"fdivrp", 2, 0xdef0, X, 0,      FP|ShortForm,          { FloatAcc, FloatReg, 0} },
 756 {"fdivrp", 1, 0xdef0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 757 {"fdivrp", 0, 0xdef1, X, 0,      FP,                    { 0, 0, 0} },
 758 #endif
 759
 760 {"f2xm1",  0, 0xd9f0, X, 0,      FP,                    { 0, 0, 0} },
 761 {"fyl2x",  0, 0xd9f1, X, 0,      FP,                    { 0, 0, 0} },
 762 {"fptan",  0, 0xd9f2, X, 0,      FP,                    { 0, 0, 0} },
 763 {"fpatan", 0, 0xd9f3, X, 0,      FP,                    { 0, 0, 0} },
 764 {"fxtract",0, 0xd9f4, X, 0,      FP,                    { 0, 0, 0} },
 765 {"fprem1", 0, 0xd9f5, X, Cpu286, FP,                    { 0, 0, 0} },
 766 {"fdecstp",0, 0xd9f6, X, 0,      FP,                    { 0, 0, 0} },
 767 {"fincstp",0, 0xd9f7, X, 0,      FP,                    { 0, 0, 0} },
 768 {"fprem",  0, 0xd9f8, X, 0,      FP,                    { 0, 0, 0} },
 769 {"fyl2xp1",0, 0xd9f9, X, 0,      FP,                    { 0, 0, 0} },
 770 {"fsqrt",  0, 0xd9fa, X, 0,      FP,                    { 0, 0, 0} },
 771 {"fsincos",0, 0xd9fb, X, Cpu286, FP,                    { 0, 0, 0} },
 772 {"frndint",0, 0xd9fc, X, 0,      FP,                    { 0, 0, 0} },
 773 {"fscale", 0, 0xd9fd, X, 0,      FP,                    { 0, 0, 0} },
 774 {"fsin",   0, 0xd9fe, X, Cpu286, FP,                    { 0, 0, 0} },
 775 {"fcos",   0, 0xd9ff, X, Cpu286, FP,                    { 0, 0, 0} },
 776 {"fchs",   0, 0xd9e0, X, 0,      FP,                    { 0, 0, 0} },
 777 {"fabs",   0, 0xd9e1, X, 0,      FP,                    { 0, 0, 0} },
 778
 779 /* processor control */
 780 {"fninit", 0, 0xdbe3, X, 0,      FP,                    { 0, 0, 0} },
 781 {"finit",  0, 0xdbe3, X, 0,      FP|FWait,              { 0, 0, 0} },
 782 {"fldcw",  1,   0xd9, 5, 0,      w_Suf|FloatMF|Modrm,   { ShortMem, 0, 0} },
 783 {"fnstcw", 1,   0xd9, 7, 0,      w_Suf|FloatMF|Modrm,   { ShortMem, 0, 0} },
 784 {"fstcw",  1,   0xd9, 7, 0,      w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
 785 /* XXX should reject %al, %eax, and %rax */
 786 {"fnstsw", 1, 0xdfe0, X, 0,      FP|IgnoreSize,         { Acc, 0, 0} },
 787 {"fnstsw", 1,   0xdd, 7, 0,      w_Suf|FloatMF|Modrm,   { ShortMem, 0, 0} },
 788 {"fnstsw", 0, 0xdfe0, X, 0,      FP,                    { 0, 0, 0} },
 789 /* XXX should reject %al, %eax, and %rax */
 790 {"fstsw",  1, 0xdfe0, X, 0,      FP|FWait|IgnoreSize,   { Acc, 0, 0} },
 791 {"fstsw",  1,   0xdd, 7, 0,      w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
 792 {"fstsw",  0, 0xdfe0, X, 0,      FP|FWait,              { 0, 0, 0} },
 793 {"fnclex", 0, 0xdbe2, X, 0,      FP,                    { 0, 0, 0} },
 794 {"fclex",  0, 0xdbe2, X, 0,      FP|FWait,              { 0, 0, 0} },
 795 /* Short forms of fldenv, fstenv use data size prefix.  */
 796 {"fnstenv",1,   0xd9, 6, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
 797 {"fstenv", 1,   0xd9, 6, 0,      sl_Suf|FWait|Modrm|DefaultSize,        { LLongMem, 0, 0} },
 798 {"fldenv", 1,   0xd9, 4, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
 799 {"fnsave", 1,   0xdd, 6, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
 800 {"fsave",  1,   0xdd, 6, 0,      sl_Suf|FWait|Modrm|DefaultSize,        { LLongMem, 0, 0} },
 801 {"frstor", 1,   0xdd, 4, 0,      sl_Suf|Modrm|DefaultSize,              { LLongMem, 0, 0} },
 802
 803 {"ffree",  1, 0xddc0, X, 0,      FP|ShortForm,          { FloatReg, 0, 0} },
 804 /* P6:free st(i), pop st */
 805 {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm,          { FloatReg, 0, 0} },
 806 {"fnop",   0, 0xd9d0, X, 0,      FP,                    { 0, 0, 0} },
 807 {"fwait",  0,   0x9b, X, 0,      FP,                    { 0, 0, 0} },
 808
 809 /* Opcode prefixes; we allow them as separate insns too.  */
 810
 811 {"addr16", 0,   0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize,      { 0, 0, 0} },
 812 {"addr32", 0,   0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
 813 {"aword",  0,   0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
 814 {"adword", 0,   0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
 815 {"data16", 0,   0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
 816 {"data32", 0,   0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
 817 {"word",   0,   0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
 818 {"dword",  0,   0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
 819 {"lock",   0,   0xf0, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 820 {"wait",   0,   0x9b, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 821 {"cs",     0,   0x2e, X, 0,     NoSuf|IsPrefix, { 0, 0, 0} },
 822 {"ds",     0,   0x3e, X, 0,     NoSuf|IsPrefix, { 0, 0, 0} },
 823 {"es",     0,   0x26, X, CpuNo64,       NoSuf|IsPrefix, { 0, 0, 0} },
 824 {"fs",     0,   0x64, X, Cpu386, NoSuf|IsPrefix,        { 0, 0, 0} },
 825 {"gs",     0,   0x65, X, Cpu386, NoSuf|IsPrefix,        { 0, 0, 0} },
 826 {"ss",     0,   0x36, X, CpuNo64,       NoSuf|IsPrefix, { 0, 0, 0} },
 827 {"rep",    0,   0xf3, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 828 {"repe",   0,   0xf3, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 829 {"repz",   0,   0xf3, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 830 {"repne",  0,   0xf2, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 831 {"repnz",  0,   0xf2, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 832 {"ht",     0,   0x3e, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 833 {"hnt",    0,   0x2e, X, 0,      NoSuf|IsPrefix,        { 0, 0, 0} },
 834 {"rex",    0,   0x40, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 835 {"rexz",   0,   0x41, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 836 {"rexy",   0,   0x42, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 837 {"rexyz",  0,   0x43, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 838 {"rexx",   0,   0x44, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 839 {"rexxz",  0,   0x45, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 840 {"rexxy",  0,   0x46, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 841 {"rexxyz", 0,   0x47, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 842 {"rex64",  0,   0x48, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 843 {"rex64z", 0,   0x49, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 844 {"rex64y", 0,   0x4a, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 845 {"rex64yz",0,   0x4b, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 846 {"rex64x", 0,   0x4c, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 847 {"rex64xz",0,   0x4d, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 848 {"rex64xy",0,   0x4e, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 849 {"rex64xyz",0,  0x4f, X, Cpu64,  NoSuf|IsPrefix,        { 0, 0, 0} },
 850
 851 /* 486 extensions.  */
 852
 853 {"bswap",   1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm,     { Reg32|Reg64, 0, 0 } },
 854 {"xadd",    2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm,     { Reg, Reg|AnyMem, 0 } },
 855 {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm,     { Reg, Reg|AnyMem, 0 } },
 856 {"invd",    0, 0x0f08, X, Cpu486, NoSuf,                { 0, 0, 0} },
 857 {"wbinvd",  0, 0x0f09, X, Cpu486, NoSuf,                { 0, 0, 0} },
 858 {"invlpg",  1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} },
 859
 860 /* 586 and late 486 extensions.  */
 861 {"cpuid",   0, 0x0fa2, X, Cpu486, NoSuf,                { 0, 0, 0} },
 862
 863 /* Pentium extensions.  */
 864 {"wrmsr",   0, 0x0f30, X, Cpu586, NoSuf,                { 0, 0, 0} },
 865 {"rdtsc",   0, 0x0f31, X, Cpu586, NoSuf,                { 0, 0, 0} },
 866 {"rdmsr",   0, 0x0f32, X, Cpu586, NoSuf,                { 0, 0, 0} },
 867 {"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm,          { LLongMem, 0, 0} },
 868
 869 /* Pentium II/Pentium Pro extensions.  */
 870 {"sysenter",0, 0x0f34, X, Cpu686, NoSuf,                { 0, 0, 0} },
 871 {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf,                { 0, 0, 0} },
 872 {"fxsave",  1, 0x0fae, 0, Cpu686, q_Suf|Modrm,          { LLongMem, 0, 0} },
 873 {"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm,          { LLongMem, 0, 0} },
 874 {"rdpmc",   0, 0x0f33, X, Cpu686, NoSuf,                { 0, 0, 0} },
 875 /* official undefined instr. */
 876 {"ud2",     0, 0x0f0b, X, Cpu686, NoSuf,                { 0, 0, 0} },
 877 /* alias for ud2 */
 878 {"ud2a",    0, 0x0f0b, X, Cpu686, NoSuf,                { 0, 0, 0} },
 879 /* 2nd. official undefined instr. */
 880 {"ud2b",    0, 0x0fb9, X, Cpu686, NoSuf,                { 0, 0, 0} },
 881
 882 {"cmovo",   2, 0x0f40, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 883 {"cmovno",  2, 0x0f41, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 884 {"cmovb",   2, 0x0f42, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 885 {"cmovc",   2, 0x0f42, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 886 {"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 887 {"cmovae",  2, 0x0f43, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 888 {"cmovnc",  2, 0x0f43, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 889 {"cmovnb",  2, 0x0f43, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 890 {"cmove",   2, 0x0f44, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 891 {"cmovz",   2, 0x0f44, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 892 {"cmovne",  2, 0x0f45, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 893 {"cmovnz",  2, 0x0f45, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 894 {"cmovbe",  2, 0x0f46, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 895 {"cmovna",  2, 0x0f46, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 896 {"cmova",   2, 0x0f47, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 897 {"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 898 {"cmovs",   2, 0x0f48, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 899 {"cmovns",  2, 0x0f49, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 900 {"cmovp",   2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 901 {"cmovnp",  2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 902 {"cmovl",   2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 903 {"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 904 {"cmovge",  2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 905 {"cmovnl",  2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 906 {"cmovle",  2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 907 {"cmovng",  2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 908 {"cmovg",   2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 909 {"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm,        { WordReg|WordMem, WordReg, 0} },
 910
 911 {"fcmovb",  2, 0xdac0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 912 {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 913 {"fcmove",  2, 0xdac8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 914 {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 915 {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 916 {"fcmovu",  2, 0xdad8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 917 {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 918 {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 919 {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 920 {"fcmova",  2, 0xdbd0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 921 {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 922 {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 923
 924 {"fcomi",   2, 0xdbf0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 925 {"fcomi",   0, 0xdbf1, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
 926 {"fcomi",   1, 0xdbf0, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
 927 {"fucomi",  2, 0xdbe8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 928 {"fucomi",  0, 0xdbe9, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
 929 {"fucomi",  1, 0xdbe8, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
 930 {"fcomip",  2, 0xdff0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 931 {"fcompi",  2, 0xdff0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 932 {"fcompi",  0, 0xdff1, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
 933 {"fcompi",  1, 0xdff0, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
 934 {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 935 {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
 936 {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
 937 {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
 938
 939 /* Pentium4 extensions.  */
 940
 941 {"movnti",   2, 0x0fc3,    X, CpuP4, wlq_Suf|Modrm,             { WordReg, WordMem, 0 } },
 942 {"clflush",  1, 0x0fae,    7, CpuP4, NoSuf|Modrm|IgnoreSize,    { ByteMem, 0, 0 } },
 943 {"lfence",   0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt,              { 0, 0, 0 } },
 944 {"mfence",   0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt,              { 0, 0, 0 } },
 945 {"pause",    0, 0xf390,    X, CpuP4, NoSuf,             { 0, 0, 0 } },
 946
 947 /* MMX/SSE2 instructions.  */
 948
 949 {"emms",     0, 0x0f77, X, CpuMMX, NoSuf,                       { 0, 0, 0 } },
 950 /* These really shouldn't allow for Reg64 (movq is the right mnemonic for
 951    copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's
 952    spec). AMD's spec, having been in existence for much longer, failed to
 953    recognize that and specified movd for 32- and 64-bit operations.  */
 954 {"movd",     2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } },
 955 {"movd",     2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } },
 956 {"movd",     2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegXMM, 0 } },
 957 {"movd",     2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LongMem, 0 } },
 958 /* In the 64bit mode the short form mov immediate is redefined to have
 959    64bit displacement value.  */
 960 {"movq",     2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX|LLongMem, RegMMX, 0 } },
 961 {"movq",     2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX, RegMMX|LLongMem, 0 } },
 962 {"movq",     2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } },
 963 {"movq",     2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } },
 964 {"movq",     2, 0x0f6e, X, Cpu64,       NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegMMX, 0 } },
 965 {"movq",     2, 0x0f7e, X, Cpu64,       NoSuf|IgnoreSize|Modrm, { RegMMX, Reg64|LLongMem, 0 } },
 966 {"movq",     2, 0x660f6e,X,Cpu64,       NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegXMM, 0 } },
 967 {"movq",     2, 0x660f7e,X,Cpu64,       NoSuf|IgnoreSize|Modrm, { RegXMM, Reg64|LLongMem, 0 } },
 968 /* We put the 64bit displacement first and we only mark constants
 969    larger than 32bit as Disp64.  */
 970 {"movq",   2,   0xa0, X, Cpu64,  NoSuf|D|W|Size64, { Disp64, Acc, 0 } },
 971 {"movq",   2,   0x88, X, Cpu64,  NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
 972 {"movq",   2,   0xc6, 0, Cpu64,  NoSuf|W|Modrm|Size64,  { Imm32S, Reg64|WordMem, 0 } },
 973 {"movq",   2,   0xb0, X, Cpu64,  NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
 974 /* The segment register moves accept Reg64 so that a segment register
 975    can be copied to a 64 bit register, and vice versa.  */
 976 {"movq",   2,   0x8c, X, Cpu64,  NoSuf|Modrm|Size64,    { SReg2|SReg3, Reg64|InvMem, 0 } },
 977 {"movq",   2,   0x8e, X, Cpu64,  NoSuf|Modrm|Size64,    { Reg64, SReg2|SReg3, 0 } },
 978 /* Move to/from control debug registers.  In the 16 or 32bit modes they are 32bit.  In the 64bit
 979    mode they are 64bit.*/
 980 {"movq",   2, 0x0f20, X, Cpu64,  NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
 981 {"movq",   2, 0x0f21, X, Cpu64,  NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
 982 /* Real MMX instructions.  */
 983 {"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
 984 {"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 985 {"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
 986 {"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 987 {"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
 988 {"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 989 {"paddb",    2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
 990 {"paddb",    2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 991 {"paddw",    2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
 992 {"paddw",    2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 993 {"paddd",    2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
 994 {"paddd",    2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 995 {"paddq",    2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegMMX|LLongMem, RegMMX, 0 } },
 996 {"paddq",    2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 997 {"paddsb",   2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
 998 {"paddsb",   2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
 999 {"paddsw",   2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1000 {"paddsw",   2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1001 {"paddusb",  2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1002 {"paddusb",  2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1003 {"paddusw",  2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1004 {"paddusw",  2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1005 {"pand",     2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1006 {"pand",     2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1007 {"pandn",    2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1008 {"pandn",    2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1009 {"pcmpeqb",  2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1010 {"pcmpeqb",  2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1011 {"pcmpeqw",  2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1012 {"pcmpeqw",  2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1013 {"pcmpeqd",  2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1014 {"pcmpeqd",  2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1015 {"pcmpgtb",  2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1016 {"pcmpgtb",  2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1017 {"pcmpgtw",  2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1018 {"pcmpgtw",  2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1019 {"pcmpgtd",  2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1020 {"pcmpgtd",  2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1021 {"pmaddwd",  2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1022 {"pmaddwd",  2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1023 {"pmulhw",   2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1024 {"pmulhw",   2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1025 {"pmullw",   2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1026 {"pmullw",   2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1027 {"por",      2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1028 {"por",      2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1029 {"psllw",    2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1030 {"psllw",    2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1031 {"psllw",    2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1032 {"psllw",    2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1033 {"pslld",    2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1034 {"pslld",    2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1035 {"pslld",    2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1036 {"pslld",    2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1037 {"psllq",    2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1038 {"psllq",    2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1039 {"psllq",    2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1040 {"psllq",    2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1041 {"psraw",    2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1042 {"psraw",    2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1043 {"psraw",    2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1044 {"psraw",    2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1045 {"psrad",    2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1046 {"psrad",    2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1047 {"psrad",    2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1048 {"psrad",    2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1049 {"psrlw",    2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1050 {"psrlw",    2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1051 {"psrlw",    2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1052 {"psrlw",    2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1053 {"psrld",    2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1054 {"psrld",    2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1055 {"psrld",    2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1056 {"psrld",    2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1057 {"psrlq",    2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1058 {"psrlq",    2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1059 {"psrlq",    2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,              { Imm8, RegMMX, 0 } },
1060 {"psrlq",    2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { Imm8, RegXMM, 0 } },
1061 {"psubb",    2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1062 {"psubb",    2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1063 {"psubw",    2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1064 {"psubw",    2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1065 {"psubd",    2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1066 {"psubd",    2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1067 {"psubq",    2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegMMX|LLongMem, RegMMX, 0 } },
1068 {"psubq",    2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1069 {"psubsb",   2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1070 {"psubsb",   2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1071 {"psubsw",   2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1072 {"psubsw",   2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1073 {"psubusb",  2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1074 {"psubusb",  2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1075 {"psubusw",  2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1076 {"psubusw",  2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1077 {"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1078 {"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1079 {"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1080 {"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1081 {"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1082 {"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1083 {"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1084 {"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1085 {"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1086 {"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1087 {"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1088 {"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1089 {"pxor",     2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm,              { RegMMX|LongMem, RegMMX, 0 } },
1090 {"pxor",     2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,              { RegXMM|LLongMem, RegXMM, 0 } },
1091
1092 /* PIII Katmai New Instructions / SIMD instructions.  */
1093
1094 {"addps",     2, 0x0f58,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1095 {"addss",     2, 0xf30f58,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1096 {"andnps",    2, 0x0f55,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1097 {"andps",     2, 0x0f54,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1098 {"cmpeqps",   2, 0x0fc2,    0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1099 {"cmpeqss",   2, 0xf30fc2,  0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1100 {"cmpleps",   2, 0x0fc2,    2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1101 {"cmpless",   2, 0xf30fc2,  2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1102 {"cmpltps",   2, 0x0fc2,    1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1103 {"cmpltss",   2, 0xf30fc2,  1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1104 {"cmpneqps",  2, 0x0fc2,    4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1105 {"cmpneqss",  2, 0xf30fc2,  4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1106 {"cmpnleps",  2, 0x0fc2,    6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1107 {"cmpnless",  2, 0xf30fc2,  6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1108 {"cmpnltps",  2, 0x0fc2,    5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1109 {"cmpnltss",  2, 0xf30fc2,  5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1110 {"cmpordps",  2, 0x0fc2,    7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1111 {"cmpordss",  2, 0xf30fc2,  7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1112 {"cmpunordps",2, 0x0fc2,    3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|LLongMem, RegXMM, 0 } },
1113 {"cmpunordss",2, 0xf30fc2,  3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt,   { RegXMM|WordMem, RegXMM, 0 } },
1114 {"cmpps",     3, 0x0fc2,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { Imm8, RegXMM|LLongMem, RegXMM } },
1115 {"cmpss",     3, 0xf30fc2,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { Imm8, RegXMM|WordMem, RegXMM } },
1116 {"comiss",    2, 0x0f2f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1117 {"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegXMM, 0 } },
1118 {"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegMMX, 0 } },
1119 {"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
1120 {"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
1121 {"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegMMX, 0 } },
1122 {"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } },
1123 {"divps",     2, 0x0f5e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1124 {"divss",     2, 0xf30f5e,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1125 {"ldmxcsr",   1, 0x0fae,    2, CpuSSE, NoSuf|IgnoreSize|Modrm,  { WordMem, 0, 0 } },
1126 {"maskmovq",  2, 0x0ff7,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX, RegMMX, 0 } },
1127 {"maxps",     2, 0x0f5f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1128 {"maxss",     2, 0xf30f5f,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1129 {"minps",     2, 0x0f5d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1130 {"minss",     2, 0xf30f5d,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1131 {"movaps",    2, 0x0f28,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1132 {"movaps",    2, 0x0f29,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM|LLongMem, 0 } },
1133 {"movhlps",   2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM, 0 } },
1134 {"movhps",    2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { LLongMem, RegXMM, 0 } },
1135 {"movhps",    2, 0x0f17,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1136 {"movlhps",   2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM, 0 } },
1137 {"movlps",    2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { LLongMem, RegXMM, 0 } },
1138 {"movlps",    2, 0x0f13,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1139 {"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } },
1140 {"movntps",   2, 0x0f2b,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1141 {"movntq",    2, 0x0fe7,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX, LLongMem, 0 } },
1142 {"movntdq",   2, 0x660fe7,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM, LLongMem, 0 } },
1143 {"movss",     2, 0xf30f10,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1144 {"movss",     2, 0xf30f11,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM|WordMem, 0 } },
1145 {"movups",    2, 0x0f10,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1146 {"movups",    2, 0x0f11,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM, RegXMM|LLongMem, 0 } },
1147 {"mulps",     2, 0x0f59,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1148 {"mulss",     2, 0xf30f59,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1149 {"orps",      2, 0x0f56,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1150 {"pavgb",     2, 0x0fe0,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1151 {"pavgb",     2, 0x660fe0,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1152 {"pavgw",     2, 0x0fe3,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1153 {"pavgw",     2, 0x660fe3,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1154 {"pextrw",    3, 0x0fc5,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX, Reg32|Reg64 } },
1155 {"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64 } },
1156 {"pinsrw",    3, 0x0fc4,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
1157 {"pinsrw",    3, 0x660fc4,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
1158 {"pmaxsw",    2, 0x0fee,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1159 {"pmaxsw",    2, 0x660fee,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1160 {"pmaxub",    2, 0x0fde,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1161 {"pmaxub",    2, 0x660fde,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1162 {"pminsw",    2, 0x0fea,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1163 {"pminsw",    2, 0x660fea,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1164 {"pminub",    2, 0x0fda,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1165 {"pminub",    2, 0x660fda,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1166 {"pmovmskb",  2, 0x0fd7,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64, 0 } },
1167 {"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } },
1168 {"pmulhuw",   2, 0x0fe4,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1169 {"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1170 {"prefetchnta", 1, 0x0f18,  0, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1171 {"prefetcht0",  1, 0x0f18,  1, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1172 {"prefetcht1",  1, 0x0f18,  2, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1173 {"prefetcht2",  1, 0x0f18,  3, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { LLongMem, 0, 0 } },
1174 {"psadbw",    2, 0x0ff6,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { RegMMX|LLongMem, RegMMX, 0 } },
1175 {"psadbw",    2, 0x660ff6,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1176 {"pshufw",    3, 0x0f70,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,  { Imm8, RegMMX|LLongMem, RegMMX } },
1177 {"rcpps",     2, 0x0f53,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1178 {"rcpss",     2, 0xf30f53,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1179 {"rsqrtps",   2, 0x0f52,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1180 {"rsqrtss",   2, 0xf30f52,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1181 {"sfence",    0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } },
1182 {"shufps",    3, 0x0fc6,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { Imm8, RegXMM|LLongMem, RegXMM } },
1183 {"sqrtps",    2, 0x0f51,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1184 {"sqrtss",    2, 0xf30f51,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1185 {"stmxcsr",   1, 0x0fae,    3, CpuSSE, NoSuf|IgnoreSize|Modrm,  { WordMem, 0, 0 } },
1186 {"subps",     2, 0x0f5c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1187 {"subss",     2, 0xf30f5c,  X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1188 {"ucomiss",   2, 0x0f2e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|WordMem, RegXMM, 0 } },
1189 {"unpckhps",  2, 0x0f15,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1190 {"unpcklps",  2, 0x0f14,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1191 {"xorps",     2, 0x0f57,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,  { RegXMM|LLongMem, RegXMM, 0 } },
1192
1193 /* SSE-2 instructions.  */
1194
1195 {"addpd",     2, 0x660f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1196 {"addsd",     2, 0xf20f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1197 {"andnpd",    2, 0x660f55,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1198 {"andpd",     2, 0x660f54,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1199 {"cmpeqpd",   2, 0x660fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1200 {"cmpeqsd",   2, 0xf20fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1201 {"cmplepd",   2, 0x660fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1202 {"cmplesd",   2, 0xf20fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1203 {"cmpltpd",   2, 0x660fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1204 {"cmpltsd",   2, 0xf20fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1205 {"cmpneqpd",  2, 0x660fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1206 {"cmpneqsd",  2, 0xf20fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1207 {"cmpnlepd",  2, 0x660fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1208 {"cmpnlesd",  2, 0xf20fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1209 {"cmpnltpd",  2, 0x660fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1210 {"cmpnltsd",  2, 0xf20fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1211 {"cmpordpd",  2, 0x660fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1212 {"cmpordsd",  2, 0xf20fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1213 {"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1214 {"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1215 {"cmppd",     3, 0x660fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1216 /* Intel mode string compare.  */
1217 {"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1218 {"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
1219 {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
1220 {"comisd",    2, 0x660f2f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1221 {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
1222 {"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
1223 {"divpd",     2, 0x660f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1224 {"divsd",     2, 0xf20f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1225 {"maxpd",     2, 0x660f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1226 {"maxsd",     2, 0xf20f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1227 {"minpd",     2, 0x660f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1228 {"minsd",     2, 0xf20f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1229 {"movapd",    2, 0x660f28,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1230 {"movapd",    2, 0x660f29,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1231 {"movhpd",    2, 0x660f16,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1232 {"movhpd",    2, 0x660f17,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
1233 {"movlpd",    2, 0x660f12,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1234 {"movlpd",    2, 0x660f13,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
1235 {"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } },
1236 {"movntpd",   2, 0x660f2b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,         { RegXMM, LLongMem, 0 } },
1237 /* Intel mode string move.  */
1238 {"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1239 {"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
1240 {"movsd",     2, 0xf20f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1241 {"movsd",     2, 0xf20f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
1242 {"movupd",    2, 0x660f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1243 {"movupd",    2, 0x660f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1244 {"mulpd",     2, 0x660f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1245 {"mulsd",     2, 0xf20f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1246 {"orpd",      2, 0x660f56,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1247 {"shufpd",    3, 0x660fc6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1248 {"sqrtpd",    2, 0x660f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1249 {"sqrtsd",    2, 0xf20f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1250 {"subpd",     2, 0x660f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1251 {"subsd",     2, 0xf20f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1252 {"ucomisd",   2, 0x660f2e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1253 {"unpckhpd",  2, 0x660f15,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1254 {"unpcklpd",  2, 0x660f14,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1255 {"xorpd",     2, 0x660f57,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1256 {"cvtdq2pd",  2, 0xf30fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1257 {"cvtpd2dq",  2, 0xf20fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1258 {"cvtdq2ps",  2, 0x0f5b,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1259 {"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1260 {"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1261 {"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1262 {"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1263 {"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
1264 {"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1265 {"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1266 {"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1267 {"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
1268 {"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1269 {"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1270 {"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } },
1271 {"movdqa",    2, 0x660f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1272 {"movdqa",    2, 0x660f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1273 {"movdqu",    2, 0xf30f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1274 {"movdqu",    2, 0xf30f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1275 {"movdq2q",    2, 0xf20fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,        { RegXMM, RegMMX, 0 } },
1276 {"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX, RegXMM, 0 } },
1277 {"pmuludq",   2, 0x0ff4,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1278 {"pmuludq",   2, 0x660ff4,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1279 {"pshufd",    3, 0x660f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1280 {"pshufhw",   3, 0xf30f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1281 {"pshuflw",   3, 0xf20f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1282 {"pslldq",    2, 0x660f73,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1283 {"psrldq",    2, 0x660f73,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } },
1284 {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1285 {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1286
1287 /* SSE-3 instructions.  */
1288
1289 {"addsubpd",  2, 0x660fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1290 {"addsubps",  2, 0xf20fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1291 {"cmpxchg16b",1, 0x0fc7,    1, CpuSSE3|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
1292 {"fisttp",    1, 0xdf,      1, CpuSSE3, sl_FP|Modrm,    { ShortMem|LongMem, 0, 0} },
1293 {"fisttp",    1, 0xdd,      1, CpuSSE3, q_FP|Modrm,     { LLongMem, 0, 0} },
1294 {"fisttpll",  1, 0xdd,      1, CpuSSE3, FP|Modrm,       { LLongMem, 0, 0} },
1295 {"haddpd",    2, 0x660f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1296 {"haddps",    2, 0xf20f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1297 {"hsubpd",    2, 0x660f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1298 {"hsubps",    2, 0xf20f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1299 {"lddqu",     2, 0xf20ff0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
1300 {"monitor",   0, 0x0f01, 0xc8, CpuSSE3, NoSuf|ImmExt,   { 0, 0, 0} },
1301 /* monitor is very special. CX and DX are always 64bits with zero upper
1302    32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The
1303    address size override prefix can be used to overrride the AX size in
1304    all modes.  */
1305 /* Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. */
1306 {"monitor",   3, 0x0f01, 0xc8, CpuSSE3|CpuNo64, NoSuf|ImmExt,   { Reg16|Reg32, Reg32, Reg32 } },
1307 /* Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. */
1308 {"monitor",   3, 0x0f01, 0xc8, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,     { Reg32|Reg64, Reg64, Reg64 } },
1309 {"movddup",   2, 0xf20f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1310 {"movshdup",  2, 0xf30f16,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1311 {"movsldup",  2, 0xf30f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1312 {"mwait",     0, 0x0f01, 0xc9, CpuSSE3, NoSuf|ImmExt,   { 0, 0, 0} },
1313 /* mwait is very special. AX and CX are always 64bits with zero upper
1314    32bits in 64bit mode, and 32bits in 16bit and 32bit modes.  */
1315 /* Need to ensure only "mwait %eax,%ecx" is accepted.  */
1316 {"mwait",     2, 0x0f01, 0xc9, CpuSSE3|CpuNo64, NoSuf|ImmExt,   { Reg32, Reg32, 0} },
1317 /* Need to ensure only "mwait %rax,%rcx" is accepted.  */
1318 {"mwait",     2, 0x0f01, 0xc9, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,     { Reg64, Reg64, 0} },
1319
1320 /* VMX instructions.  */
1321 {"vmcall",    0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
1322 {"vmclear",   1, 0x660fc7,  6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,  { LLongMem, 0, 0} },
1323 {"vmlaunch",  0, 0x0f01, 0xc2, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
1324 {"vmresume",  0, 0x0f01, 0xc3, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
1325 {"vmptrld",   1, 0x0fc7,    6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,  { LLongMem, 0, 0} },
1326 {"vmptrst",   1, 0x0fc7,    7, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,  { LLongMem, 0, 0} },
1327 {"vmread",    2, 0x0f78,    X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32, Reg32|LongMem, 0} },
1328 {"vmread",    2, 0x0f78,    X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64, Reg64|LLongMem, 0} },
1329 {"vmwrite",   2, 0x0f79,    X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32|LongMem, Reg32, 0} },
1330 {"vmwrite",   2, 0x0f79,    X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64|LLongMem, Reg64, 0} },
1331 {"vmxoff",    0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
1332 {"vmxon",     1, 0xf30fc7,  6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,  { LLongMem, 0, 0} },
1333
1334 /* Supplemental Streaming SIMD extensions 3 Instructions.  */
1335
1336 {"phaddw",    2,   0x0f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1337 {"phaddw",    2, 0x660f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1338 {"phaddd",    2,   0x0f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1339 {"phaddd",    2, 0x660f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1340 {"phaddsw",   2,   0x0f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1341 {"phaddsw",   2, 0x660f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1342 {"phsubw",    2,   0x0f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1343 {"phsubw",    2, 0x660f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1344 {"phsubd",    2,   0x0f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1345 {"phsubd",    2, 0x660f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1346 {"phsubsw",   2,   0x0f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1347 {"phsubsw",   2, 0x660f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1348 {"pmaddubsw", 2,   0x0f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1349 {"pmaddubsw", 2, 0x660f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1350 {"pmulhrsw", 2,    0x0f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1351 {"pmulhrsw", 2,  0x660f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1352 {"pshufb",   2,    0x0f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1353 {"pshufb",   2,  0x660f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1354 {"psignb",   2,    0x0f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1355 {"psignb",   2,  0x660f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1356 {"psignw",   2,    0x0f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1357 {"psignw",   2,  0x660f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1358 {"psignd",   2,    0x0f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1359 {"psignd",   2,  0x660f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1360 {"palignr",  3,    0x0f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { Imm8, RegMMX|LongMem, RegMMX } },
1361 {"palignr",  3,  0x660f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { Imm8, RegXMM|LLongMem, RegXMM } },
1362 {"pabsb",    2,    0x0f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1363 {"pabsb",    2,  0x660f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1364 {"pabsw",    2,    0x0f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1365 {"pabsw",    2,  0x660f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1366 {"pabsd",    2,    0x0f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegMMX|LongMem, RegMMX, 0 } },
1367 {"pabsd",    2,  0x660f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
1368
1369 /* AMD 3DNow! instructions.  */
1370
1371 {"prefetch", 1, 0x0f0d,    0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
1372 {"prefetchw",1, 0x0f0d,    1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
1373 {"femms",    0, 0x0f0e,    X, Cpu3dnow, NoSuf,                  { 0, 0, 0 } },
1374 {"pavgusb",  2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1375 {"pf2id",    2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1376 {"pf2iw",    2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1377 {"pfacc",    2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1378 {"pfadd",    2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1379 {"pfcmpeq",  2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1380 {"pfcmpge",  2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1381 {"pfcmpgt",  2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1382 {"pfmax",    2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1383 {"pfmin",    2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1384 {"pfmul",    2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1385 {"pfnacc",   2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1386 {"pfpnacc",  2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1387 {"pfrcp",    2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1388 {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1389 {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1390 {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1391 {"pfrsqrt",  2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1392 {"pfsub",    2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1393 {"pfsubr",   2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1394 {"pi2fd",    2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1395 {"pi2fw",    2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1396 {"pmulhrw",  2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1397 {"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,  { RegMMX|LongMem, RegMMX, 0 } },
1398
1399 /* AMD extensions. */
1400 {"syscall",  0, 0x0f05,    X, CpuK6,    NoSuf,                  { 0, 0, 0} },
1401 {"sysret",   0, 0x0f07,    X, CpuK6,    lq_Suf|DefaultSize,     { 0, 0, 0} },
1402 {"swapgs",   0, 0x0f01, 0xf8, Cpu64,    NoSuf|ImmExt,           { 0, 0, 0} },
1403 {"rdtscp",   0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt,     { 0, 0, 0} },
1404
1405 /* AMD Pacifica additions.  */
1406 {"clgi",     0, 0x0f01, 0xdd, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1407 {"invlpga",  0, 0x0f01, 0xdf, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1408 /* Need to ensure only "invlpga ...,%ecx" is accepted.  */
1409 {"invlpga",  2, 0x0f01, 0xdf, CpuSVME,  NoSuf|ImmExt,           { AnyMem, Reg32, 0 } },
1410 {"skinit",   0, 0x0f01, 0xde, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1411 {"skinit",   1, 0x0f01, 0xde, CpuSVME,  NoSuf|ImmExt,           { AnyMem, 0, 0 } },
1412 {"stgi",     0, 0x0f01, 0xdc, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1413 {"vmload",   0, 0x0f01, 0xda, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1414 {"vmload",   1, 0x0f01, 0xda, CpuSVME,  NoSuf|ImmExt,           { AnyMem, 0, 0 } },
1415 {"vmmcall",  0, 0x0f01, 0xd9, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1416 {"vmrun",    0, 0x0f01, 0xd8, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1417 {"vmrun",    1, 0x0f01, 0xd8, CpuSVME,  NoSuf|ImmExt,           { AnyMem, 0, 0 } },
1418 {"vmsave",   0, 0x0f01, 0xdb, CpuSVME,  NoSuf|ImmExt,           { 0, 0, 0 } },
1419 {"vmsave",   1, 0x0f01, 0xdb, CpuSVME,  NoSuf|ImmExt,           { AnyMem, 0, 0 } },
1420
1421
1422 /* SSE4a instructions */
1423 {"movntsd",  2, 0xf20f2b,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, LongMem, 0 } },
1424 {"movntss",  2, 0xf30f2b,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, WordMem, 0 } },
1425 {"extrq",    3, 0x660f78,  0, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { Imm8, Imm8, RegXMM } },
1426 {"extrq",    2, 0x660f79,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM} },
1427 {"insertq",  2, 0xf20f79,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM} },
1428 {"insertq",  4, 0xf20f78,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { Imm8, Imm8, RegXMM, RegXMM} },
1429
1430 /* ABM instructions */
1431 {"popcnt",   2, 0xf30fb8,  X, CpuABM, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
1432 {"lzcnt",    2, 0xf30fbd,  X, CpuABM, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
1433
1434
1435 /* VIA PadLock extensions.  */
1436 {"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1437 {"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1438 {"xcrypt-cbc",0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1439 {"xcrypt-ctr",0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1440 {"xcrypt-cfb",0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1441 {"xcrypt-ofb",0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1442 {"montmul",   0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1443 {"xsha1",     0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1444 {"xsha256",   0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1445 /* Aliases without hyphens.  */
1446 {"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1447 {"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1448 {"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1449 {"xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1450 {"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1451 {"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1452 /* Alias for xstore-rng.  */
1453 {"xstore",    0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
1454
1455 /* sentinel */
1456 {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
1457 };
1458
1459 /* 386 register table.  */
1460
1461 const reg_entry i386_regtab[] =
1462 {
1463   /* Make %st first as we test for it.  */
1464   {"st", FloatReg|FloatAcc, 0, 0},
1465   /* 8 bit regs */
1466   {"al", Reg8|Acc, 0, 0},
1467   {"cl", Reg8|ShiftCount, 0, 1},
1468   {"dl", Reg8, 0, 2},
1469   {"bl", Reg8, 0, 3},
1470   {"ah", Reg8, 0, 4},
1471   {"ch", Reg8, 0, 5},
1472   {"dh", Reg8, 0, 6},
1473   {"bh", Reg8, 0, 7},
1474   {"axl", Reg8|Acc, RegRex64, 0},  /* Must be in the "al + 8" slot.  */
1475   {"cxl", Reg8, RegRex64, 1},
1476   {"dxl", Reg8, RegRex64, 2},
1477   {"bxl", Reg8, RegRex64, 3},
1478   {"spl", Reg8, RegRex64, 4},
1479   {"bpl", Reg8, RegRex64, 5},
1480   {"sil", Reg8, RegRex64, 6},
1481   {"dil", Reg8, RegRex64, 7},
1482   {"r8b", Reg8, RegRex64|RegRex, 0},
1483   {"r9b", Reg8, RegRex64|RegRex, 1},
1484   {"r10b", Reg8, RegRex64|RegRex, 2},
1485   {"r11b", Reg8, RegRex64|RegRex, 3},
1486   {"r12b", Reg8, RegRex64|RegRex, 4},
1487   {"r13b", Reg8, RegRex64|RegRex, 5},
1488   {"r14b", Reg8, RegRex64|RegRex, 6},
1489   {"r15b", Reg8, RegRex64|RegRex, 7},
1490   /* 16 bit regs */
1491   {"ax", Reg16|Acc, 0, 0},
1492   {"cx", Reg16, 0, 1},
1493   {"dx", Reg16|InOutPortReg, 0, 2},
1494   {"bx", Reg16|BaseIndex, 0, 3},
1495   {"sp", Reg16, 0, 4},
1496   {"bp", Reg16|BaseIndex, 0, 5},
1497   {"si", Reg16|BaseIndex, 0, 6},
1498   {"di", Reg16|BaseIndex, 0, 7},
1499   {"r8w", Reg16, RegRex, 0},
1500   {"r9w", Reg16, RegRex, 1},
1501   {"r10w", Reg16, RegRex, 2},
1502   {"r11w", Reg16, RegRex, 3},
1503   {"r12w", Reg16, RegRex, 4},
1504   {"r13w", Reg16, RegRex, 5},
1505   {"r14w", Reg16, RegRex, 6},
1506   {"r15w", Reg16, RegRex, 7},
1507   /* 32 bit regs */
1508   {"eax", Reg32|BaseIndex|Acc, 0, 0},  /* Must be in ax + 16 slot.  */
1509   {"ecx", Reg32|BaseIndex, 0, 1},
1510   {"edx", Reg32|BaseIndex, 0, 2},
1511   {"ebx", Reg32|BaseIndex, 0, 3},
1512   {"esp", Reg32, 0, 4},
1513   {"ebp", Reg32|BaseIndex, 0, 5},
1514   {"esi", Reg32|BaseIndex, 0, 6},
1515   {"edi", Reg32|BaseIndex, 0, 7},
1516   {"r8d", Reg32|BaseIndex, RegRex, 0},
1517   {"r9d", Reg32|BaseIndex, RegRex, 1},
1518   {"r10d", Reg32|BaseIndex, RegRex, 2},
1519   {"r11d", Reg32|BaseIndex, RegRex, 3},
1520   {"r12d", Reg32|BaseIndex, RegRex, 4},
1521   {"r13d", Reg32|BaseIndex, RegRex, 5},
1522   {"r14d", Reg32|BaseIndex, RegRex, 6},
1523   {"r15d", Reg32|BaseIndex, RegRex, 7},
1524   {"rax", Reg64|BaseIndex|Acc, 0, 0},
1525   {"rcx", Reg64|BaseIndex, 0, 1},
1526   {"rdx", Reg64|BaseIndex, 0, 2},
1527   {"rbx", Reg64|BaseIndex, 0, 3},
1528   {"rsp", Reg64, 0, 4},
1529   {"rbp", Reg64|BaseIndex, 0, 5},
1530   {"rsi", Reg64|BaseIndex, 0, 6},
1531   {"rdi", Reg64|BaseIndex, 0, 7},
1532   {"r8", Reg64|BaseIndex, RegRex, 0},
1533   {"r9", Reg64|BaseIndex, RegRex, 1},
1534   {"r10", Reg64|BaseIndex, RegRex, 2},
1535   {"r11", Reg64|BaseIndex, RegRex, 3},
1536   {"r12", Reg64|BaseIndex, RegRex, 4},
1537   {"r13", Reg64|BaseIndex, RegRex, 5},
1538   {"r14", Reg64|BaseIndex, RegRex, 6},
1539   {"r15", Reg64|BaseIndex, RegRex, 7},
1540   /* Segment registers.  */
1541   {"es", SReg2, 0, 0},
1542   {"cs", SReg2, 0, 1},
1543   {"ss", SReg2, 0, 2},
1544   {"ds", SReg2, 0, 3},
1545   {"fs", SReg3, 0, 4},
1546   {"gs", SReg3, 0, 5},
1547   /* Control registers.  */
1548   {"cr0", Control, 0, 0},
1549   {"cr1", Control, 0, 1},
1550   {"cr2", Control, 0, 2},
1551   {"cr3", Control, 0, 3},
1552   {"cr4", Control, 0, 4},
1553   {"cr5", Control, 0, 5},
1554   {"cr6", Control, 0, 6},
1555   {"cr7", Control, 0, 7},
1556   {"cr8", Control, RegRex, 0},
1557   {"cr9", Control, RegRex, 1},
1558   {"cr10", Control, RegRex, 2},
1559   {"cr11", Control, RegRex, 3},
1560   {"cr12", Control, RegRex, 4},
1561   {"cr13", Control, RegRex, 5},
1562   {"cr14", Control, RegRex, 6},
1563   {"cr15", Control, RegRex, 7},
1564   /* Debug registers.  */
1565   {"db0", Debug, 0, 0},
1566   {"db1", Debug, 0, 1},
1567   {"db2", Debug, 0, 2},
1568   {"db3", Debug, 0, 3},
1569   {"db4", Debug, 0, 4},
1570   {"db5", Debug, 0, 5},
1571   {"db6", Debug, 0, 6},
1572   {"db7", Debug, 0, 7},
1573   {"db8", Debug, RegRex, 0},
1574   {"db9", Debug, RegRex, 1},
1575   {"db10", Debug, RegRex, 2},
1576   {"db11", Debug, RegRex, 3},
1577   {"db12", Debug, RegRex, 4},
1578   {"db13", Debug, RegRex, 5},
1579   {"db14", Debug, RegRex, 6},
1580   {"db15", Debug, RegRex, 7},
1581   {"dr0", Debug, 0, 0},
1582   {"dr1", Debug, 0, 1},
1583   {"dr2", Debug, 0, 2},
1584   {"dr3", Debug, 0, 3},
1585   {"dr4", Debug, 0, 4},
1586   {"dr5", Debug, 0, 5},
1587   {"dr6", Debug, 0, 6},
1588   {"dr7", Debug, 0, 7},
1589   {"dr8", Debug, RegRex, 0},
1590   {"dr9", Debug, RegRex, 1},
1591   {"dr10", Debug, RegRex, 2},
1592   {"dr11", Debug, RegRex, 3},
1593   {"dr12", Debug, RegRex, 4},
1594   {"dr13", Debug, RegRex, 5},
1595   {"dr14", Debug, RegRex, 6},
1596   {"dr15", Debug, RegRex, 7},
1597   /* Test registers.  */
1598   {"tr0", Test, 0, 0},
1599   {"tr1", Test, 0, 1},
1600   {"tr2", Test, 0, 2},
1601   {"tr3", Test, 0, 3},
1602   {"tr4", Test, 0, 4},
1603   {"tr5", Test, 0, 5},
1604   {"tr6", Test, 0, 6},
1605   {"tr7", Test, 0, 7},
1606   /* MMX and simd registers.  */
1607   {"mm0", RegMMX, 0, 0},
1608   {"mm1", RegMMX, 0, 1},
1609   {"mm2", RegMMX, 0, 2},
1610   {"mm3", RegMMX, 0, 3},
1611   {"mm4", RegMMX, 0, 4},
1612   {"mm5", RegMMX, 0, 5},
1613   {"mm6", RegMMX, 0, 6},
1614   {"mm7", RegMMX, 0, 7},
1615   {"xmm0", RegXMM, 0, 0},
1616   {"xmm1", RegXMM, 0, 1},
1617   {"xmm2", RegXMM, 0, 2},
1618   {"xmm3", RegXMM, 0, 3},
1619   {"xmm4", RegXMM, 0, 4},
1620   {"xmm5", RegXMM, 0, 5},
1621   {"xmm6", RegXMM, 0, 6},
1622   {"xmm7", RegXMM, 0, 7},
1623   {"xmm8", RegXMM, RegRex, 0},
1624   {"xmm9", RegXMM, RegRex, 1},
1625   {"xmm10", RegXMM, RegRex, 2},
1626   {"xmm11", RegXMM, RegRex, 3},
1627   {"xmm12", RegXMM, RegRex, 4},
1628   {"xmm13", RegXMM, RegRex, 5},
1629   {"xmm14", RegXMM, RegRex, 6},
1630   {"xmm15", RegXMM, RegRex, 7},
1631   /* No type will make this register rejected for all purposes except
1632      for addressing.  This saves creating one extra type for RIP.  */
1633   {"rip", BaseIndex, 0, 0},
1634
1635   /* sentinel */
1636   {NULL, 0, 0, 0}
1637 };
1638
1639 const reg_entry i386_float_regtab[] =
1640 {
1641   {"st(0)", FloatReg|FloatAcc, 0, 0},
1642   {"st(1)", FloatReg, 0, 1},
1643   {"st(2)", FloatReg, 0, 2},
1644   {"st(3)", FloatReg, 0, 3},
1645   {"st(4)", FloatReg, 0, 4},
1646   {"st(5)", FloatReg, 0, 5},
1647   {"st(6)", FloatReg, 0, 6},
1648   {"st(7)", FloatReg, 0, 7}
1649 };
1650
1651 /* Segment stuff.  */
1652 const seg_entry cs = { "cs", 0x2e };
1653 const seg_entry ds = { "ds", 0x3e };
1654 const seg_entry ss = { "ss", 0x36 };
1655 const seg_entry es = { "es", 0x26 };
1656 const seg_entry fs = { "fs", 0x64 };
1657 const seg_entry gs = { "gs", 0x65 };