opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* PCOMMIT instruction required */
 192   CpuPCOMMIT,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* mwaitx instruction required */
 198   CpuMWAITX,
 199   /* Clzero instruction required */
 200   CpuCLZERO,
 201   /* OSPKE instruction required */
 202   CpuOSPKE,
 203   /* RDPID instruction required */
 204   CpuRDPID,
 205   /* PTWRITE instruction required */
 206   CpuPTWRITE,
 207   /* MMX register support required */
 208   CpuRegMMX,
 209   /* XMM register support required */
 210   CpuRegXMM,
 211   /* YMM register support required */
 212   CpuRegYMM,
 213   /* ZMM register support required */
 214   CpuRegZMM,
 215   /* Mask register support required */
 216   CpuRegMask,
 217   /* 64bit support required  */
 218   Cpu64,
 219   /* Not supported in the 64bit mode  */
 220   CpuNo64,
 221   /* The last bitfield in i386_cpu_flags.  */
 222   CpuMax = CpuNo64
 223 };
 224
 225 #define CpuNumOfUints \
 226   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 227 #define CpuNumOfBits \
 228   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 229
 230 /* If you get a compiler error for zero width of the unused field,
 231    comment it out.  */
 232 #define CpuUnused       (CpuMax + 1)
 233
 234 /* We can check if an instruction is available with array instead
 235    of bitfield. */
 236 typedef union i386_cpu_flags
 237 {
 238   struct
 239     {
 240       unsigned int cpui186:1;
 241       unsigned int cpui286:1;
 242       unsigned int cpui386:1;
 243       unsigned int cpui486:1;
 244       unsigned int cpui586:1;
 245       unsigned int cpui686:1;
 246       unsigned int cpuclflush:1;
 247       unsigned int cpunop:1;
 248       unsigned int cpusyscall:1;
 249       unsigned int cpu8087:1;
 250       unsigned int cpu287:1;
 251       unsigned int cpu387:1;
 252       unsigned int cpu687:1;
 253       unsigned int cpufisttp:1;
 254       unsigned int cpummx:1;
 255       unsigned int cpusse:1;
 256       unsigned int cpusse2:1;
 257       unsigned int cpua3dnow:1;
 258       unsigned int cpua3dnowa:1;
 259       unsigned int cpusse3:1;
 260       unsigned int cpupadlock:1;
 261       unsigned int cpusvme:1;
 262       unsigned int cpuvmx:1;
 263       unsigned int cpusmx:1;
 264       unsigned int cpussse3:1;
 265       unsigned int cpusse4a:1;
 266       unsigned int cpuabm:1;
 267       unsigned int cpusse4_1:1;
 268       unsigned int cpusse4_2:1;
 269       unsigned int cpuavx:1;
 270       unsigned int cpuavx2:1;
 271       unsigned int cpuavx512f:1;
 272       unsigned int cpuavx512cd:1;
 273       unsigned int cpuavx512er:1;
 274       unsigned int cpuavx512pf:1;
 275       unsigned int cpuavx512vl:1;
 276       unsigned int cpuavx512dq:1;
 277       unsigned int cpuavx512bw:1;
 278       unsigned int cpul1om:1;
 279       unsigned int cpuk1om:1;
 280       unsigned int cpuiamcu:1;
 281       unsigned int cpuxsave:1;
 282       unsigned int cpuxsaveopt:1;
 283       unsigned int cpuaes:1;
 284       unsigned int cpupclmul:1;
 285       unsigned int cpufma:1;
 286       unsigned int cpufma4:1;
 287       unsigned int cpuxop:1;
 288       unsigned int cpulwp:1;
 289       unsigned int cpubmi:1;
 290       unsigned int cputbm:1;
 291       unsigned int cpumovbe:1;
 292       unsigned int cpucx16:1;
 293       unsigned int cpuept:1;
 294       unsigned int cpurdtscp:1;
 295       unsigned int cpufsgsbase:1;
 296       unsigned int cpurdrnd:1;
 297       unsigned int cpuf16c:1;
 298       unsigned int cpubmi2:1;
 299       unsigned int cpulzcnt:1;
 300       unsigned int cpuhle:1;
 301       unsigned int cpurtm:1;
 302       unsigned int cpuinvpcid:1;
 303       unsigned int cpuvmfunc:1;
 304       unsigned int cpumpx:1;
 305       unsigned int cpulm:1;
 306       unsigned int cpurdseed:1;
 307       unsigned int cpuadx:1;
 308       unsigned int cpuprfchw:1;
 309       unsigned int cpusmap:1;
 310       unsigned int cpusha:1;
 311       unsigned int cpuvrex:1;
 312       unsigned int cpuclflushopt:1;
 313       unsigned int cpuxsaves:1;
 314       unsigned int cpuxsavec:1;
 315       unsigned int cpuprefetchwt1:1;
 316       unsigned int cpuse1:1;
 317       unsigned int cpuclwb:1;
 318       unsigned int cpupcommit:1;
 319       unsigned int cpuavx512ifma:1;
 320       unsigned int cpuavx512vbmi:1;
 321       unsigned int cpumwaitx:1;
 322       unsigned int cpuclzero:1;
 323       unsigned int cpuospke:1;
 324       unsigned int cpurdpid:1;
 325       unsigned int cpuptwrite:1;
 326       unsigned int cpuregmmx:1;
 327       unsigned int cpuregxmm:1;
 328       unsigned int cpuregymm:1;
 329       unsigned int cpuregzmm:1;
 330       unsigned int cpuregmask:1;
 331       unsigned int cpu64:1;
 332       unsigned int cpuno64:1;
 333 #ifdef CpuUnused
 334       unsigned int unused:(CpuNumOfBits - CpuUnused);
 335 #endif
 336     } bitfield;
 337   unsigned int array[CpuNumOfUints];
 338 } i386_cpu_flags;
 339
 340 /* Position of opcode_modifier bits.  */
 341
 342 enum
 343 {
 344   /* has direction bit. */
 345   D = 0,
 346   /* set if operands can be words or dwords encoded the canonical way */
 347   W,
 348   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 349      operand in encoding.  */
 350   S,
 351   /* insn has a modrm byte. */
 352   Modrm,
 353   /* register is in low 3 bits of opcode */
 354   ShortForm,
 355   /* special case for jump insns.  */
 356   Jump,
 357   /* call and jump */
 358   JumpDword,
 359   /* loop and jecxz */
 360   JumpByte,
 361   /* special case for intersegment leaps/calls */
 362   JumpInterSegment,
 363   /* FP insn memory format bit, sized by 0x4 */
 364   FloatMF,
 365   /* src/dest swap for floats. */
 366   FloatR,
 367   /* has float insn direction bit. */
 368   FloatD,
 369   /* needs size prefix if in 32-bit mode */
 370   Size16,
 371   /* needs size prefix if in 16-bit mode */
 372   Size32,
 373   /* needs size prefix if in 64-bit mode */
 374   Size64,
 375   /* check register size.  */
 376   CheckRegSize,
 377   /* instruction ignores operand size prefix and in Intel mode ignores
 378      mnemonic size suffix check.  */
 379   IgnoreSize,
 380   /* default insn size depends on mode */
 381   DefaultSize,
 382   /* b suffix on instruction illegal */
 383   No_bSuf,
 384   /* w suffix on instruction illegal */
 385   No_wSuf,
 386   /* l suffix on instruction illegal */
 387   No_lSuf,
 388   /* s suffix on instruction illegal */
 389   No_sSuf,
 390   /* q suffix on instruction illegal */
 391   No_qSuf,
 392   /* long double suffix on instruction illegal */
 393   No_ldSuf,
 394   /* instruction needs FWAIT */
 395   FWait,
 396   /* quick test for string instructions */
 397   IsString,
 398   /* quick test if branch instruction is MPX supported */
 399   BNDPrefixOk,
 400   /* quick test for lockable instructions */
 401   IsLockable,
 402   /* fake an extra reg operand for clr, imul and special register
 403      processing for some instructions.  */
 404   RegKludge,
 405   /* The first operand must be xmm0 */
 406   FirstXmm0,
 407   /* An implicit xmm0 as the first operand */
 408   Implicit1stXmm0,
 409   /* The HLE prefix is OK:
 410      1. With a LOCK prefix.
 411      2. With or without a LOCK prefix.
 412      3. With a RELEASE (0xf3) prefix.
 413    */
 414 #define HLEPrefixNone           0
 415 #define HLEPrefixLock           1
 416 #define HLEPrefixAny            2
 417 #define HLEPrefixRelease        3
 418   HLEPrefixOk,
 419   /* An instruction on which a "rep" prefix is acceptable.  */
 420   RepPrefixOk,
 421   /* Convert to DWORD */
 422   ToDword,
 423   /* Convert to QWORD */
 424   ToQword,
 425   /* Address prefix changes operand 0 */
 426   AddrPrefixOp0,
 427   /* opcode is a prefix */
 428   IsPrefix,
 429   /* instruction has extension in 8 bit imm */
 430   ImmExt,
 431   /* instruction don't need Rex64 prefix.  */
 432   NoRex64,
 433   /* instruction require Rex64 prefix.  */
 434   Rex64,
 435   /* deprecated fp insn, gets a warning */
 436   Ugh,
 437   /* insn has VEX prefix:
 438         1: 128bit VEX prefix.
 439         2: 256bit VEX prefix.
 440         3: Scalar VEX prefix.
 441    */
 442 #define VEX128          1
 443 #define VEX256          2
 444 #define VEXScalar       3
 445   Vex,
 446   /* How to encode VEX.vvvv:
 447      0: VEX.vvvv must be 1111b.
 448      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 449         the content of source registers will be preserved.
 450         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 451         where the content of first source register will be overwritten
 452         by the result.
 453         VEX.NDD2.  The second destination register operand is encoded in
 454         VEX.vvvv for instructions with 2 destination register operands.
 455         For assembler, there are no difference between VEX.NDS, VEX.DDS
 456         and VEX.NDD2.
 457      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 458      instructions with 1 destination register operand.
 459      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 460         of the operands can access a memory location.
 461    */
 462 #define VEXXDS  1
 463 #define VEXNDD  2
 464 #define VEXLWP  3
 465   VexVVVV,
 466   /* How the VEX.W bit is used:
 467      0: Set by the REX.W bit.
 468      1: VEX.W0.  Should always be 0.
 469      2: VEX.W1.  Should always be 1.
 470    */
 471 #define VEXW0   1
 472 #define VEXW1   2
 473   VexW,
 474   /* VEX opcode prefix:
 475      0: VEX 0x0F opcode prefix.
 476      1: VEX 0x0F38 opcode prefix.
 477      2: VEX 0x0F3A opcode prefix
 478      3: XOP 0x08 opcode prefix.
 479      4: XOP 0x09 opcode prefix
 480      5: XOP 0x0A opcode prefix.
 481    */
 482 #define VEX0F           0
 483 #define VEX0F38         1
 484 #define VEX0F3A         2
 485 #define XOP08           3
 486 #define XOP09           4
 487 #define XOP0A           5
 488   VexOpcode,
 489   /* number of VEX source operands:
 490      0: <= 2 source operands.
 491      1: 2 XOP source operands.
 492      2: 3 source operands.
 493    */
 494 #define XOP2SOURCES     1
 495 #define VEX3SOURCES     2
 496   VexSources,
 497   /* instruction has VEX 8 bit imm */
 498   VexImmExt,
 499   /* Instruction with vector SIB byte:
 500         1: 128bit vector register.
 501         2: 256bit vector register.
 502         3: 512bit vector register.
 503    */
 504 #define VecSIB128       1
 505 #define VecSIB256       2
 506 #define VecSIB512       3
 507   VecSIB,
 508   /* SSE to AVX support required */
 509   SSE2AVX,
 510   /* No AVX equivalent */
 511   NoAVX,
 512
 513   /* insn has EVEX prefix:
 514         1: 512bit EVEX prefix.
 515         2: 128bit EVEX prefix.
 516         3: 256bit EVEX prefix.
 517         4: Length-ignored (LIG) EVEX prefix.
 518    */
 519 #define EVEX512                1
 520 #define EVEX128                2
 521 #define EVEX256                3
 522 #define EVEXLIG                4
 523   EVex,
 524
 525   /* AVX512 masking support:
 526         1: Zeroing-masking.
 527         2: Merging-masking.
 528         3: Both zeroing and merging masking.
 529    */
 530 #define ZEROING_MASKING 1
 531 #define MERGING_MASKING 2
 532 #define BOTH_MASKING    3
 533   Masking,
 534
 535   /* Input element size of vector insn:
 536         0: 32bit.
 537         1: 64bit.
 538    */
 539   VecESize,
 540
 541   /* Broadcast factor.
 542         0: No broadcast.
 543         1: 1to16 broadcast.
 544         2: 1to8 broadcast.
 545    */
 546 #define NO_BROADCAST    0
 547 #define BROADCAST_1TO16 1
 548 #define BROADCAST_1TO8  2
 549 #define BROADCAST_1TO4  3
 550 #define BROADCAST_1TO2  4
 551   Broadcast,
 552
 553   /* Static rounding control is supported.  */
 554   StaticRounding,
 555
 556   /* Supress All Exceptions is supported.  */
 557   SAE,
 558
 559   /* Copressed Disp8*N attribute.  */
 560   Disp8MemShift,
 561
 562   /* Default mask isn't allowed.  */
 563   NoDefMask,
 564
 565   /* Compatible with old (<= 2.8.1) versions of gcc  */
 566   OldGcc,
 567   /* AT&T mnemonic.  */
 568   ATTMnemonic,
 569   /* AT&T syntax.  */
 570   ATTSyntax,
 571   /* Intel syntax.  */
 572   IntelSyntax,
 573   /* AMD64.  */
 574   AMD64,
 575   /* Intel64.  */
 576   Intel64,
 577   /* The last bitfield in i386_opcode_modifier.  */
 578   Opcode_Modifier_Max
 579 };
 580
 581 typedef struct i386_opcode_modifier
 582 {
 583   unsigned int d:1;
 584   unsigned int w:1;
 585   unsigned int s:1;
 586   unsigned int modrm:1;
 587   unsigned int shortform:1;
 588   unsigned int jump:1;
 589   unsigned int jumpdword:1;
 590   unsigned int jumpbyte:1;
 591   unsigned int jumpintersegment:1;
 592   unsigned int floatmf:1;
 593   unsigned int floatr:1;
 594   unsigned int floatd:1;
 595   unsigned int size16:1;
 596   unsigned int size32:1;
 597   unsigned int size64:1;
 598   unsigned int checkregsize:1;
 599   unsigned int ignoresize:1;
 600   unsigned int defaultsize:1;
 601   unsigned int no_bsuf:1;
 602   unsigned int no_wsuf:1;
 603   unsigned int no_lsuf:1;
 604   unsigned int no_ssuf:1;
 605   unsigned int no_qsuf:1;
 606   unsigned int no_ldsuf:1;
 607   unsigned int fwait:1;
 608   unsigned int isstring:1;
 609   unsigned int bndprefixok:1;
 610   unsigned int islockable:1;
 611   unsigned int regkludge:1;
 612   unsigned int firstxmm0:1;
 613   unsigned int implicit1stxmm0:1;
 614   unsigned int hleprefixok:2;
 615   unsigned int repprefixok:1;
 616   unsigned int todword:1;
 617   unsigned int toqword:1;
 618   unsigned int addrprefixop0:1;
 619   unsigned int isprefix:1;
 620   unsigned int immext:1;
 621   unsigned int norex64:1;
 622   unsigned int rex64:1;
 623   unsigned int ugh:1;
 624   unsigned int vex:2;
 625   unsigned int vexvvvv:2;
 626   unsigned int vexw:2;
 627   unsigned int vexopcode:3;
 628   unsigned int vexsources:2;
 629   unsigned int veximmext:1;
 630   unsigned int vecsib:2;
 631   unsigned int sse2avx:1;
 632   unsigned int noavx:1;
 633   unsigned int evex:3;
 634   unsigned int masking:2;
 635   unsigned int vecesize:1;
 636   unsigned int broadcast:3;
 637   unsigned int staticrounding:1;
 638   unsigned int sae:1;
 639   unsigned int disp8memshift:3;
 640   unsigned int nodefmask:1;
 641   unsigned int oldgcc:1;
 642   unsigned int attmnemonic:1;
 643   unsigned int attsyntax:1;
 644   unsigned int intelsyntax:1;
 645   unsigned int amd64:1;
 646   unsigned int intel64:1;
 647 } i386_opcode_modifier;
 648
 649 /* Position of operand_type bits.  */
 650
 651 enum
 652 {
 653   /* 8bit register */
 654   Reg8 = 0,
 655   /* 16bit register */
 656   Reg16,
 657   /* 32bit register */
 658   Reg32,
 659   /* 64bit register */
 660   Reg64,
 661   /* Floating pointer stack register */
 662   FloatReg,
 663   /* MMX register */
 664   RegMMX,
 665   /* SSE register */
 666   RegXMM,
 667   /* AVX registers */
 668   RegYMM,
 669   /* AVX512 registers */
 670   RegZMM,
 671   /* Vector Mask registers */
 672   RegMask,
 673   /* Control register */
 674   Control,
 675   /* Debug register */
 676   Debug,
 677   /* Test register */
 678   Test,
 679   /* 2 bit segment register */
 680   SReg2,
 681   /* 3 bit segment register */
 682   SReg3,
 683   /* 1 bit immediate */
 684   Imm1,
 685   /* 8 bit immediate */
 686   Imm8,
 687   /* 8 bit immediate sign extended */
 688   Imm8S,
 689   /* 16 bit immediate */
 690   Imm16,
 691   /* 32 bit immediate */
 692   Imm32,
 693   /* 32 bit immediate sign extended */
 694   Imm32S,
 695   /* 64 bit immediate */
 696   Imm64,
 697   /* 8bit/16bit/32bit displacements are used in different ways,
 698      depending on the instruction.  For jumps, they specify the
 699      size of the PC relative displacement, for instructions with
 700      memory operand, they specify the size of the offset relative
 701      to the base register, and for instructions with memory offset
 702      such as `mov 1234,%al' they specify the size of the offset
 703      relative to the segment base.  */
 704   /* 8 bit displacement */
 705   Disp8,
 706   /* 16 bit displacement */
 707   Disp16,
 708   /* 32 bit displacement */
 709   Disp32,
 710   /* 32 bit signed displacement */
 711   Disp32S,
 712   /* 64 bit displacement */
 713   Disp64,
 714   /* Accumulator %al/%ax/%eax/%rax */
 715   Acc,
 716   /* Floating pointer top stack register %st(0) */
 717   FloatAcc,
 718   /* Register which can be used for base or index in memory operand.  */
 719   BaseIndex,
 720   /* Register to hold in/out port addr = dx */
 721   InOutPortReg,
 722   /* Register to hold shift count = cl */
 723   ShiftCount,
 724   /* Absolute address for jump.  */
 725   JumpAbsolute,
 726   /* String insn operand with fixed es segment */
 727   EsSeg,
 728   /* RegMem is for instructions with a modrm byte where the register
 729      destination operand should be encoded in the mod and regmem fields.
 730      Normally, it will be encoded in the reg field. We add a RegMem
 731      flag to the destination register operand to indicate that it should
 732      be encoded in the regmem field.  */
 733   RegMem,
 734   /* Memory.  */
 735   Mem,
 736   /* BYTE memory. */
 737   Byte,
 738   /* WORD memory. 2 byte */
 739   Word,
 740   /* DWORD memory. 4 byte */
 741   Dword,
 742   /* FWORD memory. 6 byte */
 743   Fword,
 744   /* QWORD memory. 8 byte */
 745   Qword,
 746   /* TBYTE memory. 10 byte */
 747   Tbyte,
 748   /* XMMWORD memory. */
 749   Xmmword,
 750   /* YMMWORD memory. */
 751   Ymmword,
 752   /* ZMMWORD memory.  */
 753   Zmmword,
 754   /* Unspecified memory size.  */
 755   Unspecified,
 756   /* Any memory size.  */
 757   Anysize,
 758
 759   /* Vector 4 bit immediate.  */
 760   Vec_Imm4,
 761
 762   /* Bound register.  */
 763   RegBND,
 764
 765   /* Vector 8bit displacement */
 766   Vec_Disp8,
 767
 768   /* The last bitfield in i386_operand_type.  */
 769   OTMax
 770 };
 771
 772 #define OTNumOfUints \
 773   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 774 #define OTNumOfBits \
 775   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 776
 777 /* If you get a compiler error for zero width of the unused field,
 778    comment it out.  */
 779 #define OTUnused                (OTMax + 1)
 780
 781 typedef union i386_operand_type
 782 {
 783   struct
 784     {
 785       unsigned int reg8:1;
 786       unsigned int reg16:1;
 787       unsigned int reg32:1;
 788       unsigned int reg64:1;
 789       unsigned int floatreg:1;
 790       unsigned int regmmx:1;
 791       unsigned int regxmm:1;
 792       unsigned int regymm:1;
 793       unsigned int regzmm:1;
 794       unsigned int regmask:1;
 795       unsigned int control:1;
 796       unsigned int debug:1;
 797       unsigned int test:1;
 798       unsigned int sreg2:1;
 799       unsigned int sreg3:1;
 800       unsigned int imm1:1;
 801       unsigned int imm8:1;
 802       unsigned int imm8s:1;
 803       unsigned int imm16:1;
 804       unsigned int imm32:1;
 805       unsigned int imm32s:1;
 806       unsigned int imm64:1;
 807       unsigned int disp8:1;
 808       unsigned int disp16:1;
 809       unsigned int disp32:1;
 810       unsigned int disp32s:1;
 811       unsigned int disp64:1;
 812       unsigned int acc:1;
 813       unsigned int floatacc:1;
 814       unsigned int baseindex:1;
 815       unsigned int inoutportreg:1;
 816       unsigned int shiftcount:1;
 817       unsigned int jumpabsolute:1;
 818       unsigned int esseg:1;
 819       unsigned int regmem:1;
 820       unsigned int mem:1;
 821       unsigned int byte:1;
 822       unsigned int word:1;
 823       unsigned int dword:1;
 824       unsigned int fword:1;
 825       unsigned int qword:1;
 826       unsigned int tbyte:1;
 827       unsigned int xmmword:1;
 828       unsigned int ymmword:1;
 829       unsigned int zmmword:1;
 830       unsigned int unspecified:1;
 831       unsigned int anysize:1;
 832       unsigned int vec_imm4:1;
 833       unsigned int regbnd:1;
 834       unsigned int vec_disp8:1;
 835 #ifdef OTUnused
 836       unsigned int unused:(OTNumOfBits - OTUnused);
 837 #endif
 838     } bitfield;
 839   unsigned int array[OTNumOfUints];
 840 } i386_operand_type;
 841
 842 typedef struct insn_template
 843 {
 844   /* instruction name sans width suffix ("mov" for movl insns) */
 845   char *name;
 846
 847   /* how many operands */
 848   unsigned int operands;
 849
 850   /* base_opcode is the fundamental opcode byte without optional
 851      prefix(es).  */
 852   unsigned int base_opcode;
 853 #define Opcode_D        0x2 /* Direction bit:
 854                                set if Reg --> Regmem;
 855                                unset if Regmem --> Reg. */
 856 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 857 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 858
 859   /* extension_opcode is the 3 bit extension for group <n> insns.
 860      This field is also used to store the 8-bit opcode suffix for the
 861      AMD 3DNow! instructions.
 862      If this template has no extension opcode (the usual case) use None
 863      Instructions */
 864   unsigned int extension_opcode;
 865 #define None 0xffff             /* If no extension_opcode is possible.  */
 866
 867   /* Opcode length.  */
 868   unsigned char opcode_length;
 869
 870   /* cpu feature flags */
 871   i386_cpu_flags cpu_flags;
 872
 873   /* the bits in opcode_modifier are used to generate the final opcode from
 874      the base_opcode.  These bits also are used to detect alternate forms of
 875      the same instruction */
 876   i386_opcode_modifier opcode_modifier;
 877
 878   /* operand_types[i] describes the type of operand i.  This is made
 879      by OR'ing together all of the possible type masks.  (e.g.
 880      'operand_types[i] = Reg|Imm' specifies that operand i can be
 881      either a register or an immediate operand.  */
 882   i386_operand_type operand_types[MAX_OPERANDS];
 883 }
 884 insn_template;
 885
 886 extern const insn_template i386_optab[];
 887
 888 /* these are for register name --> number & type hash lookup */
 889 typedef struct
 890 {
 891   char *reg_name;
 892   i386_operand_type reg_type;
 893   unsigned char reg_flags;
 894 #define RegRex      0x1  /* Extended register.  */
 895 #define RegRex64    0x2  /* Extended 8 bit register.  */
 896 #define RegVRex     0x4  /* Extended vector register.  */
 897   unsigned char reg_num;
 898 #define RegRip  ((unsigned char ) ~0)
 899 #define RegEip  (RegRip - 1)
 900 /* EIZ and RIZ are fake index registers.  */
 901 #define RegEiz  (RegEip - 1)
 902 #define RegRiz  (RegEiz - 1)
 903 /* FLAT is a fake segment register (Intel mode).  */
 904 #define RegFlat     ((unsigned char) ~0)
 905   signed char dw2_regnum[2];
 906 #define Dw2Inval (-1)
 907 }
 908 reg_entry;
 909
 910 /* Entries in i386_regtab.  */
 911 #define REGNAM_AL 1
 912 #define REGNAM_AX 25
 913 #define REGNAM_EAX 41
 914
 915 extern const reg_entry i386_regtab[];
 916 extern const unsigned int i386_regtab_size;
 917
 918 typedef struct
 919 {
 920   char *seg_name;
 921   unsigned int seg_prefix;
 922 }
 923 seg_entry;
 924
 925 extern const seg_entry cs;
 926 extern const seg_entry ds;
 927 extern const seg_entry ss;
 928 extern const seg_entry es;
 929 extern const seg_entry fs;
 930 extern const seg_entry gs;