opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2021 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* LZCNT support required */
  91   CpuLZCNT,
  92   /* POPCNT support required */
  93   CpuPOPCNT,
  94   /* SSE4.1 support required */
  95   CpuSSE4_1,
  96   /* SSE4.2 support required */
  97   CpuSSE4_2,
  98   /* AVX support required */
  99   CpuAVX,
 100   /* AVX2 support required */
 101   CpuAVX2,
 102   /* Intel AVX-512 Foundation Instructions support required */
 103   CpuAVX512F,
 104   /* Intel AVX-512 Conflict Detection Instructions support required */
 105   CpuAVX512CD,
 106   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 107      required */
 108   CpuAVX512ER,
 109   /* Intel AVX-512 Prefetch Instructions support required */
 110   CpuAVX512PF,
 111   /* Intel AVX-512 VL Instructions support required.  */
 112   CpuAVX512VL,
 113   /* Intel AVX-512 DQ Instructions support required.  */
 114   CpuAVX512DQ,
 115   /* Intel AVX-512 BW Instructions support required.  */
 116   CpuAVX512BW,
 117   /* Intel L1OM support required */
 118   CpuL1OM,
 119   /* Intel K1OM support required */
 120   CpuK1OM,
 121   /* Intel IAMCU support required */
 122   CpuIAMCU,
 123   /* Xsave/xrstor New Instructions support required */
 124   CpuXsave,
 125   /* Xsaveopt New Instructions support required */
 126   CpuXsaveopt,
 127   /* AES support required */
 128   CpuAES,
 129   /* PCLMUL support required */
 130   CpuPCLMUL,
 131   /* FMA support required */
 132   CpuFMA,
 133   /* FMA4 support required */
 134   CpuFMA4,
 135   /* XOP support required */
 136   CpuXOP,
 137   /* LWP support required */
 138   CpuLWP,
 139   /* BMI support required */
 140   CpuBMI,
 141   /* TBM support required */
 142   CpuTBM,
 143   /* MOVBE Instruction support required */
 144   CpuMovbe,
 145   /* CMPXCHG16B instruction support required.  */
 146   CpuCX16,
 147   /* EPT Instructions required */
 148   CpuEPT,
 149   /* RDTSCP Instruction support required */
 150   CpuRdtscp,
 151   /* FSGSBASE Instructions required */
 152   CpuFSGSBase,
 153   /* RDRND Instructions required */
 154   CpuRdRnd,
 155   /* F16C Instructions required */
 156   CpuF16C,
 157   /* Intel BMI2 support required */
 158   CpuBMI2,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 212   CpuAVX512_VP2INTERSECT,
 213   /* TDX Instructions support required.  */
 214   CpuTDX,
 215   /* Intel AVX VNNI Instructions support required.  */
 216   CpuAVX_VNNI,
 217   /* mwaitx instruction required */
 218   CpuMWAITX,
 219   /* Clzero instruction required */
 220   CpuCLZERO,
 221   /* OSPKE instruction required */
 222   CpuOSPKE,
 223   /* RDPID instruction required */
 224   CpuRDPID,
 225   /* PTWRITE instruction required */
 226   CpuPTWRITE,
 227   /* CET instructions support required */
 228   CpuIBT,
 229   CpuSHSTK,
 230   /* AMX-INT8 instructions required */
 231   CpuAMX_INT8,
 232   /* AMX-BF16 instructions required */
 233   CpuAMX_BF16,
 234   /* AMX-TILE instructions required */
 235   CpuAMX_TILE,
 236   /* GFNI instructions required */
 237   CpuGFNI,
 238   /* VAES instructions required */
 239   CpuVAES,
 240   /* VPCLMULQDQ instructions required */
 241   CpuVPCLMULQDQ,
 242   /* WBNOINVD instructions required */
 243   CpuWBNOINVD,
 244   /* PCONFIG instructions required */
 245   CpuPCONFIG,
 246   /* WAITPKG instructions required */
 247   CpuWAITPKG,
 248   /* UINTR instructions required */
 249   CpuUINTR,
 250   /* CLDEMOTE instruction required */
 251   CpuCLDEMOTE,
 252   /* MOVDIRI instruction support required */
 253   CpuMOVDIRI,
 254   /* MOVDIRR64B instruction required */
 255   CpuMOVDIR64B,
 256   /* ENQCMD instruction required */
 257   CpuENQCMD,
 258   /* SERIALIZE instruction required */
 259   CpuSERIALIZE,
 260   /* RDPRU instruction required */
 261   CpuRDPRU,
 262   /* MCOMMIT instruction required */
 263   CpuMCOMMIT,
 264   /* SEV-ES instruction(s) required */
 265   CpuSEV_ES,
 266   /* TSXLDTRK instruction required */
 267   CpuTSXLDTRK,
 268   /* KL instruction support required */
 269   CpuKL,
 270   /* WideKL instruction support required */
 271   CpuWideKL,
 272   /* HRESET instruction required */
 273   CpuHRESET,
 274   /* INVLPGB instructions required */
 275   CpuINVLPGB,
 276   /* TLBSYNC instructions required */
 277   CpuTLBSYNC,
 278   /* SNP instructions required */
 279   CpuSNP,
 280   /* 64bit support required  */
 281   Cpu64,
 282   /* Not supported in the 64bit mode  */
 283   CpuNo64,
 284   /* The last bitfield in i386_cpu_flags.  */
 285   CpuMax = CpuNo64
 286 };
 287
 288 #define CpuNumOfUints \
 289   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 290 #define CpuNumOfBits \
 291   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 292
 293 /* If you get a compiler error for zero width of the unused field,
 294    comment it out.  */
 295 #define CpuUnused       (CpuMax + 1)
 296
 297 /* We can check if an instruction is available with array instead
 298    of bitfield. */
 299 typedef union i386_cpu_flags
 300 {
 301   struct
 302     {
 303       unsigned int cpui186:1;
 304       unsigned int cpui286:1;
 305       unsigned int cpui386:1;
 306       unsigned int cpui486:1;
 307       unsigned int cpui586:1;
 308       unsigned int cpui686:1;
 309       unsigned int cpucmov:1;
 310       unsigned int cpufxsr:1;
 311       unsigned int cpuclflush:1;
 312       unsigned int cpunop:1;
 313       unsigned int cpusyscall:1;
 314       unsigned int cpu8087:1;
 315       unsigned int cpu287:1;
 316       unsigned int cpu387:1;
 317       unsigned int cpu687:1;
 318       unsigned int cpufisttp:1;
 319       unsigned int cpummx:1;
 320       unsigned int cpusse:1;
 321       unsigned int cpusse2:1;
 322       unsigned int cpua3dnow:1;
 323       unsigned int cpua3dnowa:1;
 324       unsigned int cpusse3:1;
 325       unsigned int cpupadlock:1;
 326       unsigned int cpusvme:1;
 327       unsigned int cpuvmx:1;
 328       unsigned int cpusmx:1;
 329       unsigned int cpussse3:1;
 330       unsigned int cpusse4a:1;
 331       unsigned int cpulzcnt:1;
 332       unsigned int cpupopcnt:1;
 333       unsigned int cpusse4_1:1;
 334       unsigned int cpusse4_2:1;
 335       unsigned int cpuavx:1;
 336       unsigned int cpuavx2:1;
 337       unsigned int cpuavx512f:1;
 338       unsigned int cpuavx512cd:1;
 339       unsigned int cpuavx512er:1;
 340       unsigned int cpuavx512pf:1;
 341       unsigned int cpuavx512vl:1;
 342       unsigned int cpuavx512dq:1;
 343       unsigned int cpuavx512bw:1;
 344       unsigned int cpul1om:1;
 345       unsigned int cpuk1om:1;
 346       unsigned int cpuiamcu:1;
 347       unsigned int cpuxsave:1;
 348       unsigned int cpuxsaveopt:1;
 349       unsigned int cpuaes:1;
 350       unsigned int cpupclmul:1;
 351       unsigned int cpufma:1;
 352       unsigned int cpufma4:1;
 353       unsigned int cpuxop:1;
 354       unsigned int cpulwp:1;
 355       unsigned int cpubmi:1;
 356       unsigned int cputbm:1;
 357       unsigned int cpumovbe:1;
 358       unsigned int cpucx16:1;
 359       unsigned int cpuept:1;
 360       unsigned int cpurdtscp:1;
 361       unsigned int cpufsgsbase:1;
 362       unsigned int cpurdrnd:1;
 363       unsigned int cpuf16c:1;
 364       unsigned int cpubmi2:1;
 365       unsigned int cpuhle:1;
 366       unsigned int cpurtm:1;
 367       unsigned int cpuinvpcid:1;
 368       unsigned int cpuvmfunc:1;
 369       unsigned int cpumpx:1;
 370       unsigned int cpulm:1;
 371       unsigned int cpurdseed:1;
 372       unsigned int cpuadx:1;
 373       unsigned int cpuprfchw:1;
 374       unsigned int cpusmap:1;
 375       unsigned int cpusha:1;
 376       unsigned int cpuclflushopt:1;
 377       unsigned int cpuxsaves:1;
 378       unsigned int cpuxsavec:1;
 379       unsigned int cpuprefetchwt1:1;
 380       unsigned int cpuse1:1;
 381       unsigned int cpuclwb:1;
 382       unsigned int cpuavx512ifma:1;
 383       unsigned int cpuavx512vbmi:1;
 384       unsigned int cpuavx512_4fmaps:1;
 385       unsigned int cpuavx512_4vnniw:1;
 386       unsigned int cpuavx512_vpopcntdq:1;
 387       unsigned int cpuavx512_vbmi2:1;
 388       unsigned int cpuavx512_vnni:1;
 389       unsigned int cpuavx512_bitalg:1;
 390       unsigned int cpuavx512_bf16:1;
 391       unsigned int cpuavx512_vp2intersect:1;
 392       unsigned int cputdx:1;
 393       unsigned int cpuavx_vnni:1;
 394       unsigned int cpumwaitx:1;
 395       unsigned int cpuclzero:1;
 396       unsigned int cpuospke:1;
 397       unsigned int cpurdpid:1;
 398       unsigned int cpuptwrite:1;
 399       unsigned int cpuibt:1;
 400       unsigned int cpushstk:1;
 401       unsigned int cpuamx_int8:1;
 402       unsigned int cpuamx_bf16:1;
 403       unsigned int cpuamx_tile:1;
 404       unsigned int cpugfni:1;
 405       unsigned int cpuvaes:1;
 406       unsigned int cpuvpclmulqdq:1;
 407       unsigned int cpuwbnoinvd:1;
 408       unsigned int cpupconfig:1;
 409       unsigned int cpuwaitpkg:1;
 410       unsigned int cpuuintr:1;
 411       unsigned int cpucldemote:1;
 412       unsigned int cpumovdiri:1;
 413       unsigned int cpumovdir64b:1;
 414       unsigned int cpuenqcmd:1;
 415       unsigned int cpuserialize:1;
 416       unsigned int cpurdpru:1;
 417       unsigned int cpumcommit:1;
 418       unsigned int cpusev_es:1;
 419       unsigned int cputsxldtrk:1;
 420       unsigned int cpukl:1;
 421       unsigned int cpuwidekl:1;
 422       unsigned int cpuhreset:1;
 423       unsigned int cpuinvlpgb:1;
 424       unsigned int cputlbsync:1;
 425       unsigned int cpusnp:1;
 426       unsigned int cpu64:1;
 427       unsigned int cpuno64:1;
 428 #ifdef CpuUnused
 429       unsigned int unused:(CpuNumOfBits - CpuUnused);
 430 #endif
 431     } bitfield;
 432   unsigned int array[CpuNumOfUints];
 433 } i386_cpu_flags;
 434
 435 /* Position of opcode_modifier bits.  */
 436
 437 enum
 438 {
 439   /* has direction bit. */
 440   D = 0,
 441   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 442      canonical way; the base_opcode field should hold the encoding for byte
 443      operands  */
 444   W,
 445   /* load form instruction. Must be placed before store form.  */
 446   Load,
 447   /* insn has a modrm byte. */
 448   Modrm,
 449   /* special case for jump insns; value has to be 1 */
 450 #define JUMP 1
 451   /* call and jump */
 452 #define JUMP_DWORD 2
 453   /* loop and jecxz */
 454 #define JUMP_BYTE 3
 455   /* special case for intersegment leaps/calls */
 456 #define JUMP_INTERSEGMENT 4
 457   /* absolute address for jump */
 458 #define JUMP_ABSOLUTE 5
 459   Jump,
 460   /* FP insn memory format bit, sized by 0x4 */
 461   FloatMF,
 462   /* src/dest swap for floats. */
 463   FloatR,
 464   /* needs size prefix if in 32-bit mode */
 465 #define SIZE16 1
 466   /* needs size prefix if in 16-bit mode */
 467 #define SIZE32 2
 468   /* needs size prefix if in 64-bit mode */
 469 #define SIZE64 3
 470   Size,
 471   /* check register size.  */
 472   CheckRegSize,
 473   /* instruction ignores operand size prefix and in Intel mode ignores
 474      mnemonic size suffix check.  */
 475 #define IGNORESIZE      1
 476   /* default insn size depends on mode */
 477 #define DEFAULTSIZE     2
 478   MnemonicSize,
 479   /* any memory size */
 480   Anysize,
 481   /* b suffix on instruction illegal */
 482   No_bSuf,
 483   /* w suffix on instruction illegal */
 484   No_wSuf,
 485   /* l suffix on instruction illegal */
 486   No_lSuf,
 487   /* s suffix on instruction illegal */
 488   No_sSuf,
 489   /* q suffix on instruction illegal */
 490   No_qSuf,
 491   /* long double suffix on instruction illegal */
 492   No_ldSuf,
 493   /* instruction needs FWAIT */
 494   FWait,
 495   /* IsString provides for a quick test for string instructions, and
 496      its actual value also indicates which of the operands (if any)
 497      requires use of the %es segment.  */
 498 #define IS_STRING_ES_OP0 2
 499 #define IS_STRING_ES_OP1 3
 500   IsString,
 501   /* RegMem is for instructions with a modrm byte where the register
 502      destination operand should be encoded in the mod and regmem fields.
 503      Normally, it will be encoded in the reg field. We add a RegMem
 504      flag to indicate that it should be encoded in the regmem field.  */
 505   RegMem,
 506   /* quick test if branch instruction is MPX supported */
 507   BNDPrefixOk,
 508   /* fake an extra reg operand for clr, imul and special register
 509      processing for some instructions.  */
 510   RegKludge,
 511   /* An implicit xmm0 as the first operand */
 512   Implicit1stXmm0,
 513 #define PrefixNone              0
 514 #define PrefixRep               1
 515 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 516 #define PrefixNoTrack           3
 517   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 518      to come before.  */
 519 #define PrefixLock              4
 520 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 521 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 522   PrefixOk,
 523   /* Convert to DWORD */
 524   ToDword,
 525   /* Convert to QWORD */
 526   ToQword,
 527   /* Address prefix changes register operand */
 528   AddrPrefixOpReg,
 529   /* opcode is a prefix */
 530   IsPrefix,
 531   /* instruction has extension in 8 bit imm */
 532   ImmExt,
 533   /* instruction don't need Rex64 prefix.  */
 534   NoRex64,
 535   /* deprecated fp insn, gets a warning */
 536   Ugh,
 537   /* Intel AVX Instructions support via {vex} prefix */
 538   PseudoVexPrefix,
 539   /* insn has VEX prefix:
 540         1: 128bit VEX prefix (or operand dependent).
 541         2: 256bit VEX prefix.
 542         3: Scalar VEX prefix.
 543    */
 544 #define VEX128          1
 545 #define VEX256          2
 546 #define VEXScalar       3
 547   Vex,
 548   /* How to encode VEX.vvvv:
 549      0: VEX.vvvv must be 1111b.
 550      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 551         the content of source registers will be preserved.
 552         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 553         where the content of first source register will be overwritten
 554         by the result.
 555         VEX.NDD2.  The second destination register operand is encoded in
 556         VEX.vvvv for instructions with 2 destination register operands.
 557         For assembler, there are no difference between VEX.NDS, VEX.DDS
 558         and VEX.NDD2.
 559      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 560      instructions with 1 destination register operand.
 561      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 562         of the operands can access a memory location.
 563    */
 564 #define VEXXDS  1
 565 #define VEXNDD  2
 566 #define VEXLWP  3
 567   VexVVVV,
 568   /* How the VEX.W bit is used:
 569      0: Set by the REX.W bit.
 570      1: VEX.W0.  Should always be 0.
 571      2: VEX.W1.  Should always be 1.
 572      3: VEX.WIG. The VEX.W bit is ignored.
 573    */
 574 #define VEXW0   1
 575 #define VEXW1   2
 576 #define VEXWIG  3
 577   VexW,
 578   /* Opcode encoding space (values chosen to be usable directly in
 579      VEX/XOP mmmmm and EVEX mm fields):
 580      0: Base opcode space.
 581      1: 0F opcode prefix / space.
 582      2: 0F38 opcode prefix / space.
 583      3: 0F3A opcode prefix / space.
 584      8: XOP 08 opcode space.
 585      9: XOP 09 opcode space.
 586      A: XOP 0A opcode space.
 587    */
 588 #define SPACE_BASE      0
 589 #define SPACE_0F        1
 590 #define SPACE_0F38      2
 591 #define SPACE_0F3A      3
 592 #define SPACE_XOP08     8
 593 #define SPACE_XOP09     9
 594 #define SPACE_XOP0A     0xA
 595   OpcodeSpace,
 596   /* Opcode prefix:
 597      0: None
 598      1: Add 0x66 opcode prefix.
 599      2: Add 0xf2 opcode prefix.
 600      3: Add 0xf3 opcode prefix.
 601    */
 602 #define PREFIX_NONE     0
 603 #define PREFIX_0X66     1
 604 #define PREFIX_0XF2     2
 605 #define PREFIX_0XF3     3
 606   OpcodePrefix,
 607   /* number of VEX source operands:
 608      0: <= 2 source operands.
 609      1: 2 XOP source operands.
 610      2: 3 source operands.
 611    */
 612 #define XOP2SOURCES     1
 613 #define VEX3SOURCES     2
 614   VexSources,
 615   /* Instruction with a mandatory SIB byte:
 616         1: 128bit vector register.
 617         2: 256bit vector register.
 618         3: 512bit vector register.
 619    */
 620 #define VECSIB128       1
 621 #define VECSIB256       2
 622 #define VECSIB512       3
 623 #define SIBMEM          4
 624   SIB,
 625
 626   /* SSE to AVX support required */
 627   SSE2AVX,
 628   /* No AVX equivalent */
 629   NoAVX,
 630
 631   /* insn has EVEX prefix:
 632         1: 512bit EVEX prefix.
 633         2: 128bit EVEX prefix.
 634         3: 256bit EVEX prefix.
 635         4: Length-ignored (LIG) EVEX prefix.
 636         5: Length determined from actual operands.
 637    */
 638 #define EVEX512                1
 639 #define EVEX128                2
 640 #define EVEX256                3
 641 #define EVEXLIG                4
 642 #define EVEXDYN                5
 643   EVex,
 644
 645   /* AVX512 masking support:
 646         1: Zeroing or merging masking depending on operands.
 647         2: Merging-masking.
 648         3: Both zeroing and merging masking.
 649    */
 650 #define DYNAMIC_MASKING 1
 651 #define MERGING_MASKING 2
 652 #define BOTH_MASKING    3
 653   Masking,
 654
 655   /* AVX512 broadcast support.  The number of bytes to broadcast is
 656      1 << (Broadcast - 1):
 657         1: Byte broadcast.
 658         2: Word broadcast.
 659         3: Dword broadcast.
 660         4: Qword broadcast.
 661    */
 662 #define BYTE_BROADCAST  1
 663 #define WORD_BROADCAST  2
 664 #define DWORD_BROADCAST 3
 665 #define QWORD_BROADCAST 4
 666   Broadcast,
 667
 668   /* Static rounding control is supported.  */
 669   StaticRounding,
 670
 671   /* Supress All Exceptions is supported.  */
 672   SAE,
 673
 674   /* Compressed Disp8*N attribute.  */
 675 #define DISP8_SHIFT_VL 7
 676   Disp8MemShift,
 677
 678   /* Default mask isn't allowed.  */
 679   NoDefMask,
 680
 681   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 682      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 683    */
 684   ImplicitQuadGroup,
 685
 686   /* Two source operands are swapped.  */
 687   SwapSources,
 688
 689   /* Support encoding optimization.  */
 690   Optimize,
 691
 692   /* AT&T mnemonic.  */
 693   ATTMnemonic,
 694   /* AT&T syntax.  */
 695   ATTSyntax,
 696   /* Intel syntax.  */
 697   IntelSyntax,
 698   /* ISA64: Don't change the order without other code adjustments.
 699         0: Common to AMD64 and Intel64.
 700         1: AMD64.
 701         2: Intel64.
 702         3: Only in Intel64.
 703    */
 704 #define AMD64           1
 705 #define INTEL64         2
 706 #define INTEL64ONLY     3
 707   ISA64,
 708   /* The last bitfield in i386_opcode_modifier.  */
 709   Opcode_Modifier_Num
 710 };
 711
 712 typedef struct i386_opcode_modifier
 713 {
 714   unsigned int d:1;
 715   unsigned int w:1;
 716   unsigned int load:1;
 717   unsigned int modrm:1;
 718   unsigned int jump:3;
 719   unsigned int floatmf:1;
 720   unsigned int floatr:1;
 721   unsigned int size:2;
 722   unsigned int checkregsize:1;
 723   unsigned int mnemonicsize:2;
 724   unsigned int anysize:1;
 725   unsigned int no_bsuf:1;
 726   unsigned int no_wsuf:1;
 727   unsigned int no_lsuf:1;
 728   unsigned int no_ssuf:1;
 729   unsigned int no_qsuf:1;
 730   unsigned int no_ldsuf:1;
 731   unsigned int fwait:1;
 732   unsigned int isstring:2;
 733   unsigned int regmem:1;
 734   unsigned int bndprefixok:1;
 735   unsigned int regkludge:1;
 736   unsigned int implicit1stxmm0:1;
 737   unsigned int prefixok:3;
 738   unsigned int todword:1;
 739   unsigned int toqword:1;
 740   unsigned int addrprefixopreg:1;
 741   unsigned int isprefix:1;
 742   unsigned int immext:1;
 743   unsigned int norex64:1;
 744   unsigned int ugh:1;
 745   unsigned int pseudovexprefix:1;
 746   unsigned int vex:2;
 747   unsigned int vexvvvv:2;
 748   unsigned int vexw:2;
 749   unsigned int opcodespace:4;
 750   unsigned int opcodeprefix:2;
 751   unsigned int vexsources:2;
 752   unsigned int sib:3;
 753   unsigned int sse2avx:1;
 754   unsigned int noavx:1;
 755   unsigned int evex:3;
 756   unsigned int masking:2;
 757   unsigned int broadcast:3;
 758   unsigned int staticrounding:1;
 759   unsigned int sae:1;
 760   unsigned int disp8memshift:3;
 761   unsigned int nodefmask:1;
 762   unsigned int implicitquadgroup:1;
 763   unsigned int swapsources:1;
 764   unsigned int optimize:1;
 765   unsigned int attmnemonic:1;
 766   unsigned int attsyntax:1;
 767   unsigned int intelsyntax:1;
 768   unsigned int isa64:2;
 769 } i386_opcode_modifier;
 770
 771 /* Operand classes.  */
 772
 773 #define CLASS_WIDTH 4
 774 enum operand_class
 775 {
 776   ClassNone,
 777   Reg, /* GPRs and FP regs, distinguished by operand size */
 778   SReg, /* Segment register */
 779   RegCR, /* Control register */
 780   RegDR, /* Debug register */
 781   RegTR, /* Test register */
 782   RegMMX, /* MMX register */
 783   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 784   RegMask, /* Vector Mask register */
 785   RegBND, /* Bound register */
 786 };
 787
 788 /* Special operand instances.  */
 789
 790 #define INSTANCE_WIDTH 3
 791 enum operand_instance
 792 {
 793   InstanceNone,
 794   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 795   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 796   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 797   RegB,  /* %bl / %bx / %ebx / %rbx */
 798 };
 799
 800 /* Position of operand_type bits.  */
 801
 802 enum
 803 {
 804   /* Class and Instance */
 805   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 806   /* 1 bit immediate */
 807   Imm1,
 808   /* 8 bit immediate */
 809   Imm8,
 810   /* 8 bit immediate sign extended */
 811   Imm8S,
 812   /* 16 bit immediate */
 813   Imm16,
 814   /* 32 bit immediate */
 815   Imm32,
 816   /* 32 bit immediate sign extended */
 817   Imm32S,
 818   /* 64 bit immediate */
 819   Imm64,
 820   /* 8bit/16bit/32bit displacements are used in different ways,
 821      depending on the instruction.  For jumps, they specify the
 822      size of the PC relative displacement, for instructions with
 823      memory operand, they specify the size of the offset relative
 824      to the base register, and for instructions with memory offset
 825      such as `mov 1234,%al' they specify the size of the offset
 826      relative to the segment base.  */
 827   /* 8 bit displacement */
 828   Disp8,
 829   /* 16 bit displacement */
 830   Disp16,
 831   /* 32 bit displacement */
 832   Disp32,
 833   /* 32 bit signed displacement */
 834   Disp32S,
 835   /* 64 bit displacement */
 836   Disp64,
 837   /* Register which can be used for base or index in memory operand.  */
 838   BaseIndex,
 839   /* BYTE size. */
 840   Byte,
 841   /* WORD size. 2 byte */
 842   Word,
 843   /* DWORD size. 4 byte */
 844   Dword,
 845   /* FWORD size. 6 byte */
 846   Fword,
 847   /* QWORD size. 8 byte */
 848   Qword,
 849   /* TBYTE size. 10 byte */
 850   Tbyte,
 851   /* XMMWORD size. */
 852   Xmmword,
 853   /* YMMWORD size. */
 854   Ymmword,
 855   /* ZMMWORD size.  */
 856   Zmmword,
 857   /* TMMWORD size.  */
 858   Tmmword,
 859   /* Unspecified memory size.  */
 860   Unspecified,
 861
 862   /* The number of bits in i386_operand_type.  */
 863   OTNum
 864 };
 865
 866 #define OTNumOfUints \
 867   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 868 #define OTNumOfBits \
 869   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 870
 871 /* If you get a compiler error for zero width of the unused field,
 872    comment it out.  */
 873 #define OTUnused                OTNum
 874
 875 typedef union i386_operand_type
 876 {
 877   struct
 878     {
 879       unsigned int class:CLASS_WIDTH;
 880       unsigned int instance:INSTANCE_WIDTH;
 881       unsigned int imm1:1;
 882       unsigned int imm8:1;
 883       unsigned int imm8s:1;
 884       unsigned int imm16:1;
 885       unsigned int imm32:1;
 886       unsigned int imm32s:1;
 887       unsigned int imm64:1;
 888       unsigned int disp8:1;
 889       unsigned int disp16:1;
 890       unsigned int disp32:1;
 891       unsigned int disp32s:1;
 892       unsigned int disp64:1;
 893       unsigned int baseindex:1;
 894       unsigned int byte:1;
 895       unsigned int word:1;
 896       unsigned int dword:1;
 897       unsigned int fword:1;
 898       unsigned int qword:1;
 899       unsigned int tbyte:1;
 900       unsigned int xmmword:1;
 901       unsigned int ymmword:1;
 902       unsigned int zmmword:1;
 903       unsigned int tmmword:1;
 904       unsigned int unspecified:1;
 905 #ifdef OTUnused
 906       unsigned int unused:(OTNumOfBits - OTUnused);
 907 #endif
 908     } bitfield;
 909   unsigned int array[OTNumOfUints];
 910 } i386_operand_type;
 911
 912 typedef struct insn_template
 913 {
 914   /* instruction name sans width suffix ("mov" for movl insns) */
 915   char *name;
 916
 917   /* base_opcode is the fundamental opcode byte without optional
 918      prefix(es).  */
 919   unsigned int base_opcode;
 920 #define Opcode_D        0x2 /* Direction bit:
 921                                set if Reg --> Regmem;
 922                                unset if Regmem --> Reg. */
 923 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 924 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 925 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 926 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 927
 928 /* Pseudo prefixes.  */
 929 #define Prefix_Disp8            0       /* {disp8} */
 930 #define Prefix_Disp16           1       /* {disp16} */
 931 #define Prefix_Disp32           2       /* {disp32} */
 932 #define Prefix_Load             3       /* {load} */
 933 #define Prefix_Store            4       /* {store} */
 934 #define Prefix_VEX              5       /* {vex} */
 935 #define Prefix_VEX3             6       /* {vex3} */
 936 #define Prefix_EVEX             7       /* {evex} */
 937 #define Prefix_REX              8       /* {rex} */
 938 #define Prefix_NoOptimize       9       /* {nooptimize} */
 939
 940   /* extension_opcode is the 3 bit extension for group <n> insns.
 941      This field is also used to store the 8-bit opcode suffix for the
 942      AMD 3DNow! instructions.
 943      If this template has no extension opcode (the usual case) use None
 944      Instructions */
 945   unsigned short extension_opcode;
 946 #define None 0xffff             /* If no extension_opcode is possible.  */
 947
 948   /* Opcode length.  */
 949   unsigned char opcode_length;
 950
 951   /* how many operands */
 952   unsigned char operands;
 953
 954   /* cpu feature flags */
 955   i386_cpu_flags cpu_flags;
 956
 957   /* the bits in opcode_modifier are used to generate the final opcode from
 958      the base_opcode.  These bits also are used to detect alternate forms of
 959      the same instruction */
 960   i386_opcode_modifier opcode_modifier;
 961
 962   /* operand_types[i] describes the type of operand i.  This is made
 963      by OR'ing together all of the possible type masks.  (e.g.
 964      'operand_types[i] = Reg|Imm' specifies that operand i can be
 965      either a register or an immediate operand.  */
 966   i386_operand_type operand_types[MAX_OPERANDS];
 967 }
 968 insn_template;
 969
 970 extern const insn_template i386_optab[];
 971
 972 /* these are for register name --> number & type hash lookup */
 973 typedef struct
 974 {
 975   const char *reg_name;
 976   i386_operand_type reg_type;
 977   unsigned char reg_flags;
 978 #define RegRex      0x1  /* Extended register.  */
 979 #define RegRex64    0x2  /* Extended 8 bit register.  */
 980 #define RegVRex     0x4  /* Extended vector register.  */
 981   unsigned char reg_num;
 982 #define RegIP   ((unsigned char ) ~0)
 983 /* EIZ and RIZ are fake index registers.  */
 984 #define RegIZ   (RegIP - 1)
 985 /* FLAT is a fake segment register (Intel mode).  */
 986 #define RegFlat     ((unsigned char) ~0)
 987   signed char dw2_regnum[2];
 988 #define Dw2Inval (-1)
 989 }
 990 reg_entry;
 991
 992 /* Entries in i386_regtab.  */
 993 #define REGNAM_AL 1
 994 #define REGNAM_AX 25
 995 #define REGNAM_EAX 41
 996
 997 extern const reg_entry i386_regtab[];
 998 extern const unsigned int i386_regtab_size;
 999
1000 typedef struct
1001 {
1002   char *seg_name;
1003   unsigned int seg_prefix;
1004 }
1005 seg_entry;
1006
1007 extern const seg_entry cs;
1008 extern const seg_entry ds;
1009 extern const seg_entry ss;
1010 extern const seg_entry es;
1011 extern const seg_entry fs;
1012 extern const seg_entry gs;