opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Xsave/xrstor New Instructions support required */
 116   CpuXsave,
 117   /* Xsaveopt New Instructions support required */
 118   CpuXsaveopt,
 119   /* AES support required */
 120   CpuAES,
 121   /* PCLMUL support required */
 122   CpuPCLMUL,
 123   /* FMA support required */
 124   CpuFMA,
 125   /* FMA4 support required */
 126   CpuFMA4,
 127   /* XOP support required */
 128   CpuXOP,
 129   /* LWP support required */
 130   CpuLWP,
 131   /* BMI support required */
 132   CpuBMI,
 133   /* TBM support required */
 134   CpuTBM,
 135   /* MOVBE Instruction support required */
 136   CpuMovbe,
 137   /* CMPXCHG16B instruction support required.  */
 138   CpuCX16,
 139   /* EPT Instructions required */
 140   CpuEPT,
 141   /* RDTSCP Instruction support required */
 142   CpuRdtscp,
 143   /* FSGSBASE Instructions required */
 144   CpuFSGSBase,
 145   /* RDRND Instructions required */
 146   CpuRdRnd,
 147   /* F16C Instructions required */
 148   CpuF16C,
 149   /* Intel BMI2 support required */
 150   CpuBMI2,
 151   /* LZCNT support required */
 152   CpuLZCNT,
 153   /* HLE support required */
 154   CpuHLE,
 155   /* RTM support required */
 156   CpuRTM,
 157   /* INVPCID Instructions required */
 158   CpuINVPCID,
 159   /* VMFUNC Instruction required */
 160   CpuVMFUNC,
 161   /* Intel MPX Instructions required  */
 162   CpuMPX,
 163   /* 64bit support available, used by -march= in assembler.  */
 164   CpuLM,
 165   /* RDRSEED instruction required.  */
 166   CpuRDSEED,
 167   /* Multi-presisionn add-carry instructions are required.  */
 168   CpuADX,
 169   /* Supports prefetchw and prefetch instructions.  */
 170   CpuPRFCHW,
 171   /* SMAP instructions required.  */
 172   CpuSMAP,
 173   /* SHA instructions required.  */
 174   CpuSHA,
 175   /* VREX support required  */
 176   CpuVREX,
 177   /* CLFLUSHOPT instruction required */
 178   CpuClflushOpt,
 179   /* XSAVES/XRSTORS instruction required */
 180   CpuXSAVES,
 181   /* XSAVEC instruction required */
 182   CpuXSAVEC,
 183   /* PREFETCHWT1 instruction required */
 184   CpuPREFETCHWT1,
 185   /* SE1 instruction required */
 186   CpuSE1,
 187   /* CLWB instruction required */
 188   CpuCLWB,
 189   /* PCOMMIT instruction required */
 190   CpuPCOMMIT,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* 64bit support required  */
 196   Cpu64,
 197   /* Not supported in the 64bit mode  */
 198   CpuNo64,
 199   /* The last bitfield in i386_cpu_flags.  */
 200   CpuMax = CpuNo64
 201 };
 202
 203 #define CpuNumOfUints \
 204   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 205 #define CpuNumOfBits \
 206   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 207
 208 /* If you get a compiler error for zero width of the unused field,
 209    comment it out.  */
 210 #define CpuUnused       (CpuMax + 1)
 211
 212 /* We can check if an instruction is available with array instead
 213    of bitfield. */
 214 typedef union i386_cpu_flags
 215 {
 216   struct
 217     {
 218       unsigned int cpui186:1;
 219       unsigned int cpui286:1;
 220       unsigned int cpui386:1;
 221       unsigned int cpui486:1;
 222       unsigned int cpui586:1;
 223       unsigned int cpui686:1;
 224       unsigned int cpuclflush:1;
 225       unsigned int cpunop:1;
 226       unsigned int cpusyscall:1;
 227       unsigned int cpu8087:1;
 228       unsigned int cpu287:1;
 229       unsigned int cpu387:1;
 230       unsigned int cpu687:1;
 231       unsigned int cpufisttp:1;
 232       unsigned int cpummx:1;
 233       unsigned int cpusse:1;
 234       unsigned int cpusse2:1;
 235       unsigned int cpua3dnow:1;
 236       unsigned int cpua3dnowa:1;
 237       unsigned int cpusse3:1;
 238       unsigned int cpupadlock:1;
 239       unsigned int cpusvme:1;
 240       unsigned int cpuvmx:1;
 241       unsigned int cpusmx:1;
 242       unsigned int cpussse3:1;
 243       unsigned int cpusse4a:1;
 244       unsigned int cpuabm:1;
 245       unsigned int cpusse4_1:1;
 246       unsigned int cpusse4_2:1;
 247       unsigned int cpuavx:1;
 248       unsigned int cpuavx2:1;
 249       unsigned int cpuavx512f:1;
 250       unsigned int cpuavx512cd:1;
 251       unsigned int cpuavx512er:1;
 252       unsigned int cpuavx512pf:1;
 253       unsigned int cpuavx512vl:1;
 254       unsigned int cpuavx512dq:1;
 255       unsigned int cpuavx512bw:1;
 256       unsigned int cpul1om:1;
 257       unsigned int cpuk1om:1;
 258       unsigned int cpuxsave:1;
 259       unsigned int cpuxsaveopt:1;
 260       unsigned int cpuaes:1;
 261       unsigned int cpupclmul:1;
 262       unsigned int cpufma:1;
 263       unsigned int cpufma4:1;
 264       unsigned int cpuxop:1;
 265       unsigned int cpulwp:1;
 266       unsigned int cpubmi:1;
 267       unsigned int cputbm:1;
 268       unsigned int cpumovbe:1;
 269       unsigned int cpucx16:1;
 270       unsigned int cpuept:1;
 271       unsigned int cpurdtscp:1;
 272       unsigned int cpufsgsbase:1;
 273       unsigned int cpurdrnd:1;
 274       unsigned int cpuf16c:1;
 275       unsigned int cpubmi2:1;
 276       unsigned int cpulzcnt:1;
 277       unsigned int cpuhle:1;
 278       unsigned int cpurtm:1;
 279       unsigned int cpuinvpcid:1;
 280       unsigned int cpuvmfunc:1;
 281       unsigned int cpumpx:1;
 282       unsigned int cpulm:1;
 283       unsigned int cpurdseed:1;
 284       unsigned int cpuadx:1;
 285       unsigned int cpuprfchw:1;
 286       unsigned int cpusmap:1;
 287       unsigned int cpusha:1;
 288       unsigned int cpuvrex:1;
 289       unsigned int cpuclflushopt:1;
 290       unsigned int cpuxsaves:1;
 291       unsigned int cpuxsavec:1;
 292       unsigned int cpuprefetchwt1:1;
 293       unsigned int cpuse1:1;
 294       unsigned int cpuclwb:1;
 295       unsigned int cpupcommit:1;
 296       unsigned int cpuavx512ifma:1;
 297       unsigned int cpuavx512vbmi:1;
 298       unsigned int cpu64:1;
 299       unsigned int cpuno64:1;
 300 #ifdef CpuUnused
 301       unsigned int unused:(CpuNumOfBits - CpuUnused);
 302 #endif
 303     } bitfield;
 304   unsigned int array[CpuNumOfUints];
 305 } i386_cpu_flags;
 306
 307 /* Position of opcode_modifier bits.  */
 308
 309 enum
 310 {
 311   /* has direction bit. */
 312   D = 0,
 313   /* set if operands can be words or dwords encoded the canonical way */
 314   W,
 315   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 316      operand in encoding.  */
 317   S,
 318   /* insn has a modrm byte. */
 319   Modrm,
 320   /* register is in low 3 bits of opcode */
 321   ShortForm,
 322   /* special case for jump insns.  */
 323   Jump,
 324   /* call and jump */
 325   JumpDword,
 326   /* loop and jecxz */
 327   JumpByte,
 328   /* special case for intersegment leaps/calls */
 329   JumpInterSegment,
 330   /* FP insn memory format bit, sized by 0x4 */
 331   FloatMF,
 332   /* src/dest swap for floats. */
 333   FloatR,
 334   /* has float insn direction bit. */
 335   FloatD,
 336   /* needs size prefix if in 32-bit mode */
 337   Size16,
 338   /* needs size prefix if in 16-bit mode */
 339   Size32,
 340   /* needs size prefix if in 64-bit mode */
 341   Size64,
 342   /* check register size.  */
 343   CheckRegSize,
 344   /* instruction ignores operand size prefix and in Intel mode ignores
 345      mnemonic size suffix check.  */
 346   IgnoreSize,
 347   /* default insn size depends on mode */
 348   DefaultSize,
 349   /* b suffix on instruction illegal */
 350   No_bSuf,
 351   /* w suffix on instruction illegal */
 352   No_wSuf,
 353   /* l suffix on instruction illegal */
 354   No_lSuf,
 355   /* s suffix on instruction illegal */
 356   No_sSuf,
 357   /* q suffix on instruction illegal */
 358   No_qSuf,
 359   /* long double suffix on instruction illegal */
 360   No_ldSuf,
 361   /* instruction needs FWAIT */
 362   FWait,
 363   /* quick test for string instructions */
 364   IsString,
 365   /* quick test if branch instruction is MPX supported */
 366   BNDPrefixOk,
 367   /* quick test for lockable instructions */
 368   IsLockable,
 369   /* fake an extra reg operand for clr, imul and special register
 370      processing for some instructions.  */
 371   RegKludge,
 372   /* The first operand must be xmm0 */
 373   FirstXmm0,
 374   /* An implicit xmm0 as the first operand */
 375   Implicit1stXmm0,
 376   /* The HLE prefix is OK:
 377      1. With a LOCK prefix.
 378      2. With or without a LOCK prefix.
 379      3. With a RELEASE (0xf3) prefix.
 380    */
 381 #define HLEPrefixNone           0
 382 #define HLEPrefixLock           1
 383 #define HLEPrefixAny            2
 384 #define HLEPrefixRelease        3
 385   HLEPrefixOk,
 386   /* An instruction on which a "rep" prefix is acceptable.  */
 387   RepPrefixOk,
 388   /* Convert to DWORD */
 389   ToDword,
 390   /* Convert to QWORD */
 391   ToQword,
 392   /* Address prefix changes operand 0 */
 393   AddrPrefixOp0,
 394   /* opcode is a prefix */
 395   IsPrefix,
 396   /* instruction has extension in 8 bit imm */
 397   ImmExt,
 398   /* instruction don't need Rex64 prefix.  */
 399   NoRex64,
 400   /* instruction require Rex64 prefix.  */
 401   Rex64,
 402   /* deprecated fp insn, gets a warning */
 403   Ugh,
 404   /* insn has VEX prefix:
 405         1: 128bit VEX prefix.
 406         2: 256bit VEX prefix.
 407         3: Scalar VEX prefix.
 408    */
 409 #define VEX128          1
 410 #define VEX256          2
 411 #define VEXScalar       3
 412   Vex,
 413   /* How to encode VEX.vvvv:
 414      0: VEX.vvvv must be 1111b.
 415      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 416         the content of source registers will be preserved.
 417         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 418         where the content of first source register will be overwritten
 419         by the result.
 420         VEX.NDD2.  The second destination register operand is encoded in
 421         VEX.vvvv for instructions with 2 destination register operands.
 422         For assembler, there are no difference between VEX.NDS, VEX.DDS
 423         and VEX.NDD2.
 424      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 425      instructions with 1 destination register operand.
 426      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 427         of the operands can access a memory location.
 428    */
 429 #define VEXXDS  1
 430 #define VEXNDD  2
 431 #define VEXLWP  3
 432   VexVVVV,
 433   /* How the VEX.W bit is used:
 434      0: Set by the REX.W bit.
 435      1: VEX.W0.  Should always be 0.
 436      2: VEX.W1.  Should always be 1.
 437    */
 438 #define VEXW0   1
 439 #define VEXW1   2
 440   VexW,
 441   /* VEX opcode prefix:
 442      0: VEX 0x0F opcode prefix.
 443      1: VEX 0x0F38 opcode prefix.
 444      2: VEX 0x0F3A opcode prefix
 445      3: XOP 0x08 opcode prefix.
 446      4: XOP 0x09 opcode prefix
 447      5: XOP 0x0A opcode prefix.
 448    */
 449 #define VEX0F           0
 450 #define VEX0F38         1
 451 #define VEX0F3A         2
 452 #define XOP08           3
 453 #define XOP09           4
 454 #define XOP0A           5
 455   VexOpcode,
 456   /* number of VEX source operands:
 457      0: <= 2 source operands.
 458      1: 2 XOP source operands.
 459      2: 3 source operands.
 460    */
 461 #define XOP2SOURCES     1
 462 #define VEX3SOURCES     2
 463   VexSources,
 464   /* instruction has VEX 8 bit imm */
 465   VexImmExt,
 466   /* Instruction with vector SIB byte:
 467         1: 128bit vector register.
 468         2: 256bit vector register.
 469         3: 512bit vector register.
 470    */
 471 #define VecSIB128       1
 472 #define VecSIB256       2
 473 #define VecSIB512       3
 474   VecSIB,
 475   /* SSE to AVX support required */
 476   SSE2AVX,
 477   /* No AVX equivalent */
 478   NoAVX,
 479
 480   /* insn has EVEX prefix:
 481         1: 512bit EVEX prefix.
 482         2: 128bit EVEX prefix.
 483         3: 256bit EVEX prefix.
 484         4: Length-ignored (LIG) EVEX prefix.
 485    */
 486 #define EVEX512                1
 487 #define EVEX128                2
 488 #define EVEX256                3
 489 #define EVEXLIG                4
 490   EVex,
 491
 492   /* AVX512 masking support:
 493         1: Zeroing-masking.
 494         2: Merging-masking.
 495         3: Both zeroing and merging masking.
 496    */
 497 #define ZEROING_MASKING 1
 498 #define MERGING_MASKING 2
 499 #define BOTH_MASKING    3
 500   Masking,
 501
 502   /* Input element size of vector insn:
 503         0: 32bit.
 504         1: 64bit.
 505    */
 506   VecESize,
 507
 508   /* Broadcast factor.
 509         0: No broadcast.
 510         1: 1to16 broadcast.
 511         2: 1to8 broadcast.
 512    */
 513 #define NO_BROADCAST    0
 514 #define BROADCAST_1TO16 1
 515 #define BROADCAST_1TO8  2
 516 #define BROADCAST_1TO4  3
 517 #define BROADCAST_1TO2  4
 518   Broadcast,
 519
 520   /* Static rounding control is supported.  */
 521   StaticRounding,
 522
 523   /* Supress All Exceptions is supported.  */
 524   SAE,
 525
 526   /* Copressed Disp8*N attribute.  */
 527   Disp8MemShift,
 528
 529   /* Default mask isn't allowed.  */
 530   NoDefMask,
 531
 532   /* Compatible with old (<= 2.8.1) versions of gcc  */
 533   OldGcc,
 534   /* AT&T mnemonic.  */
 535   ATTMnemonic,
 536   /* AT&T syntax.  */
 537   ATTSyntax,
 538   /* Intel syntax.  */
 539   IntelSyntax,
 540   /* The last bitfield in i386_opcode_modifier.  */
 541   Opcode_Modifier_Max
 542 };
 543
 544 typedef struct i386_opcode_modifier
 545 {
 546   unsigned int d:1;
 547   unsigned int w:1;
 548   unsigned int s:1;
 549   unsigned int modrm:1;
 550   unsigned int shortform:1;
 551   unsigned int jump:1;
 552   unsigned int jumpdword:1;
 553   unsigned int jumpbyte:1;
 554   unsigned int jumpintersegment:1;
 555   unsigned int floatmf:1;
 556   unsigned int floatr:1;
 557   unsigned int floatd:1;
 558   unsigned int size16:1;
 559   unsigned int size32:1;
 560   unsigned int size64:1;
 561   unsigned int checkregsize:1;
 562   unsigned int ignoresize:1;
 563   unsigned int defaultsize:1;
 564   unsigned int no_bsuf:1;
 565   unsigned int no_wsuf:1;
 566   unsigned int no_lsuf:1;
 567   unsigned int no_ssuf:1;
 568   unsigned int no_qsuf:1;
 569   unsigned int no_ldsuf:1;
 570   unsigned int fwait:1;
 571   unsigned int isstring:1;
 572   unsigned int bndprefixok:1;
 573   unsigned int islockable:1;
 574   unsigned int regkludge:1;
 575   unsigned int firstxmm0:1;
 576   unsigned int implicit1stxmm0:1;
 577   unsigned int hleprefixok:2;
 578   unsigned int repprefixok:1;
 579   unsigned int todword:1;
 580   unsigned int toqword:1;
 581   unsigned int addrprefixop0:1;
 582   unsigned int isprefix:1;
 583   unsigned int immext:1;
 584   unsigned int norex64:1;
 585   unsigned int rex64:1;
 586   unsigned int ugh:1;
 587   unsigned int vex:2;
 588   unsigned int vexvvvv:2;
 589   unsigned int vexw:2;
 590   unsigned int vexopcode:3;
 591   unsigned int vexsources:2;
 592   unsigned int veximmext:1;
 593   unsigned int vecsib:2;
 594   unsigned int sse2avx:1;
 595   unsigned int noavx:1;
 596   unsigned int evex:3;
 597   unsigned int masking:2;
 598   unsigned int vecesize:1;
 599   unsigned int broadcast:3;
 600   unsigned int staticrounding:1;
 601   unsigned int sae:1;
 602   unsigned int disp8memshift:3;
 603   unsigned int nodefmask:1;
 604   unsigned int oldgcc:1;
 605   unsigned int attmnemonic:1;
 606   unsigned int attsyntax:1;
 607   unsigned int intelsyntax:1;
 608 } i386_opcode_modifier;
 609
 610 /* Position of operand_type bits.  */
 611
 612 enum
 613 {
 614   /* 8bit register */
 615   Reg8 = 0,
 616   /* 16bit register */
 617   Reg16,
 618   /* 32bit register */
 619   Reg32,
 620   /* 64bit register */
 621   Reg64,
 622   /* Floating pointer stack register */
 623   FloatReg,
 624   /* MMX register */
 625   RegMMX,
 626   /* SSE register */
 627   RegXMM,
 628   /* AVX registers */
 629   RegYMM,
 630   /* AVX512 registers */
 631   RegZMM,
 632   /* Vector Mask registers */
 633   RegMask,
 634   /* Control register */
 635   Control,
 636   /* Debug register */
 637   Debug,
 638   /* Test register */
 639   Test,
 640   /* 2 bit segment register */
 641   SReg2,
 642   /* 3 bit segment register */
 643   SReg3,
 644   /* 1 bit immediate */
 645   Imm1,
 646   /* 8 bit immediate */
 647   Imm8,
 648   /* 8 bit immediate sign extended */
 649   Imm8S,
 650   /* 16 bit immediate */
 651   Imm16,
 652   /* 32 bit immediate */
 653   Imm32,
 654   /* 32 bit immediate sign extended */
 655   Imm32S,
 656   /* 64 bit immediate */
 657   Imm64,
 658   /* 8bit/16bit/32bit displacements are used in different ways,
 659      depending on the instruction.  For jumps, they specify the
 660      size of the PC relative displacement, for instructions with
 661      memory operand, they specify the size of the offset relative
 662      to the base register, and for instructions with memory offset
 663      such as `mov 1234,%al' they specify the size of the offset
 664      relative to the segment base.  */
 665   /* 8 bit displacement */
 666   Disp8,
 667   /* 16 bit displacement */
 668   Disp16,
 669   /* 32 bit displacement */
 670   Disp32,
 671   /* 32 bit signed displacement */
 672   Disp32S,
 673   /* 64 bit displacement */
 674   Disp64,
 675   /* Accumulator %al/%ax/%eax/%rax */
 676   Acc,
 677   /* Floating pointer top stack register %st(0) */
 678   FloatAcc,
 679   /* Register which can be used for base or index in memory operand.  */
 680   BaseIndex,
 681   /* Register to hold in/out port addr = dx */
 682   InOutPortReg,
 683   /* Register to hold shift count = cl */
 684   ShiftCount,
 685   /* Absolute address for jump.  */
 686   JumpAbsolute,
 687   /* String insn operand with fixed es segment */
 688   EsSeg,
 689   /* RegMem is for instructions with a modrm byte where the register
 690      destination operand should be encoded in the mod and regmem fields.
 691      Normally, it will be encoded in the reg field. We add a RegMem
 692      flag to the destination register operand to indicate that it should
 693      be encoded in the regmem field.  */
 694   RegMem,
 695   /* Memory.  */
 696   Mem,
 697   /* BYTE memory. */
 698   Byte,
 699   /* WORD memory. 2 byte */
 700   Word,
 701   /* DWORD memory. 4 byte */
 702   Dword,
 703   /* FWORD memory. 6 byte */
 704   Fword,
 705   /* QWORD memory. 8 byte */
 706   Qword,
 707   /* TBYTE memory. 10 byte */
 708   Tbyte,
 709   /* XMMWORD memory. */
 710   Xmmword,
 711   /* YMMWORD memory. */
 712   Ymmword,
 713   /* ZMMWORD memory.  */
 714   Zmmword,
 715   /* Unspecified memory size.  */
 716   Unspecified,
 717   /* Any memory size.  */
 718   Anysize,
 719
 720   /* Vector 4 bit immediate.  */
 721   Vec_Imm4,
 722
 723   /* Bound register.  */
 724   RegBND,
 725
 726   /* Vector 8bit displacement */
 727   Vec_Disp8,
 728
 729   /* The last bitfield in i386_operand_type.  */
 730   OTMax
 731 };
 732
 733 #define OTNumOfUints \
 734   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 735 #define OTNumOfBits \
 736   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 737
 738 /* If you get a compiler error for zero width of the unused field,
 739    comment it out.  */
 740 #define OTUnused                (OTMax + 1)
 741
 742 typedef union i386_operand_type
 743 {
 744   struct
 745     {
 746       unsigned int reg8:1;
 747       unsigned int reg16:1;
 748       unsigned int reg32:1;
 749       unsigned int reg64:1;
 750       unsigned int floatreg:1;
 751       unsigned int regmmx:1;
 752       unsigned int regxmm:1;
 753       unsigned int regymm:1;
 754       unsigned int regzmm:1;
 755       unsigned int regmask:1;
 756       unsigned int control:1;
 757       unsigned int debug:1;
 758       unsigned int test:1;
 759       unsigned int sreg2:1;
 760       unsigned int sreg3:1;
 761       unsigned int imm1:1;
 762       unsigned int imm8:1;
 763       unsigned int imm8s:1;
 764       unsigned int imm16:1;
 765       unsigned int imm32:1;
 766       unsigned int imm32s:1;
 767       unsigned int imm64:1;
 768       unsigned int disp8:1;
 769       unsigned int disp16:1;
 770       unsigned int disp32:1;
 771       unsigned int disp32s:1;
 772       unsigned int disp64:1;
 773       unsigned int acc:1;
 774       unsigned int floatacc:1;
 775       unsigned int baseindex:1;
 776       unsigned int inoutportreg:1;
 777       unsigned int shiftcount:1;
 778       unsigned int jumpabsolute:1;
 779       unsigned int esseg:1;
 780       unsigned int regmem:1;
 781       unsigned int mem:1;
 782       unsigned int byte:1;
 783       unsigned int word:1;
 784       unsigned int dword:1;
 785       unsigned int fword:1;
 786       unsigned int qword:1;
 787       unsigned int tbyte:1;
 788       unsigned int xmmword:1;
 789       unsigned int ymmword:1;
 790       unsigned int zmmword:1;
 791       unsigned int unspecified:1;
 792       unsigned int anysize:1;
 793       unsigned int vec_imm4:1;
 794       unsigned int regbnd:1;
 795       unsigned int vec_disp8:1;
 796 #ifdef OTUnused
 797       unsigned int unused:(OTNumOfBits - OTUnused);
 798 #endif
 799     } bitfield;
 800   unsigned int array[OTNumOfUints];
 801 } i386_operand_type;
 802
 803 typedef struct insn_template
 804 {
 805   /* instruction name sans width suffix ("mov" for movl insns) */
 806   char *name;
 807
 808   /* how many operands */
 809   unsigned int operands;
 810
 811   /* base_opcode is the fundamental opcode byte without optional
 812      prefix(es).  */
 813   unsigned int base_opcode;
 814 #define Opcode_D        0x2 /* Direction bit:
 815                                set if Reg --> Regmem;
 816                                unset if Regmem --> Reg. */
 817 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 818 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 819
 820   /* extension_opcode is the 3 bit extension for group <n> insns.
 821      This field is also used to store the 8-bit opcode suffix for the
 822      AMD 3DNow! instructions.
 823      If this template has no extension opcode (the usual case) use None
 824      Instructions */
 825   unsigned int extension_opcode;
 826 #define None 0xffff             /* If no extension_opcode is possible.  */
 827
 828   /* Opcode length.  */
 829   unsigned char opcode_length;
 830
 831   /* cpu feature flags */
 832   i386_cpu_flags cpu_flags;
 833
 834   /* the bits in opcode_modifier are used to generate the final opcode from
 835      the base_opcode.  These bits also are used to detect alternate forms of
 836      the same instruction */
 837   i386_opcode_modifier opcode_modifier;
 838
 839   /* operand_types[i] describes the type of operand i.  This is made
 840      by OR'ing together all of the possible type masks.  (e.g.
 841      'operand_types[i] = Reg|Imm' specifies that operand i can be
 842      either a register or an immediate operand.  */
 843   i386_operand_type operand_types[MAX_OPERANDS];
 844 }
 845 insn_template;
 846
 847 extern const insn_template i386_optab[];
 848
 849 /* these are for register name --> number & type hash lookup */
 850 typedef struct
 851 {
 852   char *reg_name;
 853   i386_operand_type reg_type;
 854   unsigned char reg_flags;
 855 #define RegRex      0x1  /* Extended register.  */
 856 #define RegRex64    0x2  /* Extended 8 bit register.  */
 857 #define RegVRex     0x4  /* Extended vector register.  */
 858   unsigned char reg_num;
 859 #define RegRip  ((unsigned char ) ~0)
 860 #define RegEip  (RegRip - 1)
 861 /* EIZ and RIZ are fake index registers.  */
 862 #define RegEiz  (RegEip - 1)
 863 #define RegRiz  (RegEiz - 1)
 864 /* FLAT is a fake segment register (Intel mode).  */
 865 #define RegFlat     ((unsigned char) ~0)
 866   signed char dw2_regnum[2];
 867 #define Dw2Inval (-1)
 868 }
 869 reg_entry;
 870
 871 /* Entries in i386_regtab.  */
 872 #define REGNAM_AL 1
 873 #define REGNAM_AX 25
 874 #define REGNAM_EAX 41
 875
 876 extern const reg_entry i386_regtab[];
 877 extern const unsigned int i386_regtab_size;
 878
 879 typedef struct
 880 {
 881   char *seg_name;
 882   unsigned int seg_prefix;
 883 }
 884 seg_entry;
 885
 886 extern const seg_entry cs;
 887 extern const seg_entry ds;
 888 extern const seg_entry ss;
 889 extern const seg_entry es;
 890 extern const seg_entry fs;
 891 extern const seg_entry gs;