opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2021 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #include <limits.h>
  23 #ifndef CHAR_BIT
  24 #define CHAR_BIT 8
  25 #endif
  26
  27 /* Position of cpu flags bitfiled.  */
  28
  29 enum
  30 {
  31   /* i186 or better required */
  32   Cpu186 = 0,
  33   /* i286 or better required */
  34   Cpu286,
  35   /* i386 or better required */
  36   Cpu386,
  37   /* i486 or better required */
  38   Cpu486,
  39   /* i585 or better required */
  40   Cpu586,
  41   /* i686 or better required */
  42   Cpu686,
  43   /* CMOV Instruction support required */
  44   CpuCMOV,
  45   /* FXSR Instruction support required */
  46   CpuFXSR,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* LZCNT support required */
  88   CpuLZCNT,
  89   /* POPCNT support required */
  90   CpuPOPCNT,
  91   /* SSE4.1 support required */
  92   CpuSSE4_1,
  93   /* SSE4.2 support required */
  94   CpuSSE4_2,
  95   /* AVX support required */
  96   CpuAVX,
  97   /* AVX2 support required */
  98   CpuAVX2,
  99   /* Intel AVX-512 Foundation Instructions support required */
 100   CpuAVX512F,
 101   /* Intel AVX-512 Conflict Detection Instructions support required */
 102   CpuAVX512CD,
 103   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 104      required */
 105   CpuAVX512ER,
 106   /* Intel AVX-512 Prefetch Instructions support required */
 107   CpuAVX512PF,
 108   /* Intel AVX-512 VL Instructions support required.  */
 109   CpuAVX512VL,
 110   /* Intel AVX-512 DQ Instructions support required.  */
 111   CpuAVX512DQ,
 112   /* Intel AVX-512 BW Instructions support required.  */
 113   CpuAVX512BW,
 114   /* Intel L1OM support required */
 115   CpuL1OM,
 116   /* Intel K1OM support required */
 117   CpuK1OM,
 118   /* Intel IAMCU support required */
 119   CpuIAMCU,
 120   /* Xsave/xrstor New Instructions support required */
 121   CpuXsave,
 122   /* Xsaveopt New Instructions support required */
 123   CpuXsaveopt,
 124   /* AES support required */
 125   CpuAES,
 126   /* PCLMUL support required */
 127   CpuPCLMUL,
 128   /* FMA support required */
 129   CpuFMA,
 130   /* FMA4 support required */
 131   CpuFMA4,
 132   /* XOP support required */
 133   CpuXOP,
 134   /* LWP support required */
 135   CpuLWP,
 136   /* BMI support required */
 137   CpuBMI,
 138   /* TBM support required */
 139   CpuTBM,
 140   /* MOVBE Instruction support required */
 141   CpuMovbe,
 142   /* CMPXCHG16B instruction support required.  */
 143   CpuCX16,
 144   /* EPT Instructions required */
 145   CpuEPT,
 146   /* RDTSCP Instruction support required */
 147   CpuRdtscp,
 148   /* FSGSBASE Instructions required */
 149   CpuFSGSBase,
 150   /* RDRND Instructions required */
 151   CpuRdRnd,
 152   /* F16C Instructions required */
 153   CpuF16C,
 154   /* Intel BMI2 support required */
 155   CpuBMI2,
 156   /* HLE support required */
 157   CpuHLE,
 158   /* RTM support required */
 159   CpuRTM,
 160   /* INVPCID Instructions required */
 161   CpuINVPCID,
 162   /* VMFUNC Instruction required */
 163   CpuVMFUNC,
 164   /* Intel MPX Instructions required  */
 165   CpuMPX,
 166   /* 64bit support available, used by -march= in assembler.  */
 167   CpuLM,
 168   /* RDRSEED instruction required.  */
 169   CpuRDSEED,
 170   /* Multi-presisionn add-carry instructions are required.  */
 171   CpuADX,
 172   /* Supports prefetchw and prefetch instructions.  */
 173   CpuPRFCHW,
 174   /* SMAP instructions required.  */
 175   CpuSMAP,
 176   /* SHA instructions required.  */
 177   CpuSHA,
 178   /* CLFLUSHOPT instruction required */
 179   CpuClflushOpt,
 180   /* XSAVES/XRSTORS instruction required */
 181   CpuXSAVES,
 182   /* XSAVEC instruction required */
 183   CpuXSAVEC,
 184   /* PREFETCHWT1 instruction required */
 185   CpuPREFETCHWT1,
 186   /* SE1 instruction required */
 187   CpuSE1,
 188   /* CLWB instruction required */
 189   CpuCLWB,
 190   /* Intel AVX-512 IFMA Instructions support required.  */
 191   CpuAVX512IFMA,
 192   /* Intel AVX-512 VBMI Instructions support required.  */
 193   CpuAVX512VBMI,
 194   /* Intel AVX-512 4FMAPS Instructions support required.  */
 195   CpuAVX512_4FMAPS,
 196   /* Intel AVX-512 4VNNIW Instructions support required.  */
 197   CpuAVX512_4VNNIW,
 198   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 199   CpuAVX512_VPOPCNTDQ,
 200   /* Intel AVX-512 VBMI2 Instructions support required.  */
 201   CpuAVX512_VBMI2,
 202   /* Intel AVX-512 VNNI Instructions support required.  */
 203   CpuAVX512_VNNI,
 204   /* Intel AVX-512 BITALG Instructions support required.  */
 205   CpuAVX512_BITALG,
 206   /* Intel AVX-512 BF16 Instructions support required.  */
 207   CpuAVX512_BF16,
 208   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 209   CpuAVX512_VP2INTERSECT,
 210   /* TDX Instructions support required.  */
 211   CpuTDX,
 212   /* Intel AVX VNNI Instructions support required.  */
 213   CpuAVX_VNNI,
 214   /* mwaitx instruction required */
 215   CpuMWAITX,
 216   /* Clzero instruction required */
 217   CpuCLZERO,
 218   /* OSPKE instruction required */
 219   CpuOSPKE,
 220   /* RDPID instruction required */
 221   CpuRDPID,
 222   /* PTWRITE instruction required */
 223   CpuPTWRITE,
 224   /* CET instructions support required */
 225   CpuIBT,
 226   CpuSHSTK,
 227   /* AMX-INT8 instructions required */
 228   CpuAMX_INT8,
 229   /* AMX-BF16 instructions required */
 230   CpuAMX_BF16,
 231   /* AMX-TILE instructions required */
 232   CpuAMX_TILE,
 233   /* GFNI instructions required */
 234   CpuGFNI,
 235   /* VAES instructions required */
 236   CpuVAES,
 237   /* VPCLMULQDQ instructions required */
 238   CpuVPCLMULQDQ,
 239   /* WBNOINVD instructions required */
 240   CpuWBNOINVD,
 241   /* PCONFIG instructions required */
 242   CpuPCONFIG,
 243   /* WAITPKG instructions required */
 244   CpuWAITPKG,
 245   /* UINTR instructions required */
 246   CpuUINTR,
 247   /* CLDEMOTE instruction required */
 248   CpuCLDEMOTE,
 249   /* MOVDIRI instruction support required */
 250   CpuMOVDIRI,
 251   /* MOVDIRR64B instruction required */
 252   CpuMOVDIR64B,
 253   /* ENQCMD instruction required */
 254   CpuENQCMD,
 255   /* SERIALIZE instruction required */
 256   CpuSERIALIZE,
 257   /* RDPRU instruction required */
 258   CpuRDPRU,
 259   /* MCOMMIT instruction required */
 260   CpuMCOMMIT,
 261   /* SEV-ES instruction(s) required */
 262   CpuSEV_ES,
 263   /* TSXLDTRK instruction required */
 264   CpuTSXLDTRK,
 265   /* KL instruction support required */
 266   CpuKL,
 267   /* WideKL instruction support required */
 268   CpuWideKL,
 269   /* HRESET instruction required */
 270   CpuHRESET,
 271   /* INVLPGB instructions required */
 272   CpuINVLPGB,
 273   /* TLBSYNC instructions required */
 274   CpuTLBSYNC,
 275   /* SNP instructions required */
 276   CpuSNP,
 277   /* 64bit support required  */
 278   Cpu64,
 279   /* Not supported in the 64bit mode  */
 280   CpuNo64,
 281   /* The last bitfield in i386_cpu_flags.  */
 282   CpuMax = CpuNo64
 283 };
 284
 285 #define CpuNumOfUints \
 286   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 287 #define CpuNumOfBits \
 288   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 289
 290 /* If you get a compiler error for zero width of the unused field,
 291    comment it out.  */
 292 #define CpuUnused       (CpuMax + 1)
 293
 294 /* We can check if an instruction is available with array instead
 295    of bitfield. */
 296 typedef union i386_cpu_flags
 297 {
 298   struct
 299     {
 300       unsigned int cpui186:1;
 301       unsigned int cpui286:1;
 302       unsigned int cpui386:1;
 303       unsigned int cpui486:1;
 304       unsigned int cpui586:1;
 305       unsigned int cpui686:1;
 306       unsigned int cpucmov:1;
 307       unsigned int cpufxsr:1;
 308       unsigned int cpuclflush:1;
 309       unsigned int cpunop:1;
 310       unsigned int cpusyscall:1;
 311       unsigned int cpu8087:1;
 312       unsigned int cpu287:1;
 313       unsigned int cpu387:1;
 314       unsigned int cpu687:1;
 315       unsigned int cpufisttp:1;
 316       unsigned int cpummx:1;
 317       unsigned int cpusse:1;
 318       unsigned int cpusse2:1;
 319       unsigned int cpua3dnow:1;
 320       unsigned int cpua3dnowa:1;
 321       unsigned int cpusse3:1;
 322       unsigned int cpupadlock:1;
 323       unsigned int cpusvme:1;
 324       unsigned int cpuvmx:1;
 325       unsigned int cpusmx:1;
 326       unsigned int cpussse3:1;
 327       unsigned int cpusse4a:1;
 328       unsigned int cpulzcnt:1;
 329       unsigned int cpupopcnt:1;
 330       unsigned int cpusse4_1:1;
 331       unsigned int cpusse4_2:1;
 332       unsigned int cpuavx:1;
 333       unsigned int cpuavx2:1;
 334       unsigned int cpuavx512f:1;
 335       unsigned int cpuavx512cd:1;
 336       unsigned int cpuavx512er:1;
 337       unsigned int cpuavx512pf:1;
 338       unsigned int cpuavx512vl:1;
 339       unsigned int cpuavx512dq:1;
 340       unsigned int cpuavx512bw:1;
 341       unsigned int cpul1om:1;
 342       unsigned int cpuk1om:1;
 343       unsigned int cpuiamcu:1;
 344       unsigned int cpuxsave:1;
 345       unsigned int cpuxsaveopt:1;
 346       unsigned int cpuaes:1;
 347       unsigned int cpupclmul:1;
 348       unsigned int cpufma:1;
 349       unsigned int cpufma4:1;
 350       unsigned int cpuxop:1;
 351       unsigned int cpulwp:1;
 352       unsigned int cpubmi:1;
 353       unsigned int cputbm:1;
 354       unsigned int cpumovbe:1;
 355       unsigned int cpucx16:1;
 356       unsigned int cpuept:1;
 357       unsigned int cpurdtscp:1;
 358       unsigned int cpufsgsbase:1;
 359       unsigned int cpurdrnd:1;
 360       unsigned int cpuf16c:1;
 361       unsigned int cpubmi2:1;
 362       unsigned int cpuhle:1;
 363       unsigned int cpurtm:1;
 364       unsigned int cpuinvpcid:1;
 365       unsigned int cpuvmfunc:1;
 366       unsigned int cpumpx:1;
 367       unsigned int cpulm:1;
 368       unsigned int cpurdseed:1;
 369       unsigned int cpuadx:1;
 370       unsigned int cpuprfchw:1;
 371       unsigned int cpusmap:1;
 372       unsigned int cpusha:1;
 373       unsigned int cpuclflushopt:1;
 374       unsigned int cpuxsaves:1;
 375       unsigned int cpuxsavec:1;
 376       unsigned int cpuprefetchwt1:1;
 377       unsigned int cpuse1:1;
 378       unsigned int cpuclwb:1;
 379       unsigned int cpuavx512ifma:1;
 380       unsigned int cpuavx512vbmi:1;
 381       unsigned int cpuavx512_4fmaps:1;
 382       unsigned int cpuavx512_4vnniw:1;
 383       unsigned int cpuavx512_vpopcntdq:1;
 384       unsigned int cpuavx512_vbmi2:1;
 385       unsigned int cpuavx512_vnni:1;
 386       unsigned int cpuavx512_bitalg:1;
 387       unsigned int cpuavx512_bf16:1;
 388       unsigned int cpuavx512_vp2intersect:1;
 389       unsigned int cputdx:1;
 390       unsigned int cpuavx_vnni:1;
 391       unsigned int cpumwaitx:1;
 392       unsigned int cpuclzero:1;
 393       unsigned int cpuospke:1;
 394       unsigned int cpurdpid:1;
 395       unsigned int cpuptwrite:1;
 396       unsigned int cpuibt:1;
 397       unsigned int cpushstk:1;
 398       unsigned int cpuamx_int8:1;
 399       unsigned int cpuamx_bf16:1;
 400       unsigned int cpuamx_tile:1;
 401       unsigned int cpugfni:1;
 402       unsigned int cpuvaes:1;
 403       unsigned int cpuvpclmulqdq:1;
 404       unsigned int cpuwbnoinvd:1;
 405       unsigned int cpupconfig:1;
 406       unsigned int cpuwaitpkg:1;
 407       unsigned int cpuuintr:1;
 408       unsigned int cpucldemote:1;
 409       unsigned int cpumovdiri:1;
 410       unsigned int cpumovdir64b:1;
 411       unsigned int cpuenqcmd:1;
 412       unsigned int cpuserialize:1;
 413       unsigned int cpurdpru:1;
 414       unsigned int cpumcommit:1;
 415       unsigned int cpusev_es:1;
 416       unsigned int cputsxldtrk:1;
 417       unsigned int cpukl:1;
 418       unsigned int cpuwidekl:1;
 419       unsigned int cpuhreset:1;
 420       unsigned int cpuinvlpgb:1;
 421       unsigned int cputlbsync:1;
 422       unsigned int cpusnp:1;
 423       unsigned int cpu64:1;
 424       unsigned int cpuno64:1;
 425 #ifdef CpuUnused
 426       unsigned int unused:(CpuNumOfBits - CpuUnused);
 427 #endif
 428     } bitfield;
 429   unsigned int array[CpuNumOfUints];
 430 } i386_cpu_flags;
 431
 432 /* Position of opcode_modifier bits.  */
 433
 434 enum
 435 {
 436   /* has direction bit. */
 437   D = 0,
 438   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 439      canonical way; the base_opcode field should hold the encoding for byte
 440      operands  */
 441   W,
 442   /* load form instruction. Must be placed before store form.  */
 443   Load,
 444   /* insn has a modrm byte. */
 445   Modrm,
 446   /* special case for jump insns; value has to be 1 */
 447 #define JUMP 1
 448   /* call and jump */
 449 #define JUMP_DWORD 2
 450   /* loop and jecxz */
 451 #define JUMP_BYTE 3
 452   /* special case for intersegment leaps/calls */
 453 #define JUMP_INTERSEGMENT 4
 454   /* absolute address for jump */
 455 #define JUMP_ABSOLUTE 5
 456   Jump,
 457   /* FP insn memory format bit, sized by 0x4 */
 458   FloatMF,
 459   /* src/dest swap for floats. */
 460   FloatR,
 461   /* needs size prefix if in 32-bit mode */
 462 #define SIZE16 1
 463   /* needs size prefix if in 16-bit mode */
 464 #define SIZE32 2
 465   /* needs size prefix if in 64-bit mode */
 466 #define SIZE64 3
 467   Size,
 468   /* check register size.  */
 469   CheckRegSize,
 470   /* instruction ignores operand size prefix and in Intel mode ignores
 471      mnemonic size suffix check.  */
 472 #define IGNORESIZE      1
 473   /* default insn size depends on mode */
 474 #define DEFAULTSIZE     2
 475   MnemonicSize,
 476   /* any memory size */
 477   Anysize,
 478   /* b suffix on instruction illegal */
 479   No_bSuf,
 480   /* w suffix on instruction illegal */
 481   No_wSuf,
 482   /* l suffix on instruction illegal */
 483   No_lSuf,
 484   /* s suffix on instruction illegal */
 485   No_sSuf,
 486   /* q suffix on instruction illegal */
 487   No_qSuf,
 488   /* long double suffix on instruction illegal */
 489   No_ldSuf,
 490   /* instruction needs FWAIT */
 491   FWait,
 492   /* IsString provides for a quick test for string instructions, and
 493      its actual value also indicates which of the operands (if any)
 494      requires use of the %es segment.  */
 495 #define IS_STRING_ES_OP0 2
 496 #define IS_STRING_ES_OP1 3
 497   IsString,
 498   /* RegMem is for instructions with a modrm byte where the register
 499      destination operand should be encoded in the mod and regmem fields.
 500      Normally, it will be encoded in the reg field. We add a RegMem
 501      flag to indicate that it should be encoded in the regmem field.  */
 502   RegMem,
 503   /* quick test if branch instruction is MPX supported */
 504   BNDPrefixOk,
 505   /* fake an extra reg operand for clr, imul and special register
 506      processing for some instructions.  */
 507   RegKludge,
 508   /* An implicit xmm0 as the first operand */
 509   Implicit1stXmm0,
 510 #define PrefixNone              0
 511 #define PrefixRep               1
 512 #define PrefixHLERelease        2 /* Okay with an XRELEASE (0xf3) prefix. */
 513 #define PrefixNoTrack           3
 514   /* Prefixes implying "LOCK okay" must come after Lock. All others have
 515      to come before.  */
 516 #define PrefixLock              4
 517 #define PrefixHLELock           5 /* Okay with a LOCK prefix.  */
 518 #define PrefixHLEAny            6 /* Okay with or without a LOCK prefix.  */
 519   PrefixOk,
 520   /* Convert to DWORD */
 521   ToDword,
 522   /* Convert to QWORD */
 523   ToQword,
 524   /* Address prefix changes register operand */
 525   AddrPrefixOpReg,
 526   /* opcode is a prefix */
 527   IsPrefix,
 528   /* instruction has extension in 8 bit imm */
 529   ImmExt,
 530   /* instruction don't need Rex64 prefix.  */
 531   NoRex64,
 532   /* deprecated fp insn, gets a warning */
 533   Ugh,
 534   /* Intel AVX Instructions support via {vex} prefix */
 535   PseudoVexPrefix,
 536   /* insn has VEX prefix:
 537         1: 128bit VEX prefix (or operand dependent).
 538         2: 256bit VEX prefix.
 539         3: Scalar VEX prefix.
 540    */
 541 #define VEX128          1
 542 #define VEX256          2
 543 #define VEXScalar       3
 544   Vex,
 545   /* How to encode VEX.vvvv:
 546      0: VEX.vvvv must be 1111b.
 547      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 548         the content of source registers will be preserved.
 549         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 550         where the content of first source register will be overwritten
 551         by the result.
 552         VEX.NDD2.  The second destination register operand is encoded in
 553         VEX.vvvv for instructions with 2 destination register operands.
 554         For assembler, there are no difference between VEX.NDS, VEX.DDS
 555         and VEX.NDD2.
 556      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 557      instructions with 1 destination register operand.
 558      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 559         of the operands can access a memory location.
 560    */
 561 #define VEXXDS  1
 562 #define VEXNDD  2
 563 #define VEXLWP  3
 564   VexVVVV,
 565   /* How the VEX.W bit is used:
 566      0: Set by the REX.W bit.
 567      1: VEX.W0.  Should always be 0.
 568      2: VEX.W1.  Should always be 1.
 569      3: VEX.WIG. The VEX.W bit is ignored.
 570    */
 571 #define VEXW0   1
 572 #define VEXW1   2
 573 #define VEXWIG  3
 574   VexW,
 575   /* Opcode encoding space (values chosen to be usable directly in
 576      VEX/XOP mmmmm and EVEX mm fields):
 577      0: Base opcode space.
 578      1: 0F opcode prefix / space.
 579      2: 0F38 opcode prefix / space.
 580      3: 0F3A opcode prefix / space.
 581      8: XOP 08 opcode space.
 582      9: XOP 09 opcode space.
 583      A: XOP 0A opcode space.
 584    */
 585 #define SPACE_BASE      0
 586 #define SPACE_0F        1
 587 #define SPACE_0F38      2
 588 #define SPACE_0F3A      3
 589 #define SPACE_XOP08     8
 590 #define SPACE_XOP09     9
 591 #define SPACE_XOP0A     0xA
 592   OpcodeSpace,
 593   /* Opcode prefix (values chosen to be usable directly in
 594      VEX/XOP/EVEX pp fields):
 595      0: None
 596      1: Add 0x66 opcode prefix.
 597      2: Add 0xf3 opcode prefix.
 598      3: Add 0xf2 opcode prefix.
 599    */
 600 #define PREFIX_NONE     0
 601 #define PREFIX_0X66     1
 602 #define PREFIX_0XF3     2
 603 #define PREFIX_0XF2     3
 604   OpcodePrefix,
 605   /* number of VEX source operands:
 606      0: <= 2 source operands.
 607      1: 2 XOP source operands.
 608      2: 3 source operands.
 609    */
 610 #define XOP2SOURCES     1
 611 #define VEX3SOURCES     2
 612   VexSources,
 613   /* Instruction with a mandatory SIB byte:
 614         1: 128bit vector register.
 615         2: 256bit vector register.
 616         3: 512bit vector register.
 617    */
 618 #define VECSIB128       1
 619 #define VECSIB256       2
 620 #define VECSIB512       3
 621 #define SIBMEM          4
 622   SIB,
 623
 624   /* SSE to AVX support required */
 625   SSE2AVX,
 626   /* No AVX equivalent */
 627   NoAVX,
 628
 629   /* insn has EVEX prefix:
 630         1: 512bit EVEX prefix.
 631         2: 128bit EVEX prefix.
 632         3: 256bit EVEX prefix.
 633         4: Length-ignored (LIG) EVEX prefix.
 634         5: Length determined from actual operands.
 635    */
 636 #define EVEX512                1
 637 #define EVEX128                2
 638 #define EVEX256                3
 639 #define EVEXLIG                4
 640 #define EVEXDYN                5
 641   EVex,
 642
 643   /* AVX512 masking support:
 644         1: Zeroing or merging masking depending on operands.
 645         2: Merging-masking.
 646         3: Both zeroing and merging masking.
 647    */
 648 #define DYNAMIC_MASKING 1
 649 #define MERGING_MASKING 2
 650 #define BOTH_MASKING    3
 651   Masking,
 652
 653   /* AVX512 broadcast support.  The number of bytes to broadcast is
 654      1 << (Broadcast - 1):
 655         1: Byte broadcast.
 656         2: Word broadcast.
 657         3: Dword broadcast.
 658         4: Qword broadcast.
 659    */
 660 #define BYTE_BROADCAST  1
 661 #define WORD_BROADCAST  2
 662 #define DWORD_BROADCAST 3
 663 #define QWORD_BROADCAST 4
 664   Broadcast,
 665
 666   /* Static rounding control is supported.  */
 667   StaticRounding,
 668
 669   /* Supress All Exceptions is supported.  */
 670   SAE,
 671
 672   /* Compressed Disp8*N attribute.  */
 673 #define DISP8_SHIFT_VL 7
 674   Disp8MemShift,
 675
 676   /* Default mask isn't allowed.  */
 677   NoDefMask,
 678
 679   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 680      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 681    */
 682   ImplicitQuadGroup,
 683
 684   /* Two source operands are swapped.  */
 685   SwapSources,
 686
 687   /* Support encoding optimization.  */
 688   Optimize,
 689
 690   /* AT&T mnemonic.  */
 691   ATTMnemonic,
 692   /* AT&T syntax.  */
 693   ATTSyntax,
 694   /* Intel syntax.  */
 695   IntelSyntax,
 696   /* ISA64: Don't change the order without other code adjustments.
 697         0: Common to AMD64 and Intel64.
 698         1: AMD64.
 699         2: Intel64.
 700         3: Only in Intel64.
 701    */
 702 #define AMD64           1
 703 #define INTEL64         2
 704 #define INTEL64ONLY     3
 705   ISA64,
 706   /* The last bitfield in i386_opcode_modifier.  */
 707   Opcode_Modifier_Num
 708 };
 709
 710 typedef struct i386_opcode_modifier
 711 {
 712   unsigned int d:1;
 713   unsigned int w:1;
 714   unsigned int load:1;
 715   unsigned int modrm:1;
 716   unsigned int jump:3;
 717   unsigned int floatmf:1;
 718   unsigned int floatr:1;
 719   unsigned int size:2;
 720   unsigned int checkregsize:1;
 721   unsigned int mnemonicsize:2;
 722   unsigned int anysize:1;
 723   unsigned int no_bsuf:1;
 724   unsigned int no_wsuf:1;
 725   unsigned int no_lsuf:1;
 726   unsigned int no_ssuf:1;
 727   unsigned int no_qsuf:1;
 728   unsigned int no_ldsuf:1;
 729   unsigned int fwait:1;
 730   unsigned int isstring:2;
 731   unsigned int regmem:1;
 732   unsigned int bndprefixok:1;
 733   unsigned int regkludge:1;
 734   unsigned int implicit1stxmm0:1;
 735   unsigned int prefixok:3;
 736   unsigned int todword:1;
 737   unsigned int toqword:1;
 738   unsigned int addrprefixopreg:1;
 739   unsigned int isprefix:1;
 740   unsigned int immext:1;
 741   unsigned int norex64:1;
 742   unsigned int ugh:1;
 743   unsigned int pseudovexprefix:1;
 744   unsigned int vex:2;
 745   unsigned int vexvvvv:2;
 746   unsigned int vexw:2;
 747   unsigned int opcodespace:4;
 748   unsigned int opcodeprefix:2;
 749   unsigned int vexsources:2;
 750   unsigned int sib:3;
 751   unsigned int sse2avx:1;
 752   unsigned int noavx:1;
 753   unsigned int evex:3;
 754   unsigned int masking:2;
 755   unsigned int broadcast:3;
 756   unsigned int staticrounding:1;
 757   unsigned int sae:1;
 758   unsigned int disp8memshift:3;
 759   unsigned int nodefmask:1;
 760   unsigned int implicitquadgroup:1;
 761   unsigned int swapsources:1;
 762   unsigned int optimize:1;
 763   unsigned int attmnemonic:1;
 764   unsigned int attsyntax:1;
 765   unsigned int intelsyntax:1;
 766   unsigned int isa64:2;
 767 } i386_opcode_modifier;
 768
 769 /* Operand classes.  */
 770
 771 #define CLASS_WIDTH 4
 772 enum operand_class
 773 {
 774   ClassNone,
 775   Reg, /* GPRs and FP regs, distinguished by operand size */
 776   SReg, /* Segment register */
 777   RegCR, /* Control register */
 778   RegDR, /* Debug register */
 779   RegTR, /* Test register */
 780   RegMMX, /* MMX register */
 781   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 782   RegMask, /* Vector Mask register */
 783   RegBND, /* Bound register */
 784 };
 785
 786 /* Special operand instances.  */
 787
 788 #define INSTANCE_WIDTH 3
 789 enum operand_instance
 790 {
 791   InstanceNone,
 792   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 793   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 794   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 795   RegB,  /* %bl / %bx / %ebx / %rbx */
 796 };
 797
 798 /* Position of operand_type bits.  */
 799
 800 enum
 801 {
 802   /* Class and Instance */
 803   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 804   /* 1 bit immediate */
 805   Imm1,
 806   /* 8 bit immediate */
 807   Imm8,
 808   /* 8 bit immediate sign extended */
 809   Imm8S,
 810   /* 16 bit immediate */
 811   Imm16,
 812   /* 32 bit immediate */
 813   Imm32,
 814   /* 32 bit immediate sign extended */
 815   Imm32S,
 816   /* 64 bit immediate */
 817   Imm64,
 818   /* 8bit/16bit/32bit displacements are used in different ways,
 819      depending on the instruction.  For jumps, they specify the
 820      size of the PC relative displacement, for instructions with
 821      memory operand, they specify the size of the offset relative
 822      to the base register, and for instructions with memory offset
 823      such as `mov 1234,%al' they specify the size of the offset
 824      relative to the segment base.  */
 825   /* 8 bit displacement */
 826   Disp8,
 827   /* 16 bit displacement */
 828   Disp16,
 829   /* 32 bit displacement */
 830   Disp32,
 831   /* 32 bit signed displacement */
 832   Disp32S,
 833   /* 64 bit displacement */
 834   Disp64,
 835   /* Register which can be used for base or index in memory operand.  */
 836   BaseIndex,
 837   /* BYTE size. */
 838   Byte,
 839   /* WORD size. 2 byte */
 840   Word,
 841   /* DWORD size. 4 byte */
 842   Dword,
 843   /* FWORD size. 6 byte */
 844   Fword,
 845   /* QWORD size. 8 byte */
 846   Qword,
 847   /* TBYTE size. 10 byte */
 848   Tbyte,
 849   /* XMMWORD size. */
 850   Xmmword,
 851   /* YMMWORD size. */
 852   Ymmword,
 853   /* ZMMWORD size.  */
 854   Zmmword,
 855   /* TMMWORD size.  */
 856   Tmmword,
 857   /* Unspecified memory size.  */
 858   Unspecified,
 859
 860   /* The number of bits in i386_operand_type.  */
 861   OTNum
 862 };
 863
 864 #define OTNumOfUints \
 865   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 866 #define OTNumOfBits \
 867   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 868
 869 /* If you get a compiler error for zero width of the unused field,
 870    comment it out.  */
 871 #define OTUnused                OTNum
 872
 873 typedef union i386_operand_type
 874 {
 875   struct
 876     {
 877       unsigned int class:CLASS_WIDTH;
 878       unsigned int instance:INSTANCE_WIDTH;
 879       unsigned int imm1:1;
 880       unsigned int imm8:1;
 881       unsigned int imm8s:1;
 882       unsigned int imm16:1;
 883       unsigned int imm32:1;
 884       unsigned int imm32s:1;
 885       unsigned int imm64:1;
 886       unsigned int disp8:1;
 887       unsigned int disp16:1;
 888       unsigned int disp32:1;
 889       unsigned int disp32s:1;
 890       unsigned int disp64:1;
 891       unsigned int baseindex:1;
 892       unsigned int byte:1;
 893       unsigned int word:1;
 894       unsigned int dword:1;
 895       unsigned int fword:1;
 896       unsigned int qword:1;
 897       unsigned int tbyte:1;
 898       unsigned int xmmword:1;
 899       unsigned int ymmword:1;
 900       unsigned int zmmword:1;
 901       unsigned int tmmword:1;
 902       unsigned int unspecified:1;
 903 #ifdef OTUnused
 904       unsigned int unused:(OTNumOfBits - OTUnused);
 905 #endif
 906     } bitfield;
 907   unsigned int array[OTNumOfUints];
 908 } i386_operand_type;
 909
 910 typedef struct insn_template
 911 {
 912   /* instruction name sans width suffix ("mov" for movl insns) */
 913   char *name;
 914
 915   /* base_opcode is the fundamental opcode byte without optional
 916      prefix(es).  */
 917   unsigned int base_opcode:16;
 918 #define Opcode_D        0x2 /* Direction bit:
 919                                set if Reg --> Regmem;
 920                                unset if Regmem --> Reg. */
 921 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 922 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 923 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 924 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 925
 926 /* (Fake) base opcode value for pseudo prefixes.  */
 927 #define PSEUDO_PREFIX 0
 928
 929   /* extension_opcode is the 3 bit extension for group <n> insns.
 930      This field is also used to store the 8-bit opcode suffix for the
 931      AMD 3DNow! instructions.
 932      If this template has no extension opcode (the usual case) use None
 933      Instructions */
 934   signed int extension_opcode:9;
 935 #define None (-1)               /* If no extension_opcode is possible.  */
 936
 937 /* Pseudo prefixes.  */
 938 #define Prefix_Disp8            0       /* {disp8} */
 939 #define Prefix_Disp16           1       /* {disp16} */
 940 #define Prefix_Disp32           2       /* {disp32} */
 941 #define Prefix_Load             3       /* {load} */
 942 #define Prefix_Store            4       /* {store} */
 943 #define Prefix_VEX              5       /* {vex} */
 944 #define Prefix_VEX3             6       /* {vex3} */
 945 #define Prefix_EVEX             7       /* {evex} */
 946 #define Prefix_REX              8       /* {rex} */
 947 #define Prefix_NoOptimize       9       /* {nooptimize} */
 948
 949   /* how many operands */
 950   unsigned int operands:3;
 951
 952   /* the bits in opcode_modifier are used to generate the final opcode from
 953      the base_opcode.  These bits also are used to detect alternate forms of
 954      the same instruction */
 955   i386_opcode_modifier opcode_modifier;
 956
 957   /* cpu feature flags */
 958   i386_cpu_flags cpu_flags;
 959
 960   /* operand_types[i] describes the type of operand i.  This is made
 961      by OR'ing together all of the possible type masks.  (e.g.
 962      'operand_types[i] = Reg|Imm' specifies that operand i can be
 963      either a register or an immediate operand.  */
 964   i386_operand_type operand_types[MAX_OPERANDS];
 965 }
 966 insn_template;
 967
 968 extern const insn_template i386_optab[];
 969
 970 /* these are for register name --> number & type hash lookup */
 971 typedef struct
 972 {
 973   const char *reg_name;
 974   i386_operand_type reg_type;
 975   unsigned char reg_flags;
 976 #define RegRex      0x1  /* Extended register.  */
 977 #define RegRex64    0x2  /* Extended 8 bit register.  */
 978 #define RegVRex     0x4  /* Extended vector register.  */
 979   unsigned char reg_num;
 980 #define RegIP   ((unsigned char ) ~0)
 981 /* EIZ and RIZ are fake index registers.  */
 982 #define RegIZ   (RegIP - 1)
 983 /* FLAT is a fake segment register (Intel mode).  */
 984 #define RegFlat     ((unsigned char) ~0)
 985   signed char dw2_regnum[2];
 986 #define Dw2Inval (-1)
 987 }
 988 reg_entry;
 989
 990 extern const reg_entry i386_regtab[];
 991 extern const unsigned int i386_regtab_size;
 992 extern const unsigned char i386_seg_prefixes[6];