opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* LZCNT support required */
  91   CpuLZCNT,
  92   /* POPCNT support required */
  93   CpuPOPCNT,
  94   /* SSE4.1 support required */
  95   CpuSSE4_1,
  96   /* SSE4.2 support required */
  97   CpuSSE4_2,
  98   /* AVX support required */
  99   CpuAVX,
 100   /* AVX2 support required */
 101   CpuAVX2,
 102   /* Intel AVX-512 Foundation Instructions support required */
 103   CpuAVX512F,
 104   /* Intel AVX-512 Conflict Detection Instructions support required */
 105   CpuAVX512CD,
 106   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 107      required */
 108   CpuAVX512ER,
 109   /* Intel AVX-512 Prefetch Instructions support required */
 110   CpuAVX512PF,
 111   /* Intel AVX-512 VL Instructions support required.  */
 112   CpuAVX512VL,
 113   /* Intel AVX-512 DQ Instructions support required.  */
 114   CpuAVX512DQ,
 115   /* Intel AVX-512 BW Instructions support required.  */
 116   CpuAVX512BW,
 117   /* Intel L1OM support required */
 118   CpuL1OM,
 119   /* Intel K1OM support required */
 120   CpuK1OM,
 121   /* Intel IAMCU support required */
 122   CpuIAMCU,
 123   /* Xsave/xrstor New Instructions support required */
 124   CpuXsave,
 125   /* Xsaveopt New Instructions support required */
 126   CpuXsaveopt,
 127   /* AES support required */
 128   CpuAES,
 129   /* PCLMUL support required */
 130   CpuPCLMUL,
 131   /* FMA support required */
 132   CpuFMA,
 133   /* FMA4 support required */
 134   CpuFMA4,
 135   /* XOP support required */
 136   CpuXOP,
 137   /* LWP support required */
 138   CpuLWP,
 139   /* BMI support required */
 140   CpuBMI,
 141   /* TBM support required */
 142   CpuTBM,
 143   /* MOVBE Instruction support required */
 144   CpuMovbe,
 145   /* CMPXCHG16B instruction support required.  */
 146   CpuCX16,
 147   /* EPT Instructions required */
 148   CpuEPT,
 149   /* RDTSCP Instruction support required */
 150   CpuRdtscp,
 151   /* FSGSBASE Instructions required */
 152   CpuFSGSBase,
 153   /* RDRND Instructions required */
 154   CpuRdRnd,
 155   /* F16C Instructions required */
 156   CpuF16C,
 157   /* Intel BMI2 support required */
 158   CpuBMI2,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 212   CpuAVX512_VP2INTERSECT,
 213   /* mwaitx instruction required */
 214   CpuMWAITX,
 215   /* Clzero instruction required */
 216   CpuCLZERO,
 217   /* OSPKE instruction required */
 218   CpuOSPKE,
 219   /* RDPID instruction required */
 220   CpuRDPID,
 221   /* PTWRITE instruction required */
 222   CpuPTWRITE,
 223   /* CET instructions support required */
 224   CpuIBT,
 225   CpuSHSTK,
 226   /* GFNI instructions required */
 227   CpuGFNI,
 228   /* VAES instructions required */
 229   CpuVAES,
 230   /* VPCLMULQDQ instructions required */
 231   CpuVPCLMULQDQ,
 232   /* WBNOINVD instructions required */
 233   CpuWBNOINVD,
 234   /* PCONFIG instructions required */
 235   CpuPCONFIG,
 236   /* WAITPKG instructions required */
 237   CpuWAITPKG,
 238   /* CLDEMOTE instruction required */
 239   CpuCLDEMOTE,
 240   /* MOVDIRI instruction support required */
 241   CpuMOVDIRI,
 242   /* MOVDIRR64B instruction required */
 243   CpuMOVDIR64B,
 244   /* ENQCMD instruction required */
 245   CpuENQCMD,
 246   /* RDPRU instruction required */
 247   CpuRDPRU,
 248   /* MCOMMIT instruction required */
 249   CpuMCOMMIT,
 250   /* SEV-ES instruction(s) required */
 251   CpuSEV_ES,
 252   /* 64bit support required  */
 253   Cpu64,
 254   /* Not supported in the 64bit mode  */
 255   CpuNo64,
 256   /* The last bitfield in i386_cpu_flags.  */
 257   CpuMax = CpuNo64
 258 };
 259
 260 #define CpuNumOfUints \
 261   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 262 #define CpuNumOfBits \
 263   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 264
 265 /* If you get a compiler error for zero width of the unused field,
 266    comment it out.  */
 267 #define CpuUnused       (CpuMax + 1)
 268
 269 /* We can check if an instruction is available with array instead
 270    of bitfield. */
 271 typedef union i386_cpu_flags
 272 {
 273   struct
 274     {
 275       unsigned int cpui186:1;
 276       unsigned int cpui286:1;
 277       unsigned int cpui386:1;
 278       unsigned int cpui486:1;
 279       unsigned int cpui586:1;
 280       unsigned int cpui686:1;
 281       unsigned int cpucmov:1;
 282       unsigned int cpufxsr:1;
 283       unsigned int cpuclflush:1;
 284       unsigned int cpunop:1;
 285       unsigned int cpusyscall:1;
 286       unsigned int cpu8087:1;
 287       unsigned int cpu287:1;
 288       unsigned int cpu387:1;
 289       unsigned int cpu687:1;
 290       unsigned int cpufisttp:1;
 291       unsigned int cpummx:1;
 292       unsigned int cpusse:1;
 293       unsigned int cpusse2:1;
 294       unsigned int cpua3dnow:1;
 295       unsigned int cpua3dnowa:1;
 296       unsigned int cpusse3:1;
 297       unsigned int cpupadlock:1;
 298       unsigned int cpusvme:1;
 299       unsigned int cpuvmx:1;
 300       unsigned int cpusmx:1;
 301       unsigned int cpussse3:1;
 302       unsigned int cpusse4a:1;
 303       unsigned int cpulzcnt:1;
 304       unsigned int cpupopcnt:1;
 305       unsigned int cpusse4_1:1;
 306       unsigned int cpusse4_2:1;
 307       unsigned int cpuavx:1;
 308       unsigned int cpuavx2:1;
 309       unsigned int cpuavx512f:1;
 310       unsigned int cpuavx512cd:1;
 311       unsigned int cpuavx512er:1;
 312       unsigned int cpuavx512pf:1;
 313       unsigned int cpuavx512vl:1;
 314       unsigned int cpuavx512dq:1;
 315       unsigned int cpuavx512bw:1;
 316       unsigned int cpul1om:1;
 317       unsigned int cpuk1om:1;
 318       unsigned int cpuiamcu:1;
 319       unsigned int cpuxsave:1;
 320       unsigned int cpuxsaveopt:1;
 321       unsigned int cpuaes:1;
 322       unsigned int cpupclmul:1;
 323       unsigned int cpufma:1;
 324       unsigned int cpufma4:1;
 325       unsigned int cpuxop:1;
 326       unsigned int cpulwp:1;
 327       unsigned int cpubmi:1;
 328       unsigned int cputbm:1;
 329       unsigned int cpumovbe:1;
 330       unsigned int cpucx16:1;
 331       unsigned int cpuept:1;
 332       unsigned int cpurdtscp:1;
 333       unsigned int cpufsgsbase:1;
 334       unsigned int cpurdrnd:1;
 335       unsigned int cpuf16c:1;
 336       unsigned int cpubmi2:1;
 337       unsigned int cpuhle:1;
 338       unsigned int cpurtm:1;
 339       unsigned int cpuinvpcid:1;
 340       unsigned int cpuvmfunc:1;
 341       unsigned int cpumpx:1;
 342       unsigned int cpulm:1;
 343       unsigned int cpurdseed:1;
 344       unsigned int cpuadx:1;
 345       unsigned int cpuprfchw:1;
 346       unsigned int cpusmap:1;
 347       unsigned int cpusha:1;
 348       unsigned int cpuclflushopt:1;
 349       unsigned int cpuxsaves:1;
 350       unsigned int cpuxsavec:1;
 351       unsigned int cpuprefetchwt1:1;
 352       unsigned int cpuse1:1;
 353       unsigned int cpuclwb:1;
 354       unsigned int cpuavx512ifma:1;
 355       unsigned int cpuavx512vbmi:1;
 356       unsigned int cpuavx512_4fmaps:1;
 357       unsigned int cpuavx512_4vnniw:1;
 358       unsigned int cpuavx512_vpopcntdq:1;
 359       unsigned int cpuavx512_vbmi2:1;
 360       unsigned int cpuavx512_vnni:1;
 361       unsigned int cpuavx512_bitalg:1;
 362       unsigned int cpuavx512_bf16:1;
 363       unsigned int cpuavx512_vp2intersect:1;
 364       unsigned int cpumwaitx:1;
 365       unsigned int cpuclzero:1;
 366       unsigned int cpuospke:1;
 367       unsigned int cpurdpid:1;
 368       unsigned int cpuptwrite:1;
 369       unsigned int cpuibt:1;
 370       unsigned int cpushstk:1;
 371       unsigned int cpugfni:1;
 372       unsigned int cpuvaes:1;
 373       unsigned int cpuvpclmulqdq:1;
 374       unsigned int cpuwbnoinvd:1;
 375       unsigned int cpupconfig:1;
 376       unsigned int cpuwaitpkg:1;
 377       unsigned int cpucldemote:1;
 378       unsigned int cpumovdiri:1;
 379       unsigned int cpumovdir64b:1;
 380       unsigned int cpuenqcmd:1;
 381       unsigned int cpurdpru:1;
 382       unsigned int cpumcommit:1;
 383       unsigned int cpusev_es:1;
 384       unsigned int cpu64:1;
 385       unsigned int cpuno64:1;
 386 #ifdef CpuUnused
 387       unsigned int unused:(CpuNumOfBits - CpuUnused);
 388 #endif
 389     } bitfield;
 390   unsigned int array[CpuNumOfUints];
 391 } i386_cpu_flags;
 392
 393 /* Position of opcode_modifier bits.  */
 394
 395 enum
 396 {
 397   /* has direction bit. */
 398   D = 0,
 399   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 400      canonical way; the base_opcode field should hold the encoding for byte
 401      operands  */
 402   W,
 403   /* load form instruction. Must be placed before store form.  */
 404   Load,
 405   /* insn has a modrm byte. */
 406   Modrm,
 407   /* special case for jump insns; value has to be 1 */
 408 #define JUMP 1
 409   /* call and jump */
 410 #define JUMP_DWORD 2
 411   /* loop and jecxz */
 412 #define JUMP_BYTE 3
 413   /* special case for intersegment leaps/calls */
 414 #define JUMP_INTERSEGMENT 4
 415   /* absolute address for jump */
 416 #define JUMP_ABSOLUTE 5
 417   Jump,
 418   /* FP insn memory format bit, sized by 0x4 */
 419   FloatMF,
 420   /* src/dest swap for floats. */
 421   FloatR,
 422   /* needs size prefix if in 32-bit mode */
 423 #define SIZE16 1
 424   /* needs size prefix if in 16-bit mode */
 425 #define SIZE32 2
 426   /* needs size prefix if in 64-bit mode */
 427 #define SIZE64 3
 428   Size,
 429   /* check register size.  */
 430   CheckRegSize,
 431   /* instruction ignores operand size prefix and in Intel mode ignores
 432      mnemonic size suffix check.  */
 433 #define IGNORESIZE      1
 434   /* default insn size depends on mode */
 435 #define DEFAULTSIZE     2
 436   MnemonicSize,
 437   /* any memory size */
 438   Anysize,
 439   /* b suffix on instruction illegal */
 440   No_bSuf,
 441   /* w suffix on instruction illegal */
 442   No_wSuf,
 443   /* l suffix on instruction illegal */
 444   No_lSuf,
 445   /* s suffix on instruction illegal */
 446   No_sSuf,
 447   /* q suffix on instruction illegal */
 448   No_qSuf,
 449   /* long double suffix on instruction illegal */
 450   No_ldSuf,
 451   /* instruction needs FWAIT */
 452   FWait,
 453   /* IsString provides for a quick test for string instructions, and
 454      its actual value also indicates which of the operands (if any)
 455      requires use of the %es segment.  */
 456 #define IS_STRING_ES_OP0 2
 457 #define IS_STRING_ES_OP1 3
 458   IsString,
 459   /* RegMem is for instructions with a modrm byte where the register
 460      destination operand should be encoded in the mod and regmem fields.
 461      Normally, it will be encoded in the reg field. We add a RegMem
 462      flag to indicate that it should be encoded in the regmem field.  */
 463   RegMem,
 464   /* quick test if branch instruction is MPX supported */
 465   BNDPrefixOk,
 466   /* quick test if NOTRACK prefix is supported */
 467   NoTrackPrefixOk,
 468   /* quick test for lockable instructions */
 469   IsLockable,
 470   /* fake an extra reg operand for clr, imul and special register
 471      processing for some instructions.  */
 472   RegKludge,
 473   /* An implicit xmm0 as the first operand */
 474   Implicit1stXmm0,
 475   /* The HLE prefix is OK:
 476      1. With a LOCK prefix.
 477      2. With or without a LOCK prefix.
 478      3. With a RELEASE (0xf3) prefix.
 479    */
 480 #define HLEPrefixNone           0
 481 #define HLEPrefixLock           1
 482 #define HLEPrefixAny            2
 483 #define HLEPrefixRelease        3
 484   HLEPrefixOk,
 485   /* An instruction on which a "rep" prefix is acceptable.  */
 486   RepPrefixOk,
 487   /* Convert to DWORD */
 488   ToDword,
 489   /* Convert to QWORD */
 490   ToQword,
 491   /* Address prefix changes register operand */
 492   AddrPrefixOpReg,
 493   /* opcode is a prefix */
 494   IsPrefix,
 495   /* instruction has extension in 8 bit imm */
 496   ImmExt,
 497   /* instruction don't need Rex64 prefix.  */
 498   NoRex64,
 499   /* instruction require Rex64 prefix.  */
 500   Rex64,
 501   /* deprecated fp insn, gets a warning */
 502   Ugh,
 503   /* insn has VEX prefix:
 504         1: 128bit VEX prefix (or operand dependent).
 505         2: 256bit VEX prefix.
 506         3: Scalar VEX prefix.
 507    */
 508 #define VEX128          1
 509 #define VEX256          2
 510 #define VEXScalar       3
 511   Vex,
 512   /* How to encode VEX.vvvv:
 513      0: VEX.vvvv must be 1111b.
 514      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 515         the content of source registers will be preserved.
 516         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 517         where the content of first source register will be overwritten
 518         by the result.
 519         VEX.NDD2.  The second destination register operand is encoded in
 520         VEX.vvvv for instructions with 2 destination register operands.
 521         For assembler, there are no difference between VEX.NDS, VEX.DDS
 522         and VEX.NDD2.
 523      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 524      instructions with 1 destination register operand.
 525      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 526         of the operands can access a memory location.
 527    */
 528 #define VEXXDS  1
 529 #define VEXNDD  2
 530 #define VEXLWP  3
 531   VexVVVV,
 532   /* How the VEX.W bit is used:
 533      0: Set by the REX.W bit.
 534      1: VEX.W0.  Should always be 0.
 535      2: VEX.W1.  Should always be 1.
 536      3: VEX.WIG. The VEX.W bit is ignored.
 537    */
 538 #define VEXW0   1
 539 #define VEXW1   2
 540 #define VEXWIG  3
 541   VexW,
 542   /* VEX opcode prefix:
 543      0: VEX 0x0F opcode prefix.
 544      1: VEX 0x0F38 opcode prefix.
 545      2: VEX 0x0F3A opcode prefix
 546      3: XOP 0x08 opcode prefix.
 547      4: XOP 0x09 opcode prefix
 548      5: XOP 0x0A opcode prefix.
 549    */
 550 #define VEX0F           0
 551 #define VEX0F38         1
 552 #define VEX0F3A         2
 553 #define XOP08           3
 554 #define XOP09           4
 555 #define XOP0A           5
 556   VexOpcode,
 557   /* number of VEX source operands:
 558      0: <= 2 source operands.
 559      1: 2 XOP source operands.
 560      2: 3 source operands.
 561    */
 562 #define XOP2SOURCES     1
 563 #define VEX3SOURCES     2
 564   VexSources,
 565   /* Instruction with vector SIB byte:
 566         1: 128bit vector register.
 567         2: 256bit vector register.
 568         3: 512bit vector register.
 569    */
 570 #define VecSIB128       1
 571 #define VecSIB256       2
 572 #define VecSIB512       3
 573   VecSIB,
 574   /* SSE to AVX support required */
 575   SSE2AVX,
 576   /* No AVX equivalent */
 577   NoAVX,
 578
 579   /* insn has EVEX prefix:
 580         1: 512bit EVEX prefix.
 581         2: 128bit EVEX prefix.
 582         3: 256bit EVEX prefix.
 583         4: Length-ignored (LIG) EVEX prefix.
 584         5: Length determined from actual operands.
 585    */
 586 #define EVEX512                1
 587 #define EVEX128                2
 588 #define EVEX256                3
 589 #define EVEXLIG                4
 590 #define EVEXDYN                5
 591   EVex,
 592
 593   /* AVX512 masking support:
 594         1: Zeroing or merging masking depending on operands.
 595         2: Merging-masking.
 596         3: Both zeroing and merging masking.
 597    */
 598 #define DYNAMIC_MASKING 1
 599 #define MERGING_MASKING 2
 600 #define BOTH_MASKING    3
 601   Masking,
 602
 603   /* AVX512 broadcast support.  The number of bytes to broadcast is
 604      1 << (Broadcast - 1):
 605         1: Byte broadcast.
 606         2: Word broadcast.
 607         3: Dword broadcast.
 608         4: Qword broadcast.
 609    */
 610 #define BYTE_BROADCAST  1
 611 #define WORD_BROADCAST  2
 612 #define DWORD_BROADCAST 3
 613 #define QWORD_BROADCAST 4
 614   Broadcast,
 615
 616   /* Static rounding control is supported.  */
 617   StaticRounding,
 618
 619   /* Supress All Exceptions is supported.  */
 620   SAE,
 621
 622   /* Compressed Disp8*N attribute.  */
 623 #define DISP8_SHIFT_VL 7
 624   Disp8MemShift,
 625
 626   /* Default mask isn't allowed.  */
 627   NoDefMask,
 628
 629   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 630      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 631    */
 632   ImplicitQuadGroup,
 633
 634   /* Support encoding optimization.  */
 635   Optimize,
 636
 637   /* AT&T mnemonic.  */
 638   ATTMnemonic,
 639   /* AT&T syntax.  */
 640   ATTSyntax,
 641   /* Intel syntax.  */
 642   IntelSyntax,
 643   /* ISA64: Don't change the order without other code adjustments.
 644         0: Common to AMD64 and Intel64.
 645         1: AMD64.
 646         2: Intel64.
 647         3: Only in Intel64.
 648    */
 649 #define AMD64           1
 650 #define INTEL64         2
 651 #define INTEL64ONLY     3
 652   ISA64,
 653   /* The last bitfield in i386_opcode_modifier.  */
 654   Opcode_Modifier_Num
 655 };
 656
 657 typedef struct i386_opcode_modifier
 658 {
 659   unsigned int d:1;
 660   unsigned int w:1;
 661   unsigned int load:1;
 662   unsigned int modrm:1;
 663   unsigned int jump:3;
 664   unsigned int floatmf:1;
 665   unsigned int floatr:1;
 666   unsigned int size:2;
 667   unsigned int checkregsize:1;
 668   unsigned int mnemonicsize:2;
 669   unsigned int anysize:1;
 670   unsigned int no_bsuf:1;
 671   unsigned int no_wsuf:1;
 672   unsigned int no_lsuf:1;
 673   unsigned int no_ssuf:1;
 674   unsigned int no_qsuf:1;
 675   unsigned int no_ldsuf:1;
 676   unsigned int fwait:1;
 677   unsigned int isstring:2;
 678   unsigned int regmem:1;
 679   unsigned int bndprefixok:1;
 680   unsigned int notrackprefixok:1;
 681   unsigned int islockable:1;
 682   unsigned int regkludge:1;
 683   unsigned int implicit1stxmm0:1;
 684   unsigned int hleprefixok:2;
 685   unsigned int repprefixok:1;
 686   unsigned int todword:1;
 687   unsigned int toqword:1;
 688   unsigned int addrprefixopreg:1;
 689   unsigned int isprefix:1;
 690   unsigned int immext:1;
 691   unsigned int norex64:1;
 692   unsigned int rex64:1;
 693   unsigned int ugh:1;
 694   unsigned int vex:2;
 695   unsigned int vexvvvv:2;
 696   unsigned int vexw:2;
 697   unsigned int vexopcode:3;
 698   unsigned int vexsources:2;
 699   unsigned int vecsib:2;
 700   unsigned int sse2avx:1;
 701   unsigned int noavx:1;
 702   unsigned int evex:3;
 703   unsigned int masking:2;
 704   unsigned int broadcast:3;
 705   unsigned int staticrounding:1;
 706   unsigned int sae:1;
 707   unsigned int disp8memshift:3;
 708   unsigned int nodefmask:1;
 709   unsigned int implicitquadgroup:1;
 710   unsigned int optimize:1;
 711   unsigned int attmnemonic:1;
 712   unsigned int attsyntax:1;
 713   unsigned int intelsyntax:1;
 714   unsigned int isa64:2;
 715 } i386_opcode_modifier;
 716
 717 /* Operand classes.  */
 718
 719 #define CLASS_WIDTH 4
 720 enum operand_class
 721 {
 722   ClassNone,
 723   Reg, /* GPRs and FP regs, distinguished by operand size */
 724   SReg, /* Segment register */
 725   RegCR, /* Control register */
 726   RegDR, /* Debug register */
 727   RegTR, /* Test register */
 728   RegMMX, /* MMX register */
 729   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 730   RegMask, /* Vector Mask register */
 731   RegBND, /* Bound register */
 732 };
 733
 734 /* Special operand instances.  */
 735
 736 #define INSTANCE_WIDTH 3
 737 enum operand_instance
 738 {
 739   InstanceNone,
 740   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 741   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 742   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 743   RegB,  /* %bl / %bx / %ebx / %rbx */
 744 };
 745
 746 /* Position of operand_type bits.  */
 747
 748 enum
 749 {
 750   /* Class and Instance */
 751   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 752   /* 1 bit immediate */
 753   Imm1,
 754   /* 8 bit immediate */
 755   Imm8,
 756   /* 8 bit immediate sign extended */
 757   Imm8S,
 758   /* 16 bit immediate */
 759   Imm16,
 760   /* 32 bit immediate */
 761   Imm32,
 762   /* 32 bit immediate sign extended */
 763   Imm32S,
 764   /* 64 bit immediate */
 765   Imm64,
 766   /* 8bit/16bit/32bit displacements are used in different ways,
 767      depending on the instruction.  For jumps, they specify the
 768      size of the PC relative displacement, for instructions with
 769      memory operand, they specify the size of the offset relative
 770      to the base register, and for instructions with memory offset
 771      such as `mov 1234,%al' they specify the size of the offset
 772      relative to the segment base.  */
 773   /* 8 bit displacement */
 774   Disp8,
 775   /* 16 bit displacement */
 776   Disp16,
 777   /* 32 bit displacement */
 778   Disp32,
 779   /* 32 bit signed displacement */
 780   Disp32S,
 781   /* 64 bit displacement */
 782   Disp64,
 783   /* Register which can be used for base or index in memory operand.  */
 784   BaseIndex,
 785   /* BYTE size. */
 786   Byte,
 787   /* WORD size. 2 byte */
 788   Word,
 789   /* DWORD size. 4 byte */
 790   Dword,
 791   /* FWORD size. 6 byte */
 792   Fword,
 793   /* QWORD size. 8 byte */
 794   Qword,
 795   /* TBYTE size. 10 byte */
 796   Tbyte,
 797   /* XMMWORD size. */
 798   Xmmword,
 799   /* YMMWORD size. */
 800   Ymmword,
 801   /* ZMMWORD size.  */
 802   Zmmword,
 803   /* Unspecified memory size.  */
 804   Unspecified,
 805
 806   /* The number of bits in i386_operand_type.  */
 807   OTNum
 808 };
 809
 810 #define OTNumOfUints \
 811   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 812 #define OTNumOfBits \
 813   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 814
 815 /* If you get a compiler error for zero width of the unused field,
 816    comment it out.  */
 817 #define OTUnused                OTNum
 818
 819 typedef union i386_operand_type
 820 {
 821   struct
 822     {
 823       unsigned int class:CLASS_WIDTH;
 824       unsigned int instance:INSTANCE_WIDTH;
 825       unsigned int imm1:1;
 826       unsigned int imm8:1;
 827       unsigned int imm8s:1;
 828       unsigned int imm16:1;
 829       unsigned int imm32:1;
 830       unsigned int imm32s:1;
 831       unsigned int imm64:1;
 832       unsigned int disp8:1;
 833       unsigned int disp16:1;
 834       unsigned int disp32:1;
 835       unsigned int disp32s:1;
 836       unsigned int disp64:1;
 837       unsigned int baseindex:1;
 838       unsigned int byte:1;
 839       unsigned int word:1;
 840       unsigned int dword:1;
 841       unsigned int fword:1;
 842       unsigned int qword:1;
 843       unsigned int tbyte:1;
 844       unsigned int xmmword:1;
 845       unsigned int ymmword:1;
 846       unsigned int zmmword:1;
 847       unsigned int unspecified:1;
 848 #ifdef OTUnused
 849       unsigned int unused:(OTNumOfBits - OTUnused);
 850 #endif
 851     } bitfield;
 852   unsigned int array[OTNumOfUints];
 853 } i386_operand_type;
 854
 855 typedef struct insn_template
 856 {
 857   /* instruction name sans width suffix ("mov" for movl insns) */
 858   char *name;
 859
 860   /* base_opcode is the fundamental opcode byte without optional
 861      prefix(es).  */
 862   unsigned int base_opcode;
 863 #define Opcode_D        0x2 /* Direction bit:
 864                                set if Reg --> Regmem;
 865                                unset if Regmem --> Reg. */
 866 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 867 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 868 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 869 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 870
 871   /* extension_opcode is the 3 bit extension for group <n> insns.
 872      This field is also used to store the 8-bit opcode suffix for the
 873      AMD 3DNow! instructions.
 874      If this template has no extension opcode (the usual case) use None
 875      Instructions */
 876   unsigned short extension_opcode;
 877 #define None 0xffff             /* If no extension_opcode is possible.  */
 878
 879   /* Opcode length.  */
 880   unsigned char opcode_length;
 881
 882   /* how many operands */
 883   unsigned char operands;
 884
 885   /* cpu feature flags */
 886   i386_cpu_flags cpu_flags;
 887
 888   /* the bits in opcode_modifier are used to generate the final opcode from
 889      the base_opcode.  These bits also are used to detect alternate forms of
 890      the same instruction */
 891   i386_opcode_modifier opcode_modifier;
 892
 893   /* operand_types[i] describes the type of operand i.  This is made
 894      by OR'ing together all of the possible type masks.  (e.g.
 895      'operand_types[i] = Reg|Imm' specifies that operand i can be
 896      either a register or an immediate operand.  */
 897   i386_operand_type operand_types[MAX_OPERANDS];
 898 }
 899 insn_template;
 900
 901 extern const insn_template i386_optab[];
 902
 903 /* these are for register name --> number & type hash lookup */
 904 typedef struct
 905 {
 906   char *reg_name;
 907   i386_operand_type reg_type;
 908   unsigned char reg_flags;
 909 #define RegRex      0x1  /* Extended register.  */
 910 #define RegRex64    0x2  /* Extended 8 bit register.  */
 911 #define RegVRex     0x4  /* Extended vector register.  */
 912   unsigned char reg_num;
 913 #define RegIP   ((unsigned char ) ~0)
 914 /* EIZ and RIZ are fake index registers.  */
 915 #define RegIZ   (RegIP - 1)
 916 /* FLAT is a fake segment register (Intel mode).  */
 917 #define RegFlat     ((unsigned char) ~0)
 918   signed char dw2_regnum[2];
 919 #define Dw2Inval (-1)
 920 }
 921 reg_entry;
 922
 923 /* Entries in i386_regtab.  */
 924 #define REGNAM_AL 1
 925 #define REGNAM_AX 25
 926 #define REGNAM_EAX 41
 927
 928 extern const reg_entry i386_regtab[];
 929 extern const unsigned int i386_regtab_size;
 930
 931 typedef struct
 932 {
 933   char *seg_name;
 934   unsigned int seg_prefix;
 935 }
 936 seg_entry;
 937
 938 extern const seg_entry cs;
 939 extern const seg_entry ds;
 940 extern const seg_entry ss;
 941 extern const seg_entry es;
 942 extern const seg_entry fs;
 943 extern const seg_entry gs;