Harden gdb.base/coredump-filter.exp
[deliverable/binutils-gdb.git] / opcodes / i386-opc.h
1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2015 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 #include "opcode/i386.h"
22 #ifdef HAVE_LIMITS_H
23 #include <limits.h>
24 #endif
25
26 #ifndef CHAR_BIT
27 #define CHAR_BIT 8
28 #endif
29
30 /* Position of cpu flags bitfiled. */
31
32 enum
33 {
34 /* i186 or better required */
35 Cpu186 = 0,
36 /* i286 or better required */
37 Cpu286,
38 /* i386 or better required */
39 Cpu386,
40 /* i486 or better required */
41 Cpu486,
42 /* i585 or better required */
43 Cpu586,
44 /* i686 or better required */
45 Cpu686,
46 /* CLFLUSH Instruction support required */
47 CpuClflush,
48 /* NOP Instruction support required */
49 CpuNop,
50 /* SYSCALL Instructions support required */
51 CpuSYSCALL,
52 /* Floating point support required */
53 Cpu8087,
54 /* i287 support required */
55 Cpu287,
56 /* i387 support required */
57 Cpu387,
58 /* i686 and floating point support required */
59 Cpu687,
60 /* SSE3 and floating point support required */
61 CpuFISTTP,
62 /* MMX support required */
63 CpuMMX,
64 /* SSE support required */
65 CpuSSE,
66 /* SSE2 support required */
67 CpuSSE2,
68 /* 3dnow! support required */
69 Cpu3dnow,
70 /* 3dnow! Extensions support required */
71 Cpu3dnowA,
72 /* SSE3 support required */
73 CpuSSE3,
74 /* VIA PadLock required */
75 CpuPadLock,
76 /* AMD Secure Virtual Machine Ext-s required */
77 CpuSVME,
78 /* VMX Instructions required */
79 CpuVMX,
80 /* SMX Instructions required */
81 CpuSMX,
82 /* SSSE3 support required */
83 CpuSSSE3,
84 /* SSE4a support required */
85 CpuSSE4a,
86 /* ABM New Instructions required */
87 CpuABM,
88 /* SSE4.1 support required */
89 CpuSSE4_1,
90 /* SSE4.2 support required */
91 CpuSSE4_2,
92 /* AVX support required */
93 CpuAVX,
94 /* AVX2 support required */
95 CpuAVX2,
96 /* Intel AVX-512 Foundation Instructions support required */
97 CpuAVX512F,
98 /* Intel AVX-512 Conflict Detection Instructions support required */
99 CpuAVX512CD,
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
101 required */
102 CpuAVX512ER,
103 /* Intel AVX-512 Prefetch Instructions support required */
104 CpuAVX512PF,
105 /* Intel AVX-512 VL Instructions support required. */
106 CpuAVX512VL,
107 /* Intel AVX-512 DQ Instructions support required. */
108 CpuAVX512DQ,
109 /* Intel AVX-512 BW Instructions support required. */
110 CpuAVX512BW,
111 /* Intel L1OM support required */
112 CpuL1OM,
113 /* Intel K1OM support required */
114 CpuK1OM,
115 /* Xsave/xrstor New Instructions support required */
116 CpuXsave,
117 /* Xsaveopt New Instructions support required */
118 CpuXsaveopt,
119 /* AES support required */
120 CpuAES,
121 /* PCLMUL support required */
122 CpuPCLMUL,
123 /* FMA support required */
124 CpuFMA,
125 /* FMA4 support required */
126 CpuFMA4,
127 /* XOP support required */
128 CpuXOP,
129 /* LWP support required */
130 CpuLWP,
131 /* BMI support required */
132 CpuBMI,
133 /* TBM support required */
134 CpuTBM,
135 /* MOVBE Instruction support required */
136 CpuMovbe,
137 /* CMPXCHG16B instruction support required. */
138 CpuCX16,
139 /* EPT Instructions required */
140 CpuEPT,
141 /* RDTSCP Instruction support required */
142 CpuRdtscp,
143 /* FSGSBASE Instructions required */
144 CpuFSGSBase,
145 /* RDRND Instructions required */
146 CpuRdRnd,
147 /* F16C Instructions required */
148 CpuF16C,
149 /* Intel BMI2 support required */
150 CpuBMI2,
151 /* LZCNT support required */
152 CpuLZCNT,
153 /* HLE support required */
154 CpuHLE,
155 /* RTM support required */
156 CpuRTM,
157 /* INVPCID Instructions required */
158 CpuINVPCID,
159 /* VMFUNC Instruction required */
160 CpuVMFUNC,
161 /* Intel MPX Instructions required */
162 CpuMPX,
163 /* 64bit support available, used by -march= in assembler. */
164 CpuLM,
165 /* RDRSEED instruction required. */
166 CpuRDSEED,
167 /* Multi-presisionn add-carry instructions are required. */
168 CpuADX,
169 /* Supports prefetchw and prefetch instructions. */
170 CpuPRFCHW,
171 /* SMAP instructions required. */
172 CpuSMAP,
173 /* SHA instructions required. */
174 CpuSHA,
175 /* VREX support required */
176 CpuVREX,
177 /* CLFLUSHOPT instruction required */
178 CpuClflushOpt,
179 /* XSAVES/XRSTORS instruction required */
180 CpuXSAVES,
181 /* XSAVEC instruction required */
182 CpuXSAVEC,
183 /* PREFETCHWT1 instruction required */
184 CpuPREFETCHWT1,
185 /* SE1 instruction required */
186 CpuSE1,
187 /* CLWB instruction required */
188 CpuCLWB,
189 /* PCOMMIT instruction required */
190 CpuPCOMMIT,
191 /* Intel AVX-512 IFMA Instructions support required. */
192 CpuAVX512IFMA,
193 /* Intel AVX-512 VBMI Instructions support required. */
194 CpuAVX512VBMI,
195 /* Clzero instruction required */
196 CpuCLZERO,
197 /* 64bit support required */
198 Cpu64,
199 /* Not supported in the 64bit mode */
200 CpuNo64,
201 /* The last bitfield in i386_cpu_flags. */
202 CpuMax = CpuNo64
203 };
204
205 #define CpuNumOfUints \
206 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
207 #define CpuNumOfBits \
208 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
209
210 /* If you get a compiler error for zero width of the unused field,
211 comment it out. */
212 #define CpuUnused (CpuMax + 1)
213
214 /* We can check if an instruction is available with array instead
215 of bitfield. */
216 typedef union i386_cpu_flags
217 {
218 struct
219 {
220 unsigned int cpui186:1;
221 unsigned int cpui286:1;
222 unsigned int cpui386:1;
223 unsigned int cpui486:1;
224 unsigned int cpui586:1;
225 unsigned int cpui686:1;
226 unsigned int cpuclflush:1;
227 unsigned int cpunop:1;
228 unsigned int cpusyscall:1;
229 unsigned int cpu8087:1;
230 unsigned int cpu287:1;
231 unsigned int cpu387:1;
232 unsigned int cpu687:1;
233 unsigned int cpufisttp:1;
234 unsigned int cpummx:1;
235 unsigned int cpusse:1;
236 unsigned int cpusse2:1;
237 unsigned int cpua3dnow:1;
238 unsigned int cpua3dnowa:1;
239 unsigned int cpusse3:1;
240 unsigned int cpupadlock:1;
241 unsigned int cpusvme:1;
242 unsigned int cpuvmx:1;
243 unsigned int cpusmx:1;
244 unsigned int cpussse3:1;
245 unsigned int cpusse4a:1;
246 unsigned int cpuabm:1;
247 unsigned int cpusse4_1:1;
248 unsigned int cpusse4_2:1;
249 unsigned int cpuavx:1;
250 unsigned int cpuavx2:1;
251 unsigned int cpuavx512f:1;
252 unsigned int cpuavx512cd:1;
253 unsigned int cpuavx512er:1;
254 unsigned int cpuavx512pf:1;
255 unsigned int cpuavx512vl:1;
256 unsigned int cpuavx512dq:1;
257 unsigned int cpuavx512bw:1;
258 unsigned int cpul1om:1;
259 unsigned int cpuk1om:1;
260 unsigned int cpuxsave:1;
261 unsigned int cpuxsaveopt:1;
262 unsigned int cpuaes:1;
263 unsigned int cpupclmul:1;
264 unsigned int cpufma:1;
265 unsigned int cpufma4:1;
266 unsigned int cpuxop:1;
267 unsigned int cpulwp:1;
268 unsigned int cpubmi:1;
269 unsigned int cputbm:1;
270 unsigned int cpumovbe:1;
271 unsigned int cpucx16:1;
272 unsigned int cpuept:1;
273 unsigned int cpurdtscp:1;
274 unsigned int cpufsgsbase:1;
275 unsigned int cpurdrnd:1;
276 unsigned int cpuf16c:1;
277 unsigned int cpubmi2:1;
278 unsigned int cpulzcnt:1;
279 unsigned int cpuhle:1;
280 unsigned int cpurtm:1;
281 unsigned int cpuinvpcid:1;
282 unsigned int cpuvmfunc:1;
283 unsigned int cpumpx:1;
284 unsigned int cpulm:1;
285 unsigned int cpurdseed:1;
286 unsigned int cpuadx:1;
287 unsigned int cpuprfchw:1;
288 unsigned int cpusmap:1;
289 unsigned int cpusha:1;
290 unsigned int cpuvrex:1;
291 unsigned int cpuclflushopt:1;
292 unsigned int cpuxsaves:1;
293 unsigned int cpuxsavec:1;
294 unsigned int cpuprefetchwt1:1;
295 unsigned int cpuse1:1;
296 unsigned int cpuclwb:1;
297 unsigned int cpupcommit:1;
298 unsigned int cpuavx512ifma:1;
299 unsigned int cpuavx512vbmi:1;
300 unsigned int cpuclzero:1;
301 unsigned int cpu64:1;
302 unsigned int cpuno64:1;
303 #ifdef CpuUnused
304 unsigned int unused:(CpuNumOfBits - CpuUnused);
305 #endif
306 } bitfield;
307 unsigned int array[CpuNumOfUints];
308 } i386_cpu_flags;
309
310 /* Position of opcode_modifier bits. */
311
312 enum
313 {
314 /* has direction bit. */
315 D = 0,
316 /* set if operands can be words or dwords encoded the canonical way */
317 W,
318 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
319 operand in encoding. */
320 S,
321 /* insn has a modrm byte. */
322 Modrm,
323 /* register is in low 3 bits of opcode */
324 ShortForm,
325 /* special case for jump insns. */
326 Jump,
327 /* call and jump */
328 JumpDword,
329 /* loop and jecxz */
330 JumpByte,
331 /* special case for intersegment leaps/calls */
332 JumpInterSegment,
333 /* FP insn memory format bit, sized by 0x4 */
334 FloatMF,
335 /* src/dest swap for floats. */
336 FloatR,
337 /* has float insn direction bit. */
338 FloatD,
339 /* needs size prefix if in 32-bit mode */
340 Size16,
341 /* needs size prefix if in 16-bit mode */
342 Size32,
343 /* needs size prefix if in 64-bit mode */
344 Size64,
345 /* check register size. */
346 CheckRegSize,
347 /* instruction ignores operand size prefix and in Intel mode ignores
348 mnemonic size suffix check. */
349 IgnoreSize,
350 /* default insn size depends on mode */
351 DefaultSize,
352 /* b suffix on instruction illegal */
353 No_bSuf,
354 /* w suffix on instruction illegal */
355 No_wSuf,
356 /* l suffix on instruction illegal */
357 No_lSuf,
358 /* s suffix on instruction illegal */
359 No_sSuf,
360 /* q suffix on instruction illegal */
361 No_qSuf,
362 /* long double suffix on instruction illegal */
363 No_ldSuf,
364 /* instruction needs FWAIT */
365 FWait,
366 /* quick test for string instructions */
367 IsString,
368 /* quick test if branch instruction is MPX supported */
369 BNDPrefixOk,
370 /* quick test for lockable instructions */
371 IsLockable,
372 /* fake an extra reg operand for clr, imul and special register
373 processing for some instructions. */
374 RegKludge,
375 /* The first operand must be xmm0 */
376 FirstXmm0,
377 /* An implicit xmm0 as the first operand */
378 Implicit1stXmm0,
379 /* The HLE prefix is OK:
380 1. With a LOCK prefix.
381 2. With or without a LOCK prefix.
382 3. With a RELEASE (0xf3) prefix.
383 */
384 #define HLEPrefixNone 0
385 #define HLEPrefixLock 1
386 #define HLEPrefixAny 2
387 #define HLEPrefixRelease 3
388 HLEPrefixOk,
389 /* An instruction on which a "rep" prefix is acceptable. */
390 RepPrefixOk,
391 /* Convert to DWORD */
392 ToDword,
393 /* Convert to QWORD */
394 ToQword,
395 /* Address prefix changes operand 0 */
396 AddrPrefixOp0,
397 /* opcode is a prefix */
398 IsPrefix,
399 /* instruction has extension in 8 bit imm */
400 ImmExt,
401 /* instruction don't need Rex64 prefix. */
402 NoRex64,
403 /* instruction require Rex64 prefix. */
404 Rex64,
405 /* deprecated fp insn, gets a warning */
406 Ugh,
407 /* insn has VEX prefix:
408 1: 128bit VEX prefix.
409 2: 256bit VEX prefix.
410 3: Scalar VEX prefix.
411 */
412 #define VEX128 1
413 #define VEX256 2
414 #define VEXScalar 3
415 Vex,
416 /* How to encode VEX.vvvv:
417 0: VEX.vvvv must be 1111b.
418 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
419 the content of source registers will be preserved.
420 VEX.DDS. The second register operand is encoded in VEX.vvvv
421 where the content of first source register will be overwritten
422 by the result.
423 VEX.NDD2. The second destination register operand is encoded in
424 VEX.vvvv for instructions with 2 destination register operands.
425 For assembler, there are no difference between VEX.NDS, VEX.DDS
426 and VEX.NDD2.
427 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
428 instructions with 1 destination register operand.
429 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
430 of the operands can access a memory location.
431 */
432 #define VEXXDS 1
433 #define VEXNDD 2
434 #define VEXLWP 3
435 VexVVVV,
436 /* How the VEX.W bit is used:
437 0: Set by the REX.W bit.
438 1: VEX.W0. Should always be 0.
439 2: VEX.W1. Should always be 1.
440 */
441 #define VEXW0 1
442 #define VEXW1 2
443 VexW,
444 /* VEX opcode prefix:
445 0: VEX 0x0F opcode prefix.
446 1: VEX 0x0F38 opcode prefix.
447 2: VEX 0x0F3A opcode prefix
448 3: XOP 0x08 opcode prefix.
449 4: XOP 0x09 opcode prefix
450 5: XOP 0x0A opcode prefix.
451 */
452 #define VEX0F 0
453 #define VEX0F38 1
454 #define VEX0F3A 2
455 #define XOP08 3
456 #define XOP09 4
457 #define XOP0A 5
458 VexOpcode,
459 /* number of VEX source operands:
460 0: <= 2 source operands.
461 1: 2 XOP source operands.
462 2: 3 source operands.
463 */
464 #define XOP2SOURCES 1
465 #define VEX3SOURCES 2
466 VexSources,
467 /* instruction has VEX 8 bit imm */
468 VexImmExt,
469 /* Instruction with vector SIB byte:
470 1: 128bit vector register.
471 2: 256bit vector register.
472 3: 512bit vector register.
473 */
474 #define VecSIB128 1
475 #define VecSIB256 2
476 #define VecSIB512 3
477 VecSIB,
478 /* SSE to AVX support required */
479 SSE2AVX,
480 /* No AVX equivalent */
481 NoAVX,
482
483 /* insn has EVEX prefix:
484 1: 512bit EVEX prefix.
485 2: 128bit EVEX prefix.
486 3: 256bit EVEX prefix.
487 4: Length-ignored (LIG) EVEX prefix.
488 */
489 #define EVEX512 1
490 #define EVEX128 2
491 #define EVEX256 3
492 #define EVEXLIG 4
493 EVex,
494
495 /* AVX512 masking support:
496 1: Zeroing-masking.
497 2: Merging-masking.
498 3: Both zeroing and merging masking.
499 */
500 #define ZEROING_MASKING 1
501 #define MERGING_MASKING 2
502 #define BOTH_MASKING 3
503 Masking,
504
505 /* Input element size of vector insn:
506 0: 32bit.
507 1: 64bit.
508 */
509 VecESize,
510
511 /* Broadcast factor.
512 0: No broadcast.
513 1: 1to16 broadcast.
514 2: 1to8 broadcast.
515 */
516 #define NO_BROADCAST 0
517 #define BROADCAST_1TO16 1
518 #define BROADCAST_1TO8 2
519 #define BROADCAST_1TO4 3
520 #define BROADCAST_1TO2 4
521 Broadcast,
522
523 /* Static rounding control is supported. */
524 StaticRounding,
525
526 /* Supress All Exceptions is supported. */
527 SAE,
528
529 /* Copressed Disp8*N attribute. */
530 Disp8MemShift,
531
532 /* Default mask isn't allowed. */
533 NoDefMask,
534
535 /* Compatible with old (<= 2.8.1) versions of gcc */
536 OldGcc,
537 /* AT&T mnemonic. */
538 ATTMnemonic,
539 /* AT&T syntax. */
540 ATTSyntax,
541 /* Intel syntax. */
542 IntelSyntax,
543 /* The last bitfield in i386_opcode_modifier. */
544 Opcode_Modifier_Max
545 };
546
547 typedef struct i386_opcode_modifier
548 {
549 unsigned int d:1;
550 unsigned int w:1;
551 unsigned int s:1;
552 unsigned int modrm:1;
553 unsigned int shortform:1;
554 unsigned int jump:1;
555 unsigned int jumpdword:1;
556 unsigned int jumpbyte:1;
557 unsigned int jumpintersegment:1;
558 unsigned int floatmf:1;
559 unsigned int floatr:1;
560 unsigned int floatd:1;
561 unsigned int size16:1;
562 unsigned int size32:1;
563 unsigned int size64:1;
564 unsigned int checkregsize:1;
565 unsigned int ignoresize:1;
566 unsigned int defaultsize:1;
567 unsigned int no_bsuf:1;
568 unsigned int no_wsuf:1;
569 unsigned int no_lsuf:1;
570 unsigned int no_ssuf:1;
571 unsigned int no_qsuf:1;
572 unsigned int no_ldsuf:1;
573 unsigned int fwait:1;
574 unsigned int isstring:1;
575 unsigned int bndprefixok:1;
576 unsigned int islockable:1;
577 unsigned int regkludge:1;
578 unsigned int firstxmm0:1;
579 unsigned int implicit1stxmm0:1;
580 unsigned int hleprefixok:2;
581 unsigned int repprefixok:1;
582 unsigned int todword:1;
583 unsigned int toqword:1;
584 unsigned int addrprefixop0:1;
585 unsigned int isprefix:1;
586 unsigned int immext:1;
587 unsigned int norex64:1;
588 unsigned int rex64:1;
589 unsigned int ugh:1;
590 unsigned int vex:2;
591 unsigned int vexvvvv:2;
592 unsigned int vexw:2;
593 unsigned int vexopcode:3;
594 unsigned int vexsources:2;
595 unsigned int veximmext:1;
596 unsigned int vecsib:2;
597 unsigned int sse2avx:1;
598 unsigned int noavx:1;
599 unsigned int evex:3;
600 unsigned int masking:2;
601 unsigned int vecesize:1;
602 unsigned int broadcast:3;
603 unsigned int staticrounding:1;
604 unsigned int sae:1;
605 unsigned int disp8memshift:3;
606 unsigned int nodefmask:1;
607 unsigned int oldgcc:1;
608 unsigned int attmnemonic:1;
609 unsigned int attsyntax:1;
610 unsigned int intelsyntax:1;
611 } i386_opcode_modifier;
612
613 /* Position of operand_type bits. */
614
615 enum
616 {
617 /* 8bit register */
618 Reg8 = 0,
619 /* 16bit register */
620 Reg16,
621 /* 32bit register */
622 Reg32,
623 /* 64bit register */
624 Reg64,
625 /* Floating pointer stack register */
626 FloatReg,
627 /* MMX register */
628 RegMMX,
629 /* SSE register */
630 RegXMM,
631 /* AVX registers */
632 RegYMM,
633 /* AVX512 registers */
634 RegZMM,
635 /* Vector Mask registers */
636 RegMask,
637 /* Control register */
638 Control,
639 /* Debug register */
640 Debug,
641 /* Test register */
642 Test,
643 /* 2 bit segment register */
644 SReg2,
645 /* 3 bit segment register */
646 SReg3,
647 /* 1 bit immediate */
648 Imm1,
649 /* 8 bit immediate */
650 Imm8,
651 /* 8 bit immediate sign extended */
652 Imm8S,
653 /* 16 bit immediate */
654 Imm16,
655 /* 32 bit immediate */
656 Imm32,
657 /* 32 bit immediate sign extended */
658 Imm32S,
659 /* 64 bit immediate */
660 Imm64,
661 /* 8bit/16bit/32bit displacements are used in different ways,
662 depending on the instruction. For jumps, they specify the
663 size of the PC relative displacement, for instructions with
664 memory operand, they specify the size of the offset relative
665 to the base register, and for instructions with memory offset
666 such as `mov 1234,%al' they specify the size of the offset
667 relative to the segment base. */
668 /* 8 bit displacement */
669 Disp8,
670 /* 16 bit displacement */
671 Disp16,
672 /* 32 bit displacement */
673 Disp32,
674 /* 32 bit signed displacement */
675 Disp32S,
676 /* 64 bit displacement */
677 Disp64,
678 /* Accumulator %al/%ax/%eax/%rax */
679 Acc,
680 /* Floating pointer top stack register %st(0) */
681 FloatAcc,
682 /* Register which can be used for base or index in memory operand. */
683 BaseIndex,
684 /* Register to hold in/out port addr = dx */
685 InOutPortReg,
686 /* Register to hold shift count = cl */
687 ShiftCount,
688 /* Absolute address for jump. */
689 JumpAbsolute,
690 /* String insn operand with fixed es segment */
691 EsSeg,
692 /* RegMem is for instructions with a modrm byte where the register
693 destination operand should be encoded in the mod and regmem fields.
694 Normally, it will be encoded in the reg field. We add a RegMem
695 flag to the destination register operand to indicate that it should
696 be encoded in the regmem field. */
697 RegMem,
698 /* Memory. */
699 Mem,
700 /* BYTE memory. */
701 Byte,
702 /* WORD memory. 2 byte */
703 Word,
704 /* DWORD memory. 4 byte */
705 Dword,
706 /* FWORD memory. 6 byte */
707 Fword,
708 /* QWORD memory. 8 byte */
709 Qword,
710 /* TBYTE memory. 10 byte */
711 Tbyte,
712 /* XMMWORD memory. */
713 Xmmword,
714 /* YMMWORD memory. */
715 Ymmword,
716 /* ZMMWORD memory. */
717 Zmmword,
718 /* Unspecified memory size. */
719 Unspecified,
720 /* Any memory size. */
721 Anysize,
722
723 /* Vector 4 bit immediate. */
724 Vec_Imm4,
725
726 /* Bound register. */
727 RegBND,
728
729 /* Vector 8bit displacement */
730 Vec_Disp8,
731
732 /* The last bitfield in i386_operand_type. */
733 OTMax
734 };
735
736 #define OTNumOfUints \
737 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
738 #define OTNumOfBits \
739 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
740
741 /* If you get a compiler error for zero width of the unused field,
742 comment it out. */
743 #define OTUnused (OTMax + 1)
744
745 typedef union i386_operand_type
746 {
747 struct
748 {
749 unsigned int reg8:1;
750 unsigned int reg16:1;
751 unsigned int reg32:1;
752 unsigned int reg64:1;
753 unsigned int floatreg:1;
754 unsigned int regmmx:1;
755 unsigned int regxmm:1;
756 unsigned int regymm:1;
757 unsigned int regzmm:1;
758 unsigned int regmask:1;
759 unsigned int control:1;
760 unsigned int debug:1;
761 unsigned int test:1;
762 unsigned int sreg2:1;
763 unsigned int sreg3:1;
764 unsigned int imm1:1;
765 unsigned int imm8:1;
766 unsigned int imm8s:1;
767 unsigned int imm16:1;
768 unsigned int imm32:1;
769 unsigned int imm32s:1;
770 unsigned int imm64:1;
771 unsigned int disp8:1;
772 unsigned int disp16:1;
773 unsigned int disp32:1;
774 unsigned int disp32s:1;
775 unsigned int disp64:1;
776 unsigned int acc:1;
777 unsigned int floatacc:1;
778 unsigned int baseindex:1;
779 unsigned int inoutportreg:1;
780 unsigned int shiftcount:1;
781 unsigned int jumpabsolute:1;
782 unsigned int esseg:1;
783 unsigned int regmem:1;
784 unsigned int mem:1;
785 unsigned int byte:1;
786 unsigned int word:1;
787 unsigned int dword:1;
788 unsigned int fword:1;
789 unsigned int qword:1;
790 unsigned int tbyte:1;
791 unsigned int xmmword:1;
792 unsigned int ymmword:1;
793 unsigned int zmmword:1;
794 unsigned int unspecified:1;
795 unsigned int anysize:1;
796 unsigned int vec_imm4:1;
797 unsigned int regbnd:1;
798 unsigned int vec_disp8:1;
799 #ifdef OTUnused
800 unsigned int unused:(OTNumOfBits - OTUnused);
801 #endif
802 } bitfield;
803 unsigned int array[OTNumOfUints];
804 } i386_operand_type;
805
806 typedef struct insn_template
807 {
808 /* instruction name sans width suffix ("mov" for movl insns) */
809 char *name;
810
811 /* how many operands */
812 unsigned int operands;
813
814 /* base_opcode is the fundamental opcode byte without optional
815 prefix(es). */
816 unsigned int base_opcode;
817 #define Opcode_D 0x2 /* Direction bit:
818 set if Reg --> Regmem;
819 unset if Regmem --> Reg. */
820 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
821 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
822
823 /* extension_opcode is the 3 bit extension for group <n> insns.
824 This field is also used to store the 8-bit opcode suffix for the
825 AMD 3DNow! instructions.
826 If this template has no extension opcode (the usual case) use None
827 Instructions */
828 unsigned int extension_opcode;
829 #define None 0xffff /* If no extension_opcode is possible. */
830
831 /* Opcode length. */
832 unsigned char opcode_length;
833
834 /* cpu feature flags */
835 i386_cpu_flags cpu_flags;
836
837 /* the bits in opcode_modifier are used to generate the final opcode from
838 the base_opcode. These bits also are used to detect alternate forms of
839 the same instruction */
840 i386_opcode_modifier opcode_modifier;
841
842 /* operand_types[i] describes the type of operand i. This is made
843 by OR'ing together all of the possible type masks. (e.g.
844 'operand_types[i] = Reg|Imm' specifies that operand i can be
845 either a register or an immediate operand. */
846 i386_operand_type operand_types[MAX_OPERANDS];
847 }
848 insn_template;
849
850 extern const insn_template i386_optab[];
851
852 /* these are for register name --> number & type hash lookup */
853 typedef struct
854 {
855 char *reg_name;
856 i386_operand_type reg_type;
857 unsigned char reg_flags;
858 #define RegRex 0x1 /* Extended register. */
859 #define RegRex64 0x2 /* Extended 8 bit register. */
860 #define RegVRex 0x4 /* Extended vector register. */
861 unsigned char reg_num;
862 #define RegRip ((unsigned char ) ~0)
863 #define RegEip (RegRip - 1)
864 /* EIZ and RIZ are fake index registers. */
865 #define RegEiz (RegEip - 1)
866 #define RegRiz (RegEiz - 1)
867 /* FLAT is a fake segment register (Intel mode). */
868 #define RegFlat ((unsigned char) ~0)
869 signed char dw2_regnum[2];
870 #define Dw2Inval (-1)
871 }
872 reg_entry;
873
874 /* Entries in i386_regtab. */
875 #define REGNAM_AL 1
876 #define REGNAM_AX 25
877 #define REGNAM_EAX 41
878
879 extern const reg_entry i386_regtab[];
880 extern const unsigned int i386_regtab_size;
881
882 typedef struct
883 {
884 char *seg_name;
885 unsigned int seg_prefix;
886 }
887 seg_entry;
888
889 extern const seg_entry cs;
890 extern const seg_entry ds;
891 extern const seg_entry ss;
892 extern const seg_entry es;
893 extern const seg_entry fs;
894 extern const seg_entry gs;
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