opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* ABM New Instructions required */
  91   CpuABM,
  92   /* SSE4.1 support required */
  93   CpuSSE4_1,
  94   /* SSE4.2 support required */
  95   CpuSSE4_2,
  96   /* AVX support required */
  97   CpuAVX,
  98   /* AVX2 support required */
  99   CpuAVX2,
 100   /* Intel AVX-512 Foundation Instructions support required */
 101   CpuAVX512F,
 102   /* Intel AVX-512 Conflict Detection Instructions support required */
 103   CpuAVX512CD,
 104   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 105      required */
 106   CpuAVX512ER,
 107   /* Intel AVX-512 Prefetch Instructions support required */
 108   CpuAVX512PF,
 109   /* Intel AVX-512 VL Instructions support required.  */
 110   CpuAVX512VL,
 111   /* Intel AVX-512 DQ Instructions support required.  */
 112   CpuAVX512DQ,
 113   /* Intel AVX-512 BW Instructions support required.  */
 114   CpuAVX512BW,
 115   /* Intel L1OM support required */
 116   CpuL1OM,
 117   /* Intel K1OM support required */
 118   CpuK1OM,
 119   /* Intel IAMCU support required */
 120   CpuIAMCU,
 121   /* Xsave/xrstor New Instructions support required */
 122   CpuXsave,
 123   /* Xsaveopt New Instructions support required */
 124   CpuXsaveopt,
 125   /* AES support required */
 126   CpuAES,
 127   /* PCLMUL support required */
 128   CpuPCLMUL,
 129   /* FMA support required */
 130   CpuFMA,
 131   /* FMA4 support required */
 132   CpuFMA4,
 133   /* XOP support required */
 134   CpuXOP,
 135   /* LWP support required */
 136   CpuLWP,
 137   /* BMI support required */
 138   CpuBMI,
 139   /* TBM support required */
 140   CpuTBM,
 141   /* MOVBE Instruction support required */
 142   CpuMovbe,
 143   /* CMPXCHG16B instruction support required.  */
 144   CpuCX16,
 145   /* EPT Instructions required */
 146   CpuEPT,
 147   /* RDTSCP Instruction support required */
 148   CpuRdtscp,
 149   /* FSGSBASE Instructions required */
 150   CpuFSGSBase,
 151   /* RDRND Instructions required */
 152   CpuRdRnd,
 153   /* F16C Instructions required */
 154   CpuF16C,
 155   /* Intel BMI2 support required */
 156   CpuBMI2,
 157   /* LZCNT support required */
 158   CpuLZCNT,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 212   CpuAVX512_VP2INTERSECT,
 213   /* mwaitx instruction required */
 214   CpuMWAITX,
 215   /* Clzero instruction required */
 216   CpuCLZERO,
 217   /* OSPKE instruction required */
 218   CpuOSPKE,
 219   /* RDPID instruction required */
 220   CpuRDPID,
 221   /* PTWRITE instruction required */
 222   CpuPTWRITE,
 223   /* CET instructions support required */
 224   CpuIBT,
 225   CpuSHSTK,
 226   /* GFNI instructions required */
 227   CpuGFNI,
 228   /* VAES instructions required */
 229   CpuVAES,
 230   /* VPCLMULQDQ instructions required */
 231   CpuVPCLMULQDQ,
 232   /* WBNOINVD instructions required */
 233   CpuWBNOINVD,
 234   /* PCONFIG instructions required */
 235   CpuPCONFIG,
 236   /* WAITPKG instructions required */
 237   CpuWAITPKG,
 238   /* CLDEMOTE instruction required */
 239   CpuCLDEMOTE,
 240   /* MOVDIRI instruction support required */
 241   CpuMOVDIRI,
 242   /* MOVDIRR64B instruction required */
 243   CpuMOVDIR64B,
 244   /* ENQCMD instruction required */
 245   CpuENQCMD,
 246   /* 64bit support required  */
 247   Cpu64,
 248   /* Not supported in the 64bit mode  */
 249   CpuNo64,
 250   /* The last bitfield in i386_cpu_flags.  */
 251   CpuMax = CpuNo64
 252 };
 253
 254 #define CpuNumOfUints \
 255   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 256 #define CpuNumOfBits \
 257   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 258
 259 /* If you get a compiler error for zero width of the unused field,
 260    comment it out.  */
 261 #define CpuUnused       (CpuMax + 1)
 262
 263 /* We can check if an instruction is available with array instead
 264    of bitfield. */
 265 typedef union i386_cpu_flags
 266 {
 267   struct
 268     {
 269       unsigned int cpui186:1;
 270       unsigned int cpui286:1;
 271       unsigned int cpui386:1;
 272       unsigned int cpui486:1;
 273       unsigned int cpui586:1;
 274       unsigned int cpui686:1;
 275       unsigned int cpucmov:1;
 276       unsigned int cpufxsr:1;
 277       unsigned int cpuclflush:1;
 278       unsigned int cpunop:1;
 279       unsigned int cpusyscall:1;
 280       unsigned int cpu8087:1;
 281       unsigned int cpu287:1;
 282       unsigned int cpu387:1;
 283       unsigned int cpu687:1;
 284       unsigned int cpufisttp:1;
 285       unsigned int cpummx:1;
 286       unsigned int cpusse:1;
 287       unsigned int cpusse2:1;
 288       unsigned int cpua3dnow:1;
 289       unsigned int cpua3dnowa:1;
 290       unsigned int cpusse3:1;
 291       unsigned int cpupadlock:1;
 292       unsigned int cpusvme:1;
 293       unsigned int cpuvmx:1;
 294       unsigned int cpusmx:1;
 295       unsigned int cpussse3:1;
 296       unsigned int cpusse4a:1;
 297       unsigned int cpuabm:1;
 298       unsigned int cpusse4_1:1;
 299       unsigned int cpusse4_2:1;
 300       unsigned int cpuavx:1;
 301       unsigned int cpuavx2:1;
 302       unsigned int cpuavx512f:1;
 303       unsigned int cpuavx512cd:1;
 304       unsigned int cpuavx512er:1;
 305       unsigned int cpuavx512pf:1;
 306       unsigned int cpuavx512vl:1;
 307       unsigned int cpuavx512dq:1;
 308       unsigned int cpuavx512bw:1;
 309       unsigned int cpul1om:1;
 310       unsigned int cpuk1om:1;
 311       unsigned int cpuiamcu:1;
 312       unsigned int cpuxsave:1;
 313       unsigned int cpuxsaveopt:1;
 314       unsigned int cpuaes:1;
 315       unsigned int cpupclmul:1;
 316       unsigned int cpufma:1;
 317       unsigned int cpufma4:1;
 318       unsigned int cpuxop:1;
 319       unsigned int cpulwp:1;
 320       unsigned int cpubmi:1;
 321       unsigned int cputbm:1;
 322       unsigned int cpumovbe:1;
 323       unsigned int cpucx16:1;
 324       unsigned int cpuept:1;
 325       unsigned int cpurdtscp:1;
 326       unsigned int cpufsgsbase:1;
 327       unsigned int cpurdrnd:1;
 328       unsigned int cpuf16c:1;
 329       unsigned int cpubmi2:1;
 330       unsigned int cpulzcnt:1;
 331       unsigned int cpuhle:1;
 332       unsigned int cpurtm:1;
 333       unsigned int cpuinvpcid:1;
 334       unsigned int cpuvmfunc:1;
 335       unsigned int cpumpx:1;
 336       unsigned int cpulm:1;
 337       unsigned int cpurdseed:1;
 338       unsigned int cpuadx:1;
 339       unsigned int cpuprfchw:1;
 340       unsigned int cpusmap:1;
 341       unsigned int cpusha:1;
 342       unsigned int cpuclflushopt:1;
 343       unsigned int cpuxsaves:1;
 344       unsigned int cpuxsavec:1;
 345       unsigned int cpuprefetchwt1:1;
 346       unsigned int cpuse1:1;
 347       unsigned int cpuclwb:1;
 348       unsigned int cpuavx512ifma:1;
 349       unsigned int cpuavx512vbmi:1;
 350       unsigned int cpuavx512_4fmaps:1;
 351       unsigned int cpuavx512_4vnniw:1;
 352       unsigned int cpuavx512_vpopcntdq:1;
 353       unsigned int cpuavx512_vbmi2:1;
 354       unsigned int cpuavx512_vnni:1;
 355       unsigned int cpuavx512_bitalg:1;
 356       unsigned int cpuavx512_bf16:1;
 357       unsigned int cpuavx512_vp2intersect:1;
 358       unsigned int cpumwaitx:1;
 359       unsigned int cpuclzero:1;
 360       unsigned int cpuospke:1;
 361       unsigned int cpurdpid:1;
 362       unsigned int cpuptwrite:1;
 363       unsigned int cpuibt:1;
 364       unsigned int cpushstk:1;
 365       unsigned int cpugfni:1;
 366       unsigned int cpuvaes:1;
 367       unsigned int cpuvpclmulqdq:1;
 368       unsigned int cpuwbnoinvd:1;
 369       unsigned int cpupconfig:1;
 370       unsigned int cpuwaitpkg:1;
 371       unsigned int cpucldemote:1;
 372       unsigned int cpumovdiri:1;
 373       unsigned int cpumovdir64b:1;
 374       unsigned int cpuenqcmd:1;
 375       unsigned int cpu64:1;
 376       unsigned int cpuno64:1;
 377 #ifdef CpuUnused
 378       unsigned int unused:(CpuNumOfBits - CpuUnused);
 379 #endif
 380     } bitfield;
 381   unsigned int array[CpuNumOfUints];
 382 } i386_cpu_flags;
 383
 384 /* Position of opcode_modifier bits.  */
 385
 386 enum
 387 {
 388   /* has direction bit. */
 389   D = 0,
 390   /* set if operands can be words or dwords encoded the canonical way */
 391   W,
 392   /* load form instruction. Must be placed before store form.  */
 393   Load,
 394   /* insn has a modrm byte. */
 395   Modrm,
 396   /* register is in low 3 bits of opcode */
 397   ShortForm,
 398   /* special case for jump insns.  */
 399   Jump,
 400   /* call and jump */
 401   JumpDword,
 402   /* loop and jecxz */
 403   JumpByte,
 404   /* special case for intersegment leaps/calls */
 405   JumpInterSegment,
 406   /* FP insn memory format bit, sized by 0x4 */
 407   FloatMF,
 408   /* src/dest swap for floats. */
 409   FloatR,
 410   /* needs size prefix if in 32-bit mode */
 411 #define SIZE16 1
 412   /* needs size prefix if in 16-bit mode */
 413 #define SIZE32 2
 414   /* needs size prefix if in 64-bit mode */
 415 #define SIZE64 3
 416   Size,
 417   /* check register size.  */
 418   CheckRegSize,
 419   /* instruction ignores operand size prefix and in Intel mode ignores
 420      mnemonic size suffix check.  */
 421   IgnoreSize,
 422   /* default insn size depends on mode */
 423   DefaultSize,
 424   /* b suffix on instruction illegal */
 425   No_bSuf,
 426   /* w suffix on instruction illegal */
 427   No_wSuf,
 428   /* l suffix on instruction illegal */
 429   No_lSuf,
 430   /* s suffix on instruction illegal */
 431   No_sSuf,
 432   /* q suffix on instruction illegal */
 433   No_qSuf,
 434   /* long double suffix on instruction illegal */
 435   No_ldSuf,
 436   /* instruction needs FWAIT */
 437   FWait,
 438   /* quick test for string instructions */
 439   IsString,
 440   /* quick test if branch instruction is MPX supported */
 441   BNDPrefixOk,
 442   /* quick test if NOTRACK prefix is supported */
 443   NoTrackPrefixOk,
 444   /* quick test for lockable instructions */
 445   IsLockable,
 446   /* fake an extra reg operand for clr, imul and special register
 447      processing for some instructions.  */
 448   RegKludge,
 449   /* An implicit xmm0 as the first operand */
 450   Implicit1stXmm0,
 451   /* The HLE prefix is OK:
 452      1. With a LOCK prefix.
 453      2. With or without a LOCK prefix.
 454      3. With a RELEASE (0xf3) prefix.
 455    */
 456 #define HLEPrefixNone           0
 457 #define HLEPrefixLock           1
 458 #define HLEPrefixAny            2
 459 #define HLEPrefixRelease        3
 460   HLEPrefixOk,
 461   /* An instruction on which a "rep" prefix is acceptable.  */
 462   RepPrefixOk,
 463   /* Convert to DWORD */
 464   ToDword,
 465   /* Convert to QWORD */
 466   ToQword,
 467   /* Address prefix changes register operand */
 468   AddrPrefixOpReg,
 469   /* opcode is a prefix */
 470   IsPrefix,
 471   /* instruction has extension in 8 bit imm */
 472   ImmExt,
 473   /* instruction don't need Rex64 prefix.  */
 474   NoRex64,
 475   /* instruction require Rex64 prefix.  */
 476   Rex64,
 477   /* deprecated fp insn, gets a warning */
 478   Ugh,
 479   /* insn has VEX prefix:
 480         1: 128bit VEX prefix (or operand dependent).
 481         2: 256bit VEX prefix.
 482         3: Scalar VEX prefix.
 483    */
 484 #define VEX128          1
 485 #define VEX256          2
 486 #define VEXScalar       3
 487   Vex,
 488   /* How to encode VEX.vvvv:
 489      0: VEX.vvvv must be 1111b.
 490      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 491         the content of source registers will be preserved.
 492         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 493         where the content of first source register will be overwritten
 494         by the result.
 495         VEX.NDD2.  The second destination register operand is encoded in
 496         VEX.vvvv for instructions with 2 destination register operands.
 497         For assembler, there are no difference between VEX.NDS, VEX.DDS
 498         and VEX.NDD2.
 499      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 500      instructions with 1 destination register operand.
 501      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 502         of the operands can access a memory location.
 503    */
 504 #define VEXXDS  1
 505 #define VEXNDD  2
 506 #define VEXLWP  3
 507   VexVVVV,
 508   /* How the VEX.W bit is used:
 509      0: Set by the REX.W bit.
 510      1: VEX.W0.  Should always be 0.
 511      2: VEX.W1.  Should always be 1.
 512      3: VEX.WIG. The VEX.W bit is ignored.
 513    */
 514 #define VEXW0   1
 515 #define VEXW1   2
 516 #define VEXWIG  3
 517   VexW,
 518   /* VEX opcode prefix:
 519      0: VEX 0x0F opcode prefix.
 520      1: VEX 0x0F38 opcode prefix.
 521      2: VEX 0x0F3A opcode prefix
 522      3: XOP 0x08 opcode prefix.
 523      4: XOP 0x09 opcode prefix
 524      5: XOP 0x0A opcode prefix.
 525    */
 526 #define VEX0F           0
 527 #define VEX0F38         1
 528 #define VEX0F3A         2
 529 #define XOP08           3
 530 #define XOP09           4
 531 #define XOP0A           5
 532   VexOpcode,
 533   /* number of VEX source operands:
 534      0: <= 2 source operands.
 535      1: 2 XOP source operands.
 536      2: 3 source operands.
 537    */
 538 #define XOP2SOURCES     1
 539 #define VEX3SOURCES     2
 540   VexSources,
 541   /* Instruction with vector SIB byte:
 542         1: 128bit vector register.
 543         2: 256bit vector register.
 544         3: 512bit vector register.
 545    */
 546 #define VecSIB128       1
 547 #define VecSIB256       2
 548 #define VecSIB512       3
 549   VecSIB,
 550   /* SSE to AVX support required */
 551   SSE2AVX,
 552   /* No AVX equivalent */
 553   NoAVX,
 554
 555   /* insn has EVEX prefix:
 556         1: 512bit EVEX prefix.
 557         2: 128bit EVEX prefix.
 558         3: 256bit EVEX prefix.
 559         4: Length-ignored (LIG) EVEX prefix.
 560         5: Length determined from actual operands.
 561    */
 562 #define EVEX512                1
 563 #define EVEX128                2
 564 #define EVEX256                3
 565 #define EVEXLIG                4
 566 #define EVEXDYN                5
 567   EVex,
 568
 569   /* AVX512 masking support:
 570         1: Zeroing or merging masking depending on operands.
 571         2: Merging-masking.
 572         3: Both zeroing and merging masking.
 573    */
 574 #define DYNAMIC_MASKING 1
 575 #define MERGING_MASKING 2
 576 #define BOTH_MASKING    3
 577   Masking,
 578
 579   /* AVX512 broadcast support.  The number of bytes to broadcast is
 580      1 << (Broadcast - 1):
 581         1: Byte broadcast.
 582         2: Word broadcast.
 583         3: Dword broadcast.
 584         4: Qword broadcast.
 585    */
 586 #define BYTE_BROADCAST  1
 587 #define WORD_BROADCAST  2
 588 #define DWORD_BROADCAST 3
 589 #define QWORD_BROADCAST 4
 590   Broadcast,
 591
 592   /* Static rounding control is supported.  */
 593   StaticRounding,
 594
 595   /* Supress All Exceptions is supported.  */
 596   SAE,
 597
 598   /* Compressed Disp8*N attribute.  */
 599 #define DISP8_SHIFT_VL 7
 600   Disp8MemShift,
 601
 602   /* Default mask isn't allowed.  */
 603   NoDefMask,
 604
 605   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 606      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 607    */
 608   ImplicitQuadGroup,
 609
 610   /* Support encoding optimization.  */
 611   Optimize,
 612
 613   /* AT&T mnemonic.  */
 614   ATTMnemonic,
 615   /* AT&T syntax.  */
 616   ATTSyntax,
 617   /* Intel syntax.  */
 618   IntelSyntax,
 619   /* AMD64.  */
 620   AMD64,
 621   /* Intel64.  */
 622   Intel64,
 623   /* The last bitfield in i386_opcode_modifier.  */
 624   Opcode_Modifier_Max
 625 };
 626
 627 typedef struct i386_opcode_modifier
 628 {
 629   unsigned int d:1;
 630   unsigned int w:1;
 631   unsigned int load:1;
 632   unsigned int modrm:1;
 633   unsigned int shortform:1;
 634   unsigned int jump:1;
 635   unsigned int jumpdword:1;
 636   unsigned int jumpbyte:1;
 637   unsigned int jumpintersegment:1;
 638   unsigned int floatmf:1;
 639   unsigned int floatr:1;
 640   unsigned int size:2;
 641   unsigned int checkregsize:1;
 642   unsigned int ignoresize:1;
 643   unsigned int defaultsize:1;
 644   unsigned int no_bsuf:1;
 645   unsigned int no_wsuf:1;
 646   unsigned int no_lsuf:1;
 647   unsigned int no_ssuf:1;
 648   unsigned int no_qsuf:1;
 649   unsigned int no_ldsuf:1;
 650   unsigned int fwait:1;
 651   unsigned int isstring:1;
 652   unsigned int bndprefixok:1;
 653   unsigned int notrackprefixok:1;
 654   unsigned int islockable:1;
 655   unsigned int regkludge:1;
 656   unsigned int implicit1stxmm0:1;
 657   unsigned int hleprefixok:2;
 658   unsigned int repprefixok:1;
 659   unsigned int todword:1;
 660   unsigned int toqword:1;
 661   unsigned int addrprefixopreg:1;
 662   unsigned int isprefix:1;
 663   unsigned int immext:1;
 664   unsigned int norex64:1;
 665   unsigned int rex64:1;
 666   unsigned int ugh:1;
 667   unsigned int vex:2;
 668   unsigned int vexvvvv:2;
 669   unsigned int vexw:2;
 670   unsigned int vexopcode:3;
 671   unsigned int vexsources:2;
 672   unsigned int vecsib:2;
 673   unsigned int sse2avx:1;
 674   unsigned int noavx:1;
 675   unsigned int evex:3;
 676   unsigned int masking:2;
 677   unsigned int broadcast:3;
 678   unsigned int staticrounding:1;
 679   unsigned int sae:1;
 680   unsigned int disp8memshift:3;
 681   unsigned int nodefmask:1;
 682   unsigned int implicitquadgroup:1;
 683   unsigned int optimize:1;
 684   unsigned int attmnemonic:1;
 685   unsigned int attsyntax:1;
 686   unsigned int intelsyntax:1;
 687   unsigned int amd64:1;
 688   unsigned int intel64:1;
 689 } i386_opcode_modifier;
 690
 691 /* Position of operand_type bits.  */
 692
 693 enum
 694 {
 695   /* Register (qualified by Byte, Word, etc) */
 696   Reg = 0,
 697   /* MMX register */
 698   RegMMX,
 699   /* Vector registers */
 700   RegSIMD,
 701   /* Vector Mask registers */
 702   RegMask,
 703   /* Control register */
 704   Control,
 705   /* Debug register */
 706   Debug,
 707   /* Test register */
 708   Test,
 709   /* Segment register */
 710   SReg,
 711   /* 1 bit immediate */
 712   Imm1,
 713   /* 8 bit immediate */
 714   Imm8,
 715   /* 8 bit immediate sign extended */
 716   Imm8S,
 717   /* 16 bit immediate */
 718   Imm16,
 719   /* 32 bit immediate */
 720   Imm32,
 721   /* 32 bit immediate sign extended */
 722   Imm32S,
 723   /* 64 bit immediate */
 724   Imm64,
 725   /* 8bit/16bit/32bit displacements are used in different ways,
 726      depending on the instruction.  For jumps, they specify the
 727      size of the PC relative displacement, for instructions with
 728      memory operand, they specify the size of the offset relative
 729      to the base register, and for instructions with memory offset
 730      such as `mov 1234,%al' they specify the size of the offset
 731      relative to the segment base.  */
 732   /* 8 bit displacement */
 733   Disp8,
 734   /* 16 bit displacement */
 735   Disp16,
 736   /* 32 bit displacement */
 737   Disp32,
 738   /* 32 bit signed displacement */
 739   Disp32S,
 740   /* 64 bit displacement */
 741   Disp64,
 742   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 743   Acc,
 744   /* Register which can be used for base or index in memory operand.  */
 745   BaseIndex,
 746   /* Register to hold in/out port addr = dx */
 747   InOutPortReg,
 748   /* Register to hold shift count = cl */
 749   ShiftCount,
 750   /* Absolute address for jump.  */
 751   JumpAbsolute,
 752   /* String insn operand with fixed es segment */
 753   EsSeg,
 754   /* RegMem is for instructions with a modrm byte where the register
 755      destination operand should be encoded in the mod and regmem fields.
 756      Normally, it will be encoded in the reg field. We add a RegMem
 757      flag to the destination register operand to indicate that it should
 758      be encoded in the regmem field.  */
 759   RegMem,
 760   /* Memory.  */
 761   Mem,
 762   /* BYTE size. */
 763   Byte,
 764   /* WORD size. 2 byte */
 765   Word,
 766   /* DWORD size. 4 byte */
 767   Dword,
 768   /* FWORD size. 6 byte */
 769   Fword,
 770   /* QWORD size. 8 byte */
 771   Qword,
 772   /* TBYTE size. 10 byte */
 773   Tbyte,
 774   /* XMMWORD size. */
 775   Xmmword,
 776   /* YMMWORD size. */
 777   Ymmword,
 778   /* ZMMWORD size.  */
 779   Zmmword,
 780   /* Unspecified memory size.  */
 781   Unspecified,
 782   /* Any memory size.  */
 783   Anysize,
 784
 785   /* Bound register.  */
 786   RegBND,
 787
 788   /* The number of bitfields in i386_operand_type.  */
 789   OTNum
 790 };
 791
 792 #define OTNumOfUints \
 793   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 794 #define OTNumOfBits \
 795   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 796
 797 /* If you get a compiler error for zero width of the unused field,
 798    comment it out.  */
 799 #define OTUnused                OTNum
 800
 801 typedef union i386_operand_type
 802 {
 803   struct
 804     {
 805       unsigned int reg:1;
 806       unsigned int regmmx:1;
 807       unsigned int regsimd:1;
 808       unsigned int regmask:1;
 809       unsigned int control:1;
 810       unsigned int debug:1;
 811       unsigned int test:1;
 812       unsigned int sreg:1;
 813       unsigned int imm1:1;
 814       unsigned int imm8:1;
 815       unsigned int imm8s:1;
 816       unsigned int imm16:1;
 817       unsigned int imm32:1;
 818       unsigned int imm32s:1;
 819       unsigned int imm64:1;
 820       unsigned int disp8:1;
 821       unsigned int disp16:1;
 822       unsigned int disp32:1;
 823       unsigned int disp32s:1;
 824       unsigned int disp64:1;
 825       unsigned int acc:1;
 826       unsigned int baseindex:1;
 827       unsigned int inoutportreg:1;
 828       unsigned int shiftcount:1;
 829       unsigned int jumpabsolute:1;
 830       unsigned int esseg:1;
 831       unsigned int regmem:1;
 832       unsigned int byte:1;
 833       unsigned int word:1;
 834       unsigned int dword:1;
 835       unsigned int fword:1;
 836       unsigned int qword:1;
 837       unsigned int tbyte:1;
 838       unsigned int xmmword:1;
 839       unsigned int ymmword:1;
 840       unsigned int zmmword:1;
 841       unsigned int unspecified:1;
 842       unsigned int anysize:1;
 843       unsigned int regbnd:1;
 844 #ifdef OTUnused
 845       unsigned int unused:(OTNumOfBits - OTUnused);
 846 #endif
 847     } bitfield;
 848   unsigned int array[OTNumOfUints];
 849 } i386_operand_type;
 850
 851 typedef struct insn_template
 852 {
 853   /* instruction name sans width suffix ("mov" for movl insns) */
 854   char *name;
 855
 856   /* how many operands */
 857   unsigned int operands;
 858
 859   /* base_opcode is the fundamental opcode byte without optional
 860      prefix(es).  */
 861   unsigned int base_opcode;
 862 #define Opcode_D        0x2 /* Direction bit:
 863                                set if Reg --> Regmem;
 864                                unset if Regmem --> Reg. */
 865 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 866 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 867 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 868 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 869
 870   /* extension_opcode is the 3 bit extension for group <n> insns.
 871      This field is also used to store the 8-bit opcode suffix for the
 872      AMD 3DNow! instructions.
 873      If this template has no extension opcode (the usual case) use None
 874      Instructions */
 875   unsigned int extension_opcode;
 876 #define None 0xffff             /* If no extension_opcode is possible.  */
 877
 878   /* Opcode length.  */
 879   unsigned char opcode_length;
 880
 881   /* cpu feature flags */
 882   i386_cpu_flags cpu_flags;
 883
 884   /* the bits in opcode_modifier are used to generate the final opcode from
 885      the base_opcode.  These bits also are used to detect alternate forms of
 886      the same instruction */
 887   i386_opcode_modifier opcode_modifier;
 888
 889   /* operand_types[i] describes the type of operand i.  This is made
 890      by OR'ing together all of the possible type masks.  (e.g.
 891      'operand_types[i] = Reg|Imm' specifies that operand i can be
 892      either a register or an immediate operand.  */
 893   i386_operand_type operand_types[MAX_OPERANDS];
 894 }
 895 insn_template;
 896
 897 extern const insn_template i386_optab[];
 898
 899 /* these are for register name --> number & type hash lookup */
 900 typedef struct
 901 {
 902   char *reg_name;
 903   i386_operand_type reg_type;
 904   unsigned char reg_flags;
 905 #define RegRex      0x1  /* Extended register.  */
 906 #define RegRex64    0x2  /* Extended 8 bit register.  */
 907 #define RegVRex     0x4  /* Extended vector register.  */
 908   unsigned char reg_num;
 909 #define RegIP   ((unsigned char ) ~0)
 910 /* EIZ and RIZ are fake index registers.  */
 911 #define RegIZ   (RegIP - 1)
 912 /* FLAT is a fake segment register (Intel mode).  */
 913 #define RegFlat     ((unsigned char) ~0)
 914   signed char dw2_regnum[2];
 915 #define Dw2Inval (-1)
 916 }
 917 reg_entry;
 918
 919 /* Entries in i386_regtab.  */
 920 #define REGNAM_AL 1
 921 #define REGNAM_AX 25
 922 #define REGNAM_EAX 41
 923
 924 extern const reg_entry i386_regtab[];
 925 extern const unsigned int i386_regtab_size;
 926
 927 typedef struct
 928 {
 929   char *seg_name;
 930   unsigned int seg_prefix;
 931 }
 932 seg_entry;
 933
 934 extern const seg_entry cs;
 935 extern const seg_entry ds;
 936 extern const seg_entry ss;
 937 extern const seg_entry es;
 938 extern const seg_entry fs;
 939 extern const seg_entry gs;