opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* mwaitx instruction required */
 200   CpuMWAITX,
 201   /* Clzero instruction required */
 202   CpuCLZERO,
 203   /* OSPKE instruction required */
 204   CpuOSPKE,
 205   /* RDPID instruction required */
 206   CpuRDPID,
 207   /* PTWRITE instruction required */
 208   CpuPTWRITE,
 209   /* MMX register support required */
 210   CpuRegMMX,
 211   /* XMM register support required */
 212   CpuRegXMM,
 213   /* YMM register support required */
 214   CpuRegYMM,
 215   /* ZMM register support required */
 216   CpuRegZMM,
 217   /* Mask register support required */
 218   CpuRegMask,
 219   /* 64bit support required  */
 220   Cpu64,
 221   /* Not supported in the 64bit mode  */
 222   CpuNo64,
 223   /* The last bitfield in i386_cpu_flags.  */
 224   CpuMax = CpuNo64
 225 };
 226
 227 #define CpuNumOfUints \
 228   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 229 #define CpuNumOfBits \
 230   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 231
 232 /* If you get a compiler error for zero width of the unused field,
 233    comment it out.  */
 234 #define CpuUnused       (CpuMax + 1)
 235
 236 /* We can check if an instruction is available with array instead
 237    of bitfield. */
 238 typedef union i386_cpu_flags
 239 {
 240   struct
 241     {
 242       unsigned int cpui186:1;
 243       unsigned int cpui286:1;
 244       unsigned int cpui386:1;
 245       unsigned int cpui486:1;
 246       unsigned int cpui586:1;
 247       unsigned int cpui686:1;
 248       unsigned int cpuclflush:1;
 249       unsigned int cpunop:1;
 250       unsigned int cpusyscall:1;
 251       unsigned int cpu8087:1;
 252       unsigned int cpu287:1;
 253       unsigned int cpu387:1;
 254       unsigned int cpu687:1;
 255       unsigned int cpufisttp:1;
 256       unsigned int cpummx:1;
 257       unsigned int cpusse:1;
 258       unsigned int cpusse2:1;
 259       unsigned int cpua3dnow:1;
 260       unsigned int cpua3dnowa:1;
 261       unsigned int cpusse3:1;
 262       unsigned int cpupadlock:1;
 263       unsigned int cpusvme:1;
 264       unsigned int cpuvmx:1;
 265       unsigned int cpusmx:1;
 266       unsigned int cpussse3:1;
 267       unsigned int cpusse4a:1;
 268       unsigned int cpuabm:1;
 269       unsigned int cpusse4_1:1;
 270       unsigned int cpusse4_2:1;
 271       unsigned int cpuavx:1;
 272       unsigned int cpuavx2:1;
 273       unsigned int cpuavx512f:1;
 274       unsigned int cpuavx512cd:1;
 275       unsigned int cpuavx512er:1;
 276       unsigned int cpuavx512pf:1;
 277       unsigned int cpuavx512vl:1;
 278       unsigned int cpuavx512dq:1;
 279       unsigned int cpuavx512bw:1;
 280       unsigned int cpul1om:1;
 281       unsigned int cpuk1om:1;
 282       unsigned int cpuiamcu:1;
 283       unsigned int cpuxsave:1;
 284       unsigned int cpuxsaveopt:1;
 285       unsigned int cpuaes:1;
 286       unsigned int cpupclmul:1;
 287       unsigned int cpufma:1;
 288       unsigned int cpufma4:1;
 289       unsigned int cpuxop:1;
 290       unsigned int cpulwp:1;
 291       unsigned int cpubmi:1;
 292       unsigned int cputbm:1;
 293       unsigned int cpumovbe:1;
 294       unsigned int cpucx16:1;
 295       unsigned int cpuept:1;
 296       unsigned int cpurdtscp:1;
 297       unsigned int cpufsgsbase:1;
 298       unsigned int cpurdrnd:1;
 299       unsigned int cpuf16c:1;
 300       unsigned int cpubmi2:1;
 301       unsigned int cpulzcnt:1;
 302       unsigned int cpuhle:1;
 303       unsigned int cpurtm:1;
 304       unsigned int cpuinvpcid:1;
 305       unsigned int cpuvmfunc:1;
 306       unsigned int cpumpx:1;
 307       unsigned int cpulm:1;
 308       unsigned int cpurdseed:1;
 309       unsigned int cpuadx:1;
 310       unsigned int cpuprfchw:1;
 311       unsigned int cpusmap:1;
 312       unsigned int cpusha:1;
 313       unsigned int cpuvrex:1;
 314       unsigned int cpuclflushopt:1;
 315       unsigned int cpuxsaves:1;
 316       unsigned int cpuxsavec:1;
 317       unsigned int cpuprefetchwt1:1;
 318       unsigned int cpuse1:1;
 319       unsigned int cpuclwb:1;
 320       unsigned int cpuavx512ifma:1;
 321       unsigned int cpuavx512vbmi:1;
 322       unsigned int cpuavx512_4fmaps:1;
 323       unsigned int cpuavx512_4vnniw:1;
 324       unsigned int cpumwaitx:1;
 325       unsigned int cpuclzero:1;
 326       unsigned int cpuospke:1;
 327       unsigned int cpurdpid:1;
 328       unsigned int cpuptwrite:1;
 329       unsigned int cpuregmmx:1;
 330       unsigned int cpuregxmm:1;
 331       unsigned int cpuregymm:1;
 332       unsigned int cpuregzmm:1;
 333       unsigned int cpuregmask:1;
 334       unsigned int cpu64:1;
 335       unsigned int cpuno64:1;
 336 #ifdef CpuUnused
 337       unsigned int unused:(CpuNumOfBits - CpuUnused);
 338 #endif
 339     } bitfield;
 340   unsigned int array[CpuNumOfUints];
 341 } i386_cpu_flags;
 342
 343 /* Position of opcode_modifier bits.  */
 344
 345 enum
 346 {
 347   /* has direction bit. */
 348   D = 0,
 349   /* set if operands can be words or dwords encoded the canonical way */
 350   W,
 351   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 352      operand in encoding.  */
 353   S,
 354   /* insn has a modrm byte. */
 355   Modrm,
 356   /* register is in low 3 bits of opcode */
 357   ShortForm,
 358   /* special case for jump insns.  */
 359   Jump,
 360   /* call and jump */
 361   JumpDword,
 362   /* loop and jecxz */
 363   JumpByte,
 364   /* special case for intersegment leaps/calls */
 365   JumpInterSegment,
 366   /* FP insn memory format bit, sized by 0x4 */
 367   FloatMF,
 368   /* src/dest swap for floats. */
 369   FloatR,
 370   /* has float insn direction bit. */
 371   FloatD,
 372   /* needs size prefix if in 32-bit mode */
 373   Size16,
 374   /* needs size prefix if in 16-bit mode */
 375   Size32,
 376   /* needs size prefix if in 64-bit mode */
 377   Size64,
 378   /* check register size.  */
 379   CheckRegSize,
 380   /* instruction ignores operand size prefix and in Intel mode ignores
 381      mnemonic size suffix check.  */
 382   IgnoreSize,
 383   /* default insn size depends on mode */
 384   DefaultSize,
 385   /* b suffix on instruction illegal */
 386   No_bSuf,
 387   /* w suffix on instruction illegal */
 388   No_wSuf,
 389   /* l suffix on instruction illegal */
 390   No_lSuf,
 391   /* s suffix on instruction illegal */
 392   No_sSuf,
 393   /* q suffix on instruction illegal */
 394   No_qSuf,
 395   /* long double suffix on instruction illegal */
 396   No_ldSuf,
 397   /* instruction needs FWAIT */
 398   FWait,
 399   /* quick test for string instructions */
 400   IsString,
 401   /* quick test if branch instruction is MPX supported */
 402   BNDPrefixOk,
 403   /* quick test for lockable instructions */
 404   IsLockable,
 405   /* fake an extra reg operand for clr, imul and special register
 406      processing for some instructions.  */
 407   RegKludge,
 408   /* The first operand must be xmm0 */
 409   FirstXmm0,
 410   /* An implicit xmm0 as the first operand */
 411   Implicit1stXmm0,
 412   /* The HLE prefix is OK:
 413      1. With a LOCK prefix.
 414      2. With or without a LOCK prefix.
 415      3. With a RELEASE (0xf3) prefix.
 416    */
 417 #define HLEPrefixNone           0
 418 #define HLEPrefixLock           1
 419 #define HLEPrefixAny            2
 420 #define HLEPrefixRelease        3
 421   HLEPrefixOk,
 422   /* An instruction on which a "rep" prefix is acceptable.  */
 423   RepPrefixOk,
 424   /* Convert to DWORD */
 425   ToDword,
 426   /* Convert to QWORD */
 427   ToQword,
 428   /* Address prefix changes operand 0 */
 429   AddrPrefixOp0,
 430   /* opcode is a prefix */
 431   IsPrefix,
 432   /* instruction has extension in 8 bit imm */
 433   ImmExt,
 434   /* instruction don't need Rex64 prefix.  */
 435   NoRex64,
 436   /* instruction require Rex64 prefix.  */
 437   Rex64,
 438   /* deprecated fp insn, gets a warning */
 439   Ugh,
 440   /* insn has VEX prefix:
 441         1: 128bit VEX prefix.
 442         2: 256bit VEX prefix.
 443         3: Scalar VEX prefix.
 444    */
 445 #define VEX128          1
 446 #define VEX256          2
 447 #define VEXScalar       3
 448   Vex,
 449   /* How to encode VEX.vvvv:
 450      0: VEX.vvvv must be 1111b.
 451      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 452         the content of source registers will be preserved.
 453         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 454         where the content of first source register will be overwritten
 455         by the result.
 456         VEX.NDD2.  The second destination register operand is encoded in
 457         VEX.vvvv for instructions with 2 destination register operands.
 458         For assembler, there are no difference between VEX.NDS, VEX.DDS
 459         and VEX.NDD2.
 460      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 461      instructions with 1 destination register operand.
 462      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 463         of the operands can access a memory location.
 464    */
 465 #define VEXXDS  1
 466 #define VEXNDD  2
 467 #define VEXLWP  3
 468   VexVVVV,
 469   /* How the VEX.W bit is used:
 470      0: Set by the REX.W bit.
 471      1: VEX.W0.  Should always be 0.
 472      2: VEX.W1.  Should always be 1.
 473    */
 474 #define VEXW0   1
 475 #define VEXW1   2
 476   VexW,
 477   /* VEX opcode prefix:
 478      0: VEX 0x0F opcode prefix.
 479      1: VEX 0x0F38 opcode prefix.
 480      2: VEX 0x0F3A opcode prefix
 481      3: XOP 0x08 opcode prefix.
 482      4: XOP 0x09 opcode prefix
 483      5: XOP 0x0A opcode prefix.
 484    */
 485 #define VEX0F           0
 486 #define VEX0F38         1
 487 #define VEX0F3A         2
 488 #define XOP08           3
 489 #define XOP09           4
 490 #define XOP0A           5
 491   VexOpcode,
 492   /* number of VEX source operands:
 493      0: <= 2 source operands.
 494      1: 2 XOP source operands.
 495      2: 3 source operands.
 496    */
 497 #define XOP2SOURCES     1
 498 #define VEX3SOURCES     2
 499   VexSources,
 500   /* instruction has VEX 8 bit imm */
 501   VexImmExt,
 502   /* Instruction with vector SIB byte:
 503         1: 128bit vector register.
 504         2: 256bit vector register.
 505         3: 512bit vector register.
 506    */
 507 #define VecSIB128       1
 508 #define VecSIB256       2
 509 #define VecSIB512       3
 510   VecSIB,
 511   /* SSE to AVX support required */
 512   SSE2AVX,
 513   /* No AVX equivalent */
 514   NoAVX,
 515
 516   /* insn has EVEX prefix:
 517         1: 512bit EVEX prefix.
 518         2: 128bit EVEX prefix.
 519         3: 256bit EVEX prefix.
 520         4: Length-ignored (LIG) EVEX prefix.
 521    */
 522 #define EVEX512                1
 523 #define EVEX128                2
 524 #define EVEX256                3
 525 #define EVEXLIG                4
 526   EVex,
 527
 528   /* AVX512 masking support:
 529         1: Zeroing-masking.
 530         2: Merging-masking.
 531         3: Both zeroing and merging masking.
 532    */
 533 #define ZEROING_MASKING 1
 534 #define MERGING_MASKING 2
 535 #define BOTH_MASKING    3
 536   Masking,
 537
 538   /* Input element size of vector insn:
 539         0: 32bit.
 540         1: 64bit.
 541    */
 542   VecESize,
 543
 544   /* Broadcast factor.
 545         0: No broadcast.
 546         1: 1to16 broadcast.
 547         2: 1to8 broadcast.
 548    */
 549 #define NO_BROADCAST    0
 550 #define BROADCAST_1TO16 1
 551 #define BROADCAST_1TO8  2
 552 #define BROADCAST_1TO4  3
 553 #define BROADCAST_1TO2  4
 554   Broadcast,
 555
 556   /* Static rounding control is supported.  */
 557   StaticRounding,
 558
 559   /* Supress All Exceptions is supported.  */
 560   SAE,
 561
 562   /* Copressed Disp8*N attribute.  */
 563   Disp8MemShift,
 564
 565   /* Default mask isn't allowed.  */
 566   NoDefMask,
 567
 568   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 569      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 570    */
 571   ImplicitQuadGroup,
 572
 573   /* Compatible with old (<= 2.8.1) versions of gcc  */
 574   OldGcc,
 575   /* AT&T mnemonic.  */
 576   ATTMnemonic,
 577   /* AT&T syntax.  */
 578   ATTSyntax,
 579   /* Intel syntax.  */
 580   IntelSyntax,
 581   /* AMD64.  */
 582   AMD64,
 583   /* Intel64.  */
 584   Intel64,
 585   /* The last bitfield in i386_opcode_modifier.  */
 586   Opcode_Modifier_Max
 587 };
 588
 589 typedef struct i386_opcode_modifier
 590 {
 591   unsigned int d:1;
 592   unsigned int w:1;
 593   unsigned int s:1;
 594   unsigned int modrm:1;
 595   unsigned int shortform:1;
 596   unsigned int jump:1;
 597   unsigned int jumpdword:1;
 598   unsigned int jumpbyte:1;
 599   unsigned int jumpintersegment:1;
 600   unsigned int floatmf:1;
 601   unsigned int floatr:1;
 602   unsigned int floatd:1;
 603   unsigned int size16:1;
 604   unsigned int size32:1;
 605   unsigned int size64:1;
 606   unsigned int checkregsize:1;
 607   unsigned int ignoresize:1;
 608   unsigned int defaultsize:1;
 609   unsigned int no_bsuf:1;
 610   unsigned int no_wsuf:1;
 611   unsigned int no_lsuf:1;
 612   unsigned int no_ssuf:1;
 613   unsigned int no_qsuf:1;
 614   unsigned int no_ldsuf:1;
 615   unsigned int fwait:1;
 616   unsigned int isstring:1;
 617   unsigned int bndprefixok:1;
 618   unsigned int islockable:1;
 619   unsigned int regkludge:1;
 620   unsigned int firstxmm0:1;
 621   unsigned int implicit1stxmm0:1;
 622   unsigned int hleprefixok:2;
 623   unsigned int repprefixok:1;
 624   unsigned int todword:1;
 625   unsigned int toqword:1;
 626   unsigned int addrprefixop0:1;
 627   unsigned int isprefix:1;
 628   unsigned int immext:1;
 629   unsigned int norex64:1;
 630   unsigned int rex64:1;
 631   unsigned int ugh:1;
 632   unsigned int vex:2;
 633   unsigned int vexvvvv:2;
 634   unsigned int vexw:2;
 635   unsigned int vexopcode:3;
 636   unsigned int vexsources:2;
 637   unsigned int veximmext:1;
 638   unsigned int vecsib:2;
 639   unsigned int sse2avx:1;
 640   unsigned int noavx:1;
 641   unsigned int evex:3;
 642   unsigned int masking:2;
 643   unsigned int vecesize:1;
 644   unsigned int broadcast:3;
 645   unsigned int staticrounding:1;
 646   unsigned int sae:1;
 647   unsigned int disp8memshift:3;
 648   unsigned int nodefmask:1;
 649   unsigned int implicitquadgroup:1;
 650   unsigned int oldgcc:1;
 651   unsigned int attmnemonic:1;
 652   unsigned int attsyntax:1;
 653   unsigned int intelsyntax:1;
 654   unsigned int amd64:1;
 655   unsigned int intel64:1;
 656 } i386_opcode_modifier;
 657
 658 /* Position of operand_type bits.  */
 659
 660 enum
 661 {
 662   /* 8bit register */
 663   Reg8 = 0,
 664   /* 16bit register */
 665   Reg16,
 666   /* 32bit register */
 667   Reg32,
 668   /* 64bit register */
 669   Reg64,
 670   /* Floating pointer stack register */
 671   FloatReg,
 672   /* MMX register */
 673   RegMMX,
 674   /* SSE register */
 675   RegXMM,
 676   /* AVX registers */
 677   RegYMM,
 678   /* AVX512 registers */
 679   RegZMM,
 680   /* Vector Mask registers */
 681   RegMask,
 682   /* Control register */
 683   Control,
 684   /* Debug register */
 685   Debug,
 686   /* Test register */
 687   Test,
 688   /* 2 bit segment register */
 689   SReg2,
 690   /* 3 bit segment register */
 691   SReg3,
 692   /* 1 bit immediate */
 693   Imm1,
 694   /* 8 bit immediate */
 695   Imm8,
 696   /* 8 bit immediate sign extended */
 697   Imm8S,
 698   /* 16 bit immediate */
 699   Imm16,
 700   /* 32 bit immediate */
 701   Imm32,
 702   /* 32 bit immediate sign extended */
 703   Imm32S,
 704   /* 64 bit immediate */
 705   Imm64,
 706   /* 8bit/16bit/32bit displacements are used in different ways,
 707      depending on the instruction.  For jumps, they specify the
 708      size of the PC relative displacement, for instructions with
 709      memory operand, they specify the size of the offset relative
 710      to the base register, and for instructions with memory offset
 711      such as `mov 1234,%al' they specify the size of the offset
 712      relative to the segment base.  */
 713   /* 8 bit displacement */
 714   Disp8,
 715   /* 16 bit displacement */
 716   Disp16,
 717   /* 32 bit displacement */
 718   Disp32,
 719   /* 32 bit signed displacement */
 720   Disp32S,
 721   /* 64 bit displacement */
 722   Disp64,
 723   /* Accumulator %al/%ax/%eax/%rax */
 724   Acc,
 725   /* Floating pointer top stack register %st(0) */
 726   FloatAcc,
 727   /* Register which can be used for base or index in memory operand.  */
 728   BaseIndex,
 729   /* Register to hold in/out port addr = dx */
 730   InOutPortReg,
 731   /* Register to hold shift count = cl */
 732   ShiftCount,
 733   /* Absolute address for jump.  */
 734   JumpAbsolute,
 735   /* String insn operand with fixed es segment */
 736   EsSeg,
 737   /* RegMem is for instructions with a modrm byte where the register
 738      destination operand should be encoded in the mod and regmem fields.
 739      Normally, it will be encoded in the reg field. We add a RegMem
 740      flag to the destination register operand to indicate that it should
 741      be encoded in the regmem field.  */
 742   RegMem,
 743   /* Memory.  */
 744   Mem,
 745   /* BYTE memory. */
 746   Byte,
 747   /* WORD memory. 2 byte */
 748   Word,
 749   /* DWORD memory. 4 byte */
 750   Dword,
 751   /* FWORD memory. 6 byte */
 752   Fword,
 753   /* QWORD memory. 8 byte */
 754   Qword,
 755   /* TBYTE memory. 10 byte */
 756   Tbyte,
 757   /* XMMWORD memory. */
 758   Xmmword,
 759   /* YMMWORD memory. */
 760   Ymmword,
 761   /* ZMMWORD memory.  */
 762   Zmmword,
 763   /* Unspecified memory size.  */
 764   Unspecified,
 765   /* Any memory size.  */
 766   Anysize,
 767
 768   /* Vector 4 bit immediate.  */
 769   Vec_Imm4,
 770
 771   /* Bound register.  */
 772   RegBND,
 773
 774   /* Vector 8bit displacement */
 775   Vec_Disp8,
 776
 777   /* The last bitfield in i386_operand_type.  */
 778   OTMax
 779 };
 780
 781 #define OTNumOfUints \
 782   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 783 #define OTNumOfBits \
 784   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 785
 786 /* If you get a compiler error for zero width of the unused field,
 787    comment it out.  */
 788 #define OTUnused                (OTMax + 1)
 789
 790 typedef union i386_operand_type
 791 {
 792   struct
 793     {
 794       unsigned int reg8:1;
 795       unsigned int reg16:1;
 796       unsigned int reg32:1;
 797       unsigned int reg64:1;
 798       unsigned int floatreg:1;
 799       unsigned int regmmx:1;
 800       unsigned int regxmm:1;
 801       unsigned int regymm:1;
 802       unsigned int regzmm:1;
 803       unsigned int regmask:1;
 804       unsigned int control:1;
 805       unsigned int debug:1;
 806       unsigned int test:1;
 807       unsigned int sreg2:1;
 808       unsigned int sreg3:1;
 809       unsigned int imm1:1;
 810       unsigned int imm8:1;
 811       unsigned int imm8s:1;
 812       unsigned int imm16:1;
 813       unsigned int imm32:1;
 814       unsigned int imm32s:1;
 815       unsigned int imm64:1;
 816       unsigned int disp8:1;
 817       unsigned int disp16:1;
 818       unsigned int disp32:1;
 819       unsigned int disp32s:1;
 820       unsigned int disp64:1;
 821       unsigned int acc:1;
 822       unsigned int floatacc:1;
 823       unsigned int baseindex:1;
 824       unsigned int inoutportreg:1;
 825       unsigned int shiftcount:1;
 826       unsigned int jumpabsolute:1;
 827       unsigned int esseg:1;
 828       unsigned int regmem:1;
 829       unsigned int mem:1;
 830       unsigned int byte:1;
 831       unsigned int word:1;
 832       unsigned int dword:1;
 833       unsigned int fword:1;
 834       unsigned int qword:1;
 835       unsigned int tbyte:1;
 836       unsigned int xmmword:1;
 837       unsigned int ymmword:1;
 838       unsigned int zmmword:1;
 839       unsigned int unspecified:1;
 840       unsigned int anysize:1;
 841       unsigned int vec_imm4:1;
 842       unsigned int regbnd:1;
 843       unsigned int vec_disp8:1;
 844 #ifdef OTUnused
 845       unsigned int unused:(OTNumOfBits - OTUnused);
 846 #endif
 847     } bitfield;
 848   unsigned int array[OTNumOfUints];
 849 } i386_operand_type;
 850
 851 typedef struct insn_template
 852 {
 853   /* instruction name sans width suffix ("mov" for movl insns) */
 854   char *name;
 855
 856   /* how many operands */
 857   unsigned int operands;
 858
 859   /* base_opcode is the fundamental opcode byte without optional
 860      prefix(es).  */
 861   unsigned int base_opcode;
 862 #define Opcode_D        0x2 /* Direction bit:
 863                                set if Reg --> Regmem;
 864                                unset if Regmem --> Reg. */
 865 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 866 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 867
 868   /* extension_opcode is the 3 bit extension for group <n> insns.
 869      This field is also used to store the 8-bit opcode suffix for the
 870      AMD 3DNow! instructions.
 871      If this template has no extension opcode (the usual case) use None
 872      Instructions */
 873   unsigned int extension_opcode;
 874 #define None 0xffff             /* If no extension_opcode is possible.  */
 875
 876   /* Opcode length.  */
 877   unsigned char opcode_length;
 878
 879   /* cpu feature flags */
 880   i386_cpu_flags cpu_flags;
 881
 882   /* the bits in opcode_modifier are used to generate the final opcode from
 883      the base_opcode.  These bits also are used to detect alternate forms of
 884      the same instruction */
 885   i386_opcode_modifier opcode_modifier;
 886
 887   /* operand_types[i] describes the type of operand i.  This is made
 888      by OR'ing together all of the possible type masks.  (e.g.
 889      'operand_types[i] = Reg|Imm' specifies that operand i can be
 890      either a register or an immediate operand.  */
 891   i386_operand_type operand_types[MAX_OPERANDS];
 892 }
 893 insn_template;
 894
 895 extern const insn_template i386_optab[];
 896
 897 /* these are for register name --> number & type hash lookup */
 898 typedef struct
 899 {
 900   char *reg_name;
 901   i386_operand_type reg_type;
 902   unsigned char reg_flags;
 903 #define RegRex      0x1  /* Extended register.  */
 904 #define RegRex64    0x2  /* Extended 8 bit register.  */
 905 #define RegVRex     0x4  /* Extended vector register.  */
 906   unsigned char reg_num;
 907 #define RegRip  ((unsigned char ) ~0)
 908 #define RegEip  (RegRip - 1)
 909 /* EIZ and RIZ are fake index registers.  */
 910 #define RegEiz  (RegEip - 1)
 911 #define RegRiz  (RegEiz - 1)
 912 /* FLAT is a fake segment register (Intel mode).  */
 913 #define RegFlat     ((unsigned char) ~0)
 914   signed char dw2_regnum[2];
 915 #define Dw2Inval (-1)
 916 }
 917 reg_entry;
 918
 919 /* Entries in i386_regtab.  */
 920 #define REGNAM_AL 1
 921 #define REGNAM_AX 25
 922 #define REGNAM_EAX 41
 923
 924 extern const reg_entry i386_regtab[];
 925 extern const unsigned int i386_regtab_size;
 926
 927 typedef struct
 928 {
 929   char *seg_name;
 930   unsigned int seg_prefix;
 931 }
 932 seg_entry;
 933
 934 extern const seg_entry cs;
 935 extern const seg_entry ds;
 936 extern const seg_entry ss;
 937 extern const seg_entry es;
 938 extern const seg_entry fs;
 939 extern const seg_entry gs;