opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* mwaitx instruction required */
 204   CpuMWAITX,
 205   /* Clzero instruction required */
 206   CpuCLZERO,
 207   /* OSPKE instruction required */
 208   CpuOSPKE,
 209   /* RDPID instruction required */
 210   CpuRDPID,
 211   /* PTWRITE instruction required */
 212   CpuPTWRITE,
 213   /* CET instruction support required */
 214   CpuCET,
 215   /* GFNI instructions required */
 216   CpuGFNI,
 217   /* MMX register support required */
 218   CpuRegMMX,
 219   /* XMM register support required */
 220   CpuRegXMM,
 221   /* YMM register support required */
 222   CpuRegYMM,
 223   /* ZMM register support required */
 224   CpuRegZMM,
 225   /* Mask register support required */
 226   CpuRegMask,
 227   /* 64bit support required  */
 228   Cpu64,
 229   /* Not supported in the 64bit mode  */
 230   CpuNo64,
 231   /* The last bitfield in i386_cpu_flags.  */
 232   CpuMax = CpuNo64
 233 };
 234
 235 #define CpuNumOfUints \
 236   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 237 #define CpuNumOfBits \
 238   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 239
 240 /* If you get a compiler error for zero width of the unused field,
 241    comment it out.  */
 242 #define CpuUnused       (CpuMax + 1)
 243
 244 /* We can check if an instruction is available with array instead
 245    of bitfield. */
 246 typedef union i386_cpu_flags
 247 {
 248   struct
 249     {
 250       unsigned int cpui186:1;
 251       unsigned int cpui286:1;
 252       unsigned int cpui386:1;
 253       unsigned int cpui486:1;
 254       unsigned int cpui586:1;
 255       unsigned int cpui686:1;
 256       unsigned int cpuclflush:1;
 257       unsigned int cpunop:1;
 258       unsigned int cpusyscall:1;
 259       unsigned int cpu8087:1;
 260       unsigned int cpu287:1;
 261       unsigned int cpu387:1;
 262       unsigned int cpu687:1;
 263       unsigned int cpufisttp:1;
 264       unsigned int cpummx:1;
 265       unsigned int cpusse:1;
 266       unsigned int cpusse2:1;
 267       unsigned int cpua3dnow:1;
 268       unsigned int cpua3dnowa:1;
 269       unsigned int cpusse3:1;
 270       unsigned int cpupadlock:1;
 271       unsigned int cpusvme:1;
 272       unsigned int cpuvmx:1;
 273       unsigned int cpusmx:1;
 274       unsigned int cpussse3:1;
 275       unsigned int cpusse4a:1;
 276       unsigned int cpuabm:1;
 277       unsigned int cpusse4_1:1;
 278       unsigned int cpusse4_2:1;
 279       unsigned int cpuavx:1;
 280       unsigned int cpuavx2:1;
 281       unsigned int cpuavx512f:1;
 282       unsigned int cpuavx512cd:1;
 283       unsigned int cpuavx512er:1;
 284       unsigned int cpuavx512pf:1;
 285       unsigned int cpuavx512vl:1;
 286       unsigned int cpuavx512dq:1;
 287       unsigned int cpuavx512bw:1;
 288       unsigned int cpul1om:1;
 289       unsigned int cpuk1om:1;
 290       unsigned int cpuiamcu:1;
 291       unsigned int cpuxsave:1;
 292       unsigned int cpuxsaveopt:1;
 293       unsigned int cpuaes:1;
 294       unsigned int cpupclmul:1;
 295       unsigned int cpufma:1;
 296       unsigned int cpufma4:1;
 297       unsigned int cpuxop:1;
 298       unsigned int cpulwp:1;
 299       unsigned int cpubmi:1;
 300       unsigned int cputbm:1;
 301       unsigned int cpumovbe:1;
 302       unsigned int cpucx16:1;
 303       unsigned int cpuept:1;
 304       unsigned int cpurdtscp:1;
 305       unsigned int cpufsgsbase:1;
 306       unsigned int cpurdrnd:1;
 307       unsigned int cpuf16c:1;
 308       unsigned int cpubmi2:1;
 309       unsigned int cpulzcnt:1;
 310       unsigned int cpuhle:1;
 311       unsigned int cpurtm:1;
 312       unsigned int cpuinvpcid:1;
 313       unsigned int cpuvmfunc:1;
 314       unsigned int cpumpx:1;
 315       unsigned int cpulm:1;
 316       unsigned int cpurdseed:1;
 317       unsigned int cpuadx:1;
 318       unsigned int cpuprfchw:1;
 319       unsigned int cpusmap:1;
 320       unsigned int cpusha:1;
 321       unsigned int cpuvrex:1;
 322       unsigned int cpuclflushopt:1;
 323       unsigned int cpuxsaves:1;
 324       unsigned int cpuxsavec:1;
 325       unsigned int cpuprefetchwt1:1;
 326       unsigned int cpuse1:1;
 327       unsigned int cpuclwb:1;
 328       unsigned int cpuavx512ifma:1;
 329       unsigned int cpuavx512vbmi:1;
 330       unsigned int cpuavx512_4fmaps:1;
 331       unsigned int cpuavx512_4vnniw:1;
 332       unsigned int cpuavx512_vpopcntdq:1;
 333       unsigned int cpuavx512_vbmi2:1;
 334       unsigned int cpumwaitx:1;
 335       unsigned int cpuclzero:1;
 336       unsigned int cpuospke:1;
 337       unsigned int cpurdpid:1;
 338       unsigned int cpuptwrite:1;
 339       unsigned int cpucet:1;
 340       unsigned int cpugfni:1;
 341       unsigned int cpuregmmx:1;
 342       unsigned int cpuregxmm:1;
 343       unsigned int cpuregymm:1;
 344       unsigned int cpuregzmm:1;
 345       unsigned int cpuregmask:1;
 346       unsigned int cpu64:1;
 347       unsigned int cpuno64:1;
 348 #ifdef CpuUnused
 349       unsigned int unused:(CpuNumOfBits - CpuUnused);
 350 #endif
 351     } bitfield;
 352   unsigned int array[CpuNumOfUints];
 353 } i386_cpu_flags;
 354
 355 /* Position of opcode_modifier bits.  */
 356
 357 enum
 358 {
 359   /* has direction bit. */
 360   D = 0,
 361   /* set if operands can be words or dwords encoded the canonical way */
 362   W,
 363   /* load form instruction. Must be placed before store form.  */
 364   Load,
 365   /* insn has a modrm byte. */
 366   Modrm,
 367   /* register is in low 3 bits of opcode */
 368   ShortForm,
 369   /* special case for jump insns.  */
 370   Jump,
 371   /* call and jump */
 372   JumpDword,
 373   /* loop and jecxz */
 374   JumpByte,
 375   /* special case for intersegment leaps/calls */
 376   JumpInterSegment,
 377   /* FP insn memory format bit, sized by 0x4 */
 378   FloatMF,
 379   /* src/dest swap for floats. */
 380   FloatR,
 381   /* has float insn direction bit. */
 382   FloatD,
 383   /* needs size prefix if in 32-bit mode */
 384   Size16,
 385   /* needs size prefix if in 16-bit mode */
 386   Size32,
 387   /* needs size prefix if in 64-bit mode */
 388   Size64,
 389   /* check register size.  */
 390   CheckRegSize,
 391   /* instruction ignores operand size prefix and in Intel mode ignores
 392      mnemonic size suffix check.  */
 393   IgnoreSize,
 394   /* default insn size depends on mode */
 395   DefaultSize,
 396   /* b suffix on instruction illegal */
 397   No_bSuf,
 398   /* w suffix on instruction illegal */
 399   No_wSuf,
 400   /* l suffix on instruction illegal */
 401   No_lSuf,
 402   /* s suffix on instruction illegal */
 403   No_sSuf,
 404   /* q suffix on instruction illegal */
 405   No_qSuf,
 406   /* long double suffix on instruction illegal */
 407   No_ldSuf,
 408   /* instruction needs FWAIT */
 409   FWait,
 410   /* quick test for string instructions */
 411   IsString,
 412   /* quick test if branch instruction is MPX supported */
 413   BNDPrefixOk,
 414   /* quick test if NOTRACK prefix is supported */
 415   NoTrackPrefixOk,
 416   /* quick test for lockable instructions */
 417   IsLockable,
 418   /* fake an extra reg operand for clr, imul and special register
 419      processing for some instructions.  */
 420   RegKludge,
 421   /* The first operand must be xmm0 */
 422   FirstXmm0,
 423   /* An implicit xmm0 as the first operand */
 424   Implicit1stXmm0,
 425   /* The HLE prefix is OK:
 426      1. With a LOCK prefix.
 427      2. With or without a LOCK prefix.
 428      3. With a RELEASE (0xf3) prefix.
 429    */
 430 #define HLEPrefixNone           0
 431 #define HLEPrefixLock           1
 432 #define HLEPrefixAny            2
 433 #define HLEPrefixRelease        3
 434   HLEPrefixOk,
 435   /* An instruction on which a "rep" prefix is acceptable.  */
 436   RepPrefixOk,
 437   /* Convert to DWORD */
 438   ToDword,
 439   /* Convert to QWORD */
 440   ToQword,
 441   /* Address prefix changes operand 0 */
 442   AddrPrefixOp0,
 443   /* opcode is a prefix */
 444   IsPrefix,
 445   /* instruction has extension in 8 bit imm */
 446   ImmExt,
 447   /* instruction don't need Rex64 prefix.  */
 448   NoRex64,
 449   /* instruction require Rex64 prefix.  */
 450   Rex64,
 451   /* deprecated fp insn, gets a warning */
 452   Ugh,
 453   /* insn has VEX prefix:
 454         1: 128bit VEX prefix.
 455         2: 256bit VEX prefix.
 456         3: Scalar VEX prefix.
 457    */
 458 #define VEX128          1
 459 #define VEX256          2
 460 #define VEXScalar       3
 461   Vex,
 462   /* How to encode VEX.vvvv:
 463      0: VEX.vvvv must be 1111b.
 464      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 465         the content of source registers will be preserved.
 466         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 467         where the content of first source register will be overwritten
 468         by the result.
 469         VEX.NDD2.  The second destination register operand is encoded in
 470         VEX.vvvv for instructions with 2 destination register operands.
 471         For assembler, there are no difference between VEX.NDS, VEX.DDS
 472         and VEX.NDD2.
 473      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 474      instructions with 1 destination register operand.
 475      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 476         of the operands can access a memory location.
 477    */
 478 #define VEXXDS  1
 479 #define VEXNDD  2
 480 #define VEXLWP  3
 481   VexVVVV,
 482   /* How the VEX.W bit is used:
 483      0: Set by the REX.W bit.
 484      1: VEX.W0.  Should always be 0.
 485      2: VEX.W1.  Should always be 1.
 486    */
 487 #define VEXW0   1
 488 #define VEXW1   2
 489   VexW,
 490   /* VEX opcode prefix:
 491      0: VEX 0x0F opcode prefix.
 492      1: VEX 0x0F38 opcode prefix.
 493      2: VEX 0x0F3A opcode prefix
 494      3: XOP 0x08 opcode prefix.
 495      4: XOP 0x09 opcode prefix
 496      5: XOP 0x0A opcode prefix.
 497    */
 498 #define VEX0F           0
 499 #define VEX0F38         1
 500 #define VEX0F3A         2
 501 #define XOP08           3
 502 #define XOP09           4
 503 #define XOP0A           5
 504   VexOpcode,
 505   /* number of VEX source operands:
 506      0: <= 2 source operands.
 507      1: 2 XOP source operands.
 508      2: 3 source operands.
 509    */
 510 #define XOP2SOURCES     1
 511 #define VEX3SOURCES     2
 512   VexSources,
 513   /* instruction has VEX 8 bit imm */
 514   VexImmExt,
 515   /* Instruction with vector SIB byte:
 516         1: 128bit vector register.
 517         2: 256bit vector register.
 518         3: 512bit vector register.
 519    */
 520 #define VecSIB128       1
 521 #define VecSIB256       2
 522 #define VecSIB512       3
 523   VecSIB,
 524   /* SSE to AVX support required */
 525   SSE2AVX,
 526   /* No AVX equivalent */
 527   NoAVX,
 528
 529   /* insn has EVEX prefix:
 530         1: 512bit EVEX prefix.
 531         2: 128bit EVEX prefix.
 532         3: 256bit EVEX prefix.
 533         4: Length-ignored (LIG) EVEX prefix.
 534    */
 535 #define EVEX512                1
 536 #define EVEX128                2
 537 #define EVEX256                3
 538 #define EVEXLIG                4
 539   EVex,
 540
 541   /* AVX512 masking support:
 542         1: Zeroing-masking.
 543         2: Merging-masking.
 544         3: Both zeroing and merging masking.
 545    */
 546 #define ZEROING_MASKING 1
 547 #define MERGING_MASKING 2
 548 #define BOTH_MASKING    3
 549   Masking,
 550
 551   /* Input element size of vector insn:
 552         0: 32bit.
 553         1: 64bit.
 554    */
 555   VecESize,
 556
 557   /* Broadcast factor.
 558         0: No broadcast.
 559         1: 1to16 broadcast.
 560         2: 1to8 broadcast.
 561    */
 562 #define NO_BROADCAST    0
 563 #define BROADCAST_1TO16 1
 564 #define BROADCAST_1TO8  2
 565 #define BROADCAST_1TO4  3
 566 #define BROADCAST_1TO2  4
 567   Broadcast,
 568
 569   /* Static rounding control is supported.  */
 570   StaticRounding,
 571
 572   /* Supress All Exceptions is supported.  */
 573   SAE,
 574
 575   /* Copressed Disp8*N attribute.  */
 576   Disp8MemShift,
 577
 578   /* Default mask isn't allowed.  */
 579   NoDefMask,
 580
 581   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 582      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 583    */
 584   ImplicitQuadGroup,
 585
 586   /* Compatible with old (<= 2.8.1) versions of gcc  */
 587   OldGcc,
 588   /* AT&T mnemonic.  */
 589   ATTMnemonic,
 590   /* AT&T syntax.  */
 591   ATTSyntax,
 592   /* Intel syntax.  */
 593   IntelSyntax,
 594   /* AMD64.  */
 595   AMD64,
 596   /* Intel64.  */
 597   Intel64,
 598   /* The last bitfield in i386_opcode_modifier.  */
 599   Opcode_Modifier_Max
 600 };
 601
 602 typedef struct i386_opcode_modifier
 603 {
 604   unsigned int d:1;
 605   unsigned int w:1;
 606   unsigned int load:1;
 607   unsigned int modrm:1;
 608   unsigned int shortform:1;
 609   unsigned int jump:1;
 610   unsigned int jumpdword:1;
 611   unsigned int jumpbyte:1;
 612   unsigned int jumpintersegment:1;
 613   unsigned int floatmf:1;
 614   unsigned int floatr:1;
 615   unsigned int floatd:1;
 616   unsigned int size16:1;
 617   unsigned int size32:1;
 618   unsigned int size64:1;
 619   unsigned int checkregsize:1;
 620   unsigned int ignoresize:1;
 621   unsigned int defaultsize:1;
 622   unsigned int no_bsuf:1;
 623   unsigned int no_wsuf:1;
 624   unsigned int no_lsuf:1;
 625   unsigned int no_ssuf:1;
 626   unsigned int no_qsuf:1;
 627   unsigned int no_ldsuf:1;
 628   unsigned int fwait:1;
 629   unsigned int isstring:1;
 630   unsigned int bndprefixok:1;
 631   unsigned int notrackprefixok:1;
 632   unsigned int islockable:1;
 633   unsigned int regkludge:1;
 634   unsigned int firstxmm0:1;
 635   unsigned int implicit1stxmm0:1;
 636   unsigned int hleprefixok:2;
 637   unsigned int repprefixok:1;
 638   unsigned int todword:1;
 639   unsigned int toqword:1;
 640   unsigned int addrprefixop0:1;
 641   unsigned int isprefix:1;
 642   unsigned int immext:1;
 643   unsigned int norex64:1;
 644   unsigned int rex64:1;
 645   unsigned int ugh:1;
 646   unsigned int vex:2;
 647   unsigned int vexvvvv:2;
 648   unsigned int vexw:2;
 649   unsigned int vexopcode:3;
 650   unsigned int vexsources:2;
 651   unsigned int veximmext:1;
 652   unsigned int vecsib:2;
 653   unsigned int sse2avx:1;
 654   unsigned int noavx:1;
 655   unsigned int evex:3;
 656   unsigned int masking:2;
 657   unsigned int vecesize:1;
 658   unsigned int broadcast:3;
 659   unsigned int staticrounding:1;
 660   unsigned int sae:1;
 661   unsigned int disp8memshift:3;
 662   unsigned int nodefmask:1;
 663   unsigned int implicitquadgroup:1;
 664   unsigned int oldgcc:1;
 665   unsigned int attmnemonic:1;
 666   unsigned int attsyntax:1;
 667   unsigned int intelsyntax:1;
 668   unsigned int amd64:1;
 669   unsigned int intel64:1;
 670 } i386_opcode_modifier;
 671
 672 /* Position of operand_type bits.  */
 673
 674 enum
 675 {
 676   /* 8bit register */
 677   Reg8 = 0,
 678   /* 16bit register */
 679   Reg16,
 680   /* 32bit register */
 681   Reg32,
 682   /* 64bit register */
 683   Reg64,
 684   /* Floating pointer stack register */
 685   FloatReg,
 686   /* MMX register */
 687   RegMMX,
 688   /* SSE register */
 689   RegXMM,
 690   /* AVX registers */
 691   RegYMM,
 692   /* AVX512 registers */
 693   RegZMM,
 694   /* Vector Mask registers */
 695   RegMask,
 696   /* Control register */
 697   Control,
 698   /* Debug register */
 699   Debug,
 700   /* Test register */
 701   Test,
 702   /* 2 bit segment register */
 703   SReg2,
 704   /* 3 bit segment register */
 705   SReg3,
 706   /* 1 bit immediate */
 707   Imm1,
 708   /* 8 bit immediate */
 709   Imm8,
 710   /* 8 bit immediate sign extended */
 711   Imm8S,
 712   /* 16 bit immediate */
 713   Imm16,
 714   /* 32 bit immediate */
 715   Imm32,
 716   /* 32 bit immediate sign extended */
 717   Imm32S,
 718   /* 64 bit immediate */
 719   Imm64,
 720   /* 8bit/16bit/32bit displacements are used in different ways,
 721      depending on the instruction.  For jumps, they specify the
 722      size of the PC relative displacement, for instructions with
 723      memory operand, they specify the size of the offset relative
 724      to the base register, and for instructions with memory offset
 725      such as `mov 1234,%al' they specify the size of the offset
 726      relative to the segment base.  */
 727   /* 8 bit displacement */
 728   Disp8,
 729   /* 16 bit displacement */
 730   Disp16,
 731   /* 32 bit displacement */
 732   Disp32,
 733   /* 32 bit signed displacement */
 734   Disp32S,
 735   /* 64 bit displacement */
 736   Disp64,
 737   /* Accumulator %al/%ax/%eax/%rax */
 738   Acc,
 739   /* Floating pointer top stack register %st(0) */
 740   FloatAcc,
 741   /* Register which can be used for base or index in memory operand.  */
 742   BaseIndex,
 743   /* Register to hold in/out port addr = dx */
 744   InOutPortReg,
 745   /* Register to hold shift count = cl */
 746   ShiftCount,
 747   /* Absolute address for jump.  */
 748   JumpAbsolute,
 749   /* String insn operand with fixed es segment */
 750   EsSeg,
 751   /* RegMem is for instructions with a modrm byte where the register
 752      destination operand should be encoded in the mod and regmem fields.
 753      Normally, it will be encoded in the reg field. We add a RegMem
 754      flag to the destination register operand to indicate that it should
 755      be encoded in the regmem field.  */
 756   RegMem,
 757   /* Memory.  */
 758   Mem,
 759   /* BYTE memory. */
 760   Byte,
 761   /* WORD memory. 2 byte */
 762   Word,
 763   /* DWORD memory. 4 byte */
 764   Dword,
 765   /* FWORD memory. 6 byte */
 766   Fword,
 767   /* QWORD memory. 8 byte */
 768   Qword,
 769   /* TBYTE memory. 10 byte */
 770   Tbyte,
 771   /* XMMWORD memory. */
 772   Xmmword,
 773   /* YMMWORD memory. */
 774   Ymmword,
 775   /* ZMMWORD memory.  */
 776   Zmmword,
 777   /* Unspecified memory size.  */
 778   Unspecified,
 779   /* Any memory size.  */
 780   Anysize,
 781
 782   /* Vector 4 bit immediate.  */
 783   Vec_Imm4,
 784
 785   /* Bound register.  */
 786   RegBND,
 787
 788   /* Vector 8bit displacement */
 789   Vec_Disp8,
 790
 791   /* The last bitfield in i386_operand_type.  */
 792   OTMax
 793 };
 794
 795 #define OTNumOfUints \
 796   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 797 #define OTNumOfBits \
 798   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 799
 800 /* If you get a compiler error for zero width of the unused field,
 801    comment it out.  */
 802 #define OTUnused                (OTMax + 1)
 803
 804 typedef union i386_operand_type
 805 {
 806   struct
 807     {
 808       unsigned int reg8:1;
 809       unsigned int reg16:1;
 810       unsigned int reg32:1;
 811       unsigned int reg64:1;
 812       unsigned int floatreg:1;
 813       unsigned int regmmx:1;
 814       unsigned int regxmm:1;
 815       unsigned int regymm:1;
 816       unsigned int regzmm:1;
 817       unsigned int regmask:1;
 818       unsigned int control:1;
 819       unsigned int debug:1;
 820       unsigned int test:1;
 821       unsigned int sreg2:1;
 822       unsigned int sreg3:1;
 823       unsigned int imm1:1;
 824       unsigned int imm8:1;
 825       unsigned int imm8s:1;
 826       unsigned int imm16:1;
 827       unsigned int imm32:1;
 828       unsigned int imm32s:1;
 829       unsigned int imm64:1;
 830       unsigned int disp8:1;
 831       unsigned int disp16:1;
 832       unsigned int disp32:1;
 833       unsigned int disp32s:1;
 834       unsigned int disp64:1;
 835       unsigned int acc:1;
 836       unsigned int floatacc:1;
 837       unsigned int baseindex:1;
 838       unsigned int inoutportreg:1;
 839       unsigned int shiftcount:1;
 840       unsigned int jumpabsolute:1;
 841       unsigned int esseg:1;
 842       unsigned int regmem:1;
 843       unsigned int mem:1;
 844       unsigned int byte:1;
 845       unsigned int word:1;
 846       unsigned int dword:1;
 847       unsigned int fword:1;
 848       unsigned int qword:1;
 849       unsigned int tbyte:1;
 850       unsigned int xmmword:1;
 851       unsigned int ymmword:1;
 852       unsigned int zmmword:1;
 853       unsigned int unspecified:1;
 854       unsigned int anysize:1;
 855       unsigned int vec_imm4:1;
 856       unsigned int regbnd:1;
 857       unsigned int vec_disp8:1;
 858 #ifdef OTUnused
 859       unsigned int unused:(OTNumOfBits - OTUnused);
 860 #endif
 861     } bitfield;
 862   unsigned int array[OTNumOfUints];
 863 } i386_operand_type;
 864
 865 typedef struct insn_template
 866 {
 867   /* instruction name sans width suffix ("mov" for movl insns) */
 868   char *name;
 869
 870   /* how many operands */
 871   unsigned int operands;
 872
 873   /* base_opcode is the fundamental opcode byte without optional
 874      prefix(es).  */
 875   unsigned int base_opcode;
 876 #define Opcode_D        0x2 /* Direction bit:
 877                                set if Reg --> Regmem;
 878                                unset if Regmem --> Reg. */
 879 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 880 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 881
 882   /* extension_opcode is the 3 bit extension for group <n> insns.
 883      This field is also used to store the 8-bit opcode suffix for the
 884      AMD 3DNow! instructions.
 885      If this template has no extension opcode (the usual case) use None
 886      Instructions */
 887   unsigned int extension_opcode;
 888 #define None 0xffff             /* If no extension_opcode is possible.  */
 889
 890   /* Opcode length.  */
 891   unsigned char opcode_length;
 892
 893   /* cpu feature flags */
 894   i386_cpu_flags cpu_flags;
 895
 896   /* the bits in opcode_modifier are used to generate the final opcode from
 897      the base_opcode.  These bits also are used to detect alternate forms of
 898      the same instruction */
 899   i386_opcode_modifier opcode_modifier;
 900
 901   /* operand_types[i] describes the type of operand i.  This is made
 902      by OR'ing together all of the possible type masks.  (e.g.
 903      'operand_types[i] = Reg|Imm' specifies that operand i can be
 904      either a register or an immediate operand.  */
 905   i386_operand_type operand_types[MAX_OPERANDS];
 906 }
 907 insn_template;
 908
 909 extern const insn_template i386_optab[];
 910
 911 /* these are for register name --> number & type hash lookup */
 912 typedef struct
 913 {
 914   char *reg_name;
 915   i386_operand_type reg_type;
 916   unsigned char reg_flags;
 917 #define RegRex      0x1  /* Extended register.  */
 918 #define RegRex64    0x2  /* Extended 8 bit register.  */
 919 #define RegVRex     0x4  /* Extended vector register.  */
 920   unsigned char reg_num;
 921 #define RegRip  ((unsigned char ) ~0)
 922 #define RegEip  (RegRip - 1)
 923 /* EIZ and RIZ are fake index registers.  */
 924 #define RegEiz  (RegEip - 1)
 925 #define RegRiz  (RegEiz - 1)
 926 /* FLAT is a fake segment register (Intel mode).  */
 927 #define RegFlat     ((unsigned char) ~0)
 928   signed char dw2_regnum[2];
 929 #define Dw2Inval (-1)
 930 }
 931 reg_entry;
 932
 933 /* Entries in i386_regtab.  */
 934 #define REGNAM_AL 1
 935 #define REGNAM_AX 25
 936 #define REGNAM_EAX 41
 937
 938 extern const reg_entry i386_regtab[];
 939 extern const unsigned int i386_regtab_size;
 940
 941 typedef struct
 942 {
 943   char *seg_name;
 944   unsigned int seg_prefix;
 945 }
 946 seg_entry;
 947
 948 extern const seg_entry cs;
 949 extern const seg_entry ds;
 950 extern const seg_entry ss;
 951 extern const seg_entry es;
 952 extern const seg_entry fs;
 953 extern const seg_entry gs;