opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* PCOMMIT instruction required */
 192   CpuPCOMMIT,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* mwaitx instruction required */
 198   CpuMWAITX,
 199   /* Clzero instruction required */
 200   CpuCLZERO,
 201   /* OSPKE instruction required */
 202   CpuOSPKE,
 203   /* RDPID instruction required */
 204   CpuRDPID,
 205   /* 64bit support required  */
 206   Cpu64,
 207   /* Not supported in the 64bit mode  */
 208   CpuNo64,
 209   /* AMD64 support required  */
 210   CpuAMD64,
 211   /* Intel64 support required  */
 212   CpuIntel64,
 213   /* The last bitfield in i386_cpu_flags.  */
 214   CpuMax = CpuNo64
 215 };
 216
 217 #define CpuNumOfUints \
 218   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 219 #define CpuNumOfBits \
 220   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 221
 222 /* If you get a compiler error for zero width of the unused field,
 223    comment it out.  */
 224 #define CpuUnused       (CpuMax + 1)
 225
 226 /* We can check if an instruction is available with array instead
 227    of bitfield. */
 228 typedef union i386_cpu_flags
 229 {
 230   struct
 231     {
 232       unsigned int cpui186:1;
 233       unsigned int cpui286:1;
 234       unsigned int cpui386:1;
 235       unsigned int cpui486:1;
 236       unsigned int cpui586:1;
 237       unsigned int cpui686:1;
 238       unsigned int cpuclflush:1;
 239       unsigned int cpunop:1;
 240       unsigned int cpusyscall:1;
 241       unsigned int cpu8087:1;
 242       unsigned int cpu287:1;
 243       unsigned int cpu387:1;
 244       unsigned int cpu687:1;
 245       unsigned int cpufisttp:1;
 246       unsigned int cpummx:1;
 247       unsigned int cpusse:1;
 248       unsigned int cpusse2:1;
 249       unsigned int cpua3dnow:1;
 250       unsigned int cpua3dnowa:1;
 251       unsigned int cpusse3:1;
 252       unsigned int cpupadlock:1;
 253       unsigned int cpusvme:1;
 254       unsigned int cpuvmx:1;
 255       unsigned int cpusmx:1;
 256       unsigned int cpussse3:1;
 257       unsigned int cpusse4a:1;
 258       unsigned int cpuabm:1;
 259       unsigned int cpusse4_1:1;
 260       unsigned int cpusse4_2:1;
 261       unsigned int cpuavx:1;
 262       unsigned int cpuavx2:1;
 263       unsigned int cpuavx512f:1;
 264       unsigned int cpuavx512cd:1;
 265       unsigned int cpuavx512er:1;
 266       unsigned int cpuavx512pf:1;
 267       unsigned int cpuavx512vl:1;
 268       unsigned int cpuavx512dq:1;
 269       unsigned int cpuavx512bw:1;
 270       unsigned int cpul1om:1;
 271       unsigned int cpuk1om:1;
 272       unsigned int cpuiamcu:1;
 273       unsigned int cpuxsave:1;
 274       unsigned int cpuxsaveopt:1;
 275       unsigned int cpuaes:1;
 276       unsigned int cpupclmul:1;
 277       unsigned int cpufma:1;
 278       unsigned int cpufma4:1;
 279       unsigned int cpuxop:1;
 280       unsigned int cpulwp:1;
 281       unsigned int cpubmi:1;
 282       unsigned int cputbm:1;
 283       unsigned int cpumovbe:1;
 284       unsigned int cpucx16:1;
 285       unsigned int cpuept:1;
 286       unsigned int cpurdtscp:1;
 287       unsigned int cpufsgsbase:1;
 288       unsigned int cpurdrnd:1;
 289       unsigned int cpuf16c:1;
 290       unsigned int cpubmi2:1;
 291       unsigned int cpulzcnt:1;
 292       unsigned int cpuhle:1;
 293       unsigned int cpurtm:1;
 294       unsigned int cpuinvpcid:1;
 295       unsigned int cpuvmfunc:1;
 296       unsigned int cpumpx:1;
 297       unsigned int cpulm:1;
 298       unsigned int cpurdseed:1;
 299       unsigned int cpuadx:1;
 300       unsigned int cpuprfchw:1;
 301       unsigned int cpusmap:1;
 302       unsigned int cpusha:1;
 303       unsigned int cpuvrex:1;
 304       unsigned int cpuclflushopt:1;
 305       unsigned int cpuxsaves:1;
 306       unsigned int cpuxsavec:1;
 307       unsigned int cpuprefetchwt1:1;
 308       unsigned int cpuse1:1;
 309       unsigned int cpuclwb:1;
 310       unsigned int cpupcommit:1;
 311       unsigned int cpuavx512ifma:1;
 312       unsigned int cpuavx512vbmi:1;
 313       unsigned int cpumwaitx:1;
 314       unsigned int cpuclzero:1;
 315       unsigned int cpuospke:1;
 316       unsigned int cpurdpid:1;
 317       unsigned int cpu64:1;
 318       unsigned int cpuno64:1;
 319       unsigned int cpuamd64:1;
 320       unsigned int cpuintel64:1;
 321 #ifdef CpuUnused
 322       unsigned int unused:(CpuNumOfBits - CpuUnused);
 323 #endif
 324     } bitfield;
 325   unsigned int array[CpuNumOfUints];
 326 } i386_cpu_flags;
 327
 328 /* Position of opcode_modifier bits.  */
 329
 330 enum
 331 {
 332   /* has direction bit. */
 333   D = 0,
 334   /* set if operands can be words or dwords encoded the canonical way */
 335   W,
 336   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 337      operand in encoding.  */
 338   S,
 339   /* insn has a modrm byte. */
 340   Modrm,
 341   /* register is in low 3 bits of opcode */
 342   ShortForm,
 343   /* special case for jump insns.  */
 344   Jump,
 345   /* call and jump */
 346   JumpDword,
 347   /* loop and jecxz */
 348   JumpByte,
 349   /* special case for intersegment leaps/calls */
 350   JumpInterSegment,
 351   /* FP insn memory format bit, sized by 0x4 */
 352   FloatMF,
 353   /* src/dest swap for floats. */
 354   FloatR,
 355   /* has float insn direction bit. */
 356   FloatD,
 357   /* needs size prefix if in 32-bit mode */
 358   Size16,
 359   /* needs size prefix if in 16-bit mode */
 360   Size32,
 361   /* needs size prefix if in 64-bit mode */
 362   Size64,
 363   /* check register size.  */
 364   CheckRegSize,
 365   /* instruction ignores operand size prefix and in Intel mode ignores
 366      mnemonic size suffix check.  */
 367   IgnoreSize,
 368   /* default insn size depends on mode */
 369   DefaultSize,
 370   /* b suffix on instruction illegal */
 371   No_bSuf,
 372   /* w suffix on instruction illegal */
 373   No_wSuf,
 374   /* l suffix on instruction illegal */
 375   No_lSuf,
 376   /* s suffix on instruction illegal */
 377   No_sSuf,
 378   /* q suffix on instruction illegal */
 379   No_qSuf,
 380   /* long double suffix on instruction illegal */
 381   No_ldSuf,
 382   /* instruction needs FWAIT */
 383   FWait,
 384   /* quick test for string instructions */
 385   IsString,
 386   /* quick test if branch instruction is MPX supported */
 387   BNDPrefixOk,
 388   /* quick test for lockable instructions */
 389   IsLockable,
 390   /* fake an extra reg operand for clr, imul and special register
 391      processing for some instructions.  */
 392   RegKludge,
 393   /* The first operand must be xmm0 */
 394   FirstXmm0,
 395   /* An implicit xmm0 as the first operand */
 396   Implicit1stXmm0,
 397   /* The HLE prefix is OK:
 398      1. With a LOCK prefix.
 399      2. With or without a LOCK prefix.
 400      3. With a RELEASE (0xf3) prefix.
 401    */
 402 #define HLEPrefixNone           0
 403 #define HLEPrefixLock           1
 404 #define HLEPrefixAny            2
 405 #define HLEPrefixRelease        3
 406   HLEPrefixOk,
 407   /* An instruction on which a "rep" prefix is acceptable.  */
 408   RepPrefixOk,
 409   /* Convert to DWORD */
 410   ToDword,
 411   /* Convert to QWORD */
 412   ToQword,
 413   /* Address prefix changes operand 0 */
 414   AddrPrefixOp0,
 415   /* opcode is a prefix */
 416   IsPrefix,
 417   /* instruction has extension in 8 bit imm */
 418   ImmExt,
 419   /* instruction don't need Rex64 prefix.  */
 420   NoRex64,
 421   /* instruction require Rex64 prefix.  */
 422   Rex64,
 423   /* deprecated fp insn, gets a warning */
 424   Ugh,
 425   /* insn has VEX prefix:
 426         1: 128bit VEX prefix.
 427         2: 256bit VEX prefix.
 428         3: Scalar VEX prefix.
 429    */
 430 #define VEX128          1
 431 #define VEX256          2
 432 #define VEXScalar       3
 433   Vex,
 434   /* How to encode VEX.vvvv:
 435      0: VEX.vvvv must be 1111b.
 436      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 437         the content of source registers will be preserved.
 438         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 439         where the content of first source register will be overwritten
 440         by the result.
 441         VEX.NDD2.  The second destination register operand is encoded in
 442         VEX.vvvv for instructions with 2 destination register operands.
 443         For assembler, there are no difference between VEX.NDS, VEX.DDS
 444         and VEX.NDD2.
 445      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 446      instructions with 1 destination register operand.
 447      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 448         of the operands can access a memory location.
 449    */
 450 #define VEXXDS  1
 451 #define VEXNDD  2
 452 #define VEXLWP  3
 453   VexVVVV,
 454   /* How the VEX.W bit is used:
 455      0: Set by the REX.W bit.
 456      1: VEX.W0.  Should always be 0.
 457      2: VEX.W1.  Should always be 1.
 458    */
 459 #define VEXW0   1
 460 #define VEXW1   2
 461   VexW,
 462   /* VEX opcode prefix:
 463      0: VEX 0x0F opcode prefix.
 464      1: VEX 0x0F38 opcode prefix.
 465      2: VEX 0x0F3A opcode prefix
 466      3: XOP 0x08 opcode prefix.
 467      4: XOP 0x09 opcode prefix
 468      5: XOP 0x0A opcode prefix.
 469    */
 470 #define VEX0F           0
 471 #define VEX0F38         1
 472 #define VEX0F3A         2
 473 #define XOP08           3
 474 #define XOP09           4
 475 #define XOP0A           5
 476   VexOpcode,
 477   /* number of VEX source operands:
 478      0: <= 2 source operands.
 479      1: 2 XOP source operands.
 480      2: 3 source operands.
 481    */
 482 #define XOP2SOURCES     1
 483 #define VEX3SOURCES     2
 484   VexSources,
 485   /* instruction has VEX 8 bit imm */
 486   VexImmExt,
 487   /* Instruction with vector SIB byte:
 488         1: 128bit vector register.
 489         2: 256bit vector register.
 490         3: 512bit vector register.
 491    */
 492 #define VecSIB128       1
 493 #define VecSIB256       2
 494 #define VecSIB512       3
 495   VecSIB,
 496   /* SSE to AVX support required */
 497   SSE2AVX,
 498   /* No AVX equivalent */
 499   NoAVX,
 500
 501   /* insn has EVEX prefix:
 502         1: 512bit EVEX prefix.
 503         2: 128bit EVEX prefix.
 504         3: 256bit EVEX prefix.
 505         4: Length-ignored (LIG) EVEX prefix.
 506    */
 507 #define EVEX512                1
 508 #define EVEX128                2
 509 #define EVEX256                3
 510 #define EVEXLIG                4
 511   EVex,
 512
 513   /* AVX512 masking support:
 514         1: Zeroing-masking.
 515         2: Merging-masking.
 516         3: Both zeroing and merging masking.
 517    */
 518 #define ZEROING_MASKING 1
 519 #define MERGING_MASKING 2
 520 #define BOTH_MASKING    3
 521   Masking,
 522
 523   /* Input element size of vector insn:
 524         0: 32bit.
 525         1: 64bit.
 526    */
 527   VecESize,
 528
 529   /* Broadcast factor.
 530         0: No broadcast.
 531         1: 1to16 broadcast.
 532         2: 1to8 broadcast.
 533    */
 534 #define NO_BROADCAST    0
 535 #define BROADCAST_1TO16 1
 536 #define BROADCAST_1TO8  2
 537 #define BROADCAST_1TO4  3
 538 #define BROADCAST_1TO2  4
 539   Broadcast,
 540
 541   /* Static rounding control is supported.  */
 542   StaticRounding,
 543
 544   /* Supress All Exceptions is supported.  */
 545   SAE,
 546
 547   /* Copressed Disp8*N attribute.  */
 548   Disp8MemShift,
 549
 550   /* Default mask isn't allowed.  */
 551   NoDefMask,
 552
 553   /* Compatible with old (<= 2.8.1) versions of gcc  */
 554   OldGcc,
 555   /* AT&T mnemonic.  */
 556   ATTMnemonic,
 557   /* AT&T syntax.  */
 558   ATTSyntax,
 559   /* Intel syntax.  */
 560   IntelSyntax,
 561   /* The last bitfield in i386_opcode_modifier.  */
 562   Opcode_Modifier_Max
 563 };
 564
 565 typedef struct i386_opcode_modifier
 566 {
 567   unsigned int d:1;
 568   unsigned int w:1;
 569   unsigned int s:1;
 570   unsigned int modrm:1;
 571   unsigned int shortform:1;
 572   unsigned int jump:1;
 573   unsigned int jumpdword:1;
 574   unsigned int jumpbyte:1;
 575   unsigned int jumpintersegment:1;
 576   unsigned int floatmf:1;
 577   unsigned int floatr:1;
 578   unsigned int floatd:1;
 579   unsigned int size16:1;
 580   unsigned int size32:1;
 581   unsigned int size64:1;
 582   unsigned int checkregsize:1;
 583   unsigned int ignoresize:1;
 584   unsigned int defaultsize:1;
 585   unsigned int no_bsuf:1;
 586   unsigned int no_wsuf:1;
 587   unsigned int no_lsuf:1;
 588   unsigned int no_ssuf:1;
 589   unsigned int no_qsuf:1;
 590   unsigned int no_ldsuf:1;
 591   unsigned int fwait:1;
 592   unsigned int isstring:1;
 593   unsigned int bndprefixok:1;
 594   unsigned int islockable:1;
 595   unsigned int regkludge:1;
 596   unsigned int firstxmm0:1;
 597   unsigned int implicit1stxmm0:1;
 598   unsigned int hleprefixok:2;
 599   unsigned int repprefixok:1;
 600   unsigned int todword:1;
 601   unsigned int toqword:1;
 602   unsigned int addrprefixop0:1;
 603   unsigned int isprefix:1;
 604   unsigned int immext:1;
 605   unsigned int norex64:1;
 606   unsigned int rex64:1;
 607   unsigned int ugh:1;
 608   unsigned int vex:2;
 609   unsigned int vexvvvv:2;
 610   unsigned int vexw:2;
 611   unsigned int vexopcode:3;
 612   unsigned int vexsources:2;
 613   unsigned int veximmext:1;
 614   unsigned int vecsib:2;
 615   unsigned int sse2avx:1;
 616   unsigned int noavx:1;
 617   unsigned int evex:3;
 618   unsigned int masking:2;
 619   unsigned int vecesize:1;
 620   unsigned int broadcast:3;
 621   unsigned int staticrounding:1;
 622   unsigned int sae:1;
 623   unsigned int disp8memshift:3;
 624   unsigned int nodefmask:1;
 625   unsigned int oldgcc:1;
 626   unsigned int attmnemonic:1;
 627   unsigned int attsyntax:1;
 628   unsigned int intelsyntax:1;
 629 } i386_opcode_modifier;
 630
 631 /* Position of operand_type bits.  */
 632
 633 enum
 634 {
 635   /* 8bit register */
 636   Reg8 = 0,
 637   /* 16bit register */
 638   Reg16,
 639   /* 32bit register */
 640   Reg32,
 641   /* 64bit register */
 642   Reg64,
 643   /* Floating pointer stack register */
 644   FloatReg,
 645   /* MMX register */
 646   RegMMX,
 647   /* SSE register */
 648   RegXMM,
 649   /* AVX registers */
 650   RegYMM,
 651   /* AVX512 registers */
 652   RegZMM,
 653   /* Vector Mask registers */
 654   RegMask,
 655   /* Control register */
 656   Control,
 657   /* Debug register */
 658   Debug,
 659   /* Test register */
 660   Test,
 661   /* 2 bit segment register */
 662   SReg2,
 663   /* 3 bit segment register */
 664   SReg3,
 665   /* 1 bit immediate */
 666   Imm1,
 667   /* 8 bit immediate */
 668   Imm8,
 669   /* 8 bit immediate sign extended */
 670   Imm8S,
 671   /* 16 bit immediate */
 672   Imm16,
 673   /* 32 bit immediate */
 674   Imm32,
 675   /* 32 bit immediate sign extended */
 676   Imm32S,
 677   /* 64 bit immediate */
 678   Imm64,
 679   /* 8bit/16bit/32bit displacements are used in different ways,
 680      depending on the instruction.  For jumps, they specify the
 681      size of the PC relative displacement, for instructions with
 682      memory operand, they specify the size of the offset relative
 683      to the base register, and for instructions with memory offset
 684      such as `mov 1234,%al' they specify the size of the offset
 685      relative to the segment base.  */
 686   /* 8 bit displacement */
 687   Disp8,
 688   /* 16 bit displacement */
 689   Disp16,
 690   /* 32 bit displacement */
 691   Disp32,
 692   /* 32 bit signed displacement */
 693   Disp32S,
 694   /* 64 bit displacement */
 695   Disp64,
 696   /* Accumulator %al/%ax/%eax/%rax */
 697   Acc,
 698   /* Floating pointer top stack register %st(0) */
 699   FloatAcc,
 700   /* Register which can be used for base or index in memory operand.  */
 701   BaseIndex,
 702   /* Register to hold in/out port addr = dx */
 703   InOutPortReg,
 704   /* Register to hold shift count = cl */
 705   ShiftCount,
 706   /* Absolute address for jump.  */
 707   JumpAbsolute,
 708   /* String insn operand with fixed es segment */
 709   EsSeg,
 710   /* RegMem is for instructions with a modrm byte where the register
 711      destination operand should be encoded in the mod and regmem fields.
 712      Normally, it will be encoded in the reg field. We add a RegMem
 713      flag to the destination register operand to indicate that it should
 714      be encoded in the regmem field.  */
 715   RegMem,
 716   /* Memory.  */
 717   Mem,
 718   /* BYTE memory. */
 719   Byte,
 720   /* WORD memory. 2 byte */
 721   Word,
 722   /* DWORD memory. 4 byte */
 723   Dword,
 724   /* FWORD memory. 6 byte */
 725   Fword,
 726   /* QWORD memory. 8 byte */
 727   Qword,
 728   /* TBYTE memory. 10 byte */
 729   Tbyte,
 730   /* XMMWORD memory. */
 731   Xmmword,
 732   /* YMMWORD memory. */
 733   Ymmword,
 734   /* ZMMWORD memory.  */
 735   Zmmword,
 736   /* Unspecified memory size.  */
 737   Unspecified,
 738   /* Any memory size.  */
 739   Anysize,
 740
 741   /* Vector 4 bit immediate.  */
 742   Vec_Imm4,
 743
 744   /* Bound register.  */
 745   RegBND,
 746
 747   /* Vector 8bit displacement */
 748   Vec_Disp8,
 749
 750   /* The last bitfield in i386_operand_type.  */
 751   OTMax
 752 };
 753
 754 #define OTNumOfUints \
 755   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 756 #define OTNumOfBits \
 757   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 758
 759 /* If you get a compiler error for zero width of the unused field,
 760    comment it out.  */
 761 #define OTUnused                (OTMax + 1)
 762
 763 typedef union i386_operand_type
 764 {
 765   struct
 766     {
 767       unsigned int reg8:1;
 768       unsigned int reg16:1;
 769       unsigned int reg32:1;
 770       unsigned int reg64:1;
 771       unsigned int floatreg:1;
 772       unsigned int regmmx:1;
 773       unsigned int regxmm:1;
 774       unsigned int regymm:1;
 775       unsigned int regzmm:1;
 776       unsigned int regmask:1;
 777       unsigned int control:1;
 778       unsigned int debug:1;
 779       unsigned int test:1;
 780       unsigned int sreg2:1;
 781       unsigned int sreg3:1;
 782       unsigned int imm1:1;
 783       unsigned int imm8:1;
 784       unsigned int imm8s:1;
 785       unsigned int imm16:1;
 786       unsigned int imm32:1;
 787       unsigned int imm32s:1;
 788       unsigned int imm64:1;
 789       unsigned int disp8:1;
 790       unsigned int disp16:1;
 791       unsigned int disp32:1;
 792       unsigned int disp32s:1;
 793       unsigned int disp64:1;
 794       unsigned int acc:1;
 795       unsigned int floatacc:1;
 796       unsigned int baseindex:1;
 797       unsigned int inoutportreg:1;
 798       unsigned int shiftcount:1;
 799       unsigned int jumpabsolute:1;
 800       unsigned int esseg:1;
 801       unsigned int regmem:1;
 802       unsigned int mem:1;
 803       unsigned int byte:1;
 804       unsigned int word:1;
 805       unsigned int dword:1;
 806       unsigned int fword:1;
 807       unsigned int qword:1;
 808       unsigned int tbyte:1;
 809       unsigned int xmmword:1;
 810       unsigned int ymmword:1;
 811       unsigned int zmmword:1;
 812       unsigned int unspecified:1;
 813       unsigned int anysize:1;
 814       unsigned int vec_imm4:1;
 815       unsigned int regbnd:1;
 816       unsigned int vec_disp8:1;
 817 #ifdef OTUnused
 818       unsigned int unused:(OTNumOfBits - OTUnused);
 819 #endif
 820     } bitfield;
 821   unsigned int array[OTNumOfUints];
 822 } i386_operand_type;
 823
 824 typedef struct insn_template
 825 {
 826   /* instruction name sans width suffix ("mov" for movl insns) */
 827   char *name;
 828
 829   /* how many operands */
 830   unsigned int operands;
 831
 832   /* base_opcode is the fundamental opcode byte without optional
 833      prefix(es).  */
 834   unsigned int base_opcode;
 835 #define Opcode_D        0x2 /* Direction bit:
 836                                set if Reg --> Regmem;
 837                                unset if Regmem --> Reg. */
 838 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 839 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 840
 841   /* extension_opcode is the 3 bit extension for group <n> insns.
 842      This field is also used to store the 8-bit opcode suffix for the
 843      AMD 3DNow! instructions.
 844      If this template has no extension opcode (the usual case) use None
 845      Instructions */
 846   unsigned int extension_opcode;
 847 #define None 0xffff             /* If no extension_opcode is possible.  */
 848
 849   /* Opcode length.  */
 850   unsigned char opcode_length;
 851
 852   /* cpu feature flags */
 853   i386_cpu_flags cpu_flags;
 854
 855   /* the bits in opcode_modifier are used to generate the final opcode from
 856      the base_opcode.  These bits also are used to detect alternate forms of
 857      the same instruction */
 858   i386_opcode_modifier opcode_modifier;
 859
 860   /* operand_types[i] describes the type of operand i.  This is made
 861      by OR'ing together all of the possible type masks.  (e.g.
 862      'operand_types[i] = Reg|Imm' specifies that operand i can be
 863      either a register or an immediate operand.  */
 864   i386_operand_type operand_types[MAX_OPERANDS];
 865 }
 866 insn_template;
 867
 868 extern const insn_template i386_optab[];
 869
 870 /* these are for register name --> number & type hash lookup */
 871 typedef struct
 872 {
 873   char *reg_name;
 874   i386_operand_type reg_type;
 875   unsigned char reg_flags;
 876 #define RegRex      0x1  /* Extended register.  */
 877 #define RegRex64    0x2  /* Extended 8 bit register.  */
 878 #define RegVRex     0x4  /* Extended vector register.  */
 879   unsigned char reg_num;
 880 #define RegRip  ((unsigned char ) ~0)
 881 #define RegEip  (RegRip - 1)
 882 /* EIZ and RIZ are fake index registers.  */
 883 #define RegEiz  (RegEip - 1)
 884 #define RegRiz  (RegEiz - 1)
 885 /* FLAT is a fake segment register (Intel mode).  */
 886 #define RegFlat     ((unsigned char) ~0)
 887   signed char dw2_regnum[2];
 888 #define Dw2Inval (-1)
 889 }
 890 reg_entry;
 891
 892 /* Entries in i386_regtab.  */
 893 #define REGNAM_AL 1
 894 #define REGNAM_AX 25
 895 #define REGNAM_EAX 41
 896
 897 extern const reg_entry i386_regtab[];
 898 extern const unsigned int i386_regtab_size;
 899
 900 typedef struct
 901 {
 902   char *seg_name;
 903   unsigned int seg_prefix;
 904 }
 905 seg_entry;
 906
 907 extern const seg_entry cs;
 908 extern const seg_entry ds;
 909 extern const seg_entry ss;
 910 extern const seg_entry es;
 911 extern const seg_entry fs;
 912 extern const seg_entry gs;