opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* PCONFIG instructions required */
 229   CpuPCONFIG,
 230   /* WAITPKG instructions required */
 231   CpuWAITPKG,
 232   /* CLDEMOTE instruction required */
 233   CpuCLDEMOTE,
 234   /* MOVDIRI instruction support required */
 235   CpuMOVDIRI,
 236   /* MOVDIRR64B instruction required */
 237   CpuMOVDIR64B,
 238   /* MMX register support required */
 239   CpuRegMMX,
 240   /* XMM register support required */
 241   CpuRegXMM,
 242   /* YMM register support required */
 243   CpuRegYMM,
 244   /* ZMM register support required */
 245   CpuRegZMM,
 246   /* Mask register support required */
 247   CpuRegMask,
 248   /* 64bit support required  */
 249   Cpu64,
 250   /* Not supported in the 64bit mode  */
 251   CpuNo64,
 252   /* The last bitfield in i386_cpu_flags.  */
 253   CpuMax = CpuNo64
 254 };
 255
 256 #define CpuNumOfUints \
 257   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 258 #define CpuNumOfBits \
 259   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 260
 261 /* If you get a compiler error for zero width of the unused field,
 262    comment it out.  */
 263 #define CpuUnused       (CpuMax + 1)
 264
 265 /* We can check if an instruction is available with array instead
 266    of bitfield. */
 267 typedef union i386_cpu_flags
 268 {
 269   struct
 270     {
 271       unsigned int cpui186:1;
 272       unsigned int cpui286:1;
 273       unsigned int cpui386:1;
 274       unsigned int cpui486:1;
 275       unsigned int cpui586:1;
 276       unsigned int cpui686:1;
 277       unsigned int cpuclflush:1;
 278       unsigned int cpunop:1;
 279       unsigned int cpusyscall:1;
 280       unsigned int cpu8087:1;
 281       unsigned int cpu287:1;
 282       unsigned int cpu387:1;
 283       unsigned int cpu687:1;
 284       unsigned int cpufisttp:1;
 285       unsigned int cpummx:1;
 286       unsigned int cpusse:1;
 287       unsigned int cpusse2:1;
 288       unsigned int cpua3dnow:1;
 289       unsigned int cpua3dnowa:1;
 290       unsigned int cpusse3:1;
 291       unsigned int cpupadlock:1;
 292       unsigned int cpusvme:1;
 293       unsigned int cpuvmx:1;
 294       unsigned int cpusmx:1;
 295       unsigned int cpussse3:1;
 296       unsigned int cpusse4a:1;
 297       unsigned int cpuabm:1;
 298       unsigned int cpusse4_1:1;
 299       unsigned int cpusse4_2:1;
 300       unsigned int cpuavx:1;
 301       unsigned int cpuavx2:1;
 302       unsigned int cpuavx512f:1;
 303       unsigned int cpuavx512cd:1;
 304       unsigned int cpuavx512er:1;
 305       unsigned int cpuavx512pf:1;
 306       unsigned int cpuavx512vl:1;
 307       unsigned int cpuavx512dq:1;
 308       unsigned int cpuavx512bw:1;
 309       unsigned int cpul1om:1;
 310       unsigned int cpuk1om:1;
 311       unsigned int cpuiamcu:1;
 312       unsigned int cpuxsave:1;
 313       unsigned int cpuxsaveopt:1;
 314       unsigned int cpuaes:1;
 315       unsigned int cpupclmul:1;
 316       unsigned int cpufma:1;
 317       unsigned int cpufma4:1;
 318       unsigned int cpuxop:1;
 319       unsigned int cpulwp:1;
 320       unsigned int cpubmi:1;
 321       unsigned int cputbm:1;
 322       unsigned int cpumovbe:1;
 323       unsigned int cpucx16:1;
 324       unsigned int cpuept:1;
 325       unsigned int cpurdtscp:1;
 326       unsigned int cpufsgsbase:1;
 327       unsigned int cpurdrnd:1;
 328       unsigned int cpuf16c:1;
 329       unsigned int cpubmi2:1;
 330       unsigned int cpulzcnt:1;
 331       unsigned int cpuhle:1;
 332       unsigned int cpurtm:1;
 333       unsigned int cpuinvpcid:1;
 334       unsigned int cpuvmfunc:1;
 335       unsigned int cpumpx:1;
 336       unsigned int cpulm:1;
 337       unsigned int cpurdseed:1;
 338       unsigned int cpuadx:1;
 339       unsigned int cpuprfchw:1;
 340       unsigned int cpusmap:1;
 341       unsigned int cpusha:1;
 342       unsigned int cpuvrex:1;
 343       unsigned int cpuclflushopt:1;
 344       unsigned int cpuxsaves:1;
 345       unsigned int cpuxsavec:1;
 346       unsigned int cpuprefetchwt1:1;
 347       unsigned int cpuse1:1;
 348       unsigned int cpuclwb:1;
 349       unsigned int cpuavx512ifma:1;
 350       unsigned int cpuavx512vbmi:1;
 351       unsigned int cpuavx512_4fmaps:1;
 352       unsigned int cpuavx512_4vnniw:1;
 353       unsigned int cpuavx512_vpopcntdq:1;
 354       unsigned int cpuavx512_vbmi2:1;
 355       unsigned int cpuavx512_vnni:1;
 356       unsigned int cpuavx512_bitalg:1;
 357       unsigned int cpumwaitx:1;
 358       unsigned int cpuclzero:1;
 359       unsigned int cpuospke:1;
 360       unsigned int cpurdpid:1;
 361       unsigned int cpuptwrite:1;
 362       unsigned int cpuibt:1;
 363       unsigned int cpushstk:1;
 364       unsigned int cpugfni:1;
 365       unsigned int cpuvaes:1;
 366       unsigned int cpuvpclmulqdq:1;
 367       unsigned int cpuwbnoinvd:1;
 368       unsigned int cpupconfig:1;
 369       unsigned int cpuwaitpkg:1;
 370       unsigned int cpucldemote:1;
 371       unsigned int cpumovdiri:1;
 372       unsigned int cpumovdir64b:1;
 373       unsigned int cpuregmmx:1;
 374       unsigned int cpuregxmm:1;
 375       unsigned int cpuregymm:1;
 376       unsigned int cpuregzmm:1;
 377       unsigned int cpuregmask:1;
 378       unsigned int cpu64:1;
 379       unsigned int cpuno64:1;
 380 #ifdef CpuUnused
 381       unsigned int unused:(CpuNumOfBits - CpuUnused);
 382 #endif
 383     } bitfield;
 384   unsigned int array[CpuNumOfUints];
 385 } i386_cpu_flags;
 386
 387 /* Position of opcode_modifier bits.  */
 388
 389 enum
 390 {
 391   /* has direction bit. */
 392   D = 0,
 393   /* set if operands can be words or dwords encoded the canonical way */
 394   W,
 395   /* load form instruction. Must be placed before store form.  */
 396   Load,
 397   /* insn has a modrm byte. */
 398   Modrm,
 399   /* register is in low 3 bits of opcode */
 400   ShortForm,
 401   /* special case for jump insns.  */
 402   Jump,
 403   /* call and jump */
 404   JumpDword,
 405   /* loop and jecxz */
 406   JumpByte,
 407   /* special case for intersegment leaps/calls */
 408   JumpInterSegment,
 409   /* FP insn memory format bit, sized by 0x4 */
 410   FloatMF,
 411   /* src/dest swap for floats. */
 412   FloatR,
 413   /* needs size prefix if in 32-bit mode */
 414   Size16,
 415   /* needs size prefix if in 16-bit mode */
 416   Size32,
 417   /* needs size prefix if in 64-bit mode */
 418   Size64,
 419   /* check register size.  */
 420   CheckRegSize,
 421   /* instruction ignores operand size prefix and in Intel mode ignores
 422      mnemonic size suffix check.  */
 423   IgnoreSize,
 424   /* default insn size depends on mode */
 425   DefaultSize,
 426   /* b suffix on instruction illegal */
 427   No_bSuf,
 428   /* w suffix on instruction illegal */
 429   No_wSuf,
 430   /* l suffix on instruction illegal */
 431   No_lSuf,
 432   /* s suffix on instruction illegal */
 433   No_sSuf,
 434   /* q suffix on instruction illegal */
 435   No_qSuf,
 436   /* long double suffix on instruction illegal */
 437   No_ldSuf,
 438   /* instruction needs FWAIT */
 439   FWait,
 440   /* quick test for string instructions */
 441   IsString,
 442   /* quick test if branch instruction is MPX supported */
 443   BNDPrefixOk,
 444   /* quick test if NOTRACK prefix is supported */
 445   NoTrackPrefixOk,
 446   /* quick test for lockable instructions */
 447   IsLockable,
 448   /* fake an extra reg operand for clr, imul and special register
 449      processing for some instructions.  */
 450   RegKludge,
 451   /* An implicit xmm0 as the first operand */
 452   Implicit1stXmm0,
 453   /* The HLE prefix is OK:
 454      1. With a LOCK prefix.
 455      2. With or without a LOCK prefix.
 456      3. With a RELEASE (0xf3) prefix.
 457    */
 458 #define HLEPrefixNone           0
 459 #define HLEPrefixLock           1
 460 #define HLEPrefixAny            2
 461 #define HLEPrefixRelease        3
 462   HLEPrefixOk,
 463   /* An instruction on which a "rep" prefix is acceptable.  */
 464   RepPrefixOk,
 465   /* Convert to DWORD */
 466   ToDword,
 467   /* Convert to QWORD */
 468   ToQword,
 469   /* Address prefix changes operand 0 */
 470   AddrPrefixOp0,
 471   /* Address prefix changes register operand */
 472   AddrPrefixOpReg,
 473   /* opcode is a prefix */
 474   IsPrefix,
 475   /* instruction has extension in 8 bit imm */
 476   ImmExt,
 477   /* instruction don't need Rex64 prefix.  */
 478   NoRex64,
 479   /* instruction require Rex64 prefix.  */
 480   Rex64,
 481   /* deprecated fp insn, gets a warning */
 482   Ugh,
 483   /* insn has VEX prefix:
 484         1: 128bit VEX prefix (or operand dependent).
 485         2: 256bit VEX prefix.
 486         3: Scalar VEX prefix.
 487    */
 488 #define VEX128          1
 489 #define VEX256          2
 490 #define VEXScalar       3
 491   Vex,
 492   /* How to encode VEX.vvvv:
 493      0: VEX.vvvv must be 1111b.
 494      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 495         the content of source registers will be preserved.
 496         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 497         where the content of first source register will be overwritten
 498         by the result.
 499         VEX.NDD2.  The second destination register operand is encoded in
 500         VEX.vvvv for instructions with 2 destination register operands.
 501         For assembler, there are no difference between VEX.NDS, VEX.DDS
 502         and VEX.NDD2.
 503      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 504      instructions with 1 destination register operand.
 505      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 506         of the operands can access a memory location.
 507    */
 508 #define VEXXDS  1
 509 #define VEXNDD  2
 510 #define VEXLWP  3
 511   VexVVVV,
 512   /* How the VEX.W bit is used:
 513      0: Set by the REX.W bit.
 514      1: VEX.W0.  Should always be 0.
 515      2: VEX.W1.  Should always be 1.
 516    */
 517 #define VEXW0   1
 518 #define VEXW1   2
 519   VexW,
 520   /* VEX opcode prefix:
 521      0: VEX 0x0F opcode prefix.
 522      1: VEX 0x0F38 opcode prefix.
 523      2: VEX 0x0F3A opcode prefix
 524      3: XOP 0x08 opcode prefix.
 525      4: XOP 0x09 opcode prefix
 526      5: XOP 0x0A opcode prefix.
 527    */
 528 #define VEX0F           0
 529 #define VEX0F38         1
 530 #define VEX0F3A         2
 531 #define XOP08           3
 532 #define XOP09           4
 533 #define XOP0A           5
 534   VexOpcode,
 535   /* number of VEX source operands:
 536      0: <= 2 source operands.
 537      1: 2 XOP source operands.
 538      2: 3 source operands.
 539    */
 540 #define XOP2SOURCES     1
 541 #define VEX3SOURCES     2
 542   VexSources,
 543   /* Instruction with vector SIB byte:
 544         1: 128bit vector register.
 545         2: 256bit vector register.
 546         3: 512bit vector register.
 547    */
 548 #define VecSIB128       1
 549 #define VecSIB256       2
 550 #define VecSIB512       3
 551   VecSIB,
 552   /* SSE to AVX support required */
 553   SSE2AVX,
 554   /* No AVX equivalent */
 555   NoAVX,
 556
 557   /* insn has EVEX prefix:
 558         1: 512bit EVEX prefix.
 559         2: 128bit EVEX prefix.
 560         3: 256bit EVEX prefix.
 561         4: Length-ignored (LIG) EVEX prefix.
 562         5: Length determined from actual operands.
 563    */
 564 #define EVEX512                1
 565 #define EVEX128                2
 566 #define EVEX256                3
 567 #define EVEXLIG                4
 568 #define EVEXDYN                5
 569   EVex,
 570
 571   /* AVX512 masking support:
 572         1: Zeroing-masking.
 573         2: Merging-masking.
 574         3: Both zeroing and merging masking.
 575    */
 576 #define ZEROING_MASKING 1
 577 #define MERGING_MASKING 2
 578 #define BOTH_MASKING    3
 579   Masking,
 580
 581   Broadcast,
 582
 583   /* Static rounding control is supported.  */
 584   StaticRounding,
 585
 586   /* Supress All Exceptions is supported.  */
 587   SAE,
 588
 589   /* Copressed Disp8*N attribute.  */
 590   Disp8MemShift,
 591
 592   /* Default mask isn't allowed.  */
 593   NoDefMask,
 594
 595   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 596      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 597    */
 598   ImplicitQuadGroup,
 599
 600   /* Support encoding optimization.  */
 601   Optimize,
 602
 603   /* AT&T mnemonic.  */
 604   ATTMnemonic,
 605   /* AT&T syntax.  */
 606   ATTSyntax,
 607   /* Intel syntax.  */
 608   IntelSyntax,
 609   /* AMD64.  */
 610   AMD64,
 611   /* Intel64.  */
 612   Intel64,
 613   /* The last bitfield in i386_opcode_modifier.  */
 614   Opcode_Modifier_Max
 615 };
 616
 617 typedef struct i386_opcode_modifier
 618 {
 619   unsigned int d:1;
 620   unsigned int w:1;
 621   unsigned int load:1;
 622   unsigned int modrm:1;
 623   unsigned int shortform:1;
 624   unsigned int jump:1;
 625   unsigned int jumpdword:1;
 626   unsigned int jumpbyte:1;
 627   unsigned int jumpintersegment:1;
 628   unsigned int floatmf:1;
 629   unsigned int floatr:1;
 630   unsigned int size16:1;
 631   unsigned int size32:1;
 632   unsigned int size64:1;
 633   unsigned int checkregsize:1;
 634   unsigned int ignoresize:1;
 635   unsigned int defaultsize:1;
 636   unsigned int no_bsuf:1;
 637   unsigned int no_wsuf:1;
 638   unsigned int no_lsuf:1;
 639   unsigned int no_ssuf:1;
 640   unsigned int no_qsuf:1;
 641   unsigned int no_ldsuf:1;
 642   unsigned int fwait:1;
 643   unsigned int isstring:1;
 644   unsigned int bndprefixok:1;
 645   unsigned int notrackprefixok:1;
 646   unsigned int islockable:1;
 647   unsigned int regkludge:1;
 648   unsigned int implicit1stxmm0:1;
 649   unsigned int hleprefixok:2;
 650   unsigned int repprefixok:1;
 651   unsigned int todword:1;
 652   unsigned int toqword:1;
 653   unsigned int addrprefixop0:1;
 654   unsigned int addrprefixopreg:1;
 655   unsigned int isprefix:1;
 656   unsigned int immext:1;
 657   unsigned int norex64:1;
 658   unsigned int rex64:1;
 659   unsigned int ugh:1;
 660   unsigned int vex:2;
 661   unsigned int vexvvvv:2;
 662   unsigned int vexw:2;
 663   unsigned int vexopcode:3;
 664   unsigned int vexsources:2;
 665   unsigned int vecsib:2;
 666   unsigned int sse2avx:1;
 667   unsigned int noavx:1;
 668   unsigned int evex:3;
 669   unsigned int masking:2;
 670   unsigned int broadcast:1;
 671   unsigned int staticrounding:1;
 672   unsigned int sae:1;
 673   unsigned int disp8memshift:3;
 674   unsigned int nodefmask:1;
 675   unsigned int implicitquadgroup:1;
 676   unsigned int optimize:1;
 677   unsigned int attmnemonic:1;
 678   unsigned int attsyntax:1;
 679   unsigned int intelsyntax:1;
 680   unsigned int amd64:1;
 681   unsigned int intel64:1;
 682 } i386_opcode_modifier;
 683
 684 /* Position of operand_type bits.  */
 685
 686 enum
 687 {
 688   /* Register (qualified by Byte, Word, etc) */
 689   Reg = 0,
 690   /* MMX register */
 691   RegMMX,
 692   /* Vector registers */
 693   RegSIMD,
 694   /* Vector Mask registers */
 695   RegMask,
 696   /* Control register */
 697   Control,
 698   /* Debug register */
 699   Debug,
 700   /* Test register */
 701   Test,
 702   /* 2 bit segment register */
 703   SReg2,
 704   /* 3 bit segment register */
 705   SReg3,
 706   /* 1 bit immediate */
 707   Imm1,
 708   /* 8 bit immediate */
 709   Imm8,
 710   /* 8 bit immediate sign extended */
 711   Imm8S,
 712   /* 16 bit immediate */
 713   Imm16,
 714   /* 32 bit immediate */
 715   Imm32,
 716   /* 32 bit immediate sign extended */
 717   Imm32S,
 718   /* 64 bit immediate */
 719   Imm64,
 720   /* 8bit/16bit/32bit displacements are used in different ways,
 721      depending on the instruction.  For jumps, they specify the
 722      size of the PC relative displacement, for instructions with
 723      memory operand, they specify the size of the offset relative
 724      to the base register, and for instructions with memory offset
 725      such as `mov 1234,%al' they specify the size of the offset
 726      relative to the segment base.  */
 727   /* 8 bit displacement */
 728   Disp8,
 729   /* 16 bit displacement */
 730   Disp16,
 731   /* 32 bit displacement */
 732   Disp32,
 733   /* 32 bit signed displacement */
 734   Disp32S,
 735   /* 64 bit displacement */
 736   Disp64,
 737   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 738   Acc,
 739   /* Register which can be used for base or index in memory operand.  */
 740   BaseIndex,
 741   /* Register to hold in/out port addr = dx */
 742   InOutPortReg,
 743   /* Register to hold shift count = cl */
 744   ShiftCount,
 745   /* Absolute address for jump.  */
 746   JumpAbsolute,
 747   /* String insn operand with fixed es segment */
 748   EsSeg,
 749   /* RegMem is for instructions with a modrm byte where the register
 750      destination operand should be encoded in the mod and regmem fields.
 751      Normally, it will be encoded in the reg field. We add a RegMem
 752      flag to the destination register operand to indicate that it should
 753      be encoded in the regmem field.  */
 754   RegMem,
 755   /* Memory.  */
 756   Mem,
 757   /* BYTE memory. */
 758   Byte,
 759   /* WORD memory. 2 byte */
 760   Word,
 761   /* DWORD memory. 4 byte */
 762   Dword,
 763   /* FWORD memory. 6 byte */
 764   Fword,
 765   /* QWORD memory. 8 byte */
 766   Qword,
 767   /* TBYTE memory. 10 byte */
 768   Tbyte,
 769   /* XMMWORD memory. */
 770   Xmmword,
 771   /* YMMWORD memory. */
 772   Ymmword,
 773   /* ZMMWORD memory.  */
 774   Zmmword,
 775   /* Unspecified memory size.  */
 776   Unspecified,
 777   /* Any memory size.  */
 778   Anysize,
 779
 780   /* Vector 4 bit immediate.  */
 781   Vec_Imm4,
 782
 783   /* Bound register.  */
 784   RegBND,
 785
 786   /* The last bitfield in i386_operand_type.  */
 787   OTMax
 788 };
 789
 790 #define OTNumOfUints \
 791   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 792 #define OTNumOfBits \
 793   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 794
 795 /* If you get a compiler error for zero width of the unused field,
 796    comment it out.  */
 797 #define OTUnused                (OTMax + 1)
 798
 799 typedef union i386_operand_type
 800 {
 801   struct
 802     {
 803       unsigned int reg:1;
 804       unsigned int regmmx:1;
 805       unsigned int regsimd:1;
 806       unsigned int regmask:1;
 807       unsigned int control:1;
 808       unsigned int debug:1;
 809       unsigned int test:1;
 810       unsigned int sreg2:1;
 811       unsigned int sreg3:1;
 812       unsigned int imm1:1;
 813       unsigned int imm8:1;
 814       unsigned int imm8s:1;
 815       unsigned int imm16:1;
 816       unsigned int imm32:1;
 817       unsigned int imm32s:1;
 818       unsigned int imm64:1;
 819       unsigned int disp8:1;
 820       unsigned int disp16:1;
 821       unsigned int disp32:1;
 822       unsigned int disp32s:1;
 823       unsigned int disp64:1;
 824       unsigned int acc:1;
 825       unsigned int baseindex:1;
 826       unsigned int inoutportreg:1;
 827       unsigned int shiftcount:1;
 828       unsigned int jumpabsolute:1;
 829       unsigned int esseg:1;
 830       unsigned int regmem:1;
 831       unsigned int mem:1;
 832       unsigned int byte:1;
 833       unsigned int word:1;
 834       unsigned int dword:1;
 835       unsigned int fword:1;
 836       unsigned int qword:1;
 837       unsigned int tbyte:1;
 838       unsigned int xmmword:1;
 839       unsigned int ymmword:1;
 840       unsigned int zmmword:1;
 841       unsigned int unspecified:1;
 842       unsigned int anysize:1;
 843       unsigned int vec_imm4:1;
 844       unsigned int regbnd:1;
 845 #ifdef OTUnused
 846       unsigned int unused:(OTNumOfBits - OTUnused);
 847 #endif
 848     } bitfield;
 849   unsigned int array[OTNumOfUints];
 850 } i386_operand_type;
 851
 852 typedef struct insn_template
 853 {
 854   /* instruction name sans width suffix ("mov" for movl insns) */
 855   char *name;
 856
 857   /* how many operands */
 858   unsigned int operands;
 859
 860   /* base_opcode is the fundamental opcode byte without optional
 861      prefix(es).  */
 862   unsigned int base_opcode;
 863 #define Opcode_D        0x2 /* Direction bit:
 864                                set if Reg --> Regmem;
 865                                unset if Regmem --> Reg. */
 866 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 867 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 868
 869   /* extension_opcode is the 3 bit extension for group <n> insns.
 870      This field is also used to store the 8-bit opcode suffix for the
 871      AMD 3DNow! instructions.
 872      If this template has no extension opcode (the usual case) use None
 873      Instructions */
 874   unsigned int extension_opcode;
 875 #define None 0xffff             /* If no extension_opcode is possible.  */
 876
 877   /* Opcode length.  */
 878   unsigned char opcode_length;
 879
 880   /* cpu feature flags */
 881   i386_cpu_flags cpu_flags;
 882
 883   /* the bits in opcode_modifier are used to generate the final opcode from
 884      the base_opcode.  These bits also are used to detect alternate forms of
 885      the same instruction */
 886   i386_opcode_modifier opcode_modifier;
 887
 888   /* operand_types[i] describes the type of operand i.  This is made
 889      by OR'ing together all of the possible type masks.  (e.g.
 890      'operand_types[i] = Reg|Imm' specifies that operand i can be
 891      either a register or an immediate operand.  */
 892   i386_operand_type operand_types[MAX_OPERANDS];
 893 }
 894 insn_template;
 895
 896 extern const insn_template i386_optab[];
 897
 898 /* these are for register name --> number & type hash lookup */
 899 typedef struct
 900 {
 901   char *reg_name;
 902   i386_operand_type reg_type;
 903   unsigned char reg_flags;
 904 #define RegRex      0x1  /* Extended register.  */
 905 #define RegRex64    0x2  /* Extended 8 bit register.  */
 906 #define RegVRex     0x4  /* Extended vector register.  */
 907   unsigned char reg_num;
 908 #define RegRip  ((unsigned char ) ~0)
 909 #define RegEip  (RegRip - 1)
 910 /* EIZ and RIZ are fake index registers.  */
 911 #define RegEiz  (RegEip - 1)
 912 #define RegRiz  (RegEiz - 1)
 913 /* FLAT is a fake segment register (Intel mode).  */
 914 #define RegFlat     ((unsigned char) ~0)
 915   signed char dw2_regnum[2];
 916 #define Dw2Inval (-1)
 917 }
 918 reg_entry;
 919
 920 /* Entries in i386_regtab.  */
 921 #define REGNAM_AL 1
 922 #define REGNAM_AX 25
 923 #define REGNAM_EAX 41
 924
 925 extern const reg_entry i386_regtab[];
 926 extern const unsigned int i386_regtab_size;
 927
 928 typedef struct
 929 {
 930   char *seg_name;
 931   unsigned int seg_prefix;
 932 }
 933 seg_entry;
 934
 935 extern const seg_entry cs;
 936 extern const seg_entry ds;
 937 extern const seg_entry ss;
 938 extern const seg_entry es;
 939 extern const seg_entry fs;
 940 extern const seg_entry gs;