opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* PCONFIG instructions required */
 229   CpuPCONFIG,
 230   /* MMX register support required */
 231   CpuRegMMX,
 232   /* XMM register support required */
 233   CpuRegXMM,
 234   /* YMM register support required */
 235   CpuRegYMM,
 236   /* ZMM register support required */
 237   CpuRegZMM,
 238   /* Mask register support required */
 239   CpuRegMask,
 240   /* 64bit support required  */
 241   Cpu64,
 242   /* Not supported in the 64bit mode  */
 243   CpuNo64,
 244   /* The last bitfield in i386_cpu_flags.  */
 245   CpuMax = CpuNo64
 246 };
 247
 248 #define CpuNumOfUints \
 249   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 250 #define CpuNumOfBits \
 251   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 252
 253 /* If you get a compiler error for zero width of the unused field,
 254    comment it out.  */
 255 #define CpuUnused       (CpuMax + 1)
 256
 257 /* We can check if an instruction is available with array instead
 258    of bitfield. */
 259 typedef union i386_cpu_flags
 260 {
 261   struct
 262     {
 263       unsigned int cpui186:1;
 264       unsigned int cpui286:1;
 265       unsigned int cpui386:1;
 266       unsigned int cpui486:1;
 267       unsigned int cpui586:1;
 268       unsigned int cpui686:1;
 269       unsigned int cpuclflush:1;
 270       unsigned int cpunop:1;
 271       unsigned int cpusyscall:1;
 272       unsigned int cpu8087:1;
 273       unsigned int cpu287:1;
 274       unsigned int cpu387:1;
 275       unsigned int cpu687:1;
 276       unsigned int cpufisttp:1;
 277       unsigned int cpummx:1;
 278       unsigned int cpusse:1;
 279       unsigned int cpusse2:1;
 280       unsigned int cpua3dnow:1;
 281       unsigned int cpua3dnowa:1;
 282       unsigned int cpusse3:1;
 283       unsigned int cpupadlock:1;
 284       unsigned int cpusvme:1;
 285       unsigned int cpuvmx:1;
 286       unsigned int cpusmx:1;
 287       unsigned int cpussse3:1;
 288       unsigned int cpusse4a:1;
 289       unsigned int cpuabm:1;
 290       unsigned int cpusse4_1:1;
 291       unsigned int cpusse4_2:1;
 292       unsigned int cpuavx:1;
 293       unsigned int cpuavx2:1;
 294       unsigned int cpuavx512f:1;
 295       unsigned int cpuavx512cd:1;
 296       unsigned int cpuavx512er:1;
 297       unsigned int cpuavx512pf:1;
 298       unsigned int cpuavx512vl:1;
 299       unsigned int cpuavx512dq:1;
 300       unsigned int cpuavx512bw:1;
 301       unsigned int cpul1om:1;
 302       unsigned int cpuk1om:1;
 303       unsigned int cpuiamcu:1;
 304       unsigned int cpuxsave:1;
 305       unsigned int cpuxsaveopt:1;
 306       unsigned int cpuaes:1;
 307       unsigned int cpupclmul:1;
 308       unsigned int cpufma:1;
 309       unsigned int cpufma4:1;
 310       unsigned int cpuxop:1;
 311       unsigned int cpulwp:1;
 312       unsigned int cpubmi:1;
 313       unsigned int cputbm:1;
 314       unsigned int cpumovbe:1;
 315       unsigned int cpucx16:1;
 316       unsigned int cpuept:1;
 317       unsigned int cpurdtscp:1;
 318       unsigned int cpufsgsbase:1;
 319       unsigned int cpurdrnd:1;
 320       unsigned int cpuf16c:1;
 321       unsigned int cpubmi2:1;
 322       unsigned int cpulzcnt:1;
 323       unsigned int cpuhle:1;
 324       unsigned int cpurtm:1;
 325       unsigned int cpuinvpcid:1;
 326       unsigned int cpuvmfunc:1;
 327       unsigned int cpumpx:1;
 328       unsigned int cpulm:1;
 329       unsigned int cpurdseed:1;
 330       unsigned int cpuadx:1;
 331       unsigned int cpuprfchw:1;
 332       unsigned int cpusmap:1;
 333       unsigned int cpusha:1;
 334       unsigned int cpuvrex:1;
 335       unsigned int cpuclflushopt:1;
 336       unsigned int cpuxsaves:1;
 337       unsigned int cpuxsavec:1;
 338       unsigned int cpuprefetchwt1:1;
 339       unsigned int cpuse1:1;
 340       unsigned int cpuclwb:1;
 341       unsigned int cpuavx512ifma:1;
 342       unsigned int cpuavx512vbmi:1;
 343       unsigned int cpuavx512_4fmaps:1;
 344       unsigned int cpuavx512_4vnniw:1;
 345       unsigned int cpuavx512_vpopcntdq:1;
 346       unsigned int cpuavx512_vbmi2:1;
 347       unsigned int cpuavx512_vnni:1;
 348       unsigned int cpuavx512_bitalg:1;
 349       unsigned int cpumwaitx:1;
 350       unsigned int cpuclzero:1;
 351       unsigned int cpuospke:1;
 352       unsigned int cpurdpid:1;
 353       unsigned int cpuptwrite:1;
 354       unsigned int cpuibt:1;
 355       unsigned int cpushstk:1;
 356       unsigned int cpugfni:1;
 357       unsigned int cpuvaes:1;
 358       unsigned int cpuvpclmulqdq:1;
 359       unsigned int cpuwbnoinvd:1;
 360       unsigned int cpupconfig:1;
 361       unsigned int cpuregmmx:1;
 362       unsigned int cpuregxmm:1;
 363       unsigned int cpuregymm:1;
 364       unsigned int cpuregzmm:1;
 365       unsigned int cpuregmask:1;
 366       unsigned int cpu64:1;
 367       unsigned int cpuno64:1;
 368 #ifdef CpuUnused
 369       unsigned int unused:(CpuNumOfBits - CpuUnused);
 370 #endif
 371     } bitfield;
 372   unsigned int array[CpuNumOfUints];
 373 } i386_cpu_flags;
 374
 375 /* Position of opcode_modifier bits.  */
 376
 377 enum
 378 {
 379   /* has direction bit. */
 380   D = 0,
 381   /* set if operands can be words or dwords encoded the canonical way */
 382   W,
 383   /* load form instruction. Must be placed before store form.  */
 384   Load,
 385   /* insn has a modrm byte. */
 386   Modrm,
 387   /* register is in low 3 bits of opcode */
 388   ShortForm,
 389   /* special case for jump insns.  */
 390   Jump,
 391   /* call and jump */
 392   JumpDword,
 393   /* loop and jecxz */
 394   JumpByte,
 395   /* special case for intersegment leaps/calls */
 396   JumpInterSegment,
 397   /* FP insn memory format bit, sized by 0x4 */
 398   FloatMF,
 399   /* src/dest swap for floats. */
 400   FloatR,
 401   /* needs size prefix if in 32-bit mode */
 402   Size16,
 403   /* needs size prefix if in 16-bit mode */
 404   Size32,
 405   /* needs size prefix if in 64-bit mode */
 406   Size64,
 407   /* check register size.  */
 408   CheckRegSize,
 409   /* instruction ignores operand size prefix and in Intel mode ignores
 410      mnemonic size suffix check.  */
 411   IgnoreSize,
 412   /* default insn size depends on mode */
 413   DefaultSize,
 414   /* b suffix on instruction illegal */
 415   No_bSuf,
 416   /* w suffix on instruction illegal */
 417   No_wSuf,
 418   /* l suffix on instruction illegal */
 419   No_lSuf,
 420   /* s suffix on instruction illegal */
 421   No_sSuf,
 422   /* q suffix on instruction illegal */
 423   No_qSuf,
 424   /* long double suffix on instruction illegal */
 425   No_ldSuf,
 426   /* instruction needs FWAIT */
 427   FWait,
 428   /* quick test for string instructions */
 429   IsString,
 430   /* quick test if branch instruction is MPX supported */
 431   BNDPrefixOk,
 432   /* quick test if NOTRACK prefix is supported */
 433   NoTrackPrefixOk,
 434   /* quick test for lockable instructions */
 435   IsLockable,
 436   /* fake an extra reg operand for clr, imul and special register
 437      processing for some instructions.  */
 438   RegKludge,
 439   /* An implicit xmm0 as the first operand */
 440   Implicit1stXmm0,
 441   /* The HLE prefix is OK:
 442      1. With a LOCK prefix.
 443      2. With or without a LOCK prefix.
 444      3. With a RELEASE (0xf3) prefix.
 445    */
 446 #define HLEPrefixNone           0
 447 #define HLEPrefixLock           1
 448 #define HLEPrefixAny            2
 449 #define HLEPrefixRelease        3
 450   HLEPrefixOk,
 451   /* An instruction on which a "rep" prefix is acceptable.  */
 452   RepPrefixOk,
 453   /* Convert to DWORD */
 454   ToDword,
 455   /* Convert to QWORD */
 456   ToQword,
 457   /* Address prefix changes operand 0 */
 458   AddrPrefixOp0,
 459   /* opcode is a prefix */
 460   IsPrefix,
 461   /* instruction has extension in 8 bit imm */
 462   ImmExt,
 463   /* instruction don't need Rex64 prefix.  */
 464   NoRex64,
 465   /* instruction require Rex64 prefix.  */
 466   Rex64,
 467   /* deprecated fp insn, gets a warning */
 468   Ugh,
 469   /* insn has VEX prefix:
 470         1: 128bit VEX prefix (or operand dependent).
 471         2: 256bit VEX prefix.
 472         3: Scalar VEX prefix.
 473    */
 474 #define VEX128          1
 475 #define VEX256          2
 476 #define VEXScalar       3
 477   Vex,
 478   /* How to encode VEX.vvvv:
 479      0: VEX.vvvv must be 1111b.
 480      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 481         the content of source registers will be preserved.
 482         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 483         where the content of first source register will be overwritten
 484         by the result.
 485         VEX.NDD2.  The second destination register operand is encoded in
 486         VEX.vvvv for instructions with 2 destination register operands.
 487         For assembler, there are no difference between VEX.NDS, VEX.DDS
 488         and VEX.NDD2.
 489      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 490      instructions with 1 destination register operand.
 491      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 492         of the operands can access a memory location.
 493    */
 494 #define VEXXDS  1
 495 #define VEXNDD  2
 496 #define VEXLWP  3
 497   VexVVVV,
 498   /* How the VEX.W bit is used:
 499      0: Set by the REX.W bit.
 500      1: VEX.W0.  Should always be 0.
 501      2: VEX.W1.  Should always be 1.
 502    */
 503 #define VEXW0   1
 504 #define VEXW1   2
 505   VexW,
 506   /* VEX opcode prefix:
 507      0: VEX 0x0F opcode prefix.
 508      1: VEX 0x0F38 opcode prefix.
 509      2: VEX 0x0F3A opcode prefix
 510      3: XOP 0x08 opcode prefix.
 511      4: XOP 0x09 opcode prefix
 512      5: XOP 0x0A opcode prefix.
 513    */
 514 #define VEX0F           0
 515 #define VEX0F38         1
 516 #define VEX0F3A         2
 517 #define XOP08           3
 518 #define XOP09           4
 519 #define XOP0A           5
 520   VexOpcode,
 521   /* number of VEX source operands:
 522      0: <= 2 source operands.
 523      1: 2 XOP source operands.
 524      2: 3 source operands.
 525    */
 526 #define XOP2SOURCES     1
 527 #define VEX3SOURCES     2
 528   VexSources,
 529   /* instruction has VEX 8 bit imm */
 530   VexImmExt,
 531   /* Instruction with vector SIB byte:
 532         1: 128bit vector register.
 533         2: 256bit vector register.
 534         3: 512bit vector register.
 535    */
 536 #define VecSIB128       1
 537 #define VecSIB256       2
 538 #define VecSIB512       3
 539   VecSIB,
 540   /* SSE to AVX support required */
 541   SSE2AVX,
 542   /* No AVX equivalent */
 543   NoAVX,
 544
 545   /* insn has EVEX prefix:
 546         1: 512bit EVEX prefix.
 547         2: 128bit EVEX prefix.
 548         3: 256bit EVEX prefix.
 549         4: Length-ignored (LIG) EVEX prefix.
 550         5: Length determined from actual operands.
 551    */
 552 #define EVEX512                1
 553 #define EVEX128                2
 554 #define EVEX256                3
 555 #define EVEXLIG                4
 556 #define EVEXDYN                5
 557   EVex,
 558
 559   /* AVX512 masking support:
 560         1: Zeroing-masking.
 561         2: Merging-masking.
 562         3: Both zeroing and merging masking.
 563    */
 564 #define ZEROING_MASKING 1
 565 #define MERGING_MASKING 2
 566 #define BOTH_MASKING    3
 567   Masking,
 568
 569   /* Input element size of vector insn:
 570         0: 32bit.
 571         1: 64bit.
 572    */
 573   VecESize,
 574
 575   /* Broadcast factor.
 576         0: No broadcast.
 577         1: 1to16 broadcast.
 578         2: 1to8 broadcast.
 579    */
 580 #define NO_BROADCAST    0
 581 #define BROADCAST_1TO16 1
 582 #define BROADCAST_1TO8  2
 583 #define BROADCAST_1TO4  3
 584 #define BROADCAST_1TO2  4
 585   Broadcast,
 586
 587   /* Static rounding control is supported.  */
 588   StaticRounding,
 589
 590   /* Supress All Exceptions is supported.  */
 591   SAE,
 592
 593   /* Copressed Disp8*N attribute.  */
 594   Disp8MemShift,
 595
 596   /* Default mask isn't allowed.  */
 597   NoDefMask,
 598
 599   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 600      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 601    */
 602   ImplicitQuadGroup,
 603
 604   /* Support encoding optimization.  */
 605   Optimize,
 606
 607   /* AT&T mnemonic.  */
 608   ATTMnemonic,
 609   /* AT&T syntax.  */
 610   ATTSyntax,
 611   /* Intel syntax.  */
 612   IntelSyntax,
 613   /* AMD64.  */
 614   AMD64,
 615   /* Intel64.  */
 616   Intel64,
 617   /* The last bitfield in i386_opcode_modifier.  */
 618   Opcode_Modifier_Max
 619 };
 620
 621 typedef struct i386_opcode_modifier
 622 {
 623   unsigned int d:1;
 624   unsigned int w:1;
 625   unsigned int load:1;
 626   unsigned int modrm:1;
 627   unsigned int shortform:1;
 628   unsigned int jump:1;
 629   unsigned int jumpdword:1;
 630   unsigned int jumpbyte:1;
 631   unsigned int jumpintersegment:1;
 632   unsigned int floatmf:1;
 633   unsigned int floatr:1;
 634   unsigned int size16:1;
 635   unsigned int size32:1;
 636   unsigned int size64:1;
 637   unsigned int checkregsize:1;
 638   unsigned int ignoresize:1;
 639   unsigned int defaultsize:1;
 640   unsigned int no_bsuf:1;
 641   unsigned int no_wsuf:1;
 642   unsigned int no_lsuf:1;
 643   unsigned int no_ssuf:1;
 644   unsigned int no_qsuf:1;
 645   unsigned int no_ldsuf:1;
 646   unsigned int fwait:1;
 647   unsigned int isstring:1;
 648   unsigned int bndprefixok:1;
 649   unsigned int notrackprefixok:1;
 650   unsigned int islockable:1;
 651   unsigned int regkludge:1;
 652   unsigned int implicit1stxmm0:1;
 653   unsigned int hleprefixok:2;
 654   unsigned int repprefixok:1;
 655   unsigned int todword:1;
 656   unsigned int toqword:1;
 657   unsigned int addrprefixop0:1;
 658   unsigned int isprefix:1;
 659   unsigned int immext:1;
 660   unsigned int norex64:1;
 661   unsigned int rex64:1;
 662   unsigned int ugh:1;
 663   unsigned int vex:2;
 664   unsigned int vexvvvv:2;
 665   unsigned int vexw:2;
 666   unsigned int vexopcode:3;
 667   unsigned int vexsources:2;
 668   unsigned int veximmext:1;
 669   unsigned int vecsib:2;
 670   unsigned int sse2avx:1;
 671   unsigned int noavx:1;
 672   unsigned int evex:3;
 673   unsigned int masking:2;
 674   unsigned int vecesize:1;
 675   unsigned int broadcast:3;
 676   unsigned int staticrounding:1;
 677   unsigned int sae:1;
 678   unsigned int disp8memshift:3;
 679   unsigned int nodefmask:1;
 680   unsigned int implicitquadgroup:1;
 681   unsigned int optimize:1;
 682   unsigned int attmnemonic:1;
 683   unsigned int attsyntax:1;
 684   unsigned int intelsyntax:1;
 685   unsigned int amd64:1;
 686   unsigned int intel64:1;
 687 } i386_opcode_modifier;
 688
 689 /* Position of operand_type bits.  */
 690
 691 enum
 692 {
 693   /* Register (qualified by Byte, Word, etc) */
 694   Reg = 0,
 695   /* MMX register */
 696   RegMMX,
 697   /* Vector registers */
 698   RegSIMD,
 699   /* Vector Mask registers */
 700   RegMask,
 701   /* Control register */
 702   Control,
 703   /* Debug register */
 704   Debug,
 705   /* Test register */
 706   Test,
 707   /* 2 bit segment register */
 708   SReg2,
 709   /* 3 bit segment register */
 710   SReg3,
 711   /* 1 bit immediate */
 712   Imm1,
 713   /* 8 bit immediate */
 714   Imm8,
 715   /* 8 bit immediate sign extended */
 716   Imm8S,
 717   /* 16 bit immediate */
 718   Imm16,
 719   /* 32 bit immediate */
 720   Imm32,
 721   /* 32 bit immediate sign extended */
 722   Imm32S,
 723   /* 64 bit immediate */
 724   Imm64,
 725   /* 8bit/16bit/32bit displacements are used in different ways,
 726      depending on the instruction.  For jumps, they specify the
 727      size of the PC relative displacement, for instructions with
 728      memory operand, they specify the size of the offset relative
 729      to the base register, and for instructions with memory offset
 730      such as `mov 1234,%al' they specify the size of the offset
 731      relative to the segment base.  */
 732   /* 8 bit displacement */
 733   Disp8,
 734   /* 16 bit displacement */
 735   Disp16,
 736   /* 32 bit displacement */
 737   Disp32,
 738   /* 32 bit signed displacement */
 739   Disp32S,
 740   /* 64 bit displacement */
 741   Disp64,
 742   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 743   Acc,
 744   /* Register which can be used for base or index in memory operand.  */
 745   BaseIndex,
 746   /* Register to hold in/out port addr = dx */
 747   InOutPortReg,
 748   /* Register to hold shift count = cl */
 749   ShiftCount,
 750   /* Absolute address for jump.  */
 751   JumpAbsolute,
 752   /* String insn operand with fixed es segment */
 753   EsSeg,
 754   /* RegMem is for instructions with a modrm byte where the register
 755      destination operand should be encoded in the mod and regmem fields.
 756      Normally, it will be encoded in the reg field. We add a RegMem
 757      flag to the destination register operand to indicate that it should
 758      be encoded in the regmem field.  */
 759   RegMem,
 760   /* Memory.  */
 761   Mem,
 762   /* BYTE memory. */
 763   Byte,
 764   /* WORD memory. 2 byte */
 765   Word,
 766   /* DWORD memory. 4 byte */
 767   Dword,
 768   /* FWORD memory. 6 byte */
 769   Fword,
 770   /* QWORD memory. 8 byte */
 771   Qword,
 772   /* TBYTE memory. 10 byte */
 773   Tbyte,
 774   /* XMMWORD memory. */
 775   Xmmword,
 776   /* YMMWORD memory. */
 777   Ymmword,
 778   /* ZMMWORD memory.  */
 779   Zmmword,
 780   /* Unspecified memory size.  */
 781   Unspecified,
 782   /* Any memory size.  */
 783   Anysize,
 784
 785   /* Vector 4 bit immediate.  */
 786   Vec_Imm4,
 787
 788   /* Bound register.  */
 789   RegBND,
 790
 791   /* The last bitfield in i386_operand_type.  */
 792   OTMax
 793 };
 794
 795 #define OTNumOfUints \
 796   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 797 #define OTNumOfBits \
 798   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 799
 800 /* If you get a compiler error for zero width of the unused field,
 801    comment it out.  */
 802 #define OTUnused                (OTMax + 1)
 803
 804 typedef union i386_operand_type
 805 {
 806   struct
 807     {
 808       unsigned int reg:1;
 809       unsigned int regmmx:1;
 810       unsigned int regsimd:1;
 811       unsigned int regmask:1;
 812       unsigned int control:1;
 813       unsigned int debug:1;
 814       unsigned int test:1;
 815       unsigned int sreg2:1;
 816       unsigned int sreg3:1;
 817       unsigned int imm1:1;
 818       unsigned int imm8:1;
 819       unsigned int imm8s:1;
 820       unsigned int imm16:1;
 821       unsigned int imm32:1;
 822       unsigned int imm32s:1;
 823       unsigned int imm64:1;
 824       unsigned int disp8:1;
 825       unsigned int disp16:1;
 826       unsigned int disp32:1;
 827       unsigned int disp32s:1;
 828       unsigned int disp64:1;
 829       unsigned int acc:1;
 830       unsigned int baseindex:1;
 831       unsigned int inoutportreg:1;
 832       unsigned int shiftcount:1;
 833       unsigned int jumpabsolute:1;
 834       unsigned int esseg:1;
 835       unsigned int regmem:1;
 836       unsigned int mem:1;
 837       unsigned int byte:1;
 838       unsigned int word:1;
 839       unsigned int dword:1;
 840       unsigned int fword:1;
 841       unsigned int qword:1;
 842       unsigned int tbyte:1;
 843       unsigned int xmmword:1;
 844       unsigned int ymmword:1;
 845       unsigned int zmmword:1;
 846       unsigned int unspecified:1;
 847       unsigned int anysize:1;
 848       unsigned int vec_imm4:1;
 849       unsigned int regbnd:1;
 850 #ifdef OTUnused
 851       unsigned int unused:(OTNumOfBits - OTUnused);
 852 #endif
 853     } bitfield;
 854   unsigned int array[OTNumOfUints];
 855 } i386_operand_type;
 856
 857 typedef struct insn_template
 858 {
 859   /* instruction name sans width suffix ("mov" for movl insns) */
 860   char *name;
 861
 862   /* how many operands */
 863   unsigned int operands;
 864
 865   /* base_opcode is the fundamental opcode byte without optional
 866      prefix(es).  */
 867   unsigned int base_opcode;
 868 #define Opcode_D        0x2 /* Direction bit:
 869                                set if Reg --> Regmem;
 870                                unset if Regmem --> Reg. */
 871 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 872 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 873
 874   /* extension_opcode is the 3 bit extension for group <n> insns.
 875      This field is also used to store the 8-bit opcode suffix for the
 876      AMD 3DNow! instructions.
 877      If this template has no extension opcode (the usual case) use None
 878      Instructions */
 879   unsigned int extension_opcode;
 880 #define None 0xffff             /* If no extension_opcode is possible.  */
 881
 882   /* Opcode length.  */
 883   unsigned char opcode_length;
 884
 885   /* cpu feature flags */
 886   i386_cpu_flags cpu_flags;
 887
 888   /* the bits in opcode_modifier are used to generate the final opcode from
 889      the base_opcode.  These bits also are used to detect alternate forms of
 890      the same instruction */
 891   i386_opcode_modifier opcode_modifier;
 892
 893   /* operand_types[i] describes the type of operand i.  This is made
 894      by OR'ing together all of the possible type masks.  (e.g.
 895      'operand_types[i] = Reg|Imm' specifies that operand i can be
 896      either a register or an immediate operand.  */
 897   i386_operand_type operand_types[MAX_OPERANDS];
 898 }
 899 insn_template;
 900
 901 extern const insn_template i386_optab[];
 902
 903 /* these are for register name --> number & type hash lookup */
 904 typedef struct
 905 {
 906   char *reg_name;
 907   i386_operand_type reg_type;
 908   unsigned char reg_flags;
 909 #define RegRex      0x1  /* Extended register.  */
 910 #define RegRex64    0x2  /* Extended 8 bit register.  */
 911 #define RegVRex     0x4  /* Extended vector register.  */
 912   unsigned char reg_num;
 913 #define RegRip  ((unsigned char ) ~0)
 914 #define RegEip  (RegRip - 1)
 915 /* EIZ and RIZ are fake index registers.  */
 916 #define RegEiz  (RegEip - 1)
 917 #define RegRiz  (RegEiz - 1)
 918 /* FLAT is a fake segment register (Intel mode).  */
 919 #define RegFlat     ((unsigned char) ~0)
 920   signed char dw2_regnum[2];
 921 #define Dw2Inval (-1)
 922 }
 923 reg_entry;
 924
 925 /* Entries in i386_regtab.  */
 926 #define REGNAM_AL 1
 927 #define REGNAM_AX 25
 928 #define REGNAM_EAX 41
 929
 930 extern const reg_entry i386_regtab[];
 931 extern const unsigned int i386_regtab_size;
 932
 933 typedef struct
 934 {
 935   char *seg_name;
 936   unsigned int seg_prefix;
 937 }
 938 seg_entry;
 939
 940 extern const seg_entry cs;
 941 extern const seg_entry ds;
 942 extern const seg_entry ss;
 943 extern const seg_entry es;
 944 extern const seg_entry fs;
 945 extern const seg_entry gs;