opcodes/i386-reg.tbl

   1 // i386 register table.
   2 // Copyright (C) 2007-2021 Free Software Foundation, Inc.
   3 //
   4 // This file is part of the GNU opcodes library.
   5 //
   6 // This library is free software; you can redistribute it and/or modify
   7 // it under the terms of the GNU General Public License as published by
   8 // the Free Software Foundation; either version 3, or (at your option)
   9 // any later version.
  10 //
  11 // It is distributed in the hope that it will be useful, but WITHOUT
  12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 // or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 // License for more details.
  15 //
  16 // You should have received a copy of the GNU General Public License
  17 // along with GAS; see the file COPYING.  If not, write to the Free
  18 // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19 // 02110-1301, USA.
  20
  21 // 8 bit regs
  22 al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
  23 cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
  24 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
  25 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
  26 ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
  27 ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
  28 dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
  29 bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
  30 axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
  31 cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
  32 dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
  33 bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
  34 spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
  35 bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
  36 sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
  37 dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
  38 r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
  39 r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
  40 r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
  41 r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
  42 r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
  43 r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
  44 r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
  45 r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
  46 // 16 bit regs
  47 ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
  48 cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
  49 dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
  50 bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
  51 sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
  52 bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
  53 si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
  54 di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
  55 r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
  56 r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
  57 r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
  58 r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
  59 r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
  60 r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
  61 r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
  62 r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
  63 // 32 bit regs
  64 eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
  65 ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
  66 edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval
  67 ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
  68 esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval
  69 ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
  70 esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
  71 edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
  72 r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
  73 r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
  74 r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
  75 r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
  76 r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
  77 r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
  78 r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
  79 r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
  80 rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
  81 rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
  82 rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1
  83 rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
  84 rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7
  85 rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
  86 rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
  87 rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
  88 r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
  89 r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
  90 r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
  91 r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
  92 r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
  93 r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
  94 r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
  95 r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
  96 // Vector mask registers.
  97 k0, Class=RegMask, 0, 0, 93, 118
  98 k1, Class=RegMask, 0, 1, 94, 119
  99 k2, Class=RegMask, 0, 2, 95, 120
 100 k3, Class=RegMask, 0, 3, 96, 121
 101 k4, Class=RegMask, 0, 4, 97, 122
 102 k5, Class=RegMask, 0, 5, 98, 123
 103 k6, Class=RegMask, 0, 6, 99, 124
 104 k7, Class=RegMask, 0, 7, 100, 125
 105 // Segment registers.
 106 es, Class=SReg, 0, 0, 40, 50
 107 cs, Class=SReg, 0, 1, 41, 51
 108 ss, Class=SReg, 0, 2, 42, 52
 109 ds, Class=SReg, 0, 3, 43, 53
 110 fs, Class=SReg, 0, 4, 44, 54
 111 gs, Class=SReg, 0, 5, 45, 55
 112 flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
 113 // Control registers.
 114 cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
 115 cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
 116 cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
 117 cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
 118 cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
 119 cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
 120 cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
 121 cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
 122 cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
 123 cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
 124 cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
 125 cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
 126 cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
 127 cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
 128 cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
 129 cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
 130 // Debug registers.
 131 db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
 132 db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
 133 db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
 134 db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
 135 db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
 136 db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
 137 db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
 138 db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
 139 db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
 140 db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
 141 db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
 142 db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
 143 db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
 144 db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
 145 db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
 146 db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
 147 dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
 148 dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
 149 dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
 150 dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
 151 dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
 152 dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
 153 dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
 154 dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
 155 dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
 156 dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
 157 dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
 158 dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
 159 dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
 160 dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
 161 dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
 162 dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
 163 // Test registers.
 164 tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
 165 tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
 166 tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
 167 tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
 168 tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
 169 tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
 170 tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
 171 tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
 172 // MMX and simd registers.
 173 mm0, Class=RegMMX, 0, 0, 29, 41
 174 mm1, Class=RegMMX, 0, 1, 30, 42
 175 mm2, Class=RegMMX, 0, 2, 31, 43
 176 mm3, Class=RegMMX, 0, 3, 32, 44
 177 mm4, Class=RegMMX, 0, 4, 33, 45
 178 mm5, Class=RegMMX, 0, 5, 34, 46
 179 mm6, Class=RegMMX, 0, 6, 35, 47
 180 mm7, Class=RegMMX, 0, 7, 36, 48
 181 xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
 182 xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
 183 xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
 184 xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
 185 xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
 186 xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
 187 xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
 188 xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
 189 xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
 190 xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
 191 xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
 192 xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
 193 xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
 194 xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
 195 xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
 196 xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
 197 xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
 198 xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
 199 xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
 200 xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
 201 xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
 202 xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
 203 xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
 204 xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
 205 xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
 206 xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
 207 xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
 208 xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
 209 xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
 210 xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
 211 xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
 212 xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
 213 // AVX registers.
 214 ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
 215 ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
 216 ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
 217 ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
 218 ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
 219 ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
 220 ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
 221 ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
 222 ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
 223 ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
 224 ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
 225 ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
 226 ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
 227 ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
 228 ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
 229 ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
 230 ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
 231 ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
 232 ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
 233 ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
 234 ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
 235 ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
 236 ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
 237 ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
 238 ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
 239 ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
 240 ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
 241 ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
 242 ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
 243 ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
 244 ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
 245 ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
 246 // AVX512 registers.
 247 zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
 248 zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
 249 zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
 250 zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
 251 zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
 252 zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
 253 zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
 254 zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
 255 zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
 256 zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
 257 zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
 258 zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
 259 zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
 260 zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
 261 zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
 262 zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
 263 zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
 264 zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
 265 zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
 266 zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
 267 zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
 268 zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
 269 zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
 270 zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
 271 zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
 272 zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
 273 zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
 274 zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
 275 zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
 276 zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
 277 zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
 278 zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
 279 // TMM registers for AMX
 280 tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
 281 tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
 282 tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
 283 tmm3, Class=RegSIMD|Tmmword, 0, 3, Dw2Inval, Dw2Inval
 284 tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
 285 tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
 286 tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
 287 tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
 288 // Bound registers for MPX
 289 bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
 290 bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
 291 bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
 292 bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
 293 // No Class=Reg will make these registers rejected for all purposes except
 294 // for addressing.  This saves creating one extra type for RIP/EIP.
 295 rip, Qword, RegRex64, RegIP, Dw2Inval, 16
 296 eip, Dword, RegRex64, RegIP, 8, Dw2Inval
 297 // No Class=Reg will make these registers rejected for all purposes except
 298 // for addressing.
 299 riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
 300 eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
 301 // fp regs. No need for an explicit st(0) here.
 302 st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
 303 st(1), Class=Reg|Tbyte, 0, 1, 12, 34
 304 st(2), Class=Reg|Tbyte, 0, 2, 13, 35
 305 st(3), Class=Reg|Tbyte, 0, 3, 14, 36
 306 st(4), Class=Reg|Tbyte, 0, 4, 15, 37
 307 st(5), Class=Reg|Tbyte, 0, 5, 16, 38
 308 st(6), Class=Reg|Tbyte, 0, 6, 17, 39
 309 st(7), Class=Reg|Tbyte, 0, 7, 18, 40
 310 // Pseudo-register names only used in .cfi_* directives
 311 eflags, 0, 0, 0, 9, 49
 312 rflags, 0, 0, 0, Dw2Inval, 49
 313 fs.base, 0, 0, 0, Dw2Inval, 58
 314 gs.base, 0, 0, 0, Dw2Inval, 59
 315 tr, 0, 0, 0, 48, 62
 316 ldtr, 0, 0, 0, 49, 63
 317 // st0...7 for backward compatibility
 318 st0, 0, 0, 0, 11, 33
 319 st1, 0, 0, 1, 12, 34
 320 st2, 0, 0, 2, 13, 35
 321 st3, 0, 0, 3, 14, 36
 322 st4, 0, 0, 4, 15, 37
 323 st5, 0, 0, 5, 16, 38
 324 st6, 0, 0, 6, 17, 39
 325 st7, 0, 0, 7, 18, 40
 326 fcw, 0, 0, 0, 37, 65
 327 fsw, 0, 0, 0, 38, 66
 328 mxcsr, 0, 0, 0, 39, 64