opcodes/i860-dis.c

   1 /* Disassembler for the i860.
   2    Copyright 2000, 2003 Free Software Foundation, Inc.
   3
   4    Contributed by Jason Eckhardt <jle@cygnus.com>.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include "dis-asm.h"
  21 #include "opcode/i860.h"
  22
  23 /* Later we should probably choose the prefix based on which OS flavor.  */
  24 #define I860_REG_PREFIX "%"
  25
  26 /* Integer register names (encoded as 0..31 in the instruction).  */
  27 static const char *const grnames[] =
  28  {"r0",  "r1",  "sp",  "fp",  "r4",  "r5",  "r6",  "r7",
  29   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
  30   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  31   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
  32
  33 /* FP register names (encoded as 0..31 in the instruction).  */
  34 static const char *const frnames[] =
  35  {"f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
  36   "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
  37   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  38   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
  39
  40 /* Control/status register names (encoded as 0..11 in the instruction).
  41    Registers bear, ccr, p0, p1, p2 and p3 are XP only.  */
  42 static const char *const crnames[] =
  43  {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
  44   "p0", "p1", "p2", "p3", "--", "--", "--", "--" };
  45
  46
  47 /* Prototypes.  */
  48 static int sign_ext             PARAMS((unsigned int, int));
  49 static void print_br_address    PARAMS((disassemble_info *, bfd_vma, long));
  50
  51
  52 /* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth.  */
  53 #define BITWISE_OP(op)  ((op) == 0x30 || (op) == 0x31           \
  54                          || (op) == 0x34 || (op) == 0x35        \
  55                          || (op) == 0x38 || (op) == 0x39        \
  56                          || (op) == 0x3c || (op) == 0x3d        \
  57                          || (op) == 0x33 || (op) == 0x37        \
  58                          || (op) == 0x3b || (op) == 0x3f)
  59
  60
  61 /* Sign extend N-bit number.  */
  62 static int
  63 sign_ext (x, n)
  64      unsigned int x;
  65      int n;
  66 {
  67   int t;
  68   t = x >> (n - 1);
  69   t = ((-t) << n) | x;
  70   return t;
  71 }
  72
  73
  74 /* Print a PC-relative branch offset.  VAL is the sign extended value
  75    from the branch instruction.  */
  76 static void
  77 print_br_address (info, memaddr, val)
  78      disassemble_info *info;
  79      bfd_vma memaddr;
  80      long val;
  81 {
  82
  83   long adj = (long)memaddr + 4 + (val << 2);
  84
  85   (*info->fprintf_func) (info->stream, "0x%08x", adj);
  86
  87   /* Attempt to obtain a symbol for the target address.  */
  88
  89   if (info->print_address_func && adj != 0)
  90     {
  91       (*info->fprintf_func) (info->stream, "\t// ");
  92       (*info->print_address_func) (adj, info);
  93     }
  94 }
  95
  96
  97 /* Print one instruction.  */
  98 int
  99 print_insn_i860 (memaddr, info)
 100      bfd_vma memaddr;
 101      disassemble_info *info;
 102 {
 103   bfd_byte buff[4];
 104   unsigned int insn, i;
 105   int status;
 106   const struct i860_opcode *opcode = 0;
 107
 108   status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info);
 109   if (status != 0)
 110     {
 111       (*info->memory_error_func) (status, memaddr, info);
 112       return -1;
 113     }
 114
 115   /* Note that i860 instructions are always accessed as little endian
 116      data, regardless of the endian mode of the i860.  */
 117   insn = bfd_getl32 (buff);
 118
 119   status = 0;
 120   i = 0;
 121   while (i860_opcodes[i].name != NULL)
 122     {
 123       opcode = &i860_opcodes[i];
 124       if ((insn & opcode->match) == opcode->match
 125           && (insn & opcode->lose) == 0)
 126         {
 127           status = 1;
 128           break;
 129         }
 130       ++i;
 131     }
 132
 133   if (status == 0)
 134     {
 135       /* Instruction not in opcode table.  */
 136       (*info->fprintf_func) (info->stream, ".long %#08x", insn);
 137     }
 138   else
 139     {
 140       const char *s;
 141       int val;
 142
 143       /* If this a flop (or a shrd) and its dual bit is set,
 144          prefix with 'd.'.  */
 145       if (((insn & 0xfc000000) == 0x48000000
 146            || (insn & 0xfc000000) == 0xb0000000)
 147           && (insn & 0x200))
 148         (*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
 149       else
 150         (*info->fprintf_func) (info->stream, "%s\t", opcode->name);
 151
 152       for (s = opcode->args; *s; s++)
 153         {
 154           switch (*s)
 155             {
 156             /* Integer register (src1).  */
 157             case '1':
 158               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 159                                      grnames[(insn >> 11) & 0x1f]);
 160               break;
 161
 162             /* Integer register (src2).  */
 163             case '2':
 164               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 165                                      grnames[(insn >> 21) & 0x1f]);
 166               break;
 167
 168             /* Integer destination register.  */
 169             case 'd':
 170               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 171                                      grnames[(insn >> 16) & 0x1f]);
 172               break;
 173
 174             /* Floating-point register (src1).  */
 175             case 'e':
 176               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 177                                      frnames[(insn >> 11) & 0x1f]);
 178               break;
 179
 180             /* Floating-point register (src2).  */
 181             case 'f':
 182               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 183                                      frnames[(insn >> 21) & 0x1f]);
 184               break;
 185
 186             /* Floating-point destination register.  */
 187             case 'g':
 188               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 189                                      frnames[(insn >> 16) & 0x1f]);
 190               break;
 191
 192             /* Control register.  */
 193             case 'c':
 194               (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
 195                                      crnames[(insn >> 21) & 0xf]);
 196               break;
 197
 198             /* 16-bit immediate (sign extend, except for bitwise ops).  */
 199             case 'i':
 200               if (BITWISE_OP ((insn & 0xfc000000) >> 26))
 201                 (*info->fprintf_func) (info->stream, "0x%04x",
 202                                        (unsigned int) (insn & 0xffff));
 203               else
 204                 (*info->fprintf_func) (info->stream, "%d",
 205                                        sign_ext ((insn & 0xffff), 16));
 206               break;
 207
 208             /* 16-bit immediate, aligned (2^0, ld.b).  */
 209             case 'I':
 210               (*info->fprintf_func) (info->stream, "%d",
 211                                      sign_ext ((insn & 0xffff), 16));
 212               break;
 213
 214             /* 16-bit immediate, aligned (2^1, ld.s).  */
 215             case 'J':
 216               (*info->fprintf_func) (info->stream, "%d",
 217                                      sign_ext ((insn & 0xfffe), 16));
 218               break;
 219
 220             /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l).  */
 221             case 'K':
 222               (*info->fprintf_func) (info->stream, "%d",
 223                                      sign_ext ((insn & 0xfffc), 16));
 224               break;
 225
 226             /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d).  */
 227             case 'L':
 228               (*info->fprintf_func) (info->stream, "%d",
 229                                      sign_ext ((insn & 0xfff8), 16));
 230               break;
 231
 232             /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q).  */
 233             case 'M':
 234               (*info->fprintf_func) (info->stream, "%d",
 235                                      sign_ext ((insn & 0xfff0), 16));
 236               break;
 237
 238             /* 5-bit immediate (zero extend).  */
 239             case '5':
 240               (*info->fprintf_func) (info->stream, "%d",
 241                                      ((insn >> 11) & 0x1f));
 242               break;
 243
 244             /* Split 16 bit immediate (20..16:10..0).  */
 245             case 's':
 246               val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
 247               (*info->fprintf_func) (info->stream, "%d",
 248                                      sign_ext (val, 16));
 249               break;
 250
 251             /* Split 16 bit immediate, aligned. (2^0, st.b).  */
 252             case 'S':
 253               val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
 254               (*info->fprintf_func) (info->stream, "%d",
 255                                      sign_ext (val, 16));
 256               break;
 257
 258             /* Split 16 bit immediate, aligned. (2^1, st.s).  */
 259             case 'T':
 260               val = ((insn >> 5) & 0xf800) | (insn & 0x07fe);
 261               (*info->fprintf_func) (info->stream, "%d",
 262                                      sign_ext (val, 16));
 263               break;
 264
 265             /* Split 16 bit immediate, aligned. (2^2, st.l).  */
 266             case 'U':
 267               val = ((insn >> 5) & 0xf800) | (insn & 0x07fc);
 268               (*info->fprintf_func) (info->stream, "%d",
 269                                      sign_ext (val, 16));
 270               break;
 271
 272             /* 26-bit PC relative immediate (lbroff).  */
 273             case 'l':
 274               val = sign_ext ((insn & 0x03ffffff), 26);
 275               print_br_address (info, memaddr, val);
 276               break;
 277
 278             /* 16-bit PC relative immediate (sbroff).  */
 279             case 'r':
 280               val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16);
 281               print_br_address (info, memaddr, val);
 282               break;
 283
 284             default:
 285               (*info->fprintf_func) (info->stream, "%c", *s);
 286               break;
 287             }
 288         }
 289     }
 290
 291   return sizeof (insn);
 292 }
 293