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* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
[deliverable/binutils-gdb.git] / opcodes / m32c-desc.c
1 /* CPU data for m32c.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996-2005 Free Software Foundation, Inc.
6
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
22
23 */
24
25 #include "sysdep.h"
26 #include <stdio.h>
27 #include <stdarg.h>
28 #include "ansidecl.h"
29 #include "bfd.h"
30 #include "symcat.h"
31 #include "m32c-desc.h"
32 #include "m32c-opc.h"
33 #include "opintl.h"
34 #include "libiberty.h"
35 #include "xregex.h"
36
37 /* Attributes. */
38
39 static const CGEN_ATTR_ENTRY bool_attr[] =
40 {
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44 };
45
46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
47 {
48 { "base", MACH_BASE },
49 { "m16c", MACH_M16C },
50 { "m32c", MACH_M32C },
51 { "max", MACH_MAX },
52 { 0, 0 }
53 };
54
55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
56 {
57 { "m16c", ISA_M16C },
58 { "m32c", ISA_M32C },
59 { "max", ISA_MAX },
60 { 0, 0 }
61 };
62
63 const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] =
64 {
65 { "MACH", & MACH_attr[0], & MACH_attr[0] },
66 { "ISA", & ISA_attr[0], & ISA_attr[0] },
67 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
68 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
70 { "RESERVED", &bool_attr[0], &bool_attr[0] },
71 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
72 { "SIGNED", &bool_attr[0], &bool_attr[0] },
73 { 0, 0, 0 }
74 };
75
76 const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] =
77 {
78 { "MACH", & MACH_attr[0], & MACH_attr[0] },
79 { "ISA", & ISA_attr[0], & ISA_attr[0] },
80 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
81 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
82 { "PC", &bool_attr[0], &bool_attr[0] },
83 { "PROFILE", &bool_attr[0], &bool_attr[0] },
84 { 0, 0, 0 }
85 };
86
87 const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] =
88 {
89 { "MACH", & MACH_attr[0], & MACH_attr[0] },
90 { "ISA", & ISA_attr[0], & ISA_attr[0] },
91 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
92 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
93 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
94 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
95 { "SIGNED", &bool_attr[0], &bool_attr[0] },
96 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
97 { "RELAX", &bool_attr[0], &bool_attr[0] },
98 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
99 { 0, 0, 0 }
100 };
101
102 const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] =
103 {
104 { "MACH", & MACH_attr[0], & MACH_attr[0] },
105 { "ISA", & ISA_attr[0], & ISA_attr[0] },
106 { "ALIAS", &bool_attr[0], &bool_attr[0] },
107 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
108 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
109 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
110 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
111 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
112 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
113 { "RELAXED", &bool_attr[0], &bool_attr[0] },
114 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
115 { "PBB", &bool_attr[0], &bool_attr[0] },
116 { 0, 0, 0 }
117 };
118
119 /* Instruction set variants. */
120
121 static const CGEN_ISA m32c_cgen_isa_table[] = {
122 { "m16c", 32, 32, 8, 56 },
123 { "m32c", 32, 32, 8, 80 },
124 { 0, 0, 0, 0, 0 }
125 };
126
127 /* Machine variants. */
128
129 static const CGEN_MACH m32c_cgen_mach_table[] = {
130 { "m16c", "m16c", MACH_M16C, 0 },
131 { "m32c", "m32c", MACH_M32C, 0 },
132 { 0, 0, 0, 0 }
133 };
134
135 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] =
136 {
137 { "r0", 0, {0, {0}}, 0, 0 },
138 { "r1", 1, {0, {0}}, 0, 0 },
139 { "r2", 2, {0, {0}}, 0, 0 },
140 { "r3", 3, {0, {0}}, 0, 0 }
141 };
142
143 CGEN_KEYWORD m32c_cgen_opval_h_gr =
144 {
145 & m32c_cgen_opval_h_gr_entries[0],
146 4,
147 0, 0, 0, 0, ""
148 };
149
150 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] =
151 {
152 { "r0l", 0, {0, {0}}, 0, 0 },
153 { "r0h", 1, {0, {0}}, 0, 0 },
154 { "r1l", 2, {0, {0}}, 0, 0 },
155 { "r1h", 3, {0, {0}}, 0, 0 }
156 };
157
158 CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
159 {
160 & m32c_cgen_opval_h_gr_QI_entries[0],
161 4,
162 0, 0, 0, 0, ""
163 };
164
165 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] =
166 {
167 { "r0", 0, {0, {0}}, 0, 0 },
168 { "r1", 1, {0, {0}}, 0, 0 },
169 { "r2", 2, {0, {0}}, 0, 0 },
170 { "r3", 3, {0, {0}}, 0, 0 }
171 };
172
173 CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
174 {
175 & m32c_cgen_opval_h_gr_HI_entries[0],
176 4,
177 0, 0, 0, 0, ""
178 };
179
180 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] =
181 {
182 { "r2r0", 0, {0, {0}}, 0, 0 },
183 { "r3r1", 1, {0, {0}}, 0, 0 }
184 };
185
186 CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
187 {
188 & m32c_cgen_opval_h_gr_SI_entries[0],
189 2,
190 0, 0, 0, 0, ""
191 };
192
193 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] =
194 {
195 { "r0l", 0, {0, {0}}, 0, 0 },
196 { "r1l", 1, {0, {0}}, 0, 0 }
197 };
198
199 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
200 {
201 & m32c_cgen_opval_h_gr_ext_QI_entries[0],
202 2,
203 0, 0, 0, 0, ""
204 };
205
206 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] =
207 {
208 { "r0", 0, {0, {0}}, 0, 0 },
209 { "r1", 1, {0, {0}}, 0, 0 }
210 };
211
212 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
213 {
214 & m32c_cgen_opval_h_gr_ext_HI_entries[0],
215 2,
216 0, 0, 0, 0, ""
217 };
218
219 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] =
220 {
221 { "r0l", 0, {0, {0}}, 0, 0 }
222 };
223
224 CGEN_KEYWORD m32c_cgen_opval_h_r0l =
225 {
226 & m32c_cgen_opval_h_r0l_entries[0],
227 1,
228 0, 0, 0, 0, ""
229 };
230
231 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] =
232 {
233 { "r0h", 0, {0, {0}}, 0, 0 }
234 };
235
236 CGEN_KEYWORD m32c_cgen_opval_h_r0h =
237 {
238 & m32c_cgen_opval_h_r0h_entries[0],
239 1,
240 0, 0, 0, 0, ""
241 };
242
243 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] =
244 {
245 { "r1l", 0, {0, {0}}, 0, 0 }
246 };
247
248 CGEN_KEYWORD m32c_cgen_opval_h_r1l =
249 {
250 & m32c_cgen_opval_h_r1l_entries[0],
251 1,
252 0, 0, 0, 0, ""
253 };
254
255 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] =
256 {
257 { "r1h", 0, {0, {0}}, 0, 0 }
258 };
259
260 CGEN_KEYWORD m32c_cgen_opval_h_r1h =
261 {
262 & m32c_cgen_opval_h_r1h_entries[0],
263 1,
264 0, 0, 0, 0, ""
265 };
266
267 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] =
268 {
269 { "r0", 0, {0, {0}}, 0, 0 }
270 };
271
272 CGEN_KEYWORD m32c_cgen_opval_h_r0 =
273 {
274 & m32c_cgen_opval_h_r0_entries[0],
275 1,
276 0, 0, 0, 0, ""
277 };
278
279 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] =
280 {
281 { "r1", 0, {0, {0}}, 0, 0 }
282 };
283
284 CGEN_KEYWORD m32c_cgen_opval_h_r1 =
285 {
286 & m32c_cgen_opval_h_r1_entries[0],
287 1,
288 0, 0, 0, 0, ""
289 };
290
291 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] =
292 {
293 { "r2", 0, {0, {0}}, 0, 0 }
294 };
295
296 CGEN_KEYWORD m32c_cgen_opval_h_r2 =
297 {
298 & m32c_cgen_opval_h_r2_entries[0],
299 1,
300 0, 0, 0, 0, ""
301 };
302
303 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] =
304 {
305 { "r3", 0, {0, {0}}, 0, 0 }
306 };
307
308 CGEN_KEYWORD m32c_cgen_opval_h_r3 =
309 {
310 & m32c_cgen_opval_h_r3_entries[0],
311 1,
312 0, 0, 0, 0, ""
313 };
314
315 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] =
316 {
317 { "r0l", 0, {0, {0}}, 0, 0 },
318 { "r0h", 1, {0, {0}}, 0, 0 }
319 };
320
321 CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
322 {
323 & m32c_cgen_opval_h_r0l_r0h_entries[0],
324 2,
325 0, 0, 0, 0, ""
326 };
327
328 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] =
329 {
330 { "r2r0", 0, {0, {0}}, 0, 0 }
331 };
332
333 CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
334 {
335 & m32c_cgen_opval_h_r2r0_entries[0],
336 1,
337 0, 0, 0, 0, ""
338 };
339
340 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] =
341 {
342 { "r3r1", 0, {0, {0}}, 0, 0 }
343 };
344
345 CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
346 {
347 & m32c_cgen_opval_h_r3r1_entries[0],
348 1,
349 0, 0, 0, 0, ""
350 };
351
352 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] =
353 {
354 { "r1r2r0", 0, {0, {0}}, 0, 0 }
355 };
356
357 CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
358 {
359 & m32c_cgen_opval_h_r1r2r0_entries[0],
360 1,
361 0, 0, 0, 0, ""
362 };
363
364 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] =
365 {
366 { "a0", 0, {0, {0}}, 0, 0 },
367 { "a1", 1, {0, {0}}, 0, 0 }
368 };
369
370 CGEN_KEYWORD m32c_cgen_opval_h_ar =
371 {
372 & m32c_cgen_opval_h_ar_entries[0],
373 2,
374 0, 0, 0, 0, ""
375 };
376
377 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] =
378 {
379 { "a0", 0, {0, {0}}, 0, 0 },
380 { "a1", 1, {0, {0}}, 0, 0 }
381 };
382
383 CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
384 {
385 & m32c_cgen_opval_h_ar_QI_entries[0],
386 2,
387 0, 0, 0, 0, ""
388 };
389
390 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] =
391 {
392 { "a0", 0, {0, {0}}, 0, 0 },
393 { "a1", 1, {0, {0}}, 0, 0 }
394 };
395
396 CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
397 {
398 & m32c_cgen_opval_h_ar_HI_entries[0],
399 2,
400 0, 0, 0, 0, ""
401 };
402
403 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] =
404 {
405 { "a1a0", 0, {0, {0}}, 0, 0 }
406 };
407
408 CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
409 {
410 & m32c_cgen_opval_h_ar_SI_entries[0],
411 1,
412 0, 0, 0, 0, ""
413 };
414
415 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] =
416 {
417 { "a0", 0, {0, {0}}, 0, 0 }
418 };
419
420 CGEN_KEYWORD m32c_cgen_opval_h_a0 =
421 {
422 & m32c_cgen_opval_h_a0_entries[0],
423 1,
424 0, 0, 0, 0, ""
425 };
426
427 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] =
428 {
429 { "a1", 1, {0, {0}}, 0, 0 }
430 };
431
432 CGEN_KEYWORD m32c_cgen_opval_h_a1 =
433 {
434 & m32c_cgen_opval_h_a1_entries[0],
435 1,
436 0, 0, 0, 0, ""
437 };
438
439 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] =
440 {
441 { "geu", 0, {0, {0}}, 0, 0 },
442 { "c", 0, {0, {0}}, 0, 0 },
443 { "gtu", 1, {0, {0}}, 0, 0 },
444 { "eq", 2, {0, {0}}, 0, 0 },
445 { "z", 2, {0, {0}}, 0, 0 },
446 { "n", 3, {0, {0}}, 0, 0 },
447 { "le", 4, {0, {0}}, 0, 0 },
448 { "o", 5, {0, {0}}, 0, 0 },
449 { "ge", 6, {0, {0}}, 0, 0 },
450 { "ltu", 248, {0, {0}}, 0, 0 },
451 { "nc", 248, {0, {0}}, 0, 0 },
452 { "leu", 249, {0, {0}}, 0, 0 },
453 { "ne", 250, {0, {0}}, 0, 0 },
454 { "nz", 250, {0, {0}}, 0, 0 },
455 { "pz", 251, {0, {0}}, 0, 0 },
456 { "gt", 252, {0, {0}}, 0, 0 },
457 { "no", 253, {0, {0}}, 0, 0 },
458 { "lt", 254, {0, {0}}, 0, 0 }
459 };
460
461 CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
462 {
463 & m32c_cgen_opval_h_cond16_entries[0],
464 18,
465 0, 0, 0, 0, ""
466 };
467
468 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] =
469 {
470 { "geu", 0, {0, {0}}, 0, 0 },
471 { "c", 0, {0, {0}}, 0, 0 },
472 { "gtu", 1, {0, {0}}, 0, 0 },
473 { "eq", 2, {0, {0}}, 0, 0 },
474 { "z", 2, {0, {0}}, 0, 0 },
475 { "n", 3, {0, {0}}, 0, 0 },
476 { "ltu", 4, {0, {0}}, 0, 0 },
477 { "nc", 4, {0, {0}}, 0, 0 },
478 { "leu", 5, {0, {0}}, 0, 0 },
479 { "ne", 6, {0, {0}}, 0, 0 },
480 { "nz", 6, {0, {0}}, 0, 0 },
481 { "pz", 7, {0, {0}}, 0, 0 },
482 { "le", 8, {0, {0}}, 0, 0 },
483 { "o", 9, {0, {0}}, 0, 0 },
484 { "ge", 10, {0, {0}}, 0, 0 },
485 { "gt", 12, {0, {0}}, 0, 0 },
486 { "no", 13, {0, {0}}, 0, 0 },
487 { "lt", 14, {0, {0}}, 0, 0 }
488 };
489
490 CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
491 {
492 & m32c_cgen_opval_h_cond16c_entries[0],
493 18,
494 0, 0, 0, 0, ""
495 };
496
497 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] =
498 {
499 { "le", 8, {0, {0}}, 0, 0 },
500 { "o", 9, {0, {0}}, 0, 0 },
501 { "ge", 10, {0, {0}}, 0, 0 },
502 { "gt", 12, {0, {0}}, 0, 0 },
503 { "no", 13, {0, {0}}, 0, 0 },
504 { "lt", 14, {0, {0}}, 0, 0 }
505 };
506
507 CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
508 {
509 & m32c_cgen_opval_h_cond16j_entries[0],
510 6,
511 0, 0, 0, 0, ""
512 };
513
514 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] =
515 {
516 { "geu", 0, {0, {0}}, 0, 0 },
517 { "c", 0, {0, {0}}, 0, 0 },
518 { "gtu", 1, {0, {0}}, 0, 0 },
519 { "eq", 2, {0, {0}}, 0, 0 },
520 { "z", 2, {0, {0}}, 0, 0 },
521 { "n", 3, {0, {0}}, 0, 0 },
522 { "ltu", 4, {0, {0}}, 0, 0 },
523 { "nc", 4, {0, {0}}, 0, 0 },
524 { "leu", 5, {0, {0}}, 0, 0 },
525 { "ne", 6, {0, {0}}, 0, 0 },
526 { "nz", 6, {0, {0}}, 0, 0 },
527 { "pz", 7, {0, {0}}, 0, 0 }
528 };
529
530 CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
531 {
532 & m32c_cgen_opval_h_cond16j_5_entries[0],
533 12,
534 0, 0, 0, 0, ""
535 };
536
537 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] =
538 {
539 { "ltu", 0, {0, {0}}, 0, 0 },
540 { "nc", 0, {0, {0}}, 0, 0 },
541 { "leu", 1, {0, {0}}, 0, 0 },
542 { "ne", 2, {0, {0}}, 0, 0 },
543 { "nz", 2, {0, {0}}, 0, 0 },
544 { "pz", 3, {0, {0}}, 0, 0 },
545 { "no", 4, {0, {0}}, 0, 0 },
546 { "gt", 5, {0, {0}}, 0, 0 },
547 { "ge", 6, {0, {0}}, 0, 0 },
548 { "geu", 8, {0, {0}}, 0, 0 },
549 { "c", 8, {0, {0}}, 0, 0 },
550 { "gtu", 9, {0, {0}}, 0, 0 },
551 { "eq", 10, {0, {0}}, 0, 0 },
552 { "z", 10, {0, {0}}, 0, 0 },
553 { "n", 11, {0, {0}}, 0, 0 },
554 { "o", 12, {0, {0}}, 0, 0 },
555 { "le", 13, {0, {0}}, 0, 0 },
556 { "lt", 14, {0, {0}}, 0, 0 }
557 };
558
559 CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
560 {
561 & m32c_cgen_opval_h_cond32_entries[0],
562 18,
563 0, 0, 0, 0, ""
564 };
565
566 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] =
567 {
568 { "dct0", 0, {0, {0}}, 0, 0 },
569 { "dct1", 1, {0, {0}}, 0, 0 },
570 { "flg", 2, {0, {0}}, 0, 0 },
571 { "svf", 3, {0, {0}}, 0, 0 },
572 { "drc0", 4, {0, {0}}, 0, 0 },
573 { "drc1", 5, {0, {0}}, 0, 0 },
574 { "dmd0", 6, {0, {0}}, 0, 0 },
575 { "dmd1", 7, {0, {0}}, 0, 0 }
576 };
577
578 CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
579 {
580 & m32c_cgen_opval_h_cr1_32_entries[0],
581 8,
582 0, 0, 0, 0, ""
583 };
584
585 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] =
586 {
587 { "intb", 0, {0, {0}}, 0, 0 },
588 { "sp", 1, {0, {0}}, 0, 0 },
589 { "sb", 2, {0, {0}}, 0, 0 },
590 { "fb", 3, {0, {0}}, 0, 0 },
591 { "svp", 4, {0, {0}}, 0, 0 },
592 { "vct", 5, {0, {0}}, 0, 0 },
593 { "isp", 7, {0, {0}}, 0, 0 }
594 };
595
596 CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
597 {
598 & m32c_cgen_opval_h_cr2_32_entries[0],
599 7,
600 0, 0, 0, 0, ""
601 };
602
603 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] =
604 {
605 { "dma0", 2, {0, {0}}, 0, 0 },
606 { "dma1", 3, {0, {0}}, 0, 0 },
607 { "dra0", 4, {0, {0}}, 0, 0 },
608 { "dra1", 5, {0, {0}}, 0, 0 },
609 { "dsa0", 6, {0, {0}}, 0, 0 },
610 { "dsa1", 7, {0, {0}}, 0, 0 }
611 };
612
613 CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
614 {
615 & m32c_cgen_opval_h_cr3_32_entries[0],
616 6,
617 0, 0, 0, 0, ""
618 };
619
620 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] =
621 {
622 { "intbl", 1, {0, {0}}, 0, 0 },
623 { "intbh", 2, {0, {0}}, 0, 0 },
624 { "flg", 3, {0, {0}}, 0, 0 },
625 { "isp", 4, {0, {0}}, 0, 0 },
626 { "sp", 5, {0, {0}}, 0, 0 },
627 { "sb", 6, {0, {0}}, 0, 0 },
628 { "fb", 7, {0, {0}}, 0, 0 }
629 };
630
631 CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
632 {
633 & m32c_cgen_opval_h_cr_16_entries[0],
634 7,
635 0, 0, 0, 0, ""
636 };
637
638 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] =
639 {
640 { "c", 0, {0, {0}}, 0, 0 },
641 { "d", 1, {0, {0}}, 0, 0 },
642 { "z", 2, {0, {0}}, 0, 0 },
643 { "s", 3, {0, {0}}, 0, 0 },
644 { "b", 4, {0, {0}}, 0, 0 },
645 { "o", 5, {0, {0}}, 0, 0 },
646 { "i", 6, {0, {0}}, 0, 0 },
647 { "u", 7, {0, {0}}, 0, 0 }
648 };
649
650 CGEN_KEYWORD m32c_cgen_opval_h_flags =
651 {
652 & m32c_cgen_opval_h_flags_entries[0],
653 8,
654 0, 0, 0, 0, ""
655 };
656
657 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] =
658 {
659 { "1", 0, {0, {0}}, 0, 0 },
660 { "2", 1, {0, {0}}, 0, 0 },
661 { "3", 2, {0, {0}}, 0, 0 },
662 { "4", 3, {0, {0}}, 0, 0 },
663 { "5", 4, {0, {0}}, 0, 0 },
664 { "6", 5, {0, {0}}, 0, 0 },
665 { "7", 6, {0, {0}}, 0, 0 },
666 { "8", 7, {0, {0}}, 0, 0 },
667 { "-1", -8, {0, {0}}, 0, 0 },
668 { "-2", -7, {0, {0}}, 0, 0 },
669 { "-3", -6, {0, {0}}, 0, 0 },
670 { "-4", -5, {0, {0}}, 0, 0 },
671 { "-5", -4, {0, {0}}, 0, 0 },
672 { "-6", -3, {0, {0}}, 0, 0 },
673 { "-7", -2, {0, {0}}, 0, 0 },
674 { "-8", -1, {0, {0}}, 0, 0 }
675 };
676
677 CGEN_KEYWORD m32c_cgen_opval_h_shimm =
678 {
679 & m32c_cgen_opval_h_shimm_entries[0],
680 16,
681 0, 0, 0, 0, ""
682 };
683
684
685 /* The hardware table. */
686
687 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
688 #define A(a) (1 << CGEN_HW_##a)
689 #else
690 #define A(a) (1 << CGEN_HW_/**/a)
691 #endif
692
693 const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
694 {
695 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
696 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
697 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
698 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
699 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
700 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
701 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
702 { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
703 { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
704 { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
705 { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
706 { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
707 { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
708 { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
709 { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
710 { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
711 { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
712 { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
713 { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
714 { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
715 { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
716 { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
717 { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
718 { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
719 { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
720 { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
721 { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
722 { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
723 { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
724 { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
725 { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
726 { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
727 { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
728 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
729 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
730 { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
731 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
732 { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
733 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
734 { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
735 { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
736 { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
737 { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
738 { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
739 { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
740 { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
741 { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
742 { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
743 { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
744 { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
745 { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
746 { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
747 { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
748 { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
749 { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
750 { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
751 { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
752 { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
753 { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
754 { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
755 { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
756 { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
757 { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
758 { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
759 { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
760 { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
761 { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
762 { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
763 { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
764 { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
765 { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
766 { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
767 { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
768 { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
769 { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
770 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
771 };
772
773 #undef A
774
775
776 /* The instruction field table. */
777
778 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
779 #define A(a) (1 << CGEN_IFLD_##a)
780 #else
781 #define A(a) (1 << CGEN_IFLD_/**/a)
782 #endif
783
784 const CGEN_IFLD m32c_cgen_ifld_table[] =
785 {
786 { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
787 { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
788 { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
789 { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
790 { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
791 { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
792 { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
793 { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
794 { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
795 { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
796 { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
797 { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
798 { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
799 { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
800 { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
801 { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
802 { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
803 { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
804 { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
805 { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
806 { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
807 { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
808 { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
809 { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
810 { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
811 { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
812 { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
813 { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
814 { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
815 { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
816 { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
817 { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
818 { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
819 { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
820 { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
821 { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
822 { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
823 { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
824 { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
825 { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
826 { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
827 { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
828 { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
829 { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
830 { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
831 { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
832 { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
833 { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
834 { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
835 { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
836 { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
837 { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
838 { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
839 { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
840 { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
841 { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
842 { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
843 { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
844 { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
845 { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
846 { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
847 { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
848 { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
849 { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
850 { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
851 { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
852 { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
853 { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
854 { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
855 { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
856 { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
857 { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
858 { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
859 { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
860 { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
861 { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
862 { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
863 { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
864 { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
865 { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
866 { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
867 { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
868 { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
869 { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
870 { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
871 { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
872 { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
873 { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
874 { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
875 { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
876 { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
877 { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
878 { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
879 { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
880 { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
881 { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
882 { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
883 { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
884 { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
885 { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
886 { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
887 { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
888 { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
889 { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
890 { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
891 { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
892 { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
893 { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
894 { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
895 { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
896 { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
897 { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
898 { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
899 { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
900 { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
901 { M32C_F_DSP_8_S24, "f-dsp-8-s24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
902 { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
903 { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
904 { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
905 { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
906 { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
907 { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
908 { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
909 { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
910 { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
911 { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
912 { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
913 { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
914 { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
915 { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
916 { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
917 { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
918 { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
919 { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
920 { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
921 { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
922 { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
923 { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
924 { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
925 { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
926 { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
927 { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
928 { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
929 { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
930 { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
931 { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
932 { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
933 { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
934 { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
935 { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
936 { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
937 { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
938 { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
939 { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
940 { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
941 { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
942 { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
943 { 0, 0, 0, 0, 0, 0, {0, {0}} }
944 };
945
946 #undef A
947
948
949
950 /* multi ifield declarations */
951
952 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [];
953 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [];
954 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [];
955 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [];
956 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [];
957 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [];
958 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [];
959 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [];
960 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [];
961 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [];
962 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [];
963 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [];
964 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [];
965 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [];
966 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [];
967 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [];
968 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [];
969 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [];
970 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [];
971 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [];
972 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [];
973 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [];
974 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [];
975 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [];
976 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [];
977 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [];
978
979
980 /* multi ifield definitions */
981
982 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [] =
983 {
984 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
985 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
986 { 0, { (const PTR) 0 } }
987 };
988 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [] =
989 {
990 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
991 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
992 { 0, { (const PTR) 0 } }
993 };
994 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [] =
995 {
996 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
997 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
998 { 0, { (const PTR) 0 } }
999 };
1000 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [] =
1001 {
1002 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1003 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1004 { 0, { (const PTR) 0 } }
1005 };
1006 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [] =
1007 {
1008 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1009 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1010 { 0, { (const PTR) 0 } }
1011 };
1012 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] =
1013 {
1014 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1015 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1016 { 0, { (const PTR) 0 } }
1017 };
1018 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] =
1019 {
1020 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1021 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1022 { 0, { (const PTR) 0 } }
1023 };
1024 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [] =
1025 {
1026 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1027 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1028 { 0, { (const PTR) 0 } }
1029 };
1030 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [] =
1031 {
1032 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1033 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1034 { 0, { (const PTR) 0 } }
1035 };
1036 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [] =
1037 {
1038 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1039 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1040 { 0, { (const PTR) 0 } }
1041 };
1042 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [] =
1043 {
1044 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1045 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1046 { 0, { (const PTR) 0 } }
1047 };
1048 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [] =
1049 {
1050 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } },
1051 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1052 { 0, { (const PTR) 0 } }
1053 };
1054 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [] =
1055 {
1056 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } },
1057 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1058 { 0, { (const PTR) 0 } }
1059 };
1060 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [] =
1061 {
1062 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1063 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1064 { 0, { (const PTR) 0 } }
1065 };
1066 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [] =
1067 {
1068 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1069 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1070 { 0, { (const PTR) 0 } }
1071 };
1072 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [] =
1073 {
1074 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1075 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1076 { 0, { (const PTR) 0 } }
1077 };
1078 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [] =
1079 {
1080 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1081 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1082 { 0, { (const PTR) 0 } }
1083 };
1084 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [] =
1085 {
1086 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1087 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1088 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1089 { 0, { (const PTR) 0 } }
1090 };
1091 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [] =
1092 {
1093 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1094 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1095 { 0, { (const PTR) 0 } }
1096 };
1097 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [] =
1098 {
1099 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1100 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1101 { 0, { (const PTR) 0 } }
1102 };
1103 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [] =
1104 {
1105 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1106 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1107 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1108 { 0, { (const PTR) 0 } }
1109 };
1110 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [] =
1111 {
1112 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1113 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1114 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1115 { 0, { (const PTR) 0 } }
1116 };
1117 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [] =
1118 {
1119 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1120 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1121 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1122 { 0, { (const PTR) 0 } }
1123 };
1124 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [] =
1125 {
1126 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
1127 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1128 { 0, { (const PTR) 0 } }
1129 };
1130 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [] =
1131 {
1132 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } },
1133 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1134 { 0, { (const PTR) 0 } }
1135 };
1136 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [] =
1137 {
1138 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } },
1139 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1140 { 0, { (const PTR) 0 } }
1141 };
1142
1143 /* The operand table. */
1144
1145 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1146 #define A(a) (1 << CGEN_OPERAND_##a)
1147 #else
1148 #define A(a) (1 << CGEN_OPERAND_/**/a)
1149 #endif
1150 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1151 #define OPERAND(op) M32C_OPERAND_##op
1152 #else
1153 #define OPERAND(op) M32C_OPERAND_/**/op
1154 #endif
1155
1156 const CGEN_OPERAND m32c_cgen_operand_table[] =
1157 {
1158 /* pc: program counter */
1159 { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
1160 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
1161 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1162 /* Src16RnQI: general register QI view */
1163 { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
1164 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1165 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1166 /* Src16RnHI: general register QH view */
1167 { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
1168 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1169 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1170 /* Src32RnUnprefixedQI: general register QI view */
1171 { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
1172 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
1173 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1174 /* Src32RnUnprefixedHI: general register HI view */
1175 { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
1176 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
1177 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1178 /* Src32RnUnprefixedSI: general register SI view */
1179 { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
1180 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
1181 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1182 /* Src32RnPrefixedQI: general register QI view */
1183 { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
1184 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
1185 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1186 /* Src32RnPrefixedHI: general register HI view */
1187 { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
1188 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
1189 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1190 /* Src32RnPrefixedSI: general register SI view */
1191 { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
1192 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
1193 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1194 /* Src16An: address register */
1195 { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
1196 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1197 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1198 /* Src16AnQI: address register QI view */
1199 { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
1200 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1201 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1202 /* Src16AnHI: address register HI view */
1203 { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
1204 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1205 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1206 /* Src32AnUnprefixed: address register */
1207 { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
1208 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1209 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1210 /* Src32AnUnprefixedQI: address register QI view */
1211 { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
1212 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1213 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1214 /* Src32AnUnprefixedHI: address register HI view */
1215 { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
1216 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1217 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1218 /* Src32AnUnprefixedSI: address register SI view */
1219 { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
1220 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1221 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1222 /* Src32AnPrefixed: address register */
1223 { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
1224 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1225 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1226 /* Src32AnPrefixedQI: address register QI view */
1227 { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
1228 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1229 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1230 /* Src32AnPrefixedHI: address register HI view */
1231 { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
1232 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1233 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1234 /* Src32AnPrefixedSI: address register SI view */
1235 { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
1236 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1237 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1238 /* Dst16RnQI: general register QI view */
1239 { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
1240 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1241 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1242 /* Dst16RnHI: general register HI view */
1243 { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
1244 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1245 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1246 /* Dst16RnSI: general register SI view */
1247 { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
1248 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1249 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1250 /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
1251 { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
1252 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
1253 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1254 /* Dst32R0QI-S: general register QI view */
1255 { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
1256 { 0, { (const PTR) 0 } },
1257 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1258 /* Dst32R0HI-S: general register HI view */
1259 { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
1260 { 0, { (const PTR) 0 } },
1261 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1262 /* Dst32RnUnprefixedQI: general register QI view */
1263 { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
1264 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1265 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1266 /* Dst32RnUnprefixedHI: general register HI view */
1267 { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
1268 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
1269 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1270 /* Dst32RnUnprefixedSI: general register SI view */
1271 { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
1272 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
1273 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1274 /* Dst32RnExtUnprefixedQI: general register QI view */
1275 { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
1276 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1277 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1278 /* Dst32RnExtUnprefixedHI: general register HI view */
1279 { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
1280 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1281 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1282 /* Dst32RnPrefixedQI: general register QI view */
1283 { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
1284 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1285 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1286 /* Dst32RnPrefixedHI: general register HI view */
1287 { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
1288 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
1289 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1290 /* Dst32RnPrefixedSI: general register SI view */
1291 { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
1292 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
1293 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1294 /* Dst16RnQI-S: general register QI view */
1295 { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
1296 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1297 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1298 /* Dst16AnQI-S: address register QI view */
1299 { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
1300 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1301 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1302 /* Bit16Rn: general register bit view */
1303 { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
1304 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1305 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1306 /* Bit32RnPrefixed: general register bit view */
1307 { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
1308 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1309 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1310 /* Bit32RnUnprefixed: general register bit view */
1311 { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
1312 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1313 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1314 /* R0: r0 */
1315 { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
1316 { 0, { (const PTR) 0 } },
1317 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1318 /* R1: r1 */
1319 { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
1320 { 0, { (const PTR) 0 } },
1321 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1322 /* R2: r2 */
1323 { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
1324 { 0, { (const PTR) 0 } },
1325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1326 /* R3: r3 */
1327 { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
1328 { 0, { (const PTR) 0 } },
1329 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1330 /* R0l: r0l */
1331 { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
1332 { 0, { (const PTR) 0 } },
1333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1334 /* R0h: r0h */
1335 { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
1336 { 0, { (const PTR) 0 } },
1337 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1338 /* R2R0: r2r0 */
1339 { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
1340 { 0, { (const PTR) 0 } },
1341 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1342 /* R3R1: r3r1 */
1343 { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
1344 { 0, { (const PTR) 0 } },
1345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1346 /* R1R2R0: r1r2r0 */
1347 { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
1348 { 0, { (const PTR) 0 } },
1349 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1350 /* Dst16An: address register */
1351 { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
1352 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1353 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1354 /* Dst16AnQI: address register QI view */
1355 { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
1356 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1357 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1358 /* Dst16AnHI: address register HI view */
1359 { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
1360 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1361 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1362 /* Dst16AnSI: address register SI view */
1363 { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
1364 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1365 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1366 /* Dst16An-S: address register HI view */
1367 { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
1368 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
1369 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1370 /* Dst32AnUnprefixed: address register */
1371 { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
1372 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1373 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1374 /* Dst32AnUnprefixedQI: address register QI view */
1375 { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
1376 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1377 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1378 /* Dst32AnUnprefixedHI: address register HI view */
1379 { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
1380 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1381 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1382 /* Dst32AnUnprefixedSI: address register SI view */
1383 { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
1384 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1385 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1386 /* Dst32AnExtUnprefixed: address register */
1387 { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
1388 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1389 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1390 /* Dst32AnPrefixed: address register */
1391 { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
1392 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1393 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1394 /* Dst32AnPrefixedQI: address register QI view */
1395 { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
1396 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1397 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1398 /* Dst32AnPrefixedHI: address register HI view */
1399 { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
1400 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1401 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1402 /* Dst32AnPrefixedSI: address register SI view */
1403 { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
1404 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1405 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1406 /* Bit16An: address register bit view */
1407 { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
1408 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1409 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1410 /* Bit32AnPrefixed: address register bit */
1411 { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
1412 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1413 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1414 /* Bit32AnUnprefixed: address register bit */
1415 { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
1416 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1417 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1418 /* A0: a0 */
1419 { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
1420 { 0, { (const PTR) 0 } },
1421 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1422 /* A1: a1 */
1423 { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
1424 { 0, { (const PTR) 0 } },
1425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1426 /* sb: SB register */
1427 { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
1428 { 0, { (const PTR) 0 } },
1429 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1430 /* fb: FB register */
1431 { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
1432 { 0, { (const PTR) 0 } },
1433 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1434 /* sp: SP register */
1435 { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
1436 { 0, { (const PTR) 0 } },
1437 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1438 /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
1439 { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
1440 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
1441 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1442 /* Regsetpop: popm regset */
1443 { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
1444 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1446 /* Regsetpush: pushm regset */
1447 { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
1448 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1449 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1450 /* Rn16-push-S: r0[lh] */
1451 { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
1452 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1453 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1454 /* An16-push-S: a[01] */
1455 { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
1456 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1457 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1458 /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
1459 { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
1460 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
1461 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1462 /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
1463 { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
1464 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1466 /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
1467 { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
1468 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
1469 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1470 /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
1471 { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
1472 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1474 /* Dsp-8-s24: signed 24 bit displacement at offset 8 bits */
1475 { "Dsp-8-s24", M32C_OPERAND_DSP_8_S24, HW_H_SINT, 8, 24,
1476 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S24] } },
1477 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1478 /* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
1479 { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
1480 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
1481 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1482 /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
1483 { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
1484 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
1485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1486 /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
1487 { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
1488 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1489 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1490 /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
1491 { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
1492 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1494 /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
1495 { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
1496 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1497 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1498 /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
1499 { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
1500 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1501 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1502 /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
1503 { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
1504 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1506 /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
1507 { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
1508 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1509 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1510 /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
1511 { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
1512 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1514 /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
1515 { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
1516 { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
1517 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1518 /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
1519 { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
1520 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1521 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1522 /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
1523 { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
1524 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1525 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1526 /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
1527 { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
1528 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1529 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1530 /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
1531 { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
1532 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1533 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1534 /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
1535 { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
1536 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1537 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1538 /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
1539 { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
1540 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1541 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1542 /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
1543 { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
1544 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1546 /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
1547 { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
1548 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1549 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1550 /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
1551 { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
1552 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1554 /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
1555 { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
1556 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1557 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1558 /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
1559 { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
1560 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1561 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1562 /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
1563 { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
1564 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1566 /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
1567 { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
1568 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
1569 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1570 /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
1571 { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
1572 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1574 /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
1575 { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
1576 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1577 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1578 /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
1579 { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
1580 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
1581 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1582 /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
1583 { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
1584 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1586 /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
1587 { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
1588 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1589 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1590 /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
1591 { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
1592 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1594 /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
1595 { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
1596 { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
1597 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1598 /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
1599 { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
1600 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1601 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1602 /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
1603 { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
1604 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1606 /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
1607 { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
1608 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1609 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1610 /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
1611 { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
1612 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
1613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1614 /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
1615 { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
1616 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1617 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1618 /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
1619 { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
1620 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1621 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1622 /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
1623 { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
1624 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
1625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1626 /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
1627 { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
1628 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1629 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1630 /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
1631 { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
1632 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1634 /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
1635 { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
1636 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1637 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1638 /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
1639 { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
1640 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1641 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1642 /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
1643 { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
1644 { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
1645 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1646 /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
1647 { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
1648 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1649 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1650 /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
1651 { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
1652 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1653 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1654 /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
1655 { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
1656 { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
1657 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1658 /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
1659 { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
1660 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1661 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1662 /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
1663 { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
1664 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
1665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1666 /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
1667 { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
1668 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1669 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1670 /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
1671 { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
1672 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1674 /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
1675 { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
1676 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1677 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1678 /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
1679 { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
1680 { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
1681 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1682 /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
1683 { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
1684 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1686 /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
1687 { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
1688 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1689 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1690 /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
1691 { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
1692 { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
1693 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1694 /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
1695 { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
1696 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
1697 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1698 /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
1699 { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
1700 { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
1701 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1702 /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
1703 { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
1704 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
1705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1706 /* Imm1-S: signed 1 bit immediate for short format binary insns */
1707 { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
1708 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
1709 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1710 /* Imm3-S: signed 3 bit immediate for short format binary insns */
1711 { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
1712 { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
1713 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1714 /* Bitno16R: bit number for indexing registers */
1715 { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
1716 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1717 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1718 /* Bitno32Prefixed: bit number for indexing objects */
1719 { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
1720 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1721 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1722 /* Bitno32Unprefixed: bit number for indexing objects */
1723 { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
1724 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1726 /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
1727 { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
1728 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1729 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1730 /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
1731 { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
1732 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1734 /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
1735 { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
1736 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1737 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1738 /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
1739 { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
1740 { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
1741 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1742 /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
1743 { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
1744 { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
1745 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1746 /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
1747 { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
1748 { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
1749 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1750 /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
1751 { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
1752 { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
1753 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1754 /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
1755 { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
1756 { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
1757 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1758 /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
1759 { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
1760 { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
1761 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1762 /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
1763 { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
1764 { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
1765 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1766 /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
1767 { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
1768 { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
1769 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1770 /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
1771 { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
1772 { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
1773 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1774 /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
1775 { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
1776 { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
1777 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1778 /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
1779 { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
1780 { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
1781 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1782 /* Lab-5-3: 3 bit label */
1783 { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
1784 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
1785 { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1786 /* Lab32-jmp-s: 3 bit label */
1787 { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
1788 { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
1789 { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1790 /* Lab-8-8: 8 bit label */
1791 { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
1792 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
1793 { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1794 /* Lab-8-16: 16 bit label */
1795 { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
1796 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
1797 { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1798 /* Lab-8-24: 24 bit label */
1799 { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
1800 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
1801 { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1802 /* Lab-16-8: 8 bit label */
1803 { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
1804 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
1805 { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1806 /* Lab-24-8: 8 bit label */
1807 { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
1808 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
1809 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1810 /* Lab-32-8: 8 bit label */
1811 { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
1812 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
1813 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1814 /* Lab-40-8: 8 bit label */
1815 { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
1816 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
1817 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1818 /* sbit: negative bit */
1819 { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
1820 { 0, { (const PTR) 0 } },
1821 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1822 /* obit: overflow bit */
1823 { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
1824 { 0, { (const PTR) 0 } },
1825 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1826 /* zbit: zero bit */
1827 { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
1828 { 0, { (const PTR) 0 } },
1829 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1830 /* cbit: carry bit */
1831 { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
1832 { 0, { (const PTR) 0 } },
1833 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1834 /* ubit: stack ptr select bit */
1835 { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
1836 { 0, { (const PTR) 0 } },
1837 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1838 /* ibit: interrupt enable bit */
1839 { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
1840 { 0, { (const PTR) 0 } },
1841 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1842 /* bbit: reg bank select bit */
1843 { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
1844 { 0, { (const PTR) 0 } },
1845 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1846 /* dbit: debug bit */
1847 { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
1848 { 0, { (const PTR) 0 } },
1849 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1850 /* cond16-16: condition */
1851 { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
1852 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1854 /* cond16-24: condition */
1855 { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
1856 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1857 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1858 /* cond16-32: condition */
1859 { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
1860 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1861 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1862 /* cond32-16: condition */
1863 { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
1864 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1866 /* cond32-24: condition */
1867 { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
1868 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1869 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1870 /* cond32-32: condition */
1871 { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
1872 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1874 /* cond32-40: condition */
1875 { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
1876 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1877 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1878 /* cond16c: condition */
1879 { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
1880 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1881 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1882 /* cond16j: condition */
1883 { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
1884 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1886 /* cond16j5: condition */
1887 { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
1888 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
1889 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1890 /* cond32: condition */
1891 { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
1892 { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
1893 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1894 /* cond32j: condition */
1895 { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
1896 { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
1897 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1898 /* sccond32: scCND condition */
1899 { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
1900 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1901 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1902 /* flags16: flags */
1903 { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
1904 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1906 /* flags32: flags */
1907 { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
1908 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1909 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1910 /* cr16: control */
1911 { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
1912 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1914 /* cr1-Unprefixed-32: control */
1915 { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
1916 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1917 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1918 /* cr1-Prefixed-32: control */
1919 { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
1920 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1921 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1922 /* cr2-32: control */
1923 { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
1924 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1926 /* cr3-Unprefixed-32: control */
1927 { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
1928 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1929 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1930 /* cr3-Prefixed-32: control */
1931 { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
1932 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1934 /* Z: Suffix for zero format insns */
1935 { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
1936 { 0, { (const PTR) 0 } },
1937 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1938 /* S: Suffix for short format insns */
1939 { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
1940 { 0, { (const PTR) 0 } },
1941 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1942 /* Q: Suffix for quick format insns */
1943 { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
1944 { 0, { (const PTR) 0 } },
1945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1946 /* G: Suffix for general format insns */
1947 { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
1948 { 0, { (const PTR) 0 } },
1949 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1950 /* X: Empty suffix */
1951 { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
1952 { 0, { (const PTR) 0 } },
1953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1954 /* size: any size specifier */
1955 { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
1956 { 0, { (const PTR) 0 } },
1957 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1958 /* BitIndex: Bit Index for the next insn */
1959 { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
1960 { 0, { (const PTR) 0 } },
1961 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1962 /* SrcIndex: Source Index for the next insn */
1963 { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
1964 { 0, { (const PTR) 0 } },
1965 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1966 /* DstIndex: Destination Index for the next insn */
1967 { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
1968 { 0, { (const PTR) 0 } },
1969 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1970 /* NoRemainder: Place holder for when the remainder is not kept */
1971 { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
1972 { 0, { (const PTR) 0 } },
1973 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1974 /* src16-Rn-direct-QI: m16c Rn direct source QI */
1975 /* src16-Rn-direct-HI: m16c Rn direct source HI */
1976 /* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */
1977 /* src32-Rn-direct-Prefixed-QI: m32c Rn direct source QI */
1978 /* src32-Rn-direct-Unprefixed-HI: m32c Rn direct source HI */
1979 /* src32-Rn-direct-Prefixed-HI: m32c Rn direct source HI */
1980 /* src32-Rn-direct-Unprefixed-SI: m32c Rn direct source SI */
1981 /* src32-Rn-direct-Prefixed-SI: m32c Rn direct source SI */
1982 /* src16-An-direct-QI: m16c An direct destination QI */
1983 /* src16-An-direct-HI: m16c An direct destination HI */
1984 /* src32-An-direct-Unprefixed-QI: m32c An direct destination QI */
1985 /* src32-An-direct-Unprefixed-HI: m32c An direct destination HI */
1986 /* src32-An-direct-Unprefixed-SI: m32c An direct destination SI */
1987 /* src32-An-direct-Prefixed-QI: m32c An direct destination QI */
1988 /* src32-An-direct-Prefixed-HI: m32c An direct destination HI */
1989 /* src32-An-direct-Prefixed-SI: m32c An direct destination SI */
1990 /* src16-An-indirect-QI: m16c An indirect destination QI */
1991 /* src16-An-indirect-HI: m16c An indirect destination HI */
1992 /* src32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
1993 /* src32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
1994 /* src32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
1995 /* src32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
1996 /* src32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
1997 /* src32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
1998 /* src16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
1999 /* src16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2000 /* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2001 /* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2002 /* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2003 /* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2004 /* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2005 /* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2006 /* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2007 /* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2008 /* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2009 /* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2010 /* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2011 /* src32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2012 /* src32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2013 /* src32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2014 /* src32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2015 /* src32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2016 /* src32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2017 /* src32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2018 /* src32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2019 /* src32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2020 /* src32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2021 /* src32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2022 /* src32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2023 /* src32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2024 /* src32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2025 /* src32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2026 /* src32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2027 /* src32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2028 /* src32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2029 /* src32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2030 /* src32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2031 /* src32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2032 /* src32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2033 /* src32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2034 /* src32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2035 /* src32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2036 /* src32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2037 /* src32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2038 /* src32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2039 /* src32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2040 /* src32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2041 /* src32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2042 /* src32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2043 /* src32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2044 /* src32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2045 /* src32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2046 /* src32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2047 /* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2048 /* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2049 /* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2050 /* src16-16-16-absolute-QI: m16c absolute address QI */
2051 /* src16-16-16-absolute-HI: m16c absolute address HI */
2052 /* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2053 /* src32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2054 /* src32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2055 /* src32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2056 /* src32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2057 /* src32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2058 /* src32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2059 /* src32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2060 /* src32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2061 /* src32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2062 /* src32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2063 /* src32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2064 /* src16-2-S-8-SB-relative-QI: m16c SB relative address */
2065 /* src16-2-S-8-FB-relative-QI: m16c FB relative address */
2066 /* src16-2-S-16-absolute-QI: m16c absolute address */
2067 /* src32-2-S-8-SB-relative-QI: m32c SB relative address */
2068 /* src32-2-S-8-FB-relative-QI: m32c FB relative address */
2069 /* src32-2-S-16-absolute-QI: m32c absolute address */
2070 /* src32-2-S-8-SB-relative-HI: m32c SB relative address */
2071 /* src32-2-S-8-FB-relative-HI: m32c FB relative address */
2072 /* src32-2-S-16-absolute-HI: m32c absolute address */
2073 /* dst16-Rn-direct-QI: m16c Rn direct destination QI */
2074 /* dst16-Rn-direct-HI: m16c Rn direct destination HI */
2075 /* dst16-Rn-direct-SI: m16c Rn direct destination SI */
2076 /* dst16-Rn-direct-Ext-QI: m16c Rn direct destination QI */
2077 /* dst32-Rn-direct-Unprefixed-QI: m32c Rn direct destination QI */
2078 /* dst32-Rn-direct-Prefixed-QI: m32c Rn direct destination QI */
2079 /* dst32-Rn-direct-Unprefixed-HI: m32c Rn direct destination HI */
2080 /* dst32-Rn-direct-Prefixed-HI: m32c Rn direct destination HI */
2081 /* dst32-Rn-direct-Unprefixed-SI: m32c Rn direct destination SI */
2082 /* dst32-Rn-direct-Prefixed-SI: m32c Rn direct destination SI */
2083 /* dst32-Rn-direct-ExtUnprefixed-QI: m32c Rn direct destination QI */
2084 /* dst32-Rn-direct-ExtUnprefixed-HI: m32c Rn direct destination HI */
2085 /* dst32-R3-direct-Unprefixed-HI: m32c R3 direct HI */
2086 /* dst16-An-direct-QI: m16c An direct destination QI */
2087 /* dst16-An-direct-HI: m16c An direct destination HI */
2088 /* dst16-An-direct-SI: m16c An direct destination SI */
2089 /* dst32-An-direct-Unprefixed-QI: m32c An direct destination QI */
2090 /* dst32-An-direct-Prefixed-QI: m32c An direct destination QI */
2091 /* dst32-An-direct-Unprefixed-HI: m32c An direct destination HI */
2092 /* dst32-An-direct-Prefixed-HI: m32c An direct destination HI */
2093 /* dst32-An-direct-Unprefixed-SI: m32c An direct destination SI */
2094 /* dst32-An-direct-Prefixed-SI: m32c An direct destination SI */
2095 /* dst16-An-indirect-QI: m16c An indirect destination QI */
2096 /* dst16-An-indirect-HI: m16c An indirect destination HI */
2097 /* dst16-An-indirect-SI: m16c An indirect destination SI */
2098 /* dst16-An-indirect-Ext-QI: m16c An indirect destination QI */
2099 /* dst32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
2100 /* dst32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
2101 /* dst32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
2102 /* dst32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
2103 /* dst32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
2104 /* dst32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
2105 /* dst32-An-indirect-ExtUnprefixed-QI: m32c An indirect destination QI */
2106 /* dst32-An-indirect-ExtUnprefixed-HI: m32c An indirect destination HI */
2107 /* dst16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2108 /* dst16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2109 /* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2110 /* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2111 /* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2112 /* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2113 /* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2114 /* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2115 /* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2116 /* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2117 /* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2118 /* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2119 /* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2120 /* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2121 /* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2122 /* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2123 /* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2124 /* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2125 /* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2126 /* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2127 /* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2128 /* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2129 /* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2130 /* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2131 /* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2132 /* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2133 /* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2134 /* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2135 /* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2136 /* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2137 /* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2138 /* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2139 /* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2140 /* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2141 /* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2142 /* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2143 /* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2144 /* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2145 /* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2146 /* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2147 /* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2148 /* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2149 /* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2150 /* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2151 /* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2152 /* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2153 /* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2154 /* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2155 /* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2156 /* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2157 /* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2158 /* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2159 /* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2160 /* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2161 /* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2162 /* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2163 /* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2164 /* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2165 /* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2166 /* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2167 /* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2168 /* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2169 /* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2170 /* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2171 /* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2172 /* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2173 /* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2174 /* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2175 /* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2176 /* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2177 /* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2178 /* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2179 /* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2180 /* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2181 /* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2182 /* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */
2183 /* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */
2184 /* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */
2185 /* dst16-16-8-An-relative-Ext-QI: m16c dsp:8[An] relative destination QI */
2186 /* dst16-16-16-An-relative-Ext-QI: m16c dsp:16[An] relative destination QI */
2187 /* dst32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2188 /* dst32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2189 /* dst32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2190 /* dst32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2191 /* dst32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2192 /* dst32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2193 /* dst32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2194 /* dst32-24-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2195 /* dst32-24-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2196 /* dst32-24-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2197 /* dst32-24-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2198 /* dst32-24-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2199 /* dst32-24-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2200 /* dst32-24-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2201 /* dst32-32-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2202 /* dst32-32-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2203 /* dst32-32-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2204 /* dst32-32-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2205 /* dst32-32-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2206 /* dst32-32-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2207 /* dst32-32-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2208 /* dst32-40-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2209 /* dst32-40-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2210 /* dst32-40-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2211 /* dst32-40-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2212 /* dst32-40-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2213 /* dst32-40-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2214 /* dst32-40-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2215 /* dst32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2216 /* dst32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2217 /* dst32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2218 /* dst32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2219 /* dst32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2220 /* dst32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2221 /* dst32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2222 /* dst32-24-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2223 /* dst32-24-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2224 /* dst32-24-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2225 /* dst32-24-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2226 /* dst32-24-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2227 /* dst32-24-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2228 /* dst32-24-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2229 /* dst32-32-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2230 /* dst32-32-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2231 /* dst32-32-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2232 /* dst32-32-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2233 /* dst32-32-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2234 /* dst32-32-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2235 /* dst32-32-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2236 /* dst32-40-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2237 /* dst32-40-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2238 /* dst32-40-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2239 /* dst32-40-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2240 /* dst32-40-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2241 /* dst32-40-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2242 /* dst32-40-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2243 /* dst32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2244 /* dst32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2245 /* dst32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2246 /* dst32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2247 /* dst32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2248 /* dst32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2249 /* dst32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2250 /* dst32-24-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2251 /* dst32-24-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2252 /* dst32-24-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2253 /* dst32-24-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2254 /* dst32-24-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2255 /* dst32-24-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2256 /* dst32-24-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2257 /* dst32-32-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2258 /* dst32-32-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2259 /* dst32-32-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2260 /* dst32-32-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2261 /* dst32-32-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2262 /* dst32-32-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2263 /* dst32-32-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2264 /* dst32-40-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2265 /* dst32-40-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2266 /* dst32-40-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2267 /* dst32-40-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2268 /* dst32-40-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2269 /* dst32-40-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2270 /* dst32-40-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2271 /* dst32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2272 /* dst32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2273 /* dst32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2274 /* dst32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2275 /* dst32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2276 /* dst32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2277 /* dst32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2278 /* dst32-32-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2279 /* dst32-32-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2280 /* dst32-32-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2281 /* dst32-32-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2282 /* dst32-32-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2283 /* dst32-32-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2284 /* dst32-32-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2285 /* dst32-40-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2286 /* dst32-40-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2287 /* dst32-40-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2288 /* dst32-40-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2289 /* dst32-40-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2290 /* dst32-40-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2291 /* dst32-40-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2292 /* dst32-48-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2293 /* dst32-48-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2294 /* dst32-48-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2295 /* dst32-48-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2296 /* dst32-48-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2297 /* dst32-48-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2298 /* dst32-48-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2299 /* dst32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2300 /* dst32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2301 /* dst32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2302 /* dst32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2303 /* dst32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2304 /* dst32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2305 /* dst32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2306 /* dst32-32-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2307 /* dst32-32-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2308 /* dst32-32-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2309 /* dst32-32-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2310 /* dst32-32-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2311 /* dst32-32-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2312 /* dst32-32-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2313 /* dst32-40-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2314 /* dst32-40-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2315 /* dst32-40-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2316 /* dst32-40-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2317 /* dst32-40-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2318 /* dst32-40-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2319 /* dst32-40-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2320 /* dst32-48-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2321 /* dst32-48-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2322 /* dst32-48-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2323 /* dst32-48-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2324 /* dst32-48-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2325 /* dst32-48-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2326 /* dst32-48-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2327 /* dst32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2328 /* dst32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2329 /* dst32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2330 /* dst32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2331 /* dst32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2332 /* dst32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2333 /* dst32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2334 /* dst32-32-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2335 /* dst32-32-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2336 /* dst32-32-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2337 /* dst32-32-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2338 /* dst32-32-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2339 /* dst32-32-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2340 /* dst32-32-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2341 /* dst32-40-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2342 /* dst32-40-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2343 /* dst32-40-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2344 /* dst32-40-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2345 /* dst32-40-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2346 /* dst32-40-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2347 /* dst32-40-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2348 /* dst32-48-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2349 /* dst32-48-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2350 /* dst32-48-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2351 /* dst32-48-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2352 /* dst32-48-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2353 /* dst32-48-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2354 /* dst32-48-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2355 /* dst32-16-8-SB-relative-ExtUnprefixed-QI: m32c dsp:8[sb] relative destination QI */
2356 /* dst32-16-16-SB-relative-ExtUnprefixed-QI: m32c dsp:16[sb] relative destination QI */
2357 /* dst32-16-8-FB-relative-ExtUnprefixed-QI: m32c dsp:8[fb] relative destination QI */
2358 /* dst32-16-16-FB-relative-ExtUnprefixed-QI: m32c dsp:16[fb] relative destination QI */
2359 /* dst32-16-8-An-relative-ExtUnprefixed-QI: m32c dsp:8[An] relative destination QI */
2360 /* dst32-16-16-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2361 /* dst32-16-24-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2362 /* dst32-16-8-SB-relative-ExtUnprefixed-HI: m32c dsp:8[sb] relative destination HI */
2363 /* dst32-16-16-SB-relative-ExtUnprefixed-HI: m32c dsp:16[sb] relative destination HI */
2364 /* dst32-16-8-FB-relative-ExtUnprefixed-HI: m32c dsp:8[fb] relative destination HI */
2365 /* dst32-16-16-FB-relative-ExtUnprefixed-HI: m32c dsp:16[fb] relative destination HI */
2366 /* dst32-16-8-An-relative-ExtUnprefixed-HI: m32c dsp:8[An] relative destination HI */
2367 /* dst32-16-16-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2368 /* dst32-16-24-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2369 /* dst16-16-16-absolute-QI: m16c absolute address QI */
2370 /* dst16-24-16-absolute-QI: m16c absolute address QI */
2371 /* dst16-32-16-absolute-QI: m16c absolute address QI */
2372 /* dst16-40-16-absolute-QI: m16c absolute address QI */
2373 /* dst16-48-16-absolute-QI: m16c absolute address QI */
2374 /* dst16-16-16-absolute-HI: m16c absolute address HI */
2375 /* dst16-24-16-absolute-HI: m16c absolute address HI */
2376 /* dst16-32-16-absolute-HI: m16c absolute address HI */
2377 /* dst16-40-16-absolute-HI: m16c absolute address HI */
2378 /* dst16-48-16-absolute-HI: m16c absolute address HI */
2379 /* dst16-16-16-absolute-SI: m16c absolute address SI */
2380 /* dst16-24-16-absolute-SI: m16c absolute address SI */
2381 /* dst16-32-16-absolute-SI: m16c absolute address SI */
2382 /* dst16-40-16-absolute-SI: m16c absolute address SI */
2383 /* dst16-48-16-absolute-SI: m16c absolute address SI */
2384 /* dst16-16-16-absolute-Ext-QI: m16c absolute address QI */
2385 /* dst32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2386 /* dst32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2387 /* dst32-24-16-absolute-Unprefixed-QI: m32c absolute address QI */
2388 /* dst32-24-24-absolute-Unprefixed-QI: m32c absolute address QI */
2389 /* dst32-32-16-absolute-Unprefixed-QI: m32c absolute address QI */
2390 /* dst32-32-24-absolute-Unprefixed-QI: m32c absolute address QI */
2391 /* dst32-40-16-absolute-Unprefixed-QI: m32c absolute address QI */
2392 /* dst32-40-24-absolute-Unprefixed-QI: m32c absolute address QI */
2393 /* dst32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2394 /* dst32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2395 /* dst32-24-16-absolute-Unprefixed-HI: m32c absolute address HI */
2396 /* dst32-24-24-absolute-Unprefixed-HI: m32c absolute address HI */
2397 /* dst32-32-16-absolute-Unprefixed-HI: m32c absolute address HI */
2398 /* dst32-32-24-absolute-Unprefixed-HI: m32c absolute address HI */
2399 /* dst32-40-16-absolute-Unprefixed-HI: m32c absolute address HI */
2400 /* dst32-40-24-absolute-Unprefixed-HI: m32c absolute address HI */
2401 /* dst32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2402 /* dst32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2403 /* dst32-24-16-absolute-Unprefixed-SI: m32c absolute address SI */
2404 /* dst32-24-24-absolute-Unprefixed-SI: m32c absolute address SI */
2405 /* dst32-32-16-absolute-Unprefixed-SI: m32c absolute address SI */
2406 /* dst32-32-24-absolute-Unprefixed-SI: m32c absolute address SI */
2407 /* dst32-40-16-absolute-Unprefixed-SI: m32c absolute address SI */
2408 /* dst32-40-24-absolute-Unprefixed-SI: m32c absolute address SI */
2409 /* dst32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2410 /* dst32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2411 /* dst32-32-16-absolute-Prefixed-QI: m32c absolute address QI */
2412 /* dst32-32-24-absolute-Prefixed-QI: m32c absolute address QI */
2413 /* dst32-40-16-absolute-Prefixed-QI: m32c absolute address QI */
2414 /* dst32-40-24-absolute-Prefixed-QI: m32c absolute address QI */
2415 /* dst32-48-16-absolute-Prefixed-QI: m32c absolute address QI */
2416 /* dst32-48-24-absolute-Prefixed-QI: m32c absolute address QI */
2417 /* dst32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2418 /* dst32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2419 /* dst32-32-16-absolute-Prefixed-HI: m32c absolute address HI */
2420 /* dst32-32-24-absolute-Prefixed-HI: m32c absolute address HI */
2421 /* dst32-40-16-absolute-Prefixed-HI: m32c absolute address HI */
2422 /* dst32-40-24-absolute-Prefixed-HI: m32c absolute address HI */
2423 /* dst32-48-16-absolute-Prefixed-HI: m32c absolute address HI */
2424 /* dst32-48-24-absolute-Prefixed-HI: m32c absolute address HI */
2425 /* dst32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2426 /* dst32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2427 /* dst32-32-16-absolute-Prefixed-SI: m32c absolute address SI */
2428 /* dst32-32-24-absolute-Prefixed-SI: m32c absolute address SI */
2429 /* dst32-40-16-absolute-Prefixed-SI: m32c absolute address SI */
2430 /* dst32-40-24-absolute-Prefixed-SI: m32c absolute address SI */
2431 /* dst32-48-16-absolute-Prefixed-SI: m32c absolute address SI */
2432 /* dst32-48-24-absolute-Prefixed-SI: m32c absolute address SI */
2433 /* dst32-16-16-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2434 /* dst32-16-24-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2435 /* dst32-16-16-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2436 /* dst32-16-24-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2437 /* bit16-Rn-direct: m16c Rn direct bit */
2438 /* bit32-Rn-direct-Unprefixed: m32c Rn direct bit */
2439 /* bit32-Rn-direct-Prefixed: m32c Rn direct bit */
2440 /* bit16-An-direct: m16c An direct bit */
2441 /* bit32-An-direct-Unprefixed: m32c An direct bit */
2442 /* bit32-An-direct-Prefixed: m32c An direct bit */
2443 /* bit16-An-indirect: m16c An indirect bit */
2444 /* bit32-An-indirect-Unprefixed: m32c An indirect destination */
2445 /* bit32-An-indirect-Prefixed: m32c An indirect destination */
2446 /* bit16-16-8-SB-relative: m16c dsp:8[sb] relative bit xmode */
2447 /* bit16-16-16-SB-relative: m16c dsp:16[sb] relative bit xmode */
2448 /* bit16-16-8-FB-relative: m16c dsp:8[fb] relative bit xmode */
2449 /* bit16-16-8-An-relative: m16c dsp:8[An] relative bit xmode */
2450 /* bit16-16-16-An-relative: m16c dsp:16[An] relative bit xmode */
2451 /* bit32-16-11-SB-relative-Unprefixed: m32c bit,base:11[sb] relative bit */
2452 /* bit32-16-19-SB-relative-Unprefixed: m32c bit,base:19[sb] relative bit */
2453 /* bit32-16-11-FB-relative-Unprefixed: m32c bit,base:11[fb] relative bit */
2454 /* bit32-16-19-FB-relative-Unprefixed: m32c bit,base:19[fb] relative bit */
2455 /* bit32-16-11-An-relative-Unprefixed: m32c bit,base:11[An] relative bit */
2456 /* bit32-16-19-An-relative-Unprefixed: m32c bit,base:19[An] relative bit */
2457 /* bit32-16-27-An-relative-Unprefixed: m32c bit,base:27[An] relative bit */
2458 /* bit32-24-11-SB-relative-Prefixed: m32c bit,base:11[sb] relative bit */
2459 /* bit32-24-19-SB-relative-Prefixed: m32c bit,base:19[sb] relative bit */
2460 /* bit32-24-11-FB-relative-Prefixed: m32c bit,base:11[fb] relative bit */
2461 /* bit32-24-19-FB-relative-Prefixed: m32c bit,base:19[fb] relative bit */
2462 /* bit32-24-11-An-relative-Prefixed: m32c bit,base:11[An] relative bit */
2463 /* bit32-24-19-An-relative-Prefixed: m32c bit,base:19[An] relative bit */
2464 /* bit32-24-27-An-relative-Prefixed: m32c bit,base:27[An] relative bit */
2465 /* bit16-11-SB-relative-S: m16c bit,base:11[sb] relative bit */
2466 /* Rn16-push-S-derived: m16c r0[lh] for push,pop short version */
2467 /* An16-push-S-derived: m16c r0[lh] for push,pop short version */
2468 /* bit16-16-16-absolute: m16c absolute address */
2469 /* bit32-16-19-absolute-Unprefixed: m32c absolute address bit */
2470 /* bit32-16-27-absolute-Unprefixed: m32c absolute address bit */
2471 /* bit32-24-19-absolute-Prefixed: m32c absolute address bit */
2472 /* bit32-24-27-absolute-Prefixed: m32c absolute address bit */
2473 /* dst16-3-S-R0l-direct-QI: m16c R0l direct QI */
2474 /* dst16-3-S-R0h-direct-QI: m16c R0h direct QI */
2475 /* dst16-3-S-8-8-SB-relative-QI: m16c SB relative QI */
2476 /* dst16-3-S-8-8-FB-relative-QI: m16c FB relative QI */
2477 /* dst16-3-S-8-16-absolute-QI: m16c absolute address QI */
2478 /* dst16-3-S-16-8-SB-relative-QI: m16c SB relative QI */
2479 /* dst16-3-S-16-8-FB-relative-QI: m16c FB relative QI */
2480 /* dst16-3-S-16-16-absolute-QI: m16c absolute address QI */
2481 /* srcdst16-r0l-r0h-S-derived: m16c r0l/r0h operand for short format insns */
2482 /* dst32-2-S-R0l-direct-QI: m32c R0l direct QI */
2483 /* dst32-2-S-R0-direct-HI: m32c R0 direct HI */
2484 /* dst32-1-S-A0-direct-HI: m32c A0 direct HI */
2485 /* dst32-1-S-A1-direct-HI: m32c A1 direct HI */
2486 /* dst32-2-S-8-SB-relative-QI: m32c SB relative for short binary insns */
2487 /* dst32-2-S-8-FB-relative-QI: m32c FB relative for short binary insns */
2488 /* dst32-2-S-16-absolute-QI: m32c absolute address for short binary insns */
2489 /* dst32-2-S-8-SB-relative-HI: m32c SB relative for short binary insns */
2490 /* dst32-2-S-8-FB-relative-HI: m32c FB relative for short binary insns */
2491 /* dst32-2-S-16-absolute-HI: m32c absolute address for short binary insns */
2492 /* dst32-2-S-8-SB-relative-SI: m32c SB relative for short binary insns */
2493 /* dst32-2-S-8-FB-relative-SI: m32c FB relative for short binary insns */
2494 /* dst32-2-S-16-absolute-SI: m32c absolute address for short binary insns */
2495 /* src16-basic-QI: m16c source operand of size QI with no additional fields */
2496 /* src16-basic-HI: m16c source operand of size HI with no additional fields */
2497 /* src32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2498 /* src32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2499 /* src32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2500 /* src32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2501 /* src32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2502 /* src32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2503 /* src32-basic-ExtPrefixed-QI: m32c source operand of size QI with no additional fields */
2504 /* src16-16-8-QI: m16c source operand of size QI with additional 8 bit fields at offset 16 */
2505 /* src16-16-16-QI: m16c source operand of size QI with additional 16 bit fields at offset 16 */
2506 /* src16-16-8-HI: m16c source operand of size HI with additional 8 bit fields at offset 16 */
2507 /* src16-16-16-HI: m16c source operand of size HI with additional 16 bit fields at offset 16 */
2508 /* src32-16-8-Unprefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 16 */
2509 /* src32-16-16-Unprefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2510 /* src32-16-24-Unprefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2511 /* src32-16-8-Unprefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 16 */
2512 /* src32-16-16-Unprefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2513 /* src32-16-24-Unprefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2514 /* src32-16-8-Unprefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 16 */
2515 /* src32-16-16-Unprefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2516 /* src32-16-24-Unprefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2517 /* src32-24-8-Prefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 24 */
2518 /* src32-24-16-Prefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2519 /* src32-24-24-Prefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2520 /* src32-24-8-Prefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 24 */
2521 /* src32-24-16-Prefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2522 /* src32-24-24-Prefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2523 /* src32-24-8-Prefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 24 */
2524 /* src32-24-16-Prefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2525 /* src32-24-24-Prefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2526 /* dst16-basic-QI: m16c destination operand of size QI with no additional fields */
2527 /* dst16-basic-HI: m16c destination operand of size HI with no additional fields */
2528 /* dst16-basic-SI: m16c destination operand of size SI with no additional fields */
2529 /* dst32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2530 /* dst32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2531 /* dst32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2532 /* dst32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2533 /* dst32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2534 /* dst32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2535 /* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2536 /* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */
2537 /* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2538 /* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2539 /* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */
2540 /* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2541 /* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2542 /* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */
2543 /* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2544 /* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */
2545 /* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */
2546 /* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */
2547 /* dst16-16-16-An-relative-Mova-HI: m16c addressof dsp:16[An] relative destination HI */
2548 /* dst16-16-8-SB-relative-Mova-HI: m16c addressof dsp:8[sb] relative destination HI */
2549 /* dst16-16-16-SB-relative-Mova-HI: m16c addressof dsp:16[sb] relative destination HI */
2550 /* dst16-16-8-FB-relative-Mova-HI: m16c addressof dsp:8[fb] relative destination HI */
2551 /* dst16-16-16-absolute-Mova-HI: m16c addressof absolute address HI */
2552 /* dst16-16-Mova-HI: m16c addressof destination operand of size HI with additional fields at offset 16 */
2553 /* dst32-An-indirect-Unprefixed-Mova-SI: m32c addressof An indirect destination SI */
2554 /* dst32-16-8-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[An] relative destination SI */
2555 /* dst32-16-16-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[An] relative destination SI */
2556 /* dst32-16-24-An-relative-Unprefixed-Mova-SI: addressof m32c dsp:16[An] relative destination SI */
2557 /* dst32-16-8-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[sb] relative destination SI */
2558 /* dst32-16-16-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[sb] relative destination SI */
2559 /* dst32-16-8-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[fb] relative destination SI */
2560 /* dst32-16-16-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[fb] relative destination SI */
2561 /* dst32-16-16-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2562 /* dst32-16-24-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2563 /* dst32-16-Unprefixed-Mova-SI: m32c addressof destination operand of size SI with additional fields at offset 16 */
2564 /* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2565 /* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2566 /* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2567 /* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2568 /* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2569 /* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2570 /* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2571 /* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2572 /* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2573 /* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2574 /* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2575 /* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2576 /* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2577 /* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2578 /* dst32-16-Unprefixed-Mulex-HI: m32c destination operand of size HI with additional fields at offset 16 */
2579 /* dst16-24-QI: m16c destination operand of size QI with additional fields at offset 24 */
2580 /* dst16-24-HI: m16c destination operand of size HI with additional fields at offset 24 */
2581 /* dst32-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2582 /* dst32-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2583 /* dst32-24-8-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2584 /* dst32-24-16-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2585 /* dst32-24-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2586 /* dst32-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2587 /* dst32-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2588 /* dst32-24-8-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2589 /* dst32-24-16-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2590 /* dst32-24-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2591 /* dst32-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2592 /* dst32-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2593 /* dst32-24-8-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2594 /* dst32-24-16-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2595 /* dst32-24-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2596 /* dst16-32-QI: m16c destination operand of size QI with additional fields at offset 32 */
2597 /* dst16-32-HI: m16c destination operand of size HI with additional fields at offset 32 */
2598 /* dst32-32-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2599 /* dst32-32-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2600 /* dst32-32-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2601 /* dst32-32-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2602 /* dst32-32-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2603 /* dst32-32-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2604 /* dst32-40-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2605 /* dst32-40-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2606 /* dst32-40-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2607 /* dst32-40-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2608 /* dst32-40-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2609 /* dst32-40-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2610 /* dst32-48-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2611 /* dst32-48-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2612 /* dst32-48-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2613 /* bit16-16: m16c bit operand with possible additional fields at offset 24 */
2614 /* bit16-16-basic: m16c bit operand with no additional fields */
2615 /* bit16-16-8: m16c bit operand with possible additional fields at offset 24 */
2616 /* bit16-16-16: m16c bit operand with possible additional fields at offset 24 */
2617 /* bit32-16-Unprefixed: m32c bit operand with possible additional fields at offset 24 */
2618 /* bit32-24-Prefixed: m32c bit operand with possible additional fields at offset 24 */
2619 /* bit32-basic-Unprefixed: m32c bit operand with no additional fields */
2620 /* bit32-16-8-Unprefixed: m32c bit operand with 8 bit additional fields */
2621 /* bit32-16-16-Unprefixed: m32c bit operand with 16 bit additional fields */
2622 /* bit32-16-24-Unprefixed: m32c bit operand with 24 bit additional fields */
2623 /* src16-2-S: m16c source operand of size QI for short format insns */
2624 /* src32-2-S-QI: m32c source operand of size QI for short format insns */
2625 /* src32-2-S-HI: m32c source operand of size QI for short format insns */
2626 /* Dst16-3-S-8: m16c destination operand of size QI for short format insns */
2627 /* Dst16-3-S-16: m16c destination operand of size QI for short format insns */
2628 /* srcdst16-r0l-r0h-S: m16c r0l/r0h operand of size QI for short format insns */
2629 /* dst32-2-S-basic-QI: m32c r0l operand of size QI for short format binary insns */
2630 /* dst32-2-S-basic-HI: m32c r0 operand of size HI for short format binary insns */
2631 /* dst32-2-S-8-QI: m32c operand of size */
2632 /* dst32-2-S-16-QI: m32c operand of size */
2633 /* dst32-2-S-8-HI: m32c operand of size */
2634 /* dst32-2-S-16-HI: m32c operand of size */
2635 /* dst32-2-S-8-SI: m32c operand of size */
2636 /* dst32-2-S-16-SI: m32c operand of size */
2637 /* dst32-an-S: m32c An operand for short format binary insns */
2638 /* bit16-11-S: m16c bit operand for short format insns */
2639 /* Rn16-push-S-anyof: m16c bit operand for short format insns */
2640 /* An16-push-S-anyof: m16c bit operand for short format insns */
2641 /* sentinel */
2642 { 0, 0, 0, 0, 0,
2643 { 0, { (const PTR) 0 } },
2644 { 0, { 0 } } }
2645 };
2646
2647 #undef A
2648
2649
2650 /* The instruction table. */
2651
2652 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2653 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2654 #define A(a) (1 << CGEN_INSN_##a)
2655 #else
2656 #define A(a) (1 << CGEN_INSN_/**/a)
2657 #endif
2658
2659 static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
2660 {
2661 /* Special null first entry.
2662 A `num' value of zero is thus invalid.
2663 Also, the special `invalid' insn resides here. */
2664 { 0, 0, 0, 0, {0, {0}} },
2665 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2666 {
2667 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2669 },
2670 /* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
2671 {
2672 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2674 },
2675 /* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
2676 {
2677 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2679 },
2680 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2681 {
2682 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2684 },
2685 /* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
2686 {
2687 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2689 },
2690 /* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
2691 {
2692 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2694 },
2695 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2696 {
2697 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2699 },
2700 /* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
2701 {
2702 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2704 },
2705 /* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
2706 {
2707 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2709 },
2710 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
2711 {
2712 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2714 },
2715 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2716 {
2717 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2719 },
2720 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2721 {
2722 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2724 },
2725 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
2726 {
2727 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2729 },
2730 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2731 {
2732 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2734 },
2735 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2736 {
2737 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2739 },
2740 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
2741 {
2742 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2744 },
2745 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2746 {
2747 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2749 },
2750 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2751 {
2752 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2754 },
2755 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
2756 {
2757 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2759 },
2760 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
2761 {
2762 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2764 },
2765 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
2766 {
2767 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2769 },
2770 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
2771 {
2772 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2774 },
2775 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
2776 {
2777 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2779 },
2780 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
2781 {
2782 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2784 },
2785 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
2786 {
2787 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2789 },
2790 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
2791 {
2792 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2794 },
2795 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
2796 {
2797 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2799 },
2800 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
2801 {
2802 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2804 },
2805 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
2806 {
2807 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2809 },
2810 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
2811 {
2812 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2814 },
2815 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
2816 {
2817 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2819 },
2820 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
2821 {
2822 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2824 },
2825 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
2826 {
2827 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2829 },
2830 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
2831 {
2832 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2834 },
2835 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
2836 {
2837 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2839 },
2840 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
2841 {
2842 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2844 },
2845 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2846 {
2847 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2849 },
2850 /* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
2851 {
2852 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2854 },
2855 /* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
2856 {
2857 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2859 },
2860 /* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
2861 {
2862 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2864 },
2865 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2866 {
2867 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2869 },
2870 /* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
2871 {
2872 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2874 },
2875 /* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
2876 {
2877 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2879 },
2880 /* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
2881 {
2882 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2884 },
2885 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2886 {
2887 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2889 },
2890 /* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
2891 {
2892 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2894 },
2895 /* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
2896 {
2897 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2899 },
2900 /* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
2901 {
2902 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2904 },
2905 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
2906 {
2907 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2909 },
2910 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2911 {
2912 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2914 },
2915 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2916 {
2917 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2919 },
2920 /* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
2921 {
2922 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2924 },
2925 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
2926 {
2927 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2929 },
2930 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2931 {
2932 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2934 },
2935 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2936 {
2937 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2939 },
2940 /* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
2941 {
2942 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2944 },
2945 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
2946 {
2947 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2949 },
2950 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2951 {
2952 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2954 },
2955 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2956 {
2957 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2959 },
2960 /* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
2961 {
2962 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2964 },
2965 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
2966 {
2967 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2969 },
2970 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
2971 {
2972 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2974 },
2975 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
2976 {
2977 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2979 },
2980 /* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
2981 {
2982 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2984 },
2985 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
2986 {
2987 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2989 },
2990 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
2991 {
2992 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2994 },
2995 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
2996 {
2997 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2999 },
3000 /* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3001 {
3002 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3004 },
3005 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3006 {
3007 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3009 },
3010 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3011 {
3012 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3014 },
3015 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3016 {
3017 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3019 },
3020 /* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3021 {
3022 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3024 },
3025 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3026 {
3027 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3029 },
3030 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3031 {
3032 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3034 },
3035 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3036 {
3037 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3039 },
3040 /* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3041 {
3042 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3044 },
3045 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3046 {
3047 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3049 },
3050 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3051 {
3052 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3054 },
3055 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3056 {
3057 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3059 },
3060 /* extz ${Dsp-24-u16},${Dsp-40-u16} */
3061 {
3062 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3064 },
3065 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3066 {
3067 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3069 },
3070 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3071 {
3072 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3074 },
3075 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3076 {
3077 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3079 },
3080 /* extz ${Dsp-24-u16},${Dsp-40-u24} */
3081 {
3082 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3084 },
3085 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3086 {
3087 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3089 },
3090 /* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
3091 {
3092 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3094 },
3095 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3096 {
3097 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3099 },
3100 /* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
3101 {
3102 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3104 },
3105 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3106 {
3107 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3109 },
3110 /* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
3111 {
3112 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3114 },
3115 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3116 {
3117 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3119 },
3120 /* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3121 {
3122 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3124 },
3125 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3126 {
3127 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3129 },
3130 /* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3131 {
3132 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3134 },
3135 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3136 {
3137 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3139 },
3140 /* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3141 {
3142 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3144 },
3145 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3146 {
3147 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3149 },
3150 /* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3151 {
3152 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3154 },
3155 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3156 {
3157 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3159 },
3160 /* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3161 {
3162 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3164 },
3165 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3166 {
3167 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3169 },
3170 /* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3171 {
3172 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3174 },
3175 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3176 {
3177 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3179 },
3180 /* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3181 {
3182 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3184 },
3185 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3186 {
3187 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3189 },
3190 /* extz ${Dsp-24-u24},${Dsp-48-u16} */
3191 {
3192 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3194 },
3195 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3196 {
3197 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3199 },
3200 /* extz ${Dsp-24-u24},${Dsp-48-u24} */
3201 {
3202 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3204 },
3205 /* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3206 {
3207 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3209 },
3210 /* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3211 {
3212 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3214 },
3215 /* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3216 {
3217 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3219 },
3220 /* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3221 {
3222 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3224 },
3225 /* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3226 {
3227 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3229 },
3230 /* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3231 {
3232 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3234 },
3235 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3236 {
3237 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3239 },
3240 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3241 {
3242 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3244 },
3245 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3246 {
3247 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3249 },
3250 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3251 {
3252 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3254 },
3255 /* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3256 {
3257 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3259 },
3260 /* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3261 {
3262 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3264 },
3265 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3266 {
3267 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3269 },
3270 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3271 {
3272 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3274 },
3275 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3276 {
3277 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3279 },
3280 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3281 {
3282 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3284 },
3285 /* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3286 {
3287 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3289 },
3290 /* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3291 {
3292 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3294 },
3295 /* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3296 {
3297 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3299 },
3300 /* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3301 {
3302 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3304 },
3305 /* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
3306 {
3307 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3309 },
3310 /* extz [$Src32AnPrefixed],${Dsp-24-u16} */
3311 {
3312 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3314 },
3315 /* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
3316 {
3317 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3319 },
3320 /* extz [$Src32AnPrefixed],${Dsp-24-u24} */
3321 {
3322 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3324 },
3325 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3326 {
3327 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3329 },
3330 /* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
3331 {
3332 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3334 },
3335 /* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
3336 {
3337 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3339 },
3340 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3341 {
3342 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3344 },
3345 /* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
3346 {
3347 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3349 },
3350 /* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
3351 {
3352 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3354 },
3355 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3356 {
3357 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3359 },
3360 /* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
3361 {
3362 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3364 },
3365 /* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
3366 {
3367 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3369 },
3370 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
3371 {
3372 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3374 },
3375 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3376 {
3377 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3379 },
3380 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3381 {
3382 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3384 },
3385 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
3386 {
3387 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3389 },
3390 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3391 {
3392 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3394 },
3395 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3396 {
3397 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3399 },
3400 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
3401 {
3402 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3404 },
3405 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3406 {
3407 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3409 },
3410 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3411 {
3412 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3414 },
3415 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
3416 {
3417 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3419 },
3420 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
3421 {
3422 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3424 },
3425 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
3426 {
3427 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3429 },
3430 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
3431 {
3432 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3434 },
3435 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
3436 {
3437 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3439 },
3440 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
3441 {
3442 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3444 },
3445 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
3446 {
3447 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3449 },
3450 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
3451 {
3452 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3454 },
3455 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
3456 {
3457 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3459 },
3460 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
3461 {
3462 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3464 },
3465 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
3466 {
3467 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3469 },
3470 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
3471 {
3472 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3474 },
3475 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
3476 {
3477 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3479 },
3480 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
3481 {
3482 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3484 },
3485 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
3486 {
3487 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3489 },
3490 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
3491 {
3492 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3494 },
3495 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
3496 {
3497 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3499 },
3500 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
3501 {
3502 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3504 },
3505 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3506 {
3507 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3509 },
3510 /* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
3511 {
3512 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3514 },
3515 /* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
3516 {
3517 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3519 },
3520 /* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
3521 {
3522 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3524 },
3525 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3526 {
3527 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3529 },
3530 /* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
3531 {
3532 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3534 },
3535 /* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
3536 {
3537 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3539 },
3540 /* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
3541 {
3542 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3544 },
3545 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3546 {
3547 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3549 },
3550 /* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
3551 {
3552 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3554 },
3555 /* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
3556 {
3557 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3559 },
3560 /* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
3561 {
3562 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3564 },
3565 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
3566 {
3567 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3569 },
3570 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3571 {
3572 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3574 },
3575 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3576 {
3577 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3579 },
3580 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
3581 {
3582 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3584 },
3585 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
3586 {
3587 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3589 },
3590 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3591 {
3592 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3594 },
3595 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3596 {
3597 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3599 },
3600 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
3601 {
3602 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3604 },
3605 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
3606 {
3607 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3609 },
3610 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3611 {
3612 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3614 },
3615 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3616 {
3617 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3619 },
3620 /* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
3621 {
3622 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3624 },
3625 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
3626 {
3627 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3629 },
3630 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
3631 {
3632 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3634 },
3635 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
3636 {
3637 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3639 },
3640 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
3641 {
3642 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3644 },
3645 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
3646 {
3647 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3649 },
3650 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3651 {
3652 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3654 },
3655 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3656 {
3657 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3659 },
3660 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3661 {
3662 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3664 },
3665 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3666 {
3667 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3669 },
3670 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3671 {
3672 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3674 },
3675 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3676 {
3677 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3679 },
3680 /* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3681 {
3682 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3684 },
3685 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3686 {
3687 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3689 },
3690 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3691 {
3692 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3694 },
3695 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3696 {
3697 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3699 },
3700 /* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3701 {
3702 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3704 },
3705 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3706 {
3707 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3709 },
3710 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3711 {
3712 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3714 },
3715 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3716 {
3717 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3719 },
3720 /* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
3721 {
3722 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3724 },
3725 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3726 {
3727 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3729 },
3730 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3731 {
3732 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3734 },
3735 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3736 {
3737 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3739 },
3740 /* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
3741 {
3742 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3744 },
3745 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3746 {
3747 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3749 },
3750 /* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
3751 {
3752 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3754 },
3755 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3756 {
3757 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3759 },
3760 /* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
3761 {
3762 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3764 },
3765 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3766 {
3767 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3769 },
3770 /* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
3771 {
3772 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3774 },
3775 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3776 {
3777 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3779 },
3780 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3781 {
3782 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3784 },
3785 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3786 {
3787 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3789 },
3790 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3791 {
3792 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3794 },
3795 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3796 {
3797 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3799 },
3800 /* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3801 {
3802 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3804 },
3805 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3806 {
3807 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3809 },
3810 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3811 {
3812 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3814 },
3815 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3816 {
3817 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3819 },
3820 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3821 {
3822 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3824 },
3825 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3826 {
3827 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3829 },
3830 /* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3831 {
3832 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3834 },
3835 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3836 {
3837 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3839 },
3840 /* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3841 {
3842 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3844 },
3845 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3846 {
3847 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3849 },
3850 /* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
3851 {
3852 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3854 },
3855 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3856 {
3857 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3859 },
3860 /* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
3861 {
3862 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3864 },
3865 /* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3866 {
3867 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3869 },
3870 /* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3871 {
3872 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3874 },
3875 /* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3876 {
3877 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3879 },
3880 /* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3881 {
3882 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3884 },
3885 /* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3886 {
3887 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3889 },
3890 /* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3891 {
3892 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3894 },
3895 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3896 {
3897 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3899 },
3900 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3901 {
3902 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3904 },
3905 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3906 {
3907 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3909 },
3910 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3911 {
3912 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3914 },
3915 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3916 {
3917 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3919 },
3920 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3921 {
3922 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3924 },
3925 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3926 {
3927 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3929 },
3930 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3931 {
3932 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3934 },
3935 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3936 {
3937 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3939 },
3940 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3941 {
3942 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3944 },
3945 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3946 {
3947 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3949 },
3950 /* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3951 {
3952 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3954 },
3955 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3956 {
3957 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3959 },
3960 /* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3961 {
3962 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3964 },
3965 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
3966 {
3967 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3969 },
3970 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
3971 {
3972 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3974 },
3975 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
3976 {
3977 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
3978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3979 },
3980 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
3981 {
3982 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
3983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3984 },
3985 /* exts.w $Dst32RnExtUnprefixedHI */
3986 {
3987 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16,
3988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3989 },
3990 /* exts.w $Dst32AnUnprefixedSI */
3991 {
3992 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16,
3993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3994 },
3995 /* exts.w [$Dst32AnExtUnprefixed] */
3996 {
3997 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16,
3998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3999 },
4000 /* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4001 {
4002 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24,
4003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4004 },
4005 /* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4006 {
4007 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32,
4008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4009 },
4010 /* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4011 {
4012 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40,
4013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4014 },
4015 /* exts.w ${Dsp-16-u8}[sb] */
4016 {
4017 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24,
4018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4019 },
4020 /* exts.w ${Dsp-16-u16}[sb] */
4021 {
4022 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32,
4023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4024 },
4025 /* exts.w ${Dsp-16-s8}[fb] */
4026 {
4027 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24,
4028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4029 },
4030 /* exts.w ${Dsp-16-s16}[fb] */
4031 {
4032 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32,
4033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4034 },
4035 /* exts.w ${Dsp-16-u16} */
4036 {
4037 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32,
4038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4039 },
4040 /* exts.w ${Dsp-16-u24} */
4041 {
4042 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40,
4043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4044 },
4045 /* exts.b $Dst32RnExtUnprefixedQI */
4046 {
4047 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16,
4048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4049 },
4050 /* exts.b $Dst32AnUnprefixedHI */
4051 {
4052 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16,
4053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4054 },
4055 /* exts.b [$Dst32AnExtUnprefixed] */
4056 {
4057 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16,
4058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4059 },
4060 /* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4061 {
4062 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24,
4063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4064 },
4065 /* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4066 {
4067 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32,
4068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4069 },
4070 /* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4071 {
4072 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40,
4073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4074 },
4075 /* exts.b ${Dsp-16-u8}[sb] */
4076 {
4077 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24,
4078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4079 },
4080 /* exts.b ${Dsp-16-u16}[sb] */
4081 {
4082 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32,
4083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4084 },
4085 /* exts.b ${Dsp-16-s8}[fb] */
4086 {
4087 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24,
4088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4089 },
4090 /* exts.b ${Dsp-16-s16}[fb] */
4091 {
4092 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32,
4093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4094 },
4095 /* exts.b ${Dsp-16-u16} */
4096 {
4097 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32,
4098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4099 },
4100 /* exts.b ${Dsp-16-u24} */
4101 {
4102 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40,
4103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4104 },
4105 /* exts.b $Dst16RnExtQI */
4106 {
4107 M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16,
4108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4109 },
4110 /* exts.b [$Dst16An] */
4111 {
4112 M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16,
4113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4114 },
4115 /* exts.b ${Dsp-16-u8}[$Dst16An] */
4116 {
4117 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24,
4118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4119 },
4120 /* exts.b ${Dsp-16-u16}[$Dst16An] */
4121 {
4122 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32,
4123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4124 },
4125 /* exts.b ${Dsp-16-u8}[sb] */
4126 {
4127 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24,
4128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4129 },
4130 /* exts.b ${Dsp-16-u16}[sb] */
4131 {
4132 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32,
4133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4134 },
4135 /* exts.b ${Dsp-16-s8}[fb] */
4136 {
4137 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24,
4138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4139 },
4140 /* exts.b ${Dsp-16-u16} */
4141 {
4142 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32,
4143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4144 },
4145 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4146 {
4147 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4149 },
4150 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
4151 {
4152 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4154 },
4155 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
4156 {
4157 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4159 },
4160 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4161 {
4162 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4164 },
4165 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
4166 {
4167 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4169 },
4170 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
4171 {
4172 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4174 },
4175 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4176 {
4177 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4179 },
4180 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4181 {
4182 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4184 },
4185 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4186 {
4187 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4189 },
4190 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4191 {
4192 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4194 },
4195 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4196 {
4197 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4199 },
4200 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4201 {
4202 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4204 },
4205 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4206 {
4207 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4209 },
4210 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4211 {
4212 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4214 },
4215 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4216 {
4217 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4219 },
4220 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4221 {
4222 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4224 },
4225 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4226 {
4227 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4229 },
4230 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4231 {
4232 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4234 },
4235 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4236 {
4237 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4239 },
4240 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4241 {
4242 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4244 },
4245 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4246 {
4247 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4249 },
4250 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4251 {
4252 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4254 },
4255 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4256 {
4257 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4259 },
4260 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4261 {
4262 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4264 },
4265 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4266 {
4267 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4269 },
4270 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
4271 {
4272 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4274 },
4275 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
4276 {
4277 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4279 },
4280 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
4281 {
4282 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4284 },
4285 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
4286 {
4287 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4289 },
4290 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
4291 {
4292 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4294 },
4295 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
4296 {
4297 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4299 },
4300 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
4301 {
4302 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4304 },
4305 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
4306 {
4307 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4309 },
4310 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
4311 {
4312 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4314 },
4315 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
4316 {
4317 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4319 },
4320 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
4321 {
4322 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4324 },
4325 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4326 {
4327 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4329 },
4330 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
4331 {
4332 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4334 },
4335 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
4336 {
4337 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4339 },
4340 /* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
4341 {
4342 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4344 },
4345 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4346 {
4347 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4349 },
4350 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
4351 {
4352 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4354 },
4355 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
4356 {
4357 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4359 },
4360 /* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
4361 {
4362 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4364 },
4365 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4366 {
4367 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4369 },
4370 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
4371 {
4372 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4374 },
4375 /* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
4376 {
4377 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4379 },
4380 /* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
4381 {
4382 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4384 },
4385 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4386 {
4387 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4389 },
4390 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4391 {
4392 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4394 },
4395 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4396 {
4397 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4399 },
4400 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
4401 {
4402 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4404 },
4405 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4406 {
4407 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4409 },
4410 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4411 {
4412 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4414 },
4415 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4416 {
4417 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4419 },
4420 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
4421 {
4422 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4424 },
4425 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4426 {
4427 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4429 },
4430 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4431 {
4432 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4434 },
4435 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4436 {
4437 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4439 },
4440 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
4441 {
4442 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4444 },
4445 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
4446 {
4447 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4449 },
4450 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
4451 {
4452 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4454 },
4455 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
4456 {
4457 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4459 },
4460 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
4461 {
4462 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4464 },
4465 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
4466 {
4467 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4469 },
4470 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
4471 {
4472 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4474 },
4475 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
4476 {
4477 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4479 },
4480 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
4481 {
4482 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4484 },
4485 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
4486 {
4487 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4489 },
4490 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
4491 {
4492 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4494 },
4495 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
4496 {
4497 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4499 },
4500 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
4501 {
4502 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4504 },
4505 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
4506 {
4507 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4509 },
4510 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
4511 {
4512 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4514 },
4515 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
4516 {
4517 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4519 },
4520 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
4521 {
4522 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4524 },
4525 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
4526 {
4527 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4529 },
4530 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
4531 {
4532 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4534 },
4535 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
4536 {
4537 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4539 },
4540 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
4541 {
4542 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4544 },
4545 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
4546 {
4547 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4549 },
4550 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
4551 {
4552 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4554 },
4555 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
4556 {
4557 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4559 },
4560 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
4561 {
4562 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4564 },
4565 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4566 {
4567 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4569 },
4570 /* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
4571 {
4572 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4574 },
4575 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4576 {
4577 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4579 },
4580 /* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
4581 {
4582 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4584 },
4585 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4586 {
4587 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4589 },
4590 /* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
4591 {
4592 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4594 },
4595 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
4596 {
4597 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4599 },
4600 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
4601 {
4602 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4604 },
4605 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
4606 {
4607 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4609 },
4610 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
4611 {
4612 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4614 },
4615 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
4616 {
4617 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4619 },
4620 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
4621 {
4622 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4624 },
4625 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
4626 {
4627 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4629 },
4630 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
4631 {
4632 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4634 },
4635 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
4636 {
4637 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4639 },
4640 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
4641 {
4642 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4644 },
4645 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
4646 {
4647 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4649 },
4650 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
4651 {
4652 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4654 },
4655 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
4656 {
4657 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4659 },
4660 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
4661 {
4662 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4664 },
4665 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
4666 {
4667 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4669 },
4670 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
4671 {
4672 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4674 },
4675 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
4676 {
4677 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4679 },
4680 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
4681 {
4682 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4684 },
4685 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
4686 {
4687 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4689 },
4690 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
4691 {
4692 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4694 },
4695 /* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4696 {
4697 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4699 },
4700 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
4701 {
4702 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4704 },
4705 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
4706 {
4707 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4709 },
4710 /* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4711 {
4712 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4714 },
4715 /* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
4716 {
4717 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4719 },
4720 /* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
4721 {
4722 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4724 },
4725 /* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4726 {
4727 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4729 },
4730 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4731 {
4732 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4734 },
4735 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4736 {
4737 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4739 },
4740 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
4741 {
4742 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4744 },
4745 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4746 {
4747 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4749 },
4750 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4751 {
4752 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4754 },
4755 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
4756 {
4757 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4759 },
4760 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4761 {
4762 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4764 },
4765 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4766 {
4767 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4769 },
4770 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
4771 {
4772 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4774 },
4775 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
4776 {
4777 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4779 },
4780 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
4781 {
4782 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4784 },
4785 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
4786 {
4787 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4789 },
4790 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
4791 {
4792 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4794 },
4795 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
4796 {
4797 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4799 },
4800 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
4801 {
4802 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4804 },
4805 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
4806 {
4807 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4809 },
4810 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
4811 {
4812 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4814 },
4815 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
4816 {
4817 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4819 },
4820 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
4821 {
4822 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4824 },
4825 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
4826 {
4827 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4829 },
4830 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
4831 {
4832 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4834 },
4835 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
4836 {
4837 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4839 },
4840 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
4841 {
4842 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4844 },
4845 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
4846 {
4847 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4849 },
4850 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
4851 {
4852 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4854 },
4855 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
4856 {
4857 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4859 },
4860 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
4861 {
4862 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4864 },
4865 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
4866 {
4867 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4869 },
4870 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
4871 {
4872 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4874 },
4875 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
4876 {
4877 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4879 },
4880 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
4881 {
4882 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4884 },
4885 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
4886 {
4887 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4889 },
4890 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
4891 {
4892 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4894 },
4895 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4896 {
4897 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4899 },
4900 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4901 {
4902 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4904 },
4905 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4906 {
4907 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4909 },
4910 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4911 {
4912 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4914 },
4915 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4916 {
4917 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4919 },
4920 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4921 {
4922 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4924 },
4925 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4926 {
4927 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4929 },
4930 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4931 {
4932 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4934 },
4935 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4936 {
4937 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4939 },
4940 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4941 {
4942 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4944 },
4945 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4946 {
4947 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4949 },
4950 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4951 {
4952 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4954 },
4955 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4956 {
4957 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4959 },
4960 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4961 {
4962 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4964 },
4965 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4966 {
4967 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4969 },
4970 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4971 {
4972 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4974 },
4975 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4976 {
4977 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4979 },
4980 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4981 {
4982 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4984 },
4985 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4986 {
4987 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
4988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4989 },
4990 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
4991 {
4992 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
4993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4994 },
4995 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
4996 {
4997 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
4998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4999 },
5000 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
5001 {
5002 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5004 },
5005 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
5006 {
5007 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5009 },
5010 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
5011 {
5012 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5014 },
5015 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
5016 {
5017 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5019 },
5020 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5021 {
5022 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5024 },
5025 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5026 {
5027 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5029 },
5030 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
5031 {
5032 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5034 },
5035 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
5036 {
5037 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5039 },
5040 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
5041 {
5042 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5044 },
5045 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5046 {
5047 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5049 },
5050 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
5051 {
5052 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5054 },
5055 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
5056 {
5057 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5059 },
5060 /* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
5061 {
5062 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5064 },
5065 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5066 {
5067 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5069 },
5070 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
5071 {
5072 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5074 },
5075 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
5076 {
5077 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5079 },
5080 /* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
5081 {
5082 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5084 },
5085 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5086 {
5087 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5089 },
5090 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
5091 {
5092 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5094 },
5095 /* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
5096 {
5097 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5099 },
5100 /* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
5101 {
5102 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5104 },
5105 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5106 {
5107 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5109 },
5110 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5111 {
5112 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5114 },
5115 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5116 {
5117 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5119 },
5120 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
5121 {
5122 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5124 },
5125 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5126 {
5127 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5129 },
5130 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5131 {
5132 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5134 },
5135 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5136 {
5137 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5139 },
5140 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
5141 {
5142 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5144 },
5145 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5146 {
5147 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5149 },
5150 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5151 {
5152 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5154 },
5155 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5156 {
5157 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5159 },
5160 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
5161 {
5162 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5164 },
5165 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
5166 {
5167 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5169 },
5170 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5171 {
5172 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5174 },
5175 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
5176 {
5177 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5179 },
5180 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5181 {
5182 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5184 },
5185 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
5186 {
5187 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5189 },
5190 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5191 {
5192 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5194 },
5195 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
5196 {
5197 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5199 },
5200 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5201 {
5202 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5204 },
5205 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
5206 {
5207 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5209 },
5210 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5211 {
5212 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5214 },
5215 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
5216 {
5217 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5219 },
5220 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5221 {
5222 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5224 },
5225 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
5226 {
5227 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5229 },
5230 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
5231 {
5232 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5234 },
5235 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
5236 {
5237 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5239 },
5240 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
5241 {
5242 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5244 },
5245 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
5246 {
5247 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5249 },
5250 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5251 {
5252 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5254 },
5255 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
5256 {
5257 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5259 },
5260 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
5261 {
5262 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5264 },
5265 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
5266 {
5267 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5269 },
5270 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
5271 {
5272 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5274 },
5275 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
5276 {
5277 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5279 },
5280 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
5281 {
5282 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5284 },
5285 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5286 {
5287 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5289 },
5290 /* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
5291 {
5292 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5294 },
5295 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5296 {
5297 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5299 },
5300 /* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
5301 {
5302 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5304 },
5305 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5306 {
5307 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5309 },
5310 /* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
5311 {
5312 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5314 },
5315 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
5316 {
5317 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5319 },
5320 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
5321 {
5322 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5324 },
5325 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
5326 {
5327 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5329 },
5330 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
5331 {
5332 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5334 },
5335 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
5336 {
5337 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5339 },
5340 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
5341 {
5342 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5344 },
5345 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
5346 {
5347 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5349 },
5350 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
5351 {
5352 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5354 },
5355 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
5356 {
5357 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5359 },
5360 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
5361 {
5362 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5364 },
5365 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
5366 {
5367 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5369 },
5370 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
5371 {
5372 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5374 },
5375 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
5376 {
5377 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5379 },
5380 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
5381 {
5382 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5384 },
5385 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
5386 {
5387 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5389 },
5390 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
5391 {
5392 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5394 },
5395 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
5396 {
5397 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5399 },
5400 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
5401 {
5402 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5404 },
5405 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
5406 {
5407 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5409 },
5410 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
5411 {
5412 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5414 },
5415 /* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5416 {
5417 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5419 },
5420 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
5421 {
5422 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5424 },
5425 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
5426 {
5427 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5429 },
5430 /* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5431 {
5432 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5434 },
5435 /* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
5436 {
5437 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5439 },
5440 /* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
5441 {
5442 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5444 },
5445 /* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5446 {
5447 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5449 },
5450 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5451 {
5452 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5454 },
5455 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5456 {
5457 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5459 },
5460 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
5461 {
5462 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5464 },
5465 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5466 {
5467 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5469 },
5470 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5471 {
5472 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5474 },
5475 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
5476 {
5477 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5479 },
5480 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5481 {
5482 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5484 },
5485 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5486 {
5487 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5489 },
5490 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
5491 {
5492 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5494 },
5495 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
5496 {
5497 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5499 },
5500 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
5501 {
5502 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5504 },
5505 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
5506 {
5507 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5509 },
5510 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
5511 {
5512 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5514 },
5515 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
5516 {
5517 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5519 },
5520 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
5521 {
5522 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5524 },
5525 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
5526 {
5527 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5529 },
5530 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
5531 {
5532 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5534 },
5535 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
5536 {
5537 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5539 },
5540 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
5541 {
5542 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5544 },
5545 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
5546 {
5547 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5549 },
5550 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
5551 {
5552 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5554 },
5555 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
5556 {
5557 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5559 },
5560 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
5561 {
5562 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5564 },
5565 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
5566 {
5567 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5569 },
5570 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
5571 {
5572 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5574 },
5575 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
5576 {
5577 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5579 },
5580 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
5581 {
5582 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5584 },
5585 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
5586 {
5587 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5589 },
5590 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
5591 {
5592 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5594 },
5595 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
5596 {
5597 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5599 },
5600 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
5601 {
5602 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5604 },
5605 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
5606 {
5607 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5609 },
5610 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
5611 {
5612 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5614 },
5615 /* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
5616 {
5617 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5619 },
5620 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
5621 {
5622 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5624 },
5625 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
5626 {
5627 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5629 },
5630 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
5631 {
5632 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5634 },
5635 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
5636 {
5637 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5639 },
5640 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
5641 {
5642 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5644 },
5645 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
5646 {
5647 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5649 },
5650 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
5651 {
5652 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5654 },
5655 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
5656 {
5657 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5659 },
5660 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
5661 {
5662 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5664 },
5665 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
5666 {
5667 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5669 },
5670 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
5671 {
5672 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5674 },
5675 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
5676 {
5677 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5679 },
5680 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
5681 {
5682 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5684 },
5685 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
5686 {
5687 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5689 },
5690 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
5691 {
5692 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5694 },
5695 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5696 {
5697 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5699 },
5700 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5701 {
5702 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5704 },
5705 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
5706 {
5707 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5709 },
5710 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5711 {
5712 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5714 },
5715 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5716 {
5717 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5719 },
5720 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
5721 {
5722 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5724 },
5725 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
5726 {
5727 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5729 },
5730 /* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
5731 {
5732 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32,
5733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5734 },
5735 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
5736 {
5737 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5739 },
5740 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
5741 {
5742 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5744 },
5745 /* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
5746 {
5747 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32,
5748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5749 },
5750 /* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
5751 {
5752 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5754 },
5755 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
5756 {
5757 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5759 },
5760 /* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
5761 {
5762 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32,
5763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5764 },
5765 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
5766 {
5767 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5769 },
5770 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
5771 {
5772 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5774 },
5775 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
5776 {
5777 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5779 },
5780 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
5781 {
5782 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5784 },
5785 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
5786 {
5787 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5789 },
5790 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
5791 {
5792 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5794 },
5795 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
5796 {
5797 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5799 },
5800 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5801 {
5802 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5804 },
5805 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5806 {
5807 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5809 },
5810 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
5811 {
5812 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5814 },
5815 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5816 {
5817 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5819 },
5820 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5821 {
5822 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5824 },
5825 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
5826 {
5827 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5829 },
5830 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5831 {
5832 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5834 },
5835 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5836 {
5837 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5839 },
5840 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
5841 {
5842 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5844 },
5845 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5846 {
5847 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5849 },
5850 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
5851 {
5852 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5854 },
5855 /* xor.w${G} $Src16RnHI,$Dst16RnHI */
5856 {
5857 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5859 },
5860 /* xor.w${G} $Src16AnHI,$Dst16RnHI */
5861 {
5862 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5864 },
5865 /* xor.w${G} [$Src16An],$Dst16RnHI */
5866 {
5867 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16,
5868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5869 },
5870 /* xor.w${G} $Src16RnHI,$Dst16AnHI */
5871 {
5872 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5874 },
5875 /* xor.w${G} $Src16AnHI,$Dst16AnHI */
5876 {
5877 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5879 },
5880 /* xor.w${G} [$Src16An],$Dst16AnHI */
5881 {
5882 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16,
5883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5884 },
5885 /* xor.w${G} $Src16RnHI,[$Dst16An] */
5886 {
5887 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5889 },
5890 /* xor.w${G} $Src16AnHI,[$Dst16An] */
5891 {
5892 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5894 },
5895 /* xor.w${G} [$Src16An],[$Dst16An] */
5896 {
5897 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16,
5898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5899 },
5900 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
5901 {
5902 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5904 },
5905 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
5906 {
5907 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5909 },
5910 /* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
5911 {
5912 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5914 },
5915 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
5916 {
5917 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5919 },
5920 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
5921 {
5922 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5924 },
5925 /* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
5926 {
5927 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5929 },
5930 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
5931 {
5932 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5934 },
5935 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
5936 {
5937 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5939 },
5940 /* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
5941 {
5942 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5944 },
5945 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
5946 {
5947 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5949 },
5950 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
5951 {
5952 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5954 },
5955 /* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
5956 {
5957 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5959 },
5960 /* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
5961 {
5962 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5964 },
5965 /* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
5966 {
5967 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5969 },
5970 /* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
5971 {
5972 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5974 },
5975 /* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
5976 {
5977 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5979 },
5980 /* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
5981 {
5982 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5984 },
5985 /* xor.w${G} [$Src16An],${Dsp-16-u16} */
5986 {
5987 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5989 },
5990 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
5991 {
5992 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
5993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5994 },
5995 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
5996 {
5997 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
5998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5999 },
6000 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
6001 {
6002 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6004 },
6005 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
6006 {
6007 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6009 },
6010 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
6011 {
6012 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6014 },
6015 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
6016 {
6017 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6019 },
6020 /* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
6021 {
6022 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6024 },
6025 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
6026 {
6027 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6029 },
6030 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
6031 {
6032 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6034 },
6035 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
6036 {
6037 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6039 },
6040 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
6041 {
6042 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6044 },
6045 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
6046 {
6047 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6049 },
6050 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
6051 {
6052 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6054 },
6055 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
6056 {
6057 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6059 },
6060 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
6061 {
6062 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6064 },
6065 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
6066 {
6067 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6069 },
6070 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
6071 {
6072 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6074 },
6075 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
6076 {
6077 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6079 },
6080 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
6081 {
6082 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6084 },
6085 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
6086 {
6087 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6089 },
6090 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
6091 {
6092 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6094 },
6095 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
6096 {
6097 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6099 },
6100 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
6101 {
6102 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6104 },
6105 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
6106 {
6107 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6109 },
6110 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
6111 {
6112 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6114 },
6115 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
6116 {
6117 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6119 },
6120 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
6121 {
6122 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6124 },
6125 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
6126 {
6127 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6129 },
6130 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
6131 {
6132 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6134 },
6135 /* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
6136 {
6137 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32,
6138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6139 },
6140 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
6141 {
6142 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6144 },
6145 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
6146 {
6147 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6149 },
6150 /* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
6151 {
6152 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32,
6153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6154 },
6155 /* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
6156 {
6157 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6159 },
6160 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
6161 {
6162 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6164 },
6165 /* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
6166 {
6167 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32,
6168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6169 },
6170 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
6171 {
6172 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6174 },
6175 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
6176 {
6177 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6179 },
6180 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
6181 {
6182 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6184 },
6185 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
6186 {
6187 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6189 },
6190 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
6191 {
6192 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6194 },
6195 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
6196 {
6197 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6199 },
6200 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
6201 {
6202 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6204 },
6205 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
6206 {
6207 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6209 },
6210 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
6211 {
6212 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6214 },
6215 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
6216 {
6217 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6219 },
6220 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
6221 {
6222 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6224 },
6225 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
6226 {
6227 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6229 },
6230 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
6231 {
6232 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6234 },
6235 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
6236 {
6237 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6239 },
6240 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
6241 {
6242 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6244 },
6245 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
6246 {
6247 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6249 },
6250 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
6251 {
6252 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6254 },
6255 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
6256 {
6257 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6259 },
6260 /* xor.b${G} $Src16RnQI,$Dst16RnQI */
6261 {
6262 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6264 },
6265 /* xor.b${G} $Src16AnQI,$Dst16RnQI */
6266 {
6267 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6269 },
6270 /* xor.b${G} [$Src16An],$Dst16RnQI */
6271 {
6272 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16,
6273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6274 },
6275 /* xor.b${G} $Src16RnQI,$Dst16AnQI */
6276 {
6277 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6279 },
6280 /* xor.b${G} $Src16AnQI,$Dst16AnQI */
6281 {
6282 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6284 },
6285 /* xor.b${G} [$Src16An],$Dst16AnQI */
6286 {
6287 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16,
6288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6289 },
6290 /* xor.b${G} $Src16RnQI,[$Dst16An] */
6291 {
6292 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6294 },
6295 /* xor.b${G} $Src16AnQI,[$Dst16An] */
6296 {
6297 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6299 },
6300 /* xor.b${G} [$Src16An],[$Dst16An] */
6301 {
6302 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16,
6303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6304 },
6305 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
6306 {
6307 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6309 },
6310 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
6311 {
6312 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6314 },
6315 /* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
6316 {
6317 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6319 },
6320 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
6321 {
6322 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6324 },
6325 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
6326 {
6327 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6329 },
6330 /* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
6331 {
6332 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6334 },
6335 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
6336 {
6337 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6339 },
6340 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
6341 {
6342 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6344 },
6345 /* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
6346 {
6347 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6349 },
6350 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
6351 {
6352 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6354 },
6355 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
6356 {
6357 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6359 },
6360 /* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
6361 {
6362 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6364 },
6365 /* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
6366 {
6367 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6369 },
6370 /* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
6371 {
6372 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6374 },
6375 /* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
6376 {
6377 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6379 },
6380 /* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
6381 {
6382 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6384 },
6385 /* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
6386 {
6387 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6389 },
6390 /* xor.b${G} [$Src16An],${Dsp-16-u16} */
6391 {
6392 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6394 },
6395 /* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
6396 {
6397 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6399 },
6400 /* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
6401 {
6402 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6404 },
6405 /* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
6406 {
6407 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6409 },
6410 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6411 {
6412 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40,
6413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6414 },
6415 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6416 {
6417 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6419 },
6420 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6421 {
6422 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6424 },
6425 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6426 {
6427 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48,
6428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6429 },
6430 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6431 {
6432 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6434 },
6435 /* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
6436 {
6437 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6439 },
6440 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6441 {
6442 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48,
6443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6444 },
6445 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6446 {
6447 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56,
6448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6449 },
6450 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
6451 {
6452 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56,
6453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6454 },
6455 /* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
6456 {
6457 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6459 },
6460 /* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
6461 {
6462 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6464 },
6465 /* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
6466 {
6467 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6469 },
6470 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6471 {
6472 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32,
6473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6474 },
6475 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6476 {
6477 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6479 },
6480 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6481 {
6482 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6484 },
6485 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6486 {
6487 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40,
6488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6489 },
6490 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6491 {
6492 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6494 },
6495 /* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
6496 {
6497 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6499 },
6500 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6501 {
6502 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40,
6503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6504 },
6505 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6506 {
6507 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48,
6508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6509 },
6510 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
6511 {
6512 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48,
6513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6514 },
6515 /* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
6516 {
6517 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32,
6518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6519 },
6520 /* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
6521 {
6522 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32,
6523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6524 },
6525 /* xor.w${G} #${Imm-16-HI},[$Dst16An] */
6526 {
6527 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32,
6528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6529 },
6530 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
6531 {
6532 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40,
6533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6534 },
6535 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6536 {
6537 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40,
6538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6539 },
6540 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6541 {
6542 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40,
6543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6544 },
6545 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
6546 {
6547 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48,
6548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6549 },
6550 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6551 {
6552 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48,
6553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6554 },
6555 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6556 {
6557 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48,
6558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6559 },
6560 /* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
6561 {
6562 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24,
6563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6564 },
6565 /* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
6566 {
6567 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24,
6568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6569 },
6570 /* xor.b${G} #${Imm-16-QI},[$Dst16An] */
6571 {
6572 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24,
6573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6574 },
6575 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
6576 {
6577 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32,
6578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6579 },
6580 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6581 {
6582 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32,
6583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6584 },
6585 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6586 {
6587 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32,
6588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6589 },
6590 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
6591 {
6592 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40,
6593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6594 },
6595 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6596 {
6597 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40,
6598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6599 },
6600 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6601 {
6602 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40,
6603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6604 },
6605 /* xchg.w r3,$Dst32RnUnprefixedHI */
6606 {
6607 M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6609 },
6610 /* xchg.w r3,$Dst32AnUnprefixedHI */
6611 {
6612 M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6614 },
6615 /* xchg.w r3,[$Dst32AnUnprefixed] */
6616 {
6617 M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6619 },
6620 /* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6621 {
6622 M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6624 },
6625 /* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6626 {
6627 M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6629 },
6630 /* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6631 {
6632 M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6634 },
6635 /* xchg.w r3,${Dsp-16-u8}[sb] */
6636 {
6637 M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6639 },
6640 /* xchg.w r3,${Dsp-16-u16}[sb] */
6641 {
6642 M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6644 },
6645 /* xchg.w r3,${Dsp-16-s8}[fb] */
6646 {
6647 M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6649 },
6650 /* xchg.w r3,${Dsp-16-s16}[fb] */
6651 {
6652 M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6654 },
6655 /* xchg.w r3,${Dsp-16-u16} */
6656 {
6657 M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6659 },
6660 /* xchg.w r3,${Dsp-16-u24} */
6661 {
6662 M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6664 },
6665 /* xchg.w r2,$Dst32RnUnprefixedHI */
6666 {
6667 M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6669 },
6670 /* xchg.w r2,$Dst32AnUnprefixedHI */
6671 {
6672 M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6674 },
6675 /* xchg.w r2,[$Dst32AnUnprefixed] */
6676 {
6677 M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6679 },
6680 /* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6681 {
6682 M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6684 },
6685 /* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6686 {
6687 M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6689 },
6690 /* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6691 {
6692 M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6694 },
6695 /* xchg.w r2,${Dsp-16-u8}[sb] */
6696 {
6697 M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6699 },
6700 /* xchg.w r2,${Dsp-16-u16}[sb] */
6701 {
6702 M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6704 },
6705 /* xchg.w r2,${Dsp-16-s8}[fb] */
6706 {
6707 M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6709 },
6710 /* xchg.w r2,${Dsp-16-s16}[fb] */
6711 {
6712 M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6714 },
6715 /* xchg.w r2,${Dsp-16-u16} */
6716 {
6717 M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6719 },
6720 /* xchg.w r2,${Dsp-16-u24} */
6721 {
6722 M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6724 },
6725 /* xchg.w a1,$Dst32RnUnprefixedHI */
6726 {
6727 M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6729 },
6730 /* xchg.w a1,$Dst32AnUnprefixedHI */
6731 {
6732 M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6734 },
6735 /* xchg.w a1,[$Dst32AnUnprefixed] */
6736 {
6737 M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6739 },
6740 /* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6741 {
6742 M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6744 },
6745 /* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6746 {
6747 M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6749 },
6750 /* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6751 {
6752 M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6754 },
6755 /* xchg.w a1,${Dsp-16-u8}[sb] */
6756 {
6757 M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6759 },
6760 /* xchg.w a1,${Dsp-16-u16}[sb] */
6761 {
6762 M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6764 },
6765 /* xchg.w a1,${Dsp-16-s8}[fb] */
6766 {
6767 M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6769 },
6770 /* xchg.w a1,${Dsp-16-s16}[fb] */
6771 {
6772 M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6774 },
6775 /* xchg.w a1,${Dsp-16-u16} */
6776 {
6777 M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6779 },
6780 /* xchg.w a1,${Dsp-16-u24} */
6781 {
6782 M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6784 },
6785 /* xchg.w a0,$Dst32RnUnprefixedHI */
6786 {
6787 M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6789 },
6790 /* xchg.w a0,$Dst32AnUnprefixedHI */
6791 {
6792 M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6794 },
6795 /* xchg.w a0,[$Dst32AnUnprefixed] */
6796 {
6797 M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6799 },
6800 /* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6801 {
6802 M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6804 },
6805 /* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6806 {
6807 M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6809 },
6810 /* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6811 {
6812 M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6814 },
6815 /* xchg.w a0,${Dsp-16-u8}[sb] */
6816 {
6817 M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6819 },
6820 /* xchg.w a0,${Dsp-16-u16}[sb] */
6821 {
6822 M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6824 },
6825 /* xchg.w a0,${Dsp-16-s8}[fb] */
6826 {
6827 M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6829 },
6830 /* xchg.w a0,${Dsp-16-s16}[fb] */
6831 {
6832 M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6834 },
6835 /* xchg.w a0,${Dsp-16-u16} */
6836 {
6837 M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6839 },
6840 /* xchg.w a0,${Dsp-16-u24} */
6841 {
6842 M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6844 },
6845 /* xchg.w r1,$Dst32RnUnprefixedHI */
6846 {
6847 M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6849 },
6850 /* xchg.w r1,$Dst32AnUnprefixedHI */
6851 {
6852 M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6854 },
6855 /* xchg.w r1,[$Dst32AnUnprefixed] */
6856 {
6857 M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6859 },
6860 /* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6861 {
6862 M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6864 },
6865 /* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6866 {
6867 M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6869 },
6870 /* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6871 {
6872 M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6874 },
6875 /* xchg.w r1,${Dsp-16-u8}[sb] */
6876 {
6877 M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6879 },
6880 /* xchg.w r1,${Dsp-16-u16}[sb] */
6881 {
6882 M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6884 },
6885 /* xchg.w r1,${Dsp-16-s8}[fb] */
6886 {
6887 M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6889 },
6890 /* xchg.w r1,${Dsp-16-s16}[fb] */
6891 {
6892 M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6894 },
6895 /* xchg.w r1,${Dsp-16-u16} */
6896 {
6897 M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6899 },
6900 /* xchg.w r1,${Dsp-16-u24} */
6901 {
6902 M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6904 },
6905 /* xchg.w r0,$Dst32RnUnprefixedHI */
6906 {
6907 M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6909 },
6910 /* xchg.w r0,$Dst32AnUnprefixedHI */
6911 {
6912 M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6914 },
6915 /* xchg.w r0,[$Dst32AnUnprefixed] */
6916 {
6917 M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6919 },
6920 /* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6921 {
6922 M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6924 },
6925 /* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6926 {
6927 M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6929 },
6930 /* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6931 {
6932 M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6934 },
6935 /* xchg.w r0,${Dsp-16-u8}[sb] */
6936 {
6937 M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6939 },
6940 /* xchg.w r0,${Dsp-16-u16}[sb] */
6941 {
6942 M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6944 },
6945 /* xchg.w r0,${Dsp-16-s8}[fb] */
6946 {
6947 M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6949 },
6950 /* xchg.w r0,${Dsp-16-s16}[fb] */
6951 {
6952 M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6954 },
6955 /* xchg.w r0,${Dsp-16-u16} */
6956 {
6957 M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6959 },
6960 /* xchg.w r0,${Dsp-16-u24} */
6961 {
6962 M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6964 },
6965 /* xchg.b r1h,$Dst32RnUnprefixedQI */
6966 {
6967 M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6969 },
6970 /* xchg.b r1h,$Dst32AnUnprefixedQI */
6971 {
6972 M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6974 },
6975 /* xchg.b r1h,[$Dst32AnUnprefixed] */
6976 {
6977 M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6979 },
6980 /* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6981 {
6982 M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6984 },
6985 /* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6986 {
6987 M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6989 },
6990 /* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6991 {
6992 M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6994 },
6995 /* xchg.b r1h,${Dsp-16-u8}[sb] */
6996 {
6997 M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6999 },
7000 /* xchg.b r1h,${Dsp-16-u16}[sb] */
7001 {
7002 M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7004 },
7005 /* xchg.b r1h,${Dsp-16-s8}[fb] */
7006 {
7007 M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7009 },
7010 /* xchg.b r1h,${Dsp-16-s16}[fb] */
7011 {
7012 M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7014 },
7015 /* xchg.b r1h,${Dsp-16-u16} */
7016 {
7017 M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7019 },
7020 /* xchg.b r1h,${Dsp-16-u24} */
7021 {
7022 M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7024 },
7025 /* xchg.b r0h,$Dst32RnUnprefixedQI */
7026 {
7027 M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7029 },
7030 /* xchg.b r0h,$Dst32AnUnprefixedQI */
7031 {
7032 M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7034 },
7035 /* xchg.b r0h,[$Dst32AnUnprefixed] */
7036 {
7037 M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7039 },
7040 /* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7041 {
7042 M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7044 },
7045 /* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7046 {
7047 M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7049 },
7050 /* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7051 {
7052 M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7054 },
7055 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7056 {
7057 M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7059 },
7060 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7061 {
7062 M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7064 },
7065 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7066 {
7067 M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7069 },
7070 /* xchg.b r0h,${Dsp-16-s16}[fb] */
7071 {
7072 M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7074 },
7075 /* xchg.b r0h,${Dsp-16-u16} */
7076 {
7077 M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7079 },
7080 /* xchg.b r0h,${Dsp-16-u24} */
7081 {
7082 M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7084 },
7085 /* xchg.b a1,$Dst32RnUnprefixedQI */
7086 {
7087 M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7089 },
7090 /* xchg.b a1,$Dst32AnUnprefixedQI */
7091 {
7092 M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7094 },
7095 /* xchg.b a1,[$Dst32AnUnprefixed] */
7096 {
7097 M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7099 },
7100 /* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7101 {
7102 M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7104 },
7105 /* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7106 {
7107 M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7109 },
7110 /* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7111 {
7112 M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7114 },
7115 /* xchg.b a1,${Dsp-16-u8}[sb] */
7116 {
7117 M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7119 },
7120 /* xchg.b a1,${Dsp-16-u16}[sb] */
7121 {
7122 M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7124 },
7125 /* xchg.b a1,${Dsp-16-s8}[fb] */
7126 {
7127 M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7129 },
7130 /* xchg.b a1,${Dsp-16-s16}[fb] */
7131 {
7132 M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7134 },
7135 /* xchg.b a1,${Dsp-16-u16} */
7136 {
7137 M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7139 },
7140 /* xchg.b a1,${Dsp-16-u24} */
7141 {
7142 M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7144 },
7145 /* xchg.b a0,$Dst32RnUnprefixedQI */
7146 {
7147 M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7149 },
7150 /* xchg.b a0,$Dst32AnUnprefixedQI */
7151 {
7152 M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7154 },
7155 /* xchg.b a0,[$Dst32AnUnprefixed] */
7156 {
7157 M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7159 },
7160 /* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7161 {
7162 M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7164 },
7165 /* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7166 {
7167 M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7169 },
7170 /* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7171 {
7172 M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7174 },
7175 /* xchg.b a0,${Dsp-16-u8}[sb] */
7176 {
7177 M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7179 },
7180 /* xchg.b a0,${Dsp-16-u16}[sb] */
7181 {
7182 M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7184 },
7185 /* xchg.b a0,${Dsp-16-s8}[fb] */
7186 {
7187 M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7189 },
7190 /* xchg.b a0,${Dsp-16-s16}[fb] */
7191 {
7192 M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7194 },
7195 /* xchg.b a0,${Dsp-16-u16} */
7196 {
7197 M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7199 },
7200 /* xchg.b a0,${Dsp-16-u24} */
7201 {
7202 M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7204 },
7205 /* xchg.b r1l,$Dst32RnUnprefixedQI */
7206 {
7207 M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7209 },
7210 /* xchg.b r1l,$Dst32AnUnprefixedQI */
7211 {
7212 M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7214 },
7215 /* xchg.b r1l,[$Dst32AnUnprefixed] */
7216 {
7217 M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7219 },
7220 /* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7221 {
7222 M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7224 },
7225 /* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7226 {
7227 M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7229 },
7230 /* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7231 {
7232 M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7234 },
7235 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7236 {
7237 M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7239 },
7240 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7241 {
7242 M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7244 },
7245 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7246 {
7247 M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7249 },
7250 /* xchg.b r1l,${Dsp-16-s16}[fb] */
7251 {
7252 M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7254 },
7255 /* xchg.b r1l,${Dsp-16-u16} */
7256 {
7257 M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7259 },
7260 /* xchg.b r1l,${Dsp-16-u24} */
7261 {
7262 M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7264 },
7265 /* xchg.b r0l,$Dst32RnUnprefixedQI */
7266 {
7267 M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7269 },
7270 /* xchg.b r0l,$Dst32AnUnprefixedQI */
7271 {
7272 M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7274 },
7275 /* xchg.b r0l,[$Dst32AnUnprefixed] */
7276 {
7277 M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7279 },
7280 /* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7281 {
7282 M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7284 },
7285 /* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7286 {
7287 M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7289 },
7290 /* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7291 {
7292 M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7294 },
7295 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7296 {
7297 M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7299 },
7300 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7301 {
7302 M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7304 },
7305 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7306 {
7307 M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7309 },
7310 /* xchg.b r0l,${Dsp-16-s16}[fb] */
7311 {
7312 M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7314 },
7315 /* xchg.b r0l,${Dsp-16-u16} */
7316 {
7317 M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7319 },
7320 /* xchg.b r0l,${Dsp-16-u24} */
7321 {
7322 M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7324 },
7325 /* xchg.w r3,$Dst16RnHI */
7326 {
7327 M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16,
7328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7329 },
7330 /* xchg.w r3,$Dst16AnHI */
7331 {
7332 M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16,
7333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7334 },
7335 /* xchg.w r3,[$Dst16An] */
7336 {
7337 M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16,
7338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7339 },
7340 /* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
7341 {
7342 M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24,
7343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7344 },
7345 /* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
7346 {
7347 M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32,
7348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7349 },
7350 /* xchg.w r3,${Dsp-16-u8}[sb] */
7351 {
7352 M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7354 },
7355 /* xchg.w r3,${Dsp-16-u16}[sb] */
7356 {
7357 M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7359 },
7360 /* xchg.w r3,${Dsp-16-s8}[fb] */
7361 {
7362 M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7364 },
7365 /* xchg.w r3,${Dsp-16-u16} */
7366 {
7367 M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32,
7368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7369 },
7370 /* xchg.w r2,$Dst16RnHI */
7371 {
7372 M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16,
7373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7374 },
7375 /* xchg.w r2,$Dst16AnHI */
7376 {
7377 M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16,
7378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7379 },
7380 /* xchg.w r2,[$Dst16An] */
7381 {
7382 M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16,
7383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7384 },
7385 /* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
7386 {
7387 M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24,
7388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7389 },
7390 /* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
7391 {
7392 M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32,
7393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7394 },
7395 /* xchg.w r2,${Dsp-16-u8}[sb] */
7396 {
7397 M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7399 },
7400 /* xchg.w r2,${Dsp-16-u16}[sb] */
7401 {
7402 M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7404 },
7405 /* xchg.w r2,${Dsp-16-s8}[fb] */
7406 {
7407 M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7409 },
7410 /* xchg.w r2,${Dsp-16-u16} */
7411 {
7412 M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32,
7413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7414 },
7415 /* xchg.w r1,$Dst16RnHI */
7416 {
7417 M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16,
7418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7419 },
7420 /* xchg.w r1,$Dst16AnHI */
7421 {
7422 M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16,
7423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7424 },
7425 /* xchg.w r1,[$Dst16An] */
7426 {
7427 M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16,
7428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7429 },
7430 /* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
7431 {
7432 M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24,
7433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7434 },
7435 /* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
7436 {
7437 M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32,
7438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7439 },
7440 /* xchg.w r1,${Dsp-16-u8}[sb] */
7441 {
7442 M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7444 },
7445 /* xchg.w r1,${Dsp-16-u16}[sb] */
7446 {
7447 M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7449 },
7450 /* xchg.w r1,${Dsp-16-s8}[fb] */
7451 {
7452 M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7454 },
7455 /* xchg.w r1,${Dsp-16-u16} */
7456 {
7457 M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
7458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7459 },
7460 /* xchg.w r0,$Dst16RnHI */
7461 {
7462 M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16,
7463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7464 },
7465 /* xchg.w r0,$Dst16AnHI */
7466 {
7467 M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16,
7468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7469 },
7470 /* xchg.w r0,[$Dst16An] */
7471 {
7472 M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16,
7473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7474 },
7475 /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
7476 {
7477 M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24,
7478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7479 },
7480 /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
7481 {
7482 M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32,
7483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7484 },
7485 /* xchg.w r0,${Dsp-16-u8}[sb] */
7486 {
7487 M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7489 },
7490 /* xchg.w r0,${Dsp-16-u16}[sb] */
7491 {
7492 M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7494 },
7495 /* xchg.w r0,${Dsp-16-s8}[fb] */
7496 {
7497 M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7499 },
7500 /* xchg.w r0,${Dsp-16-u16} */
7501 {
7502 M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32,
7503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7504 },
7505 /* xchg.b r1h,$Dst16RnQI */
7506 {
7507 M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16,
7508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7509 },
7510 /* xchg.b r1h,$Dst16AnQI */
7511 {
7512 M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16,
7513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7514 },
7515 /* xchg.b r1h,[$Dst16An] */
7516 {
7517 M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16,
7518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7519 },
7520 /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
7521 {
7522 M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7524 },
7525 /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
7526 {
7527 M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7529 },
7530 /* xchg.b r1h,${Dsp-16-u8}[sb] */
7531 {
7532 M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7534 },
7535 /* xchg.b r1h,${Dsp-16-u16}[sb] */
7536 {
7537 M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7539 },
7540 /* xchg.b r1h,${Dsp-16-s8}[fb] */
7541 {
7542 M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7544 },
7545 /* xchg.b r1h,${Dsp-16-u16} */
7546 {
7547 M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32,
7548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7549 },
7550 /* xchg.b r1l,$Dst16RnQI */
7551 {
7552 M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16,
7553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7554 },
7555 /* xchg.b r1l,$Dst16AnQI */
7556 {
7557 M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16,
7558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7559 },
7560 /* xchg.b r1l,[$Dst16An] */
7561 {
7562 M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16,
7563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7564 },
7565 /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
7566 {
7567 M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7569 },
7570 /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
7571 {
7572 M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7574 },
7575 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7576 {
7577 M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7579 },
7580 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7581 {
7582 M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7584 },
7585 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7586 {
7587 M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7589 },
7590 /* xchg.b r1l,${Dsp-16-u16} */
7591 {
7592 M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32,
7593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7594 },
7595 /* xchg.b r0h,$Dst16RnQI */
7596 {
7597 M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16,
7598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7599 },
7600 /* xchg.b r0h,$Dst16AnQI */
7601 {
7602 M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16,
7603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7604 },
7605 /* xchg.b r0h,[$Dst16An] */
7606 {
7607 M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16,
7608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7609 },
7610 /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
7611 {
7612 M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7614 },
7615 /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
7616 {
7617 M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7619 },
7620 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7621 {
7622 M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7624 },
7625 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7626 {
7627 M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7629 },
7630 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7631 {
7632 M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7634 },
7635 /* xchg.b r0h,${Dsp-16-u16} */
7636 {
7637 M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32,
7638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7639 },
7640 /* xchg.b r0l,$Dst16RnQI */
7641 {
7642 M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16,
7643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7644 },
7645 /* xchg.b r0l,$Dst16AnQI */
7646 {
7647 M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16,
7648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7649 },
7650 /* xchg.b r0l,[$Dst16An] */
7651 {
7652 M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16,
7653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7654 },
7655 /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
7656 {
7657 M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7659 },
7660 /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
7661 {
7662 M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7664 },
7665 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7666 {
7667 M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7669 },
7670 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7671 {
7672 M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7674 },
7675 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7676 {
7677 M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7679 },
7680 /* xchg.b r0l,${Dsp-16-u16} */
7681 {
7682 M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32,
7683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7684 },
7685 /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
7686 {
7687 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32,
7688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7689 },
7690 /* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
7691 {
7692 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32,
7693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7694 },
7695 /* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
7696 {
7697 M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40,
7698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7699 },
7700 /* tst.w${S} #${Imm-8-HI},r0 */
7701 {
7702 M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24,
7703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7704 },
7705 /* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
7706 {
7707 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24,
7708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7709 },
7710 /* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
7711 {
7712 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24,
7713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7714 },
7715 /* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
7716 {
7717 M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32,
7718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7719 },
7720 /* tst.b${S} #${Imm-8-QI},r0l */
7721 {
7722 M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16,
7723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7724 },
7725 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7726 {
7727 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7729 },
7730 /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
7731 {
7732 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7734 },
7735 /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
7736 {
7737 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7739 },
7740 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7741 {
7742 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7744 },
7745 /* tst.w${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
7746 {
7747 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7749 },
7750 /* tst.w${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
7751 {
7752 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7754 },
7755 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7756 {
7757 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7759 },
7760 /* tst.w${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
7761 {
7762 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7764 },
7765 /* tst.w${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
7766 {
7767 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7769 },
7770 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
7771 {
7772 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7774 },
7775 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7776 {
7777 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7779 },
7780 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7781 {
7782 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7784 },
7785 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
7786 {
7787 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7789 },
7790 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7791 {
7792 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7794 },
7795 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7796 {
7797 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7799 },
7800 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
7801 {
7802 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7804 },
7805 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7806 {
7807 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7809 },
7810 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7811 {
7812 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7814 },
7815 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
7816 {
7817 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7819 },
7820 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
7821 {
7822 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7824 },
7825 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
7826 {
7827 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7829 },
7830 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
7831 {
7832 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7834 },
7835 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
7836 {
7837 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7839 },
7840 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
7841 {
7842 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7844 },
7845 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
7846 {
7847 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7849 },
7850 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
7851 {
7852 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7854 },
7855 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
7856 {
7857 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7859 },
7860 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
7861 {
7862 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7864 },
7865 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
7866 {
7867 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7869 },
7870 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
7871 {
7872 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7874 },
7875 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
7876 {
7877 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7879 },
7880 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
7881 {
7882 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7884 },
7885 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
7886 {
7887 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7889 },
7890 /* tst.w${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
7891 {
7892 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7894 },
7895 /* tst.w${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
7896 {
7897 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7899 },
7900 /* tst.w${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
7901 {
7902 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7904 },
7905 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7906 {
7907 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7909 },
7910 /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
7911 {
7912 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7914 },
7915 /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
7916 {
7917 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7919 },
7920 /* tst.w${G} ${Dsp-24-u16},$Dst32RnPrefixedHI */
7921 {
7922 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7924 },
7925 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7926 {
7927 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7929 },
7930 /* tst.w${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
7931 {
7932 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7934 },
7935 /* tst.w${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
7936 {
7937 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7939 },
7940 /* tst.w${G} ${Dsp-24-u16},$Dst32AnPrefixedHI */
7941 {
7942 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7944 },
7945 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7946 {
7947 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7949 },
7950 /* tst.w${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
7951 {
7952 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7954 },
7955 /* tst.w${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
7956 {
7957 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7959 },
7960 /* tst.w${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
7961 {
7962 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7964 },
7965 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
7966 {
7967 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7969 },
7970 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7971 {
7972 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7974 },
7975 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7976 {
7977 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7979 },
7980 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
7981 {
7982 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7984 },
7985 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
7986 {
7987 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7989 },
7990 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
7991 {
7992 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7994 },
7995 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
7996 {
7997 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7999 },
8000 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8001 {
8002 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8004 },
8005 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8006 {
8007 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8009 },
8010 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8011 {
8012 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8014 },
8015 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8016 {
8017 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8019 },
8020 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8021 {
8022 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8024 },
8025 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8026 {
8027 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8029 },
8030 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8031 {
8032 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8034 },
8035 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8036 {
8037 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8039 },
8040 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8041 {
8042 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8044 },
8045 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8046 {
8047 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8049 },
8050 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8051 {
8052 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8054 },
8055 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8056 {
8057 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8059 },
8060 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8061 {
8062 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8064 },
8065 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8066 {
8067 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8069 },
8070 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8071 {
8072 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8074 },
8075 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8076 {
8077 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8079 },
8080 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8081 {
8082 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8084 },
8085 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8086 {
8087 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8089 },
8090 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8091 {
8092 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8094 },
8095 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8096 {
8097 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8099 },
8100 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8101 {
8102 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8104 },
8105 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8106 {
8107 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8109 },
8110 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8111 {
8112 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8114 },
8115 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8116 {
8117 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8119 },
8120 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u16} */
8121 {
8122 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8124 },
8125 /* tst.w${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8126 {
8127 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8129 },
8130 /* tst.w${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8131 {
8132 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8134 },
8135 /* tst.w${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8136 {
8137 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8139 },
8140 /* tst.w${G} ${Dsp-24-u16},${Dsp-40-u24} */
8141 {
8142 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8144 },
8145 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8146 {
8147 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8149 },
8150 /* tst.w${G} ${Dsp-24-u24},$Dst32RnPrefixedHI */
8151 {
8152 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8154 },
8155 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8156 {
8157 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8159 },
8160 /* tst.w${G} ${Dsp-24-u24},$Dst32AnPrefixedHI */
8161 {
8162 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8164 },
8165 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8166 {
8167 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8169 },
8170 /* tst.w${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8171 {
8172 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8174 },
8175 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8176 {
8177 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8179 },
8180 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8181 {
8182 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8184 },
8185 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8186 {
8187 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8189 },
8190 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8191 {
8192 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8194 },
8195 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8196 {
8197 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8199 },
8200 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8201 {
8202 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8204 },
8205 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8206 {
8207 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8209 },
8210 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8211 {
8212 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8214 },
8215 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8216 {
8217 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8219 },
8220 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8221 {
8222 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8224 },
8225 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8226 {
8227 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8229 },
8230 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8231 {
8232 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8234 },
8235 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8236 {
8237 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8239 },
8240 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8241 {
8242 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8244 },
8245 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8246 {
8247 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8249 },
8250 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u16} */
8251 {
8252 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8254 },
8255 /* tst.w${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8256 {
8257 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8259 },
8260 /* tst.w${G} ${Dsp-24-u24},${Dsp-48-u24} */
8261 {
8262 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8264 },
8265 /* tst.w${G} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
8266 {
8267 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8269 },
8270 /* tst.w${G} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
8271 {
8272 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8274 },
8275 /* tst.w${G} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
8276 {
8277 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8279 },
8280 /* tst.w${G} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
8281 {
8282 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8284 },
8285 /* tst.w${G} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
8286 {
8287 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8289 },
8290 /* tst.w${G} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
8291 {
8292 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8294 },
8295 /* tst.w${G} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
8296 {
8297 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8299 },
8300 /* tst.w${G} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
8301 {
8302 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8304 },
8305 /* tst.w${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
8306 {
8307 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8309 },
8310 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8311 {
8312 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8314 },
8315 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8316 {
8317 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8319 },
8320 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
8321 {
8322 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8324 },
8325 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8326 {
8327 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8329 },
8330 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8331 {
8332 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8334 },
8335 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
8336 {
8337 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8339 },
8340 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8341 {
8342 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8344 },
8345 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8346 {
8347 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8349 },
8350 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
8351 {
8352 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8354 },
8355 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
8356 {
8357 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8359 },
8360 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
8361 {
8362 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8364 },
8365 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
8366 {
8367 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8369 },
8370 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
8371 {
8372 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8374 },
8375 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
8376 {
8377 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8379 },
8380 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
8381 {
8382 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8384 },
8385 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
8386 {
8387 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8389 },
8390 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
8391 {
8392 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8394 },
8395 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
8396 {
8397 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8399 },
8400 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
8401 {
8402 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8404 },
8405 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
8406 {
8407 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8409 },
8410 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
8411 {
8412 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8414 },
8415 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u16} */
8416 {
8417 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8419 },
8420 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u16} */
8421 {
8422 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8424 },
8425 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u16} */
8426 {
8427 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8429 },
8430 /* tst.w${G} $Src32RnPrefixedHI,${Dsp-24-u24} */
8431 {
8432 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8434 },
8435 /* tst.w${G} $Src32AnPrefixedHI,${Dsp-24-u24} */
8436 {
8437 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8439 },
8440 /* tst.w${G} [$Src32AnPrefixed],${Dsp-24-u24} */
8441 {
8442 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8444 },
8445 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8446 {
8447 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8449 },
8450 /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
8451 {
8452 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8454 },
8455 /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
8456 {
8457 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8459 },
8460 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8461 {
8462 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8464 },
8465 /* tst.b${G} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
8466 {
8467 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8469 },
8470 /* tst.b${G} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
8471 {
8472 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8474 },
8475 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8476 {
8477 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8479 },
8480 /* tst.b${G} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
8481 {
8482 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8484 },
8485 /* tst.b${G} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
8486 {
8487 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8489 },
8490 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
8491 {
8492 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8494 },
8495 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8496 {
8497 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8499 },
8500 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8501 {
8502 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8504 },
8505 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
8506 {
8507 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8509 },
8510 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8511 {
8512 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8514 },
8515 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8516 {
8517 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8519 },
8520 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
8521 {
8522 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8524 },
8525 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8526 {
8527 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8529 },
8530 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8531 {
8532 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8534 },
8535 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8536 {
8537 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8539 },
8540 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8541 {
8542 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8544 },
8545 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8546 {
8547 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8549 },
8550 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8551 {
8552 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8554 },
8555 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8556 {
8557 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8559 },
8560 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8561 {
8562 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8564 },
8565 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8566 {
8567 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8569 },
8570 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8571 {
8572 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8574 },
8575 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8576 {
8577 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8579 },
8580 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8581 {
8582 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8584 },
8585 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8586 {
8587 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8589 },
8590 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8591 {
8592 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8594 },
8595 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8596 {
8597 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8599 },
8600 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8601 {
8602 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8604 },
8605 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8606 {
8607 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8609 },
8610 /* tst.b${G} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8611 {
8612 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8614 },
8615 /* tst.b${G} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8616 {
8617 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8619 },
8620 /* tst.b${G} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8621 {
8622 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8624 },
8625 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8626 {
8627 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8629 },
8630 /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
8631 {
8632 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8634 },
8635 /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
8636 {
8637 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8639 },
8640 /* tst.b${G} ${Dsp-24-u16},$Dst32RnPrefixedQI */
8641 {
8642 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8644 },
8645 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8646 {
8647 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8649 },
8650 /* tst.b${G} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
8651 {
8652 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8654 },
8655 /* tst.b${G} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
8656 {
8657 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8659 },
8660 /* tst.b${G} ${Dsp-24-u16},$Dst32AnPrefixedQI */
8661 {
8662 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8664 },
8665 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8666 {
8667 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8669 },
8670 /* tst.b${G} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8671 {
8672 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8674 },
8675 /* tst.b${G} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8676 {
8677 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8679 },
8680 /* tst.b${G} ${Dsp-24-u16},[$Dst32AnPrefixed] */
8681 {
8682 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8684 },
8685 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8686 {
8687 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8689 },
8690 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8691 {
8692 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8694 },
8695 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8696 {
8697 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8699 },
8700 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8701 {
8702 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8704 },
8705 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8706 {
8707 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8709 },
8710 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8711 {
8712 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8714 },
8715 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8716 {
8717 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8719 },
8720 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8721 {
8722 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8724 },
8725 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8726 {
8727 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8729 },
8730 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8731 {
8732 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8734 },
8735 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8736 {
8737 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8739 },
8740 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8741 {
8742 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8744 },
8745 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8746 {
8747 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8749 },
8750 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8751 {
8752 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8754 },
8755 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8756 {
8757 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8759 },
8760 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8761 {
8762 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8764 },
8765 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8766 {
8767 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8769 },
8770 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8771 {
8772 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8774 },
8775 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8776 {
8777 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8779 },
8780 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8781 {
8782 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8784 },
8785 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8786 {
8787 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8789 },
8790 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8791 {
8792 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8794 },
8795 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8796 {
8797 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8799 },
8800 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8801 {
8802 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8804 },
8805 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8806 {
8807 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8809 },
8810 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8811 {
8812 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8814 },
8815 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8816 {
8817 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8819 },
8820 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8821 {
8822 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8824 },
8825 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8826 {
8827 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8829 },
8830 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8831 {
8832 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8834 },
8835 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8836 {
8837 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8839 },
8840 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u16} */
8841 {
8842 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8844 },
8845 /* tst.b${G} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8846 {
8847 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8849 },
8850 /* tst.b${G} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8851 {
8852 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8854 },
8855 /* tst.b${G} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8856 {
8857 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8859 },
8860 /* tst.b${G} ${Dsp-24-u16},${Dsp-40-u24} */
8861 {
8862 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8864 },
8865 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8866 {
8867 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8869 },
8870 /* tst.b${G} ${Dsp-24-u24},$Dst32RnPrefixedQI */
8871 {
8872 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8874 },
8875 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8876 {
8877 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8879 },
8880 /* tst.b${G} ${Dsp-24-u24},$Dst32AnPrefixedQI */
8881 {
8882 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8884 },
8885 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8886 {
8887 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8889 },
8890 /* tst.b${G} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8891 {
8892 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8894 },
8895 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8896 {
8897 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8899 },
8900 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8901 {
8902 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8904 },
8905 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8906 {
8907 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8909 },
8910 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8911 {
8912 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8914 },
8915 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8916 {
8917 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8919 },
8920 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8921 {
8922 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8924 },
8925 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8926 {
8927 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8929 },
8930 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8931 {
8932 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8934 },
8935 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8936 {
8937 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8939 },
8940 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8941 {
8942 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8944 },
8945 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8946 {
8947 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8949 },
8950 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8951 {
8952 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8954 },
8955 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8956 {
8957 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8959 },
8960 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8961 {
8962 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8964 },
8965 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8966 {
8967 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8969 },
8970 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u16} */
8971 {
8972 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8974 },
8975 /* tst.b${G} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8976 {
8977 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
8978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8979 },
8980 /* tst.b${G} ${Dsp-24-u24},${Dsp-48-u24} */
8981 {
8982 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
8983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8984 },
8985 /* tst.b${G} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
8986 {
8987 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
8988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8989 },
8990 /* tst.b${G} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
8991 {
8992 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
8993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8994 },
8995 /* tst.b${G} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
8996 {
8997 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
8998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8999 },
9000 /* tst.b${G} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
9001 {
9002 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9004 },
9005 /* tst.b${G} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
9006 {
9007 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9009 },
9010 /* tst.b${G} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
9011 {
9012 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9014 },
9015 /* tst.b${G} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
9016 {
9017 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9019 },
9020 /* tst.b${G} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
9021 {
9022 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9024 },
9025 /* tst.b${G} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
9026 {
9027 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9029 },
9030 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9031 {
9032 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9034 },
9035 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9036 {
9037 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9039 },
9040 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
9041 {
9042 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9044 },
9045 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9046 {
9047 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9049 },
9050 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9051 {
9052 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9054 },
9055 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
9056 {
9057 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9059 },
9060 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9061 {
9062 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9064 },
9065 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9066 {
9067 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9069 },
9070 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
9071 {
9072 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9074 },
9075 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
9076 {
9077 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9079 },
9080 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
9081 {
9082 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9084 },
9085 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
9086 {
9087 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9089 },
9090 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
9091 {
9092 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9094 },
9095 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
9096 {
9097 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9099 },
9100 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
9101 {
9102 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9104 },
9105 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
9106 {
9107 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9109 },
9110 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
9111 {
9112 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9114 },
9115 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
9116 {
9117 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9119 },
9120 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
9121 {
9122 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9124 },
9125 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
9126 {
9127 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9129 },
9130 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
9131 {
9132 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9134 },
9135 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u16} */
9136 {
9137 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9139 },
9140 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u16} */
9141 {
9142 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9144 },
9145 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u16} */
9146 {
9147 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9149 },
9150 /* tst.b${G} $Src32RnPrefixedQI,${Dsp-24-u24} */
9151 {
9152 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9154 },
9155 /* tst.b${G} $Src32AnPrefixedQI,${Dsp-24-u24} */
9156 {
9157 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9159 },
9160 /* tst.b${G} [$Src32AnPrefixed],${Dsp-24-u24} */
9161 {
9162 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9164 },
9165 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
9166 {
9167 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9169 },
9170 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
9171 {
9172 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9174 },
9175 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
9176 {
9177 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9179 },
9180 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
9181 {
9182 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9184 },
9185 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
9186 {
9187 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9189 },
9190 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
9191 {
9192 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9194 },
9195 /* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9196 {
9197 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9199 },
9200 /* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9201 {
9202 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9204 },
9205 /* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9206 {
9207 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9209 },
9210 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9211 {
9212 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9214 },
9215 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9216 {
9217 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9219 },
9220 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9221 {
9222 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9224 },
9225 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9226 {
9227 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9229 },
9230 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9231 {
9232 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9234 },
9235 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9236 {
9237 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9239 },
9240 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9241 {
9242 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9244 },
9245 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9246 {
9247 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9249 },
9250 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9251 {
9252 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9254 },
9255 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9256 {
9257 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9259 },
9260 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9261 {
9262 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9264 },
9265 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9266 {
9267 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9269 },
9270 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9271 {
9272 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9274 },
9275 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9276 {
9277 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9279 },
9280 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9281 {
9282 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9284 },
9285 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9286 {
9287 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9289 },
9290 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9291 {
9292 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9294 },
9295 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9296 {
9297 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9299 },
9300 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
9301 {
9302 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9304 },
9305 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
9306 {
9307 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9309 },
9310 /* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
9311 {
9312 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32,
9313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9314 },
9315 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
9316 {
9317 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9319 },
9320 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
9321 {
9322 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9324 },
9325 /* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
9326 {
9327 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32,
9328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9329 },
9330 /* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9331 {
9332 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9334 },
9335 /* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9336 {
9337 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9339 },
9340 /* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
9341 {
9342 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32,
9343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9344 },
9345 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9346 {
9347 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9349 },
9350 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9351 {
9352 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9354 },
9355 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9356 {
9357 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9359 },
9360 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9361 {
9362 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9364 },
9365 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9366 {
9367 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9369 },
9370 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9371 {
9372 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9374 },
9375 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9376 {
9377 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9379 },
9380 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9381 {
9382 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9384 },
9385 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9386 {
9387 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9389 },
9390 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9391 {
9392 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9394 },
9395 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9396 {
9397 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9399 },
9400 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9401 {
9402 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9404 },
9405 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9406 {
9407 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9409 },
9410 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9411 {
9412 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9414 },
9415 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9416 {
9417 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9419 },
9420 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9421 {
9422 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9424 },
9425 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9426 {
9427 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9429 },
9430 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
9431 {
9432 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9434 },
9435 /* tst.w${X} $Src16RnHI,$Dst16RnHI */
9436 {
9437 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9439 },
9440 /* tst.w${X} $Src16AnHI,$Dst16RnHI */
9441 {
9442 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9444 },
9445 /* tst.w${X} [$Src16An],$Dst16RnHI */
9446 {
9447 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16,
9448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9449 },
9450 /* tst.w${X} $Src16RnHI,$Dst16AnHI */
9451 {
9452 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9454 },
9455 /* tst.w${X} $Src16AnHI,$Dst16AnHI */
9456 {
9457 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9459 },
9460 /* tst.w${X} [$Src16An],$Dst16AnHI */
9461 {
9462 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16,
9463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9464 },
9465 /* tst.w${X} $Src16RnHI,[$Dst16An] */
9466 {
9467 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9469 },
9470 /* tst.w${X} $Src16AnHI,[$Dst16An] */
9471 {
9472 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9474 },
9475 /* tst.w${X} [$Src16An],[$Dst16An] */
9476 {
9477 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16,
9478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9479 },
9480 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
9481 {
9482 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9484 },
9485 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
9486 {
9487 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9489 },
9490 /* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9491 {
9492 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9494 },
9495 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
9496 {
9497 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9499 },
9500 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
9501 {
9502 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9504 },
9505 /* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9506 {
9507 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9509 },
9510 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
9511 {
9512 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9514 },
9515 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
9516 {
9517 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9519 },
9520 /* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
9521 {
9522 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9524 },
9525 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
9526 {
9527 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9529 },
9530 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
9531 {
9532 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9534 },
9535 /* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
9536 {
9537 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9539 },
9540 /* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
9541 {
9542 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9544 },
9545 /* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
9546 {
9547 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9549 },
9550 /* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
9551 {
9552 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9554 },
9555 /* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
9556 {
9557 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9559 },
9560 /* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
9561 {
9562 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9564 },
9565 /* tst.w${X} [$Src16An],${Dsp-16-u16} */
9566 {
9567 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9569 },
9570 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
9571 {
9572 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9574 },
9575 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
9576 {
9577 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9579 },
9580 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
9581 {
9582 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9584 },
9585 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
9586 {
9587 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9589 },
9590 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
9591 {
9592 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9594 },
9595 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
9596 {
9597 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9599 },
9600 /* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9601 {
9602 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9604 },
9605 /* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9606 {
9607 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9609 },
9610 /* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9611 {
9612 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9614 },
9615 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9616 {
9617 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9619 },
9620 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9621 {
9622 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9624 },
9625 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9626 {
9627 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9629 },
9630 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9631 {
9632 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9634 },
9635 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9636 {
9637 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9639 },
9640 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9641 {
9642 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9644 },
9645 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9646 {
9647 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9649 },
9650 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9651 {
9652 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9654 },
9655 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9656 {
9657 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9659 },
9660 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9661 {
9662 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9664 },
9665 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9666 {
9667 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9669 },
9670 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9671 {
9672 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9674 },
9675 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9676 {
9677 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9679 },
9680 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9681 {
9682 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9684 },
9685 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9686 {
9687 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9689 },
9690 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9691 {
9692 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9694 },
9695 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9696 {
9697 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9699 },
9700 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9701 {
9702 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9704 },
9705 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
9706 {
9707 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9709 },
9710 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
9711 {
9712 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9714 },
9715 /* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
9716 {
9717 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32,
9718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9719 },
9720 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
9721 {
9722 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9724 },
9725 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
9726 {
9727 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9729 },
9730 /* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
9731 {
9732 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32,
9733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9734 },
9735 /* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9736 {
9737 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9739 },
9740 /* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9741 {
9742 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9744 },
9745 /* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
9746 {
9747 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32,
9748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9749 },
9750 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9751 {
9752 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9754 },
9755 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9756 {
9757 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9759 },
9760 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9761 {
9762 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9764 },
9765 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9766 {
9767 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9769 },
9770 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9771 {
9772 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9774 },
9775 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9776 {
9777 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9779 },
9780 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9781 {
9782 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9784 },
9785 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9786 {
9787 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9789 },
9790 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9791 {
9792 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9794 },
9795 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9796 {
9797 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9799 },
9800 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9801 {
9802 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9804 },
9805 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9806 {
9807 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9809 },
9810 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9811 {
9812 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9814 },
9815 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9816 {
9817 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9819 },
9820 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9821 {
9822 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9824 },
9825 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9826 {
9827 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9829 },
9830 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9831 {
9832 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9834 },
9835 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
9836 {
9837 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9839 },
9840 /* tst.b${X} $Src16RnQI,$Dst16RnQI */
9841 {
9842 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9844 },
9845 /* tst.b${X} $Src16AnQI,$Dst16RnQI */
9846 {
9847 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9849 },
9850 /* tst.b${X} [$Src16An],$Dst16RnQI */
9851 {
9852 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16,
9853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9854 },
9855 /* tst.b${X} $Src16RnQI,$Dst16AnQI */
9856 {
9857 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9859 },
9860 /* tst.b${X} $Src16AnQI,$Dst16AnQI */
9861 {
9862 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9864 },
9865 /* tst.b${X} [$Src16An],$Dst16AnQI */
9866 {
9867 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16,
9868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9869 },
9870 /* tst.b${X} $Src16RnQI,[$Dst16An] */
9871 {
9872 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9874 },
9875 /* tst.b${X} $Src16AnQI,[$Dst16An] */
9876 {
9877 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9879 },
9880 /* tst.b${X} [$Src16An],[$Dst16An] */
9881 {
9882 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16,
9883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9884 },
9885 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
9886 {
9887 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9889 },
9890 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
9891 {
9892 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9894 },
9895 /* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9896 {
9897 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9899 },
9900 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
9901 {
9902 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9904 },
9905 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
9906 {
9907 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9909 },
9910 /* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9911 {
9912 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9914 },
9915 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
9916 {
9917 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9919 },
9920 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
9921 {
9922 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9924 },
9925 /* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
9926 {
9927 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9929 },
9930 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
9931 {
9932 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9934 },
9935 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
9936 {
9937 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9939 },
9940 /* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
9941 {
9942 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9944 },
9945 /* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
9946 {
9947 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9949 },
9950 /* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
9951 {
9952 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9954 },
9955 /* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
9956 {
9957 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9959 },
9960 /* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
9961 {
9962 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9964 },
9965 /* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
9966 {
9967 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9969 },
9970 /* tst.b${X} [$Src16An],${Dsp-16-u16} */
9971 {
9972 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9974 },
9975 /* tst.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
9976 {
9977 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32,
9978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9979 },
9980 /* tst.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
9981 {
9982 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32,
9983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9984 },
9985 /* tst.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
9986 {
9987 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32,
9988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9989 },
9990 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
9991 {
9992 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40,
9993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9994 },
9995 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
9996 {
9997 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40,
9998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9999 },
10000 /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
10001 {
10002 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40,
10003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10004 },
10005 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10006 {
10007 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48,
10008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10009 },
10010 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
10011 {
10012 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48,
10013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10014 },
10015 /* tst.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
10016 {
10017 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48,
10018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10019 },
10020 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
10021 {
10022 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48,
10023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10024 },
10025 /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10026 {
10027 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56,
10028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10029 },
10030 /* tst.w${G} #${Imm-40-HI},${Dsp-16-u24} */
10031 {
10032 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56,
10033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10034 },
10035 /* tst.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
10036 {
10037 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24,
10038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10039 },
10040 /* tst.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
10041 {
10042 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24,
10043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10044 },
10045 /* tst.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10046 {
10047 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24,
10048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10049 },
10050 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10051 {
10052 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32,
10053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10054 },
10055 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10056 {
10057 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32,
10058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10059 },
10060 /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10061 {
10062 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32,
10063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10064 },
10065 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10066 {
10067 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40,
10068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10069 },
10070 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10071 {
10072 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40,
10073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10074 },
10075 /* tst.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10076 {
10077 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40,
10078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10079 },
10080 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
10081 {
10082 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40,
10083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10084 },
10085 /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10086 {
10087 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48,
10088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10089 },
10090 /* tst.b${G} #${Imm-40-QI},${Dsp-16-u24} */
10091 {
10092 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48,
10093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10094 },
10095 /* tst.w${G} #${Imm-16-HI},$Dst16RnHI */
10096 {
10097 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32,
10098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10099 },
10100 /* tst.w${G} #${Imm-16-HI},$Dst16AnHI */
10101 {
10102 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32,
10103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10104 },
10105 /* tst.w${G} #${Imm-16-HI},[$Dst16An] */
10106 {
10107 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32,
10108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10109 },
10110 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
10111 {
10112 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40,
10113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10114 },
10115 /* tst.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
10116 {
10117 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40,
10118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10119 },
10120 /* tst.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
10121 {
10122 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40,
10123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10124 },
10125 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
10126 {
10127 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48,
10128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10129 },
10130 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
10131 {
10132 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48,
10133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10134 },
10135 /* tst.w${G} #${Imm-32-HI},${Dsp-16-u16} */
10136 {
10137 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48,
10138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10139 },
10140 /* tst.b${G} #${Imm-16-QI},$Dst16RnQI */
10141 {
10142 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24,
10143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10144 },
10145 /* tst.b${G} #${Imm-16-QI},$Dst16AnQI */
10146 {
10147 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24,
10148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10149 },
10150 /* tst.b${G} #${Imm-16-QI},[$Dst16An] */
10151 {
10152 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24,
10153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10154 },
10155 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
10156 {
10157 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32,
10158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10159 },
10160 /* tst.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10161 {
10162 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32,
10163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10164 },
10165 /* tst.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10166 {
10167 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32,
10168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10169 },
10170 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
10171 {
10172 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40,
10173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10174 },
10175 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10176 {
10177 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40,
10178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10179 },
10180 /* tst.b${G} #${Imm-32-QI},${Dsp-16-u16} */
10181 {
10182 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40,
10183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10184 },
10185 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10186 {
10187 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10189 },
10190 /* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
10191 {
10192 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10194 },
10195 /* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
10196 {
10197 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10199 },
10200 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10201 {
10202 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10204 },
10205 /* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
10206 {
10207 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10209 },
10210 /* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
10211 {
10212 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10214 },
10215 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10216 {
10217 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10219 },
10220 /* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10221 {
10222 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10224 },
10225 /* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10226 {
10227 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10229 },
10230 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10231 {
10232 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10234 },
10235 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10236 {
10237 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10239 },
10240 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10241 {
10242 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10244 },
10245 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10246 {
10247 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10249 },
10250 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10251 {
10252 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10254 },
10255 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10256 {
10257 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10259 },
10260 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10261 {
10262 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10264 },
10265 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10266 {
10267 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10269 },
10270 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10271 {
10272 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10274 },
10275 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10276 {
10277 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10279 },
10280 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10281 {
10282 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10284 },
10285 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10286 {
10287 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10289 },
10290 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10291 {
10292 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10294 },
10295 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10296 {
10297 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10299 },
10300 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10301 {
10302 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10304 },
10305 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10306 {
10307 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10309 },
10310 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10311 {
10312 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10314 },
10315 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10316 {
10317 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10319 },
10320 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10321 {
10322 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10324 },
10325 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10326 {
10327 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10329 },
10330 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10331 {
10332 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10334 },
10335 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10336 {
10337 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10339 },
10340 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10341 {
10342 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10344 },
10345 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10346 {
10347 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10349 },
10350 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10351 {
10352 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10354 },
10355 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10356 {
10357 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10359 },
10360 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10361 {
10362 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10364 },
10365 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10366 {
10367 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10369 },
10370 /* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
10371 {
10372 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10374 },
10375 /* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
10376 {
10377 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10379 },
10380 /* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
10381 {
10382 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10384 },
10385 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10386 {
10387 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10389 },
10390 /* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
10391 {
10392 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10394 },
10395 /* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
10396 {
10397 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10399 },
10400 /* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
10401 {
10402 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10404 },
10405 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10406 {
10407 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10409 },
10410 /* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10411 {
10412 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10414 },
10415 /* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10416 {
10417 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10419 },
10420 /* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10421 {
10422 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10424 },
10425 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10426 {
10427 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10429 },
10430 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10431 {
10432 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10434 },
10435 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10436 {
10437 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10439 },
10440 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10441 {
10442 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10444 },
10445 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10446 {
10447 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10449 },
10450 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10451 {
10452 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10454 },
10455 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10456 {
10457 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10459 },
10460 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10461 {
10462 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10464 },
10465 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10466 {
10467 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10469 },
10470 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10471 {
10472 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10474 },
10475 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10476 {
10477 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10479 },
10480 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10481 {
10482 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10484 },
10485 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10486 {
10487 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10489 },
10490 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10491 {
10492 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10494 },
10495 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10496 {
10497 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10499 },
10500 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10501 {
10502 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10504 },
10505 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10506 {
10507 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10509 },
10510 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10511 {
10512 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10514 },
10515 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10516 {
10517 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10519 },
10520 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10521 {
10522 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10524 },
10525 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10526 {
10527 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10529 },
10530 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10531 {
10532 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10534 },
10535 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10536 {
10537 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10539 },
10540 /* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10541 {
10542 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10544 },
10545 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10546 {
10547 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10549 },
10550 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10551 {
10552 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10554 },
10555 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10556 {
10557 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10559 },
10560 /* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10561 {
10562 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10564 },
10565 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10566 {
10567 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10569 },
10570 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10571 {
10572 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10574 },
10575 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10576 {
10577 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10579 },
10580 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
10581 {
10582 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10584 },
10585 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10586 {
10587 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10589 },
10590 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10591 {
10592 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10594 },
10595 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10596 {
10597 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10599 },
10600 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
10601 {
10602 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10604 },
10605 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10606 {
10607 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10609 },
10610 /* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
10611 {
10612 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10614 },
10615 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10616 {
10617 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10619 },
10620 /* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
10621 {
10622 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10624 },
10625 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10626 {
10627 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10629 },
10630 /* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10631 {
10632 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10634 },
10635 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10636 {
10637 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10639 },
10640 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10641 {
10642 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10644 },
10645 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10646 {
10647 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10649 },
10650 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10651 {
10652 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10654 },
10655 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10656 {
10657 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10659 },
10660 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10661 {
10662 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10664 },
10665 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10666 {
10667 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10669 },
10670 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10671 {
10672 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10674 },
10675 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10676 {
10677 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10679 },
10680 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10681 {
10682 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10684 },
10685 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10686 {
10687 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10689 },
10690 /* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10691 {
10692 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10694 },
10695 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10696 {
10697 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10699 },
10700 /* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10701 {
10702 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10704 },
10705 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10706 {
10707 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10709 },
10710 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
10711 {
10712 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10714 },
10715 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10716 {
10717 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10719 },
10720 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
10721 {
10722 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10724 },
10725 /* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
10726 {
10727 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10729 },
10730 /* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
10731 {
10732 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10734 },
10735 /* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10736 {
10737 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10739 },
10740 /* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
10741 {
10742 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10744 },
10745 /* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
10746 {
10747 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10749 },
10750 /* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10751 {
10752 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10754 },
10755 /* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
10756 {
10757 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10759 },
10760 /* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
10761 {
10762 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10764 },
10765 /* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10766 {
10767 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10769 },
10770 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10771 {
10772 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10774 },
10775 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10776 {
10777 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10779 },
10780 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10781 {
10782 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10784 },
10785 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10786 {
10787 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10789 },
10790 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10791 {
10792 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10794 },
10795 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10796 {
10797 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10799 },
10800 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10801 {
10802 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10804 },
10805 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10806 {
10807 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10809 },
10810 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10811 {
10812 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10814 },
10815 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
10816 {
10817 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10819 },
10820 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
10821 {
10822 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10824 },
10825 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10826 {
10827 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10829 },
10830 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
10831 {
10832 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10834 },
10835 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
10836 {
10837 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10839 },
10840 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10841 {
10842 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10844 },
10845 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
10846 {
10847 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10849 },
10850 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
10851 {
10852 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10854 },
10855 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10856 {
10857 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10859 },
10860 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
10861 {
10862 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10864 },
10865 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
10866 {
10867 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10869 },
10870 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10871 {
10872 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10874 },
10875 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
10876 {
10877 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10879 },
10880 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
10881 {
10882 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10884 },
10885 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10886 {
10887 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10889 },
10890 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
10891 {
10892 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10894 },
10895 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
10896 {
10897 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10899 },
10900 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10901 {
10902 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10904 },
10905 /* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
10906 {
10907 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10909 },
10910 /* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
10911 {
10912 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24,
10913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10914 },
10915 /* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10916 {
10917 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10919 },
10920 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10921 {
10922 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32,
10923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10924 },
10925 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10926 {
10927 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32,
10928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10929 },
10930 /* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10931 {
10932 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32,
10933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10934 },
10935 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10936 {
10937 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40,
10938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10939 },
10940 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10941 {
10942 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40,
10943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10944 },
10945 /* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10946 {
10947 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40,
10948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10949 },
10950 /* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
10951 {
10952 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40,
10953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10954 },
10955 /* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10956 {
10957 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48,
10958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10959 },
10960 /* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
10961 {
10962 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48,
10963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10964 },
10965 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
10966 {
10967 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48,
10968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10969 },
10970 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
10971 {
10972 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48,
10973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10974 },
10975 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
10976 {
10977 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48,
10978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10979 },
10980 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10981 {
10982 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56,
10983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10984 },
10985 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
10986 {
10987 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56,
10988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10989 },
10990 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
10991 {
10992 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56,
10993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10994 },
10995 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10996 {
10997 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64,
10998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10999 },
11000 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
11001 {
11002 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64,
11003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11004 },
11005 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
11006 {
11007 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64,
11008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11009 },
11010 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
11011 {
11012 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64,
11013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11014 },
11015 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11016 {
11017 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72,
11018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11019 },
11020 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
11021 {
11022 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72,
11023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11024 },
11025 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
11026 {
11027 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32,
11028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11029 },
11030 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
11031 {
11032 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32,
11033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11034 },
11035 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
11036 {
11037 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32,
11038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11039 },
11040 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11041 {
11042 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40,
11043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11044 },
11045 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
11046 {
11047 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40,
11048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11049 },
11050 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
11051 {
11052 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40,
11053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11054 },
11055 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11056 {
11057 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48,
11058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11059 },
11060 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
11061 {
11062 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48,
11063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11064 },
11065 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
11066 {
11067 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48,
11068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11069 },
11070 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
11071 {
11072 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48,
11073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11074 },
11075 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11076 {
11077 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56,
11078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11079 },
11080 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
11081 {
11082 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56,
11083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11084 },
11085 /* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11086 {
11087 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32,
11088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11089 },
11090 /* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11091 {
11092 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32,
11093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11094 },
11095 /* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11096 {
11097 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32,
11098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11099 },
11100 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11101 {
11102 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40,
11103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11104 },
11105 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11106 {
11107 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40,
11108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11109 },
11110 /* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11111 {
11112 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40,
11113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11114 },
11115 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11116 {
11117 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48,
11118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11119 },
11120 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11121 {
11122 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48,
11123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11124 },
11125 /* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11126 {
11127 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48,
11128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11129 },
11130 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11131 {
11132 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48,
11133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11134 },
11135 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11136 {
11137 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56,
11138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11139 },
11140 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11141 {
11142 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56,
11143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11144 },
11145 /* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11146 {
11147 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24,
11148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11149 },
11150 /* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11151 {
11152 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24,
11153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11154 },
11155 /* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11156 {
11157 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24,
11158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11159 },
11160 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11161 {
11162 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32,
11163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11164 },
11165 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11166 {
11167 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32,
11168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11169 },
11170 /* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11171 {
11172 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32,
11173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11174 },
11175 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11176 {
11177 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40,
11178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11179 },
11180 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11181 {
11182 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40,
11183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11184 },
11185 /* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11186 {
11187 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40,
11188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11189 },
11190 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11191 {
11192 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40,
11193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11194 },
11195 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11196 {
11197 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48,
11198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11199 },
11200 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11201 {
11202 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48,
11203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11204 },
11205 /* stz${S} #${Imm-8-QI},r0l */
11206 {
11207 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16,
11208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11209 },
11210 /* stz${S} #${Imm-8-QI},r0h */
11211 {
11212 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16,
11213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11214 },
11215 /* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11216 {
11217 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24,
11218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11219 },
11220 /* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11221 {
11222 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24,
11223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11224 },
11225 /* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
11226 {
11227 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32,
11228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11229 },
11230 /* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11231 {
11232 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32,
11233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11234 },
11235 /* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11236 {
11237 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32,
11238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11239 },
11240 /* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11241 {
11242 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32,
11243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11244 },
11245 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11246 {
11247 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40,
11248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11249 },
11250 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11251 {
11252 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40,
11253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11254 },
11255 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11256 {
11257 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40,
11258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11259 },
11260 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11261 {
11262 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48,
11263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11264 },
11265 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11266 {
11267 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48,
11268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11269 },
11270 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11271 {
11272 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48,
11273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11274 },
11275 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11276 {
11277 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48,
11278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11279 },
11280 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11281 {
11282 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56,
11283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11284 },
11285 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11286 {
11287 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56,
11288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11289 },
11290 /* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11291 {
11292 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24,
11293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11294 },
11295 /* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11296 {
11297 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24,
11298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11299 },
11300 /* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11301 {
11302 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24,
11303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11304 },
11305 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11306 {
11307 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32,
11308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11309 },
11310 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11311 {
11312 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32,
11313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11314 },
11315 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11316 {
11317 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32,
11318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11319 },
11320 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11321 {
11322 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40,
11323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11324 },
11325 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11326 {
11327 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40,
11328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11329 },
11330 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11331 {
11332 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40,
11333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11334 },
11335 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11336 {
11337 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40,
11338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11339 },
11340 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11341 {
11342 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48,
11343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11344 },
11345 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11346 {
11347 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48,
11348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11349 },
11350 /* stnz${S} #${Imm-8-QI},r0l */
11351 {
11352 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16,
11353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11354 },
11355 /* stnz${S} #${Imm-8-QI},r0h */
11356 {
11357 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16,
11358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11359 },
11360 /* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11361 {
11362 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24,
11363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11364 },
11365 /* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11366 {
11367 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24,
11368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11369 },
11370 /* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
11371 {
11372 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32,
11373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11374 },
11375 /* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11376 {
11377 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24,
11378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11379 },
11380 /* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11381 {
11382 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24,
11383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11384 },
11385 /* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11386 {
11387 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24,
11388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11389 },
11390 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11391 {
11392 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32,
11393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11394 },
11395 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11396 {
11397 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32,
11398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11399 },
11400 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11401 {
11402 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32,
11403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11404 },
11405 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11406 {
11407 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40,
11408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11409 },
11410 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11411 {
11412 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40,
11413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11414 },
11415 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11416 {
11417 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40,
11418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11419 },
11420 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11421 {
11422 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40,
11423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11424 },
11425 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11426 {
11427 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48,
11428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11429 },
11430 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11431 {
11432 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48,
11433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11434 },
11435 /* shl.l r1h,$Dst32RnUnprefixedSI */
11436 {
11437 M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16,
11438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11439 },
11440 /* shl.l r1h,$Dst32AnUnprefixedSI */
11441 {
11442 M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16,
11443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11444 },
11445 /* shl.l r1h,[$Dst32AnUnprefixed] */
11446 {
11447 M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16,
11448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11449 },
11450 /* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11451 {
11452 M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24,
11453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11454 },
11455 /* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11456 {
11457 M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32,
11458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11459 },
11460 /* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11461 {
11462 M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40,
11463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11464 },
11465 /* shl.l r1h,${Dsp-16-u8}[sb] */
11466 {
11467 M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24,
11468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11469 },
11470 /* shl.l r1h,${Dsp-16-u16}[sb] */
11471 {
11472 M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32,
11473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11474 },
11475 /* shl.l r1h,${Dsp-16-s8}[fb] */
11476 {
11477 M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24,
11478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11479 },
11480 /* shl.l r1h,${Dsp-16-s16}[fb] */
11481 {
11482 M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32,
11483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11484 },
11485 /* shl.l r1h,${Dsp-16-u16} */
11486 {
11487 M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32,
11488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11489 },
11490 /* shl.l r1h,${Dsp-16-u24} */
11491 {
11492 M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40,
11493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11494 },
11495 /* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11496 {
11497 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24,
11498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11499 },
11500 /* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11501 {
11502 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24,
11503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11504 },
11505 /* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11506 {
11507 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24,
11508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11509 },
11510 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11511 {
11512 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32,
11513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11514 },
11515 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11516 {
11517 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32,
11518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11519 },
11520 /* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11521 {
11522 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32,
11523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11524 },
11525 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11526 {
11527 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40,
11528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11529 },
11530 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11531 {
11532 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40,
11533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11534 },
11535 /* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11536 {
11537 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40,
11538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11539 },
11540 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11541 {
11542 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40,
11543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11544 },
11545 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11546 {
11547 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48,
11548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11549 },
11550 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11551 {
11552 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48,
11553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11554 },
11555 /* shl.w r1h,$Dst32RnUnprefixedHI */
11556 {
11557 M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11559 },
11560 /* shl.w r1h,$Dst32AnUnprefixedHI */
11561 {
11562 M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11564 },
11565 /* shl.w r1h,[$Dst32AnUnprefixed] */
11566 {
11567 M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11569 },
11570 /* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11571 {
11572 M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11574 },
11575 /* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11576 {
11577 M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11579 },
11580 /* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11581 {
11582 M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11584 },
11585 /* shl.w r1h,${Dsp-16-u8}[sb] */
11586 {
11587 M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11589 },
11590 /* shl.w r1h,${Dsp-16-u16}[sb] */
11591 {
11592 M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11594 },
11595 /* shl.w r1h,${Dsp-16-s8}[fb] */
11596 {
11597 M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11599 },
11600 /* shl.w r1h,${Dsp-16-s16}[fb] */
11601 {
11602 M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11604 },
11605 /* shl.w r1h,${Dsp-16-u16} */
11606 {
11607 M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11609 },
11610 /* shl.w r1h,${Dsp-16-u24} */
11611 {
11612 M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11614 },
11615 /* shl.b r1h,$Dst32RnUnprefixedQI */
11616 {
11617 M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11619 },
11620 /* shl.b r1h,$Dst32AnUnprefixedQI */
11621 {
11622 M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11624 },
11625 /* shl.b r1h,[$Dst32AnUnprefixed] */
11626 {
11627 M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11629 },
11630 /* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11631 {
11632 M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11634 },
11635 /* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11636 {
11637 M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11639 },
11640 /* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11641 {
11642 M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11644 },
11645 /* shl.b r1h,${Dsp-16-u8}[sb] */
11646 {
11647 M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11649 },
11650 /* shl.b r1h,${Dsp-16-u16}[sb] */
11651 {
11652 M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11654 },
11655 /* shl.b r1h,${Dsp-16-s8}[fb] */
11656 {
11657 M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11659 },
11660 /* shl.b r1h,${Dsp-16-s16}[fb] */
11661 {
11662 M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11664 },
11665 /* shl.b r1h,${Dsp-16-u16} */
11666 {
11667 M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11669 },
11670 /* shl.b r1h,${Dsp-16-u24} */
11671 {
11672 M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11674 },
11675 /* shl.w r1h,$Dst16RnHI */
11676 {
11677 M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16,
11678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11679 },
11680 /* shl.w r1h,$Dst16AnHI */
11681 {
11682 M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16,
11683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11684 },
11685 /* shl.w r1h,[$Dst16An] */
11686 {
11687 M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16,
11688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11689 },
11690 /* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
11691 {
11692 M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24,
11693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11694 },
11695 /* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
11696 {
11697 M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32,
11698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11699 },
11700 /* shl.w r1h,${Dsp-16-u8}[sb] */
11701 {
11702 M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24,
11703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11704 },
11705 /* shl.w r1h,${Dsp-16-u16}[sb] */
11706 {
11707 M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32,
11708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11709 },
11710 /* shl.w r1h,${Dsp-16-s8}[fb] */
11711 {
11712 M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24,
11713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11714 },
11715 /* shl.w r1h,${Dsp-16-u16} */
11716 {
11717 M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32,
11718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11719 },
11720 /* shl.b r1h,$Dst16RnQI */
11721 {
11722 M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16,
11723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11724 },
11725 /* shl.b r1h,$Dst16AnQI */
11726 {
11727 M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16,
11728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11729 },
11730 /* shl.b r1h,[$Dst16An] */
11731 {
11732 M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16,
11733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11734 },
11735 /* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
11736 {
11737 M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24,
11738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11739 },
11740 /* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
11741 {
11742 M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32,
11743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11744 },
11745 /* shl.b r1h,${Dsp-16-u8}[sb] */
11746 {
11747 M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24,
11748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11749 },
11750 /* shl.b r1h,${Dsp-16-u16}[sb] */
11751 {
11752 M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32,
11753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11754 },
11755 /* shl.b r1h,${Dsp-16-s8}[fb] */
11756 {
11757 M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24,
11758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11759 },
11760 /* shl.b r1h,${Dsp-16-u16} */
11761 {
11762 M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32,
11763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11764 },
11765 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
11766 {
11767 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11769 },
11770 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
11771 {
11772 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11774 },
11775 /* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11776 {
11777 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11779 },
11780 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11781 {
11782 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11784 },
11785 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11786 {
11787 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11789 },
11790 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11791 {
11792 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11794 },
11795 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11796 {
11797 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11799 },
11800 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11801 {
11802 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11804 },
11805 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11806 {
11807 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11809 },
11810 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11811 {
11812 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11814 },
11815 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11816 {
11817 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11819 },
11820 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11821 {
11822 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11824 },
11825 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
11826 {
11827 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11829 },
11830 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
11831 {
11832 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11834 },
11835 /* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11836 {
11837 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11839 },
11840 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11841 {
11842 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11844 },
11845 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11846 {
11847 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11849 },
11850 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11851 {
11852 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11854 },
11855 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11856 {
11857 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11859 },
11860 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11861 {
11862 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11864 },
11865 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11866 {
11867 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11869 },
11870 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11871 {
11872 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11874 },
11875 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11876 {
11877 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11879 },
11880 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11881 {
11882 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11884 },
11885 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
11886 {
11887 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16,
11888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11889 },
11890 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
11891 {
11892 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16,
11893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11894 },
11895 /* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
11896 {
11897 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16,
11898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11899 },
11900 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11901 {
11902 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24,
11903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11904 },
11905 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11906 {
11907 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32,
11908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11909 },
11910 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11911 {
11912 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24,
11913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11914 },
11915 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11916 {
11917 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32,
11918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11919 },
11920 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11921 {
11922 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24,
11923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11924 },
11925 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11926 {
11927 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32,
11928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11929 },
11930 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
11931 {
11932 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16,
11933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11934 },
11935 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
11936 {
11937 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16,
11938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11939 },
11940 /* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
11941 {
11942 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16,
11943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11944 },
11945 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11946 {
11947 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24,
11948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11949 },
11950 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11951 {
11952 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32,
11953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11954 },
11955 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11956 {
11957 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24,
11958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11959 },
11960 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11961 {
11962 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32,
11963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11964 },
11965 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11966 {
11967 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24,
11968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11969 },
11970 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11971 {
11972 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32,
11973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11974 },
11975 /* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11976 {
11977 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24,
11978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11979 },
11980 /* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11981 {
11982 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24,
11983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11984 },
11985 /* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11986 {
11987 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24,
11988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11989 },
11990 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11991 {
11992 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32,
11993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11994 },
11995 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11996 {
11997 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32,
11998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11999 },
12000 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12001 {
12002 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32,
12003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12004 },
12005 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12006 {
12007 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40,
12008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12009 },
12010 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12011 {
12012 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40,
12013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12014 },
12015 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12016 {
12017 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40,
12018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12019 },
12020 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12021 {
12022 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40,
12023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12024 },
12025 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12026 {
12027 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48,
12028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12029 },
12030 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12031 {
12032 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48,
12033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12034 },
12035 /* sha.l r1h,$Dst32RnUnprefixedSI */
12036 {
12037 M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16,
12038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12039 },
12040 /* sha.l r1h,$Dst32AnUnprefixedSI */
12041 {
12042 M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16,
12043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12044 },
12045 /* sha.l r1h,[$Dst32AnUnprefixed] */
12046 {
12047 M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16,
12048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12049 },
12050 /* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12051 {
12052 M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24,
12053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12054 },
12055 /* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12056 {
12057 M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32,
12058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12059 },
12060 /* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12061 {
12062 M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40,
12063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12064 },
12065 /* sha.l r1h,${Dsp-16-u8}[sb] */
12066 {
12067 M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24,
12068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12069 },
12070 /* sha.l r1h,${Dsp-16-u16}[sb] */
12071 {
12072 M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32,
12073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12074 },
12075 /* sha.l r1h,${Dsp-16-s8}[fb] */
12076 {
12077 M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24,
12078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12079 },
12080 /* sha.l r1h,${Dsp-16-s16}[fb] */
12081 {
12082 M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32,
12083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12084 },
12085 /* sha.l r1h,${Dsp-16-u16} */
12086 {
12087 M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32,
12088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12089 },
12090 /* sha.l r1h,${Dsp-16-u24} */
12091 {
12092 M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40,
12093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12094 },
12095 /* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
12096 {
12097 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24,
12098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12099 },
12100 /* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
12101 {
12102 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24,
12103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12104 },
12105 /* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12106 {
12107 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24,
12108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12109 },
12110 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12111 {
12112 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32,
12113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12114 },
12115 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12116 {
12117 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32,
12118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12119 },
12120 /* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12121 {
12122 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32,
12123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12124 },
12125 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12126 {
12127 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40,
12128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12129 },
12130 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12131 {
12132 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40,
12133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12134 },
12135 /* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12136 {
12137 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40,
12138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12139 },
12140 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12141 {
12142 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40,
12143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12144 },
12145 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12146 {
12147 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48,
12148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12149 },
12150 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12151 {
12152 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48,
12153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12154 },
12155 /* sha.w r1h,$Dst32RnUnprefixedHI */
12156 {
12157 M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12159 },
12160 /* sha.w r1h,$Dst32AnUnprefixedHI */
12161 {
12162 M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12164 },
12165 /* sha.w r1h,[$Dst32AnUnprefixed] */
12166 {
12167 M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12169 },
12170 /* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12171 {
12172 M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12174 },
12175 /* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12176 {
12177 M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12179 },
12180 /* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12181 {
12182 M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12184 },
12185 /* sha.w r1h,${Dsp-16-u8}[sb] */
12186 {
12187 M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12189 },
12190 /* sha.w r1h,${Dsp-16-u16}[sb] */
12191 {
12192 M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12194 },
12195 /* sha.w r1h,${Dsp-16-s8}[fb] */
12196 {
12197 M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12199 },
12200 /* sha.w r1h,${Dsp-16-s16}[fb] */
12201 {
12202 M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12204 },
12205 /* sha.w r1h,${Dsp-16-u16} */
12206 {
12207 M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12209 },
12210 /* sha.w r1h,${Dsp-16-u24} */
12211 {
12212 M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12214 },
12215 /* sha.b r1h,$Dst32RnUnprefixedQI */
12216 {
12217 M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12219 },
12220 /* sha.b r1h,$Dst32AnUnprefixedQI */
12221 {
12222 M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12224 },
12225 /* sha.b r1h,[$Dst32AnUnprefixed] */
12226 {
12227 M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12229 },
12230 /* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12231 {
12232 M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12234 },
12235 /* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12236 {
12237 M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12239 },
12240 /* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12241 {
12242 M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12244 },
12245 /* sha.b r1h,${Dsp-16-u8}[sb] */
12246 {
12247 M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12249 },
12250 /* sha.b r1h,${Dsp-16-u16}[sb] */
12251 {
12252 M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12254 },
12255 /* sha.b r1h,${Dsp-16-s8}[fb] */
12256 {
12257 M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12259 },
12260 /* sha.b r1h,${Dsp-16-s16}[fb] */
12261 {
12262 M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12264 },
12265 /* sha.b r1h,${Dsp-16-u16} */
12266 {
12267 M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12269 },
12270 /* sha.b r1h,${Dsp-16-u24} */
12271 {
12272 M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12274 },
12275 /* sha.w r1h,$Dst16RnHI */
12276 {
12277 M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16,
12278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12279 },
12280 /* sha.w r1h,$Dst16AnHI */
12281 {
12282 M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16,
12283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12284 },
12285 /* sha.w r1h,[$Dst16An] */
12286 {
12287 M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16,
12288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12289 },
12290 /* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
12291 {
12292 M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24,
12293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12294 },
12295 /* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
12296 {
12297 M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32,
12298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12299 },
12300 /* sha.w r1h,${Dsp-16-u8}[sb] */
12301 {
12302 M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24,
12303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12304 },
12305 /* sha.w r1h,${Dsp-16-u16}[sb] */
12306 {
12307 M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32,
12308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12309 },
12310 /* sha.w r1h,${Dsp-16-s8}[fb] */
12311 {
12312 M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24,
12313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12314 },
12315 /* sha.w r1h,${Dsp-16-u16} */
12316 {
12317 M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32,
12318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12319 },
12320 /* sha.b r1h,$Dst16RnQI */
12321 {
12322 M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16,
12323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12324 },
12325 /* sha.b r1h,$Dst16AnQI */
12326 {
12327 M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16,
12328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12329 },
12330 /* sha.b r1h,[$Dst16An] */
12331 {
12332 M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16,
12333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12334 },
12335 /* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
12336 {
12337 M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24,
12338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12339 },
12340 /* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
12341 {
12342 M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32,
12343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12344 },
12345 /* sha.b r1h,${Dsp-16-u8}[sb] */
12346 {
12347 M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24,
12348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12349 },
12350 /* sha.b r1h,${Dsp-16-u16}[sb] */
12351 {
12352 M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32,
12353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12354 },
12355 /* sha.b r1h,${Dsp-16-s8}[fb] */
12356 {
12357 M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24,
12358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12359 },
12360 /* sha.b r1h,${Dsp-16-u16} */
12361 {
12362 M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32,
12363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12364 },
12365 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
12366 {
12367 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12369 },
12370 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
12371 {
12372 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12374 },
12375 /* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12376 {
12377 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12379 },
12380 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12381 {
12382 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12384 },
12385 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12386 {
12387 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12389 },
12390 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12391 {
12392 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12394 },
12395 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12396 {
12397 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12399 },
12400 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12401 {
12402 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12404 },
12405 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12406 {
12407 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12409 },
12410 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12411 {
12412 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12414 },
12415 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12416 {
12417 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12419 },
12420 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12421 {
12422 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12424 },
12425 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
12426 {
12427 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12429 },
12430 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
12431 {
12432 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12434 },
12435 /* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12436 {
12437 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12439 },
12440 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12441 {
12442 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12444 },
12445 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12446 {
12447 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12449 },
12450 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12451 {
12452 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12454 },
12455 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12456 {
12457 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12459 },
12460 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12461 {
12462 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12464 },
12465 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12466 {
12467 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12469 },
12470 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12471 {
12472 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12474 },
12475 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12476 {
12477 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12479 },
12480 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12481 {
12482 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12484 },
12485 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
12486 {
12487 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16,
12488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12489 },
12490 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
12491 {
12492 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16,
12493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12494 },
12495 /* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
12496 {
12497 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16,
12498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12499 },
12500 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12501 {
12502 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24,
12503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12504 },
12505 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12506 {
12507 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32,
12508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12509 },
12510 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12511 {
12512 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24,
12513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12514 },
12515 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12516 {
12517 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32,
12518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12519 },
12520 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12521 {
12522 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24,
12523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12524 },
12525 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12526 {
12527 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32,
12528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12529 },
12530 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
12531 {
12532 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16,
12533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12534 },
12535 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
12536 {
12537 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16,
12538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12539 },
12540 /* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
12541 {
12542 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16,
12543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12544 },
12545 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12546 {
12547 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24,
12548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12549 },
12550 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12551 {
12552 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32,
12553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12554 },
12555 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12556 {
12557 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24,
12558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12559 },
12560 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12561 {
12562 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32,
12563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12564 },
12565 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12566 {
12567 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24,
12568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12569 },
12570 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12571 {
12572 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32,
12573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12574 },
12575 /* sc${sccond32} $Dst32RnUnprefixedHI */
12576 {
12577 M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16,
12578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12579 },
12580 /* sc${sccond32} $Dst32AnUnprefixedHI */
12581 {
12582 M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16,
12583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12584 },
12585 /* sc${sccond32} [$Dst32AnUnprefixed] */
12586 {
12587 M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16,
12588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12589 },
12590 /* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
12591 {
12592 M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24,
12593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12594 },
12595 /* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
12596 {
12597 M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32,
12598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12599 },
12600 /* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
12601 {
12602 M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40,
12603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12604 },
12605 /* sc${sccond32} ${Dsp-16-u8}[sb] */
12606 {
12607 M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24,
12608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12609 },
12610 /* sc${sccond32} ${Dsp-16-u16}[sb] */
12611 {
12612 M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32,
12613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12614 },
12615 /* sc${sccond32} ${Dsp-16-s8}[fb] */
12616 {
12617 M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24,
12618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12619 },
12620 /* sc${sccond32} ${Dsp-16-s16}[fb] */
12621 {
12622 M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32,
12623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12624 },
12625 /* sc${sccond32} ${Dsp-16-u16} */
12626 {
12627 M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32,
12628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12629 },
12630 /* sc${sccond32} ${Dsp-16-u24} */
12631 {
12632 M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
12633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12634 },
12635 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12636 {
12637 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
12638 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12639 },
12640 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12641 {
12642 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
12643 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12644 },
12645 /* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12646 {
12647 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
12648 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12649 },
12650 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12651 {
12652 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
12653 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12654 },
12655 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12656 {
12657 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
12658 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12659 },
12660 /* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
12661 {
12662 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
12663 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12664 },
12665 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
12666 {
12667 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
12668 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12669 },
12670 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12671 {
12672 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
12673 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12674 },
12675 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
12676 {
12677 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
12678 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12679 },
12680 /* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
12681 {
12682 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
12683 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12684 },
12685 /* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
12686 {
12687 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
12688 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12689 },
12690 /* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
12691 {
12692 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
12693 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12694 },
12695 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12696 {
12697 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
12698 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12699 },
12700 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12701 {
12702 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
12703 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12704 },
12705 /* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12706 {
12707 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
12708 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12709 },
12710 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12711 {
12712 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
12713 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12714 },
12715 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12716 {
12717 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
12718 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12719 },
12720 /* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
12721 {
12722 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
12723 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12724 },
12725 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
12726 {
12727 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
12728 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12729 },
12730 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12731 {
12732 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
12733 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12734 },
12735 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
12736 {
12737 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
12738 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12739 },
12740 /* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
12741 {
12742 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
12743 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12744 },
12745 /* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
12746 {
12747 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
12748 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12749 },
12750 /* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
12751 {
12752 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
12753 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12754 },
12755 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12756 {
12757 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
12758 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12759 },
12760 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12761 {
12762 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
12763 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12764 },
12765 /* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12766 {
12767 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
12768 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12769 },
12770 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12771 {
12772 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
12773 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12774 },
12775 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12776 {
12777 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
12778 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12779 },
12780 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
12781 {
12782 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
12783 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12784 },
12785 /* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
12786 {
12787 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
12788 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12789 },
12790 /* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
12791 {
12792 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
12793 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12794 },
12795 /* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
12796 {
12797 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
12798 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12799 },
12800 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12801 {
12802 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
12803 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12804 },
12805 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12806 {
12807 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
12808 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12809 },
12810 /* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12811 {
12812 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
12813 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12814 },
12815 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12816 {
12817 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
12818 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12819 },
12820 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12821 {
12822 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
12823 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12824 },
12825 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
12826 {
12827 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
12828 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12829 },
12830 /* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
12831 {
12832 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
12833 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12834 },
12835 /* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
12836 {
12837 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
12838 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12839 },
12840 /* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
12841 {
12842 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
12843 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12844 },
12845 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
12846 {
12847 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12849 },
12850 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
12851 {
12852 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12854 },
12855 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
12856 {
12857 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12859 },
12860 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
12861 {
12862 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12864 },
12865 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
12866 {
12867 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12869 },
12870 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
12871 {
12872 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12874 },
12875 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
12876 {
12877 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12879 },
12880 /* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
12881 {
12882 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12884 },
12885 /* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
12886 {
12887 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12889 },
12890 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
12891 {
12892 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12894 },
12895 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12896 {
12897 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12899 },
12900 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12901 {
12902 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12904 },
12905 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
12906 {
12907 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12909 },
12910 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12911 {
12912 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12914 },
12915 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12916 {
12917 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12919 },
12920 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
12921 {
12922 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12924 },
12925 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12926 {
12927 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12929 },
12930 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12931 {
12932 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12934 },
12935 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
12936 {
12937 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12939 },
12940 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
12941 {
12942 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12944 },
12945 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
12946 {
12947 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12949 },
12950 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
12951 {
12952 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12954 },
12955 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
12956 {
12957 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12959 },
12960 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
12961 {
12962 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12964 },
12965 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
12966 {
12967 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12969 },
12970 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
12971 {
12972 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12974 },
12975 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
12976 {
12977 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12979 },
12980 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
12981 {
12982 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12984 },
12985 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
12986 {
12987 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12989 },
12990 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
12991 {
12992 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12994 },
12995 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
12996 {
12997 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
12998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12999 },
13000 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13001 {
13002 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13004 },
13005 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13006 {
13007 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13009 },
13010 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13011 {
13012 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13014 },
13015 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13016 {
13017 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13019 },
13020 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13021 {
13022 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13024 },
13025 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13026 {
13027 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13029 },
13030 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
13031 {
13032 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13034 },
13035 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
13036 {
13037 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13039 },
13040 /* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
13041 {
13042 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13044 },
13045 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13046 {
13047 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13049 },
13050 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
13051 {
13052 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13054 },
13055 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
13056 {
13057 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13059 },
13060 /* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
13061 {
13062 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13064 },
13065 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13066 {
13067 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13069 },
13070 /* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13071 {
13072 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13074 },
13075 /* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13076 {
13077 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13079 },
13080 /* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13081 {
13082 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13084 },
13085 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13086 {
13087 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13089 },
13090 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13091 {
13092 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13094 },
13095 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13096 {
13097 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13099 },
13100 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13101 {
13102 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13104 },
13105 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13106 {
13107 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13109 },
13110 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13111 {
13112 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13114 },
13115 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13116 {
13117 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13119 },
13120 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13121 {
13122 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13124 },
13125 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13126 {
13127 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13129 },
13130 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13131 {
13132 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13134 },
13135 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13136 {
13137 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13139 },
13140 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13141 {
13142 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13144 },
13145 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13146 {
13147 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13149 },
13150 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13151 {
13152 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13154 },
13155 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13156 {
13157 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13159 },
13160 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13161 {
13162 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13164 },
13165 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13166 {
13167 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13169 },
13170 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13171 {
13172 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13174 },
13175 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13176 {
13177 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13179 },
13180 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13181 {
13182 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13184 },
13185 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13186 {
13187 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13189 },
13190 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13191 {
13192 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13194 },
13195 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13196 {
13197 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13199 },
13200 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13201 {
13202 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13204 },
13205 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13206 {
13207 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13209 },
13210 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13211 {
13212 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13214 },
13215 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13216 {
13217 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13219 },
13220 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13221 {
13222 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13224 },
13225 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13226 {
13227 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13229 },
13230 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13231 {
13232 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13234 },
13235 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13236 {
13237 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13239 },
13240 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
13241 {
13242 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13244 },
13245 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13246 {
13247 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13249 },
13250 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13251 {
13252 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13254 },
13255 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13256 {
13257 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13259 },
13260 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
13261 {
13262 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13264 },
13265 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13266 {
13267 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13269 },
13270 /* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
13271 {
13272 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13274 },
13275 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13276 {
13277 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13279 },
13280 /* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
13281 {
13282 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13284 },
13285 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13286 {
13287 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13289 },
13290 /* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
13291 {
13292 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13294 },
13295 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
13296 {
13297 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13299 },
13300 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
13301 {
13302 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13304 },
13305 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
13306 {
13307 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13309 },
13310 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
13311 {
13312 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13314 },
13315 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
13316 {
13317 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13319 },
13320 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
13321 {
13322 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13324 },
13325 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
13326 {
13327 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13329 },
13330 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
13331 {
13332 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13334 },
13335 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
13336 {
13337 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13339 },
13340 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
13341 {
13342 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13344 },
13345 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
13346 {
13347 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13349 },
13350 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
13351 {
13352 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13354 },
13355 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
13356 {
13357 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13359 },
13360 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
13361 {
13362 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13364 },
13365 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
13366 {
13367 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13369 },
13370 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
13371 {
13372 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13374 },
13375 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
13376 {
13377 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13379 },
13380 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
13381 {
13382 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13384 },
13385 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
13386 {
13387 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13389 },
13390 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
13391 {
13392 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13394 },
13395 /* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
13396 {
13397 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13399 },
13400 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
13401 {
13402 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13404 },
13405 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
13406 {
13407 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13409 },
13410 /* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
13411 {
13412 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13414 },
13415 /* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
13416 {
13417 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13419 },
13420 /* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
13421 {
13422 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13424 },
13425 /* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
13426 {
13427 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13429 },
13430 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13431 {
13432 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13434 },
13435 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13436 {
13437 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13439 },
13440 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
13441 {
13442 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13444 },
13445 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13446 {
13447 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13449 },
13450 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13451 {
13452 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13454 },
13455 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
13456 {
13457 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13459 },
13460 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13461 {
13462 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13464 },
13465 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13466 {
13467 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13469 },
13470 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
13471 {
13472 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13474 },
13475 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
13476 {
13477 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13479 },
13480 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
13481 {
13482 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13484 },
13485 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
13486 {
13487 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13489 },
13490 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
13491 {
13492 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13494 },
13495 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
13496 {
13497 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13499 },
13500 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
13501 {
13502 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13504 },
13505 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
13506 {
13507 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13509 },
13510 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
13511 {
13512 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13514 },
13515 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
13516 {
13517 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13519 },
13520 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
13521 {
13522 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13524 },
13525 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
13526 {
13527 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13529 },
13530 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
13531 {
13532 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13534 },
13535 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
13536 {
13537 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13539 },
13540 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
13541 {
13542 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13544 },
13545 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
13546 {
13547 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13549 },
13550 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
13551 {
13552 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13554 },
13555 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
13556 {
13557 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13559 },
13560 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
13561 {
13562 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13564 },
13565 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13566 {
13567 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13569 },
13570 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
13571 {
13572 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13574 },
13575 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
13576 {
13577 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13579 },
13580 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13581 {
13582 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13584 },
13585 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
13586 {
13587 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13589 },
13590 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
13591 {
13592 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13594 },
13595 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13596 {
13597 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13599 },
13600 /* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
13601 {
13602 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13604 },
13605 /* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
13606 {
13607 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13609 },
13610 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
13611 {
13612 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13614 },
13615 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13616 {
13617 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13619 },
13620 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13621 {
13622 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13624 },
13625 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
13626 {
13627 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13629 },
13630 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13631 {
13632 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13634 },
13635 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13636 {
13637 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13639 },
13640 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
13641 {
13642 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13644 },
13645 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13646 {
13647 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13649 },
13650 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13651 {
13652 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13654 },
13655 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
13656 {
13657 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13659 },
13660 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
13661 {
13662 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13664 },
13665 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
13666 {
13667 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13669 },
13670 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
13671 {
13672 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13674 },
13675 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
13676 {
13677 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13679 },
13680 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
13681 {
13682 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13684 },
13685 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
13686 {
13687 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13689 },
13690 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
13691 {
13692 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13694 },
13695 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
13696 {
13697 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13699 },
13700 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
13701 {
13702 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13704 },
13705 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
13706 {
13707 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13709 },
13710 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13711 {
13712 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13714 },
13715 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13716 {
13717 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13719 },
13720 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13721 {
13722 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13724 },
13725 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13726 {
13727 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13729 },
13730 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13731 {
13732 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13734 },
13735 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13736 {
13737 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13739 },
13740 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13741 {
13742 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13744 },
13745 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13746 {
13747 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13749 },
13750 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
13751 {
13752 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13754 },
13755 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
13756 {
13757 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13759 },
13760 /* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
13761 {
13762 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13764 },
13765 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13766 {
13767 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13769 },
13770 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
13771 {
13772 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13774 },
13775 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
13776 {
13777 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13779 },
13780 /* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
13781 {
13782 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13784 },
13785 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13786 {
13787 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13789 },
13790 /* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13791 {
13792 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13794 },
13795 /* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13796 {
13797 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13799 },
13800 /* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13801 {
13802 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13804 },
13805 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13806 {
13807 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13809 },
13810 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13811 {
13812 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13814 },
13815 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13816 {
13817 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13819 },
13820 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13821 {
13822 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13824 },
13825 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13826 {
13827 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13829 },
13830 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13831 {
13832 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13834 },
13835 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13836 {
13837 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13839 },
13840 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13841 {
13842 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13844 },
13845 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13846 {
13847 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13849 },
13850 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13851 {
13852 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13854 },
13855 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13856 {
13857 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13859 },
13860 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13861 {
13862 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13864 },
13865 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13866 {
13867 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13869 },
13870 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13871 {
13872 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13874 },
13875 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13876 {
13877 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13879 },
13880 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13881 {
13882 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13884 },
13885 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13886 {
13887 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13889 },
13890 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13891 {
13892 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13894 },
13895 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13896 {
13897 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13899 },
13900 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13901 {
13902 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13904 },
13905 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13906 {
13907 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13909 },
13910 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13911 {
13912 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13914 },
13915 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13916 {
13917 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13919 },
13920 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13921 {
13922 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13924 },
13925 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13926 {
13927 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13929 },
13930 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13931 {
13932 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13934 },
13935 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13936 {
13937 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13939 },
13940 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13941 {
13942 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13944 },
13945 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13946 {
13947 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13949 },
13950 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13951 {
13952 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13954 },
13955 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13956 {
13957 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13959 },
13960 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
13961 {
13962 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13964 },
13965 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13966 {
13967 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13969 },
13970 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13971 {
13972 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13974 },
13975 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13976 {
13977 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13979 },
13980 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
13981 {
13982 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13984 },
13985 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13986 {
13987 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
13988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13989 },
13990 /* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
13991 {
13992 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
13993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13994 },
13995 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13996 {
13997 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
13998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13999 },
14000 /* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
14001 {
14002 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
14003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14004 },
14005 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
14006 {
14007 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
14008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14009 },
14010 /* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
14011 {
14012 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
14013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14014 },
14015 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
14016 {
14017 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14019 },
14020 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
14021 {
14022 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14024 },
14025 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
14026 {
14027 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14029 },
14030 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
14031 {
14032 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14034 },
14035 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
14036 {
14037 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14039 },
14040 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
14041 {
14042 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14044 },
14045 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
14046 {
14047 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14049 },
14050 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
14051 {
14052 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14054 },
14055 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
14056 {
14057 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14059 },
14060 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
14061 {
14062 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14064 },
14065 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
14066 {
14067 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14069 },
14070 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
14071 {
14072 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14074 },
14075 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
14076 {
14077 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14079 },
14080 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
14081 {
14082 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14084 },
14085 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
14086 {
14087 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14089 },
14090 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
14091 {
14092 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14094 },
14095 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
14096 {
14097 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14099 },
14100 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
14101 {
14102 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14104 },
14105 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
14106 {
14107 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14109 },
14110 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
14111 {
14112 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14114 },
14115 /* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
14116 {
14117 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14119 },
14120 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
14121 {
14122 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14124 },
14125 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
14126 {
14127 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14129 },
14130 /* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
14131 {
14132 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14134 },
14135 /* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
14136 {
14137 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14139 },
14140 /* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
14141 {
14142 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14144 },
14145 /* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
14146 {
14147 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14149 },
14150 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14151 {
14152 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14154 },
14155 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14156 {
14157 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14159 },
14160 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
14161 {
14162 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14164 },
14165 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14166 {
14167 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14169 },
14170 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14171 {
14172 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14174 },
14175 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
14176 {
14177 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14179 },
14180 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14181 {
14182 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14184 },
14185 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14186 {
14187 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14189 },
14190 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
14191 {
14192 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14194 },
14195 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
14196 {
14197 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14199 },
14200 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
14201 {
14202 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14204 },
14205 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
14206 {
14207 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14209 },
14210 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
14211 {
14212 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14214 },
14215 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
14216 {
14217 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14219 },
14220 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
14221 {
14222 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14224 },
14225 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
14226 {
14227 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14229 },
14230 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
14231 {
14232 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14234 },
14235 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
14236 {
14237 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14239 },
14240 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
14241 {
14242 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14244 },
14245 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
14246 {
14247 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14249 },
14250 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
14251 {
14252 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14254 },
14255 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
14256 {
14257 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14259 },
14260 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
14261 {
14262 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14264 },
14265 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
14266 {
14267 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14269 },
14270 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
14271 {
14272 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14274 },
14275 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
14276 {
14277 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14279 },
14280 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
14281 {
14282 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14284 },
14285 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
14286 {
14287 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14289 },
14290 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
14291 {
14292 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14294 },
14295 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
14296 {
14297 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14299 },
14300 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
14301 {
14302 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14304 },
14305 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
14306 {
14307 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14309 },
14310 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
14311 {
14312 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14314 },
14315 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14316 {
14317 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14319 },
14320 /* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14321 {
14322 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14324 },
14325 /* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14326 {
14327 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14329 },
14330 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14331 {
14332 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14334 },
14335 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14336 {
14337 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14339 },
14340 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14341 {
14342 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14344 },
14345 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14346 {
14347 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14349 },
14350 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14351 {
14352 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14354 },
14355 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14356 {
14357 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14359 },
14360 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14361 {
14362 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14364 },
14365 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14366 {
14367 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14369 },
14370 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14371 {
14372 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14374 },
14375 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14376 {
14377 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14379 },
14380 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14381 {
14382 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14384 },
14385 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14386 {
14387 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14389 },
14390 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14391 {
14392 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14394 },
14395 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14396 {
14397 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14399 },
14400 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14401 {
14402 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14404 },
14405 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14406 {
14407 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14409 },
14410 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14411 {
14412 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14414 },
14415 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14416 {
14417 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14419 },
14420 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
14421 {
14422 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14424 },
14425 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
14426 {
14427 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14429 },
14430 /* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
14431 {
14432 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14434 },
14435 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
14436 {
14437 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14439 },
14440 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
14441 {
14442 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14444 },
14445 /* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
14446 {
14447 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32,
14448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14449 },
14450 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14451 {
14452 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14454 },
14455 /* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14456 {
14457 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14459 },
14460 /* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
14461 {
14462 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32,
14463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14464 },
14465 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14466 {
14467 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14469 },
14470 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14471 {
14472 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14474 },
14475 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14476 {
14477 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14479 },
14480 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14481 {
14482 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14484 },
14485 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14486 {
14487 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14489 },
14490 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14491 {
14492 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14494 },
14495 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14496 {
14497 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14499 },
14500 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14501 {
14502 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14504 },
14505 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14506 {
14507 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14509 },
14510 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14511 {
14512 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14514 },
14515 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14516 {
14517 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14519 },
14520 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14521 {
14522 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14524 },
14525 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14526 {
14527 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14529 },
14530 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14531 {
14532 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14534 },
14535 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14536 {
14537 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14539 },
14540 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14541 {
14542 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14544 },
14545 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14546 {
14547 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14549 },
14550 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
14551 {
14552 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14554 },
14555 /* sbb.w${X} $Src16RnHI,$Dst16RnHI */
14556 {
14557 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14559 },
14560 /* sbb.w${X} $Src16AnHI,$Dst16RnHI */
14561 {
14562 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14564 },
14565 /* sbb.w${X} [$Src16An],$Dst16RnHI */
14566 {
14567 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14569 },
14570 /* sbb.w${X} $Src16RnHI,$Dst16AnHI */
14571 {
14572 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14574 },
14575 /* sbb.w${X} $Src16AnHI,$Dst16AnHI */
14576 {
14577 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14579 },
14580 /* sbb.w${X} [$Src16An],$Dst16AnHI */
14581 {
14582 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16,
14583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14584 },
14585 /* sbb.w${X} $Src16RnHI,[$Dst16An] */
14586 {
14587 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14589 },
14590 /* sbb.w${X} $Src16AnHI,[$Dst16An] */
14591 {
14592 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14594 },
14595 /* sbb.w${X} [$Src16An],[$Dst16An] */
14596 {
14597 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16,
14598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14599 },
14600 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
14601 {
14602 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14604 },
14605 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
14606 {
14607 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14609 },
14610 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
14611 {
14612 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14614 },
14615 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
14616 {
14617 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14619 },
14620 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
14621 {
14622 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14624 },
14625 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
14626 {
14627 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14629 },
14630 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
14631 {
14632 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14634 },
14635 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
14636 {
14637 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14639 },
14640 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
14641 {
14642 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14644 },
14645 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
14646 {
14647 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14649 },
14650 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
14651 {
14652 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14654 },
14655 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
14656 {
14657 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14659 },
14660 /* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
14661 {
14662 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14664 },
14665 /* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
14666 {
14667 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14669 },
14670 /* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
14671 {
14672 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14674 },
14675 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
14676 {
14677 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14679 },
14680 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
14681 {
14682 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14684 },
14685 /* sbb.w${X} [$Src16An],${Dsp-16-u16} */
14686 {
14687 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14689 },
14690 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
14691 {
14692 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14694 },
14695 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
14696 {
14697 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14699 },
14700 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
14701 {
14702 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14704 },
14705 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
14706 {
14707 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14709 },
14710 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
14711 {
14712 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14714 },
14715 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
14716 {
14717 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14719 },
14720 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14721 {
14722 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14724 },
14725 /* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14726 {
14727 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14729 },
14730 /* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14731 {
14732 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14734 },
14735 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14736 {
14737 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14739 },
14740 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14741 {
14742 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14744 },
14745 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14746 {
14747 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14749 },
14750 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14751 {
14752 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14754 },
14755 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14756 {
14757 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14759 },
14760 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14761 {
14762 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14764 },
14765 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14766 {
14767 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14769 },
14770 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14771 {
14772 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14774 },
14775 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14776 {
14777 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14779 },
14780 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14781 {
14782 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14784 },
14785 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14786 {
14787 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14789 },
14790 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14791 {
14792 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14794 },
14795 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14796 {
14797 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14799 },
14800 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14801 {
14802 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14804 },
14805 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14806 {
14807 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14809 },
14810 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14811 {
14812 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14814 },
14815 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14816 {
14817 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14819 },
14820 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14821 {
14822 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14824 },
14825 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
14826 {
14827 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14829 },
14830 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
14831 {
14832 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14834 },
14835 /* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
14836 {
14837 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14839 },
14840 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
14841 {
14842 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14844 },
14845 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
14846 {
14847 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14849 },
14850 /* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
14851 {
14852 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32,
14853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14854 },
14855 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14856 {
14857 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14859 },
14860 /* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14861 {
14862 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14864 },
14865 /* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
14866 {
14867 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32,
14868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14869 },
14870 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14871 {
14872 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14874 },
14875 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14876 {
14877 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14879 },
14880 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14881 {
14882 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14884 },
14885 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14886 {
14887 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14889 },
14890 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14891 {
14892 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14894 },
14895 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14896 {
14897 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14899 },
14900 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14901 {
14902 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14904 },
14905 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14906 {
14907 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14909 },
14910 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14911 {
14912 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14914 },
14915 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14916 {
14917 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14919 },
14920 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14921 {
14922 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14924 },
14925 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14926 {
14927 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14929 },
14930 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14931 {
14932 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14934 },
14935 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14936 {
14937 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14939 },
14940 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14941 {
14942 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14944 },
14945 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14946 {
14947 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14949 },
14950 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14951 {
14952 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14954 },
14955 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
14956 {
14957 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14959 },
14960 /* sbb.b${X} $Src16RnQI,$Dst16RnQI */
14961 {
14962 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14964 },
14965 /* sbb.b${X} $Src16AnQI,$Dst16RnQI */
14966 {
14967 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14969 },
14970 /* sbb.b${X} [$Src16An],$Dst16RnQI */
14971 {
14972 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14974 },
14975 /* sbb.b${X} $Src16RnQI,$Dst16AnQI */
14976 {
14977 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
14978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14979 },
14980 /* sbb.b${X} $Src16AnQI,$Dst16AnQI */
14981 {
14982 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
14983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14984 },
14985 /* sbb.b${X} [$Src16An],$Dst16AnQI */
14986 {
14987 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16,
14988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14989 },
14990 /* sbb.b${X} $Src16RnQI,[$Dst16An] */
14991 {
14992 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
14993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14994 },
14995 /* sbb.b${X} $Src16AnQI,[$Dst16An] */
14996 {
14997 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
14998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14999 },
15000 /* sbb.b${X} [$Src16An],[$Dst16An] */
15001 {
15002 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16,
15003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15004 },
15005 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
15006 {
15007 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15009 },
15010 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
15011 {
15012 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15014 },
15015 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
15016 {
15017 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15019 },
15020 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
15021 {
15022 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15024 },
15025 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
15026 {
15027 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15029 },
15030 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
15031 {
15032 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15034 },
15035 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
15036 {
15037 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15039 },
15040 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
15041 {
15042 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15044 },
15045 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
15046 {
15047 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15049 },
15050 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
15051 {
15052 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15054 },
15055 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
15056 {
15057 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15059 },
15060 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
15061 {
15062 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15064 },
15065 /* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
15066 {
15067 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15069 },
15070 /* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
15071 {
15072 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15074 },
15075 /* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
15076 {
15077 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15079 },
15080 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
15081 {
15082 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15084 },
15085 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
15086 {
15087 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15089 },
15090 /* sbb.b${X} [$Src16An],${Dsp-16-u16} */
15091 {
15092 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15094 },
15095 /* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
15096 {
15097 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
15098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15099 },
15100 /* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
15101 {
15102 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
15103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15104 },
15105 /* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
15106 {
15107 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
15108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15109 },
15110 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15111 {
15112 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48,
15113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15114 },
15115 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
15116 {
15117 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48,
15118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15119 },
15120 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
15121 {
15122 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48,
15123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15124 },
15125 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15126 {
15127 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56,
15128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15129 },
15130 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
15131 {
15132 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56,
15133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15134 },
15135 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
15136 {
15137 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56,
15138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15139 },
15140 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
15141 {
15142 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56,
15143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15144 },
15145 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15146 {
15147 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64,
15148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15149 },
15150 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
15151 {
15152 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64,
15153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15154 },
15155 /* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
15156 {
15157 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
15158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15159 },
15160 /* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
15161 {
15162 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
15163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15164 },
15165 /* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
15166 {
15167 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
15168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15169 },
15170 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15171 {
15172 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40,
15173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15174 },
15175 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
15176 {
15177 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40,
15178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15179 },
15180 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
15181 {
15182 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40,
15183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15184 },
15185 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15186 {
15187 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48,
15188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15189 },
15190 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
15191 {
15192 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48,
15193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15194 },
15195 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
15196 {
15197 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48,
15198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15199 },
15200 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
15201 {
15202 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48,
15203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15204 },
15205 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15206 {
15207 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56,
15208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15209 },
15210 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
15211 {
15212 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56,
15213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15214 },
15215 /* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
15216 {
15217 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32,
15218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15219 },
15220 /* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
15221 {
15222 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32,
15223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15224 },
15225 /* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
15226 {
15227 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32,
15228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15229 },
15230 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
15231 {
15232 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40,
15233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15234 },
15235 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
15236 {
15237 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40,
15238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15239 },
15240 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
15241 {
15242 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40,
15243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15244 },
15245 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
15246 {
15247 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48,
15248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15249 },
15250 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
15251 {
15252 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48,
15253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15254 },
15255 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
15256 {
15257 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48,
15258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15259 },
15260 /* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
15261 {
15262 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24,
15263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15264 },
15265 /* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
15266 {
15267 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24,
15268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15269 },
15270 /* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
15271 {
15272 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24,
15273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15274 },
15275 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
15276 {
15277 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32,
15278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15279 },
15280 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
15281 {
15282 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32,
15283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15284 },
15285 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
15286 {
15287 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32,
15288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15289 },
15290 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
15291 {
15292 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40,
15293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15294 },
15295 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
15296 {
15297 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40,
15298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15299 },
15300 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
15301 {
15302 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
15303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15304 },
15305 /* rot.w r1h,$Dst32RnUnprefixedHI */
15306 {
15307 M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
15308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15309 },
15310 /* rot.w r1h,$Dst32AnUnprefixedHI */
15311 {
15312 M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
15313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15314 },
15315 /* rot.w r1h,[$Dst32AnUnprefixed] */
15316 {
15317 M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
15318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15319 },
15320 /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15321 {
15322 M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
15323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15324 },
15325 /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15326 {
15327 M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
15328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15329 },
15330 /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15331 {
15332 M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
15333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15334 },
15335 /* rot.w r1h,${Dsp-16-u8}[sb] */
15336 {
15337 M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
15338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15339 },
15340 /* rot.w r1h,${Dsp-16-u16}[sb] */
15341 {
15342 M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
15343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15344 },
15345 /* rot.w r1h,${Dsp-16-s8}[fb] */
15346 {
15347 M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
15348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15349 },
15350 /* rot.w r1h,${Dsp-16-s16}[fb] */
15351 {
15352 M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
15353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15354 },
15355 /* rot.w r1h,${Dsp-16-u16} */
15356 {
15357 M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
15358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15359 },
15360 /* rot.w r1h,${Dsp-16-u24} */
15361 {
15362 M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
15363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15364 },
15365 /* rot.b r1h,$Dst32RnUnprefixedQI */
15366 {
15367 M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
15368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15369 },
15370 /* rot.b r1h,$Dst32AnUnprefixedQI */
15371 {
15372 M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
15373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15374 },
15375 /* rot.b r1h,[$Dst32AnUnprefixed] */
15376 {
15377 M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
15378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15379 },
15380 /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15381 {
15382 M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
15383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15384 },
15385 /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15386 {
15387 M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
15388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15389 },
15390 /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15391 {
15392 M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
15393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15394 },
15395 /* rot.b r1h,${Dsp-16-u8}[sb] */
15396 {
15397 M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
15398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15399 },
15400 /* rot.b r1h,${Dsp-16-u16}[sb] */
15401 {
15402 M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
15403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15404 },
15405 /* rot.b r1h,${Dsp-16-s8}[fb] */
15406 {
15407 M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
15408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15409 },
15410 /* rot.b r1h,${Dsp-16-s16}[fb] */
15411 {
15412 M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
15413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15414 },
15415 /* rot.b r1h,${Dsp-16-u16} */
15416 {
15417 M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
15418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15419 },
15420 /* rot.b r1h,${Dsp-16-u24} */
15421 {
15422 M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
15423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15424 },
15425 /* rot.w r1h,$Dst16RnHI */
15426 {
15427 M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16,
15428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15429 },
15430 /* rot.w r1h,$Dst16AnHI */
15431 {
15432 M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16,
15433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15434 },
15435 /* rot.w r1h,[$Dst16An] */
15436 {
15437 M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16,
15438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15439 },
15440 /* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
15441 {
15442 M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24,
15443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15444 },
15445 /* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
15446 {
15447 M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32,
15448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15449 },
15450 /* rot.w r1h,${Dsp-16-u8}[sb] */
15451 {
15452 M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24,
15453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15454 },
15455 /* rot.w r1h,${Dsp-16-u16}[sb] */
15456 {
15457 M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32,
15458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15459 },
15460 /* rot.w r1h,${Dsp-16-s8}[fb] */
15461 {
15462 M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24,
15463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15464 },
15465 /* rot.w r1h,${Dsp-16-u16} */
15466 {
15467 M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
15468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15469 },
15470 /* rot.b r1h,$Dst16RnQI */
15471 {
15472 M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16,
15473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15474 },
15475 /* rot.b r1h,$Dst16AnQI */
15476 {
15477 M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16,
15478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15479 },
15480 /* rot.b r1h,[$Dst16An] */
15481 {
15482 M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16,
15483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15484 },
15485 /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
15486 {
15487 M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24,
15488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15489 },
15490 /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
15491 {
15492 M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32,
15493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15494 },
15495 /* rot.b r1h,${Dsp-16-u8}[sb] */
15496 {
15497 M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24,
15498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15499 },
15500 /* rot.b r1h,${Dsp-16-u16}[sb] */
15501 {
15502 M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32,
15503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15504 },
15505 /* rot.b r1h,${Dsp-16-s8}[fb] */
15506 {
15507 M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24,
15508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15509 },
15510 /* rot.b r1h,${Dsp-16-u16} */
15511 {
15512 M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32,
15513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15514 },
15515 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
15516 {
15517 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
15518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15519 },
15520 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
15521 {
15522 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
15523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15524 },
15525 /* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15526 {
15527 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
15528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15529 },
15530 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15531 {
15532 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
15533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15534 },
15535 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15536 {
15537 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
15538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15539 },
15540 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15541 {
15542 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
15543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15544 },
15545 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15546 {
15547 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
15548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15549 },
15550 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15551 {
15552 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
15553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15554 },
15555 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15556 {
15557 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
15558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15559 },
15560 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15561 {
15562 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
15563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15564 },
15565 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15566 {
15567 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
15568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15569 },
15570 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15571 {
15572 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
15573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15574 },
15575 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
15576 {
15577 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
15578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15579 },
15580 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
15581 {
15582 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
15583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15584 },
15585 /* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15586 {
15587 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
15588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15589 },
15590 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15591 {
15592 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
15593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15594 },
15595 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15596 {
15597 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
15598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15599 },
15600 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15601 {
15602 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
15603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15604 },
15605 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15606 {
15607 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
15608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15609 },
15610 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15611 {
15612 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
15613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15614 },
15615 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15616 {
15617 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
15618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15619 },
15620 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15621 {
15622 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
15623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15624 },
15625 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15626 {
15627 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
15628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15629 },
15630 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15631 {
15632 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
15633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15634 },
15635 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
15636 {
15637 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16,
15638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15639 },
15640 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
15641 {
15642 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16,
15643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15644 },
15645 /* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
15646 {
15647 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16,
15648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15649 },
15650 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15651 {
15652 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24,
15653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15654 },
15655 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15656 {
15657 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32,
15658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15659 },
15660 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15661 {
15662 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24,
15663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15664 },
15665 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15666 {
15667 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32,
15668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15669 },
15670 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15671 {
15672 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24,
15673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15674 },
15675 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15676 {
15677 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32,
15678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15679 },
15680 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
15681 {
15682 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16,
15683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15684 },
15685 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
15686 {
15687 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16,
15688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15689 },
15690 /* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
15691 {
15692 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16,
15693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15694 },
15695 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15696 {
15697 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24,
15698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15699 },
15700 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15701 {
15702 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32,
15703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15704 },
15705 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15706 {
15707 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24,
15708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15709 },
15710 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15711 {
15712 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32,
15713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15714 },
15715 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15716 {
15717 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24,
15718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15719 },
15720 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15721 {
15722 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32,
15723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15724 },
15725 /* rorc.w $Dst32RnUnprefixedHI */
15726 {
15727 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16,
15728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15729 },
15730 /* rorc.w $Dst32AnUnprefixedHI */
15731 {
15732 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16,
15733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15734 },
15735 /* rorc.w [$Dst32AnUnprefixed] */
15736 {
15737 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16,
15738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15739 },
15740 /* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15741 {
15742 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24,
15743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15744 },
15745 /* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15746 {
15747 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32,
15748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15749 },
15750 /* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15751 {
15752 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40,
15753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15754 },
15755 /* rorc.w ${Dsp-16-u8}[sb] */
15756 {
15757 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24,
15758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15759 },
15760 /* rorc.w ${Dsp-16-u16}[sb] */
15761 {
15762 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32,
15763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15764 },
15765 /* rorc.w ${Dsp-16-s8}[fb] */
15766 {
15767 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24,
15768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15769 },
15770 /* rorc.w ${Dsp-16-s16}[fb] */
15771 {
15772 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32,
15773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15774 },
15775 /* rorc.w ${Dsp-16-u16} */
15776 {
15777 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32,
15778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15779 },
15780 /* rorc.w ${Dsp-16-u24} */
15781 {
15782 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40,
15783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15784 },
15785 /* rorc.b $Dst32RnUnprefixedQI */
15786 {
15787 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16,
15788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15789 },
15790 /* rorc.b $Dst32AnUnprefixedQI */
15791 {
15792 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16,
15793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15794 },
15795 /* rorc.b [$Dst32AnUnprefixed] */
15796 {
15797 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16,
15798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15799 },
15800 /* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15801 {
15802 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24,
15803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15804 },
15805 /* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15806 {
15807 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32,
15808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15809 },
15810 /* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15811 {
15812 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40,
15813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15814 },
15815 /* rorc.b ${Dsp-16-u8}[sb] */
15816 {
15817 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24,
15818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15819 },
15820 /* rorc.b ${Dsp-16-u16}[sb] */
15821 {
15822 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32,
15823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15824 },
15825 /* rorc.b ${Dsp-16-s8}[fb] */
15826 {
15827 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24,
15828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15829 },
15830 /* rorc.b ${Dsp-16-s16}[fb] */
15831 {
15832 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32,
15833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15834 },
15835 /* rorc.b ${Dsp-16-u16} */
15836 {
15837 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32,
15838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15839 },
15840 /* rorc.b ${Dsp-16-u24} */
15841 {
15842 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40,
15843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15844 },
15845 /* rorc.w $Dst16RnHI */
15846 {
15847 M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16,
15848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15849 },
15850 /* rorc.w $Dst16AnHI */
15851 {
15852 M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16,
15853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15854 },
15855 /* rorc.w [$Dst16An] */
15856 {
15857 M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16,
15858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15859 },
15860 /* rorc.w ${Dsp-16-u8}[$Dst16An] */
15861 {
15862 M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24,
15863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15864 },
15865 /* rorc.w ${Dsp-16-u16}[$Dst16An] */
15866 {
15867 M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32,
15868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15869 },
15870 /* rorc.w ${Dsp-16-u8}[sb] */
15871 {
15872 M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24,
15873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15874 },
15875 /* rorc.w ${Dsp-16-u16}[sb] */
15876 {
15877 M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32,
15878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15879 },
15880 /* rorc.w ${Dsp-16-s8}[fb] */
15881 {
15882 M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24,
15883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15884 },
15885 /* rorc.w ${Dsp-16-u16} */
15886 {
15887 M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32,
15888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15889 },
15890 /* rorc.b $Dst16RnQI */
15891 {
15892 M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16,
15893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15894 },
15895 /* rorc.b $Dst16AnQI */
15896 {
15897 M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16,
15898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15899 },
15900 /* rorc.b [$Dst16An] */
15901 {
15902 M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16,
15903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15904 },
15905 /* rorc.b ${Dsp-16-u8}[$Dst16An] */
15906 {
15907 M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24,
15908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15909 },
15910 /* rorc.b ${Dsp-16-u16}[$Dst16An] */
15911 {
15912 M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32,
15913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15914 },
15915 /* rorc.b ${Dsp-16-u8}[sb] */
15916 {
15917 M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24,
15918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15919 },
15920 /* rorc.b ${Dsp-16-u16}[sb] */
15921 {
15922 M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32,
15923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15924 },
15925 /* rorc.b ${Dsp-16-s8}[fb] */
15926 {
15927 M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24,
15928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15929 },
15930 /* rorc.b ${Dsp-16-u16} */
15931 {
15932 M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32,
15933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15934 },
15935 /* rolc.w $Dst32RnUnprefixedHI */
15936 {
15937 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16,
15938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15939 },
15940 /* rolc.w $Dst32AnUnprefixedHI */
15941 {
15942 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16,
15943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15944 },
15945 /* rolc.w [$Dst32AnUnprefixed] */
15946 {
15947 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16,
15948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15949 },
15950 /* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15951 {
15952 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24,
15953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15954 },
15955 /* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15956 {
15957 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32,
15958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15959 },
15960 /* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15961 {
15962 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40,
15963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15964 },
15965 /* rolc.w ${Dsp-16-u8}[sb] */
15966 {
15967 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24,
15968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15969 },
15970 /* rolc.w ${Dsp-16-u16}[sb] */
15971 {
15972 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32,
15973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15974 },
15975 /* rolc.w ${Dsp-16-s8}[fb] */
15976 {
15977 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24,
15978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15979 },
15980 /* rolc.w ${Dsp-16-s16}[fb] */
15981 {
15982 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32,
15983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15984 },
15985 /* rolc.w ${Dsp-16-u16} */
15986 {
15987 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32,
15988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15989 },
15990 /* rolc.w ${Dsp-16-u24} */
15991 {
15992 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40,
15993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15994 },
15995 /* rolc.b $Dst32RnUnprefixedQI */
15996 {
15997 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16,
15998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15999 },
16000 /* rolc.b $Dst32AnUnprefixedQI */
16001 {
16002 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16,
16003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16004 },
16005 /* rolc.b [$Dst32AnUnprefixed] */
16006 {
16007 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16,
16008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16009 },
16010 /* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16011 {
16012 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24,
16013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16014 },
16015 /* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16016 {
16017 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32,
16018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16019 },
16020 /* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16021 {
16022 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40,
16023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16024 },
16025 /* rolc.b ${Dsp-16-u8}[sb] */
16026 {
16027 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24,
16028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16029 },
16030 /* rolc.b ${Dsp-16-u16}[sb] */
16031 {
16032 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32,
16033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16034 },
16035 /* rolc.b ${Dsp-16-s8}[fb] */
16036 {
16037 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24,
16038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16039 },
16040 /* rolc.b ${Dsp-16-s16}[fb] */
16041 {
16042 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32,
16043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16044 },
16045 /* rolc.b ${Dsp-16-u16} */
16046 {
16047 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32,
16048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16049 },
16050 /* rolc.b ${Dsp-16-u24} */
16051 {
16052 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40,
16053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16054 },
16055 /* rolc.w $Dst16RnHI */
16056 {
16057 M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16,
16058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16059 },
16060 /* rolc.w $Dst16AnHI */
16061 {
16062 M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16,
16063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16064 },
16065 /* rolc.w [$Dst16An] */
16066 {
16067 M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16,
16068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16069 },
16070 /* rolc.w ${Dsp-16-u8}[$Dst16An] */
16071 {
16072 M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24,
16073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16074 },
16075 /* rolc.w ${Dsp-16-u16}[$Dst16An] */
16076 {
16077 M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32,
16078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16079 },
16080 /* rolc.w ${Dsp-16-u8}[sb] */
16081 {
16082 M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24,
16083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16084 },
16085 /* rolc.w ${Dsp-16-u16}[sb] */
16086 {
16087 M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32,
16088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16089 },
16090 /* rolc.w ${Dsp-16-s8}[fb] */
16091 {
16092 M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24,
16093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16094 },
16095 /* rolc.w ${Dsp-16-u16} */
16096 {
16097 M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32,
16098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16099 },
16100 /* rolc.b $Dst16RnQI */
16101 {
16102 M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16,
16103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16104 },
16105 /* rolc.b $Dst16AnQI */
16106 {
16107 M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16,
16108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16109 },
16110 /* rolc.b [$Dst16An] */
16111 {
16112 M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16,
16113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16114 },
16115 /* rolc.b ${Dsp-16-u8}[$Dst16An] */
16116 {
16117 M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24,
16118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16119 },
16120 /* rolc.b ${Dsp-16-u16}[$Dst16An] */
16121 {
16122 M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32,
16123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16124 },
16125 /* rolc.b ${Dsp-16-u8}[sb] */
16126 {
16127 M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24,
16128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16129 },
16130 /* rolc.b ${Dsp-16-u16}[sb] */
16131 {
16132 M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32,
16133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16134 },
16135 /* rolc.b ${Dsp-16-s8}[fb] */
16136 {
16137 M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24,
16138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16139 },
16140 /* rolc.b ${Dsp-16-u16} */
16141 {
16142 M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32,
16143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16144 },
16145 /* pusha [$Dst32AnUnprefixed] */
16146 {
16147 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16,
16148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16149 },
16150 /* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16151 {
16152 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24,
16153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16154 },
16155 /* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16156 {
16157 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32,
16158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16159 },
16160 /* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16161 {
16162 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40,
16163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16164 },
16165 /* pusha ${Dsp-16-u8}[sb] */
16166 {
16167 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24,
16168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16169 },
16170 /* pusha ${Dsp-16-u16}[sb] */
16171 {
16172 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32,
16173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16174 },
16175 /* pusha ${Dsp-16-s8}[fb] */
16176 {
16177 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24,
16178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16179 },
16180 /* pusha ${Dsp-16-s16}[fb] */
16181 {
16182 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32,
16183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16184 },
16185 /* pusha ${Dsp-16-u16} */
16186 {
16187 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32,
16188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16189 },
16190 /* pusha ${Dsp-16-u24} */
16191 {
16192 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40,
16193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16194 },
16195 /* pusha [$Dst16An] */
16196 {
16197 M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16,
16198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16199 },
16200 /* pusha ${Dsp-16-u8}[$Dst16An] */
16201 {
16202 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24,
16203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16204 },
16205 /* pusha ${Dsp-16-u16}[$Dst16An] */
16206 {
16207 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32,
16208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16209 },
16210 /* pusha ${Dsp-16-u8}[sb] */
16211 {
16212 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24,
16213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16214 },
16215 /* pusha ${Dsp-16-u16}[sb] */
16216 {
16217 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32,
16218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16219 },
16220 /* pusha ${Dsp-16-s8}[fb] */
16221 {
16222 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24,
16223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16224 },
16225 /* pusha ${Dsp-16-u16} */
16226 {
16227 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32,
16228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16229 },
16230 /* push.l $Dst32RnUnprefixedSI */
16231 {
16232 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16,
16233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16234 },
16235 /* push.l $Dst32AnUnprefixedSI */
16236 {
16237 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16,
16238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16239 },
16240 /* push.l [$Dst32AnUnprefixed] */
16241 {
16242 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16,
16243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16244 },
16245 /* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16246 {
16247 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24,
16248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16249 },
16250 /* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16251 {
16252 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32,
16253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16254 },
16255 /* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16256 {
16257 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40,
16258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16259 },
16260 /* push.l ${Dsp-16-u8}[sb] */
16261 {
16262 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24,
16263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16264 },
16265 /* push.l ${Dsp-16-u16}[sb] */
16266 {
16267 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32,
16268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16269 },
16270 /* push.l ${Dsp-16-s8}[fb] */
16271 {
16272 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24,
16273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16274 },
16275 /* push.l ${Dsp-16-s16}[fb] */
16276 {
16277 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32,
16278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16279 },
16280 /* push.l ${Dsp-16-u16} */
16281 {
16282 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32,
16283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16284 },
16285 /* push.l ${Dsp-16-u24} */
16286 {
16287 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40,
16288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16289 },
16290 /* push.w${S} ${An16-push-S} */
16291 {
16292 M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8,
16293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16294 },
16295 /* push.b${S} ${Rn16-push-S} */
16296 {
16297 M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8,
16298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16299 },
16300 /* push.w $Dst32RnUnprefixedHI */
16301 {
16302 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16,
16303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16304 },
16305 /* push.w $Dst32AnUnprefixedHI */
16306 {
16307 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16,
16308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16309 },
16310 /* push.w [$Dst32AnUnprefixed] */
16311 {
16312 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16,
16313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16314 },
16315 /* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16316 {
16317 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24,
16318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16319 },
16320 /* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16321 {
16322 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32,
16323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16324 },
16325 /* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16326 {
16327 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40,
16328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16329 },
16330 /* push.w ${Dsp-16-u8}[sb] */
16331 {
16332 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24,
16333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16334 },
16335 /* push.w ${Dsp-16-u16}[sb] */
16336 {
16337 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32,
16338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16339 },
16340 /* push.w ${Dsp-16-s8}[fb] */
16341 {
16342 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24,
16343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16344 },
16345 /* push.w ${Dsp-16-s16}[fb] */
16346 {
16347 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32,
16348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16349 },
16350 /* push.w ${Dsp-16-u16} */
16351 {
16352 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32,
16353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16354 },
16355 /* push.w ${Dsp-16-u24} */
16356 {
16357 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40,
16358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16359 },
16360 /* push.b $Dst32RnUnprefixedQI */
16361 {
16362 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16,
16363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16364 },
16365 /* push.b $Dst32AnUnprefixedQI */
16366 {
16367 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16,
16368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16369 },
16370 /* push.b [$Dst32AnUnprefixed] */
16371 {
16372 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16,
16373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16374 },
16375 /* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16376 {
16377 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24,
16378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16379 },
16380 /* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16381 {
16382 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32,
16383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16384 },
16385 /* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16386 {
16387 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40,
16388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16389 },
16390 /* push.b ${Dsp-16-u8}[sb] */
16391 {
16392 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24,
16393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16394 },
16395 /* push.b ${Dsp-16-u16}[sb] */
16396 {
16397 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32,
16398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16399 },
16400 /* push.b ${Dsp-16-s8}[fb] */
16401 {
16402 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24,
16403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16404 },
16405 /* push.b ${Dsp-16-s16}[fb] */
16406 {
16407 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32,
16408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16409 },
16410 /* push.b ${Dsp-16-u16} */
16411 {
16412 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32,
16413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16414 },
16415 /* push.b ${Dsp-16-u24} */
16416 {
16417 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
16418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16419 },
16420 /* push.w $Dst16RnHI */
16421 {
16422 M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
16423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16424 },
16425 /* push.w $Dst16AnHI */
16426 {
16427 M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
16428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16429 },
16430 /* push.w [$Dst16An] */
16431 {
16432 M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
16433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16434 },
16435 /* push.w ${Dsp-16-u8}[$Dst16An] */
16436 {
16437 M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
16438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16439 },
16440 /* push.w ${Dsp-16-u16}[$Dst16An] */
16441 {
16442 M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
16443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16444 },
16445 /* push.w ${Dsp-16-u8}[sb] */
16446 {
16447 M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
16448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16449 },
16450 /* push.w ${Dsp-16-u16}[sb] */
16451 {
16452 M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
16453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16454 },
16455 /* push.w ${Dsp-16-s8}[fb] */
16456 {
16457 M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
16458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16459 },
16460 /* push.w ${Dsp-16-u16} */
16461 {
16462 M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
16463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16464 },
16465 /* push.b $Dst16RnQI */
16466 {
16467 M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
16468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16469 },
16470 /* push.b $Dst16AnQI */
16471 {
16472 M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
16473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16474 },
16475 /* push.b [$Dst16An] */
16476 {
16477 M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
16478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16479 },
16480 /* push.b ${Dsp-16-u8}[$Dst16An] */
16481 {
16482 M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
16483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16484 },
16485 /* push.b ${Dsp-16-u16}[$Dst16An] */
16486 {
16487 M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
16488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16489 },
16490 /* push.b ${Dsp-16-u8}[sb] */
16491 {
16492 M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
16493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16494 },
16495 /* push.b ${Dsp-16-u16}[sb] */
16496 {
16497 M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
16498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16499 },
16500 /* push.b ${Dsp-16-s8}[fb] */
16501 {
16502 M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
16503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16504 },
16505 /* push.b ${Dsp-16-u16} */
16506 {
16507 M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
16508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16509 },
16510 /* pop.w${S} ${An16-push-S} */
16511 {
16512 M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8,
16513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16514 },
16515 /* pop.b${S} ${Rn16-push-S} */
16516 {
16517 M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8,
16518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16519 },
16520 /* pop.w $Dst32RnUnprefixedHI */
16521 {
16522 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16,
16523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16524 },
16525 /* pop.w $Dst32AnUnprefixedHI */
16526 {
16527 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16,
16528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16529 },
16530 /* pop.w [$Dst32AnUnprefixed] */
16531 {
16532 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16,
16533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16534 },
16535 /* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16536 {
16537 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24,
16538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16539 },
16540 /* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16541 {
16542 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32,
16543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16544 },
16545 /* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16546 {
16547 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40,
16548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16549 },
16550 /* pop.w ${Dsp-16-u8}[sb] */
16551 {
16552 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24,
16553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16554 },
16555 /* pop.w ${Dsp-16-u16}[sb] */
16556 {
16557 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32,
16558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16559 },
16560 /* pop.w ${Dsp-16-s8}[fb] */
16561 {
16562 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24,
16563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16564 },
16565 /* pop.w ${Dsp-16-s16}[fb] */
16566 {
16567 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32,
16568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16569 },
16570 /* pop.w ${Dsp-16-u16} */
16571 {
16572 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32,
16573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16574 },
16575 /* pop.w ${Dsp-16-u24} */
16576 {
16577 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40,
16578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16579 },
16580 /* pop.b $Dst32RnUnprefixedQI */
16581 {
16582 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16,
16583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16584 },
16585 /* pop.b $Dst32AnUnprefixedQI */
16586 {
16587 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16,
16588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16589 },
16590 /* pop.b [$Dst32AnUnprefixed] */
16591 {
16592 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16,
16593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16594 },
16595 /* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16596 {
16597 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24,
16598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16599 },
16600 /* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16601 {
16602 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32,
16603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16604 },
16605 /* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16606 {
16607 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40,
16608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16609 },
16610 /* pop.b ${Dsp-16-u8}[sb] */
16611 {
16612 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24,
16613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16614 },
16615 /* pop.b ${Dsp-16-u16}[sb] */
16616 {
16617 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32,
16618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16619 },
16620 /* pop.b ${Dsp-16-s8}[fb] */
16621 {
16622 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24,
16623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16624 },
16625 /* pop.b ${Dsp-16-s16}[fb] */
16626 {
16627 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32,
16628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16629 },
16630 /* pop.b ${Dsp-16-u16} */
16631 {
16632 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32,
16633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16634 },
16635 /* pop.b ${Dsp-16-u24} */
16636 {
16637 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40,
16638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16639 },
16640 /* pop.w $Dst16RnHI */
16641 {
16642 M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16,
16643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16644 },
16645 /* pop.w $Dst16AnHI */
16646 {
16647 M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16,
16648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16649 },
16650 /* pop.w [$Dst16An] */
16651 {
16652 M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16,
16653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16654 },
16655 /* pop.w ${Dsp-16-u8}[$Dst16An] */
16656 {
16657 M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24,
16658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16659 },
16660 /* pop.w ${Dsp-16-u16}[$Dst16An] */
16661 {
16662 M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32,
16663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16664 },
16665 /* pop.w ${Dsp-16-u8}[sb] */
16666 {
16667 M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24,
16668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16669 },
16670 /* pop.w ${Dsp-16-u16}[sb] */
16671 {
16672 M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32,
16673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16674 },
16675 /* pop.w ${Dsp-16-s8}[fb] */
16676 {
16677 M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24,
16678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16679 },
16680 /* pop.w ${Dsp-16-u16} */
16681 {
16682 M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32,
16683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16684 },
16685 /* pop.b $Dst16RnQI */
16686 {
16687 M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16,
16688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16689 },
16690 /* pop.b $Dst16AnQI */
16691 {
16692 M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16,
16693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16694 },
16695 /* pop.b [$Dst16An] */
16696 {
16697 M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16,
16698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16699 },
16700 /* pop.b ${Dsp-16-u8}[$Dst16An] */
16701 {
16702 M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24,
16703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16704 },
16705 /* pop.b ${Dsp-16-u16}[$Dst16An] */
16706 {
16707 M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32,
16708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16709 },
16710 /* pop.b ${Dsp-16-u8}[sb] */
16711 {
16712 M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24,
16713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16714 },
16715 /* pop.b ${Dsp-16-u16}[sb] */
16716 {
16717 M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32,
16718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16719 },
16720 /* pop.b ${Dsp-16-s8}[fb] */
16721 {
16722 M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24,
16723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16724 },
16725 /* pop.b ${Dsp-16-u16} */
16726 {
16727 M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32,
16728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16729 },
16730 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16731 {
16732 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16734 },
16735 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
16736 {
16737 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16739 },
16740 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
16741 {
16742 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16744 },
16745 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16746 {
16747 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16749 },
16750 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
16751 {
16752 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16754 },
16755 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
16756 {
16757 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16759 },
16760 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16761 {
16762 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16764 },
16765 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16766 {
16767 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16769 },
16770 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16771 {
16772 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16774 },
16775 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16776 {
16777 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16779 },
16780 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16781 {
16782 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16784 },
16785 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16786 {
16787 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16789 },
16790 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16791 {
16792 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16794 },
16795 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16796 {
16797 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16799 },
16800 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16801 {
16802 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16804 },
16805 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16806 {
16807 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16809 },
16810 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16811 {
16812 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16814 },
16815 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16816 {
16817 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16819 },
16820 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
16821 {
16822 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16824 },
16825 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16826 {
16827 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16829 },
16830 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16831 {
16832 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16834 },
16835 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
16836 {
16837 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16839 },
16840 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16841 {
16842 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16844 },
16845 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16846 {
16847 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16849 },
16850 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
16851 {
16852 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16854 },
16855 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16856 {
16857 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16859 },
16860 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16861 {
16862 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16864 },
16865 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
16866 {
16867 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16869 },
16870 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
16871 {
16872 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16874 },
16875 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
16876 {
16877 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16879 },
16880 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
16881 {
16882 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16884 },
16885 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16886 {
16887 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16889 },
16890 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16891 {
16892 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16894 },
16895 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
16896 {
16897 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16899 },
16900 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
16901 {
16902 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16904 },
16905 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
16906 {
16907 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16909 },
16910 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16911 {
16912 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16914 },
16915 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
16916 {
16917 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16919 },
16920 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
16921 {
16922 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16924 },
16925 /* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
16926 {
16927 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16929 },
16930 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16931 {
16932 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16934 },
16935 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
16936 {
16937 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16939 },
16940 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
16941 {
16942 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16944 },
16945 /* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
16946 {
16947 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16949 },
16950 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16951 {
16952 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16954 },
16955 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
16956 {
16957 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16959 },
16960 /* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
16961 {
16962 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16964 },
16965 /* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
16966 {
16967 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16969 },
16970 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16971 {
16972 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16974 },
16975 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16976 {
16977 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16979 },
16980 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16981 {
16982 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16984 },
16985 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
16986 {
16987 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16989 },
16990 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
16991 {
16992 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
16993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16994 },
16995 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
16996 {
16997 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
16998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16999 },
17000 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17001 {
17002 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17004 },
17005 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17006 {
17007 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17009 },
17010 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17011 {
17012 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17014 },
17015 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17016 {
17017 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17019 },
17020 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17021 {
17022 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17024 },
17025 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17026 {
17027 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17029 },
17030 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17031 {
17032 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17034 },
17035 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17036 {
17037 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17039 },
17040 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17041 {
17042 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17044 },
17045 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17046 {
17047 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17049 },
17050 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17051 {
17052 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17054 },
17055 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17056 {
17057 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17059 },
17060 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17061 {
17062 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17064 },
17065 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17066 {
17067 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17069 },
17070 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17071 {
17072 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17074 },
17075 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17076 {
17077 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17079 },
17080 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17081 {
17082 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17084 },
17085 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17086 {
17087 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17089 },
17090 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17091 {
17092 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17094 },
17095 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17096 {
17097 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17099 },
17100 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17101 {
17102 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17104 },
17105 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17106 {
17107 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17109 },
17110 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17111 {
17112 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17114 },
17115 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17116 {
17117 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17119 },
17120 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17121 {
17122 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17124 },
17125 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
17126 {
17127 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17129 },
17130 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17131 {
17132 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17134 },
17135 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17136 {
17137 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17139 },
17140 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17141 {
17142 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17144 },
17145 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
17146 {
17147 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17149 },
17150 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17151 {
17152 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17154 },
17155 /* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
17156 {
17157 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17159 },
17160 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17161 {
17162 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17164 },
17165 /* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
17166 {
17167 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17169 },
17170 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17171 {
17172 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17174 },
17175 /* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17176 {
17177 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17179 },
17180 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17181 {
17182 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17184 },
17185 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17186 {
17187 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17189 },
17190 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17191 {
17192 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17194 },
17195 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17196 {
17197 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17199 },
17200 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17201 {
17202 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17204 },
17205 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17206 {
17207 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17209 },
17210 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17211 {
17212 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17214 },
17215 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17216 {
17217 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17219 },
17220 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17221 {
17222 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17224 },
17225 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17226 {
17227 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17229 },
17230 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17231 {
17232 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17234 },
17235 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17236 {
17237 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17239 },
17240 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17241 {
17242 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17244 },
17245 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17246 {
17247 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17249 },
17250 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17251 {
17252 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17254 },
17255 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
17256 {
17257 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17259 },
17260 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17261 {
17262 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17264 },
17265 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
17266 {
17267 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17269 },
17270 /* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
17271 {
17272 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17274 },
17275 /* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
17276 {
17277 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17279 },
17280 /* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17281 {
17282 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17284 },
17285 /* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
17286 {
17287 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17289 },
17290 /* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
17291 {
17292 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17294 },
17295 /* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17296 {
17297 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17299 },
17300 /* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
17301 {
17302 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17304 },
17305 /* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
17306 {
17307 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17309 },
17310 /* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17311 {
17312 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17314 },
17315 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17316 {
17317 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17319 },
17320 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17321 {
17322 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17324 },
17325 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17326 {
17327 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17329 },
17330 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17331 {
17332 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17334 },
17335 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17336 {
17337 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17339 },
17340 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17341 {
17342 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17344 },
17345 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17346 {
17347 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17349 },
17350 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17351 {
17352 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17354 },
17355 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17356 {
17357 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17359 },
17360 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
17361 {
17362 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17364 },
17365 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
17366 {
17367 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17369 },
17370 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17371 {
17372 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17374 },
17375 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
17376 {
17377 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17379 },
17380 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
17381 {
17382 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17384 },
17385 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17386 {
17387 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17389 },
17390 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
17391 {
17392 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17394 },
17395 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
17396 {
17397 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17399 },
17400 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17401 {
17402 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17404 },
17405 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
17406 {
17407 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17409 },
17410 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
17411 {
17412 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17414 },
17415 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17416 {
17417 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17419 },
17420 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
17421 {
17422 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17424 },
17425 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
17426 {
17427 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17429 },
17430 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17431 {
17432 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17434 },
17435 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
17436 {
17437 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17439 },
17440 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
17441 {
17442 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17444 },
17445 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17446 {
17447 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17449 },
17450 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17451 {
17452 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17454 },
17455 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
17456 {
17457 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17459 },
17460 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
17461 {
17462 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17464 },
17465 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17466 {
17467 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17469 },
17470 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
17471 {
17472 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17474 },
17475 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
17476 {
17477 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17479 },
17480 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17481 {
17482 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17484 },
17485 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
17486 {
17487 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17489 },
17490 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
17491 {
17492 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17494 },
17495 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17496 {
17497 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17499 },
17500 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17501 {
17502 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17504 },
17505 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17506 {
17507 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17509 },
17510 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17511 {
17512 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17514 },
17515 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17516 {
17517 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17519 },
17520 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17521 {
17522 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17524 },
17525 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17526 {
17527 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17529 },
17530 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17531 {
17532 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17534 },
17535 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17536 {
17537 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17539 },
17540 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
17541 {
17542 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17544 },
17545 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
17546 {
17547 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17549 },
17550 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
17551 {
17552 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17554 },
17555 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
17556 {
17557 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17559 },
17560 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
17561 {
17562 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17564 },
17565 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
17566 {
17567 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17569 },
17570 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
17571 {
17572 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17574 },
17575 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
17576 {
17577 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17579 },
17580 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
17581 {
17582 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17584 },
17585 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
17586 {
17587 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17589 },
17590 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
17591 {
17592 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17594 },
17595 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
17596 {
17597 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17599 },
17600 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
17601 {
17602 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17604 },
17605 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
17606 {
17607 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17609 },
17610 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
17611 {
17612 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17614 },
17615 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
17616 {
17617 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17619 },
17620 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
17621 {
17622 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17624 },
17625 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
17626 {
17627 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17629 },
17630 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17631 {
17632 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17634 },
17635 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
17636 {
17637 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17639 },
17640 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
17641 {
17642 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17644 },
17645 /* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
17646 {
17647 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17649 },
17650 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17651 {
17652 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17654 },
17655 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
17656 {
17657 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17659 },
17660 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
17661 {
17662 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17664 },
17665 /* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
17666 {
17667 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17669 },
17670 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17671 {
17672 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17674 },
17675 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17676 {
17677 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17679 },
17680 /* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17681 {
17682 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17684 },
17685 /* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17686 {
17687 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17689 },
17690 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17691 {
17692 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17694 },
17695 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17696 {
17697 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17699 },
17700 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17701 {
17702 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17704 },
17705 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17706 {
17707 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17709 },
17710 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17711 {
17712 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17714 },
17715 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17716 {
17717 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17719 },
17720 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17721 {
17722 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17724 },
17725 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17726 {
17727 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17729 },
17730 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17731 {
17732 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17734 },
17735 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17736 {
17737 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17739 },
17740 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17741 {
17742 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17744 },
17745 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17746 {
17747 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17749 },
17750 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17751 {
17752 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17754 },
17755 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17756 {
17757 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17759 },
17760 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17761 {
17762 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17764 },
17765 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17766 {
17767 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17769 },
17770 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17771 {
17772 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17774 },
17775 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17776 {
17777 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17779 },
17780 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17781 {
17782 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17784 },
17785 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17786 {
17787 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17789 },
17790 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17791 {
17792 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17794 },
17795 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17796 {
17797 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17799 },
17800 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17801 {
17802 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17804 },
17805 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17806 {
17807 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17809 },
17810 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17811 {
17812 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17814 },
17815 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17816 {
17817 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17819 },
17820 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17821 {
17822 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17824 },
17825 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17826 {
17827 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17829 },
17830 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17831 {
17832 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17834 },
17835 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17836 {
17837 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17839 },
17840 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17841 {
17842 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17844 },
17845 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
17846 {
17847 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17849 },
17850 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17851 {
17852 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17854 },
17855 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17856 {
17857 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17859 },
17860 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17861 {
17862 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17864 },
17865 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
17866 {
17867 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17869 },
17870 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17871 {
17872 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17874 },
17875 /* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
17876 {
17877 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17879 },
17880 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17881 {
17882 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17884 },
17885 /* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
17886 {
17887 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17889 },
17890 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17891 {
17892 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17894 },
17895 /* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17896 {
17897 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17899 },
17900 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17901 {
17902 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17904 },
17905 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17906 {
17907 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17909 },
17910 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17911 {
17912 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17914 },
17915 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17916 {
17917 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17919 },
17920 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17921 {
17922 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17924 },
17925 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17926 {
17927 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17929 },
17930 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17931 {
17932 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17934 },
17935 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17936 {
17937 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17939 },
17940 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17941 {
17942 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17944 },
17945 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17946 {
17947 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17949 },
17950 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17951 {
17952 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17954 },
17955 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17956 {
17957 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17959 },
17960 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17961 {
17962 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17964 },
17965 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17966 {
17967 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17969 },
17970 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17971 {
17972 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17974 },
17975 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
17976 {
17977 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17979 },
17980 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17981 {
17982 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
17983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17984 },
17985 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
17986 {
17987 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
17988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17989 },
17990 /* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
17991 {
17992 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
17993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17994 },
17995 /* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
17996 {
17997 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
17998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17999 },
18000 /* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
18001 {
18002 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
18003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18004 },
18005 /* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
18006 {
18007 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18009 },
18010 /* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
18011 {
18012 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18014 },
18015 /* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
18016 {
18017 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18019 },
18020 /* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
18021 {
18022 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18024 },
18025 /* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
18026 {
18027 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18029 },
18030 /* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
18031 {
18032 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18034 },
18035 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18036 {
18037 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18039 },
18040 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18041 {
18042 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18044 },
18045 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
18046 {
18047 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18049 },
18050 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18051 {
18052 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18054 },
18055 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18056 {
18057 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18059 },
18060 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
18061 {
18062 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18064 },
18065 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18066 {
18067 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18069 },
18070 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18071 {
18072 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18074 },
18075 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
18076 {
18077 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18079 },
18080 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
18081 {
18082 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18084 },
18085 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
18086 {
18087 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18089 },
18090 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
18091 {
18092 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18094 },
18095 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
18096 {
18097 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18099 },
18100 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
18101 {
18102 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18104 },
18105 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
18106 {
18107 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18109 },
18110 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
18111 {
18112 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18114 },
18115 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
18116 {
18117 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18119 },
18120 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
18121 {
18122 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18124 },
18125 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
18126 {
18127 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18129 },
18130 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
18131 {
18132 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18134 },
18135 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
18136 {
18137 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18139 },
18140 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
18141 {
18142 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18144 },
18145 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
18146 {
18147 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18149 },
18150 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
18151 {
18152 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18154 },
18155 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
18156 {
18157 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18159 },
18160 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
18161 {
18162 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18164 },
18165 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
18166 {
18167 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18169 },
18170 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
18171 {
18172 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18174 },
18175 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
18176 {
18177 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18179 },
18180 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
18181 {
18182 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18184 },
18185 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
18186 {
18187 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24,
18188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18189 },
18190 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
18191 {
18192 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18194 },
18195 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
18196 {
18197 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18199 },
18200 /* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18201 {
18202 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18204 },
18205 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18206 {
18207 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18209 },
18210 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18211 {
18212 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18214 },
18215 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18216 {
18217 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18219 },
18220 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18221 {
18222 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18224 },
18225 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18226 {
18227 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18229 },
18230 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18231 {
18232 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18234 },
18235 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18236 {
18237 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18239 },
18240 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18241 {
18242 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18244 },
18245 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18246 {
18247 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18249 },
18250 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18251 {
18252 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18254 },
18255 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18256 {
18257 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18259 },
18260 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18261 {
18262 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18264 },
18265 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18266 {
18267 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18269 },
18270 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18271 {
18272 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18274 },
18275 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18276 {
18277 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18279 },
18280 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18281 {
18282 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18284 },
18285 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18286 {
18287 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18289 },
18290 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18291 {
18292 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18294 },
18295 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18296 {
18297 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18299 },
18300 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18301 {
18302 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18304 },
18305 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
18306 {
18307 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18309 },
18310 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
18311 {
18312 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18314 },
18315 /* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
18316 {
18317 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32,
18318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18319 },
18320 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
18321 {
18322 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32,
18323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18324 },
18325 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
18326 {
18327 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32,
18328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18329 },
18330 /* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
18331 {
18332 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32,
18333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18334 },
18335 /* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18336 {
18337 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18339 },
18340 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18341 {
18342 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18344 },
18345 /* or.w${G} ${Dsp-16-u16},[$Dst16An] */
18346 {
18347 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32,
18348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18349 },
18350 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18351 {
18352 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18354 },
18355 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18356 {
18357 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18359 },
18360 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18361 {
18362 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18364 },
18365 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18366 {
18367 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18369 },
18370 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18371 {
18372 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18374 },
18375 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18376 {
18377 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18379 },
18380 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18381 {
18382 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18384 },
18385 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18386 {
18387 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18389 },
18390 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18391 {
18392 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18394 },
18395 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18396 {
18397 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18399 },
18400 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18401 {
18402 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18404 },
18405 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18406 {
18407 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18409 },
18410 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18411 {
18412 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18414 },
18415 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18416 {
18417 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18419 },
18420 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18421 {
18422 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18424 },
18425 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18426 {
18427 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18429 },
18430 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18431 {
18432 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18434 },
18435 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
18436 {
18437 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48,
18438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18439 },
18440 /* or.w${G} $Src16RnHI,$Dst16RnHI */
18441 {
18442 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18444 },
18445 /* or.w${G} $Src16AnHI,$Dst16RnHI */
18446 {
18447 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18449 },
18450 /* or.w${G} [$Src16An],$Dst16RnHI */
18451 {
18452 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16,
18453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18454 },
18455 /* or.w${G} $Src16RnHI,$Dst16AnHI */
18456 {
18457 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16,
18458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18459 },
18460 /* or.w${G} $Src16AnHI,$Dst16AnHI */
18461 {
18462 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16,
18463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18464 },
18465 /* or.w${G} [$Src16An],$Dst16AnHI */
18466 {
18467 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16,
18468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18469 },
18470 /* or.w${G} $Src16RnHI,[$Dst16An] */
18471 {
18472 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18474 },
18475 /* or.w${G} $Src16AnHI,[$Dst16An] */
18476 {
18477 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18479 },
18480 /* or.w${G} [$Src16An],[$Dst16An] */
18481 {
18482 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16,
18483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18484 },
18485 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
18486 {
18487 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18489 },
18490 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
18491 {
18492 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18494 },
18495 /* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18496 {
18497 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18499 },
18500 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
18501 {
18502 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18504 },
18505 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
18506 {
18507 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18509 },
18510 /* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18511 {
18512 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18514 },
18515 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
18516 {
18517 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18519 },
18520 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
18521 {
18522 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18524 },
18525 /* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
18526 {
18527 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18529 },
18530 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
18531 {
18532 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18534 },
18535 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
18536 {
18537 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18539 },
18540 /* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
18541 {
18542 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18544 },
18545 /* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
18546 {
18547 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18549 },
18550 /* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
18551 {
18552 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18554 },
18555 /* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
18556 {
18557 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18559 },
18560 /* or.w${G} $Src16RnHI,${Dsp-16-u16} */
18561 {
18562 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18564 },
18565 /* or.w${G} $Src16AnHI,${Dsp-16-u16} */
18566 {
18567 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18569 },
18570 /* or.w${G} [$Src16An],${Dsp-16-u16} */
18571 {
18572 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32,
18573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18574 },
18575 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
18576 {
18577 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18579 },
18580 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
18581 {
18582 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18584 },
18585 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
18586 {
18587 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18589 },
18590 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
18591 {
18592 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24,
18593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18594 },
18595 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
18596 {
18597 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18599 },
18600 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
18601 {
18602 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18604 },
18605 /* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18606 {
18607 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18609 },
18610 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18611 {
18612 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18614 },
18615 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18616 {
18617 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18619 },
18620 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18621 {
18622 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18624 },
18625 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18626 {
18627 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18629 },
18630 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18631 {
18632 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18634 },
18635 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18636 {
18637 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18639 },
18640 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18641 {
18642 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18644 },
18645 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18646 {
18647 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18649 },
18650 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18651 {
18652 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18654 },
18655 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18656 {
18657 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18659 },
18660 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18661 {
18662 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18664 },
18665 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18666 {
18667 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18669 },
18670 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18671 {
18672 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18674 },
18675 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18676 {
18677 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18679 },
18680 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18681 {
18682 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18684 },
18685 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18686 {
18687 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18689 },
18690 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18691 {
18692 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18694 },
18695 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18696 {
18697 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18699 },
18700 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18701 {
18702 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18704 },
18705 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18706 {
18707 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18709 },
18710 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
18711 {
18712 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18714 },
18715 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
18716 {
18717 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18719 },
18720 /* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
18721 {
18722 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32,
18723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18724 },
18725 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
18726 {
18727 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32,
18728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18729 },
18730 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
18731 {
18732 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32,
18733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18734 },
18735 /* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
18736 {
18737 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32,
18738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18739 },
18740 /* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18741 {
18742 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18744 },
18745 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18746 {
18747 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18749 },
18750 /* or.b${G} ${Dsp-16-u16},[$Dst16An] */
18751 {
18752 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32,
18753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18754 },
18755 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18756 {
18757 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18759 },
18760 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18761 {
18762 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18764 },
18765 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18766 {
18767 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18769 },
18770 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18771 {
18772 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18774 },
18775 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18776 {
18777 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18779 },
18780 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18781 {
18782 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18784 },
18785 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18786 {
18787 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18789 },
18790 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18791 {
18792 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18794 },
18795 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18796 {
18797 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18799 },
18800 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18801 {
18802 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18804 },
18805 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18806 {
18807 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18809 },
18810 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18811 {
18812 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18814 },
18815 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18816 {
18817 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18819 },
18820 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18821 {
18822 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18824 },
18825 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18826 {
18827 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18829 },
18830 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18831 {
18832 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18834 },
18835 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18836 {
18837 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18839 },
18840 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
18841 {
18842 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48,
18843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18844 },
18845 /* or.b${G} $Src16RnQI,$Dst16RnQI */
18846 {
18847 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18849 },
18850 /* or.b${G} $Src16AnQI,$Dst16RnQI */
18851 {
18852 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18854 },
18855 /* or.b${G} [$Src16An],$Dst16RnQI */
18856 {
18857 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16,
18858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18859 },
18860 /* or.b${G} $Src16RnQI,$Dst16AnQI */
18861 {
18862 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16,
18863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18864 },
18865 /* or.b${G} $Src16AnQI,$Dst16AnQI */
18866 {
18867 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16,
18868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18869 },
18870 /* or.b${G} [$Src16An],$Dst16AnQI */
18871 {
18872 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16,
18873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18874 },
18875 /* or.b${G} $Src16RnQI,[$Dst16An] */
18876 {
18877 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18879 },
18880 /* or.b${G} $Src16AnQI,[$Dst16An] */
18881 {
18882 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18884 },
18885 /* or.b${G} [$Src16An],[$Dst16An] */
18886 {
18887 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16,
18888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18889 },
18890 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
18891 {
18892 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18894 },
18895 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
18896 {
18897 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18899 },
18900 /* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18901 {
18902 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18904 },
18905 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
18906 {
18907 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18909 },
18910 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
18911 {
18912 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18914 },
18915 /* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18916 {
18917 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18919 },
18920 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
18921 {
18922 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18924 },
18925 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
18926 {
18927 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18929 },
18930 /* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
18931 {
18932 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18934 },
18935 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
18936 {
18937 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18939 },
18940 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
18941 {
18942 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18944 },
18945 /* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
18946 {
18947 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18949 },
18950 /* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
18951 {
18952 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18954 },
18955 /* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
18956 {
18957 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18959 },
18960 /* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
18961 {
18962 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18964 },
18965 /* or.b${G} $Src16RnQI,${Dsp-16-u16} */
18966 {
18967 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18969 },
18970 /* or.b${G} $Src16AnQI,${Dsp-16-u16} */
18971 {
18972 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18974 },
18975 /* or.b${G} [$Src16An],${Dsp-16-u16} */
18976 {
18977 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32,
18978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18979 },
18980 /* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
18981 {
18982 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32,
18983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18984 },
18985 /* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
18986 {
18987 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32,
18988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18989 },
18990 /* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
18991 {
18992 M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40,
18993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18994 },
18995 /* or.w${S} #${Imm-8-HI},r0 */
18996 {
18997 M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24,
18998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18999 },
19000 /* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
19001 {
19002 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24,
19003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19004 },
19005 /* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
19006 {
19007 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24,
19008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19009 },
19010 /* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
19011 {
19012 M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32,
19013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19014 },
19015 /* or.b${S} #${Imm-8-QI},r0l */
19016 {
19017 M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16,
19018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19019 },
19020 /* or.b${S} #${Imm-8-QI},r0l */
19021 {
19022 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16,
19023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19024 },
19025 /* or.b${S} #${Imm-8-QI},r0h */
19026 {
19027 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16,
19028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19029 },
19030 /* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
19031 {
19032 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24,
19033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19034 },
19035 /* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
19036 {
19037 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24,
19038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19039 },
19040 /* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
19041 {
19042 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32,
19043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19044 },
19045 /* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
19046 {
19047 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
19048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19049 },
19050 /* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
19051 {
19052 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32,
19053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19054 },
19055 /* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
19056 {
19057 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
19058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19059 },
19060 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19061 {
19062 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40,
19063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19064 },
19065 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19066 {
19067 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40,
19068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19069 },
19070 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19071 {
19072 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40,
19073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19074 },
19075 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19076 {
19077 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48,
19078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19079 },
19080 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19081 {
19082 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48,
19083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19084 },
19085 /* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
19086 {
19087 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48,
19088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19089 },
19090 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19091 {
19092 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48,
19093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19094 },
19095 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19096 {
19097 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56,
19098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19099 },
19100 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
19101 {
19102 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56,
19103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19104 },
19105 /* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
19106 {
19107 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
19108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19109 },
19110 /* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
19111 {
19112 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24,
19113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19114 },
19115 /* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19116 {
19117 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
19118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19119 },
19120 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19121 {
19122 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32,
19123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19124 },
19125 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19126 {
19127 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32,
19128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19129 },
19130 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19131 {
19132 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32,
19133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19134 },
19135 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19136 {
19137 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40,
19138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19139 },
19140 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19141 {
19142 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40,
19143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19144 },
19145 /* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19146 {
19147 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40,
19148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19149 },
19150 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19151 {
19152 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40,
19153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19154 },
19155 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19156 {
19157 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48,
19158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19159 },
19160 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
19161 {
19162 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48,
19163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19164 },
19165 /* or.w${G} #${Imm-16-HI},$Dst16RnHI */
19166 {
19167 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32,
19168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19169 },
19170 /* or.w${G} #${Imm-16-HI},$Dst16AnHI */
19171 {
19172 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32,
19173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19174 },
19175 /* or.w${G} #${Imm-16-HI},[$Dst16An] */
19176 {
19177 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32,
19178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19179 },
19180 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
19181 {
19182 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40,
19183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19184 },
19185 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19186 {
19187 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40,
19188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19189 },
19190 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19191 {
19192 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40,
19193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19194 },
19195 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
19196 {
19197 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48,
19198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19199 },
19200 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19201 {
19202 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48,
19203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19204 },
19205 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19206 {
19207 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48,
19208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19209 },
19210 /* or.b${G} #${Imm-16-QI},$Dst16RnQI */
19211 {
19212 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24,
19213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19214 },
19215 /* or.b${G} #${Imm-16-QI},$Dst16AnQI */
19216 {
19217 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24,
19218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19219 },
19220 /* or.b${G} #${Imm-16-QI},[$Dst16An] */
19221 {
19222 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24,
19223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19224 },
19225 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
19226 {
19227 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32,
19228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19229 },
19230 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19231 {
19232 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32,
19233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19234 },
19235 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19236 {
19237 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32,
19238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19239 },
19240 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
19241 {
19242 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40,
19243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19244 },
19245 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19246 {
19247 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40,
19248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19249 },
19250 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19251 {
19252 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
19253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19254 },
19255 /* not.w $Dst32RnUnprefixedHI */
19256 {
19257 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
19258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19259 },
19260 /* not.w $Dst32AnUnprefixedHI */
19261 {
19262 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
19263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19264 },
19265 /* not.w [$Dst32AnUnprefixed] */
19266 {
19267 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
19268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19269 },
19270 /* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19271 {
19272 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
19273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19274 },
19275 /* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19276 {
19277 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
19278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19279 },
19280 /* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19281 {
19282 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
19283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19284 },
19285 /* not.w ${Dsp-16-u8}[sb] */
19286 {
19287 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
19288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19289 },
19290 /* not.w ${Dsp-16-u16}[sb] */
19291 {
19292 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
19293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19294 },
19295 /* not.w ${Dsp-16-s8}[fb] */
19296 {
19297 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
19298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19299 },
19300 /* not.w ${Dsp-16-s16}[fb] */
19301 {
19302 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
19303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19304 },
19305 /* not.w ${Dsp-16-u16} */
19306 {
19307 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
19308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19309 },
19310 /* not.w ${Dsp-16-u24} */
19311 {
19312 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
19313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19314 },
19315 /* not.b $Dst32RnUnprefixedQI */
19316 {
19317 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
19318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19319 },
19320 /* not.b $Dst32AnUnprefixedQI */
19321 {
19322 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
19323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19324 },
19325 /* not.b [$Dst32AnUnprefixed] */
19326 {
19327 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
19328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19329 },
19330 /* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19331 {
19332 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
19333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19334 },
19335 /* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19336 {
19337 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
19338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19339 },
19340 /* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19341 {
19342 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
19343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19344 },
19345 /* not.b ${Dsp-16-u8}[sb] */
19346 {
19347 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
19348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19349 },
19350 /* not.b ${Dsp-16-u16}[sb] */
19351 {
19352 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
19353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19354 },
19355 /* not.b ${Dsp-16-s8}[fb] */
19356 {
19357 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
19358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19359 },
19360 /* not.b ${Dsp-16-s16}[fb] */
19361 {
19362 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
19363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19364 },
19365 /* not.b ${Dsp-16-u16} */
19366 {
19367 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
19368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19369 },
19370 /* not.b ${Dsp-16-u24} */
19371 {
19372 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
19373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19374 },
19375 /* not.w $Dst16RnHI */
19376 {
19377 M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
19378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19379 },
19380 /* not.w $Dst16AnHI */
19381 {
19382 M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
19383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19384 },
19385 /* not.w [$Dst16An] */
19386 {
19387 M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
19388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19389 },
19390 /* not.w ${Dsp-16-u8}[$Dst16An] */
19391 {
19392 M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
19393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19394 },
19395 /* not.w ${Dsp-16-u16}[$Dst16An] */
19396 {
19397 M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
19398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19399 },
19400 /* not.w ${Dsp-16-u8}[sb] */
19401 {
19402 M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
19403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19404 },
19405 /* not.w ${Dsp-16-u16}[sb] */
19406 {
19407 M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
19408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19409 },
19410 /* not.w ${Dsp-16-s8}[fb] */
19411 {
19412 M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
19413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19414 },
19415 /* not.w ${Dsp-16-u16} */
19416 {
19417 M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
19418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19419 },
19420 /* not.b $Dst16RnQI */
19421 {
19422 M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
19423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19424 },
19425 /* not.b $Dst16AnQI */
19426 {
19427 M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
19428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19429 },
19430 /* not.b [$Dst16An] */
19431 {
19432 M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
19433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19434 },
19435 /* not.b ${Dsp-16-u8}[$Dst16An] */
19436 {
19437 M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
19438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19439 },
19440 /* not.b ${Dsp-16-u16}[$Dst16An] */
19441 {
19442 M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
19443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19444 },
19445 /* not.b ${Dsp-16-u8}[sb] */
19446 {
19447 M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
19448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19449 },
19450 /* not.b ${Dsp-16-u16}[sb] */
19451 {
19452 M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
19453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19454 },
19455 /* not.b ${Dsp-16-s8}[fb] */
19456 {
19457 M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
19458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19459 },
19460 /* not.b ${Dsp-16-u16} */
19461 {
19462 M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
19463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19464 },
19465 /* neg.w $Dst32RnUnprefixedHI */
19466 {
19467 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16,
19468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19469 },
19470 /* neg.w $Dst32AnUnprefixedHI */
19471 {
19472 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16,
19473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19474 },
19475 /* neg.w [$Dst32AnUnprefixed] */
19476 {
19477 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16,
19478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19479 },
19480 /* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19481 {
19482 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24,
19483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19484 },
19485 /* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19486 {
19487 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32,
19488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19489 },
19490 /* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19491 {
19492 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40,
19493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19494 },
19495 /* neg.w ${Dsp-16-u8}[sb] */
19496 {
19497 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24,
19498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19499 },
19500 /* neg.w ${Dsp-16-u16}[sb] */
19501 {
19502 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32,
19503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19504 },
19505 /* neg.w ${Dsp-16-s8}[fb] */
19506 {
19507 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24,
19508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19509 },
19510 /* neg.w ${Dsp-16-s16}[fb] */
19511 {
19512 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32,
19513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19514 },
19515 /* neg.w ${Dsp-16-u16} */
19516 {
19517 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32,
19518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19519 },
19520 /* neg.w ${Dsp-16-u24} */
19521 {
19522 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40,
19523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19524 },
19525 /* neg.b $Dst32RnUnprefixedQI */
19526 {
19527 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16,
19528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19529 },
19530 /* neg.b $Dst32AnUnprefixedQI */
19531 {
19532 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16,
19533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19534 },
19535 /* neg.b [$Dst32AnUnprefixed] */
19536 {
19537 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16,
19538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19539 },
19540 /* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19541 {
19542 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24,
19543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19544 },
19545 /* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19546 {
19547 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32,
19548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19549 },
19550 /* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19551 {
19552 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40,
19553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19554 },
19555 /* neg.b ${Dsp-16-u8}[sb] */
19556 {
19557 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24,
19558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19559 },
19560 /* neg.b ${Dsp-16-u16}[sb] */
19561 {
19562 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32,
19563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19564 },
19565 /* neg.b ${Dsp-16-s8}[fb] */
19566 {
19567 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24,
19568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19569 },
19570 /* neg.b ${Dsp-16-s16}[fb] */
19571 {
19572 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32,
19573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19574 },
19575 /* neg.b ${Dsp-16-u16} */
19576 {
19577 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32,
19578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19579 },
19580 /* neg.b ${Dsp-16-u24} */
19581 {
19582 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40,
19583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19584 },
19585 /* neg.w $Dst16RnHI */
19586 {
19587 M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16,
19588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19589 },
19590 /* neg.w $Dst16AnHI */
19591 {
19592 M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16,
19593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19594 },
19595 /* neg.w [$Dst16An] */
19596 {
19597 M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16,
19598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19599 },
19600 /* neg.w ${Dsp-16-u8}[$Dst16An] */
19601 {
19602 M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24,
19603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19604 },
19605 /* neg.w ${Dsp-16-u16}[$Dst16An] */
19606 {
19607 M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32,
19608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19609 },
19610 /* neg.w ${Dsp-16-u8}[sb] */
19611 {
19612 M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24,
19613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19614 },
19615 /* neg.w ${Dsp-16-u16}[sb] */
19616 {
19617 M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32,
19618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19619 },
19620 /* neg.w ${Dsp-16-s8}[fb] */
19621 {
19622 M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24,
19623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19624 },
19625 /* neg.w ${Dsp-16-u16} */
19626 {
19627 M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32,
19628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19629 },
19630 /* neg.b $Dst16RnQI */
19631 {
19632 M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16,
19633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19634 },
19635 /* neg.b $Dst16AnQI */
19636 {
19637 M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16,
19638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19639 },
19640 /* neg.b [$Dst16An] */
19641 {
19642 M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16,
19643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19644 },
19645 /* neg.b ${Dsp-16-u8}[$Dst16An] */
19646 {
19647 M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24,
19648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19649 },
19650 /* neg.b ${Dsp-16-u16}[$Dst16An] */
19651 {
19652 M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32,
19653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19654 },
19655 /* neg.b ${Dsp-16-u8}[sb] */
19656 {
19657 M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24,
19658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19659 },
19660 /* neg.b ${Dsp-16-u16}[sb] */
19661 {
19662 M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32,
19663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19664 },
19665 /* neg.b ${Dsp-16-s8}[fb] */
19666 {
19667 M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24,
19668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19669 },
19670 /* neg.b ${Dsp-16-u16} */
19671 {
19672 M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32,
19673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19674 },
19675 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19676 {
19677 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19679 },
19680 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
19681 {
19682 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19684 },
19685 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
19686 {
19687 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19689 },
19690 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19691 {
19692 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19694 },
19695 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
19696 {
19697 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19699 },
19700 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
19701 {
19702 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19704 },
19705 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19706 {
19707 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19709 },
19710 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
19711 {
19712 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19714 },
19715 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
19716 {
19717 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19719 },
19720 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19721 {
19722 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19724 },
19725 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19726 {
19727 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19729 },
19730 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19731 {
19732 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19734 },
19735 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19736 {
19737 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19739 },
19740 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19741 {
19742 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19744 },
19745 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19746 {
19747 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19749 },
19750 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19751 {
19752 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19754 },
19755 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19756 {
19757 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19759 },
19760 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19761 {
19762 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19764 },
19765 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
19766 {
19767 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19769 },
19770 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
19771 {
19772 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19774 },
19775 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
19776 {
19777 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19779 },
19780 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
19781 {
19782 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19784 },
19785 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
19786 {
19787 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19789 },
19790 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
19791 {
19792 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19794 },
19795 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
19796 {
19797 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19799 },
19800 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
19801 {
19802 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19804 },
19805 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
19806 {
19807 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19809 },
19810 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
19811 {
19812 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19814 },
19815 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
19816 {
19817 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19819 },
19820 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
19821 {
19822 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19824 },
19825 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
19826 {
19827 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19829 },
19830 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
19831 {
19832 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19834 },
19835 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
19836 {
19837 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19839 },
19840 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
19841 {
19842 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19844 },
19845 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
19846 {
19847 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19849 },
19850 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
19851 {
19852 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19854 },
19855 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19856 {
19857 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19859 },
19860 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
19861 {
19862 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19864 },
19865 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
19866 {
19867 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19869 },
19870 /* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
19871 {
19872 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19874 },
19875 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19876 {
19877 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19879 },
19880 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
19881 {
19882 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19884 },
19885 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
19886 {
19887 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19889 },
19890 /* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
19891 {
19892 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19894 },
19895 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19896 {
19897 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19899 },
19900 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
19901 {
19902 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19904 },
19905 /* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
19906 {
19907 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19909 },
19910 /* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
19911 {
19912 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19914 },
19915 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19916 {
19917 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19919 },
19920 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19921 {
19922 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19924 },
19925 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19926 {
19927 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19929 },
19930 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
19931 {
19932 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19934 },
19935 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19936 {
19937 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19939 },
19940 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19941 {
19942 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19944 },
19945 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19946 {
19947 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19949 },
19950 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
19951 {
19952 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19954 },
19955 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19956 {
19957 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19959 },
19960 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19961 {
19962 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19964 },
19965 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19966 {
19967 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19969 },
19970 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
19971 {
19972 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19974 },
19975 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
19976 {
19977 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19979 },
19980 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
19981 {
19982 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19984 },
19985 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
19986 {
19987 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19989 },
19990 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
19991 {
19992 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19994 },
19995 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
19996 {
19997 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
19998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19999 },
20000 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20001 {
20002 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20004 },
20005 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20006 {
20007 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20009 },
20010 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20011 {
20012 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20014 },
20015 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20016 {
20017 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20019 },
20020 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20021 {
20022 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20024 },
20025 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20026 {
20027 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20029 },
20030 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20031 {
20032 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20034 },
20035 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20036 {
20037 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20039 },
20040 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20041 {
20042 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20044 },
20045 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20046 {
20047 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20049 },
20050 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20051 {
20052 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20054 },
20055 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20056 {
20057 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20059 },
20060 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20061 {
20062 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20064 },
20065 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20066 {
20067 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20069 },
20070 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
20071 {
20072 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20074 },
20075 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20076 {
20077 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20079 },
20080 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20081 {
20082 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20084 },
20085 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20086 {
20087 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20089 },
20090 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
20091 {
20092 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20094 },
20095 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20096 {
20097 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20099 },
20100 /* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
20101 {
20102 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20104 },
20105 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20106 {
20107 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20109 },
20110 /* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
20111 {
20112 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20114 },
20115 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20116 {
20117 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20119 },
20120 /* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20121 {
20122 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20124 },
20125 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20126 {
20127 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20129 },
20130 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20131 {
20132 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20134 },
20135 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20136 {
20137 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20139 },
20140 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20141 {
20142 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20144 },
20145 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20146 {
20147 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20149 },
20150 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20151 {
20152 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20154 },
20155 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20156 {
20157 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20159 },
20160 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20161 {
20162 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20164 },
20165 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20166 {
20167 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20169 },
20170 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20171 {
20172 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20174 },
20175 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20176 {
20177 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20179 },
20180 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20181 {
20182 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20184 },
20185 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20186 {
20187 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20189 },
20190 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20191 {
20192 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20194 },
20195 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20196 {
20197 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20199 },
20200 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
20201 {
20202 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20204 },
20205 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20206 {
20207 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20209 },
20210 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
20211 {
20212 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20214 },
20215 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
20216 {
20217 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20219 },
20220 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
20221 {
20222 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20224 },
20225 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20226 {
20227 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20229 },
20230 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
20231 {
20232 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20234 },
20235 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
20236 {
20237 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20239 },
20240 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20241 {
20242 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20244 },
20245 /* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
20246 {
20247 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20249 },
20250 /* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
20251 {
20252 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20254 },
20255 /* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20256 {
20257 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20259 },
20260 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20261 {
20262 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20264 },
20265 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20266 {
20267 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20269 },
20270 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
20271 {
20272 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20274 },
20275 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20276 {
20277 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20279 },
20280 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20281 {
20282 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20284 },
20285 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
20286 {
20287 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20289 },
20290 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20291 {
20292 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20294 },
20295 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20296 {
20297 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20299 },
20300 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
20301 {
20302 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20304 },
20305 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
20306 {
20307 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20309 },
20310 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
20311 {
20312 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20314 },
20315 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
20316 {
20317 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20319 },
20320 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
20321 {
20322 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20324 },
20325 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
20326 {
20327 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20329 },
20330 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
20331 {
20332 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20334 },
20335 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
20336 {
20337 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20339 },
20340 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
20341 {
20342 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20344 },
20345 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
20346 {
20347 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20349 },
20350 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
20351 {
20352 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20354 },
20355 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
20356 {
20357 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20359 },
20360 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
20361 {
20362 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20364 },
20365 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
20366 {
20367 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20369 },
20370 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
20371 {
20372 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20374 },
20375 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
20376 {
20377 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20379 },
20380 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
20381 {
20382 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20384 },
20385 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
20386 {
20387 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20389 },
20390 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
20391 {
20392 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20394 },
20395 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20396 {
20397 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20399 },
20400 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
20401 {
20402 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20404 },
20405 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
20406 {
20407 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20409 },
20410 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20411 {
20412 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20414 },
20415 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
20416 {
20417 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20419 },
20420 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
20421 {
20422 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20424 },
20425 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20426 {
20427 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20429 },
20430 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
20431 {
20432 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20434 },
20435 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
20436 {
20437 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20439 },
20440 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20441 {
20442 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20444 },
20445 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20446 {
20447 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20449 },
20450 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20451 {
20452 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20454 },
20455 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20456 {
20457 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20459 },
20460 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20461 {
20462 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20464 },
20465 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20466 {
20467 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20469 },
20470 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20471 {
20472 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20474 },
20475 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20476 {
20477 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20479 },
20480 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20481 {
20482 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20484 },
20485 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
20486 {
20487 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20489 },
20490 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
20491 {
20492 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20494 },
20495 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
20496 {
20497 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20499 },
20500 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
20501 {
20502 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20504 },
20505 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
20506 {
20507 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20509 },
20510 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
20511 {
20512 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20514 },
20515 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
20516 {
20517 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20519 },
20520 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
20521 {
20522 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20524 },
20525 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
20526 {
20527 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20529 },
20530 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
20531 {
20532 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20534 },
20535 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
20536 {
20537 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20539 },
20540 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
20541 {
20542 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20544 },
20545 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
20546 {
20547 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20549 },
20550 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
20551 {
20552 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20554 },
20555 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
20556 {
20557 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20559 },
20560 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
20561 {
20562 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20564 },
20565 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
20566 {
20567 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20569 },
20570 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
20571 {
20572 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20574 },
20575 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20576 {
20577 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20579 },
20580 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
20581 {
20582 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20584 },
20585 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
20586 {
20587 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20589 },
20590 /* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
20591 {
20592 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20594 },
20595 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20596 {
20597 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20599 },
20600 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
20601 {
20602 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20604 },
20605 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
20606 {
20607 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20609 },
20610 /* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
20611 {
20612 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20614 },
20615 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20616 {
20617 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20619 },
20620 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
20621 {
20622 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20624 },
20625 /* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
20626 {
20627 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20629 },
20630 /* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
20631 {
20632 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20634 },
20635 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20636 {
20637 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20639 },
20640 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20641 {
20642 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20644 },
20645 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20646 {
20647 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20649 },
20650 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
20651 {
20652 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20654 },
20655 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20656 {
20657 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20659 },
20660 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20661 {
20662 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20664 },
20665 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20666 {
20667 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20669 },
20670 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
20671 {
20672 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20674 },
20675 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20676 {
20677 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20679 },
20680 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20681 {
20682 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20684 },
20685 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20686 {
20687 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20689 },
20690 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
20691 {
20692 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20694 },
20695 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
20696 {
20697 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20699 },
20700 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
20701 {
20702 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20704 },
20705 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20706 {
20707 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20709 },
20710 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20711 {
20712 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20714 },
20715 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20716 {
20717 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20719 },
20720 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20721 {
20722 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20724 },
20725 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20726 {
20727 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20729 },
20730 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20731 {
20732 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20734 },
20735 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20736 {
20737 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20739 },
20740 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20741 {
20742 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20744 },
20745 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20746 {
20747 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20749 },
20750 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20751 {
20752 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20754 },
20755 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20756 {
20757 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20759 },
20760 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20761 {
20762 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20764 },
20765 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20766 {
20767 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20769 },
20770 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20771 {
20772 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20774 },
20775 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20776 {
20777 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20779 },
20780 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20781 {
20782 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20784 },
20785 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20786 {
20787 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20789 },
20790 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
20791 {
20792 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20794 },
20795 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20796 {
20797 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20799 },
20800 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20801 {
20802 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20804 },
20805 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20806 {
20807 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20809 },
20810 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
20811 {
20812 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20814 },
20815 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20816 {
20817 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20819 },
20820 /* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
20821 {
20822 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20824 },
20825 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20826 {
20827 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20829 },
20830 /* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
20831 {
20832 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20834 },
20835 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20836 {
20837 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20839 },
20840 /* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20841 {
20842 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20844 },
20845 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20846 {
20847 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20849 },
20850 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20851 {
20852 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20854 },
20855 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20856 {
20857 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20859 },
20860 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20861 {
20862 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20864 },
20865 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20866 {
20867 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20869 },
20870 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20871 {
20872 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20874 },
20875 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20876 {
20877 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20879 },
20880 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20881 {
20882 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20884 },
20885 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20886 {
20887 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20889 },
20890 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20891 {
20892 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20894 },
20895 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20896 {
20897 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20899 },
20900 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20901 {
20902 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20904 },
20905 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20906 {
20907 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20909 },
20910 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20911 {
20912 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20914 },
20915 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20916 {
20917 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20919 },
20920 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
20921 {
20922 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20924 },
20925 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20926 {
20927 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20929 },
20930 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
20931 {
20932 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20934 },
20935 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
20936 {
20937 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20939 },
20940 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
20941 {
20942 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20944 },
20945 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20946 {
20947 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20949 },
20950 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
20951 {
20952 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20954 },
20955 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
20956 {
20957 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20959 },
20960 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20961 {
20962 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20964 },
20965 /* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
20966 {
20967 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20969 },
20970 /* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
20971 {
20972 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20974 },
20975 /* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20976 {
20977 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20979 },
20980 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20981 {
20982 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
20983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20984 },
20985 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20986 {
20987 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
20988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20989 },
20990 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
20991 {
20992 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
20993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20994 },
20995 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20996 {
20997 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
20998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20999 },
21000 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
21001 {
21002 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21004 },
21005 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
21006 {
21007 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21009 },
21010 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21011 {
21012 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21014 },
21015 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21016 {
21017 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21019 },
21020 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
21021 {
21022 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21024 },
21025 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
21026 {
21027 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21029 },
21030 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
21031 {
21032 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21034 },
21035 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
21036 {
21037 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21039 },
21040 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
21041 {
21042 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21044 },
21045 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
21046 {
21047 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21049 },
21050 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
21051 {
21052 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21054 },
21055 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
21056 {
21057 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21059 },
21060 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
21061 {
21062 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21064 },
21065 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
21066 {
21067 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21069 },
21070 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
21071 {
21072 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21074 },
21075 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
21076 {
21077 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21079 },
21080 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
21081 {
21082 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21084 },
21085 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
21086 {
21087 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21089 },
21090 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
21091 {
21092 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21094 },
21095 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
21096 {
21097 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21099 },
21100 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
21101 {
21102 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21104 },
21105 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
21106 {
21107 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21109 },
21110 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
21111 {
21112 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21114 },
21115 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21116 {
21117 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21119 },
21120 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
21121 {
21122 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21124 },
21125 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
21126 {
21127 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21129 },
21130 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21131 {
21132 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21134 },
21135 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
21136 {
21137 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21139 },
21140 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
21141 {
21142 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21144 },
21145 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21146 {
21147 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21149 },
21150 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21151 {
21152 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21154 },
21155 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21156 {
21157 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21159 },
21160 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21161 {
21162 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21164 },
21165 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21166 {
21167 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21169 },
21170 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21171 {
21172 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21174 },
21175 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21176 {
21177 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21179 },
21180 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21181 {
21182 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21184 },
21185 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21186 {
21187 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21189 },
21190 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21191 {
21192 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21194 },
21195 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21196 {
21197 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21199 },
21200 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21201 {
21202 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21204 },
21205 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21206 {
21207 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21209 },
21210 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21211 {
21212 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21214 },
21215 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21216 {
21217 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21219 },
21220 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21221 {
21222 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21224 },
21225 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21226 {
21227 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21229 },
21230 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21231 {
21232 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21234 },
21235 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21236 {
21237 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21239 },
21240 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21241 {
21242 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21244 },
21245 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21246 {
21247 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21249 },
21250 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
21251 {
21252 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21254 },
21255 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
21256 {
21257 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21259 },
21260 /* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
21261 {
21262 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21264 },
21265 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
21266 {
21267 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21269 },
21270 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
21271 {
21272 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21274 },
21275 /* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
21276 {
21277 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32,
21278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21279 },
21280 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21281 {
21282 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21284 },
21285 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21286 {
21287 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21289 },
21290 /* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
21291 {
21292 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32,
21293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21294 },
21295 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21296 {
21297 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21299 },
21300 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21301 {
21302 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21304 },
21305 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21306 {
21307 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21309 },
21310 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21311 {
21312 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21314 },
21315 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21316 {
21317 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21319 },
21320 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21321 {
21322 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21324 },
21325 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21326 {
21327 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21329 },
21330 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21331 {
21332 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21334 },
21335 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21336 {
21337 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21339 },
21340 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21341 {
21342 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21344 },
21345 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21346 {
21347 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21349 },
21350 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21351 {
21352 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21354 },
21355 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21356 {
21357 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21359 },
21360 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21361 {
21362 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21364 },
21365 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21366 {
21367 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21369 },
21370 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21371 {
21372 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21374 },
21375 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21376 {
21377 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21379 },
21380 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
21381 {
21382 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21384 },
21385 /* mulu.w${G} $Src16RnHI,$Dst16RnHI */
21386 {
21387 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21389 },
21390 /* mulu.w${G} $Src16AnHI,$Dst16RnHI */
21391 {
21392 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21394 },
21395 /* mulu.w${G} [$Src16An],$Dst16RnHI */
21396 {
21397 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21399 },
21400 /* mulu.w${G} $Src16RnHI,$Dst16AnHI */
21401 {
21402 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21404 },
21405 /* mulu.w${G} $Src16AnHI,$Dst16AnHI */
21406 {
21407 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21409 },
21410 /* mulu.w${G} [$Src16An],$Dst16AnHI */
21411 {
21412 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16,
21413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21414 },
21415 /* mulu.w${G} $Src16RnHI,[$Dst16An] */
21416 {
21417 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21419 },
21420 /* mulu.w${G} $Src16AnHI,[$Dst16An] */
21421 {
21422 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21424 },
21425 /* mulu.w${G} [$Src16An],[$Dst16An] */
21426 {
21427 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16,
21428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21429 },
21430 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
21431 {
21432 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21434 },
21435 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
21436 {
21437 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21439 },
21440 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21441 {
21442 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21444 },
21445 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
21446 {
21447 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21449 },
21450 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
21451 {
21452 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21454 },
21455 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21456 {
21457 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21459 },
21460 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
21461 {
21462 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21464 },
21465 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
21466 {
21467 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21469 },
21470 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
21471 {
21472 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21474 },
21475 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
21476 {
21477 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21479 },
21480 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
21481 {
21482 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21484 },
21485 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
21486 {
21487 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21489 },
21490 /* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
21491 {
21492 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21494 },
21495 /* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
21496 {
21497 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21499 },
21500 /* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
21501 {
21502 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21504 },
21505 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
21506 {
21507 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21509 },
21510 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
21511 {
21512 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21514 },
21515 /* mulu.w${G} [$Src16An],${Dsp-16-u16} */
21516 {
21517 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21519 },
21520 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
21521 {
21522 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21524 },
21525 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
21526 {
21527 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21529 },
21530 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
21531 {
21532 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21534 },
21535 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
21536 {
21537 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21539 },
21540 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
21541 {
21542 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21544 },
21545 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
21546 {
21547 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21549 },
21550 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21551 {
21552 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21554 },
21555 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21556 {
21557 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21559 },
21560 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21561 {
21562 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21564 },
21565 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21566 {
21567 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21569 },
21570 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21571 {
21572 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21574 },
21575 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21576 {
21577 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21579 },
21580 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21581 {
21582 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21584 },
21585 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21586 {
21587 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21589 },
21590 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21591 {
21592 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21594 },
21595 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21596 {
21597 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21599 },
21600 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21601 {
21602 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21604 },
21605 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21606 {
21607 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21609 },
21610 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21611 {
21612 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21614 },
21615 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21616 {
21617 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21619 },
21620 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21621 {
21622 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21624 },
21625 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21626 {
21627 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21629 },
21630 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21631 {
21632 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21634 },
21635 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21636 {
21637 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21639 },
21640 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21641 {
21642 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21644 },
21645 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21646 {
21647 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21649 },
21650 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21651 {
21652 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21654 },
21655 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
21656 {
21657 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21659 },
21660 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
21661 {
21662 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21664 },
21665 /* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
21666 {
21667 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21669 },
21670 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
21671 {
21672 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21674 },
21675 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
21676 {
21677 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21679 },
21680 /* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
21681 {
21682 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32,
21683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21684 },
21685 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21686 {
21687 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21689 },
21690 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21691 {
21692 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21694 },
21695 /* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
21696 {
21697 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32,
21698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21699 },
21700 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21701 {
21702 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21704 },
21705 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21706 {
21707 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21709 },
21710 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21711 {
21712 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21714 },
21715 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21716 {
21717 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21719 },
21720 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21721 {
21722 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21724 },
21725 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21726 {
21727 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21729 },
21730 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21731 {
21732 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21734 },
21735 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21736 {
21737 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21739 },
21740 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21741 {
21742 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21744 },
21745 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21746 {
21747 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21749 },
21750 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21751 {
21752 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21754 },
21755 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21756 {
21757 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21759 },
21760 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21761 {
21762 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21764 },
21765 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21766 {
21767 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21769 },
21770 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21771 {
21772 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21774 },
21775 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21776 {
21777 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21779 },
21780 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21781 {
21782 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21784 },
21785 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
21786 {
21787 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21789 },
21790 /* mulu.b${G} $Src16RnQI,$Dst16RnQI */
21791 {
21792 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21794 },
21795 /* mulu.b${G} $Src16AnQI,$Dst16RnQI */
21796 {
21797 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21799 },
21800 /* mulu.b${G} [$Src16An],$Dst16RnQI */
21801 {
21802 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21804 },
21805 /* mulu.b${G} $Src16RnQI,$Dst16AnQI */
21806 {
21807 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21809 },
21810 /* mulu.b${G} $Src16AnQI,$Dst16AnQI */
21811 {
21812 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21814 },
21815 /* mulu.b${G} [$Src16An],$Dst16AnQI */
21816 {
21817 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16,
21818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21819 },
21820 /* mulu.b${G} $Src16RnQI,[$Dst16An] */
21821 {
21822 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21824 },
21825 /* mulu.b${G} $Src16AnQI,[$Dst16An] */
21826 {
21827 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21829 },
21830 /* mulu.b${G} [$Src16An],[$Dst16An] */
21831 {
21832 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16,
21833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21834 },
21835 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
21836 {
21837 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21839 },
21840 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
21841 {
21842 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21844 },
21845 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21846 {
21847 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21849 },
21850 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
21851 {
21852 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21854 },
21855 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
21856 {
21857 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21859 },
21860 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21861 {
21862 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21864 },
21865 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
21866 {
21867 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21869 },
21870 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
21871 {
21872 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21874 },
21875 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
21876 {
21877 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21879 },
21880 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
21881 {
21882 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21884 },
21885 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
21886 {
21887 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21889 },
21890 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
21891 {
21892 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21894 },
21895 /* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
21896 {
21897 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21899 },
21900 /* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
21901 {
21902 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21904 },
21905 /* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
21906 {
21907 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21909 },
21910 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
21911 {
21912 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21914 },
21915 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
21916 {
21917 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21919 },
21920 /* mulu.b${G} [$Src16An],${Dsp-16-u16} */
21921 {
21922 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21924 },
21925 /* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
21926 {
21927 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
21928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21929 },
21930 /* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
21931 {
21932 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
21933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21934 },
21935 /* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
21936 {
21937 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
21938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21939 },
21940 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
21941 {
21942 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40,
21943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21944 },
21945 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
21946 {
21947 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
21948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21949 },
21950 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
21951 {
21952 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
21953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21954 },
21955 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
21956 {
21957 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48,
21958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21959 },
21960 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
21961 {
21962 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
21963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21964 },
21965 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
21966 {
21967 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
21968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21969 },
21970 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
21971 {
21972 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48,
21973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21974 },
21975 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
21976 {
21977 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56,
21978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21979 },
21980 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
21981 {
21982 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56,
21983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21984 },
21985 /* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
21986 {
21987 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
21988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21989 },
21990 /* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
21991 {
21992 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
21993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21994 },
21995 /* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
21996 {
21997 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
21998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21999 },
22000 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
22001 {
22002 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32,
22003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22004 },
22005 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22006 {
22007 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
22008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22009 },
22010 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22011 {
22012 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
22013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22014 },
22015 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
22016 {
22017 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40,
22018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22019 },
22020 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22021 {
22022 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
22023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22024 },
22025 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
22026 {
22027 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
22028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22029 },
22030 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22031 {
22032 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40,
22033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22034 },
22035 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
22036 {
22037 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48,
22038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22039 },
22040 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
22041 {
22042 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48,
22043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22044 },
22045 /* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
22046 {
22047 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32,
22048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22049 },
22050 /* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
22051 {
22052 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32,
22053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22054 },
22055 /* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
22056 {
22057 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32,
22058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22059 },
22060 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22061 {
22062 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40,
22063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22064 },
22065 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22066 {
22067 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40,
22068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22069 },
22070 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22071 {
22072 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40,
22073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22074 },
22075 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22076 {
22077 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48,
22078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22079 },
22080 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22081 {
22082 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48,
22083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22084 },
22085 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
22086 {
22087 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48,
22088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22089 },
22090 /* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
22091 {
22092 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24,
22093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22094 },
22095 /* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
22096 {
22097 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24,
22098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22099 },
22100 /* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
22101 {
22102 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24,
22103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22104 },
22105 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
22106 {
22107 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32,
22108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22109 },
22110 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22111 {
22112 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32,
22113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22114 },
22115 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22116 {
22117 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32,
22118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22119 },
22120 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
22121 {
22122 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40,
22123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22124 },
22125 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22126 {
22127 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40,
22128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22129 },
22130 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22131 {
22132 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40,
22133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22134 },
22135 /* mulex $R3 */
22136 {
22137 M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16,
22138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22139 },
22140 /* mulex $Dst32AnUnprefixedHI */
22141 {
22142 M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16,
22143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22144 },
22145 /* mulex [$Dst32AnUnprefixed] */
22146 {
22147 M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16,
22148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22149 },
22150 /* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
22151 {
22152 M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24,
22153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22154 },
22155 /* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
22156 {
22157 M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32,
22158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22159 },
22160 /* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
22161 {
22162 M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40,
22163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22164 },
22165 /* mulex ${Dsp-16-u8}[sb] */
22166 {
22167 M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24,
22168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22169 },
22170 /* mulex ${Dsp-16-u16}[sb] */
22171 {
22172 M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32,
22173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22174 },
22175 /* mulex ${Dsp-16-s8}[fb] */
22176 {
22177 M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24,
22178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22179 },
22180 /* mulex ${Dsp-16-s16}[fb] */
22181 {
22182 M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32,
22183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22184 },
22185 /* mulex ${Dsp-16-u16} */
22186 {
22187 M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32,
22188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22189 },
22190 /* mulex ${Dsp-16-u24} */
22191 {
22192 M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40,
22193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22194 },
22195 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22196 {
22197 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22199 },
22200 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
22201 {
22202 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22204 },
22205 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
22206 {
22207 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22209 },
22210 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22211 {
22212 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22214 },
22215 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
22216 {
22217 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22219 },
22220 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
22221 {
22222 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22224 },
22225 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22226 {
22227 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22229 },
22230 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22231 {
22232 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22234 },
22235 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22236 {
22237 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22239 },
22240 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22241 {
22242 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22244 },
22245 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22246 {
22247 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22249 },
22250 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22251 {
22252 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22254 },
22255 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22256 {
22257 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22259 },
22260 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22261 {
22262 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22264 },
22265 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22266 {
22267 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22269 },
22270 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22271 {
22272 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22274 },
22275 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22276 {
22277 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22279 },
22280 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22281 {
22282 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22284 },
22285 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
22286 {
22287 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22289 },
22290 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22291 {
22292 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22294 },
22295 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22296 {
22297 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22299 },
22300 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
22301 {
22302 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22304 },
22305 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22306 {
22307 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22309 },
22310 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22311 {
22312 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22314 },
22315 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
22316 {
22317 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22319 },
22320 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22321 {
22322 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22324 },
22325 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22326 {
22327 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22329 },
22330 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
22331 {
22332 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22334 },
22335 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
22336 {
22337 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22339 },
22340 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
22341 {
22342 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22344 },
22345 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
22346 {
22347 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22349 },
22350 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22351 {
22352 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22354 },
22355 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22356 {
22357 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22359 },
22360 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
22361 {
22362 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22364 },
22365 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
22366 {
22367 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22369 },
22370 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
22371 {
22372 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22374 },
22375 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22376 {
22377 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22379 },
22380 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
22381 {
22382 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22384 },
22385 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
22386 {
22387 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22389 },
22390 /* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
22391 {
22392 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22394 },
22395 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22396 {
22397 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22399 },
22400 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
22401 {
22402 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22404 },
22405 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
22406 {
22407 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22409 },
22410 /* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
22411 {
22412 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22414 },
22415 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22416 {
22417 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22419 },
22420 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
22421 {
22422 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22424 },
22425 /* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
22426 {
22427 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22429 },
22430 /* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
22431 {
22432 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22434 },
22435 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22436 {
22437 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22439 },
22440 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22441 {
22442 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22444 },
22445 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22446 {
22447 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22449 },
22450 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
22451 {
22452 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22454 },
22455 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22456 {
22457 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22459 },
22460 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22461 {
22462 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22464 },
22465 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22466 {
22467 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22469 },
22470 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
22471 {
22472 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22474 },
22475 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22476 {
22477 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22479 },
22480 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22481 {
22482 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22484 },
22485 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22486 {
22487 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22489 },
22490 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
22491 {
22492 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22494 },
22495 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
22496 {
22497 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22499 },
22500 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22501 {
22502 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22504 },
22505 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
22506 {
22507 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22509 },
22510 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22511 {
22512 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22514 },
22515 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
22516 {
22517 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22519 },
22520 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22521 {
22522 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22524 },
22525 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
22526 {
22527 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22529 },
22530 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22531 {
22532 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22534 },
22535 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
22536 {
22537 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22539 },
22540 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22541 {
22542 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22544 },
22545 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
22546 {
22547 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22549 },
22550 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22551 {
22552 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22554 },
22555 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
22556 {
22557 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22559 },
22560 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
22561 {
22562 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22564 },
22565 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
22566 {
22567 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22569 },
22570 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
22571 {
22572 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22574 },
22575 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
22576 {
22577 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22579 },
22580 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22581 {
22582 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22584 },
22585 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
22586 {
22587 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22589 },
22590 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
22591 {
22592 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22594 },
22595 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
22596 {
22597 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22599 },
22600 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
22601 {
22602 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22604 },
22605 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
22606 {
22607 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22609 },
22610 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
22611 {
22612 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22614 },
22615 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22616 {
22617 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22619 },
22620 /* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
22621 {
22622 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22624 },
22625 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22626 {
22627 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22629 },
22630 /* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
22631 {
22632 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22634 },
22635 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22636 {
22637 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22639 },
22640 /* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
22641 {
22642 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22644 },
22645 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
22646 {
22647 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22649 },
22650 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
22651 {
22652 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22654 },
22655 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
22656 {
22657 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22659 },
22660 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
22661 {
22662 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22664 },
22665 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
22666 {
22667 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22669 },
22670 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
22671 {
22672 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22674 },
22675 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
22676 {
22677 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22679 },
22680 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
22681 {
22682 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22684 },
22685 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
22686 {
22687 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22689 },
22690 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
22691 {
22692 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22694 },
22695 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
22696 {
22697 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22699 },
22700 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
22701 {
22702 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22704 },
22705 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
22706 {
22707 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22709 },
22710 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
22711 {
22712 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22714 },
22715 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
22716 {
22717 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22719 },
22720 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
22721 {
22722 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22724 },
22725 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
22726 {
22727 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22729 },
22730 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
22731 {
22732 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22734 },
22735 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
22736 {
22737 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22739 },
22740 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
22741 {
22742 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22744 },
22745 /* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22746 {
22747 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22749 },
22750 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
22751 {
22752 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22754 },
22755 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
22756 {
22757 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22759 },
22760 /* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22761 {
22762 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22764 },
22765 /* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
22766 {
22767 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22769 },
22770 /* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
22771 {
22772 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22774 },
22775 /* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22776 {
22777 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22779 },
22780 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22781 {
22782 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22784 },
22785 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22786 {
22787 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22789 },
22790 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
22791 {
22792 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22794 },
22795 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22796 {
22797 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22799 },
22800 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22801 {
22802 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22804 },
22805 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
22806 {
22807 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22809 },
22810 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22811 {
22812 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22814 },
22815 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22816 {
22817 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22819 },
22820 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
22821 {
22822 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22824 },
22825 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
22826 {
22827 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22829 },
22830 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
22831 {
22832 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22834 },
22835 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
22836 {
22837 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22839 },
22840 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
22841 {
22842 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22844 },
22845 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
22846 {
22847 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22849 },
22850 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
22851 {
22852 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22854 },
22855 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
22856 {
22857 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22859 },
22860 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
22861 {
22862 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22864 },
22865 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
22866 {
22867 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22869 },
22870 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
22871 {
22872 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22874 },
22875 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
22876 {
22877 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22879 },
22880 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
22881 {
22882 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22884 },
22885 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
22886 {
22887 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22889 },
22890 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
22891 {
22892 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22894 },
22895 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
22896 {
22897 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22899 },
22900 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
22901 {
22902 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22904 },
22905 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
22906 {
22907 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22909 },
22910 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
22911 {
22912 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22914 },
22915 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
22916 {
22917 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22919 },
22920 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
22921 {
22922 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22924 },
22925 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
22926 {
22927 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22929 },
22930 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
22931 {
22932 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22934 },
22935 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
22936 {
22937 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22939 },
22940 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
22941 {
22942 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22944 },
22945 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22946 {
22947 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22949 },
22950 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22951 {
22952 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22954 },
22955 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22956 {
22957 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22959 },
22960 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22961 {
22962 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22964 },
22965 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22966 {
22967 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22969 },
22970 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22971 {
22972 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22974 },
22975 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22976 {
22977 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
22978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22979 },
22980 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22981 {
22982 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
22983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22984 },
22985 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22986 {
22987 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
22988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22989 },
22990 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22991 {
22992 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
22993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22994 },
22995 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22996 {
22997 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
22998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22999 },
23000 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23001 {
23002 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
23003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23004 },
23005 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
23006 {
23007 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23009 },
23010 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23011 {
23012 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23014 },
23015 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23016 {
23017 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23019 },
23020 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
23021 {
23022 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23024 },
23025 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23026 {
23027 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23029 },
23030 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23031 {
23032 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23034 },
23035 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
23036 {
23037 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23039 },
23040 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23041 {
23042 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23044 },
23045 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23046 {
23047 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23049 },
23050 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
23051 {
23052 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23054 },
23055 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
23056 {
23057 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23059 },
23060 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
23061 {
23062 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23064 },
23065 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
23066 {
23067 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23069 },
23070 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23071 {
23072 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23074 },
23075 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23076 {
23077 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23079 },
23080 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
23081 {
23082 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23084 },
23085 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
23086 {
23087 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23089 },
23090 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
23091 {
23092 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23094 },
23095 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23096 {
23097 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23099 },
23100 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
23101 {
23102 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23104 },
23105 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
23106 {
23107 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23109 },
23110 /* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
23111 {
23112 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23114 },
23115 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23116 {
23117 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23119 },
23120 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
23121 {
23122 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23124 },
23125 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
23126 {
23127 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23129 },
23130 /* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
23131 {
23132 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23134 },
23135 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23136 {
23137 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23139 },
23140 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
23141 {
23142 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23144 },
23145 /* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
23146 {
23147 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23149 },
23150 /* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
23151 {
23152 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23154 },
23155 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23156 {
23157 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23159 },
23160 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23161 {
23162 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23164 },
23165 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23166 {
23167 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23169 },
23170 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
23171 {
23172 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23174 },
23175 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23176 {
23177 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23179 },
23180 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23181 {
23182 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23184 },
23185 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23186 {
23187 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23189 },
23190 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
23191 {
23192 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23194 },
23195 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23196 {
23197 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23199 },
23200 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23201 {
23202 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23204 },
23205 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23206 {
23207 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23209 },
23210 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
23211 {
23212 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23214 },
23215 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
23216 {
23217 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23219 },
23220 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23221 {
23222 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23224 },
23225 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
23226 {
23227 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23229 },
23230 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23231 {
23232 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23234 },
23235 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
23236 {
23237 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23239 },
23240 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23241 {
23242 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23244 },
23245 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
23246 {
23247 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23249 },
23250 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23251 {
23252 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23254 },
23255 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
23256 {
23257 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23259 },
23260 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23261 {
23262 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23264 },
23265 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
23266 {
23267 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23269 },
23270 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23271 {
23272 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23274 },
23275 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
23276 {
23277 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23279 },
23280 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
23281 {
23282 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23284 },
23285 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
23286 {
23287 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23289 },
23290 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
23291 {
23292 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23294 },
23295 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
23296 {
23297 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23299 },
23300 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23301 {
23302 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23304 },
23305 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
23306 {
23307 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23309 },
23310 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
23311 {
23312 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23314 },
23315 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
23316 {
23317 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23319 },
23320 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
23321 {
23322 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23324 },
23325 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
23326 {
23327 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23329 },
23330 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
23331 {
23332 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23334 },
23335 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23336 {
23337 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23339 },
23340 /* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
23341 {
23342 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23344 },
23345 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23346 {
23347 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23349 },
23350 /* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
23351 {
23352 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23354 },
23355 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23356 {
23357 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23359 },
23360 /* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
23361 {
23362 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23364 },
23365 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
23366 {
23367 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23369 },
23370 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
23371 {
23372 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23374 },
23375 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
23376 {
23377 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23379 },
23380 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
23381 {
23382 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23384 },
23385 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
23386 {
23387 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23389 },
23390 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
23391 {
23392 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23394 },
23395 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
23396 {
23397 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23399 },
23400 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
23401 {
23402 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23404 },
23405 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
23406 {
23407 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23409 },
23410 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
23411 {
23412 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23414 },
23415 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
23416 {
23417 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23419 },
23420 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
23421 {
23422 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23424 },
23425 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
23426 {
23427 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23429 },
23430 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
23431 {
23432 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23434 },
23435 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
23436 {
23437 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23439 },
23440 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
23441 {
23442 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23444 },
23445 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
23446 {
23447 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23449 },
23450 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
23451 {
23452 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23454 },
23455 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
23456 {
23457 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23459 },
23460 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
23461 {
23462 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23464 },
23465 /* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23466 {
23467 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23469 },
23470 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
23471 {
23472 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23474 },
23475 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
23476 {
23477 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23479 },
23480 /* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23481 {
23482 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23484 },
23485 /* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
23486 {
23487 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23489 },
23490 /* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
23491 {
23492 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23494 },
23495 /* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23496 {
23497 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23499 },
23500 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23501 {
23502 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23504 },
23505 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23506 {
23507 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23509 },
23510 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
23511 {
23512 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23514 },
23515 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23516 {
23517 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23519 },
23520 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23521 {
23522 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23524 },
23525 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
23526 {
23527 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23529 },
23530 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23531 {
23532 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23534 },
23535 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23536 {
23537 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23539 },
23540 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
23541 {
23542 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23544 },
23545 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
23546 {
23547 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23549 },
23550 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
23551 {
23552 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23554 },
23555 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
23556 {
23557 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23559 },
23560 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
23561 {
23562 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23564 },
23565 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
23566 {
23567 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23569 },
23570 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
23571 {
23572 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23574 },
23575 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
23576 {
23577 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23579 },
23580 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
23581 {
23582 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23584 },
23585 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
23586 {
23587 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23589 },
23590 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
23591 {
23592 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23594 },
23595 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
23596 {
23597 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23599 },
23600 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
23601 {
23602 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23604 },
23605 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
23606 {
23607 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23609 },
23610 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
23611 {
23612 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23614 },
23615 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
23616 {
23617 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23619 },
23620 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
23621 {
23622 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23624 },
23625 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
23626 {
23627 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23629 },
23630 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
23631 {
23632 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23634 },
23635 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
23636 {
23637 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23639 },
23640 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
23641 {
23642 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23644 },
23645 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
23646 {
23647 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23649 },
23650 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
23651 {
23652 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23654 },
23655 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
23656 {
23657 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23659 },
23660 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
23661 {
23662 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23664 },
23665 /* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
23666 {
23667 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23669 },
23670 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
23671 {
23672 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23674 },
23675 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
23676 {
23677 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23679 },
23680 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
23681 {
23682 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23684 },
23685 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
23686 {
23687 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23689 },
23690 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
23691 {
23692 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23694 },
23695 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
23696 {
23697 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23699 },
23700 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
23701 {
23702 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23704 },
23705 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
23706 {
23707 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23709 },
23710 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
23711 {
23712 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23714 },
23715 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23716 {
23717 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23719 },
23720 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23721 {
23722 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23724 },
23725 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
23726 {
23727 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23729 },
23730 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23731 {
23732 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23734 },
23735 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23736 {
23737 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23739 },
23740 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
23741 {
23742 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23744 },
23745 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23746 {
23747 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23749 },
23750 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23751 {
23752 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23754 },
23755 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
23756 {
23757 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23759 },
23760 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23761 {
23762 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23764 },
23765 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23766 {
23767 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23769 },
23770 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
23771 {
23772 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23774 },
23775 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
23776 {
23777 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23779 },
23780 /* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
23781 {
23782 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32,
23783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23784 },
23785 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
23786 {
23787 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23789 },
23790 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
23791 {
23792 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23794 },
23795 /* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
23796 {
23797 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32,
23798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23799 },
23800 /* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
23801 {
23802 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23804 },
23805 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
23806 {
23807 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23809 },
23810 /* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
23811 {
23812 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32,
23813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23814 },
23815 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
23816 {
23817 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23819 },
23820 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
23821 {
23822 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23824 },
23825 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
23826 {
23827 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23829 },
23830 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
23831 {
23832 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23834 },
23835 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
23836 {
23837 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23839 },
23840 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
23841 {
23842 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23844 },
23845 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
23846 {
23847 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23849 },
23850 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23851 {
23852 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23854 },
23855 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23856 {
23857 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23859 },
23860 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
23861 {
23862 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23864 },
23865 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23866 {
23867 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23869 },
23870 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23871 {
23872 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23874 },
23875 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
23876 {
23877 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23879 },
23880 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23881 {
23882 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23884 },
23885 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23886 {
23887 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23889 },
23890 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
23891 {
23892 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23894 },
23895 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23896 {
23897 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23899 },
23900 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
23901 {
23902 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23904 },
23905 /* mul.w${G} $Src16RnHI,$Dst16RnHI */
23906 {
23907 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23909 },
23910 /* mul.w${G} $Src16AnHI,$Dst16RnHI */
23911 {
23912 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23914 },
23915 /* mul.w${G} [$Src16An],$Dst16RnHI */
23916 {
23917 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16,
23918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23919 },
23920 /* mul.w${G} $Src16RnHI,$Dst16AnHI */
23921 {
23922 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23924 },
23925 /* mul.w${G} $Src16AnHI,$Dst16AnHI */
23926 {
23927 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23929 },
23930 /* mul.w${G} [$Src16An],$Dst16AnHI */
23931 {
23932 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16,
23933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23934 },
23935 /* mul.w${G} $Src16RnHI,[$Dst16An] */
23936 {
23937 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23939 },
23940 /* mul.w${G} $Src16AnHI,[$Dst16An] */
23941 {
23942 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23944 },
23945 /* mul.w${G} [$Src16An],[$Dst16An] */
23946 {
23947 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16,
23948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23949 },
23950 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
23951 {
23952 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23954 },
23955 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
23956 {
23957 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23959 },
23960 /* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
23961 {
23962 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23964 },
23965 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
23966 {
23967 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23969 },
23970 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
23971 {
23972 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23974 },
23975 /* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
23976 {
23977 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23979 },
23980 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
23981 {
23982 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
23983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23984 },
23985 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
23986 {
23987 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
23988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23989 },
23990 /* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
23991 {
23992 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
23993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23994 },
23995 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
23996 {
23997 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
23998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23999 },
24000 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
24001 {
24002 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24004 },
24005 /* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
24006 {
24007 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24009 },
24010 /* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
24011 {
24012 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24014 },
24015 /* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
24016 {
24017 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24019 },
24020 /* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
24021 {
24022 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24024 },
24025 /* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
24026 {
24027 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24029 },
24030 /* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
24031 {
24032 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24034 },
24035 /* mul.w${G} [$Src16An],${Dsp-16-u16} */
24036 {
24037 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24039 },
24040 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
24041 {
24042 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24044 },
24045 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
24046 {
24047 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24049 },
24050 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
24051 {
24052 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24054 },
24055 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
24056 {
24057 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24059 },
24060 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
24061 {
24062 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24064 },
24065 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
24066 {
24067 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24069 },
24070 /* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
24071 {
24072 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24074 },
24075 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
24076 {
24077 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24079 },
24080 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
24081 {
24082 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24084 },
24085 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
24086 {
24087 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24089 },
24090 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
24091 {
24092 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24094 },
24095 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
24096 {
24097 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24099 },
24100 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
24101 {
24102 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24104 },
24105 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
24106 {
24107 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24109 },
24110 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
24111 {
24112 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24114 },
24115 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
24116 {
24117 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24119 },
24120 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24121 {
24122 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24124 },
24125 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24126 {
24127 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24129 },
24130 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
24131 {
24132 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24134 },
24135 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24136 {
24137 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24139 },
24140 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24141 {
24142 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24144 },
24145 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
24146 {
24147 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24149 },
24150 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24151 {
24152 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24154 },
24155 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24156 {
24157 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24159 },
24160 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
24161 {
24162 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24164 },
24165 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24166 {
24167 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24169 },
24170 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24171 {
24172 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24174 },
24175 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
24176 {
24177 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24179 },
24180 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
24181 {
24182 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24184 },
24185 /* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
24186 {
24187 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32,
24188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24189 },
24190 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
24191 {
24192 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24194 },
24195 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
24196 {
24197 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24199 },
24200 /* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
24201 {
24202 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32,
24203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24204 },
24205 /* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
24206 {
24207 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24209 },
24210 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
24211 {
24212 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24214 },
24215 /* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
24216 {
24217 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32,
24218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24219 },
24220 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
24221 {
24222 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24224 },
24225 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
24226 {
24227 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24229 },
24230 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
24231 {
24232 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24234 },
24235 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
24236 {
24237 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24239 },
24240 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
24241 {
24242 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24244 },
24245 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
24246 {
24247 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24249 },
24250 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
24251 {
24252 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24254 },
24255 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
24256 {
24257 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24259 },
24260 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
24261 {
24262 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24264 },
24265 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
24266 {
24267 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24269 },
24270 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
24271 {
24272 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24274 },
24275 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
24276 {
24277 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24279 },
24280 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
24281 {
24282 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24284 },
24285 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
24286 {
24287 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24289 },
24290 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
24291 {
24292 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24294 },
24295 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
24296 {
24297 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24299 },
24300 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
24301 {
24302 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24304 },
24305 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
24306 {
24307 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24309 },
24310 /* mul.b${G} $Src16RnQI,$Dst16RnQI */
24311 {
24312 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24314 },
24315 /* mul.b${G} $Src16AnQI,$Dst16RnQI */
24316 {
24317 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24319 },
24320 /* mul.b${G} [$Src16An],$Dst16RnQI */
24321 {
24322 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16,
24323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24324 },
24325 /* mul.b${G} $Src16RnQI,$Dst16AnQI */
24326 {
24327 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24329 },
24330 /* mul.b${G} $Src16AnQI,$Dst16AnQI */
24331 {
24332 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24334 },
24335 /* mul.b${G} [$Src16An],$Dst16AnQI */
24336 {
24337 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16,
24338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24339 },
24340 /* mul.b${G} $Src16RnQI,[$Dst16An] */
24341 {
24342 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24344 },
24345 /* mul.b${G} $Src16AnQI,[$Dst16An] */
24346 {
24347 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24349 },
24350 /* mul.b${G} [$Src16An],[$Dst16An] */
24351 {
24352 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16,
24353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24354 },
24355 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
24356 {
24357 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24359 },
24360 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
24361 {
24362 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24364 },
24365 /* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
24366 {
24367 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24369 },
24370 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
24371 {
24372 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24374 },
24375 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
24376 {
24377 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24379 },
24380 /* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
24381 {
24382 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24384 },
24385 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
24386 {
24387 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24389 },
24390 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
24391 {
24392 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24394 },
24395 /* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
24396 {
24397 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24399 },
24400 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
24401 {
24402 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24404 },
24405 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
24406 {
24407 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24409 },
24410 /* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
24411 {
24412 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24414 },
24415 /* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
24416 {
24417 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24419 },
24420 /* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
24421 {
24422 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24424 },
24425 /* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
24426 {
24427 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24429 },
24430 /* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
24431 {
24432 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24434 },
24435 /* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
24436 {
24437 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24439 },
24440 /* mul.b${G} [$Src16An],${Dsp-16-u16} */
24441 {
24442 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24444 },
24445 /* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
24446 {
24447 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
24448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24449 },
24450 /* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
24451 {
24452 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
24453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24454 },
24455 /* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
24456 {
24457 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
24458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24459 },
24460 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24461 {
24462 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40,
24463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24464 },
24465 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24466 {
24467 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40,
24468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24469 },
24470 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24471 {
24472 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40,
24473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24474 },
24475 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24476 {
24477 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48,
24478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24479 },
24480 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24481 {
24482 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48,
24483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24484 },
24485 /* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
24486 {
24487 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48,
24488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24489 },
24490 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24491 {
24492 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48,
24493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24494 },
24495 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24496 {
24497 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56,
24498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24499 },
24500 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
24501 {
24502 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56,
24503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24504 },
24505 /* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
24506 {
24507 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
24508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24509 },
24510 /* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
24511 {
24512 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
24513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24514 },
24515 /* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24516 {
24517 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
24518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24519 },
24520 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24521 {
24522 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32,
24523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24524 },
24525 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24526 {
24527 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32,
24528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24529 },
24530 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24531 {
24532 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32,
24533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24534 },
24535 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24536 {
24537 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40,
24538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24539 },
24540 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24541 {
24542 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40,
24543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24544 },
24545 /* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24546 {
24547 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40,
24548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24549 },
24550 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24551 {
24552 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40,
24553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24554 },
24555 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24556 {
24557 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48,
24558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24559 },
24560 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
24561 {
24562 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48,
24563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24564 },
24565 /* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
24566 {
24567 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32,
24568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24569 },
24570 /* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
24571 {
24572 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32,
24573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24574 },
24575 /* mul.w${G} #${Imm-16-HI},[$Dst16An] */
24576 {
24577 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32,
24578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24579 },
24580 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
24581 {
24582 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40,
24583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24584 },
24585 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24586 {
24587 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40,
24588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24589 },
24590 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24591 {
24592 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40,
24593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24594 },
24595 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
24596 {
24597 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48,
24598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24599 },
24600 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24601 {
24602 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48,
24603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24604 },
24605 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24606 {
24607 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48,
24608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24609 },
24610 /* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
24611 {
24612 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24,
24613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24614 },
24615 /* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
24616 {
24617 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24,
24618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24619 },
24620 /* mul.b${G} #${Imm-16-QI},[$Dst16An] */
24621 {
24622 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24,
24623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24624 },
24625 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
24626 {
24627 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32,
24628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24629 },
24630 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24631 {
24632 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32,
24633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24634 },
24635 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24636 {
24637 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32,
24638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24639 },
24640 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
24641 {
24642 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40,
24643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24644 },
24645 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24646 {
24647 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40,
24648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24649 },
24650 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24651 {
24652 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40,
24653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24654 },
24655 /* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
24656 {
24657 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24,
24658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24659 },
24660 /* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
24661 {
24662 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24,
24663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24664 },
24665 /* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24666 {
24667 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24,
24668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24669 },
24670 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24671 {
24672 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32,
24673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24674 },
24675 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24676 {
24677 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32,
24678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24679 },
24680 /* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24681 {
24682 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32,
24683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24684 },
24685 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24686 {
24687 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40,
24688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24689 },
24690 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24691 {
24692 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40,
24693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24694 },
24695 /* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24696 {
24697 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40,
24698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24699 },
24700 /* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
24701 {
24702 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40,
24703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24704 },
24705 /* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24706 {
24707 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48,
24708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24709 },
24710 /* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
24711 {
24712 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48,
24713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24714 },
24715 /* movhh $Dst32RnPrefixedQI,r0l */
24716 {
24717 M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24719 },
24720 /* movhh $Dst32AnPrefixedQI,r0l */
24721 {
24722 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24,
24723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24724 },
24725 /* movhh [$Dst32AnPrefixed],r0l */
24726 {
24727 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24,
24728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24729 },
24730 /* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24731 {
24732 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
24733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24734 },
24735 /* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24736 {
24737 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
24738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24739 },
24740 /* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24741 {
24742 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
24743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24744 },
24745 /* movhh ${Dsp-24-u8}[sb],r0l */
24746 {
24747 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
24748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24749 },
24750 /* movhh ${Dsp-24-u16}[sb],r0l */
24751 {
24752 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
24753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24754 },
24755 /* movhh ${Dsp-24-s8}[fb],r0l */
24756 {
24757 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
24758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24759 },
24760 /* movhh ${Dsp-24-s16}[fb],r0l */
24761 {
24762 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
24763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24764 },
24765 /* movhh ${Dsp-24-u16},r0l */
24766 {
24767 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
24768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24769 },
24770 /* movhh ${Dsp-24-u24},r0l */
24771 {
24772 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
24773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24774 },
24775 /* movhl $Dst32RnPrefixedQI,r0l */
24776 {
24777 M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
24778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24779 },
24780 /* movhl $Dst32AnPrefixedQI,r0l */
24781 {
24782 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24,
24783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24784 },
24785 /* movhl [$Dst32AnPrefixed],r0l */
24786 {
24787 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24,
24788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24789 },
24790 /* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24791 {
24792 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
24793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24794 },
24795 /* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24796 {
24797 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
24798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24799 },
24800 /* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24801 {
24802 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
24803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24804 },
24805 /* movhl ${Dsp-24-u8}[sb],r0l */
24806 {
24807 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
24808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24809 },
24810 /* movhl ${Dsp-24-u16}[sb],r0l */
24811 {
24812 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
24813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24814 },
24815 /* movhl ${Dsp-24-s8}[fb],r0l */
24816 {
24817 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
24818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24819 },
24820 /* movhl ${Dsp-24-s16}[fb],r0l */
24821 {
24822 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
24823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24824 },
24825 /* movhl ${Dsp-24-u16},r0l */
24826 {
24827 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
24828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24829 },
24830 /* movhl ${Dsp-24-u24},r0l */
24831 {
24832 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
24833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24834 },
24835 /* movlh $Dst32RnPrefixedQI,r0l */
24836 {
24837 M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
24838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24839 },
24840 /* movlh $Dst32AnPrefixedQI,r0l */
24841 {
24842 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24,
24843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24844 },
24845 /* movlh [$Dst32AnPrefixed],r0l */
24846 {
24847 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24,
24848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24849 },
24850 /* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24851 {
24852 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
24853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24854 },
24855 /* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24856 {
24857 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
24858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24859 },
24860 /* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24861 {
24862 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
24863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24864 },
24865 /* movlh ${Dsp-24-u8}[sb],r0l */
24866 {
24867 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
24868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24869 },
24870 /* movlh ${Dsp-24-u16}[sb],r0l */
24871 {
24872 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
24873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24874 },
24875 /* movlh ${Dsp-24-s8}[fb],r0l */
24876 {
24877 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
24878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24879 },
24880 /* movlh ${Dsp-24-s16}[fb],r0l */
24881 {
24882 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
24883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24884 },
24885 /* movlh ${Dsp-24-u16},r0l */
24886 {
24887 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
24888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24889 },
24890 /* movlh ${Dsp-24-u24},r0l */
24891 {
24892 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
24893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24894 },
24895 /* movll $Dst32RnPrefixedQI,r0l */
24896 {
24897 M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24,
24898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24899 },
24900 /* movll $Dst32AnPrefixedQI,r0l */
24901 {
24902 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24,
24903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24904 },
24905 /* movll [$Dst32AnPrefixed],r0l */
24906 {
24907 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24,
24908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24909 },
24910 /* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24911 {
24912 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
24913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24914 },
24915 /* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24916 {
24917 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
24918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24919 },
24920 /* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24921 {
24922 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
24923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24924 },
24925 /* movll ${Dsp-24-u8}[sb],r0l */
24926 {
24927 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
24928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24929 },
24930 /* movll ${Dsp-24-u16}[sb],r0l */
24931 {
24932 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
24933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24934 },
24935 /* movll ${Dsp-24-s8}[fb],r0l */
24936 {
24937 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
24938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24939 },
24940 /* movll ${Dsp-24-s16}[fb],r0l */
24941 {
24942 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
24943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24944 },
24945 /* movll ${Dsp-24-u16},r0l */
24946 {
24947 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
24948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24949 },
24950 /* movll ${Dsp-24-u24},r0l */
24951 {
24952 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
24953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24954 },
24955 /* movhh r0l,$Dst32RnPrefixedQI */
24956 {
24957 M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24959 },
24960 /* movhh r0l,$Dst32AnPrefixedQI */
24961 {
24962 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24,
24963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24964 },
24965 /* movhh r0l,[$Dst32AnPrefixed] */
24966 {
24967 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24,
24968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24969 },
24970 /* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
24971 {
24972 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
24973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24974 },
24975 /* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
24976 {
24977 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
24978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24979 },
24980 /* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
24981 {
24982 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
24983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24984 },
24985 /* movhh r0l,${Dsp-24-u8}[sb] */
24986 {
24987 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
24988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24989 },
24990 /* movhh r0l,${Dsp-24-u16}[sb] */
24991 {
24992 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
24993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24994 },
24995 /* movhh r0l,${Dsp-24-s8}[fb] */
24996 {
24997 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
24998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24999 },
25000 /* movhh r0l,${Dsp-24-s16}[fb] */
25001 {
25002 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
25003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25004 },
25005 /* movhh r0l,${Dsp-24-u16} */
25006 {
25007 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
25008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25009 },
25010 /* movhh r0l,${Dsp-24-u24} */
25011 {
25012 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
25013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25014 },
25015 /* movhl r0l,$Dst32RnPrefixedQI */
25016 {
25017 M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
25018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25019 },
25020 /* movhl r0l,$Dst32AnPrefixedQI */
25021 {
25022 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24,
25023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25024 },
25025 /* movhl r0l,[$Dst32AnPrefixed] */
25026 {
25027 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24,
25028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25029 },
25030 /* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25031 {
25032 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
25033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25034 },
25035 /* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25036 {
25037 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
25038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25039 },
25040 /* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25041 {
25042 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
25043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25044 },
25045 /* movhl r0l,${Dsp-24-u8}[sb] */
25046 {
25047 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
25048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25049 },
25050 /* movhl r0l,${Dsp-24-u16}[sb] */
25051 {
25052 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
25053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25054 },
25055 /* movhl r0l,${Dsp-24-s8}[fb] */
25056 {
25057 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
25058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25059 },
25060 /* movhl r0l,${Dsp-24-s16}[fb] */
25061 {
25062 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
25063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25064 },
25065 /* movhl r0l,${Dsp-24-u16} */
25066 {
25067 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
25068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25069 },
25070 /* movhl r0l,${Dsp-24-u24} */
25071 {
25072 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
25073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25074 },
25075 /* movlh r0l,$Dst32RnPrefixedQI */
25076 {
25077 M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
25078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25079 },
25080 /* movlh r0l,$Dst32AnPrefixedQI */
25081 {
25082 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24,
25083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25084 },
25085 /* movlh r0l,[$Dst32AnPrefixed] */
25086 {
25087 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24,
25088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25089 },
25090 /* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25091 {
25092 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
25093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25094 },
25095 /* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25096 {
25097 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
25098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25099 },
25100 /* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25101 {
25102 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
25103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25104 },
25105 /* movlh r0l,${Dsp-24-u8}[sb] */
25106 {
25107 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
25108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25109 },
25110 /* movlh r0l,${Dsp-24-u16}[sb] */
25111 {
25112 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
25113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25114 },
25115 /* movlh r0l,${Dsp-24-s8}[fb] */
25116 {
25117 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
25118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25119 },
25120 /* movlh r0l,${Dsp-24-s16}[fb] */
25121 {
25122 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
25123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25124 },
25125 /* movlh r0l,${Dsp-24-u16} */
25126 {
25127 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
25128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25129 },
25130 /* movlh r0l,${Dsp-24-u24} */
25131 {
25132 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
25133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25134 },
25135 /* movll r0l,$Dst32RnPrefixedQI */
25136 {
25137 M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24,
25138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25139 },
25140 /* movll r0l,$Dst32AnPrefixedQI */
25141 {
25142 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24,
25143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25144 },
25145 /* movll r0l,[$Dst32AnPrefixed] */
25146 {
25147 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24,
25148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25149 },
25150 /* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25151 {
25152 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
25153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25154 },
25155 /* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25156 {
25157 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
25158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25159 },
25160 /* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25161 {
25162 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
25163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25164 },
25165 /* movll r0l,${Dsp-24-u8}[sb] */
25166 {
25167 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
25168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25169 },
25170 /* movll r0l,${Dsp-24-u16}[sb] */
25171 {
25172 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
25173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25174 },
25175 /* movll r0l,${Dsp-24-s8}[fb] */
25176 {
25177 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
25178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25179 },
25180 /* movll r0l,${Dsp-24-s16}[fb] */
25181 {
25182 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
25183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25184 },
25185 /* movll r0l,${Dsp-24-u16} */
25186 {
25187 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
25188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25189 },
25190 /* movll r0l,${Dsp-24-u24} */
25191 {
25192 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
25193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25194 },
25195 /* movhh $Dst16RnQI,r0l */
25196 {
25197 M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16,
25198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25199 },
25200 /* movhh $Dst16AnQI,r0l */
25201 {
25202 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16,
25203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25204 },
25205 /* movhh [$Dst16An],r0l */
25206 {
25207 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16,
25208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25209 },
25210 /* movhh ${Dsp-16-u8}[$Dst16An],r0l */
25211 {
25212 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24,
25213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25214 },
25215 /* movhh ${Dsp-16-u16}[$Dst16An],r0l */
25216 {
25217 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32,
25218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25219 },
25220 /* movhh ${Dsp-16-u8}[sb],r0l */
25221 {
25222 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24,
25223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25224 },
25225 /* movhh ${Dsp-16-u16}[sb],r0l */
25226 {
25227 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32,
25228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25229 },
25230 /* movhh ${Dsp-16-s8}[fb],r0l */
25231 {
25232 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24,
25233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25234 },
25235 /* movhh ${Dsp-16-u16},r0l */
25236 {
25237 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32,
25238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25239 },
25240 /* movhl $Dst16RnQI,r0l */
25241 {
25242 M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16,
25243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25244 },
25245 /* movhl $Dst16AnQI,r0l */
25246 {
25247 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16,
25248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25249 },
25250 /* movhl [$Dst16An],r0l */
25251 {
25252 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16,
25253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25254 },
25255 /* movhl ${Dsp-16-u8}[$Dst16An],r0l */
25256 {
25257 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24,
25258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25259 },
25260 /* movhl ${Dsp-16-u16}[$Dst16An],r0l */
25261 {
25262 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32,
25263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25264 },
25265 /* movhl ${Dsp-16-u8}[sb],r0l */
25266 {
25267 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24,
25268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25269 },
25270 /* movhl ${Dsp-16-u16}[sb],r0l */
25271 {
25272 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32,
25273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25274 },
25275 /* movhl ${Dsp-16-s8}[fb],r0l */
25276 {
25277 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24,
25278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25279 },
25280 /* movhl ${Dsp-16-u16},r0l */
25281 {
25282 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32,
25283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25284 },
25285 /* movlh $Dst16RnQI,r0l */
25286 {
25287 M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16,
25288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25289 },
25290 /* movlh $Dst16AnQI,r0l */
25291 {
25292 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16,
25293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25294 },
25295 /* movlh [$Dst16An],r0l */
25296 {
25297 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16,
25298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25299 },
25300 /* movlh ${Dsp-16-u8}[$Dst16An],r0l */
25301 {
25302 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24,
25303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25304 },
25305 /* movlh ${Dsp-16-u16}[$Dst16An],r0l */
25306 {
25307 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32,
25308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25309 },
25310 /* movlh ${Dsp-16-u8}[sb],r0l */
25311 {
25312 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24,
25313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25314 },
25315 /* movlh ${Dsp-16-u16}[sb],r0l */
25316 {
25317 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32,
25318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25319 },
25320 /* movlh ${Dsp-16-s8}[fb],r0l */
25321 {
25322 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24,
25323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25324 },
25325 /* movlh ${Dsp-16-u16},r0l */
25326 {
25327 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32,
25328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25329 },
25330 /* movll $Dst16RnQI,r0l */
25331 {
25332 M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16,
25333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25334 },
25335 /* movll $Dst16AnQI,r0l */
25336 {
25337 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16,
25338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25339 },
25340 /* movll [$Dst16An],r0l */
25341 {
25342 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16,
25343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25344 },
25345 /* movll ${Dsp-16-u8}[$Dst16An],r0l */
25346 {
25347 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24,
25348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25349 },
25350 /* movll ${Dsp-16-u16}[$Dst16An],r0l */
25351 {
25352 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32,
25353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25354 },
25355 /* movll ${Dsp-16-u8}[sb],r0l */
25356 {
25357 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24,
25358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25359 },
25360 /* movll ${Dsp-16-u16}[sb],r0l */
25361 {
25362 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32,
25363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25364 },
25365 /* movll ${Dsp-16-s8}[fb],r0l */
25366 {
25367 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24,
25368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25369 },
25370 /* movll ${Dsp-16-u16},r0l */
25371 {
25372 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32,
25373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25374 },
25375 /* movhh r0l,$Dst16RnQI */
25376 {
25377 M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16,
25378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25379 },
25380 /* movhh r0l,$Dst16AnQI */
25381 {
25382 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16,
25383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25384 },
25385 /* movhh r0l,[$Dst16An] */
25386 {
25387 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16,
25388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25389 },
25390 /* movhh r0l,${Dsp-16-u8}[$Dst16An] */
25391 {
25392 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24,
25393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25394 },
25395 /* movhh r0l,${Dsp-16-u16}[$Dst16An] */
25396 {
25397 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32,
25398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25399 },
25400 /* movhh r0l,${Dsp-16-u8}[sb] */
25401 {
25402 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24,
25403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25404 },
25405 /* movhh r0l,${Dsp-16-u16}[sb] */
25406 {
25407 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32,
25408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25409 },
25410 /* movhh r0l,${Dsp-16-s8}[fb] */
25411 {
25412 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24,
25413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25414 },
25415 /* movhh r0l,${Dsp-16-u16} */
25416 {
25417 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32,
25418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25419 },
25420 /* movhl r0l,$Dst16RnQI */
25421 {
25422 M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16,
25423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25424 },
25425 /* movhl r0l,$Dst16AnQI */
25426 {
25427 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16,
25428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25429 },
25430 /* movhl r0l,[$Dst16An] */
25431 {
25432 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16,
25433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25434 },
25435 /* movhl r0l,${Dsp-16-u8}[$Dst16An] */
25436 {
25437 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24,
25438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25439 },
25440 /* movhl r0l,${Dsp-16-u16}[$Dst16An] */
25441 {
25442 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32,
25443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25444 },
25445 /* movhl r0l,${Dsp-16-u8}[sb] */
25446 {
25447 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24,
25448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25449 },
25450 /* movhl r0l,${Dsp-16-u16}[sb] */
25451 {
25452 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32,
25453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25454 },
25455 /* movhl r0l,${Dsp-16-s8}[fb] */
25456 {
25457 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24,
25458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25459 },
25460 /* movhl r0l,${Dsp-16-u16} */
25461 {
25462 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32,
25463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25464 },
25465 /* movlh r0l,$Dst16RnQI */
25466 {
25467 M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16,
25468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25469 },
25470 /* movlh r0l,$Dst16AnQI */
25471 {
25472 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16,
25473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25474 },
25475 /* movlh r0l,[$Dst16An] */
25476 {
25477 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16,
25478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25479 },
25480 /* movlh r0l,${Dsp-16-u8}[$Dst16An] */
25481 {
25482 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24,
25483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25484 },
25485 /* movlh r0l,${Dsp-16-u16}[$Dst16An] */
25486 {
25487 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32,
25488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25489 },
25490 /* movlh r0l,${Dsp-16-u8}[sb] */
25491 {
25492 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24,
25493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25494 },
25495 /* movlh r0l,${Dsp-16-u16}[sb] */
25496 {
25497 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32,
25498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25499 },
25500 /* movlh r0l,${Dsp-16-s8}[fb] */
25501 {
25502 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24,
25503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25504 },
25505 /* movlh r0l,${Dsp-16-u16} */
25506 {
25507 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32,
25508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25509 },
25510 /* movll r0l,$Dst16RnQI */
25511 {
25512 M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16,
25513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25514 },
25515 /* movll r0l,$Dst16AnQI */
25516 {
25517 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16,
25518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25519 },
25520 /* movll r0l,[$Dst16An] */
25521 {
25522 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16,
25523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25524 },
25525 /* movll r0l,${Dsp-16-u8}[$Dst16An] */
25526 {
25527 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24,
25528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25529 },
25530 /* movll r0l,${Dsp-16-u16}[$Dst16An] */
25531 {
25532 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32,
25533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25534 },
25535 /* movll r0l,${Dsp-16-u8}[sb] */
25536 {
25537 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24,
25538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25539 },
25540 /* movll r0l,${Dsp-16-u16}[sb] */
25541 {
25542 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32,
25543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25544 },
25545 /* movll r0l,${Dsp-16-s8}[fb] */
25546 {
25547 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24,
25548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25549 },
25550 /* movll r0l,${Dsp-16-u16} */
25551 {
25552 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32,
25553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25554 },
25555 /* mova [$Dst32AnUnprefixed],a1 */
25556 {
25557 M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25559 },
25560 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
25561 {
25562 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25564 },
25565 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
25566 {
25567 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25569 },
25570 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
25571 {
25572 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25574 },
25575 /* mova ${Dsp-16-u8}[sb],a1 */
25576 {
25577 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25579 },
25580 /* mova ${Dsp-16-u16}[sb],a1 */
25581 {
25582 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25584 },
25585 /* mova ${Dsp-16-s8}[fb],a1 */
25586 {
25587 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25589 },
25590 /* mova ${Dsp-16-s16}[fb],a1 */
25591 {
25592 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25594 },
25595 /* mova ${Dsp-16-u16},a1 */
25596 {
25597 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25599 },
25600 /* mova ${Dsp-16-u24},a1 */
25601 {
25602 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25604 },
25605 /* mova [$Dst32AnUnprefixed],a0 */
25606 {
25607 M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25609 },
25610 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
25611 {
25612 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25614 },
25615 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
25616 {
25617 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25619 },
25620 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
25621 {
25622 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25624 },
25625 /* mova ${Dsp-16-u8}[sb],a0 */
25626 {
25627 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25629 },
25630 /* mova ${Dsp-16-u16}[sb],a0 */
25631 {
25632 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25634 },
25635 /* mova ${Dsp-16-s8}[fb],a0 */
25636 {
25637 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25639 },
25640 /* mova ${Dsp-16-s16}[fb],a0 */
25641 {
25642 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25644 },
25645 /* mova ${Dsp-16-u16},a0 */
25646 {
25647 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25649 },
25650 /* mova ${Dsp-16-u24},a0 */
25651 {
25652 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25654 },
25655 /* mova [$Dst32AnUnprefixed],r3r1 */
25656 {
25657 M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25659 },
25660 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
25661 {
25662 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25664 },
25665 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
25666 {
25667 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25669 },
25670 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
25671 {
25672 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25674 },
25675 /* mova ${Dsp-16-u8}[sb],r3r1 */
25676 {
25677 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25679 },
25680 /* mova ${Dsp-16-u16}[sb],r3r1 */
25681 {
25682 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25684 },
25685 /* mova ${Dsp-16-s8}[fb],r3r1 */
25686 {
25687 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25689 },
25690 /* mova ${Dsp-16-s16}[fb],r3r1 */
25691 {
25692 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25694 },
25695 /* mova ${Dsp-16-u16},r3r1 */
25696 {
25697 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25699 },
25700 /* mova ${Dsp-16-u24},r3r1 */
25701 {
25702 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25704 },
25705 /* mova [$Dst32AnUnprefixed],r2r0 */
25706 {
25707 M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25709 },
25710 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
25711 {
25712 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25714 },
25715 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
25716 {
25717 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25719 },
25720 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
25721 {
25722 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25724 },
25725 /* mova ${Dsp-16-u8}[sb],r2r0 */
25726 {
25727 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25729 },
25730 /* mova ${Dsp-16-u16}[sb],r2r0 */
25731 {
25732 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25734 },
25735 /* mova ${Dsp-16-s8}[fb],r2r0 */
25736 {
25737 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25739 },
25740 /* mova ${Dsp-16-s16}[fb],r2r0 */
25741 {
25742 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25744 },
25745 /* mova ${Dsp-16-u16},r2r0 */
25746 {
25747 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25749 },
25750 /* mova ${Dsp-16-u24},r2r0 */
25751 {
25752 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25754 },
25755 /* mova [$Dst16An],a1 */
25756 {
25757 M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16,
25758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25759 },
25760 /* mova ${Dsp-16-u8}[$Dst16An],a1 */
25761 {
25762 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25764 },
25765 /* mova ${Dsp-16-u16}[$Dst16An],a1 */
25766 {
25767 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25769 },
25770 /* mova ${Dsp-16-u8}[sb],a1 */
25771 {
25772 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25774 },
25775 /* mova ${Dsp-16-u16}[sb],a1 */
25776 {
25777 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25779 },
25780 /* mova ${Dsp-16-s8}[fb],a1 */
25781 {
25782 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25784 },
25785 /* mova ${Dsp-16-u16},a1 */
25786 {
25787 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25789 },
25790 /* mova [$Dst16An],a0 */
25791 {
25792 M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16,
25793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25794 },
25795 /* mova ${Dsp-16-u8}[$Dst16An],a0 */
25796 {
25797 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25799 },
25800 /* mova ${Dsp-16-u16}[$Dst16An],a0 */
25801 {
25802 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25804 },
25805 /* mova ${Dsp-16-u8}[sb],a0 */
25806 {
25807 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25809 },
25810 /* mova ${Dsp-16-u16}[sb],a0 */
25811 {
25812 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25814 },
25815 /* mova ${Dsp-16-s8}[fb],a0 */
25816 {
25817 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25819 },
25820 /* mova ${Dsp-16-u16},a0 */
25821 {
25822 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25824 },
25825 /* mova [$Dst16An],r3 */
25826 {
25827 M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16,
25828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25829 },
25830 /* mova ${Dsp-16-u8}[$Dst16An],r3 */
25831 {
25832 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25834 },
25835 /* mova ${Dsp-16-u16}[$Dst16An],r3 */
25836 {
25837 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25839 },
25840 /* mova ${Dsp-16-u8}[sb],r3 */
25841 {
25842 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25844 },
25845 /* mova ${Dsp-16-u16}[sb],r3 */
25846 {
25847 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25849 },
25850 /* mova ${Dsp-16-s8}[fb],r3 */
25851 {
25852 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25854 },
25855 /* mova ${Dsp-16-u16},r3 */
25856 {
25857 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32,
25858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25859 },
25860 /* mova [$Dst16An],r2 */
25861 {
25862 M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16,
25863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25864 },
25865 /* mova ${Dsp-16-u8}[$Dst16An],r2 */
25866 {
25867 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25869 },
25870 /* mova ${Dsp-16-u16}[$Dst16An],r2 */
25871 {
25872 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25874 },
25875 /* mova ${Dsp-16-u8}[sb],r2 */
25876 {
25877 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25879 },
25880 /* mova ${Dsp-16-u16}[sb],r2 */
25881 {
25882 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25884 },
25885 /* mova ${Dsp-16-s8}[fb],r2 */
25886 {
25887 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25889 },
25890 /* mova ${Dsp-16-u16},r2 */
25891 {
25892 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32,
25893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25894 },
25895 /* mova [$Dst16An],r1 */
25896 {
25897 M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16,
25898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25899 },
25900 /* mova ${Dsp-16-u8}[$Dst16An],r1 */
25901 {
25902 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25904 },
25905 /* mova ${Dsp-16-u16}[$Dst16An],r1 */
25906 {
25907 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25909 },
25910 /* mova ${Dsp-16-u8}[sb],r1 */
25911 {
25912 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25914 },
25915 /* mova ${Dsp-16-u16}[sb],r1 */
25916 {
25917 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25919 },
25920 /* mova ${Dsp-16-s8}[fb],r1 */
25921 {
25922 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25924 },
25925 /* mova ${Dsp-16-u16},r1 */
25926 {
25927 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25929 },
25930 /* mova [$Dst16An],r0 */
25931 {
25932 M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16,
25933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25934 },
25935 /* mova ${Dsp-16-u8}[$Dst16An],r0 */
25936 {
25937 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25939 },
25940 /* mova ${Dsp-16-u16}[$Dst16An],r0 */
25941 {
25942 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25944 },
25945 /* mova ${Dsp-16-u8}[sb],r0 */
25946 {
25947 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25949 },
25950 /* mova ${Dsp-16-u16}[sb],r0 */
25951 {
25952 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25954 },
25955 /* mova ${Dsp-16-s8}[fb],r0 */
25956 {
25957 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25959 },
25960 /* mova ${Dsp-16-u16},r0 */
25961 {
25962 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25964 },
25965 /* mov.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
25966 {
25967 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
25968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25969 },
25970 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
25971 {
25972 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
25973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25974 },
25975 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
25976 {
25977 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
25978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25979 },
25980 /* mov.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
25981 {
25982 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
25983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25984 },
25985 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
25986 {
25987 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
25988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25989 },
25990 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
25991 {
25992 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
25993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25994 },
25995 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
25996 {
25997 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
25998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25999 },
26000 /* mov.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
26001 {
26002 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
26003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26004 },
26005 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
26006 {
26007 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
26008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26009 },
26010 /* mov.w${G} $Dst32RnUnprefixedHI,${Dsp-16-s8}[sp] */
26011 {
26012 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26014 },
26015 /* mov.w${G} $Dst32AnUnprefixedHI,${Dsp-16-s8}[sp] */
26016 {
26017 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26019 },
26020 /* mov.w${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
26021 {
26022 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26024 },
26025 /* mov.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-s8}[sp] */
26026 {
26027 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26029 },
26030 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
26031 {
26032 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26034 },
26035 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
26036 {
26037 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26039 },
26040 /* mov.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-s8}[sp] */
26041 {
26042 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26044 },
26045 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
26046 {
26047 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26049 },
26050 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[sp] */
26051 {
26052 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26054 },
26055 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
26056 {
26057 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26059 },
26060 /* mov.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-s8}[sp] */
26061 {
26062 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26064 },
26065 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[sp] */
26066 {
26067 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26069 },
26070 /* mov.b${G} $Dst32RnUnprefixedQI,${Dsp-16-s8}[sp] */
26071 {
26072 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26074 },
26075 /* mov.b${G} $Dst32AnUnprefixedQI,${Dsp-16-s8}[sp] */
26076 {
26077 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26079 },
26080 /* mov.b${G} [$Dst32AnUnprefixed],${Dsp-16-s8}[sp] */
26081 {
26082 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26084 },
26085 /* mov.w${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
26086 {
26087 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26089 },
26090 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
26091 {
26092 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26094 },
26095 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
26096 {
26097 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26099 },
26100 /* mov.w${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
26101 {
26102 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26104 },
26105 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
26106 {
26107 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26109 },
26110 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
26111 {
26112 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26114 },
26115 /* mov.w${G} $Dst16RnHI,${Dsp-16-s8}[sp] */
26116 {
26117 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24,
26118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26119 },
26120 /* mov.w${G} $Dst16AnHI,${Dsp-16-s8}[sp] */
26121 {
26122 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24,
26123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26124 },
26125 /* mov.w${G} [$Dst16An],${Dsp-16-s8}[sp] */
26126 {
26127 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24,
26128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26129 },
26130 /* mov.b${G} ${Dsp-16-u8}[$Dst16An],${Dsp-24-s8}[sp] */
26131 {
26132 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26134 },
26135 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[sp] */
26136 {
26137 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26139 },
26140 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[sp] */
26141 {
26142 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26144 },
26145 /* mov.b${G} ${Dsp-16-u16}[$Dst16An],${Dsp-32-s8}[sp] */
26146 {
26147 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26149 },
26150 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[sp] */
26151 {
26152 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26154 },
26155 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[sp] */
26156 {
26157 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26159 },
26160 /* mov.b${G} $Dst16RnQI,${Dsp-16-s8}[sp] */
26161 {
26162 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24,
26163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26164 },
26165 /* mov.b${G} $Dst16AnQI,${Dsp-16-s8}[sp] */
26166 {
26167 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24,
26168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26169 },
26170 /* mov.b${G} [$Dst16An],${Dsp-16-s8}[sp] */
26171 {
26172 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24,
26173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26174 },
26175 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26176 {
26177 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
26178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26179 },
26180 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26181 {
26182 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
26183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26184 },
26185 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26186 {
26187 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
26188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26189 },
26190 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26191 {
26192 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
26193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26194 },
26195 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26196 {
26197 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
26198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26199 },
26200 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
26201 {
26202 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
26203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26204 },
26205 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26206 {
26207 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
26208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26209 },
26210 /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26211 {
26212 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
26213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26214 },
26215 /* mov.w${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
26216 {
26217 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
26218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26219 },
26220 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedHI */
26221 {
26222 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26224 },
26225 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedHI */
26226 {
26227 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26229 },
26230 /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
26231 {
26232 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26234 },
26235 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26236 {
26237 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26239 },
26240 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26241 {
26242 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26244 },
26245 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26246 {
26247 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26249 },
26250 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26251 {
26252 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26254 },
26255 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26256 {
26257 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26259 },
26260 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-s16}[fb] */
26261 {
26262 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26264 },
26265 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26266 {
26267 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26269 },
26270 /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26271 {
26272 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26274 },
26275 /* mov.b${G} ${Dsp-40-s8}[sp],${Dsp-16-u24} */
26276 {
26277 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26279 },
26280 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32RnUnprefixedQI */
26281 {
26282 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26284 },
26285 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst32AnUnprefixedQI */
26286 {
26287 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26289 },
26290 /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst32AnUnprefixed] */
26291 {
26292 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26294 },
26295 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
26296 {
26297 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26299 },
26300 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26301 {
26302 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26304 },
26305 /* mov.w${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26306 {
26307 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26309 },
26310 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
26311 {
26312 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26314 },
26315 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26316 {
26317 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26319 },
26320 /* mov.w${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26321 {
26322 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26324 },
26325 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16RnHI */
26326 {
26327 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24,
26328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26329 },
26330 /* mov.w${G} ${Dsp-16-s8}[sp],$Dst16AnHI */
26331 {
26332 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24,
26333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26334 },
26335 /* mov.w${G} ${Dsp-16-s8}[sp],[$Dst16An] */
26336 {
26337 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24,
26338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26339 },
26340 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[$Dst16An] */
26341 {
26342 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26344 },
26345 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-u8}[sb] */
26346 {
26347 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26349 },
26350 /* mov.b${G} ${Dsp-24-s8}[sp],${Dsp-16-s8}[fb] */
26351 {
26352 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26354 },
26355 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[$Dst16An] */
26356 {
26357 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26359 },
26360 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16}[sb] */
26361 {
26362 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26364 },
26365 /* mov.b${G} ${Dsp-32-s8}[sp],${Dsp-16-u16} */
26366 {
26367 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26369 },
26370 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16RnQI */
26371 {
26372 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24,
26373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26374 },
26375 /* mov.b${G} ${Dsp-16-s8}[sp],$Dst16AnQI */
26376 {
26377 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24,
26378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26379 },
26380 /* mov.b${G} ${Dsp-16-s8}[sp],[$Dst16An] */
26381 {
26382 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24,
26383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26384 },
26385 /* mov.l${S} ${Dsp-8-u8}[sb],a1 */
26386 {
26387 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26389 },
26390 /* mov.l${S} ${Dsp-8-s8}[fb],a1 */
26391 {
26392 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26394 },
26395 /* mov.l${S} ${Dsp-8-u8}[sb],a0 */
26396 {
26397 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26399 },
26400 /* mov.l${S} ${Dsp-8-s8}[fb],a0 */
26401 {
26402 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26404 },
26405 /* mov.l${S} ${Dsp-8-u16},a1 */
26406 {
26407 M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24,
26408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26409 },
26410 /* mov.l${S} ${Dsp-8-u16},a0 */
26411 {
26412 M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24,
26413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26414 },
26415 /* mov.w${S} r0,${Dsp-8-u8}[sb] */
26416 {
26417 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26419 },
26420 /* mov.w${S} r0,${Dsp-8-s8}[fb] */
26421 {
26422 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26424 },
26425 /* mov.b${S} r0l,${Dsp-8-u8}[sb] */
26426 {
26427 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26429 },
26430 /* mov.b${S} r0l,${Dsp-8-s8}[fb] */
26431 {
26432 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26434 },
26435 /* mov.w${S} r0,${Dsp-8-u16} */
26436 {
26437 M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
26438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26439 },
26440 /* mov.b${S} r0l,${Dsp-8-u16} */
26441 {
26442 M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
26443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26444 },
26445 /* mov.w${S} ${Dsp-8-u8}[sb],r1 */
26446 {
26447 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26449 },
26450 /* mov.w${S} ${Dsp-8-s8}[fb],r1 */
26451 {
26452 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26454 },
26455 /* mov.b${S} ${Dsp-8-u8}[sb],r1l */
26456 {
26457 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26459 },
26460 /* mov.b${S} ${Dsp-8-s8}[fb],r1l */
26461 {
26462 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26464 },
26465 /* mov.w${S} ${Dsp-8-u16},r1 */
26466 {
26467 M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24,
26468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26469 },
26470 /* mov.b${S} ${Dsp-8-u16},r1l */
26471 {
26472 M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26474 },
26475 /* mov.w${S} r0,r1 */
26476 {
26477 M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1-dst32-2-S-R0-direct-HI", "mov.w", 8,
26478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26479 },
26480 /* mov.b${S} r0l,r1l */
26481 {
26482 M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8,
26483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26484 },
26485 /* mov.w${S} ${Dsp-8-u8}[sb],r0 */
26486 {
26487 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26489 },
26490 /* mov.w${S} ${Dsp-8-s8}[fb],r0 */
26491 {
26492 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26494 },
26495 /* mov.b${S} ${Dsp-8-u8}[sb],r0l */
26496 {
26497 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26499 },
26500 /* mov.b${S} ${Dsp-8-s8}[fb],r0l */
26501 {
26502 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26504 },
26505 /* mov.w${S} ${Dsp-8-u16},r0 */
26506 {
26507 M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24,
26508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26509 },
26510 /* mov.b${S} ${Dsp-8-u16},r0l */
26511 {
26512 M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26514 },
26515 /* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
26516 {
26517 M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8,
26518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26519 },
26520 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
26521 {
26522 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26524 },
26525 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
26526 {
26527 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26529 },
26530 /* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
26531 {
26532 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24,
26533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26534 },
26535 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
26536 {
26537 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26539 },
26540 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
26541 {
26542 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26544 },
26545 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
26546 {
26547 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24,
26548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26549 },
26550 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26551 {
26552 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26554 },
26555 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
26556 {
26557 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26559 },
26560 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
26561 {
26562 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26564 },
26565 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26566 {
26567 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26569 },
26570 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
26571 {
26572 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26574 },
26575 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
26576 {
26577 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26579 },
26580 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26581 {
26582 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26584 },
26585 /* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
26586 {
26587 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26589 },
26590 /* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
26591 {
26592 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26594 },
26595 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26596 {
26597 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26599 },
26600 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26601 {
26602 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26604 },
26605 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26606 {
26607 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26609 },
26610 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26611 {
26612 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26614 },
26615 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26616 {
26617 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26619 },
26620 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26621 {
26622 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26624 },
26625 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26626 {
26627 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26629 },
26630 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26631 {
26632 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26634 },
26635 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26636 {
26637 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26639 },
26640 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
26641 {
26642 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26644 },
26645 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26646 {
26647 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26649 },
26650 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26651 {
26652 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26654 },
26655 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
26656 {
26657 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26659 },
26660 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26661 {
26662 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26664 },
26665 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26666 {
26667 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26669 },
26670 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
26671 {
26672 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26674 },
26675 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26676 {
26677 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26679 },
26680 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26681 {
26682 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26684 },
26685 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
26686 {
26687 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26689 },
26690 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
26691 {
26692 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26694 },
26695 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
26696 {
26697 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26699 },
26700 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
26701 {
26702 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26704 },
26705 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26706 {
26707 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26709 },
26710 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26711 {
26712 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26714 },
26715 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
26716 {
26717 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26719 },
26720 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
26721 {
26722 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26724 },
26725 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
26726 {
26727 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26729 },
26730 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26731 {
26732 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26734 },
26735 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
26736 {
26737 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26739 },
26740 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
26741 {
26742 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26744 },
26745 /* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
26746 {
26747 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26749 },
26750 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26751 {
26752 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26754 },
26755 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
26756 {
26757 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26759 },
26760 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
26761 {
26762 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26764 },
26765 /* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
26766 {
26767 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26769 },
26770 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26771 {
26772 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26774 },
26775 /* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
26776 {
26777 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26779 },
26780 /* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
26781 {
26782 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26784 },
26785 /* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
26786 {
26787 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26789 },
26790 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26791 {
26792 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26794 },
26795 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26796 {
26797 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26799 },
26800 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26801 {
26802 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26804 },
26805 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
26806 {
26807 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26809 },
26810 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26811 {
26812 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26814 },
26815 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26816 {
26817 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26819 },
26820 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26821 {
26822 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26824 },
26825 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
26826 {
26827 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26829 },
26830 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26831 {
26832 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26834 },
26835 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26836 {
26837 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26839 },
26840 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26841 {
26842 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26844 },
26845 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
26846 {
26847 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26849 },
26850 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
26851 {
26852 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26854 },
26855 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26856 {
26857 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26859 },
26860 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
26861 {
26862 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26864 },
26865 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26866 {
26867 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26869 },
26870 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
26871 {
26872 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26874 },
26875 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26876 {
26877 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26879 },
26880 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
26881 {
26882 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26884 },
26885 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26886 {
26887 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26889 },
26890 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
26891 {
26892 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26894 },
26895 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26896 {
26897 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26899 },
26900 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
26901 {
26902 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26904 },
26905 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26906 {
26907 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26909 },
26910 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
26911 {
26912 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26914 },
26915 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
26916 {
26917 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26919 },
26920 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
26921 {
26922 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26924 },
26925 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
26926 {
26927 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26929 },
26930 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
26931 {
26932 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26934 },
26935 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26936 {
26937 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26939 },
26940 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
26941 {
26942 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26944 },
26945 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
26946 {
26947 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26949 },
26950 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
26951 {
26952 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26954 },
26955 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
26956 {
26957 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26959 },
26960 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
26961 {
26962 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26964 },
26965 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
26966 {
26967 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26969 },
26970 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26971 {
26972 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
26973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26974 },
26975 /* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
26976 {
26977 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
26978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26979 },
26980 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26981 {
26982 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
26983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26984 },
26985 /* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
26986 {
26987 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
26988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26989 },
26990 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26991 {
26992 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
26993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26994 },
26995 /* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
26996 {
26997 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
26998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26999 },
27000 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27001 {
27002 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
27003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27004 },
27005 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27006 {
27007 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
27008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27009 },
27010 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27011 {
27012 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27014 },
27015 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27016 {
27017 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27019 },
27020 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27021 {
27022 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27024 },
27025 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27026 {
27027 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27029 },
27030 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27031 {
27032 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27034 },
27035 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27036 {
27037 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27039 },
27040 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27041 {
27042 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27044 },
27045 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27046 {
27047 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27049 },
27050 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27051 {
27052 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27054 },
27055 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27056 {
27057 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27059 },
27060 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27061 {
27062 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27064 },
27065 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27066 {
27067 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27069 },
27070 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27071 {
27072 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27074 },
27075 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
27076 {
27077 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27079 },
27080 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27081 {
27082 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27084 },
27085 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
27086 {
27087 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27089 },
27090 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
27091 {
27092 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27094 },
27095 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
27096 {
27097 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27099 },
27100 /* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
27101 {
27102 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27104 },
27105 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
27106 {
27107 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27109 },
27110 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
27111 {
27112 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27114 },
27115 /* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
27116 {
27117 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27119 },
27120 /* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
27121 {
27122 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27124 },
27125 /* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
27126 {
27127 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27129 },
27130 /* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27131 {
27132 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27134 },
27135 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27136 {
27137 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27139 },
27140 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27141 {
27142 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27144 },
27145 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27146 {
27147 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27149 },
27150 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27151 {
27152 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27154 },
27155 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27156 {
27157 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27159 },
27160 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27161 {
27162 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27164 },
27165 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27166 {
27167 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27169 },
27170 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27171 {
27172 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27174 },
27175 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27176 {
27177 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27179 },
27180 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
27181 {
27182 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27184 },
27185 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
27186 {
27187 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27189 },
27190 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27191 {
27192 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27194 },
27195 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
27196 {
27197 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27199 },
27200 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
27201 {
27202 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27204 },
27205 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27206 {
27207 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27209 },
27210 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
27211 {
27212 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27214 },
27215 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
27216 {
27217 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27219 },
27220 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27221 {
27222 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27224 },
27225 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
27226 {
27227 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27229 },
27230 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
27231 {
27232 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27234 },
27235 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27236 {
27237 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27239 },
27240 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
27241 {
27242 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27244 },
27245 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
27246 {
27247 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27249 },
27250 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
27251 {
27252 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27254 },
27255 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
27256 {
27257 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27259 },
27260 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
27261 {
27262 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27264 },
27265 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
27266 {
27267 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27269 },
27270 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
27271 {
27272 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
27273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27274 },
27275 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
27276 {
27277 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
27278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27279 },
27280 /* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
27281 {
27282 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24,
27283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27284 },
27285 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27286 {
27287 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27289 },
27290 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
27291 {
27292 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27294 },
27295 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
27296 {
27297 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27299 },
27300 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27301 {
27302 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27304 },
27305 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
27306 {
27307 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27309 },
27310 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
27311 {
27312 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27314 },
27315 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27316 {
27317 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27319 },
27320 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
27321 {
27322 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27324 },
27325 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
27326 {
27327 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27329 },
27330 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27331 {
27332 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27334 },
27335 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27336 {
27337 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27339 },
27340 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27341 {
27342 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27344 },
27345 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27346 {
27347 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27349 },
27350 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27351 {
27352 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27354 },
27355 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27356 {
27357 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27359 },
27360 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27361 {
27362 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27364 },
27365 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27366 {
27367 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27369 },
27370 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27371 {
27372 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27374 },
27375 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
27376 {
27377 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27379 },
27380 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
27381 {
27382 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27384 },
27385 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
27386 {
27387 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27389 },
27390 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
27391 {
27392 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27394 },
27395 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
27396 {
27397 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27399 },
27400 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
27401 {
27402 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27404 },
27405 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
27406 {
27407 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27409 },
27410 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
27411 {
27412 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27414 },
27415 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
27416 {
27417 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27419 },
27420 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
27421 {
27422 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27424 },
27425 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
27426 {
27427 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27429 },
27430 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
27431 {
27432 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27434 },
27435 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
27436 {
27437 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27439 },
27440 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
27441 {
27442 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27444 },
27445 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
27446 {
27447 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27449 },
27450 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
27451 {
27452 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27454 },
27455 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
27456 {
27457 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27459 },
27460 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
27461 {
27462 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27464 },
27465 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27466 {
27467 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27469 },
27470 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
27471 {
27472 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27474 },
27475 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
27476 {
27477 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27479 },
27480 /* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
27481 {
27482 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27484 },
27485 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27486 {
27487 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27489 },
27490 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
27491 {
27492 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27494 },
27495 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
27496 {
27497 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27499 },
27500 /* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
27501 {
27502 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27504 },
27505 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27506 {
27507 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27509 },
27510 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
27511 {
27512 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27514 },
27515 /* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
27516 {
27517 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27519 },
27520 /* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
27521 {
27522 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27524 },
27525 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27526 {
27527 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27529 },
27530 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27531 {
27532 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27534 },
27535 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27536 {
27537 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27539 },
27540 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
27541 {
27542 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27544 },
27545 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27546 {
27547 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27549 },
27550 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27551 {
27552 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27554 },
27555 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27556 {
27557 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27559 },
27560 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
27561 {
27562 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27564 },
27565 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27566 {
27567 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27569 },
27570 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27571 {
27572 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27574 },
27575 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27576 {
27577 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27579 },
27580 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
27581 {
27582 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27584 },
27585 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
27586 {
27587 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27589 },
27590 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27591 {
27592 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27594 },
27595 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
27596 {
27597 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27599 },
27600 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27601 {
27602 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27604 },
27605 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
27606 {
27607 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27609 },
27610 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27611 {
27612 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27614 },
27615 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
27616 {
27617 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27619 },
27620 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27621 {
27622 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27624 },
27625 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
27626 {
27627 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27629 },
27630 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27631 {
27632 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27634 },
27635 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
27636 {
27637 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27639 },
27640 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27641 {
27642 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27644 },
27645 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
27646 {
27647 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27649 },
27650 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
27651 {
27652 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27654 },
27655 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
27656 {
27657 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27659 },
27660 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
27661 {
27662 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27664 },
27665 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
27666 {
27667 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27669 },
27670 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27671 {
27672 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27674 },
27675 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
27676 {
27677 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27679 },
27680 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
27681 {
27682 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27684 },
27685 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
27686 {
27687 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27689 },
27690 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
27691 {
27692 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27694 },
27695 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
27696 {
27697 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27699 },
27700 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
27701 {
27702 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27704 },
27705 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27706 {
27707 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27709 },
27710 /* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
27711 {
27712 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27714 },
27715 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27716 {
27717 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27719 },
27720 /* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
27721 {
27722 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27724 },
27725 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27726 {
27727 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27729 },
27730 /* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27731 {
27732 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27734 },
27735 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27736 {
27737 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27739 },
27740 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27741 {
27742 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27744 },
27745 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27746 {
27747 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27749 },
27750 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27751 {
27752 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27754 },
27755 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27756 {
27757 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27759 },
27760 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27761 {
27762 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27764 },
27765 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27766 {
27767 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27769 },
27770 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27771 {
27772 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27774 },
27775 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27776 {
27777 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27779 },
27780 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27781 {
27782 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27784 },
27785 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27786 {
27787 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27789 },
27790 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27791 {
27792 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27794 },
27795 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27796 {
27797 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27799 },
27800 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27801 {
27802 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27804 },
27805 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27806 {
27807 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27809 },
27810 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
27811 {
27812 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27814 },
27815 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27816 {
27817 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27819 },
27820 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
27821 {
27822 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27824 },
27825 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
27826 {
27827 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27829 },
27830 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
27831 {
27832 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27834 },
27835 /* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27836 {
27837 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27839 },
27840 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
27841 {
27842 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27844 },
27845 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
27846 {
27847 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27849 },
27850 /* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27851 {
27852 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27854 },
27855 /* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
27856 {
27857 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27859 },
27860 /* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
27861 {
27862 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27864 },
27865 /* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27866 {
27867 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27869 },
27870 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27871 {
27872 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27874 },
27875 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27876 {
27877 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27879 },
27880 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27881 {
27882 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27884 },
27885 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27886 {
27887 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27889 },
27890 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27891 {
27892 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27894 },
27895 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27896 {
27897 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27899 },
27900 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27901 {
27902 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27904 },
27905 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27906 {
27907 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27909 },
27910 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27911 {
27912 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27914 },
27915 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
27916 {
27917 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27919 },
27920 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
27921 {
27922 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27924 },
27925 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27926 {
27927 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27929 },
27930 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
27931 {
27932 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27934 },
27935 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
27936 {
27937 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27939 },
27940 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27941 {
27942 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27944 },
27945 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
27946 {
27947 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27949 },
27950 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
27951 {
27952 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27954 },
27955 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27956 {
27957 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27959 },
27960 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
27961 {
27962 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27964 },
27965 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
27966 {
27967 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27969 },
27970 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27971 {
27972 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27974 },
27975 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
27976 {
27977 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
27978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27979 },
27980 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
27981 {
27982 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
27983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27984 },
27985 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
27986 {
27987 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
27988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27989 },
27990 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
27991 {
27992 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
27993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27994 },
27995 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
27996 {
27997 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
27998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27999 },
28000 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28001 {
28002 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
28003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28004 },
28005 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28006 {
28007 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28009 },
28010 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
28011 {
28012 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28014 },
28015 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
28016 {
28017 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28019 },
28020 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28021 {
28022 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28024 },
28025 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
28026 {
28027 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28029 },
28030 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
28031 {
28032 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28034 },
28035 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28036 {
28037 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28039 },
28040 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28041 {
28042 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28044 },
28045 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28046 {
28047 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28049 },
28050 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28051 {
28052 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28054 },
28055 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28056 {
28057 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28059 },
28060 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28061 {
28062 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28064 },
28065 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28066 {
28067 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28069 },
28070 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28071 {
28072 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28074 },
28075 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28076 {
28077 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28079 },
28080 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28081 {
28082 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28084 },
28085 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28086 {
28087 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28089 },
28090 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28091 {
28092 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28094 },
28095 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28096 {
28097 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28099 },
28100 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28101 {
28102 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28104 },
28105 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28106 {
28107 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28109 },
28110 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28111 {
28112 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28114 },
28115 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28116 {
28117 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28119 },
28120 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28121 {
28122 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28124 },
28125 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28126 {
28127 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28129 },
28130 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28131 {
28132 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28134 },
28135 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28136 {
28137 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28139 },
28140 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28141 {
28142 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28144 },
28145 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28146 {
28147 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28149 },
28150 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28151 {
28152 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28154 },
28155 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28156 {
28157 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28159 },
28160 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28161 {
28162 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28164 },
28165 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28166 {
28167 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28169 },
28170 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28171 {
28172 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28174 },
28175 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28176 {
28177 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28179 },
28180 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28181 {
28182 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28184 },
28185 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28186 {
28187 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28189 },
28190 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
28191 {
28192 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28194 },
28195 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
28196 {
28197 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28199 },
28200 /* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
28201 {
28202 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28204 },
28205 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28206 {
28207 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28209 },
28210 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
28211 {
28212 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28214 },
28215 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
28216 {
28217 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28219 },
28220 /* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
28221 {
28222 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28224 },
28225 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28226 {
28227 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28229 },
28230 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28231 {
28232 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28234 },
28235 /* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28236 {
28237 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28239 },
28240 /* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28241 {
28242 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28244 },
28245 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28246 {
28247 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28249 },
28250 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28251 {
28252 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28254 },
28255 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28256 {
28257 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28259 },
28260 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28261 {
28262 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28264 },
28265 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28266 {
28267 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28269 },
28270 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28271 {
28272 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28274 },
28275 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28276 {
28277 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28279 },
28280 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28281 {
28282 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28284 },
28285 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28286 {
28287 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28289 },
28290 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28291 {
28292 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28294 },
28295 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28296 {
28297 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28299 },
28300 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28301 {
28302 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28304 },
28305 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28306 {
28307 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28309 },
28310 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28311 {
28312 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28314 },
28315 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28316 {
28317 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28319 },
28320 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28321 {
28322 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28324 },
28325 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28326 {
28327 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28329 },
28330 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28331 {
28332 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28334 },
28335 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28336 {
28337 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28339 },
28340 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28341 {
28342 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28344 },
28345 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28346 {
28347 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28349 },
28350 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28351 {
28352 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28354 },
28355 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28356 {
28357 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28359 },
28360 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28361 {
28362 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28364 },
28365 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28366 {
28367 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28369 },
28370 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28371 {
28372 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28374 },
28375 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28376 {
28377 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28379 },
28380 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28381 {
28382 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28384 },
28385 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28386 {
28387 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28389 },
28390 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28391 {
28392 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28394 },
28395 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28396 {
28397 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28399 },
28400 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
28401 {
28402 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28404 },
28405 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28406 {
28407 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28409 },
28410 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28411 {
28412 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28414 },
28415 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28416 {
28417 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28419 },
28420 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
28421 {
28422 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28424 },
28425 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28426 {
28427 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28429 },
28430 /* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
28431 {
28432 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28434 },
28435 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28436 {
28437 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28439 },
28440 /* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
28441 {
28442 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28444 },
28445 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28446 {
28447 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28449 },
28450 /* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28451 {
28452 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28454 },
28455 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28456 {
28457 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28459 },
28460 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28461 {
28462 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28464 },
28465 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28466 {
28467 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28469 },
28470 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28471 {
28472 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28474 },
28475 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28476 {
28477 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28479 },
28480 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28481 {
28482 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28484 },
28485 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28486 {
28487 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28489 },
28490 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28491 {
28492 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28494 },
28495 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28496 {
28497 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28499 },
28500 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28501 {
28502 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28504 },
28505 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28506 {
28507 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28509 },
28510 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28511 {
28512 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28514 },
28515 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28516 {
28517 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28519 },
28520 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28521 {
28522 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28524 },
28525 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28526 {
28527 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28529 },
28530 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
28531 {
28532 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28534 },
28535 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28536 {
28537 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28539 },
28540 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
28541 {
28542 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28544 },
28545 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
28546 {
28547 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28549 },
28550 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
28551 {
28552 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28554 },
28555 /* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28556 {
28557 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28559 },
28560 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
28561 {
28562 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28564 },
28565 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
28566 {
28567 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28569 },
28570 /* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28571 {
28572 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28574 },
28575 /* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
28576 {
28577 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28579 },
28580 /* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
28581 {
28582 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28584 },
28585 /* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28586 {
28587 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28589 },
28590 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28591 {
28592 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28594 },
28595 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28596 {
28597 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28599 },
28600 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
28601 {
28602 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28604 },
28605 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28606 {
28607 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28609 },
28610 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28611 {
28612 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28614 },
28615 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
28616 {
28617 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28619 },
28620 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28621 {
28622 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28624 },
28625 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28626 {
28627 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28629 },
28630 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
28631 {
28632 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28634 },
28635 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
28636 {
28637 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28639 },
28640 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
28641 {
28642 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28644 },
28645 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
28646 {
28647 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28649 },
28650 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
28651 {
28652 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28654 },
28655 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
28656 {
28657 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28659 },
28660 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
28661 {
28662 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28664 },
28665 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
28666 {
28667 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28669 },
28670 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
28671 {
28672 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28674 },
28675 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
28676 {
28677 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28679 },
28680 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
28681 {
28682 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28684 },
28685 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
28686 {
28687 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28689 },
28690 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28691 {
28692 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28694 },
28695 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
28696 {
28697 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28699 },
28700 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
28701 {
28702 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28704 },
28705 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28706 {
28707 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28709 },
28710 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
28711 {
28712 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28714 },
28715 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
28716 {
28717 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28719 },
28720 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28721 {
28722 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28724 },
28725 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
28726 {
28727 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28729 },
28730 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
28731 {
28732 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28734 },
28735 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
28736 {
28737 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28739 },
28740 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
28741 {
28742 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28744 },
28745 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
28746 {
28747 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28749 },
28750 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
28751 {
28752 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28754 },
28755 /* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
28756 {
28757 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28759 },
28760 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
28761 {
28762 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28764 },
28765 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
28766 {
28767 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28769 },
28770 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
28771 {
28772 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28774 },
28775 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
28776 {
28777 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28779 },
28780 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
28781 {
28782 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28784 },
28785 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
28786 {
28787 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28789 },
28790 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
28791 {
28792 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28794 },
28795 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
28796 {
28797 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28799 },
28800 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
28801 {
28802 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28804 },
28805 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28806 {
28807 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28809 },
28810 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28811 {
28812 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28814 },
28815 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
28816 {
28817 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28819 },
28820 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28821 {
28822 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28824 },
28825 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28826 {
28827 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28829 },
28830 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
28831 {
28832 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28834 },
28835 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28836 {
28837 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28839 },
28840 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28841 {
28842 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28844 },
28845 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
28846 {
28847 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28849 },
28850 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28851 {
28852 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28854 },
28855 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28856 {
28857 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28859 },
28860 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
28861 {
28862 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28864 },
28865 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
28866 {
28867 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28869 },
28870 /* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
28871 {
28872 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32,
28873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28874 },
28875 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
28876 {
28877 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28879 },
28880 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
28881 {
28882 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28884 },
28885 /* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
28886 {
28887 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32,
28888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28889 },
28890 /* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
28891 {
28892 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28894 },
28895 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
28896 {
28897 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28899 },
28900 /* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
28901 {
28902 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32,
28903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28904 },
28905 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
28906 {
28907 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28909 },
28910 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
28911 {
28912 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28914 },
28915 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
28916 {
28917 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28919 },
28920 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
28921 {
28922 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28924 },
28925 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
28926 {
28927 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28929 },
28930 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
28931 {
28932 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28934 },
28935 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
28936 {
28937 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28939 },
28940 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28941 {
28942 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28944 },
28945 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28946 {
28947 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28949 },
28950 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
28951 {
28952 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28954 },
28955 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28956 {
28957 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28959 },
28960 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28961 {
28962 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28964 },
28965 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
28966 {
28967 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28969 },
28970 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28971 {
28972 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28974 },
28975 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28976 {
28977 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28979 },
28980 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
28981 {
28982 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
28983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28984 },
28985 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28986 {
28987 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
28988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28989 },
28990 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
28991 {
28992 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48,
28993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28994 },
28995 /* mov.w${G} $Src16RnHI,$Dst16RnHI */
28996 {
28997 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
28998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28999 },
29000 /* mov.w${G} $Src16AnHI,$Dst16RnHI */
29001 {
29002 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
29003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29004 },
29005 /* mov.w${G} [$Src16An],$Dst16RnHI */
29006 {
29007 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16,
29008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29009 },
29010 /* mov.w${G} $Src16RnHI,$Dst16AnHI */
29011 {
29012 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29014 },
29015 /* mov.w${G} $Src16AnHI,$Dst16AnHI */
29016 {
29017 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29019 },
29020 /* mov.w${G} [$Src16An],$Dst16AnHI */
29021 {
29022 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16,
29023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29024 },
29025 /* mov.w${G} $Src16RnHI,[$Dst16An] */
29026 {
29027 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29029 },
29030 /* mov.w${G} $Src16AnHI,[$Dst16An] */
29031 {
29032 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29034 },
29035 /* mov.w${G} [$Src16An],[$Dst16An] */
29036 {
29037 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16,
29038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29039 },
29040 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
29041 {
29042 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29044 },
29045 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
29046 {
29047 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29049 },
29050 /* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29051 {
29052 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29054 },
29055 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
29056 {
29057 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29059 },
29060 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
29061 {
29062 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29064 },
29065 /* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29066 {
29067 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29069 },
29070 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
29071 {
29072 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29074 },
29075 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
29076 {
29077 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29079 },
29080 /* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
29081 {
29082 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29084 },
29085 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
29086 {
29087 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29089 },
29090 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
29091 {
29092 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29094 },
29095 /* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
29096 {
29097 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29099 },
29100 /* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
29101 {
29102 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29104 },
29105 /* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
29106 {
29107 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29109 },
29110 /* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
29111 {
29112 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29114 },
29115 /* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
29116 {
29117 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29119 },
29120 /* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
29121 {
29122 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29124 },
29125 /* mov.w${G} [$Src16An],${Dsp-16-u16} */
29126 {
29127 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29129 },
29130 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
29131 {
29132 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29134 },
29135 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
29136 {
29137 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29139 },
29140 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
29141 {
29142 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29144 },
29145 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
29146 {
29147 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29149 },
29150 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
29151 {
29152 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29154 },
29155 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
29156 {
29157 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29159 },
29160 /* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
29161 {
29162 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29164 },
29165 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
29166 {
29167 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29169 },
29170 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
29171 {
29172 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29174 },
29175 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
29176 {
29177 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29179 },
29180 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
29181 {
29182 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29184 },
29185 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
29186 {
29187 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29189 },
29190 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
29191 {
29192 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29194 },
29195 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
29196 {
29197 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29199 },
29200 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
29201 {
29202 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29204 },
29205 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
29206 {
29207 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29209 },
29210 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29211 {
29212 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29214 },
29215 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29216 {
29217 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29219 },
29220 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
29221 {
29222 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29224 },
29225 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29226 {
29227 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29229 },
29230 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29231 {
29232 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29234 },
29235 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
29236 {
29237 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29239 },
29240 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29241 {
29242 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29244 },
29245 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29246 {
29247 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29249 },
29250 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
29251 {
29252 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29254 },
29255 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29256 {
29257 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29259 },
29260 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29261 {
29262 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29264 },
29265 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
29266 {
29267 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29269 },
29270 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
29271 {
29272 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29274 },
29275 /* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
29276 {
29277 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32,
29278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29279 },
29280 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
29281 {
29282 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29284 },
29285 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
29286 {
29287 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29289 },
29290 /* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
29291 {
29292 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32,
29293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29294 },
29295 /* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
29296 {
29297 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29299 },
29300 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
29301 {
29302 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29304 },
29305 /* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
29306 {
29307 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32,
29308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29309 },
29310 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
29311 {
29312 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29314 },
29315 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
29316 {
29317 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29319 },
29320 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
29321 {
29322 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29324 },
29325 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
29326 {
29327 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29329 },
29330 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
29331 {
29332 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29334 },
29335 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
29336 {
29337 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29339 },
29340 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
29341 {
29342 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29344 },
29345 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29346 {
29347 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29349 },
29350 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29351 {
29352 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29354 },
29355 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
29356 {
29357 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29359 },
29360 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29361 {
29362 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29364 },
29365 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29366 {
29367 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29369 },
29370 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
29371 {
29372 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29374 },
29375 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29376 {
29377 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29379 },
29380 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29381 {
29382 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29384 },
29385 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
29386 {
29387 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29389 },
29390 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29391 {
29392 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29394 },
29395 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29396 {
29397 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29399 },
29400 /* mov.b${G} $Src16RnQI,$Dst16RnQI */
29401 {
29402 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29404 },
29405 /* mov.b${G} $Src16AnQI,$Dst16RnQI */
29406 {
29407 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29409 },
29410 /* mov.b${G} [$Src16An],$Dst16RnQI */
29411 {
29412 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16,
29413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29414 },
29415 /* mov.b${G} $Src16RnQI,$Dst16AnQI */
29416 {
29417 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29419 },
29420 /* mov.b${G} $Src16AnQI,$Dst16AnQI */
29421 {
29422 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29424 },
29425 /* mov.b${G} [$Src16An],$Dst16AnQI */
29426 {
29427 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16,
29428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29429 },
29430 /* mov.b${G} $Src16RnQI,[$Dst16An] */
29431 {
29432 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29434 },
29435 /* mov.b${G} $Src16AnQI,[$Dst16An] */
29436 {
29437 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29439 },
29440 /* mov.b${G} [$Src16An],[$Dst16An] */
29441 {
29442 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16,
29443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29444 },
29445 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
29446 {
29447 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29449 },
29450 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
29451 {
29452 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29454 },
29455 /* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29456 {
29457 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29459 },
29460 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
29461 {
29462 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29464 },
29465 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
29466 {
29467 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29469 },
29470 /* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29471 {
29472 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29474 },
29475 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
29476 {
29477 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29479 },
29480 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
29481 {
29482 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29484 },
29485 /* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
29486 {
29487 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29489 },
29490 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
29491 {
29492 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29494 },
29495 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
29496 {
29497 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29499 },
29500 /* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
29501 {
29502 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29504 },
29505 /* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
29506 {
29507 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29509 },
29510 /* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
29511 {
29512 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29514 },
29515 /* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
29516 {
29517 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29519 },
29520 /* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
29521 {
29522 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29524 },
29525 /* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
29526 {
29527 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29529 },
29530 /* mov.b${G} [$Src16An],${Dsp-16-u16} */
29531 {
29532 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29534 },
29535 /* mov.w${Z} #0,${Dsp-8-u8}[sb] */
29536 {
29537 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
29538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29539 },
29540 /* mov.w${Z} #0,${Dsp-8-s8}[fb] */
29541 {
29542 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
29543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29544 },
29545 /* mov.w${Z} #0,${Dsp-8-u16} */
29546 {
29547 M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
29548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29549 },
29550 /* mov.w${Z} #0,r0 */
29551 {
29552 M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8,
29553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29554 },
29555 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29556 {
29557 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
29558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29559 },
29560 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29561 {
29562 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
29563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29564 },
29565 /* mov.b${Z} #0,${Dsp-8-u16} */
29566 {
29567 M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
29568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29569 },
29570 /* mov.b${Z} #0,r0l */
29571 {
29572 M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8,
29573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29574 },
29575 /* mov.b${Z} #0,r0l */
29576 {
29577 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8,
29578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29579 },
29580 /* mov.b${Z} #0,r0h */
29581 {
29582 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8,
29583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29584 },
29585 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29586 {
29587 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16,
29588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29589 },
29590 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29591 {
29592 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16,
29593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29594 },
29595 /* mov.b${Z} #0,${Dsp-8-u16} */
29596 {
29597 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
29598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29599 },
29600 /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
29601 {
29602 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
29603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29604 },
29605 /* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
29606 {
29607 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
29608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29609 },
29610 /* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29611 {
29612 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
29613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29614 },
29615 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29616 {
29617 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
29618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29619 },
29620 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29621 {
29622 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
29623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29624 },
29625 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29626 {
29627 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
29628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29629 },
29630 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29631 {
29632 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
29633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29634 },
29635 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29636 {
29637 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
29638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29639 },
29640 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29641 {
29642 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
29643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29644 },
29645 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29646 {
29647 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
29648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29649 },
29650 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
29651 {
29652 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
29653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29654 },
29655 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
29656 {
29657 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
29658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29659 },
29660 /* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
29661 {
29662 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
29663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29664 },
29665 /* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
29666 {
29667 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
29668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29669 },
29670 /* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29671 {
29672 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
29673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29674 },
29675 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29676 {
29677 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
29678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29679 },
29680 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29681 {
29682 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
29683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29684 },
29685 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29686 {
29687 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
29688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29689 },
29690 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29691 {
29692 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
29693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29694 },
29695 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29696 {
29697 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
29698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29699 },
29700 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29701 {
29702 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
29703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29704 },
29705 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29706 {
29707 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
29708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29709 },
29710 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
29711 {
29712 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
29713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29714 },
29715 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
29716 {
29717 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
29718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29719 },
29720 /* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */
29721 {
29722 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-Rn-direct-QI", "mov.w", 16,
29723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29724 },
29725 /* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */
29726 {
29727 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-direct-QI", "mov.w", 16,
29728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29729 },
29730 /* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
29731 {
29732 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-indirect-QI", "mov.w", 16,
29733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29734 },
29735 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29736 {
29737 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.w", 24,
29738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29739 },
29740 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29741 {
29742 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.w", 32,
29743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29744 },
29745 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29746 {
29747 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.w", 24,
29748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29749 },
29750 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29751 {
29752 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.w", 32,
29753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29754 },
29755 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29756 {
29757 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.w", 24,
29758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29759 },
29760 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
29761 {
29762 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-QI", "mov.w", 32,
29763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29764 },
29765 /* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
29766 {
29767 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16,
29768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29769 },
29770 /* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
29771 {
29772 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16,
29773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29774 },
29775 /* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
29776 {
29777 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16,
29778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29779 },
29780 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29781 {
29782 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24,
29783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29784 },
29785 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29786 {
29787 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32,
29788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29789 },
29790 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29791 {
29792 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24,
29793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29794 },
29795 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29796 {
29797 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32,
29798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29799 },
29800 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29801 {
29802 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24,
29803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29804 },
29805 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
29806 {
29807 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
29808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29809 },
29810 /* mov.b${S} #${Imm-8-QI},r0l */
29811 {
29812 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
29813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29814 },
29815 /* mov.b${S} #${Imm-8-QI},r0h */
29816 {
29817 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
29818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29819 },
29820 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
29821 {
29822 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
29823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29824 },
29825 /* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
29826 {
29827 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
29828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29829 },
29830 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
29831 {
29832 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
29833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29834 },
29835 /* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
29836 {
29837 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
29838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29839 },
29840 /* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
29841 {
29842 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
29843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29844 },
29845 /* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
29846 {
29847 M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
29848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29849 },
29850 /* mov.w${S} #${Imm-8-HI},r0 */
29851 {
29852 M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
29853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29854 },
29855 /* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
29856 {
29857 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
29858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29859 },
29860 /* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
29861 {
29862 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
29863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29864 },
29865 /* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
29866 {
29867 M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
29868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29869 },
29870 /* mov.b${S} #${Imm-8-QI},r0l */
29871 {
29872 M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
29873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29874 },
29875 /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
29876 {
29877 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
29878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29879 },
29880 /* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
29881 {
29882 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48,
29883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29884 },
29885 /* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
29886 {
29887 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48,
29888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29889 },
29890 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29891 {
29892 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56,
29893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29894 },
29895 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
29896 {
29897 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56,
29898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29899 },
29900 /* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
29901 {
29902 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56,
29903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29904 },
29905 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29906 {
29907 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64,
29908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29909 },
29910 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
29911 {
29912 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64,
29913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29914 },
29915 /* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
29916 {
29917 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64,
29918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29919 },
29920 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
29921 {
29922 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64,
29923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29924 },
29925 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29926 {
29927 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72,
29928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29929 },
29930 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
29931 {
29932 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72,
29933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29934 },
29935 /* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
29936 {
29937 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
29938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29939 },
29940 /* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
29941 {
29942 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
29943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29944 },
29945 /* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
29946 {
29947 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
29948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29949 },
29950 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29951 {
29952 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40,
29953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29954 },
29955 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
29956 {
29957 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40,
29958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29959 },
29960 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
29961 {
29962 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40,
29963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29964 },
29965 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29966 {
29967 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48,
29968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29969 },
29970 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
29971 {
29972 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48,
29973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29974 },
29975 /* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
29976 {
29977 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48,
29978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29979 },
29980 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
29981 {
29982 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48,
29983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29984 },
29985 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29986 {
29987 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56,
29988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29989 },
29990 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
29991 {
29992 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56,
29993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29994 },
29995 /* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
29996 {
29997 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
29998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29999 },
30000 /* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
30001 {
30002 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
30003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30004 },
30005 /* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
30006 {
30007 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
30008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30009 },
30010 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
30011 {
30012 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
30013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30014 },
30015 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30016 {
30017 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
30018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30019 },
30020 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30021 {
30022 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
30023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30024 },
30025 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30026 {
30027 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
30028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30029 },
30030 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30031 {
30032 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
30033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30034 },
30035 /* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
30036 {
30037 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
30038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30039 },
30040 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30041 {
30042 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
30043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30044 },
30045 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30046 {
30047 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
30048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30049 },
30050 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
30051 {
30052 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
30053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30054 },
30055 /* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
30056 {
30057 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32,
30058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30059 },
30060 /* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
30061 {
30062 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32,
30063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30064 },
30065 /* mov.w${G} #${Imm-16-HI},[$Dst16An] */
30066 {
30067 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32,
30068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30069 },
30070 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
30071 {
30072 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40,
30073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30074 },
30075 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30076 {
30077 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40,
30078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30079 },
30080 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30081 {
30082 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40,
30083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30084 },
30085 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
30086 {
30087 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48,
30088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30089 },
30090 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30091 {
30092 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48,
30093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30094 },
30095 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30096 {
30097 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48,
30098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30099 },
30100 /* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
30101 {
30102 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24,
30103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30104 },
30105 /* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
30106 {
30107 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24,
30108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30109 },
30110 /* mov.b${G} #${Imm-16-QI},[$Dst16An] */
30111 {
30112 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24,
30113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30114 },
30115 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
30116 {
30117 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
30118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30119 },
30120 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30121 {
30122 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
30123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30124 },
30125 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30126 {
30127 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
30128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30129 },
30130 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
30131 {
30132 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
30133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30134 },
30135 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30136 {
30137 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
30138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30139 },
30140 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30141 {
30142 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
30143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30144 },
30145 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30146 {
30147 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30149 },
30150 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
30151 {
30152 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30154 },
30155 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
30156 {
30157 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30159 },
30160 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30161 {
30162 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30164 },
30165 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
30166 {
30167 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30169 },
30170 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
30171 {
30172 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30174 },
30175 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30176 {
30177 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30179 },
30180 /* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30181 {
30182 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30184 },
30185 /* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30186 {
30187 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30189 },
30190 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30191 {
30192 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30194 },
30195 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30196 {
30197 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30199 },
30200 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30201 {
30202 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30204 },
30205 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30206 {
30207 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30209 },
30210 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30211 {
30212 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30214 },
30215 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30216 {
30217 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30219 },
30220 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30221 {
30222 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30224 },
30225 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30226 {
30227 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30229 },
30230 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30231 {
30232 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30234 },
30235 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30236 {
30237 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30239 },
30240 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30241 {
30242 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30244 },
30245 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30246 {
30247 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30249 },
30250 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30251 {
30252 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30254 },
30255 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30256 {
30257 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30259 },
30260 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30261 {
30262 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30264 },
30265 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
30266 {
30267 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30269 },
30270 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
30271 {
30272 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30274 },
30275 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
30276 {
30277 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30279 },
30280 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
30281 {
30282 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30284 },
30285 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
30286 {
30287 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30289 },
30290 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
30291 {
30292 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30294 },
30295 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
30296 {
30297 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30299 },
30300 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
30301 {
30302 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30304 },
30305 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
30306 {
30307 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30309 },
30310 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
30311 {
30312 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30314 },
30315 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
30316 {
30317 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30319 },
30320 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
30321 {
30322 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30324 },
30325 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30326 {
30327 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30329 },
30330 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
30331 {
30332 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30334 },
30335 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
30336 {
30337 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30339 },
30340 /* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
30341 {
30342 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30344 },
30345 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30346 {
30347 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30349 },
30350 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
30351 {
30352 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30354 },
30355 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
30356 {
30357 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30359 },
30360 /* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
30361 {
30362 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30364 },
30365 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30366 {
30367 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30369 },
30370 /* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
30371 {
30372 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30374 },
30375 /* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
30376 {
30377 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30379 },
30380 /* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
30381 {
30382 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30384 },
30385 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
30386 {
30387 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30389 },
30390 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30391 {
30392 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30394 },
30395 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30396 {
30397 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30399 },
30400 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
30401 {
30402 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30404 },
30405 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
30406 {
30407 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30409 },
30410 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30411 {
30412 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30414 },
30415 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30416 {
30417 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30419 },
30420 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
30421 {
30422 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30424 },
30425 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
30426 {
30427 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30429 },
30430 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30431 {
30432 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30434 },
30435 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30436 {
30437 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30439 },
30440 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
30441 {
30442 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30444 },
30445 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
30446 {
30447 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30449 },
30450 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
30451 {
30452 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30454 },
30455 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
30456 {
30457 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30459 },
30460 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
30461 {
30462 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30464 },
30465 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
30466 {
30467 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30469 },
30470 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
30471 {
30472 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30474 },
30475 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
30476 {
30477 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30479 },
30480 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
30481 {
30482 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30484 },
30485 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
30486 {
30487 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30489 },
30490 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
30491 {
30492 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30494 },
30495 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
30496 {
30497 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30499 },
30500 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
30501 {
30502 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30504 },
30505 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
30506 {
30507 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30509 },
30510 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
30511 {
30512 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30514 },
30515 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
30516 {
30517 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30519 },
30520 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
30521 {
30522 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30524 },
30525 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
30526 {
30527 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30529 },
30530 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
30531 {
30532 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30534 },
30535 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
30536 {
30537 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30539 },
30540 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
30541 {
30542 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30544 },
30545 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
30546 {
30547 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30549 },
30550 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
30551 {
30552 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30554 },
30555 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
30556 {
30557 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30559 },
30560 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
30561 {
30562 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30564 },
30565 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30566 {
30567 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30569 },
30570 /* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
30571 {
30572 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30574 },
30575 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30576 {
30577 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30579 },
30580 /* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
30581 {
30582 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30584 },
30585 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30586 {
30587 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30589 },
30590 /* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
30591 {
30592 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30594 },
30595 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
30596 {
30597 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30599 },
30600 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
30601 {
30602 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30604 },
30605 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
30606 {
30607 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30609 },
30610 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
30611 {
30612 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30614 },
30615 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
30616 {
30617 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30619 },
30620 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
30621 {
30622 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30624 },
30625 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
30626 {
30627 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30629 },
30630 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
30631 {
30632 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30634 },
30635 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
30636 {
30637 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30639 },
30640 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
30641 {
30642 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30644 },
30645 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
30646 {
30647 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30649 },
30650 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
30651 {
30652 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30654 },
30655 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
30656 {
30657 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30659 },
30660 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
30661 {
30662 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30664 },
30665 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
30666 {
30667 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30669 },
30670 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
30671 {
30672 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30674 },
30675 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
30676 {
30677 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30679 },
30680 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
30681 {
30682 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30684 },
30685 /* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
30686 {
30687 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30689 },
30690 /* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
30691 {
30692 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30694 },
30695 /* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
30696 {
30697 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30699 },
30700 /* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
30701 {
30702 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30704 },
30705 /* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
30706 {
30707 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30709 },
30710 /* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
30711 {
30712 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30714 },
30715 /* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
30716 {
30717 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30719 },
30720 /* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
30721 {
30722 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30724 },
30725 /* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
30726 {
30727 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30729 },
30730 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30731 {
30732 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30734 },
30735 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30736 {
30737 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30739 },
30740 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
30741 {
30742 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30744 },
30745 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30746 {
30747 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30749 },
30750 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30751 {
30752 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30754 },
30755 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
30756 {
30757 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30759 },
30760 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30761 {
30762 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30764 },
30765 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30766 {
30767 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30769 },
30770 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
30771 {
30772 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30774 },
30775 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
30776 {
30777 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30779 },
30780 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
30781 {
30782 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30784 },
30785 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
30786 {
30787 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30789 },
30790 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
30791 {
30792 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30794 },
30795 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
30796 {
30797 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30799 },
30800 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
30801 {
30802 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30804 },
30805 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
30806 {
30807 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30809 },
30810 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
30811 {
30812 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30814 },
30815 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
30816 {
30817 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30819 },
30820 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
30821 {
30822 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30824 },
30825 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
30826 {
30827 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30829 },
30830 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
30831 {
30832 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30834 },
30835 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
30836 {
30837 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30839 },
30840 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
30841 {
30842 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30844 },
30845 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
30846 {
30847 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30849 },
30850 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
30851 {
30852 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30854 },
30855 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
30856 {
30857 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30859 },
30860 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
30861 {
30862 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30864 },
30865 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
30866 {
30867 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30869 },
30870 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
30871 {
30872 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30874 },
30875 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
30876 {
30877 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30879 },
30880 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
30881 {
30882 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30884 },
30885 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
30886 {
30887 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30889 },
30890 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
30891 {
30892 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30894 },
30895 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30896 {
30897 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30899 },
30900 /* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30901 {
30902 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30904 },
30905 /* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30906 {
30907 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30909 },
30910 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30911 {
30912 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30914 },
30915 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30916 {
30917 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30919 },
30920 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30921 {
30922 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30924 },
30925 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30926 {
30927 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30929 },
30930 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30931 {
30932 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30934 },
30935 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30936 {
30937 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30939 },
30940 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30941 {
30942 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30944 },
30945 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30946 {
30947 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30949 },
30950 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30951 {
30952 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30954 },
30955 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30956 {
30957 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30959 },
30960 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30961 {
30962 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30964 },
30965 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30966 {
30967 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30969 },
30970 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30971 {
30972 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30974 },
30975 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30976 {
30977 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30979 },
30980 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30981 {
30982 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30984 },
30985 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
30986 {
30987 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
30988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30989 },
30990 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
30991 {
30992 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
30993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30994 },
30995 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
30996 {
30997 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
30998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30999 },
31000 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31001 {
31002 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31004 },
31005 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31006 {
31007 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31009 },
31010 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31011 {
31012 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31014 },
31015 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31016 {
31017 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31019 },
31020 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31021 {
31022 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31024 },
31025 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31026 {
31027 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31029 },
31030 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31031 {
31032 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31034 },
31035 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31036 {
31037 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31039 },
31040 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31041 {
31042 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31044 },
31045 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31046 {
31047 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31049 },
31050 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
31051 {
31052 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31054 },
31055 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
31056 {
31057 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31059 },
31060 /* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
31061 {
31062 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31064 },
31065 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31066 {
31067 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31069 },
31070 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
31071 {
31072 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31074 },
31075 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
31076 {
31077 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31079 },
31080 /* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
31081 {
31082 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31084 },
31085 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31086 {
31087 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31089 },
31090 /* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31091 {
31092 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31094 },
31095 /* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31096 {
31097 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31099 },
31100 /* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31101 {
31102 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31104 },
31105 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31106 {
31107 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31109 },
31110 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31111 {
31112 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31114 },
31115 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31116 {
31117 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31119 },
31120 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31121 {
31122 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31124 },
31125 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31126 {
31127 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31129 },
31130 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31131 {
31132 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31134 },
31135 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31136 {
31137 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31139 },
31140 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31141 {
31142 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31144 },
31145 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
31146 {
31147 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31149 },
31150 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31151 {
31152 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31154 },
31155 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31156 {
31157 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31159 },
31160 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
31161 {
31162 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31164 },
31165 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
31166 {
31167 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31169 },
31170 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
31171 {
31172 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31174 },
31175 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
31176 {
31177 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31179 },
31180 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
31181 {
31182 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31184 },
31185 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
31186 {
31187 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31189 },
31190 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
31191 {
31192 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31194 },
31195 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
31196 {
31197 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31199 },
31200 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
31201 {
31202 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31204 },
31205 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
31206 {
31207 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31209 },
31210 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
31211 {
31212 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31214 },
31215 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
31216 {
31217 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31219 },
31220 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
31221 {
31222 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31224 },
31225 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
31226 {
31227 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31229 },
31230 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
31231 {
31232 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31234 },
31235 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
31236 {
31237 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31239 },
31240 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
31241 {
31242 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31244 },
31245 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
31246 {
31247 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31249 },
31250 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
31251 {
31252 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31254 },
31255 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
31256 {
31257 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31259 },
31260 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
31261 {
31262 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31264 },
31265 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
31266 {
31267 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31269 },
31270 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
31271 {
31272 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31274 },
31275 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
31276 {
31277 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31279 },
31280 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
31281 {
31282 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31284 },
31285 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31286 {
31287 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31289 },
31290 /* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
31291 {
31292 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31294 },
31295 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31296 {
31297 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31299 },
31300 /* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
31301 {
31302 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31304 },
31305 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31306 {
31307 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31309 },
31310 /* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
31311 {
31312 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31314 },
31315 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
31316 {
31317 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31319 },
31320 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
31321 {
31322 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31324 },
31325 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
31326 {
31327 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31329 },
31330 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
31331 {
31332 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31334 },
31335 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
31336 {
31337 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31339 },
31340 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
31341 {
31342 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31344 },
31345 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
31346 {
31347 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31349 },
31350 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
31351 {
31352 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31354 },
31355 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
31356 {
31357 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31359 },
31360 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
31361 {
31362 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31364 },
31365 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
31366 {
31367 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31369 },
31370 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
31371 {
31372 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31374 },
31375 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
31376 {
31377 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31379 },
31380 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
31381 {
31382 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31384 },
31385 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
31386 {
31387 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31389 },
31390 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
31391 {
31392 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31394 },
31395 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
31396 {
31397 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31399 },
31400 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
31401 {
31402 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31404 },
31405 /* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
31406 {
31407 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31409 },
31410 /* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
31411 {
31412 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31414 },
31415 /* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
31416 {
31417 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31419 },
31420 /* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
31421 {
31422 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31424 },
31425 /* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
31426 {
31427 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31429 },
31430 /* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
31431 {
31432 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31434 },
31435 /* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
31436 {
31437 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31439 },
31440 /* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
31441 {
31442 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31444 },
31445 /* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
31446 {
31447 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31449 },
31450 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31451 {
31452 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31454 },
31455 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31456 {
31457 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31459 },
31460 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
31461 {
31462 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31464 },
31465 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31466 {
31467 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31469 },
31470 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31471 {
31472 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31474 },
31475 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
31476 {
31477 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31479 },
31480 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31481 {
31482 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31484 },
31485 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31486 {
31487 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31489 },
31490 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
31491 {
31492 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31494 },
31495 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
31496 {
31497 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31499 },
31500 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
31501 {
31502 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31504 },
31505 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
31506 {
31507 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31509 },
31510 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
31511 {
31512 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31514 },
31515 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
31516 {
31517 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31519 },
31520 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
31521 {
31522 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31524 },
31525 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
31526 {
31527 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31529 },
31530 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
31531 {
31532 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31534 },
31535 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
31536 {
31537 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31539 },
31540 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
31541 {
31542 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31544 },
31545 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
31546 {
31547 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31549 },
31550 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
31551 {
31552 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31554 },
31555 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
31556 {
31557 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31559 },
31560 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
31561 {
31562 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31564 },
31565 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
31566 {
31567 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31569 },
31570 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
31571 {
31572 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31574 },
31575 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
31576 {
31577 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31579 },
31580 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
31581 {
31582 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31584 },
31585 /* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
31586 {
31587 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
31588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31589 },
31590 /* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
31591 {
31592 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40,
31593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31594 },
31595 /* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
31596 {
31597 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40,
31598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31599 },
31600 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31601 {
31602 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48,
31603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31604 },
31605 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
31606 {
31607 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48,
31608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31609 },
31610 /* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
31611 {
31612 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48,
31613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31614 },
31615 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31616 {
31617 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56,
31618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31619 },
31620 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
31621 {
31622 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56,
31623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31624 },
31625 /* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
31626 {
31627 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56,
31628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31629 },
31630 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
31631 {
31632 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56,
31633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31634 },
31635 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31636 {
31637 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64,
31638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31639 },
31640 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
31641 {
31642 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64,
31643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31644 },
31645 /* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
31646 {
31647 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
31648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31649 },
31650 /* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
31651 {
31652 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32,
31653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31654 },
31655 /* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
31656 {
31657 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32,
31658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31659 },
31660 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31661 {
31662 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40,
31663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31664 },
31665 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
31666 {
31667 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40,
31668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31669 },
31670 /* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
31671 {
31672 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40,
31673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31674 },
31675 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31676 {
31677 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48,
31678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31679 },
31680 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
31681 {
31682 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48,
31683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31684 },
31685 /* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
31686 {
31687 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48,
31688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31689 },
31690 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
31691 {
31692 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48,
31693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31694 },
31695 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31696 {
31697 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56,
31698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31699 },
31700 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
31701 {
31702 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56,
31703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31704 },
31705 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31706 {
31707 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31709 },
31710 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
31711 {
31712 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31714 },
31715 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
31716 {
31717 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31719 },
31720 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31721 {
31722 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31724 },
31725 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
31726 {
31727 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31729 },
31730 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
31731 {
31732 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31734 },
31735 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31736 {
31737 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31739 },
31740 /* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
31741 {
31742 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31744 },
31745 /* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
31746 {
31747 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31749 },
31750 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
31751 {
31752 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31754 },
31755 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31756 {
31757 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31759 },
31760 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31761 {
31762 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31764 },
31765 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
31766 {
31767 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31769 },
31770 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31771 {
31772 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31774 },
31775 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31776 {
31777 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31779 },
31780 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
31781 {
31782 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31784 },
31785 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31786 {
31787 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31789 },
31790 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31791 {
31792 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31794 },
31795 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
31796 {
31797 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31799 },
31800 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
31801 {
31802 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31804 },
31805 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
31806 {
31807 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31809 },
31810 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
31811 {
31812 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31814 },
31815 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
31816 {
31817 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31819 },
31820 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
31821 {
31822 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31824 },
31825 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31826 {
31827 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31829 },
31830 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31831 {
31832 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31834 },
31835 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31836 {
31837 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31839 },
31840 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31841 {
31842 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31844 },
31845 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31846 {
31847 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31849 },
31850 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31851 {
31852 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31854 },
31855 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31856 {
31857 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31859 },
31860 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31861 {
31862 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31864 },
31865 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31866 {
31867 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31869 },
31870 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31871 {
31872 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31874 },
31875 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31876 {
31877 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31879 },
31880 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31881 {
31882 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31884 },
31885 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31886 {
31887 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31889 },
31890 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
31891 {
31892 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31894 },
31895 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
31896 {
31897 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31899 },
31900 /* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
31901 {
31902 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31904 },
31905 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31906 {
31907 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31909 },
31910 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
31911 {
31912 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31914 },
31915 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
31916 {
31917 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31919 },
31920 /* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
31921 {
31922 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31924 },
31925 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31926 {
31927 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31929 },
31930 /* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31931 {
31932 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31934 },
31935 /* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31936 {
31937 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31939 },
31940 /* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31941 {
31942 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31944 },
31945 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31946 {
31947 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31949 },
31950 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31951 {
31952 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31954 },
31955 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31956 {
31957 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31959 },
31960 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31961 {
31962 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31964 },
31965 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31966 {
31967 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31969 },
31970 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31971 {
31972 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31974 },
31975 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31976 {
31977 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31979 },
31980 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31981 {
31982 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31984 },
31985 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
31986 {
31987 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
31988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31989 },
31990 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31991 {
31992 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
31993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31994 },
31995 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31996 {
31997 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
31998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31999 },
32000 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32001 {
32002 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32004 },
32005 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32006 {
32007 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32009 },
32010 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32011 {
32012 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32014 },
32015 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32016 {
32017 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32019 },
32020 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32021 {
32022 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32024 },
32025 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32026 {
32027 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32029 },
32030 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32031 {
32032 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32034 },
32035 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32036 {
32037 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32039 },
32040 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32041 {
32042 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32044 },
32045 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32046 {
32047 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32049 },
32050 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32051 {
32052 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32054 },
32055 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32056 {
32057 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32059 },
32060 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32061 {
32062 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32064 },
32065 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32066 {
32067 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32069 },
32070 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32071 {
32072 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32074 },
32075 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32076 {
32077 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32079 },
32080 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32081 {
32082 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32084 },
32085 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32086 {
32087 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32089 },
32090 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32091 {
32092 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32094 },
32095 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32096 {
32097 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32099 },
32100 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
32101 {
32102 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32104 },
32105 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32106 {
32107 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32109 },
32110 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32111 {
32112 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32114 },
32115 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32116 {
32117 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32119 },
32120 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
32121 {
32122 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32124 },
32125 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
32126 {
32127 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32129 },
32130 /* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
32131 {
32132 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32134 },
32135 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
32136 {
32137 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32139 },
32140 /* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
32141 {
32142 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32144 },
32145 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32146 {
32147 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32149 },
32150 /* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32151 {
32152 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32154 },
32155 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32156 {
32157 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32159 },
32160 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32161 {
32162 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32164 },
32165 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32166 {
32167 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32169 },
32170 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32171 {
32172 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32174 },
32175 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32176 {
32177 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32179 },
32180 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32181 {
32182 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32184 },
32185 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32186 {
32187 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32189 },
32190 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32191 {
32192 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32194 },
32195 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32196 {
32197 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32199 },
32200 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32201 {
32202 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32204 },
32205 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32206 {
32207 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32209 },
32210 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32211 {
32212 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32214 },
32215 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32216 {
32217 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32219 },
32220 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32221 {
32222 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32224 },
32225 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32226 {
32227 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32229 },
32230 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
32231 {
32232 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32234 },
32235 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32236 {
32237 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32239 },
32240 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
32241 {
32242 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32244 },
32245 /* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
32246 {
32247 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32249 },
32250 /* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
32251 {
32252 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32254 },
32255 /* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
32256 {
32257 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32259 },
32260 /* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
32261 {
32262 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32264 },
32265 /* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
32266 {
32267 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32269 },
32270 /* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
32271 {
32272 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32274 },
32275 /* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
32276 {
32277 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32279 },
32280 /* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
32281 {
32282 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32284 },
32285 /* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
32286 {
32287 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32289 },
32290 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32291 {
32292 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32294 },
32295 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32296 {
32297 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32299 },
32300 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
32301 {
32302 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32304 },
32305 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32306 {
32307 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32309 },
32310 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32311 {
32312 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32314 },
32315 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
32316 {
32317 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32319 },
32320 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32321 {
32322 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32324 },
32325 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32326 {
32327 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32329 },
32330 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
32331 {
32332 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32334 },
32335 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
32336 {
32337 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32339 },
32340 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
32341 {
32342 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32344 },
32345 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
32346 {
32347 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32349 },
32350 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
32351 {
32352 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32354 },
32355 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
32356 {
32357 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32359 },
32360 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
32361 {
32362 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32364 },
32365 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
32366 {
32367 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32369 },
32370 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
32371 {
32372 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32374 },
32375 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
32376 {
32377 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32379 },
32380 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
32381 {
32382 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32384 },
32385 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
32386 {
32387 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32389 },
32390 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
32391 {
32392 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32394 },
32395 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
32396 {
32397 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32399 },
32400 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
32401 {
32402 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32404 },
32405 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
32406 {
32407 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32409 },
32410 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
32411 {
32412 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32414 },
32415 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
32416 {
32417 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32419 },
32420 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
32421 {
32422 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32424 },
32425 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32426 {
32427 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32429 },
32430 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
32431 {
32432 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32434 },
32435 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
32436 {
32437 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32439 },
32440 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32441 {
32442 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32444 },
32445 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
32446 {
32447 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32449 },
32450 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
32451 {
32452 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32454 },
32455 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32456 {
32457 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32459 },
32460 /* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
32461 {
32462 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32464 },
32465 /* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
32466 {
32467 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32469 },
32470 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
32471 {
32472 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32474 },
32475 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32476 {
32477 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32479 },
32480 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32481 {
32482 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32484 },
32485 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
32486 {
32487 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32489 },
32490 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32491 {
32492 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32494 },
32495 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32496 {
32497 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32499 },
32500 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
32501 {
32502 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32504 },
32505 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32506 {
32507 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32509 },
32510 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32511 {
32512 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32514 },
32515 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
32516 {
32517 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32519 },
32520 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
32521 {
32522 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32524 },
32525 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
32526 {
32527 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32529 },
32530 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
32531 {
32532 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32534 },
32535 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
32536 {
32537 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32539 },
32540 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
32541 {
32542 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32544 },
32545 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
32546 {
32547 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32549 },
32550 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
32551 {
32552 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32554 },
32555 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
32556 {
32557 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32559 },
32560 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
32561 {
32562 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32564 },
32565 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
32566 {
32567 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32569 },
32570 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
32571 {
32572 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32574 },
32575 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
32576 {
32577 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32579 },
32580 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
32581 {
32582 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32584 },
32585 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
32586 {
32587 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32589 },
32590 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
32591 {
32592 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32594 },
32595 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
32596 {
32597 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32599 },
32600 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
32601 {
32602 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32604 },
32605 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32606 {
32607 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32609 },
32610 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
32611 {
32612 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32614 },
32615 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
32616 {
32617 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32619 },
32620 /* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
32621 {
32622 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32624 },
32625 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32626 {
32627 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32629 },
32630 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
32631 {
32632 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32634 },
32635 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
32636 {
32637 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32639 },
32640 /* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
32641 {
32642 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32644 },
32645 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32646 {
32647 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32649 },
32650 /* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
32651 {
32652 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32654 },
32655 /* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
32656 {
32657 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32659 },
32660 /* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
32661 {
32662 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32664 },
32665 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
32666 {
32667 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32669 },
32670 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32671 {
32672 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32674 },
32675 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32676 {
32677 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32679 },
32680 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
32681 {
32682 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32684 },
32685 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
32686 {
32687 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32689 },
32690 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32691 {
32692 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32694 },
32695 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32696 {
32697 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32699 },
32700 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
32701 {
32702 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32704 },
32705 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32706 {
32707 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32709 },
32710 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32711 {
32712 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32714 },
32715 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32716 {
32717 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32719 },
32720 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32721 {
32722 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32724 },
32725 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32726 {
32727 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32729 },
32730 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32731 {
32732 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32734 },
32735 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32736 {
32737 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32739 },
32740 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32741 {
32742 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32744 },
32745 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32746 {
32747 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32749 },
32750 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32751 {
32752 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32754 },
32755 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32756 {
32757 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32759 },
32760 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32761 {
32762 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32764 },
32765 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32766 {
32767 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32769 },
32770 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32771 {
32772 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32774 },
32775 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32776 {
32777 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32779 },
32780 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32781 {
32782 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32784 },
32785 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32786 {
32787 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32789 },
32790 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32791 {
32792 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32794 },
32795 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32796 {
32797 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32799 },
32800 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32801 {
32802 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32804 },
32805 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32806 {
32807 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32809 },
32810 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32811 {
32812 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32814 },
32815 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32816 {
32817 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32819 },
32820 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
32821 {
32822 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32824 },
32825 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32826 {
32827 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32829 },
32830 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32831 {
32832 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32834 },
32835 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32836 {
32837 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32839 },
32840 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
32841 {
32842 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32844 },
32845 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32846 {
32847 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32849 },
32850 /* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
32851 {
32852 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32854 },
32855 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32856 {
32857 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32859 },
32860 /* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
32861 {
32862 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32864 },
32865 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32866 {
32867 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32869 },
32870 /* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32871 {
32872 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32874 },
32875 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32876 {
32877 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32879 },
32880 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32881 {
32882 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32884 },
32885 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32886 {
32887 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32889 },
32890 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32891 {
32892 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32894 },
32895 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32896 {
32897 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32899 },
32900 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32901 {
32902 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32904 },
32905 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32906 {
32907 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32909 },
32910 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32911 {
32912 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32914 },
32915 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32916 {
32917 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32919 },
32920 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32921 {
32922 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32924 },
32925 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32926 {
32927 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32929 },
32930 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32931 {
32932 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32934 },
32935 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32936 {
32937 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32939 },
32940 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32941 {
32942 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32944 },
32945 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32946 {
32947 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32949 },
32950 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
32951 {
32952 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32954 },
32955 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32956 {
32957 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32959 },
32960 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
32961 {
32962 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32964 },
32965 /* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
32966 {
32967 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32969 },
32970 /* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
32971 {
32972 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32974 },
32975 /* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
32976 {
32977 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32979 },
32980 /* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
32981 {
32982 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
32983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32984 },
32985 /* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
32986 {
32987 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
32988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32989 },
32990 /* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
32991 {
32992 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
32993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32994 },
32995 /* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
32996 {
32997 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
32998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32999 },
33000 /* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
33001 {
33002 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33004 },
33005 /* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
33006 {
33007 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33009 },
33010 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33011 {
33012 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33014 },
33015 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33016 {
33017 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33019 },
33020 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
33021 {
33022 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33024 },
33025 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33026 {
33027 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33029 },
33030 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33031 {
33032 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33034 },
33035 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
33036 {
33037 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33039 },
33040 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33041 {
33042 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33044 },
33045 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33046 {
33047 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33049 },
33050 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
33051 {
33052 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33054 },
33055 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
33056 {
33057 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33059 },
33060 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
33061 {
33062 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33064 },
33065 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
33066 {
33067 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33069 },
33070 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
33071 {
33072 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33074 },
33075 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
33076 {
33077 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33079 },
33080 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
33081 {
33082 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33084 },
33085 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
33086 {
33087 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33089 },
33090 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
33091 {
33092 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33094 },
33095 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
33096 {
33097 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33099 },
33100 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
33101 {
33102 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33104 },
33105 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
33106 {
33107 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33109 },
33110 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
33111 {
33112 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33114 },
33115 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
33116 {
33117 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33119 },
33120 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
33121 {
33122 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33124 },
33125 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
33126 {
33127 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33129 },
33130 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
33131 {
33132 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33134 },
33135 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
33136 {
33137 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33139 },
33140 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
33141 {
33142 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33144 },
33145 /* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
33146 {
33147 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
33148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33149 },
33150 /* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
33151 {
33152 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40,
33153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33154 },
33155 /* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
33156 {
33157 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40,
33158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33159 },
33160 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33161 {
33162 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48,
33163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33164 },
33165 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
33166 {
33167 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48,
33168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33169 },
33170 /* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
33171 {
33172 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48,
33173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33174 },
33175 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33176 {
33177 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56,
33178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33179 },
33180 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
33181 {
33182 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56,
33183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33184 },
33185 /* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
33186 {
33187 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56,
33188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33189 },
33190 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
33191 {
33192 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56,
33193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33194 },
33195 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33196 {
33197 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64,
33198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33199 },
33200 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
33201 {
33202 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64,
33203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33204 },
33205 /* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
33206 {
33207 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
33208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33209 },
33210 /* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
33211 {
33212 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32,
33213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33214 },
33215 /* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
33216 {
33217 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32,
33218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33219 },
33220 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33221 {
33222 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40,
33223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33224 },
33225 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
33226 {
33227 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40,
33228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33229 },
33230 /* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
33231 {
33232 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40,
33233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33234 },
33235 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33236 {
33237 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48,
33238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33239 },
33240 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
33241 {
33242 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48,
33243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33244 },
33245 /* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
33246 {
33247 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48,
33248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33249 },
33250 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
33251 {
33252 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48,
33253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33254 },
33255 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33256 {
33257 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56,
33258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33259 },
33260 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
33261 {
33262 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
33263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33264 },
33265 /* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
33266 {
33267 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32,
33268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33269 },
33270 /* ste.w ${Dsp-16-u16}[sb],[a1a0] */
33271 {
33272 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32,
33273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33274 },
33275 /* ste.w ${Dsp-16-u16},[a1a0] */
33276 {
33277 M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32,
33278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33279 },
33280 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
33281 {
33282 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56,
33283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33284 },
33285 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33286 {
33287 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56,
33288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33289 },
33290 /* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33291 {
33292 M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56,
33293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33294 },
33295 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33296 {
33297 M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56,
33298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33299 },
33300 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33301 {
33302 M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56,
33303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33304 },
33305 /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
33306 {
33307 M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56,
33308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33309 },
33310 /* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
33311 {
33312 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24,
33313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33314 },
33315 /* ste.w ${Dsp-16-u8}[sb],[a1a0] */
33316 {
33317 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24,
33318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33319 },
33320 /* ste.w ${Dsp-16-s8}[fb],[a1a0] */
33321 {
33322 M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24,
33323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33324 },
33325 /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33326 {
33327 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48,
33328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33329 },
33330 /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33331 {
33332 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48,
33333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33334 },
33335 /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33336 {
33337 M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48,
33338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33339 },
33340 /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33341 {
33342 M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48,
33343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33344 },
33345 /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33346 {
33347 M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48,
33348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33349 },
33350 /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33351 {
33352 M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48,
33353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33354 },
33355 /* ste.w $Dst16RnHI,[a1a0] */
33356 {
33357 M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16,
33358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33359 },
33360 /* ste.w $Dst16AnHI,[a1a0] */
33361 {
33362 M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16,
33363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33364 },
33365 /* ste.w [$Dst16An],[a1a0] */
33366 {
33367 M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16,
33368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33369 },
33370 /* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
33371 {
33372 M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40,
33373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33374 },
33375 /* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
33376 {
33377 M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40,
33378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33379 },
33380 /* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
33381 {
33382 M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40,
33383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33384 },
33385 /* ste.w $Dst16RnHI,${Dsp-16-u20} */
33386 {
33387 M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40,
33388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33389 },
33390 /* ste.w $Dst16AnHI,${Dsp-16-u20} */
33391 {
33392 M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40,
33393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33394 },
33395 /* ste.w [$Dst16An],${Dsp-16-u20} */
33396 {
33397 M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40,
33398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33399 },
33400 /* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
33401 {
33402 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32,
33403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33404 },
33405 /* ste.b ${Dsp-16-u16}[sb],[a1a0] */
33406 {
33407 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32,
33408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33409 },
33410 /* ste.b ${Dsp-16-u16},[a1a0] */
33411 {
33412 M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32,
33413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33414 },
33415 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
33416 {
33417 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56,
33418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33419 },
33420 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33421 {
33422 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56,
33423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33424 },
33425 /* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33426 {
33427 M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56,
33428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33429 },
33430 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33431 {
33432 M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56,
33433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33434 },
33435 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33436 {
33437 M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56,
33438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33439 },
33440 /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
33441 {
33442 M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56,
33443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33444 },
33445 /* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
33446 {
33447 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24,
33448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33449 },
33450 /* ste.b ${Dsp-16-u8}[sb],[a1a0] */
33451 {
33452 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24,
33453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33454 },
33455 /* ste.b ${Dsp-16-s8}[fb],[a1a0] */
33456 {
33457 M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24,
33458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33459 },
33460 /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33461 {
33462 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48,
33463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33464 },
33465 /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33466 {
33467 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48,
33468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33469 },
33470 /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33471 {
33472 M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48,
33473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33474 },
33475 /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33476 {
33477 M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48,
33478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33479 },
33480 /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33481 {
33482 M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48,
33483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33484 },
33485 /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33486 {
33487 M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48,
33488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33489 },
33490 /* ste.b $Dst16RnQI,[a1a0] */
33491 {
33492 M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16,
33493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33494 },
33495 /* ste.b $Dst16AnQI,[a1a0] */
33496 {
33497 M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16,
33498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33499 },
33500 /* ste.b [$Dst16An],[a1a0] */
33501 {
33502 M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16,
33503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33504 },
33505 /* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
33506 {
33507 M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40,
33508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33509 },
33510 /* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
33511 {
33512 M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40,
33513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33514 },
33515 /* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
33516 {
33517 M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40,
33518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33519 },
33520 /* ste.b $Dst16RnQI,${Dsp-16-u20} */
33521 {
33522 M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40,
33523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33524 },
33525 /* ste.b $Dst16AnQI,${Dsp-16-u20} */
33526 {
33527 M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40,
33528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33529 },
33530 /* ste.b [$Dst16An],${Dsp-16-u20} */
33531 {
33532 M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40,
33533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33534 },
33535 /* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
33536 {
33537 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32,
33538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33539 },
33540 /* lde.w [a1a0],${Dsp-16-u16}[sb] */
33541 {
33542 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32,
33543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33544 },
33545 /* lde.w [a1a0],${Dsp-16-u16} */
33546 {
33547 M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32,
33548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33549 },
33550 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
33551 {
33552 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56,
33553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33554 },
33555 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33556 {
33557 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56,
33558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33559 },
33560 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
33561 {
33562 M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56,
33563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33564 },
33565 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33566 {
33567 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56,
33568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33569 },
33570 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33571 {
33572 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56,
33573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33574 },
33575 /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
33576 {
33577 M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56,
33578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33579 },
33580 /* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
33581 {
33582 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24,
33583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33584 },
33585 /* lde.w [a1a0],${Dsp-16-u8}[sb] */
33586 {
33587 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24,
33588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33589 },
33590 /* lde.w [a1a0],${Dsp-16-s8}[fb] */
33591 {
33592 M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24,
33593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33594 },
33595 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33596 {
33597 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48,
33598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33599 },
33600 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33601 {
33602 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48,
33603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33604 },
33605 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33606 {
33607 M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48,
33608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33609 },
33610 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33611 {
33612 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48,
33613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33614 },
33615 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33616 {
33617 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48,
33618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33619 },
33620 /* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33621 {
33622 M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48,
33623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33624 },
33625 /* lde.w [a1a0],$Dst16RnHI */
33626 {
33627 M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16,
33628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33629 },
33630 /* lde.w [a1a0],$Dst16AnHI */
33631 {
33632 M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16,
33633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33634 },
33635 /* lde.w [a1a0],[$Dst16An] */
33636 {
33637 M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16,
33638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33639 },
33640 /* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
33641 {
33642 M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40,
33643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33644 },
33645 /* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
33646 {
33647 M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40,
33648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33649 },
33650 /* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
33651 {
33652 M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40,
33653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33654 },
33655 /* lde.w ${Dsp-16-u20},$Dst16RnHI */
33656 {
33657 M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40,
33658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33659 },
33660 /* lde.w ${Dsp-16-u20},$Dst16AnHI */
33661 {
33662 M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40,
33663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33664 },
33665 /* lde.w ${Dsp-16-u20},[$Dst16An] */
33666 {
33667 M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40,
33668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33669 },
33670 /* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
33671 {
33672 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32,
33673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33674 },
33675 /* lde.b [a1a0],${Dsp-16-u16}[sb] */
33676 {
33677 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32,
33678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33679 },
33680 /* lde.b [a1a0],${Dsp-16-u16} */
33681 {
33682 M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32,
33683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33684 },
33685 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
33686 {
33687 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56,
33688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33689 },
33690 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33691 {
33692 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56,
33693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33694 },
33695 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
33696 {
33697 M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56,
33698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33699 },
33700 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33701 {
33702 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56,
33703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33704 },
33705 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33706 {
33707 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56,
33708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33709 },
33710 /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
33711 {
33712 M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56,
33713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33714 },
33715 /* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
33716 {
33717 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24,
33718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33719 },
33720 /* lde.b [a1a0],${Dsp-16-u8}[sb] */
33721 {
33722 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24,
33723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33724 },
33725 /* lde.b [a1a0],${Dsp-16-s8}[fb] */
33726 {
33727 M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24,
33728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33729 },
33730 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33731 {
33732 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48,
33733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33734 },
33735 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33736 {
33737 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48,
33738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33739 },
33740 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33741 {
33742 M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48,
33743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33744 },
33745 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33746 {
33747 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48,
33748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33749 },
33750 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33751 {
33752 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48,
33753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33754 },
33755 /* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33756 {
33757 M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48,
33758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33759 },
33760 /* lde.b [a1a0],$Dst16RnQI */
33761 {
33762 M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16,
33763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33764 },
33765 /* lde.b [a1a0],$Dst16AnQI */
33766 {
33767 M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16,
33768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33769 },
33770 /* lde.b [a1a0],[$Dst16An] */
33771 {
33772 M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16,
33773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33774 },
33775 /* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
33776 {
33777 M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40,
33778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33779 },
33780 /* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
33781 {
33782 M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40,
33783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33784 },
33785 /* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
33786 {
33787 M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40,
33788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33789 },
33790 /* lde.b ${Dsp-16-u20},$Dst16RnQI */
33791 {
33792 M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40,
33793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33794 },
33795 /* lde.b ${Dsp-16-u20},$Dst16AnQI */
33796 {
33797 M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40,
33798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33799 },
33800 /* lde.b ${Dsp-16-u20},[$Dst16An] */
33801 {
33802 M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40,
33803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33804 },
33805 /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
33806 {
33807 M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24,
33808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33809 },
33810 /* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
33811 {
33812 M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24,
33813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33814 },
33815 /* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
33816 {
33817 M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24,
33818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33819 },
33820 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33821 {
33822 M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32,
33823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33824 },
33825 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33826 {
33827 M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40,
33828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33829 },
33830 /* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33831 {
33832 M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48,
33833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33834 },
33835 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
33836 {
33837 M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32,
33838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33839 },
33840 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
33841 {
33842 M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40,
33843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33844 },
33845 /* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
33846 {
33847 M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32,
33848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33849 },
33850 /* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
33851 {
33852 M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40,
33853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33854 },
33855 /* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
33856 {
33857 M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40,
33858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33859 },
33860 /* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
33861 {
33862 M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48,
33863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33864 },
33865 /* stc ${cr2-32},$Dst32RnUnprefixedSI */
33866 {
33867 M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16,
33868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33869 },
33870 /* stc ${cr2-32},$Dst32AnUnprefixedSI */
33871 {
33872 M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16,
33873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33874 },
33875 /* stc ${cr2-32},[$Dst32AnUnprefixed] */
33876 {
33877 M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16,
33878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33879 },
33880 /* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
33881 {
33882 M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24,
33883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33884 },
33885 /* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
33886 {
33887 M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32,
33888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33889 },
33890 /* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
33891 {
33892 M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40,
33893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33894 },
33895 /* stc ${cr2-32},${Dsp-16-u8}[sb] */
33896 {
33897 M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24,
33898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33899 },
33900 /* stc ${cr2-32},${Dsp-16-u16}[sb] */
33901 {
33902 M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32,
33903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33904 },
33905 /* stc ${cr2-32},${Dsp-16-s8}[fb] */
33906 {
33907 M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24,
33908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33909 },
33910 /* stc ${cr2-32},${Dsp-16-s16}[fb] */
33911 {
33912 M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32,
33913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33914 },
33915 /* stc ${cr2-32},${Dsp-16-u16} */
33916 {
33917 M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32,
33918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33919 },
33920 /* stc ${cr2-32},${Dsp-16-u24} */
33921 {
33922 M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40,
33923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33924 },
33925 /* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
33926 {
33927 M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24,
33928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33929 },
33930 /* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
33931 {
33932 M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24,
33933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33934 },
33935 /* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
33936 {
33937 M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24,
33938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33939 },
33940 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33941 {
33942 M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32,
33943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33944 },
33945 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33946 {
33947 M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40,
33948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33949 },
33950 /* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33951 {
33952 M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48,
33953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33954 },
33955 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
33956 {
33957 M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32,
33958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33959 },
33960 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
33961 {
33962 M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40,
33963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33964 },
33965 /* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
33966 {
33967 M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32,
33968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33969 },
33970 /* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
33971 {
33972 M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40,
33973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33974 },
33975 /* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
33976 {
33977 M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40,
33978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33979 },
33980 /* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
33981 {
33982 M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48,
33983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33984 },
33985 /* stc pc,$Dst16RnHI */
33986 {
33987 M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16,
33988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33989 },
33990 /* stc pc,$Dst16AnHI */
33991 {
33992 M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16,
33993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33994 },
33995 /* stc pc,[$Dst16An] */
33996 {
33997 M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16,
33998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33999 },
34000 /* stc pc,${Dsp-16-u8}[$Dst16An] */
34001 {
34002 M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24,
34003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34004 },
34005 /* stc pc,${Dsp-16-u16}[$Dst16An] */
34006 {
34007 M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32,
34008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34009 },
34010 /* stc pc,${Dsp-16-u8}[sb] */
34011 {
34012 M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24,
34013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34014 },
34015 /* stc pc,${Dsp-16-u16}[sb] */
34016 {
34017 M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32,
34018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34019 },
34020 /* stc pc,${Dsp-16-s8}[fb] */
34021 {
34022 M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24,
34023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34024 },
34025 /* stc pc,${Dsp-16-u16} */
34026 {
34027 M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32,
34028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34029 },
34030 /* stc ${cr16},$Dst16RnHI */
34031 {
34032 M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16,
34033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34034 },
34035 /* stc ${cr16},$Dst16AnHI */
34036 {
34037 M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16,
34038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34039 },
34040 /* stc ${cr16},[$Dst16An] */
34041 {
34042 M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16,
34043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34044 },
34045 /* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
34046 {
34047 M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24,
34048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34049 },
34050 /* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
34051 {
34052 M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32,
34053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34054 },
34055 /* stc ${cr16},${Dsp-16-u8}[sb] */
34056 {
34057 M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24,
34058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34059 },
34060 /* stc ${cr16},${Dsp-16-u16}[sb] */
34061 {
34062 M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32,
34063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34064 },
34065 /* stc ${cr16},${Dsp-16-s8}[fb] */
34066 {
34067 M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24,
34068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34069 },
34070 /* stc ${cr16},${Dsp-16-u16} */
34071 {
34072 M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32,
34073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34074 },
34075 /* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
34076 {
34077 M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24,
34078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34079 },
34080 /* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
34081 {
34082 M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24,
34083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34084 },
34085 /* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
34086 {
34087 M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24,
34088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34089 },
34090 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34091 {
34092 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32,
34093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34094 },
34095 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34096 {
34097 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40,
34098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34099 },
34100 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34101 {
34102 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48,
34103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34104 },
34105 /* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
34106 {
34107 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32,
34108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34109 },
34110 /* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
34111 {
34112 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40,
34113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34114 },
34115 /* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
34116 {
34117 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32,
34118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34119 },
34120 /* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
34121 {
34122 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40,
34123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34124 },
34125 /* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
34126 {
34127 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40,
34128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34129 },
34130 /* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
34131 {
34132 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48,
34133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34134 },
34135 /* ldc $Dst32RnUnprefixedSI,${cr2-32} */
34136 {
34137 M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16,
34138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34139 },
34140 /* ldc $Dst32AnUnprefixedSI,${cr2-32} */
34141 {
34142 M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16,
34143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34144 },
34145 /* ldc [$Dst32AnUnprefixed],${cr2-32} */
34146 {
34147 M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16,
34148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34149 },
34150 /* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
34151 {
34152 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24,
34153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34154 },
34155 /* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
34156 {
34157 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32,
34158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34159 },
34160 /* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
34161 {
34162 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40,
34163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34164 },
34165 /* ldc ${Dsp-16-u8}[sb],${cr2-32} */
34166 {
34167 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24,
34168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34169 },
34170 /* ldc ${Dsp-16-u16}[sb],${cr2-32} */
34171 {
34172 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32,
34173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34174 },
34175 /* ldc ${Dsp-16-s8}[fb],${cr2-32} */
34176 {
34177 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24,
34178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34179 },
34180 /* ldc ${Dsp-16-s16}[fb],${cr2-32} */
34181 {
34182 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32,
34183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34184 },
34185 /* ldc ${Dsp-16-u16},${cr2-32} */
34186 {
34187 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32,
34188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34189 },
34190 /* ldc ${Dsp-16-u24},${cr2-32} */
34191 {
34192 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40,
34193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34194 },
34195 /* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
34196 {
34197 M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24,
34198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34199 },
34200 /* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
34201 {
34202 M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24,
34203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34204 },
34205 /* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
34206 {
34207 M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24,
34208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34209 },
34210 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34211 {
34212 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32,
34213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34214 },
34215 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34216 {
34217 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40,
34218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34219 },
34220 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34221 {
34222 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48,
34223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34224 },
34225 /* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
34226 {
34227 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32,
34228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34229 },
34230 /* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
34231 {
34232 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40,
34233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34234 },
34235 /* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
34236 {
34237 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32,
34238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34239 },
34240 /* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
34241 {
34242 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40,
34243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34244 },
34245 /* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
34246 {
34247 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40,
34248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34249 },
34250 /* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
34251 {
34252 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48,
34253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34254 },
34255 /* ldc $Dst16RnHI,${cr16} */
34256 {
34257 M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16,
34258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34259 },
34260 /* ldc $Dst16AnHI,${cr16} */
34261 {
34262 M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16,
34263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34264 },
34265 /* ldc [$Dst16An],${cr16} */
34266 {
34267 M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16,
34268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34269 },
34270 /* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
34271 {
34272 M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24,
34273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34274 },
34275 /* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
34276 {
34277 M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32,
34278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34279 },
34280 /* ldc ${Dsp-16-u8}[sb],${cr16} */
34281 {
34282 M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24,
34283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34284 },
34285 /* ldc ${Dsp-16-u16}[sb],${cr16} */
34286 {
34287 M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32,
34288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34289 },
34290 /* ldc ${Dsp-16-s8}[fb],${cr16} */
34291 {
34292 M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24,
34293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34294 },
34295 /* ldc ${Dsp-16-u16},${cr16} */
34296 {
34297 M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
34298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34299 },
34300 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34301 {
34302 M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40,
34303 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34304 },
34305 /* jsri.w ${Dsp-16-u24} */
34306 {
34307 M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
34308 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34309 },
34310 /* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34311 {
34312 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
34313 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34314 },
34315 /* jsri.a ${Dsp-16-u16}[sb] */
34316 {
34317 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
34318 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34319 },
34320 /* jsri.a ${Dsp-16-s16}[fb] */
34321 {
34322 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
34323 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34324 },
34325 /* jsri.a ${Dsp-16-u16} */
34326 {
34327 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
34328 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34329 },
34330 /* jsri.a ${Dsp-16-u16}[$Dst16An] */
34331 {
34332 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32,
34333 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34334 },
34335 /* jsri.a ${Dsp-16-u16}[sb] */
34336 {
34337 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
34338 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34339 },
34340 /* jsri.a ${Dsp-16-u16} */
34341 {
34342 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
34343 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34344 },
34345 /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34346 {
34347 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24,
34348 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34349 },
34350 /* jsri.a ${Dsp-16-u8}[sb] */
34351 {
34352 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24,
34353 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34354 },
34355 /* jsri.a ${Dsp-16-s8}[fb] */
34356 {
34357 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24,
34358 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34359 },
34360 /* jsri.a ${Dsp-16-u8}[$Dst16An] */
34361 {
34362 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24,
34363 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34364 },
34365 /* jsri.a ${Dsp-16-u8}[sb] */
34366 {
34367 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24,
34368 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34369 },
34370 /* jsri.a ${Dsp-16-s8}[fb] */
34371 {
34372 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
34373 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34374 },
34375 /* jsri.a $Dst32RnUnprefixedSI */
34376 {
34377 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
34378 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34379 },
34380 /* jsri.a $Dst32AnUnprefixedSI */
34381 {
34382 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
34383 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34384 },
34385 /* jsri.a [$Dst32AnUnprefixed] */
34386 {
34387 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
34388 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34389 },
34390 /* jsri.a $Dst16RnSI */
34391 {
34392 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
34393 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34394 },
34395 /* jsri.a $Dst16AnSI */
34396 {
34397 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
34398 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34399 },
34400 /* jsri.a [$Dst16An] */
34401 {
34402 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
34403 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34404 },
34405 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34406 {
34407 M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
34408 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34409 },
34410 /* jsri.w ${Dsp-16-u24} */
34411 {
34412 M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
34413 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34414 },
34415 /* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34416 {
34417 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32,
34418 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34419 },
34420 /* jsri.w ${Dsp-16-u16}[sb] */
34421 {
34422 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
34423 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34424 },
34425 /* jsri.w ${Dsp-16-s16}[fb] */
34426 {
34427 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
34428 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34429 },
34430 /* jsri.w ${Dsp-16-u16} */
34431 {
34432 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
34433 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34434 },
34435 /* jsri.w ${Dsp-16-u16}[$Dst16An] */
34436 {
34437 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32,
34438 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34439 },
34440 /* jsri.w ${Dsp-16-u16}[sb] */
34441 {
34442 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
34443 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34444 },
34445 /* jsri.w ${Dsp-16-u16} */
34446 {
34447 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
34448 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34449 },
34450 /* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34451 {
34452 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
34453 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34454 },
34455 /* jsri.w ${Dsp-16-u8}[sb] */
34456 {
34457 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
34458 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34459 },
34460 /* jsri.w ${Dsp-16-s8}[fb] */
34461 {
34462 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
34463 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34464 },
34465 /* jsri.w ${Dsp-16-u8}[$Dst16An] */
34466 {
34467 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
34468 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34469 },
34470 /* jsri.w ${Dsp-16-u8}[sb] */
34471 {
34472 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
34473 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34474 },
34475 /* jsri.w ${Dsp-16-s8}[fb] */
34476 {
34477 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
34478 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34479 },
34480 /* jsri.w $Dst32RnUnprefixedHI */
34481 {
34482 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
34483 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34484 },
34485 /* jsri.w $Dst32AnUnprefixedHI */
34486 {
34487 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
34488 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34489 },
34490 /* jsri.w [$Dst32AnUnprefixed] */
34491 {
34492 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
34493 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34494 },
34495 /* jsri.w $Dst16RnHI */
34496 {
34497 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
34498 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34499 },
34500 /* jsri.w $Dst16AnHI */
34501 {
34502 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
34503 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34504 },
34505 /* jsri.w [$Dst16An] */
34506 {
34507 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
34508 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34509 },
34510 /* jmpi.a $Dst32RnUnprefixedSI */
34511 {
34512 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
34513 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34514 },
34515 /* jmpi.a $Dst32AnUnprefixedSI */
34516 {
34517 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16,
34518 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34519 },
34520 /* jmpi.a [$Dst32AnUnprefixed] */
34521 {
34522 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16,
34523 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34524 },
34525 /* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34526 {
34527 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24,
34528 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34529 },
34530 /* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34531 {
34532 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32,
34533 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34534 },
34535 /* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34536 {
34537 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40,
34538 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34539 },
34540 /* jmpi.a ${Dsp-16-u8}[sb] */
34541 {
34542 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24,
34543 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34544 },
34545 /* jmpi.a ${Dsp-16-u16}[sb] */
34546 {
34547 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32,
34548 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34549 },
34550 /* jmpi.a ${Dsp-16-s8}[fb] */
34551 {
34552 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24,
34553 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34554 },
34555 /* jmpi.a ${Dsp-16-s16}[fb] */
34556 {
34557 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32,
34558 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34559 },
34560 /* jmpi.a ${Dsp-16-u16} */
34561 {
34562 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32,
34563 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34564 },
34565 /* jmpi.a ${Dsp-16-u24} */
34566 {
34567 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40,
34568 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34569 },
34570 /* jmpi.a $Dst16RnSI */
34571 {
34572 M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16,
34573 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34574 },
34575 /* jmpi.a $Dst16AnSI */
34576 {
34577 M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16,
34578 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34579 },
34580 /* jmpi.a [$Dst16An] */
34581 {
34582 M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16,
34583 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34584 },
34585 /* jmpi.a ${Dsp-16-u8}[$Dst16An] */
34586 {
34587 M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24,
34588 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34589 },
34590 /* jmpi.a ${Dsp-16-u16}[$Dst16An] */
34591 {
34592 M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32,
34593 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34594 },
34595 /* jmpi.a ${Dsp-16-u8}[sb] */
34596 {
34597 M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24,
34598 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34599 },
34600 /* jmpi.a ${Dsp-16-u16}[sb] */
34601 {
34602 M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32,
34603 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34604 },
34605 /* jmpi.a ${Dsp-16-s8}[fb] */
34606 {
34607 M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24,
34608 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34609 },
34610 /* jmpi.a ${Dsp-16-u16} */
34611 {
34612 M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32,
34613 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34614 },
34615 /* jmpi.w $Dst32RnUnprefixedHI */
34616 {
34617 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16,
34618 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34619 },
34620 /* jmpi.w $Dst32AnUnprefixedHI */
34621 {
34622 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16,
34623 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34624 },
34625 /* jmpi.w [$Dst32AnUnprefixed] */
34626 {
34627 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16,
34628 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34629 },
34630 /* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34631 {
34632 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24,
34633 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34634 },
34635 /* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34636 {
34637 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32,
34638 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34639 },
34640 /* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34641 {
34642 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40,
34643 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34644 },
34645 /* jmpi.w ${Dsp-16-u8}[sb] */
34646 {
34647 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24,
34648 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34649 },
34650 /* jmpi.w ${Dsp-16-u16}[sb] */
34651 {
34652 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32,
34653 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34654 },
34655 /* jmpi.w ${Dsp-16-s8}[fb] */
34656 {
34657 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24,
34658 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34659 },
34660 /* jmpi.w ${Dsp-16-s16}[fb] */
34661 {
34662 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32,
34663 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34664 },
34665 /* jmpi.w ${Dsp-16-u16} */
34666 {
34667 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32,
34668 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34669 },
34670 /* jmpi.w ${Dsp-16-u24} */
34671 {
34672 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40,
34673 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34674 },
34675 /* jmpi.w $Dst16RnHI */
34676 {
34677 M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16,
34678 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34679 },
34680 /* jmpi.w $Dst16AnHI */
34681 {
34682 M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16,
34683 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34684 },
34685 /* jmpi.w [$Dst16An] */
34686 {
34687 M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16,
34688 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34689 },
34690 /* jmpi.w ${Dsp-16-u8}[$Dst16An] */
34691 {
34692 M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24,
34693 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34694 },
34695 /* jmpi.w ${Dsp-16-u16}[$Dst16An] */
34696 {
34697 M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32,
34698 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34699 },
34700 /* jmpi.w ${Dsp-16-u8}[sb] */
34701 {
34702 M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24,
34703 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34704 },
34705 /* jmpi.w ${Dsp-16-u16}[sb] */
34706 {
34707 M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32,
34708 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34709 },
34710 /* jmpi.w ${Dsp-16-s8}[fb] */
34711 {
34712 M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24,
34713 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34714 },
34715 /* jmpi.w ${Dsp-16-u16} */
34716 {
34717 M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32,
34718 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34719 },
34720 /* indexws.w $Dst32RnUnprefixedHI */
34721 {
34722 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16,
34723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34724 },
34725 /* indexws.w $Dst32AnUnprefixedHI */
34726 {
34727 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16,
34728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34729 },
34730 /* indexws.w [$Dst32AnUnprefixed] */
34731 {
34732 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16,
34733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34734 },
34735 /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34736 {
34737 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24,
34738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34739 },
34740 /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34741 {
34742 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32,
34743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34744 },
34745 /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34746 {
34747 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40,
34748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34749 },
34750 /* indexws.w ${Dsp-16-u8}[sb] */
34751 {
34752 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24,
34753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34754 },
34755 /* indexws.w ${Dsp-16-u16}[sb] */
34756 {
34757 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32,
34758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34759 },
34760 /* indexws.w ${Dsp-16-s8}[fb] */
34761 {
34762 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24,
34763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34764 },
34765 /* indexws.w ${Dsp-16-s16}[fb] */
34766 {
34767 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32,
34768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34769 },
34770 /* indexws.w ${Dsp-16-u16} */
34771 {
34772 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32,
34773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34774 },
34775 /* indexws.w ${Dsp-16-u24} */
34776 {
34777 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40,
34778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34779 },
34780 /* indexws.b $Dst32RnUnprefixedQI */
34781 {
34782 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16,
34783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34784 },
34785 /* indexws.b $Dst32AnUnprefixedQI */
34786 {
34787 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16,
34788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34789 },
34790 /* indexws.b [$Dst32AnUnprefixed] */
34791 {
34792 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16,
34793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34794 },
34795 /* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34796 {
34797 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24,
34798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34799 },
34800 /* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34801 {
34802 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32,
34803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34804 },
34805 /* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34806 {
34807 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40,
34808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34809 },
34810 /* indexws.b ${Dsp-16-u8}[sb] */
34811 {
34812 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24,
34813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34814 },
34815 /* indexws.b ${Dsp-16-u16}[sb] */
34816 {
34817 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32,
34818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34819 },
34820 /* indexws.b ${Dsp-16-s8}[fb] */
34821 {
34822 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24,
34823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34824 },
34825 /* indexws.b ${Dsp-16-s16}[fb] */
34826 {
34827 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32,
34828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34829 },
34830 /* indexws.b ${Dsp-16-u16} */
34831 {
34832 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32,
34833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34834 },
34835 /* indexws.b ${Dsp-16-u24} */
34836 {
34837 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40,
34838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34839 },
34840 /* indexwd.w $Dst32RnUnprefixedHI */
34841 {
34842 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16,
34843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34844 },
34845 /* indexwd.w $Dst32AnUnprefixedHI */
34846 {
34847 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16,
34848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34849 },
34850 /* indexwd.w [$Dst32AnUnprefixed] */
34851 {
34852 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16,
34853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34854 },
34855 /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34856 {
34857 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24,
34858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34859 },
34860 /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34861 {
34862 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32,
34863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34864 },
34865 /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34866 {
34867 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40,
34868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34869 },
34870 /* indexwd.w ${Dsp-16-u8}[sb] */
34871 {
34872 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24,
34873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34874 },
34875 /* indexwd.w ${Dsp-16-u16}[sb] */
34876 {
34877 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32,
34878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34879 },
34880 /* indexwd.w ${Dsp-16-s8}[fb] */
34881 {
34882 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24,
34883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34884 },
34885 /* indexwd.w ${Dsp-16-s16}[fb] */
34886 {
34887 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32,
34888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34889 },
34890 /* indexwd.w ${Dsp-16-u16} */
34891 {
34892 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32,
34893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34894 },
34895 /* indexwd.w ${Dsp-16-u24} */
34896 {
34897 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40,
34898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34899 },
34900 /* indexwd.b $Dst32RnUnprefixedQI */
34901 {
34902 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16,
34903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34904 },
34905 /* indexwd.b $Dst32AnUnprefixedQI */
34906 {
34907 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16,
34908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34909 },
34910 /* indexwd.b [$Dst32AnUnprefixed] */
34911 {
34912 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16,
34913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34914 },
34915 /* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34916 {
34917 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24,
34918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34919 },
34920 /* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34921 {
34922 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32,
34923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34924 },
34925 /* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34926 {
34927 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40,
34928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34929 },
34930 /* indexwd.b ${Dsp-16-u8}[sb] */
34931 {
34932 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24,
34933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34934 },
34935 /* indexwd.b ${Dsp-16-u16}[sb] */
34936 {
34937 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32,
34938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34939 },
34940 /* indexwd.b ${Dsp-16-s8}[fb] */
34941 {
34942 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24,
34943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34944 },
34945 /* indexwd.b ${Dsp-16-s16}[fb] */
34946 {
34947 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32,
34948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34949 },
34950 /* indexwd.b ${Dsp-16-u16} */
34951 {
34952 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32,
34953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34954 },
34955 /* indexwd.b ${Dsp-16-u24} */
34956 {
34957 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40,
34958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34959 },
34960 /* indexw.w $Dst32RnUnprefixedHI */
34961 {
34962 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16,
34963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34964 },
34965 /* indexw.w $Dst32AnUnprefixedHI */
34966 {
34967 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16,
34968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34969 },
34970 /* indexw.w [$Dst32AnUnprefixed] */
34971 {
34972 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16,
34973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34974 },
34975 /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34976 {
34977 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24,
34978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34979 },
34980 /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34981 {
34982 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32,
34983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34984 },
34985 /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34986 {
34987 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40,
34988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34989 },
34990 /* indexw.w ${Dsp-16-u8}[sb] */
34991 {
34992 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24,
34993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34994 },
34995 /* indexw.w ${Dsp-16-u16}[sb] */
34996 {
34997 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32,
34998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34999 },
35000 /* indexw.w ${Dsp-16-s8}[fb] */
35001 {
35002 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24,
35003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35004 },
35005 /* indexw.w ${Dsp-16-s16}[fb] */
35006 {
35007 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32,
35008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35009 },
35010 /* indexw.w ${Dsp-16-u16} */
35011 {
35012 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32,
35013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35014 },
35015 /* indexw.w ${Dsp-16-u24} */
35016 {
35017 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40,
35018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35019 },
35020 /* indexw.b $Dst32RnUnprefixedQI */
35021 {
35022 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16,
35023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35024 },
35025 /* indexw.b $Dst32AnUnprefixedQI */
35026 {
35027 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16,
35028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35029 },
35030 /* indexw.b [$Dst32AnUnprefixed] */
35031 {
35032 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16,
35033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35034 },
35035 /* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35036 {
35037 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24,
35038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35039 },
35040 /* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35041 {
35042 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32,
35043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35044 },
35045 /* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35046 {
35047 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40,
35048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35049 },
35050 /* indexw.b ${Dsp-16-u8}[sb] */
35051 {
35052 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24,
35053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35054 },
35055 /* indexw.b ${Dsp-16-u16}[sb] */
35056 {
35057 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32,
35058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35059 },
35060 /* indexw.b ${Dsp-16-s8}[fb] */
35061 {
35062 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24,
35063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35064 },
35065 /* indexw.b ${Dsp-16-s16}[fb] */
35066 {
35067 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32,
35068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35069 },
35070 /* indexw.b ${Dsp-16-u16} */
35071 {
35072 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32,
35073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35074 },
35075 /* indexw.b ${Dsp-16-u24} */
35076 {
35077 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40,
35078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35079 },
35080 /* indexls.w $Dst32RnUnprefixedHI */
35081 {
35082 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16,
35083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35084 },
35085 /* indexls.w $Dst32AnUnprefixedHI */
35086 {
35087 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16,
35088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35089 },
35090 /* indexls.w [$Dst32AnUnprefixed] */
35091 {
35092 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16,
35093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35094 },
35095 /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35096 {
35097 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24,
35098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35099 },
35100 /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35101 {
35102 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32,
35103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35104 },
35105 /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35106 {
35107 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40,
35108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35109 },
35110 /* indexls.w ${Dsp-16-u8}[sb] */
35111 {
35112 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24,
35113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35114 },
35115 /* indexls.w ${Dsp-16-u16}[sb] */
35116 {
35117 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32,
35118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35119 },
35120 /* indexls.w ${Dsp-16-s8}[fb] */
35121 {
35122 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24,
35123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35124 },
35125 /* indexls.w ${Dsp-16-s16}[fb] */
35126 {
35127 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32,
35128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35129 },
35130 /* indexls.w ${Dsp-16-u16} */
35131 {
35132 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32,
35133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35134 },
35135 /* indexls.w ${Dsp-16-u24} */
35136 {
35137 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40,
35138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35139 },
35140 /* indexls.b $Dst32RnUnprefixedQI */
35141 {
35142 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16,
35143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35144 },
35145 /* indexls.b $Dst32AnUnprefixedQI */
35146 {
35147 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16,
35148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35149 },
35150 /* indexls.b [$Dst32AnUnprefixed] */
35151 {
35152 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16,
35153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35154 },
35155 /* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35156 {
35157 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24,
35158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35159 },
35160 /* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35161 {
35162 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32,
35163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35164 },
35165 /* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35166 {
35167 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40,
35168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35169 },
35170 /* indexls.b ${Dsp-16-u8}[sb] */
35171 {
35172 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24,
35173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35174 },
35175 /* indexls.b ${Dsp-16-u16}[sb] */
35176 {
35177 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32,
35178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35179 },
35180 /* indexls.b ${Dsp-16-s8}[fb] */
35181 {
35182 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24,
35183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35184 },
35185 /* indexls.b ${Dsp-16-s16}[fb] */
35186 {
35187 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32,
35188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35189 },
35190 /* indexls.b ${Dsp-16-u16} */
35191 {
35192 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32,
35193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35194 },
35195 /* indexls.b ${Dsp-16-u24} */
35196 {
35197 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40,
35198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35199 },
35200 /* indexld.w $Dst32RnUnprefixedHI */
35201 {
35202 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16,
35203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35204 },
35205 /* indexld.w $Dst32AnUnprefixedHI */
35206 {
35207 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16,
35208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35209 },
35210 /* indexld.w [$Dst32AnUnprefixed] */
35211 {
35212 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16,
35213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35214 },
35215 /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35216 {
35217 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24,
35218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35219 },
35220 /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35221 {
35222 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32,
35223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35224 },
35225 /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35226 {
35227 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40,
35228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35229 },
35230 /* indexld.w ${Dsp-16-u8}[sb] */
35231 {
35232 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24,
35233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35234 },
35235 /* indexld.w ${Dsp-16-u16}[sb] */
35236 {
35237 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32,
35238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35239 },
35240 /* indexld.w ${Dsp-16-s8}[fb] */
35241 {
35242 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24,
35243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35244 },
35245 /* indexld.w ${Dsp-16-s16}[fb] */
35246 {
35247 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32,
35248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35249 },
35250 /* indexld.w ${Dsp-16-u16} */
35251 {
35252 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32,
35253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35254 },
35255 /* indexld.w ${Dsp-16-u24} */
35256 {
35257 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40,
35258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35259 },
35260 /* indexld.b $Dst32RnUnprefixedQI */
35261 {
35262 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16,
35263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35264 },
35265 /* indexld.b $Dst32AnUnprefixedQI */
35266 {
35267 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16,
35268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35269 },
35270 /* indexld.b [$Dst32AnUnprefixed] */
35271 {
35272 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16,
35273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35274 },
35275 /* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35276 {
35277 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24,
35278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35279 },
35280 /* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35281 {
35282 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32,
35283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35284 },
35285 /* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35286 {
35287 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40,
35288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35289 },
35290 /* indexld.b ${Dsp-16-u8}[sb] */
35291 {
35292 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24,
35293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35294 },
35295 /* indexld.b ${Dsp-16-u16}[sb] */
35296 {
35297 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32,
35298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35299 },
35300 /* indexld.b ${Dsp-16-s8}[fb] */
35301 {
35302 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24,
35303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35304 },
35305 /* indexld.b ${Dsp-16-s16}[fb] */
35306 {
35307 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32,
35308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35309 },
35310 /* indexld.b ${Dsp-16-u16} */
35311 {
35312 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32,
35313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35314 },
35315 /* indexld.b ${Dsp-16-u24} */
35316 {
35317 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40,
35318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35319 },
35320 /* indexl.w $Dst32RnUnprefixedHI */
35321 {
35322 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16,
35323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35324 },
35325 /* indexl.w $Dst32AnUnprefixedHI */
35326 {
35327 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16,
35328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35329 },
35330 /* indexl.w [$Dst32AnUnprefixed] */
35331 {
35332 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16,
35333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35334 },
35335 /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35336 {
35337 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24,
35338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35339 },
35340 /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35341 {
35342 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32,
35343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35344 },
35345 /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35346 {
35347 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40,
35348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35349 },
35350 /* indexl.w ${Dsp-16-u8}[sb] */
35351 {
35352 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24,
35353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35354 },
35355 /* indexl.w ${Dsp-16-u16}[sb] */
35356 {
35357 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32,
35358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35359 },
35360 /* indexl.w ${Dsp-16-s8}[fb] */
35361 {
35362 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24,
35363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35364 },
35365 /* indexl.w ${Dsp-16-s16}[fb] */
35366 {
35367 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32,
35368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35369 },
35370 /* indexl.w ${Dsp-16-u16} */
35371 {
35372 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32,
35373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35374 },
35375 /* indexl.w ${Dsp-16-u24} */
35376 {
35377 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40,
35378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35379 },
35380 /* indexl.b $Dst32RnUnprefixedQI */
35381 {
35382 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16,
35383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35384 },
35385 /* indexl.b $Dst32AnUnprefixedQI */
35386 {
35387 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16,
35388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35389 },
35390 /* indexl.b [$Dst32AnUnprefixed] */
35391 {
35392 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16,
35393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35394 },
35395 /* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35396 {
35397 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24,
35398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35399 },
35400 /* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35401 {
35402 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32,
35403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35404 },
35405 /* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35406 {
35407 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40,
35408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35409 },
35410 /* indexl.b ${Dsp-16-u8}[sb] */
35411 {
35412 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24,
35413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35414 },
35415 /* indexl.b ${Dsp-16-u16}[sb] */
35416 {
35417 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32,
35418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35419 },
35420 /* indexl.b ${Dsp-16-s8}[fb] */
35421 {
35422 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24,
35423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35424 },
35425 /* indexl.b ${Dsp-16-s16}[fb] */
35426 {
35427 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32,
35428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35429 },
35430 /* indexl.b ${Dsp-16-u16} */
35431 {
35432 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32,
35433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35434 },
35435 /* indexl.b ${Dsp-16-u24} */
35436 {
35437 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40,
35438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35439 },
35440 /* indexbs.w $Dst32RnUnprefixedHI */
35441 {
35442 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16,
35443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35444 },
35445 /* indexbs.w $Dst32AnUnprefixedHI */
35446 {
35447 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16,
35448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35449 },
35450 /* indexbs.w [$Dst32AnUnprefixed] */
35451 {
35452 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16,
35453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35454 },
35455 /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35456 {
35457 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24,
35458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35459 },
35460 /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35461 {
35462 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32,
35463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35464 },
35465 /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35466 {
35467 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40,
35468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35469 },
35470 /* indexbs.w ${Dsp-16-u8}[sb] */
35471 {
35472 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24,
35473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35474 },
35475 /* indexbs.w ${Dsp-16-u16}[sb] */
35476 {
35477 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32,
35478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35479 },
35480 /* indexbs.w ${Dsp-16-s8}[fb] */
35481 {
35482 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24,
35483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35484 },
35485 /* indexbs.w ${Dsp-16-s16}[fb] */
35486 {
35487 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32,
35488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35489 },
35490 /* indexbs.w ${Dsp-16-u16} */
35491 {
35492 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32,
35493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35494 },
35495 /* indexbs.w ${Dsp-16-u24} */
35496 {
35497 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40,
35498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35499 },
35500 /* indexbs.b $Dst32RnUnprefixedQI */
35501 {
35502 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16,
35503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35504 },
35505 /* indexbs.b $Dst32AnUnprefixedQI */
35506 {
35507 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16,
35508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35509 },
35510 /* indexbs.b [$Dst32AnUnprefixed] */
35511 {
35512 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16,
35513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35514 },
35515 /* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35516 {
35517 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24,
35518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35519 },
35520 /* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35521 {
35522 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32,
35523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35524 },
35525 /* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35526 {
35527 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40,
35528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35529 },
35530 /* indexbs.b ${Dsp-16-u8}[sb] */
35531 {
35532 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24,
35533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35534 },
35535 /* indexbs.b ${Dsp-16-u16}[sb] */
35536 {
35537 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32,
35538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35539 },
35540 /* indexbs.b ${Dsp-16-s8}[fb] */
35541 {
35542 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24,
35543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35544 },
35545 /* indexbs.b ${Dsp-16-s16}[fb] */
35546 {
35547 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32,
35548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35549 },
35550 /* indexbs.b ${Dsp-16-u16} */
35551 {
35552 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32,
35553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35554 },
35555 /* indexbs.b ${Dsp-16-u24} */
35556 {
35557 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40,
35558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35559 },
35560 /* indexbd.w $Dst32RnUnprefixedHI */
35561 {
35562 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16,
35563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35564 },
35565 /* indexbd.w $Dst32AnUnprefixedHI */
35566 {
35567 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16,
35568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35569 },
35570 /* indexbd.w [$Dst32AnUnprefixed] */
35571 {
35572 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16,
35573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35574 },
35575 /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35576 {
35577 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24,
35578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35579 },
35580 /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35581 {
35582 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32,
35583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35584 },
35585 /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35586 {
35587 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40,
35588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35589 },
35590 /* indexbd.w ${Dsp-16-u8}[sb] */
35591 {
35592 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24,
35593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35594 },
35595 /* indexbd.w ${Dsp-16-u16}[sb] */
35596 {
35597 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32,
35598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35599 },
35600 /* indexbd.w ${Dsp-16-s8}[fb] */
35601 {
35602 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24,
35603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35604 },
35605 /* indexbd.w ${Dsp-16-s16}[fb] */
35606 {
35607 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32,
35608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35609 },
35610 /* indexbd.w ${Dsp-16-u16} */
35611 {
35612 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32,
35613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35614 },
35615 /* indexbd.w ${Dsp-16-u24} */
35616 {
35617 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40,
35618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35619 },
35620 /* indexbd.b $Dst32RnUnprefixedQI */
35621 {
35622 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16,
35623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35624 },
35625 /* indexbd.b $Dst32AnUnprefixedQI */
35626 {
35627 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16,
35628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35629 },
35630 /* indexbd.b [$Dst32AnUnprefixed] */
35631 {
35632 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16,
35633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35634 },
35635 /* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35636 {
35637 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24,
35638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35639 },
35640 /* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35641 {
35642 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32,
35643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35644 },
35645 /* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35646 {
35647 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40,
35648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35649 },
35650 /* indexbd.b ${Dsp-16-u8}[sb] */
35651 {
35652 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24,
35653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35654 },
35655 /* indexbd.b ${Dsp-16-u16}[sb] */
35656 {
35657 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32,
35658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35659 },
35660 /* indexbd.b ${Dsp-16-s8}[fb] */
35661 {
35662 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24,
35663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35664 },
35665 /* indexbd.b ${Dsp-16-s16}[fb] */
35666 {
35667 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32,
35668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35669 },
35670 /* indexbd.b ${Dsp-16-u16} */
35671 {
35672 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32,
35673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35674 },
35675 /* indexbd.b ${Dsp-16-u24} */
35676 {
35677 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40,
35678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35679 },
35680 /* indexb.w $Dst32RnUnprefixedHI */
35681 {
35682 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16,
35683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35684 },
35685 /* indexb.w $Dst32AnUnprefixedHI */
35686 {
35687 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16,
35688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35689 },
35690 /* indexb.w [$Dst32AnUnprefixed] */
35691 {
35692 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16,
35693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35694 },
35695 /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35696 {
35697 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24,
35698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35699 },
35700 /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35701 {
35702 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32,
35703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35704 },
35705 /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35706 {
35707 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40,
35708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35709 },
35710 /* indexb.w ${Dsp-16-u8}[sb] */
35711 {
35712 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24,
35713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35714 },
35715 /* indexb.w ${Dsp-16-u16}[sb] */
35716 {
35717 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32,
35718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35719 },
35720 /* indexb.w ${Dsp-16-s8}[fb] */
35721 {
35722 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24,
35723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35724 },
35725 /* indexb.w ${Dsp-16-s16}[fb] */
35726 {
35727 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32,
35728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35729 },
35730 /* indexb.w ${Dsp-16-u16} */
35731 {
35732 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32,
35733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35734 },
35735 /* indexb.w ${Dsp-16-u24} */
35736 {
35737 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40,
35738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35739 },
35740 /* indexb.b $Dst32RnUnprefixedQI */
35741 {
35742 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16,
35743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35744 },
35745 /* indexb.b $Dst32AnUnprefixedQI */
35746 {
35747 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16,
35748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35749 },
35750 /* indexb.b [$Dst32AnUnprefixed] */
35751 {
35752 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16,
35753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35754 },
35755 /* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35756 {
35757 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24,
35758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35759 },
35760 /* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35761 {
35762 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32,
35763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35764 },
35765 /* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35766 {
35767 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40,
35768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35769 },
35770 /* indexb.b ${Dsp-16-u8}[sb] */
35771 {
35772 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24,
35773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35774 },
35775 /* indexb.b ${Dsp-16-u16}[sb] */
35776 {
35777 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32,
35778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35779 },
35780 /* indexb.b ${Dsp-16-s8}[fb] */
35781 {
35782 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24,
35783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35784 },
35785 /* indexb.b ${Dsp-16-s16}[fb] */
35786 {
35787 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32,
35788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35789 },
35790 /* indexb.b ${Dsp-16-u16} */
35791 {
35792 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32,
35793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35794 },
35795 /* indexb.b ${Dsp-16-u24} */
35796 {
35797 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40,
35798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35799 },
35800 /* inc.w $Dst32RnUnprefixedHI */
35801 {
35802 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16,
35803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35804 },
35805 /* inc.w $Dst32AnUnprefixedHI */
35806 {
35807 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16,
35808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35809 },
35810 /* inc.w [$Dst32AnUnprefixed] */
35811 {
35812 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16,
35813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35814 },
35815 /* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35816 {
35817 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24,
35818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35819 },
35820 /* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35821 {
35822 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32,
35823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35824 },
35825 /* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35826 {
35827 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40,
35828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35829 },
35830 /* inc.w ${Dsp-16-u8}[sb] */
35831 {
35832 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24,
35833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35834 },
35835 /* inc.w ${Dsp-16-u16}[sb] */
35836 {
35837 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32,
35838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35839 },
35840 /* inc.w ${Dsp-16-s8}[fb] */
35841 {
35842 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24,
35843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35844 },
35845 /* inc.w ${Dsp-16-s16}[fb] */
35846 {
35847 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32,
35848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35849 },
35850 /* inc.w ${Dsp-16-u16} */
35851 {
35852 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32,
35853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35854 },
35855 /* inc.w ${Dsp-16-u24} */
35856 {
35857 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40,
35858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35859 },
35860 /* inc.b $Dst32RnUnprefixedQI */
35861 {
35862 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16,
35863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35864 },
35865 /* inc.b $Dst32AnUnprefixedQI */
35866 {
35867 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16,
35868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35869 },
35870 /* inc.b [$Dst32AnUnprefixed] */
35871 {
35872 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16,
35873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35874 },
35875 /* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35876 {
35877 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24,
35878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35879 },
35880 /* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35881 {
35882 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32,
35883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35884 },
35885 /* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35886 {
35887 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40,
35888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35889 },
35890 /* inc.b ${Dsp-16-u8}[sb] */
35891 {
35892 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24,
35893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35894 },
35895 /* inc.b ${Dsp-16-u16}[sb] */
35896 {
35897 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32,
35898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35899 },
35900 /* inc.b ${Dsp-16-s8}[fb] */
35901 {
35902 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24,
35903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35904 },
35905 /* inc.b ${Dsp-16-s16}[fb] */
35906 {
35907 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32,
35908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35909 },
35910 /* inc.b ${Dsp-16-u16} */
35911 {
35912 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32,
35913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35914 },
35915 /* inc.b ${Dsp-16-u24} */
35916 {
35917 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40,
35918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35919 },
35920 /* inc.b r0l */
35921 {
35922 M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8,
35923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35924 },
35925 /* inc.b r0h */
35926 {
35927 M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8,
35928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35929 },
35930 /* inc.b ${Dsp-8-u8}[sb] */
35931 {
35932 M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16,
35933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35934 },
35935 /* inc.b ${Dsp-8-s8}[fb] */
35936 {
35937 M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16,
35938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35939 },
35940 /* inc.b ${Dsp-8-u16} */
35941 {
35942 M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24,
35943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35944 },
35945 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
35946 {
35947 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35949 },
35950 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
35951 {
35952 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35954 },
35955 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
35956 {
35957 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35959 },
35960 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
35961 {
35962 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35964 },
35965 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
35966 {
35967 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35969 },
35970 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
35971 {
35972 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35974 },
35975 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
35976 {
35977 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
35978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35979 },
35980 /* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
35981 {
35982 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
35983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35984 },
35985 /* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
35986 {
35987 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
35988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35989 },
35990 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
35991 {
35992 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
35993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35994 },
35995 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
35996 {
35997 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
35998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35999 },
36000 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36001 {
36002 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
36003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36004 },
36005 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36006 {
36007 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36009 },
36010 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36011 {
36012 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36014 },
36015 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36016 {
36017 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36019 },
36020 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36021 {
36022 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36024 },
36025 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36026 {
36027 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36029 },
36030 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36031 {
36032 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36034 },
36035 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36036 {
36037 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36039 },
36040 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36041 {
36042 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36044 },
36045 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36046 {
36047 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36049 },
36050 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36051 {
36052 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36054 },
36055 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36056 {
36057 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36059 },
36060 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36061 {
36062 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36064 },
36065 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36066 {
36067 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36069 },
36070 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36071 {
36072 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36074 },
36075 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36076 {
36077 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36079 },
36080 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36081 {
36082 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36084 },
36085 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36086 {
36087 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36089 },
36090 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36091 {
36092 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36094 },
36095 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36096 {
36097 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36099 },
36100 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36101 {
36102 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36104 },
36105 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36106 {
36107 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36109 },
36110 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36111 {
36112 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36114 },
36115 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36116 {
36117 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36119 },
36120 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36121 {
36122 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36124 },
36125 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36126 {
36127 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36129 },
36130 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
36131 {
36132 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36134 },
36135 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
36136 {
36137 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36139 },
36140 /* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
36141 {
36142 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36144 },
36145 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36146 {
36147 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36149 },
36150 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
36151 {
36152 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36154 },
36155 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
36156 {
36157 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36159 },
36160 /* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
36161 {
36162 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36164 },
36165 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36166 {
36167 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36169 },
36170 /* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
36171 {
36172 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36174 },
36175 /* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
36176 {
36177 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36179 },
36180 /* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
36181 {
36182 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36184 },
36185 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36186 {
36187 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36189 },
36190 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36191 {
36192 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36194 },
36195 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36196 {
36197 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36199 },
36200 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
36201 {
36202 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36204 },
36205 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36206 {
36207 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36209 },
36210 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36211 {
36212 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36214 },
36215 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36216 {
36217 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36219 },
36220 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
36221 {
36222 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36224 },
36225 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36226 {
36227 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36229 },
36230 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36231 {
36232 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36234 },
36235 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36236 {
36237 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36239 },
36240 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
36241 {
36242 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36244 },
36245 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
36246 {
36247 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36249 },
36250 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
36251 {
36252 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36254 },
36255 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
36256 {
36257 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36259 },
36260 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
36261 {
36262 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36264 },
36265 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
36266 {
36267 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36269 },
36270 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
36271 {
36272 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36274 },
36275 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
36276 {
36277 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36279 },
36280 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
36281 {
36282 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36284 },
36285 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
36286 {
36287 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36289 },
36290 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
36291 {
36292 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36294 },
36295 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
36296 {
36297 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36299 },
36300 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
36301 {
36302 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36304 },
36305 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
36306 {
36307 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36309 },
36310 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
36311 {
36312 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36314 },
36315 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
36316 {
36317 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36319 },
36320 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
36321 {
36322 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36324 },
36325 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
36326 {
36327 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36329 },
36330 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
36331 {
36332 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36334 },
36335 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
36336 {
36337 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36339 },
36340 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
36341 {
36342 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36344 },
36345 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
36346 {
36347 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36349 },
36350 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
36351 {
36352 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36354 },
36355 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
36356 {
36357 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36359 },
36360 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
36361 {
36362 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36364 },
36365 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36366 {
36367 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
36368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36369 },
36370 /* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
36371 {
36372 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
36373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36374 },
36375 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36376 {
36377 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36379 },
36380 /* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
36381 {
36382 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36384 },
36385 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36386 {
36387 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36389 },
36390 /* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
36391 {
36392 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36394 },
36395 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
36396 {
36397 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36399 },
36400 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
36401 {
36402 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36404 },
36405 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
36406 {
36407 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36409 },
36410 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
36411 {
36412 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36414 },
36415 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
36416 {
36417 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36419 },
36420 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
36421 {
36422 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36424 },
36425 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
36426 {
36427 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36429 },
36430 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
36431 {
36432 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36434 },
36435 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
36436 {
36437 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36439 },
36440 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
36441 {
36442 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36444 },
36445 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
36446 {
36447 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36449 },
36450 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
36451 {
36452 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36454 },
36455 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
36456 {
36457 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36459 },
36460 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
36461 {
36462 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36464 },
36465 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
36466 {
36467 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36469 },
36470 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
36471 {
36472 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36474 },
36475 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
36476 {
36477 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36479 },
36480 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
36481 {
36482 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36484 },
36485 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
36486 {
36487 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36489 },
36490 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
36491 {
36492 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36494 },
36495 /* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36496 {
36497 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36499 },
36500 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
36501 {
36502 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36504 },
36505 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
36506 {
36507 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36509 },
36510 /* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36511 {
36512 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36514 },
36515 /* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
36516 {
36517 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36519 },
36520 /* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
36521 {
36522 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36524 },
36525 /* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36526 {
36527 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36529 },
36530 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36531 {
36532 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36534 },
36535 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36536 {
36537 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36539 },
36540 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
36541 {
36542 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36544 },
36545 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36546 {
36547 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36549 },
36550 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36551 {
36552 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36554 },
36555 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
36556 {
36557 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36559 },
36560 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36561 {
36562 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36564 },
36565 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36566 {
36567 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36569 },
36570 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
36571 {
36572 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36574 },
36575 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
36576 {
36577 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36579 },
36580 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
36581 {
36582 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36584 },
36585 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
36586 {
36587 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36589 },
36590 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
36591 {
36592 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36594 },
36595 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
36596 {
36597 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36599 },
36600 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
36601 {
36602 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36604 },
36605 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
36606 {
36607 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36609 },
36610 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
36611 {
36612 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36614 },
36615 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
36616 {
36617 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36619 },
36620 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
36621 {
36622 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36624 },
36625 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
36626 {
36627 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36629 },
36630 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
36631 {
36632 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36634 },
36635 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
36636 {
36637 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36639 },
36640 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
36641 {
36642 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36644 },
36645 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
36646 {
36647 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36649 },
36650 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
36651 {
36652 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36654 },
36655 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
36656 {
36657 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36659 },
36660 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
36661 {
36662 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36664 },
36665 /* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
36666 {
36667 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32,
36668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36669 },
36670 /* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
36671 {
36672 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32,
36673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36674 },
36675 /* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
36676 {
36677 M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40,
36678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36679 },
36680 /* sub.w${S} #${Imm-8-HI},r0 */
36681 {
36682 M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24,
36683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36684 },
36685 /* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
36686 {
36687 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24,
36688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36689 },
36690 /* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
36691 {
36692 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24,
36693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36694 },
36695 /* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
36696 {
36697 M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32,
36698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36699 },
36700 /* sub.b${S} #${Imm-8-QI},r0l */
36701 {
36702 M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16,
36703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36704 },
36705 /* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
36706 {
36707 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48,
36708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36709 },
36710 /* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
36711 {
36712 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48,
36713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36714 },
36715 /* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
36716 {
36717 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48,
36718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36719 },
36720 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
36721 {
36722 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56,
36723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36724 },
36725 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
36726 {
36727 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56,
36728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36729 },
36730 /* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
36731 {
36732 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56,
36733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36734 },
36735 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
36736 {
36737 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64,
36738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36739 },
36740 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
36741 {
36742 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64,
36743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36744 },
36745 /* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
36746 {
36747 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64,
36748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36749 },
36750 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
36751 {
36752 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64,
36753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36754 },
36755 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
36756 {
36757 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72,
36758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36759 },
36760 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
36761 {
36762 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72,
36763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36764 },
36765 /* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36766 {
36767 M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8,
36768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36769 },
36770 /* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36771 {
36772 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16,
36773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36774 },
36775 /* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36776 {
36777 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16,
36778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36779 },
36780 /* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36781 {
36782 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24,
36783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36784 },
36785 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36786 {
36787 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36789 },
36790 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
36791 {
36792 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36794 },
36795 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
36796 {
36797 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36799 },
36800 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36801 {
36802 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36804 },
36805 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
36806 {
36807 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36809 },
36810 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
36811 {
36812 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36814 },
36815 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36816 {
36817 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36819 },
36820 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36821 {
36822 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36824 },
36825 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36826 {
36827 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36829 },
36830 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36831 {
36832 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36834 },
36835 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36836 {
36837 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36839 },
36840 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36841 {
36842 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36844 },
36845 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36846 {
36847 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36849 },
36850 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36851 {
36852 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36854 },
36855 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36856 {
36857 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36859 },
36860 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36861 {
36862 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36864 },
36865 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36866 {
36867 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36869 },
36870 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36871 {
36872 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36874 },
36875 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36876 {
36877 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36879 },
36880 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36881 {
36882 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36884 },
36885 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36886 {
36887 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36889 },
36890 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36891 {
36892 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36894 },
36895 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36896 {
36897 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36899 },
36900 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36901 {
36902 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36904 },
36905 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36906 {
36907 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36909 },
36910 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36911 {
36912 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36914 },
36915 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36916 {
36917 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36919 },
36920 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36921 {
36922 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36924 },
36925 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36926 {
36927 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36929 },
36930 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36931 {
36932 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36934 },
36935 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36936 {
36937 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36939 },
36940 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36941 {
36942 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36944 },
36945 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36946 {
36947 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36949 },
36950 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36951 {
36952 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36954 },
36955 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36956 {
36957 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36959 },
36960 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36961 {
36962 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36964 },
36965 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36966 {
36967 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36969 },
36970 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
36971 {
36972 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36974 },
36975 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
36976 {
36977 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36979 },
36980 /* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
36981 {
36982 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36984 },
36985 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36986 {
36987 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
36988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36989 },
36990 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
36991 {
36992 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
36993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36994 },
36995 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
36996 {
36997 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
36998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36999 },
37000 /* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
37001 {
37002 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37004 },
37005 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37006 {
37007 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37009 },
37010 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37011 {
37012 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37014 },
37015 /* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37016 {
37017 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37019 },
37020 /* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37021 {
37022 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37024 },
37025 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37026 {
37027 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37029 },
37030 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37031 {
37032 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37034 },
37035 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37036 {
37037 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37039 },
37040 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37041 {
37042 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37044 },
37045 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37046 {
37047 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37049 },
37050 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37051 {
37052 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37054 },
37055 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37056 {
37057 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37059 },
37060 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37061 {
37062 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37064 },
37065 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37066 {
37067 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37069 },
37070 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37071 {
37072 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37074 },
37075 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37076 {
37077 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37079 },
37080 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37081 {
37082 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37084 },
37085 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37086 {
37087 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37089 },
37090 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37091 {
37092 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37094 },
37095 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37096 {
37097 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37099 },
37100 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37101 {
37102 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37104 },
37105 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37106 {
37107 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37109 },
37110 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37111 {
37112 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37114 },
37115 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37116 {
37117 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37119 },
37120 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37121 {
37122 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37124 },
37125 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37126 {
37127 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37129 },
37130 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37131 {
37132 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37134 },
37135 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37136 {
37137 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37139 },
37140 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37141 {
37142 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37144 },
37145 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37146 {
37147 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37149 },
37150 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37151 {
37152 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37154 },
37155 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37156 {
37157 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37159 },
37160 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37161 {
37162 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37164 },
37165 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37166 {
37167 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37169 },
37170 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37171 {
37172 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37174 },
37175 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37176 {
37177 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37179 },
37180 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
37181 {
37182 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37184 },
37185 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37186 {
37187 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37189 },
37190 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37191 {
37192 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37194 },
37195 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37196 {
37197 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37199 },
37200 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
37201 {
37202 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37204 },
37205 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37206 {
37207 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
37208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37209 },
37210 /* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
37211 {
37212 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
37213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37214 },
37215 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37216 {
37217 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
37218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37219 },
37220 /* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
37221 {
37222 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
37223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37224 },
37225 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37226 {
37227 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
37228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37229 },
37230 /* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37231 {
37232 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
37233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37234 },
37235 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37236 {
37237 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
37238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37239 },
37240 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37241 {
37242 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
37243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37244 },
37245 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37246 {
37247 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
37248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37249 },
37250 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37251 {
37252 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
37253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37254 },
37255 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37256 {
37257 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
37258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37259 },
37260 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37261 {
37262 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
37263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37264 },
37265 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37266 {
37267 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
37268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37269 },
37270 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37271 {
37272 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
37273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37274 },
37275 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37276 {
37277 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
37278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37279 },
37280 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37281 {
37282 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
37283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37284 },
37285 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37286 {
37287 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
37288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37289 },
37290 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37291 {
37292 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
37293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37294 },
37295 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37296 {
37297 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
37298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37299 },
37300 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37301 {
37302 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
37303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37304 },
37305 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37306 {
37307 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
37308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37309 },
37310 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
37311 {
37312 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
37313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37314 },
37315 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37316 {
37317 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
37318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37319 },
37320 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
37321 {
37322 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
37323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37324 },
37325 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
37326 {
37327 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37329 },
37330 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
37331 {
37332 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37334 },
37335 /* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37336 {
37337 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37339 },
37340 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
37341 {
37342 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37344 },
37345 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
37346 {
37347 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37349 },
37350 /* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37351 {
37352 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37354 },
37355 /* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
37356 {
37357 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37359 },
37360 /* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
37361 {
37362 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37364 },
37365 /* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37366 {
37367 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37369 },
37370 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37371 {
37372 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37374 },
37375 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37376 {
37377 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37379 },
37380 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37381 {
37382 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37384 },
37385 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37386 {
37387 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37389 },
37390 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37391 {
37392 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37394 },
37395 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37396 {
37397 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37399 },
37400 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37401 {
37402 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37404 },
37405 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37406 {
37407 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37409 },
37410 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37411 {
37412 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37414 },
37415 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
37416 {
37417 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37419 },
37420 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
37421 {
37422 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37424 },
37425 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37426 {
37427 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37429 },
37430 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
37431 {
37432 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37434 },
37435 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
37436 {
37437 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37439 },
37440 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37441 {
37442 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37444 },
37445 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
37446 {
37447 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37449 },
37450 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
37451 {
37452 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37454 },
37455 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37456 {
37457 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37459 },
37460 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
37461 {
37462 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37464 },
37465 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
37466 {
37467 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37469 },
37470 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37471 {
37472 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37474 },
37475 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
37476 {
37477 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37479 },
37480 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
37481 {
37482 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37484 },
37485 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37486 {
37487 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37489 },
37490 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
37491 {
37492 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37494 },
37495 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
37496 {
37497 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37499 },
37500 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37501 {
37502 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37504 },
37505 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37506 {
37507 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37509 },
37510 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
37511 {
37512 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37514 },
37515 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
37516 {
37517 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37519 },
37520 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37521 {
37522 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37524 },
37525 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
37526 {
37527 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37529 },
37530 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
37531 {
37532 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37534 },
37535 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37536 {
37537 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37539 },
37540 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37541 {
37542 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37544 },
37545 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37546 {
37547 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37549 },
37550 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37551 {
37552 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37554 },
37555 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37556 {
37557 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37559 },
37560 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37561 {
37562 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37564 },
37565 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37566 {
37567 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37569 },
37570 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37571 {
37572 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37574 },
37575 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37576 {
37577 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37579 },
37580 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37581 {
37582 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37584 },
37585 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37586 {
37587 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37589 },
37590 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37591 {
37592 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37594 },
37595 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37596 {
37597 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37599 },
37600 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37601 {
37602 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37604 },
37605 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37606 {
37607 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37609 },
37610 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37611 {
37612 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37614 },
37615 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37616 {
37617 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37619 },
37620 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37621 {
37622 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37624 },
37625 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37626 {
37627 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37629 },
37630 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37631 {
37632 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37634 },
37635 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37636 {
37637 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37639 },
37640 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37641 {
37642 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37644 },
37645 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37646 {
37647 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37649 },
37650 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37651 {
37652 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37654 },
37655 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37656 {
37657 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37659 },
37660 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37661 {
37662 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37664 },
37665 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37666 {
37667 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37669 },
37670 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37671 {
37672 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37674 },
37675 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37676 {
37677 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37679 },
37680 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37681 {
37682 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37684 },
37685 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37686 {
37687 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37689 },
37690 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
37691 {
37692 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37694 },
37695 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
37696 {
37697 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37699 },
37700 /* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
37701 {
37702 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37704 },
37705 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37706 {
37707 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37709 },
37710 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
37711 {
37712 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37714 },
37715 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
37716 {
37717 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37719 },
37720 /* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
37721 {
37722 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37724 },
37725 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37726 {
37727 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37729 },
37730 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37731 {
37732 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37734 },
37735 /* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37736 {
37737 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37739 },
37740 /* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37741 {
37742 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37744 },
37745 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37746 {
37747 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37749 },
37750 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37751 {
37752 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37754 },
37755 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37756 {
37757 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37759 },
37760 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37761 {
37762 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37764 },
37765 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37766 {
37767 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37769 },
37770 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37771 {
37772 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37774 },
37775 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37776 {
37777 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37779 },
37780 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37781 {
37782 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37784 },
37785 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37786 {
37787 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37789 },
37790 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37791 {
37792 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37794 },
37795 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37796 {
37797 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37799 },
37800 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37801 {
37802 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37804 },
37805 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37806 {
37807 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37809 },
37810 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37811 {
37812 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37814 },
37815 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37816 {
37817 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37819 },
37820 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37821 {
37822 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37824 },
37825 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37826 {
37827 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37829 },
37830 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37831 {
37832 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37834 },
37835 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37836 {
37837 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37839 },
37840 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37841 {
37842 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37844 },
37845 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37846 {
37847 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37849 },
37850 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37851 {
37852 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37854 },
37855 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37856 {
37857 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37859 },
37860 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37861 {
37862 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37864 },
37865 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37866 {
37867 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37869 },
37870 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37871 {
37872 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37874 },
37875 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37876 {
37877 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37879 },
37880 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37881 {
37882 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37884 },
37885 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37886 {
37887 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37889 },
37890 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37891 {
37892 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37894 },
37895 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37896 {
37897 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37899 },
37900 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
37901 {
37902 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37904 },
37905 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37906 {
37907 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37909 },
37910 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37911 {
37912 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37914 },
37915 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37916 {
37917 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37919 },
37920 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
37921 {
37922 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37924 },
37925 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37926 {
37927 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37929 },
37930 /* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
37931 {
37932 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37934 },
37935 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37936 {
37937 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37939 },
37940 /* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
37941 {
37942 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37944 },
37945 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37946 {
37947 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37949 },
37950 /* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37951 {
37952 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37954 },
37955 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37956 {
37957 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37959 },
37960 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37961 {
37962 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37964 },
37965 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37966 {
37967 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
37968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37969 },
37970 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37971 {
37972 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
37973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37974 },
37975 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37976 {
37977 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
37978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37979 },
37980 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37981 {
37982 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
37983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37984 },
37985 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37986 {
37987 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
37988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37989 },
37990 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37991 {
37992 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
37993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37994 },
37995 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37996 {
37997 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
37998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37999 },
38000 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
38001 {
38002 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
38003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38004 },
38005 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
38006 {
38007 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
38008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38009 },
38010 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
38011 {
38012 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
38013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38014 },
38015 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
38016 {
38017 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
38018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38019 },
38020 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
38021 {
38022 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
38023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38024 },
38025 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
38026 {
38027 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
38028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38029 },
38030 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
38031 {
38032 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
38033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38034 },
38035 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
38036 {
38037 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
38038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38039 },
38040 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
38041 {
38042 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
38043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38044 },
38045 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
38046 {
38047 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38049 },
38050 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
38051 {
38052 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38054 },
38055 /* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38056 {
38057 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38059 },
38060 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
38061 {
38062 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38064 },
38065 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
38066 {
38067 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38069 },
38070 /* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38071 {
38072 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38074 },
38075 /* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
38076 {
38077 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38079 },
38080 /* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
38081 {
38082 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38084 },
38085 /* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38086 {
38087 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38089 },
38090 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38091 {
38092 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38094 },
38095 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38096 {
38097 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38099 },
38100 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
38101 {
38102 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38104 },
38105 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38106 {
38107 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38109 },
38110 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38111 {
38112 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38114 },
38115 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
38116 {
38117 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38119 },
38120 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38121 {
38122 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38124 },
38125 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38126 {
38127 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38129 },
38130 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38131 {
38132 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38134 },
38135 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
38136 {
38137 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38139 },
38140 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
38141 {
38142 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38144 },
38145 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38146 {
38147 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38149 },
38150 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
38151 {
38152 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38154 },
38155 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
38156 {
38157 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38159 },
38160 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38161 {
38162 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38164 },
38165 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
38166 {
38167 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38169 },
38170 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
38171 {
38172 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38174 },
38175 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38176 {
38177 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38179 },
38180 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
38181 {
38182 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38184 },
38185 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
38186 {
38187 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38189 },
38190 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38191 {
38192 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38194 },
38195 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
38196 {
38197 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38199 },
38200 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
38201 {
38202 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38204 },
38205 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38206 {
38207 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38209 },
38210 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
38211 {
38212 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38214 },
38215 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
38216 {
38217 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38219 },
38220 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38221 {
38222 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38224 },
38225 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
38226 {
38227 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38229 },
38230 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
38231 {
38232 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38234 },
38235 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
38236 {
38237 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38239 },
38240 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
38241 {
38242 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38244 },
38245 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
38246 {
38247 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38249 },
38250 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
38251 {
38252 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38254 },
38255 /* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38256 {
38257 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38259 },
38260 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38261 {
38262 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38264 },
38265 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38266 {
38267 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38269 },
38270 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38271 {
38272 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38274 },
38275 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38276 {
38277 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38279 },
38280 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38281 {
38282 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38284 },
38285 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38286 {
38287 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38289 },
38290 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38291 {
38292 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38294 },
38295 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38296 {
38297 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38299 },
38300 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38301 {
38302 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38304 },
38305 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38306 {
38307 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38309 },
38310 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38311 {
38312 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38314 },
38315 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38316 {
38317 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38319 },
38320 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38321 {
38322 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38324 },
38325 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38326 {
38327 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38329 },
38330 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38331 {
38332 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38334 },
38335 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38336 {
38337 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38339 },
38340 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38341 {
38342 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38344 },
38345 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38346 {
38347 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38349 },
38350 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38351 {
38352 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38354 },
38355 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38356 {
38357 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38359 },
38360 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
38361 {
38362 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
38363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38364 },
38365 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
38366 {
38367 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
38368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38369 },
38370 /* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
38371 {
38372 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32,
38373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38374 },
38375 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
38376 {
38377 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38379 },
38380 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
38381 {
38382 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38384 },
38385 /* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
38386 {
38387 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32,
38388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38389 },
38390 /* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38391 {
38392 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38394 },
38395 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38396 {
38397 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38399 },
38400 /* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
38401 {
38402 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32,
38403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38404 },
38405 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38406 {
38407 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38409 },
38410 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38411 {
38412 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38414 },
38415 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38416 {
38417 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38419 },
38420 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38421 {
38422 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38424 },
38425 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38426 {
38427 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38429 },
38430 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38431 {
38432 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38434 },
38435 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38436 {
38437 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38439 },
38440 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38441 {
38442 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38444 },
38445 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38446 {
38447 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38449 },
38450 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38451 {
38452 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38454 },
38455 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38456 {
38457 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38459 },
38460 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38461 {
38462 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38464 },
38465 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38466 {
38467 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38469 },
38470 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38471 {
38472 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38474 },
38475 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38476 {
38477 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38479 },
38480 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38481 {
38482 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38484 },
38485 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38486 {
38487 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38489 },
38490 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
38491 {
38492 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38494 },
38495 /* sub.w${G} $Src16RnHI,$Dst16RnHI */
38496 {
38497 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38499 },
38500 /* sub.w${G} $Src16AnHI,$Dst16RnHI */
38501 {
38502 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38504 },
38505 /* sub.w${G} [$Src16An],$Dst16RnHI */
38506 {
38507 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16,
38508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38509 },
38510 /* sub.w${G} $Src16RnHI,$Dst16AnHI */
38511 {
38512 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38514 },
38515 /* sub.w${G} $Src16AnHI,$Dst16AnHI */
38516 {
38517 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38519 },
38520 /* sub.w${G} [$Src16An],$Dst16AnHI */
38521 {
38522 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16,
38523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38524 },
38525 /* sub.w${G} $Src16RnHI,[$Dst16An] */
38526 {
38527 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38529 },
38530 /* sub.w${G} $Src16AnHI,[$Dst16An] */
38531 {
38532 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38534 },
38535 /* sub.w${G} [$Src16An],[$Dst16An] */
38536 {
38537 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16,
38538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38539 },
38540 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
38541 {
38542 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38544 },
38545 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
38546 {
38547 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38549 },
38550 /* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38551 {
38552 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38554 },
38555 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
38556 {
38557 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38559 },
38560 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
38561 {
38562 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38564 },
38565 /* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38566 {
38567 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38569 },
38570 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
38571 {
38572 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38574 },
38575 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
38576 {
38577 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38579 },
38580 /* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
38581 {
38582 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38584 },
38585 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
38586 {
38587 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38589 },
38590 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
38591 {
38592 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38594 },
38595 /* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
38596 {
38597 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38599 },
38600 /* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
38601 {
38602 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38604 },
38605 /* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
38606 {
38607 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38609 },
38610 /* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
38611 {
38612 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38614 },
38615 /* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
38616 {
38617 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38619 },
38620 /* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
38621 {
38622 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38624 },
38625 /* sub.w${G} [$Src16An],${Dsp-16-u16} */
38626 {
38627 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38629 },
38630 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
38631 {
38632 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38634 },
38635 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
38636 {
38637 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38639 },
38640 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
38641 {
38642 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38644 },
38645 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
38646 {
38647 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38649 },
38650 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
38651 {
38652 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38654 },
38655 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
38656 {
38657 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38659 },
38660 /* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38661 {
38662 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38664 },
38665 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38666 {
38667 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38669 },
38670 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38671 {
38672 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38674 },
38675 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38676 {
38677 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38679 },
38680 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38681 {
38682 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38684 },
38685 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38686 {
38687 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38689 },
38690 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38691 {
38692 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38694 },
38695 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38696 {
38697 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38699 },
38700 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38701 {
38702 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38704 },
38705 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38706 {
38707 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38709 },
38710 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38711 {
38712 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38714 },
38715 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38716 {
38717 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38719 },
38720 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38721 {
38722 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38724 },
38725 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38726 {
38727 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38729 },
38730 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38731 {
38732 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38734 },
38735 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38736 {
38737 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38739 },
38740 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38741 {
38742 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38744 },
38745 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38746 {
38747 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38749 },
38750 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38751 {
38752 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38754 },
38755 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38756 {
38757 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38759 },
38760 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38761 {
38762 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38764 },
38765 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
38766 {
38767 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38769 },
38770 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
38771 {
38772 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38774 },
38775 /* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
38776 {
38777 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32,
38778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38779 },
38780 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
38781 {
38782 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38784 },
38785 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
38786 {
38787 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38789 },
38790 /* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
38791 {
38792 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32,
38793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38794 },
38795 /* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38796 {
38797 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38799 },
38800 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38801 {
38802 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38804 },
38805 /* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
38806 {
38807 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32,
38808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38809 },
38810 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38811 {
38812 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38814 },
38815 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38816 {
38817 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38819 },
38820 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38821 {
38822 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38824 },
38825 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38826 {
38827 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38829 },
38830 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38831 {
38832 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38834 },
38835 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38836 {
38837 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38839 },
38840 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38841 {
38842 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38844 },
38845 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38846 {
38847 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38849 },
38850 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38851 {
38852 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38854 },
38855 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38856 {
38857 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38859 },
38860 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38861 {
38862 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38864 },
38865 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38866 {
38867 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38869 },
38870 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38871 {
38872 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38874 },
38875 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38876 {
38877 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38879 },
38880 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38881 {
38882 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38884 },
38885 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38886 {
38887 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38889 },
38890 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38891 {
38892 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38894 },
38895 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38896 {
38897 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38899 },
38900 /* sub.b${G} $Src16RnQI,$Dst16RnQI */
38901 {
38902 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38904 },
38905 /* sub.b${G} $Src16AnQI,$Dst16RnQI */
38906 {
38907 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38909 },
38910 /* sub.b${G} [$Src16An],$Dst16RnQI */
38911 {
38912 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16,
38913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38914 },
38915 /* sub.b${G} $Src16RnQI,$Dst16AnQI */
38916 {
38917 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38919 },
38920 /* sub.b${G} $Src16AnQI,$Dst16AnQI */
38921 {
38922 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38924 },
38925 /* sub.b${G} [$Src16An],$Dst16AnQI */
38926 {
38927 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16,
38928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38929 },
38930 /* sub.b${G} $Src16RnQI,[$Dst16An] */
38931 {
38932 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38934 },
38935 /* sub.b${G} $Src16AnQI,[$Dst16An] */
38936 {
38937 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38939 },
38940 /* sub.b${G} [$Src16An],[$Dst16An] */
38941 {
38942 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16,
38943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38944 },
38945 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
38946 {
38947 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38949 },
38950 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
38951 {
38952 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38954 },
38955 /* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38956 {
38957 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38959 },
38960 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
38961 {
38962 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38964 },
38965 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
38966 {
38967 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38969 },
38970 /* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38971 {
38972 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38974 },
38975 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
38976 {
38977 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
38978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38979 },
38980 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
38981 {
38982 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
38983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38984 },
38985 /* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
38986 {
38987 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
38988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38989 },
38990 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
38991 {
38992 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
38993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38994 },
38995 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
38996 {
38997 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
38998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38999 },
39000 /* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
39001 {
39002 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
39003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39004 },
39005 /* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
39006 {
39007 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39009 },
39010 /* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
39011 {
39012 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39014 },
39015 /* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
39016 {
39017 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39019 },
39020 /* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
39021 {
39022 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39024 },
39025 /* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
39026 {
39027 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39029 },
39030 /* sub.b${G} [$Src16An],${Dsp-16-u16} */
39031 {
39032 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39034 },
39035 /* sub.b${S} #${Imm-8-QI},r0l */
39036 {
39037 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16,
39038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39039 },
39040 /* sub.b${S} #${Imm-8-QI},r0h */
39041 {
39042 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16,
39043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39044 },
39045 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
39046 {
39047 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24,
39048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39049 },
39050 /* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
39051 {
39052 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24,
39053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39054 },
39055 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
39056 {
39057 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32,
39058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39059 },
39060 /* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
39061 {
39062 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
39063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39064 },
39065 /* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
39066 {
39067 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
39068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39069 },
39070 /* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
39071 {
39072 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
39073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39074 },
39075 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39076 {
39077 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40,
39078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39079 },
39080 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39081 {
39082 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40,
39083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39084 },
39085 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39086 {
39087 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40,
39088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39089 },
39090 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39091 {
39092 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48,
39093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39094 },
39095 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39096 {
39097 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48,
39098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39099 },
39100 /* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
39101 {
39102 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48,
39103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39104 },
39105 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39106 {
39107 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48,
39108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39109 },
39110 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39111 {
39112 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56,
39113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39114 },
39115 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
39116 {
39117 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56,
39118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39119 },
39120 /* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
39121 {
39122 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
39123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39124 },
39125 /* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
39126 {
39127 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
39128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39129 },
39130 /* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
39131 {
39132 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
39133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39134 },
39135 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39136 {
39137 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32,
39138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39139 },
39140 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39141 {
39142 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32,
39143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39144 },
39145 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39146 {
39147 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32,
39148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39149 },
39150 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39151 {
39152 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40,
39153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39154 },
39155 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39156 {
39157 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40,
39158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39159 },
39160 /* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
39161 {
39162 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40,
39163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39164 },
39165 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39166 {
39167 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40,
39168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39169 },
39170 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39171 {
39172 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48,
39173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39174 },
39175 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
39176 {
39177 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48,
39178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39179 },
39180 /* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
39181 {
39182 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32,
39183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39184 },
39185 /* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
39186 {
39187 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32,
39188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39189 },
39190 /* sub.w${G} #${Imm-16-HI},[$Dst16An] */
39191 {
39192 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32,
39193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39194 },
39195 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
39196 {
39197 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40,
39198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39199 },
39200 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39201 {
39202 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40,
39203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39204 },
39205 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39206 {
39207 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40,
39208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39209 },
39210 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
39211 {
39212 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48,
39213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39214 },
39215 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39216 {
39217 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48,
39218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39219 },
39220 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39221 {
39222 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48,
39223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39224 },
39225 /* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
39226 {
39227 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24,
39228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39229 },
39230 /* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
39231 {
39232 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24,
39233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39234 },
39235 /* sub.b${G} #${Imm-16-QI},[$Dst16An] */
39236 {
39237 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24,
39238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39239 },
39240 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
39241 {
39242 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32,
39243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39244 },
39245 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39246 {
39247 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32,
39248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39249 },
39250 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39251 {
39252 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32,
39253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39254 },
39255 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
39256 {
39257 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40,
39258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39259 },
39260 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39261 {
39262 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40,
39263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39264 },
39265 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39266 {
39267 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40,
39268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39269 },
39270 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39271 {
39272 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39274 },
39275 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
39276 {
39277 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39279 },
39280 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
39281 {
39282 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39284 },
39285 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39286 {
39287 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39289 },
39290 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
39291 {
39292 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39294 },
39295 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
39296 {
39297 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39299 },
39300 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39301 {
39302 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39304 },
39305 /* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
39306 {
39307 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39309 },
39310 /* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
39311 {
39312 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39314 },
39315 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
39316 {
39317 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39319 },
39320 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39321 {
39322 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39324 },
39325 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39326 {
39327 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39329 },
39330 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
39331 {
39332 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39334 },
39335 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39336 {
39337 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39339 },
39340 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39341 {
39342 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39344 },
39345 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
39346 {
39347 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39349 },
39350 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39351 {
39352 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39354 },
39355 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39356 {
39357 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39359 },
39360 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
39361 {
39362 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39364 },
39365 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
39366 {
39367 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39369 },
39370 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
39371 {
39372 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39374 },
39375 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
39376 {
39377 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39379 },
39380 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
39381 {
39382 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39384 },
39385 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
39386 {
39387 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39389 },
39390 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
39391 {
39392 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39394 },
39395 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
39396 {
39397 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39399 },
39400 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
39401 {
39402 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39404 },
39405 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
39406 {
39407 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39409 },
39410 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
39411 {
39412 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39414 },
39415 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
39416 {
39417 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39419 },
39420 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
39421 {
39422 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39424 },
39425 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
39426 {
39427 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39429 },
39430 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
39431 {
39432 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39434 },
39435 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
39436 {
39437 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39439 },
39440 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
39441 {
39442 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39444 },
39445 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
39446 {
39447 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39449 },
39450 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39451 {
39452 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39454 },
39455 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
39456 {
39457 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39459 },
39460 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
39461 {
39462 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39464 },
39465 /* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
39466 {
39467 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39469 },
39470 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39471 {
39472 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39474 },
39475 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
39476 {
39477 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39479 },
39480 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
39481 {
39482 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39484 },
39485 /* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
39486 {
39487 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39489 },
39490 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39491 {
39492 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39494 },
39495 /* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
39496 {
39497 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39499 },
39500 /* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
39501 {
39502 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39504 },
39505 /* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
39506 {
39507 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39509 },
39510 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
39511 {
39512 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39514 },
39515 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39516 {
39517 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39519 },
39520 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39521 {
39522 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39524 },
39525 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
39526 {
39527 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39529 },
39530 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
39531 {
39532 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39534 },
39535 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39536 {
39537 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39539 },
39540 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39541 {
39542 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39544 },
39545 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
39546 {
39547 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39549 },
39550 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
39551 {
39552 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39554 },
39555 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39556 {
39557 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39559 },
39560 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39561 {
39562 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39564 },
39565 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
39566 {
39567 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39569 },
39570 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
39571 {
39572 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39574 },
39575 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
39576 {
39577 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39579 },
39580 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
39581 {
39582 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39584 },
39585 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
39586 {
39587 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39589 },
39590 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
39591 {
39592 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39594 },
39595 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
39596 {
39597 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39599 },
39600 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
39601 {
39602 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39604 },
39605 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
39606 {
39607 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39609 },
39610 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
39611 {
39612 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39614 },
39615 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
39616 {
39617 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39619 },
39620 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
39621 {
39622 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39624 },
39625 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
39626 {
39627 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39629 },
39630 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
39631 {
39632 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39634 },
39635 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
39636 {
39637 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39639 },
39640 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
39641 {
39642 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39644 },
39645 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
39646 {
39647 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39649 },
39650 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
39651 {
39652 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39654 },
39655 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
39656 {
39657 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39659 },
39660 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
39661 {
39662 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39664 },
39665 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
39666 {
39667 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39669 },
39670 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
39671 {
39672 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39674 },
39675 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
39676 {
39677 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39679 },
39680 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
39681 {
39682 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39684 },
39685 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
39686 {
39687 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39689 },
39690 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39691 {
39692 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39694 },
39695 /* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
39696 {
39697 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39699 },
39700 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39701 {
39702 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39704 },
39705 /* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
39706 {
39707 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39709 },
39710 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39711 {
39712 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39714 },
39715 /* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
39716 {
39717 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39719 },
39720 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
39721 {
39722 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39724 },
39725 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
39726 {
39727 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39729 },
39730 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
39731 {
39732 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39734 },
39735 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
39736 {
39737 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39739 },
39740 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
39741 {
39742 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39744 },
39745 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
39746 {
39747 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39749 },
39750 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
39751 {
39752 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39754 },
39755 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
39756 {
39757 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39759 },
39760 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
39761 {
39762 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39764 },
39765 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
39766 {
39767 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39769 },
39770 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
39771 {
39772 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39774 },
39775 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
39776 {
39777 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39779 },
39780 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
39781 {
39782 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39784 },
39785 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
39786 {
39787 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39789 },
39790 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
39791 {
39792 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39794 },
39795 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
39796 {
39797 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39799 },
39800 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
39801 {
39802 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39804 },
39805 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
39806 {
39807 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39809 },
39810 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
39811 {
39812 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39814 },
39815 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
39816 {
39817 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39819 },
39820 /* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
39821 {
39822 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39824 },
39825 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
39826 {
39827 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39829 },
39830 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
39831 {
39832 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39834 },
39835 /* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
39836 {
39837 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39839 },
39840 /* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
39841 {
39842 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39844 },
39845 /* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
39846 {
39847 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39849 },
39850 /* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
39851 {
39852 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39854 },
39855 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39856 {
39857 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39859 },
39860 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39861 {
39862 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39864 },
39865 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
39866 {
39867 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39869 },
39870 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39871 {
39872 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39874 },
39875 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39876 {
39877 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39879 },
39880 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
39881 {
39882 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39884 },
39885 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39886 {
39887 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39889 },
39890 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39891 {
39892 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39894 },
39895 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
39896 {
39897 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39899 },
39900 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
39901 {
39902 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39904 },
39905 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
39906 {
39907 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39909 },
39910 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
39911 {
39912 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39914 },
39915 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
39916 {
39917 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39919 },
39920 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
39921 {
39922 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39924 },
39925 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
39926 {
39927 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39929 },
39930 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
39931 {
39932 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39934 },
39935 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
39936 {
39937 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39939 },
39940 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
39941 {
39942 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39944 },
39945 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
39946 {
39947 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39949 },
39950 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
39951 {
39952 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39954 },
39955 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
39956 {
39957 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39959 },
39960 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
39961 {
39962 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39964 },
39965 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
39966 {
39967 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39969 },
39970 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
39971 {
39972 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39974 },
39975 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
39976 {
39977 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
39978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39979 },
39980 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
39981 {
39982 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
39983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39984 },
39985 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
39986 {
39987 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
39988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39989 },
39990 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
39991 {
39992 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
39993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39994 },
39995 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
39996 {
39997 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
39998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39999 },
40000 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
40001 {
40002 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40004 },
40005 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40006 {
40007 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40009 },
40010 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
40011 {
40012 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40014 },
40015 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
40016 {
40017 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40019 },
40020 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40021 {
40022 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40024 },
40025 /* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40026 {
40027 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40029 },
40030 /* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40031 {
40032 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40034 },
40035 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40036 {
40037 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40039 },
40040 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40041 {
40042 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40044 },
40045 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40046 {
40047 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40049 },
40050 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40051 {
40052 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40054 },
40055 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40056 {
40057 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40059 },
40060 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40061 {
40062 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40064 },
40065 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40066 {
40067 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40069 },
40070 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40071 {
40072 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40074 },
40075 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40076 {
40077 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40079 },
40080 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40081 {
40082 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40084 },
40085 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40086 {
40087 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40089 },
40090 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40091 {
40092 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40094 },
40095 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40096 {
40097 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40099 },
40100 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40101 {
40102 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40104 },
40105 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40106 {
40107 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40109 },
40110 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40111 {
40112 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40114 },
40115 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40116 {
40117 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40119 },
40120 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40121 {
40122 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40124 },
40125 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40126 {
40127 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40129 },
40130 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40131 {
40132 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40134 },
40135 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40136 {
40137 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40139 },
40140 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40141 {
40142 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40144 },
40145 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
40146 {
40147 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40149 },
40150 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
40151 {
40152 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40154 },
40155 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
40156 {
40157 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40159 },
40160 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
40161 {
40162 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40164 },
40165 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
40166 {
40167 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40169 },
40170 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40171 {
40172 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40174 },
40175 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
40176 {
40177 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40179 },
40180 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
40181 {
40182 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40184 },
40185 /* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
40186 {
40187 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40189 },
40190 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40191 {
40192 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40194 },
40195 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
40196 {
40197 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40199 },
40200 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
40201 {
40202 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40204 },
40205 /* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
40206 {
40207 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40209 },
40210 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40211 {
40212 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40214 },
40215 /* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
40216 {
40217 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40219 },
40220 /* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
40221 {
40222 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40224 },
40225 /* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
40226 {
40227 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40229 },
40230 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
40231 {
40232 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40234 },
40235 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40236 {
40237 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40239 },
40240 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40241 {
40242 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40244 },
40245 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
40246 {
40247 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40249 },
40250 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
40251 {
40252 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40254 },
40255 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40256 {
40257 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40259 },
40260 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40261 {
40262 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40264 },
40265 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
40266 {
40267 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40269 },
40270 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
40271 {
40272 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40274 },
40275 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40276 {
40277 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40279 },
40280 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40281 {
40282 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40284 },
40285 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
40286 {
40287 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40289 },
40290 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
40291 {
40292 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40294 },
40295 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
40296 {
40297 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40299 },
40300 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
40301 {
40302 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40304 },
40305 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
40306 {
40307 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40309 },
40310 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
40311 {
40312 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40314 },
40315 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
40316 {
40317 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40319 },
40320 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
40321 {
40322 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40324 },
40325 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
40326 {
40327 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40329 },
40330 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
40331 {
40332 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40334 },
40335 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
40336 {
40337 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40339 },
40340 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
40341 {
40342 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40344 },
40345 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
40346 {
40347 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40349 },
40350 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
40351 {
40352 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40354 },
40355 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
40356 {
40357 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40359 },
40360 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
40361 {
40362 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40364 },
40365 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
40366 {
40367 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40369 },
40370 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
40371 {
40372 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40374 },
40375 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
40376 {
40377 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40379 },
40380 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
40381 {
40382 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40384 },
40385 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
40386 {
40387 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40389 },
40390 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
40391 {
40392 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40394 },
40395 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
40396 {
40397 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40399 },
40400 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
40401 {
40402 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40404 },
40405 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
40406 {
40407 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40409 },
40410 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40411 {
40412 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40414 },
40415 /* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
40416 {
40417 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40419 },
40420 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40421 {
40422 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40424 },
40425 /* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
40426 {
40427 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40429 },
40430 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40431 {
40432 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40434 },
40435 /* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
40436 {
40437 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40439 },
40440 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
40441 {
40442 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40444 },
40445 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
40446 {
40447 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40449 },
40450 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
40451 {
40452 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40454 },
40455 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
40456 {
40457 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40459 },
40460 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
40461 {
40462 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40464 },
40465 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
40466 {
40467 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40469 },
40470 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
40471 {
40472 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40474 },
40475 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
40476 {
40477 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40479 },
40480 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
40481 {
40482 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40484 },
40485 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
40486 {
40487 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40489 },
40490 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
40491 {
40492 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40494 },
40495 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
40496 {
40497 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40499 },
40500 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
40501 {
40502 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40504 },
40505 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
40506 {
40507 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40509 },
40510 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
40511 {
40512 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40514 },
40515 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
40516 {
40517 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40519 },
40520 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
40521 {
40522 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40524 },
40525 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
40526 {
40527 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40529 },
40530 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
40531 {
40532 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40534 },
40535 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
40536 {
40537 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40539 },
40540 /* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
40541 {
40542 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40544 },
40545 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
40546 {
40547 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40549 },
40550 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
40551 {
40552 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40554 },
40555 /* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
40556 {
40557 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40559 },
40560 /* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
40561 {
40562 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40564 },
40565 /* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
40566 {
40567 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40569 },
40570 /* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
40571 {
40572 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40574 },
40575 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40576 {
40577 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40579 },
40580 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40581 {
40582 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40584 },
40585 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
40586 {
40587 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40589 },
40590 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40591 {
40592 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40594 },
40595 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40596 {
40597 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40599 },
40600 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
40601 {
40602 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40604 },
40605 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40606 {
40607 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40609 },
40610 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40611 {
40612 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40614 },
40615 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
40616 {
40617 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40619 },
40620 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
40621 {
40622 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40624 },
40625 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
40626 {
40627 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40629 },
40630 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
40631 {
40632 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40634 },
40635 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
40636 {
40637 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40639 },
40640 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
40641 {
40642 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40644 },
40645 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
40646 {
40647 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40649 },
40650 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
40651 {
40652 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40654 },
40655 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
40656 {
40657 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40659 },
40660 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
40661 {
40662 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40664 },
40665 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
40666 {
40667 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40669 },
40670 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
40671 {
40672 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40674 },
40675 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
40676 {
40677 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40679 },
40680 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
40681 {
40682 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40684 },
40685 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
40686 {
40687 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40689 },
40690 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
40691 {
40692 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40694 },
40695 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
40696 {
40697 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40699 },
40700 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
40701 {
40702 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40704 },
40705 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40706 {
40707 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40709 },
40710 /* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
40711 {
40712 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
40713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40714 },
40715 /* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
40716 {
40717 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
40718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40719 },
40720 /* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
40721 {
40722 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
40723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40724 },
40725 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40726 {
40727 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48,
40728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40729 },
40730 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
40731 {
40732 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48,
40733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40734 },
40735 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
40736 {
40737 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48,
40738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40739 },
40740 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40741 {
40742 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56,
40743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40744 },
40745 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
40746 {
40747 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56,
40748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40749 },
40750 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
40751 {
40752 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56,
40753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40754 },
40755 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
40756 {
40757 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56,
40758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40759 },
40760 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40761 {
40762 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64,
40763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40764 },
40765 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
40766 {
40767 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64,
40768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40769 },
40770 /* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
40771 {
40772 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40774 },
40775 /* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
40776 {
40777 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40779 },
40780 /* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
40781 {
40782 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40784 },
40785 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40786 {
40787 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40,
40788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40789 },
40790 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
40791 {
40792 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40794 },
40795 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
40796 {
40797 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40799 },
40800 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40801 {
40802 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48,
40803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40804 },
40805 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
40806 {
40807 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40809 },
40810 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
40811 {
40812 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40814 },
40815 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
40816 {
40817 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48,
40818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40819 },
40820 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40821 {
40822 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56,
40823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40824 },
40825 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
40826 {
40827 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56,
40828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40829 },
40830 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40831 {
40832 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40834 },
40835 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
40836 {
40837 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40839 },
40840 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
40841 {
40842 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40844 },
40845 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40846 {
40847 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40849 },
40850 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
40851 {
40852 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40854 },
40855 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
40856 {
40857 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40859 },
40860 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40861 {
40862 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40864 },
40865 /* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40866 {
40867 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40869 },
40870 /* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40871 {
40872 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40874 },
40875 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40876 {
40877 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40879 },
40880 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40881 {
40882 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40884 },
40885 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40886 {
40887 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40889 },
40890 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40891 {
40892 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40894 },
40895 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40896 {
40897 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40899 },
40900 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40901 {
40902 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40904 },
40905 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40906 {
40907 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40909 },
40910 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40911 {
40912 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40914 },
40915 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40916 {
40917 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40919 },
40920 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40921 {
40922 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40924 },
40925 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40926 {
40927 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40929 },
40930 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40931 {
40932 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40934 },
40935 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40936 {
40937 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40939 },
40940 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40941 {
40942 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40944 },
40945 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40946 {
40947 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40949 },
40950 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40951 {
40952 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40954 },
40955 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40956 {
40957 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40959 },
40960 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40961 {
40962 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40964 },
40965 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40966 {
40967 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40969 },
40970 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40971 {
40972 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40974 },
40975 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40976 {
40977 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40979 },
40980 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40981 {
40982 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
40983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40984 },
40985 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
40986 {
40987 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
40988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40989 },
40990 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
40991 {
40992 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
40993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40994 },
40995 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
40996 {
40997 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
40998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40999 },
41000 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41001 {
41002 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41004 },
41005 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41006 {
41007 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41009 },
41010 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41011 {
41012 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41014 },
41015 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
41016 {
41017 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41019 },
41020 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
41021 {
41022 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41024 },
41025 /* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
41026 {
41027 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41029 },
41030 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41031 {
41032 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41034 },
41035 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
41036 {
41037 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41039 },
41040 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
41041 {
41042 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41044 },
41045 /* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
41046 {
41047 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41049 },
41050 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41051 {
41052 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41054 },
41055 /* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41056 {
41057 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41059 },
41060 /* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41061 {
41062 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41064 },
41065 /* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41066 {
41067 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41069 },
41070 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41071 {
41072 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41074 },
41075 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41076 {
41077 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41079 },
41080 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41081 {
41082 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41084 },
41085 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41086 {
41087 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41089 },
41090 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41091 {
41092 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41094 },
41095 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41096 {
41097 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41099 },
41100 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41101 {
41102 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41104 },
41105 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41106 {
41107 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41109 },
41110 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41111 {
41112 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41114 },
41115 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41116 {
41117 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41119 },
41120 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41121 {
41122 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41124 },
41125 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41126 {
41127 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41129 },
41130 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41131 {
41132 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41134 },
41135 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41136 {
41137 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41139 },
41140 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41141 {
41142 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41144 },
41145 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41146 {
41147 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41149 },
41150 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41151 {
41152 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41154 },
41155 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41156 {
41157 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41159 },
41160 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41161 {
41162 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41164 },
41165 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41166 {
41167 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41169 },
41170 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41171 {
41172 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41174 },
41175 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41176 {
41177 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41179 },
41180 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41181 {
41182 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41184 },
41185 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41186 {
41187 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41189 },
41190 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41191 {
41192 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41194 },
41195 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41196 {
41197 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41199 },
41200 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41201 {
41202 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41204 },
41205 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41206 {
41207 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41209 },
41210 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41211 {
41212 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41214 },
41215 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41216 {
41217 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41219 },
41220 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41221 {
41222 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41224 },
41225 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
41226 {
41227 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41229 },
41230 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41231 {
41232 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41234 },
41235 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41236 {
41237 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41239 },
41240 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41241 {
41242 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41244 },
41245 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
41246 {
41247 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41249 },
41250 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41251 {
41252 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
41253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41254 },
41255 /* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
41256 {
41257 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
41258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41259 },
41260 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41261 {
41262 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
41263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41264 },
41265 /* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
41266 {
41267 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
41268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41269 },
41270 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41271 {
41272 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
41273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41274 },
41275 /* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41276 {
41277 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
41278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41279 },
41280 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41281 {
41282 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
41283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41284 },
41285 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41286 {
41287 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
41288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41289 },
41290 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41291 {
41292 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
41293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41294 },
41295 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41296 {
41297 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
41298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41299 },
41300 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41301 {
41302 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
41303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41304 },
41305 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41306 {
41307 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
41308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41309 },
41310 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41311 {
41312 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
41313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41314 },
41315 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41316 {
41317 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
41318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41319 },
41320 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41321 {
41322 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
41323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41324 },
41325 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41326 {
41327 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
41328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41329 },
41330 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41331 {
41332 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
41333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41334 },
41335 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41336 {
41337 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
41338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41339 },
41340 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41341 {
41342 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
41343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41344 },
41345 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41346 {
41347 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
41348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41349 },
41350 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41351 {
41352 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
41353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41354 },
41355 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
41356 {
41357 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
41358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41359 },
41360 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41361 {
41362 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
41363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41364 },
41365 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
41366 {
41367 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
41368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41369 },
41370 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
41371 {
41372 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41374 },
41375 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41376 {
41377 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41379 },
41380 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41381 {
41382 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41384 },
41385 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41386 {
41387 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41389 },
41390 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41391 {
41392 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41394 },
41395 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41396 {
41397 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41399 },
41400 /* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41401 {
41402 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41404 },
41405 /* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41406 {
41407 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41409 },
41410 /* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41411 {
41412 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41414 },
41415 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41416 {
41417 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41419 },
41420 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41421 {
41422 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41424 },
41425 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41426 {
41427 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41429 },
41430 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41431 {
41432 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41434 },
41435 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41436 {
41437 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41439 },
41440 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41441 {
41442 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41444 },
41445 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41446 {
41447 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41449 },
41450 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41451 {
41452 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41454 },
41455 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41456 {
41457 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41459 },
41460 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41461 {
41462 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41464 },
41465 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41466 {
41467 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41469 },
41470 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41471 {
41472 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41474 },
41475 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41476 {
41477 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41479 },
41480 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41481 {
41482 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41484 },
41485 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41486 {
41487 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41489 },
41490 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41491 {
41492 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41494 },
41495 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41496 {
41497 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41499 },
41500 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41501 {
41502 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41504 },
41505 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41506 {
41507 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41509 },
41510 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41511 {
41512 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41514 },
41515 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41516 {
41517 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41519 },
41520 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41521 {
41522 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41524 },
41525 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41526 {
41527 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41529 },
41530 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41531 {
41532 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41534 },
41535 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41536 {
41537 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41539 },
41540 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41541 {
41542 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41544 },
41545 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41546 {
41547 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41549 },
41550 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41551 {
41552 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41554 },
41555 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41556 {
41557 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41559 },
41560 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41561 {
41562 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41564 },
41565 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41566 {
41567 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41569 },
41570 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41571 {
41572 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41574 },
41575 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41576 {
41577 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41579 },
41580 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41581 {
41582 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41584 },
41585 /* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41586 {
41587 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41589 },
41590 /* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41591 {
41592 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41594 },
41595 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41596 {
41597 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41599 },
41600 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41601 {
41602 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41604 },
41605 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41606 {
41607 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41609 },
41610 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41611 {
41612 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41614 },
41615 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41616 {
41617 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41619 },
41620 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41621 {
41622 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41624 },
41625 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41626 {
41627 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41629 },
41630 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41631 {
41632 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41634 },
41635 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41636 {
41637 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41639 },
41640 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41641 {
41642 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41644 },
41645 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41646 {
41647 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41649 },
41650 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41651 {
41652 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41654 },
41655 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41656 {
41657 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41659 },
41660 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41661 {
41662 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41664 },
41665 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41666 {
41667 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41669 },
41670 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41671 {
41672 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41674 },
41675 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41676 {
41677 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41679 },
41680 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41681 {
41682 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41684 },
41685 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41686 {
41687 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41689 },
41690 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41691 {
41692 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41694 },
41695 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41696 {
41697 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41699 },
41700 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41701 {
41702 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41704 },
41705 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41706 {
41707 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41709 },
41710 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41711 {
41712 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41714 },
41715 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41716 {
41717 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41719 },
41720 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41721 {
41722 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41724 },
41725 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41726 {
41727 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41729 },
41730 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41731 {
41732 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41734 },
41735 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
41736 {
41737 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41739 },
41740 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
41741 {
41742 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41744 },
41745 /* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
41746 {
41747 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41749 },
41750 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41751 {
41752 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41754 },
41755 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
41756 {
41757 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41759 },
41760 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
41761 {
41762 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41764 },
41765 /* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
41766 {
41767 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41769 },
41770 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41771 {
41772 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41774 },
41775 /* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41776 {
41777 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41779 },
41780 /* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41781 {
41782 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41784 },
41785 /* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41786 {
41787 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41789 },
41790 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41791 {
41792 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41794 },
41795 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41796 {
41797 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41799 },
41800 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41801 {
41802 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41804 },
41805 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41806 {
41807 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41809 },
41810 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41811 {
41812 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41814 },
41815 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41816 {
41817 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41819 },
41820 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41821 {
41822 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41824 },
41825 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41826 {
41827 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41829 },
41830 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41831 {
41832 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41834 },
41835 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41836 {
41837 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41839 },
41840 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41841 {
41842 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41844 },
41845 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41846 {
41847 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41849 },
41850 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41851 {
41852 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41854 },
41855 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41856 {
41857 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41859 },
41860 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41861 {
41862 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41864 },
41865 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41866 {
41867 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41869 },
41870 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41871 {
41872 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41874 },
41875 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41876 {
41877 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41879 },
41880 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41881 {
41882 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41884 },
41885 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41886 {
41887 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41889 },
41890 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41891 {
41892 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41894 },
41895 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41896 {
41897 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41899 },
41900 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41901 {
41902 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41904 },
41905 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41906 {
41907 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41909 },
41910 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41911 {
41912 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41914 },
41915 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41916 {
41917 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41919 },
41920 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41921 {
41922 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41924 },
41925 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41926 {
41927 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41929 },
41930 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41931 {
41932 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41934 },
41935 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41936 {
41937 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41939 },
41940 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41941 {
41942 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41944 },
41945 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
41946 {
41947 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41949 },
41950 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41951 {
41952 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41954 },
41955 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41956 {
41957 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41959 },
41960 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41961 {
41962 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41964 },
41965 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
41966 {
41967 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41969 },
41970 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41971 {
41972 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
41973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41974 },
41975 /* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
41976 {
41977 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
41978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41979 },
41980 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41981 {
41982 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
41983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41984 },
41985 /* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
41986 {
41987 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
41988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41989 },
41990 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41991 {
41992 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
41993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41994 },
41995 /* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41996 {
41997 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
41998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41999 },
42000 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
42001 {
42002 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
42003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42004 },
42005 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
42006 {
42007 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
42008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42009 },
42010 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
42011 {
42012 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
42013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42014 },
42015 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
42016 {
42017 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
42018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42019 },
42020 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
42021 {
42022 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
42023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42024 },
42025 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
42026 {
42027 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
42028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42029 },
42030 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
42031 {
42032 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
42033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42034 },
42035 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
42036 {
42037 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
42038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42039 },
42040 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
42041 {
42042 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
42043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42044 },
42045 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
42046 {
42047 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
42048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42049 },
42050 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
42051 {
42052 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
42053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42054 },
42055 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
42056 {
42057 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
42058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42059 },
42060 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
42061 {
42062 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
42063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42064 },
42065 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
42066 {
42067 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
42068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42069 },
42070 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
42071 {
42072 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
42073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42074 },
42075 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
42076 {
42077 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
42078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42079 },
42080 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
42081 {
42082 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
42083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42084 },
42085 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
42086 {
42087 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
42088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42089 },
42090 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
42091 {
42092 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42094 },
42095 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
42096 {
42097 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42099 },
42100 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
42101 {
42102 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42104 },
42105 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
42106 {
42107 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42109 },
42110 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
42111 {
42112 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42114 },
42115 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
42116 {
42117 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42119 },
42120 /* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
42121 {
42122 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42124 },
42125 /* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
42126 {
42127 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42129 },
42130 /* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
42131 {
42132 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42134 },
42135 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42136 {
42137 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42139 },
42140 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42141 {
42142 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42144 },
42145 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
42146 {
42147 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42149 },
42150 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42151 {
42152 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42154 },
42155 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42156 {
42157 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42159 },
42160 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
42161 {
42162 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42164 },
42165 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42166 {
42167 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42169 },
42170 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42171 {
42172 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42174 },
42175 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
42176 {
42177 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42179 },
42180 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
42181 {
42182 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42184 },
42185 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
42186 {
42187 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42189 },
42190 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
42191 {
42192 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42194 },
42195 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
42196 {
42197 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42199 },
42200 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
42201 {
42202 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42204 },
42205 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
42206 {
42207 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42209 },
42210 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
42211 {
42212 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42214 },
42215 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
42216 {
42217 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42219 },
42220 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
42221 {
42222 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42224 },
42225 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
42226 {
42227 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42229 },
42230 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
42231 {
42232 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42234 },
42235 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
42236 {
42237 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42239 },
42240 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
42241 {
42242 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42244 },
42245 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
42246 {
42247 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42249 },
42250 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
42251 {
42252 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42254 },
42255 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
42256 {
42257 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42259 },
42260 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
42261 {
42262 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42264 },
42265 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
42266 {
42267 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42269 },
42270 /* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
42271 {
42272 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
42273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42274 },
42275 /* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
42276 {
42277 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
42278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42279 },
42280 /* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
42281 {
42282 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
42283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42284 },
42285 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42286 {
42287 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48,
42288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42289 },
42290 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
42291 {
42292 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
42293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42294 },
42295 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
42296 {
42297 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
42298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42299 },
42300 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42301 {
42302 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56,
42303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42304 },
42305 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
42306 {
42307 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
42308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42309 },
42310 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
42311 {
42312 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
42313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42314 },
42315 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
42316 {
42317 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56,
42318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42319 },
42320 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42321 {
42322 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64,
42323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42324 },
42325 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
42326 {
42327 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64,
42328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42329 },
42330 /* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
42331 {
42332 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
42333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42334 },
42335 /* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
42336 {
42337 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
42338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42339 },
42340 /* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
42341 {
42342 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
42343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42344 },
42345 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42346 {
42347 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40,
42348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42349 },
42350 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
42351 {
42352 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
42353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42354 },
42355 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
42356 {
42357 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
42358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42359 },
42360 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42361 {
42362 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48,
42363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42364 },
42365 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
42366 {
42367 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
42368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42369 },
42370 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
42371 {
42372 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
42373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42374 },
42375 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42376 {
42377 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48,
42378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42379 },
42380 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42381 {
42382 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56,
42383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42384 },
42385 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42386 {
42387 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56,
42388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42389 },
42390 /* divx.l $Dst32RnPrefixedSI */
42391 {
42392 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24,
42393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42394 },
42395 /* divx.l $Dst32AnPrefixedSI */
42396 {
42397 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24,
42398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42399 },
42400 /* divx.l [$Dst32AnPrefixed] */
42401 {
42402 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24,
42403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42404 },
42405 /* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42406 {
42407 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32,
42408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42409 },
42410 /* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42411 {
42412 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40,
42413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42414 },
42415 /* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42416 {
42417 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48,
42418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42419 },
42420 /* divx.l ${Dsp-24-u8}[sb] */
42421 {
42422 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32,
42423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42424 },
42425 /* divx.l ${Dsp-24-u16}[sb] */
42426 {
42427 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40,
42428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42429 },
42430 /* divx.l ${Dsp-24-s8}[fb] */
42431 {
42432 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32,
42433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42434 },
42435 /* divx.l ${Dsp-24-s16}[fb] */
42436 {
42437 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40,
42438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42439 },
42440 /* divx.l ${Dsp-24-u16} */
42441 {
42442 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40,
42443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42444 },
42445 /* divx.l ${Dsp-24-u24} */
42446 {
42447 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48,
42448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42449 },
42450 /* divu.l $Dst32RnPrefixedSI */
42451 {
42452 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24,
42453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42454 },
42455 /* divu.l $Dst32AnPrefixedSI */
42456 {
42457 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24,
42458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42459 },
42460 /* divu.l [$Dst32AnPrefixed] */
42461 {
42462 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24,
42463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42464 },
42465 /* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42466 {
42467 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32,
42468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42469 },
42470 /* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42471 {
42472 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40,
42473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42474 },
42475 /* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42476 {
42477 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48,
42478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42479 },
42480 /* divu.l ${Dsp-24-u8}[sb] */
42481 {
42482 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32,
42483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42484 },
42485 /* divu.l ${Dsp-24-u16}[sb] */
42486 {
42487 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40,
42488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42489 },
42490 /* divu.l ${Dsp-24-s8}[fb] */
42491 {
42492 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32,
42493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42494 },
42495 /* divu.l ${Dsp-24-s16}[fb] */
42496 {
42497 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40,
42498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42499 },
42500 /* divu.l ${Dsp-24-u16} */
42501 {
42502 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40,
42503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42504 },
42505 /* divu.l ${Dsp-24-u24} */
42506 {
42507 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48,
42508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42509 },
42510 /* div.l $Dst32RnPrefixedSI */
42511 {
42512 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24,
42513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42514 },
42515 /* div.l $Dst32AnPrefixedSI */
42516 {
42517 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24,
42518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42519 },
42520 /* div.l [$Dst32AnPrefixed] */
42521 {
42522 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24,
42523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42524 },
42525 /* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42526 {
42527 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32,
42528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42529 },
42530 /* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42531 {
42532 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40,
42533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42534 },
42535 /* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42536 {
42537 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48,
42538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42539 },
42540 /* div.l ${Dsp-24-u8}[sb] */
42541 {
42542 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32,
42543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42544 },
42545 /* div.l ${Dsp-24-u16}[sb] */
42546 {
42547 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40,
42548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42549 },
42550 /* div.l ${Dsp-24-s8}[fb] */
42551 {
42552 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32,
42553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42554 },
42555 /* div.l ${Dsp-24-s16}[fb] */
42556 {
42557 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40,
42558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42559 },
42560 /* div.l ${Dsp-24-u16} */
42561 {
42562 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40,
42563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42564 },
42565 /* div.l ${Dsp-24-u24} */
42566 {
42567 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48,
42568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42569 },
42570 /* divx.w $Dst32RnUnprefixedHI */
42571 {
42572 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16,
42573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42574 },
42575 /* divx.w $Dst32AnUnprefixedHI */
42576 {
42577 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16,
42578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42579 },
42580 /* divx.w [$Dst32AnUnprefixed] */
42581 {
42582 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16,
42583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42584 },
42585 /* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42586 {
42587 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24,
42588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42589 },
42590 /* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42591 {
42592 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32,
42593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42594 },
42595 /* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42596 {
42597 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40,
42598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42599 },
42600 /* divx.w ${Dsp-16-u8}[sb] */
42601 {
42602 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24,
42603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42604 },
42605 /* divx.w ${Dsp-16-u16}[sb] */
42606 {
42607 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32,
42608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42609 },
42610 /* divx.w ${Dsp-16-s8}[fb] */
42611 {
42612 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24,
42613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42614 },
42615 /* divx.w ${Dsp-16-s16}[fb] */
42616 {
42617 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32,
42618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42619 },
42620 /* divx.w ${Dsp-16-u16} */
42621 {
42622 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32,
42623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42624 },
42625 /* divx.w ${Dsp-16-u24} */
42626 {
42627 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40,
42628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42629 },
42630 /* divx.b $Dst32RnUnprefixedQI */
42631 {
42632 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16,
42633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42634 },
42635 /* divx.b $Dst32AnUnprefixedQI */
42636 {
42637 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16,
42638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42639 },
42640 /* divx.b [$Dst32AnUnprefixed] */
42641 {
42642 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16,
42643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42644 },
42645 /* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42646 {
42647 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24,
42648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42649 },
42650 /* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42651 {
42652 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32,
42653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42654 },
42655 /* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42656 {
42657 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40,
42658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42659 },
42660 /* divx.b ${Dsp-16-u8}[sb] */
42661 {
42662 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24,
42663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42664 },
42665 /* divx.b ${Dsp-16-u16}[sb] */
42666 {
42667 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32,
42668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42669 },
42670 /* divx.b ${Dsp-16-s8}[fb] */
42671 {
42672 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24,
42673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42674 },
42675 /* divx.b ${Dsp-16-s16}[fb] */
42676 {
42677 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32,
42678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42679 },
42680 /* divx.b ${Dsp-16-u16} */
42681 {
42682 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32,
42683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42684 },
42685 /* divx.b ${Dsp-16-u24} */
42686 {
42687 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40,
42688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42689 },
42690 /* divx.w $Dst16RnHI */
42691 {
42692 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16,
42693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42694 },
42695 /* divx.w $Dst16AnHI */
42696 {
42697 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16,
42698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42699 },
42700 /* divx.w [$Dst16An] */
42701 {
42702 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16,
42703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42704 },
42705 /* divx.w ${Dsp-16-u8}[$Dst16An] */
42706 {
42707 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24,
42708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42709 },
42710 /* divx.w ${Dsp-16-u16}[$Dst16An] */
42711 {
42712 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32,
42713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42714 },
42715 /* divx.w ${Dsp-16-u8}[sb] */
42716 {
42717 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24,
42718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42719 },
42720 /* divx.w ${Dsp-16-u16}[sb] */
42721 {
42722 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32,
42723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42724 },
42725 /* divx.w ${Dsp-16-s8}[fb] */
42726 {
42727 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24,
42728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42729 },
42730 /* divx.w ${Dsp-16-u16} */
42731 {
42732 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32,
42733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42734 },
42735 /* divx.b $Dst16RnQI */
42736 {
42737 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16,
42738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42739 },
42740 /* divx.b $Dst16AnQI */
42741 {
42742 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16,
42743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42744 },
42745 /* divx.b [$Dst16An] */
42746 {
42747 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16,
42748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42749 },
42750 /* divx.b ${Dsp-16-u8}[$Dst16An] */
42751 {
42752 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24,
42753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42754 },
42755 /* divx.b ${Dsp-16-u16}[$Dst16An] */
42756 {
42757 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32,
42758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42759 },
42760 /* divx.b ${Dsp-16-u8}[sb] */
42761 {
42762 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24,
42763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42764 },
42765 /* divx.b ${Dsp-16-u16}[sb] */
42766 {
42767 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32,
42768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42769 },
42770 /* divx.b ${Dsp-16-s8}[fb] */
42771 {
42772 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24,
42773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42774 },
42775 /* divx.b ${Dsp-16-u16} */
42776 {
42777 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32,
42778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42779 },
42780 /* divu.w $Dst32RnUnprefixedHI */
42781 {
42782 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16,
42783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42784 },
42785 /* divu.w $Dst32AnUnprefixedHI */
42786 {
42787 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16,
42788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42789 },
42790 /* divu.w [$Dst32AnUnprefixed] */
42791 {
42792 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16,
42793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42794 },
42795 /* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42796 {
42797 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24,
42798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42799 },
42800 /* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42801 {
42802 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32,
42803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42804 },
42805 /* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42806 {
42807 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40,
42808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42809 },
42810 /* divu.w ${Dsp-16-u8}[sb] */
42811 {
42812 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24,
42813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42814 },
42815 /* divu.w ${Dsp-16-u16}[sb] */
42816 {
42817 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32,
42818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42819 },
42820 /* divu.w ${Dsp-16-s8}[fb] */
42821 {
42822 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24,
42823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42824 },
42825 /* divu.w ${Dsp-16-s16}[fb] */
42826 {
42827 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32,
42828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42829 },
42830 /* divu.w ${Dsp-16-u16} */
42831 {
42832 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32,
42833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42834 },
42835 /* divu.w ${Dsp-16-u24} */
42836 {
42837 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40,
42838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42839 },
42840 /* divu.b $Dst32RnUnprefixedQI */
42841 {
42842 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16,
42843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42844 },
42845 /* divu.b $Dst32AnUnprefixedQI */
42846 {
42847 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16,
42848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42849 },
42850 /* divu.b [$Dst32AnUnprefixed] */
42851 {
42852 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16,
42853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42854 },
42855 /* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42856 {
42857 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24,
42858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42859 },
42860 /* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42861 {
42862 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32,
42863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42864 },
42865 /* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42866 {
42867 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40,
42868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42869 },
42870 /* divu.b ${Dsp-16-u8}[sb] */
42871 {
42872 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24,
42873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42874 },
42875 /* divu.b ${Dsp-16-u16}[sb] */
42876 {
42877 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32,
42878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42879 },
42880 /* divu.b ${Dsp-16-s8}[fb] */
42881 {
42882 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24,
42883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42884 },
42885 /* divu.b ${Dsp-16-s16}[fb] */
42886 {
42887 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32,
42888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42889 },
42890 /* divu.b ${Dsp-16-u16} */
42891 {
42892 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32,
42893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42894 },
42895 /* divu.b ${Dsp-16-u24} */
42896 {
42897 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40,
42898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42899 },
42900 /* divu.w $Dst16RnHI */
42901 {
42902 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16,
42903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42904 },
42905 /* divu.w $Dst16AnHI */
42906 {
42907 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16,
42908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42909 },
42910 /* divu.w [$Dst16An] */
42911 {
42912 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16,
42913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42914 },
42915 /* divu.w ${Dsp-16-u8}[$Dst16An] */
42916 {
42917 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24,
42918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42919 },
42920 /* divu.w ${Dsp-16-u16}[$Dst16An] */
42921 {
42922 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32,
42923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42924 },
42925 /* divu.w ${Dsp-16-u8}[sb] */
42926 {
42927 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24,
42928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42929 },
42930 /* divu.w ${Dsp-16-u16}[sb] */
42931 {
42932 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32,
42933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42934 },
42935 /* divu.w ${Dsp-16-s8}[fb] */
42936 {
42937 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24,
42938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42939 },
42940 /* divu.w ${Dsp-16-u16} */
42941 {
42942 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32,
42943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42944 },
42945 /* divu.b $Dst16RnQI */
42946 {
42947 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16,
42948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42949 },
42950 /* divu.b $Dst16AnQI */
42951 {
42952 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16,
42953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42954 },
42955 /* divu.b [$Dst16An] */
42956 {
42957 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16,
42958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42959 },
42960 /* divu.b ${Dsp-16-u8}[$Dst16An] */
42961 {
42962 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24,
42963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42964 },
42965 /* divu.b ${Dsp-16-u16}[$Dst16An] */
42966 {
42967 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32,
42968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42969 },
42970 /* divu.b ${Dsp-16-u8}[sb] */
42971 {
42972 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24,
42973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42974 },
42975 /* divu.b ${Dsp-16-u16}[sb] */
42976 {
42977 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32,
42978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42979 },
42980 /* divu.b ${Dsp-16-s8}[fb] */
42981 {
42982 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24,
42983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42984 },
42985 /* divu.b ${Dsp-16-u16} */
42986 {
42987 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32,
42988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42989 },
42990 /* div.w $Dst32RnUnprefixedHI */
42991 {
42992 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16,
42993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42994 },
42995 /* div.w $Dst32AnUnprefixedHI */
42996 {
42997 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16,
42998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42999 },
43000 /* div.w [$Dst32AnUnprefixed] */
43001 {
43002 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16,
43003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43004 },
43005 /* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43006 {
43007 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24,
43008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43009 },
43010 /* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43011 {
43012 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32,
43013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43014 },
43015 /* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43016 {
43017 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40,
43018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43019 },
43020 /* div.w ${Dsp-16-u8}[sb] */
43021 {
43022 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24,
43023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43024 },
43025 /* div.w ${Dsp-16-u16}[sb] */
43026 {
43027 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32,
43028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43029 },
43030 /* div.w ${Dsp-16-s8}[fb] */
43031 {
43032 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24,
43033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43034 },
43035 /* div.w ${Dsp-16-s16}[fb] */
43036 {
43037 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32,
43038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43039 },
43040 /* div.w ${Dsp-16-u16} */
43041 {
43042 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32,
43043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43044 },
43045 /* div.w ${Dsp-16-u24} */
43046 {
43047 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40,
43048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43049 },
43050 /* div.b $Dst32RnUnprefixedQI */
43051 {
43052 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16,
43053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43054 },
43055 /* div.b $Dst32AnUnprefixedQI */
43056 {
43057 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16,
43058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43059 },
43060 /* div.b [$Dst32AnUnprefixed] */
43061 {
43062 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16,
43063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43064 },
43065 /* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43066 {
43067 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24,
43068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43069 },
43070 /* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43071 {
43072 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32,
43073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43074 },
43075 /* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43076 {
43077 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40,
43078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43079 },
43080 /* div.b ${Dsp-16-u8}[sb] */
43081 {
43082 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24,
43083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43084 },
43085 /* div.b ${Dsp-16-u16}[sb] */
43086 {
43087 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32,
43088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43089 },
43090 /* div.b ${Dsp-16-s8}[fb] */
43091 {
43092 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24,
43093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43094 },
43095 /* div.b ${Dsp-16-s16}[fb] */
43096 {
43097 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32,
43098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43099 },
43100 /* div.b ${Dsp-16-u16} */
43101 {
43102 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32,
43103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43104 },
43105 /* div.b ${Dsp-16-u24} */
43106 {
43107 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40,
43108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43109 },
43110 /* div.w $Dst16RnHI */
43111 {
43112 M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16,
43113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43114 },
43115 /* div.w $Dst16AnHI */
43116 {
43117 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16,
43118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43119 },
43120 /* div.w [$Dst16An] */
43121 {
43122 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16,
43123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43124 },
43125 /* div.w ${Dsp-16-u8}[$Dst16An] */
43126 {
43127 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24,
43128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43129 },
43130 /* div.w ${Dsp-16-u16}[$Dst16An] */
43131 {
43132 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32,
43133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43134 },
43135 /* div.w ${Dsp-16-u8}[sb] */
43136 {
43137 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24,
43138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43139 },
43140 /* div.w ${Dsp-16-u16}[sb] */
43141 {
43142 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32,
43143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43144 },
43145 /* div.w ${Dsp-16-s8}[fb] */
43146 {
43147 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24,
43148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43149 },
43150 /* div.w ${Dsp-16-u16} */
43151 {
43152 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32,
43153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43154 },
43155 /* div.b $Dst16RnQI */
43156 {
43157 M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16,
43158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43159 },
43160 /* div.b $Dst16AnQI */
43161 {
43162 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16,
43163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43164 },
43165 /* div.b [$Dst16An] */
43166 {
43167 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16,
43168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43169 },
43170 /* div.b ${Dsp-16-u8}[$Dst16An] */
43171 {
43172 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24,
43173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43174 },
43175 /* div.b ${Dsp-16-u16}[$Dst16An] */
43176 {
43177 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32,
43178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43179 },
43180 /* div.b ${Dsp-16-u8}[sb] */
43181 {
43182 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24,
43183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43184 },
43185 /* div.b ${Dsp-16-u16}[sb] */
43186 {
43187 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32,
43188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43189 },
43190 /* div.b ${Dsp-16-s8}[fb] */
43191 {
43192 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24,
43193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43194 },
43195 /* div.b ${Dsp-16-u16} */
43196 {
43197 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32,
43198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43199 },
43200 /* dec.w $Dst32RnUnprefixedHI */
43201 {
43202 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16,
43203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43204 },
43205 /* dec.w $Dst32AnUnprefixedHI */
43206 {
43207 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16,
43208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43209 },
43210 /* dec.w [$Dst32AnUnprefixed] */
43211 {
43212 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16,
43213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43214 },
43215 /* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43216 {
43217 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24,
43218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43219 },
43220 /* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43221 {
43222 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32,
43223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43224 },
43225 /* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43226 {
43227 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40,
43228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43229 },
43230 /* dec.w ${Dsp-16-u8}[sb] */
43231 {
43232 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24,
43233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43234 },
43235 /* dec.w ${Dsp-16-u16}[sb] */
43236 {
43237 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32,
43238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43239 },
43240 /* dec.w ${Dsp-16-s8}[fb] */
43241 {
43242 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24,
43243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43244 },
43245 /* dec.w ${Dsp-16-s16}[fb] */
43246 {
43247 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32,
43248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43249 },
43250 /* dec.w ${Dsp-16-u16} */
43251 {
43252 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32,
43253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43254 },
43255 /* dec.w ${Dsp-16-u24} */
43256 {
43257 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40,
43258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43259 },
43260 /* dec.b $Dst32RnUnprefixedQI */
43261 {
43262 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16,
43263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43264 },
43265 /* dec.b $Dst32AnUnprefixedQI */
43266 {
43267 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16,
43268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43269 },
43270 /* dec.b [$Dst32AnUnprefixed] */
43271 {
43272 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16,
43273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43274 },
43275 /* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43276 {
43277 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24,
43278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43279 },
43280 /* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43281 {
43282 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32,
43283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43284 },
43285 /* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43286 {
43287 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40,
43288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43289 },
43290 /* dec.b ${Dsp-16-u8}[sb] */
43291 {
43292 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24,
43293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43294 },
43295 /* dec.b ${Dsp-16-u16}[sb] */
43296 {
43297 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32,
43298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43299 },
43300 /* dec.b ${Dsp-16-s8}[fb] */
43301 {
43302 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24,
43303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43304 },
43305 /* dec.b ${Dsp-16-s16}[fb] */
43306 {
43307 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32,
43308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43309 },
43310 /* dec.b ${Dsp-16-u16} */
43311 {
43312 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32,
43313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43314 },
43315 /* dec.b ${Dsp-16-u24} */
43316 {
43317 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40,
43318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43319 },
43320 /* dec.b r0l */
43321 {
43322 M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8,
43323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43324 },
43325 /* dec.b r0h */
43326 {
43327 M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8,
43328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43329 },
43330 /* dec.b ${Dsp-8-u8}[sb] */
43331 {
43332 M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16,
43333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43334 },
43335 /* dec.b ${Dsp-8-s8}[fb] */
43336 {
43337 M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16,
43338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43339 },
43340 /* dec.b ${Dsp-8-u16} */
43341 {
43342 M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24,
43343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43344 },
43345 /* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
43346 {
43347 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24,
43348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43349 },
43350 /* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
43351 {
43352 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24,
43353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43354 },
43355 /* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
43356 {
43357 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24,
43358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43359 },
43360 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
43361 {
43362 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32,
43363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43364 },
43365 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
43366 {
43367 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32,
43368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43369 },
43370 /* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
43371 {
43372 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32,
43373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43374 },
43375 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
43376 {
43377 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40,
43378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43379 },
43380 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
43381 {
43382 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40,
43383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43384 },
43385 /* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
43386 {
43387 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40,
43388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43389 },
43390 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
43391 {
43392 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40,
43393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43394 },
43395 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
43396 {
43397 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48,
43398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43399 },
43400 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
43401 {
43402 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48,
43403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43404 },
43405 /* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
43406 {
43407 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16,
43408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43409 },
43410 /* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
43411 {
43412 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16,
43413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43414 },
43415 /* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
43416 {
43417 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24,
43418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43419 },
43420 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
43421 {
43422 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16,
43423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43424 },
43425 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
43426 {
43427 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16,
43428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43429 },
43430 /* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
43431 {
43432 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24,
43433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43434 },
43435 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
43436 {
43437 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32,
43438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43439 },
43440 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
43441 {
43442 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32,
43443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43444 },
43445 /* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
43446 {
43447 M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40,
43448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43449 },
43450 /* cmp.w${S} #${Imm-8-HI},r0 */
43451 {
43452 M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24,
43453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43454 },
43455 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
43456 {
43457 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24,
43458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43459 },
43460 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
43461 {
43462 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24,
43463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43464 },
43465 /* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
43466 {
43467 M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32,
43468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43469 },
43470 /* cmp.b${S} #${Imm-8-QI},r0l */
43471 {
43472 M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16,
43473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43474 },
43475 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43476 {
43477 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43479 },
43480 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
43481 {
43482 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43484 },
43485 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
43486 {
43487 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43489 },
43490 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43491 {
43492 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43494 },
43495 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
43496 {
43497 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43499 },
43500 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
43501 {
43502 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43504 },
43505 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43506 {
43507 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43509 },
43510 /* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
43511 {
43512 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43514 },
43515 /* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
43516 {
43517 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43519 },
43520 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43521 {
43522 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43524 },
43525 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43526 {
43527 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43529 },
43530 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43531 {
43532 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43534 },
43535 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43536 {
43537 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43539 },
43540 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43541 {
43542 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43544 },
43545 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43546 {
43547 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43549 },
43550 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43551 {
43552 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43554 },
43555 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43556 {
43557 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43559 },
43560 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43561 {
43562 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43564 },
43565 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
43566 {
43567 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43569 },
43570 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
43571 {
43572 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43574 },
43575 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
43576 {
43577 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43579 },
43580 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
43581 {
43582 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43584 },
43585 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
43586 {
43587 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43589 },
43590 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
43591 {
43592 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43594 },
43595 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
43596 {
43597 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43599 },
43600 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
43601 {
43602 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43604 },
43605 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
43606 {
43607 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43609 },
43610 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
43611 {
43612 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43614 },
43615 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
43616 {
43617 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43619 },
43620 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
43621 {
43622 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43624 },
43625 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
43626 {
43627 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43629 },
43630 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
43631 {
43632 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43634 },
43635 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
43636 {
43637 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43639 },
43640 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
43641 {
43642 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43644 },
43645 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
43646 {
43647 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43649 },
43650 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
43651 {
43652 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43654 },
43655 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43656 {
43657 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43659 },
43660 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
43661 {
43662 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43664 },
43665 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
43666 {
43667 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43669 },
43670 /* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
43671 {
43672 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43674 },
43675 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43676 {
43677 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43679 },
43680 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
43681 {
43682 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43684 },
43685 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
43686 {
43687 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43689 },
43690 /* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
43691 {
43692 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43694 },
43695 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43696 {
43697 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43699 },
43700 /* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
43701 {
43702 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43704 },
43705 /* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
43706 {
43707 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43709 },
43710 /* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
43711 {
43712 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43714 },
43715 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43716 {
43717 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43719 },
43720 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43721 {
43722 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43724 },
43725 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43726 {
43727 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43729 },
43730 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
43731 {
43732 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43734 },
43735 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43736 {
43737 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43739 },
43740 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43741 {
43742 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43744 },
43745 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43746 {
43747 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43749 },
43750 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
43751 {
43752 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43754 },
43755 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43756 {
43757 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43759 },
43760 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43761 {
43762 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43764 },
43765 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43766 {
43767 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43769 },
43770 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
43771 {
43772 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43774 },
43775 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
43776 {
43777 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43779 },
43780 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
43781 {
43782 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43784 },
43785 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
43786 {
43787 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43789 },
43790 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
43791 {
43792 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43794 },
43795 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
43796 {
43797 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43799 },
43800 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
43801 {
43802 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43804 },
43805 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
43806 {
43807 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43809 },
43810 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
43811 {
43812 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43814 },
43815 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
43816 {
43817 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43819 },
43820 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
43821 {
43822 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43824 },
43825 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
43826 {
43827 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43829 },
43830 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
43831 {
43832 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43834 },
43835 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
43836 {
43837 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43839 },
43840 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
43841 {
43842 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43844 },
43845 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
43846 {
43847 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43849 },
43850 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
43851 {
43852 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43854 },
43855 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
43856 {
43857 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43859 },
43860 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
43861 {
43862 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43864 },
43865 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
43866 {
43867 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43869 },
43870 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
43871 {
43872 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43874 },
43875 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
43876 {
43877 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43879 },
43880 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
43881 {
43882 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43884 },
43885 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
43886 {
43887 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43889 },
43890 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
43891 {
43892 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43894 },
43895 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43896 {
43897 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43899 },
43900 /* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
43901 {
43902 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43904 },
43905 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43906 {
43907 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43909 },
43910 /* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
43911 {
43912 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43914 },
43915 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43916 {
43917 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43919 },
43920 /* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
43921 {
43922 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43924 },
43925 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
43926 {
43927 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43929 },
43930 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
43931 {
43932 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43934 },
43935 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
43936 {
43937 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43939 },
43940 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
43941 {
43942 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43944 },
43945 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
43946 {
43947 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43949 },
43950 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
43951 {
43952 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43954 },
43955 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
43956 {
43957 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43959 },
43960 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
43961 {
43962 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43964 },
43965 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
43966 {
43967 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
43968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43969 },
43970 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
43971 {
43972 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
43973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43974 },
43975 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
43976 {
43977 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
43978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43979 },
43980 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
43981 {
43982 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
43983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43984 },
43985 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
43986 {
43987 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
43988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43989 },
43990 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
43991 {
43992 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
43993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43994 },
43995 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
43996 {
43997 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
43998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43999 },
44000 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
44001 {
44002 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
44003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44004 },
44005 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44006 {
44007 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
44008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44009 },
44010 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
44011 {
44012 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
44013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44014 },
44015 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
44016 {
44017 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44019 },
44020 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
44021 {
44022 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44024 },
44025 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
44026 {
44027 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44029 },
44030 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
44031 {
44032 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44034 },
44035 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
44036 {
44037 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44039 },
44040 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
44041 {
44042 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44044 },
44045 /* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
44046 {
44047 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44049 },
44050 /* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
44051 {
44052 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44054 },
44055 /* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44056 {
44057 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44059 },
44060 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44061 {
44062 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44064 },
44065 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44066 {
44067 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44069 },
44070 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44071 {
44072 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44074 },
44075 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44076 {
44077 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44079 },
44080 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44081 {
44082 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44084 },
44085 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44086 {
44087 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44089 },
44090 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44091 {
44092 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44094 },
44095 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44096 {
44097 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44099 },
44100 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44101 {
44102 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44104 },
44105 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
44106 {
44107 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44109 },
44110 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
44111 {
44112 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44114 },
44115 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44116 {
44117 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44119 },
44120 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
44121 {
44122 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44124 },
44125 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
44126 {
44127 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44129 },
44130 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44131 {
44132 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44134 },
44135 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
44136 {
44137 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44139 },
44140 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
44141 {
44142 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44144 },
44145 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44146 {
44147 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44149 },
44150 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
44151 {
44152 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44154 },
44155 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
44156 {
44157 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44159 },
44160 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44161 {
44162 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44164 },
44165 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
44166 {
44167 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44169 },
44170 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
44171 {
44172 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44174 },
44175 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44176 {
44177 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44179 },
44180 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
44181 {
44182 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44184 },
44185 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
44186 {
44187 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44189 },
44190 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44191 {
44192 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44194 },
44195 /* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
44196 {
44197 M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8,
44198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44199 },
44200 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
44201 {
44202 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16,
44203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44204 },
44205 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
44206 {
44207 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16,
44208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44209 },
44210 /* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
44211 {
44212 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24,
44213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44214 },
44215 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44216 {
44217 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44219 },
44220 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
44221 {
44222 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44224 },
44225 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
44226 {
44227 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44229 },
44230 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44231 {
44232 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44234 },
44235 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
44236 {
44237 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44239 },
44240 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
44241 {
44242 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44244 },
44245 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44246 {
44247 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44249 },
44250 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
44251 {
44252 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44254 },
44255 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
44256 {
44257 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44259 },
44260 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44261 {
44262 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44264 },
44265 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44266 {
44267 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44269 },
44270 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44271 {
44272 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44274 },
44275 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44276 {
44277 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44279 },
44280 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44281 {
44282 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44284 },
44285 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44286 {
44287 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44289 },
44290 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44291 {
44292 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44294 },
44295 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44296 {
44297 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44299 },
44300 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44301 {
44302 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44304 },
44305 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
44306 {
44307 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44309 },
44310 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
44311 {
44312 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44314 },
44315 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
44316 {
44317 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44319 },
44320 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
44321 {
44322 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44324 },
44325 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
44326 {
44327 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44329 },
44330 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
44331 {
44332 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44334 },
44335 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
44336 {
44337 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44339 },
44340 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
44341 {
44342 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44344 },
44345 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
44346 {
44347 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44349 },
44350 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
44351 {
44352 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44354 },
44355 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
44356 {
44357 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44359 },
44360 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
44361 {
44362 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44364 },
44365 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
44366 {
44367 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44369 },
44370 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
44371 {
44372 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44374 },
44375 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
44376 {
44377 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44379 },
44380 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
44381 {
44382 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44384 },
44385 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
44386 {
44387 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44389 },
44390 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
44391 {
44392 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44394 },
44395 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44396 {
44397 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44399 },
44400 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
44401 {
44402 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44404 },
44405 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
44406 {
44407 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44409 },
44410 /* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
44411 {
44412 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44414 },
44415 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44416 {
44417 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44419 },
44420 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
44421 {
44422 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44424 },
44425 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
44426 {
44427 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44429 },
44430 /* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
44431 {
44432 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44434 },
44435 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44436 {
44437 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44439 },
44440 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
44441 {
44442 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44444 },
44445 /* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
44446 {
44447 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44449 },
44450 /* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
44451 {
44452 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44454 },
44455 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44456 {
44457 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44459 },
44460 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44461 {
44462 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44464 },
44465 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44466 {
44467 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44469 },
44470 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
44471 {
44472 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44474 },
44475 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44476 {
44477 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44479 },
44480 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44481 {
44482 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44484 },
44485 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44486 {
44487 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44489 },
44490 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
44491 {
44492 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44494 },
44495 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44496 {
44497 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44499 },
44500 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44501 {
44502 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44504 },
44505 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44506 {
44507 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44509 },
44510 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
44511 {
44512 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44514 },
44515 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
44516 {
44517 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44519 },
44520 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
44521 {
44522 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44524 },
44525 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
44526 {
44527 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44529 },
44530 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
44531 {
44532 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44534 },
44535 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
44536 {
44537 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44539 },
44540 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
44541 {
44542 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44544 },
44545 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
44546 {
44547 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44549 },
44550 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
44551 {
44552 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44554 },
44555 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
44556 {
44557 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44559 },
44560 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
44561 {
44562 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44564 },
44565 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
44566 {
44567 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44569 },
44570 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
44571 {
44572 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44574 },
44575 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
44576 {
44577 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44579 },
44580 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
44581 {
44582 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44584 },
44585 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
44586 {
44587 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44589 },
44590 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
44591 {
44592 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44594 },
44595 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
44596 {
44597 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44599 },
44600 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
44601 {
44602 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44604 },
44605 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
44606 {
44607 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44609 },
44610 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
44611 {
44612 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44614 },
44615 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
44616 {
44617 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44619 },
44620 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
44621 {
44622 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44624 },
44625 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
44626 {
44627 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44629 },
44630 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
44631 {
44632 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44634 },
44635 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44636 {
44637 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44639 },
44640 /* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
44641 {
44642 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44644 },
44645 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44646 {
44647 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44649 },
44650 /* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
44651 {
44652 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44654 },
44655 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44656 {
44657 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44659 },
44660 /* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
44661 {
44662 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44664 },
44665 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
44666 {
44667 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44669 },
44670 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
44671 {
44672 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44674 },
44675 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
44676 {
44677 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44679 },
44680 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
44681 {
44682 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44684 },
44685 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
44686 {
44687 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44689 },
44690 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
44691 {
44692 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44694 },
44695 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
44696 {
44697 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44699 },
44700 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
44701 {
44702 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44704 },
44705 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
44706 {
44707 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44709 },
44710 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
44711 {
44712 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44714 },
44715 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
44716 {
44717 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44719 },
44720 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
44721 {
44722 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44724 },
44725 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44726 {
44727 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44729 },
44730 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44731 {
44732 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44734 },
44735 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44736 {
44737 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44739 },
44740 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
44741 {
44742 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44744 },
44745 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44746 {
44747 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44749 },
44750 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
44751 {
44752 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44754 },
44755 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
44756 {
44757 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44759 },
44760 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
44761 {
44762 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44764 },
44765 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44766 {
44767 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44769 },
44770 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
44771 {
44772 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44774 },
44775 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
44776 {
44777 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44779 },
44780 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44781 {
44782 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44784 },
44785 /* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
44786 {
44787 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44789 },
44790 /* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
44791 {
44792 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44794 },
44795 /* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44796 {
44797 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44799 },
44800 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44801 {
44802 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44804 },
44805 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44806 {
44807 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44809 },
44810 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44811 {
44812 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44814 },
44815 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44816 {
44817 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44819 },
44820 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44821 {
44822 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44824 },
44825 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44826 {
44827 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44829 },
44830 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44831 {
44832 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44834 },
44835 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44836 {
44837 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44839 },
44840 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44841 {
44842 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44844 },
44845 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
44846 {
44847 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44849 },
44850 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
44851 {
44852 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44854 },
44855 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44856 {
44857 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44859 },
44860 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
44861 {
44862 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44864 },
44865 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
44866 {
44867 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44869 },
44870 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44871 {
44872 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44874 },
44875 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
44876 {
44877 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44879 },
44880 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
44881 {
44882 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44884 },
44885 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44886 {
44887 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44889 },
44890 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
44891 {
44892 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44894 },
44895 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
44896 {
44897 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44899 },
44900 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44901 {
44902 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44904 },
44905 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
44906 {
44907 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44909 },
44910 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
44911 {
44912 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44914 },
44915 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44916 {
44917 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44919 },
44920 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
44921 {
44922 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44924 },
44925 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
44926 {
44927 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44929 },
44930 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44931 {
44932 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44934 },
44935 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
44936 {
44937 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44939 },
44940 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
44941 {
44942 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44944 },
44945 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
44946 {
44947 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44949 },
44950 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
44951 {
44952 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44954 },
44955 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
44956 {
44957 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44959 },
44960 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
44961 {
44962 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44964 },
44965 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44966 {
44967 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44969 },
44970 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
44971 {
44972 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44974 },
44975 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
44976 {
44977 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44979 },
44980 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44981 {
44982 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
44983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44984 },
44985 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44986 {
44987 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
44988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44989 },
44990 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44991 {
44992 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
44993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44994 },
44995 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44996 {
44997 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
44998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44999 },
45000 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45001 {
45002 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45004 },
45005 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45006 {
45007 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45009 },
45010 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45011 {
45012 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45014 },
45015 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45016 {
45017 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45019 },
45020 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45021 {
45022 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45024 },
45025 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
45026 {
45027 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45029 },
45030 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45031 {
45032 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45034 },
45035 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45036 {
45037 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45039 },
45040 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
45041 {
45042 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45044 },
45045 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45046 {
45047 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45049 },
45050 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45051 {
45052 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45054 },
45055 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
45056 {
45057 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45059 },
45060 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45061 {
45062 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45064 },
45065 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45066 {
45067 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45069 },
45070 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
45071 {
45072 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45074 },
45075 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
45076 {
45077 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45079 },
45080 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
45081 {
45082 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45084 },
45085 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
45086 {
45087 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45089 },
45090 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45091 {
45092 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45094 },
45095 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45096 {
45097 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45099 },
45100 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
45101 {
45102 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45104 },
45105 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
45106 {
45107 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45109 },
45110 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
45111 {
45112 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45114 },
45115 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45116 {
45117 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45119 },
45120 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
45121 {
45122 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45124 },
45125 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
45126 {
45127 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45129 },
45130 /* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
45131 {
45132 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45134 },
45135 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45136 {
45137 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45139 },
45140 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
45141 {
45142 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45144 },
45145 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
45146 {
45147 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45149 },
45150 /* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
45151 {
45152 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45154 },
45155 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45156 {
45157 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45159 },
45160 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
45161 {
45162 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45164 },
45165 /* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
45166 {
45167 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45169 },
45170 /* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
45171 {
45172 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45174 },
45175 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45176 {
45177 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45179 },
45180 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45181 {
45182 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45184 },
45185 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45186 {
45187 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45189 },
45190 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
45191 {
45192 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45194 },
45195 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45196 {
45197 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45199 },
45200 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45201 {
45202 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45204 },
45205 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45206 {
45207 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45209 },
45210 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
45211 {
45212 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45214 },
45215 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45216 {
45217 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45219 },
45220 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45221 {
45222 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45224 },
45225 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45226 {
45227 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45229 },
45230 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
45231 {
45232 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45234 },
45235 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
45236 {
45237 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45239 },
45240 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45241 {
45242 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45244 },
45245 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
45246 {
45247 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45249 },
45250 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45251 {
45252 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45254 },
45255 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
45256 {
45257 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45259 },
45260 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45261 {
45262 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45264 },
45265 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
45266 {
45267 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45269 },
45270 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45271 {
45272 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45274 },
45275 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
45276 {
45277 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45279 },
45280 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45281 {
45282 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45284 },
45285 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
45286 {
45287 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45289 },
45290 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45291 {
45292 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45294 },
45295 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
45296 {
45297 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45299 },
45300 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
45301 {
45302 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45304 },
45305 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
45306 {
45307 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45309 },
45310 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
45311 {
45312 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45314 },
45315 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
45316 {
45317 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45319 },
45320 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45321 {
45322 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45324 },
45325 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
45326 {
45327 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45329 },
45330 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
45331 {
45332 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45334 },
45335 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
45336 {
45337 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45339 },
45340 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
45341 {
45342 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45344 },
45345 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
45346 {
45347 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45349 },
45350 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
45351 {
45352 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45354 },
45355 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45356 {
45357 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
45358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45359 },
45360 /* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
45361 {
45362 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
45363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45364 },
45365 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45366 {
45367 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
45368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45369 },
45370 /* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
45371 {
45372 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
45373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45374 },
45375 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45376 {
45377 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45379 },
45380 /* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
45381 {
45382 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45384 },
45385 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
45386 {
45387 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45389 },
45390 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
45391 {
45392 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45394 },
45395 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
45396 {
45397 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45399 },
45400 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
45401 {
45402 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45404 },
45405 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
45406 {
45407 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45409 },
45410 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
45411 {
45412 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45414 },
45415 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
45416 {
45417 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45419 },
45420 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
45421 {
45422 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45424 },
45425 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
45426 {
45427 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45429 },
45430 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
45431 {
45432 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45434 },
45435 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
45436 {
45437 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45439 },
45440 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
45441 {
45442 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45444 },
45445 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
45446 {
45447 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45449 },
45450 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
45451 {
45452 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45454 },
45455 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
45456 {
45457 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45459 },
45460 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
45461 {
45462 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45464 },
45465 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
45466 {
45467 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45469 },
45470 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
45471 {
45472 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45474 },
45475 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
45476 {
45477 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45479 },
45480 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
45481 {
45482 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45484 },
45485 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45486 {
45487 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45489 },
45490 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
45491 {
45492 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45494 },
45495 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
45496 {
45497 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45499 },
45500 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45501 {
45502 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45504 },
45505 /* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
45506 {
45507 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45509 },
45510 /* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
45511 {
45512 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45514 },
45515 /* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45516 {
45517 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45519 },
45520 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45521 {
45522 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45524 },
45525 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45526 {
45527 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45529 },
45530 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
45531 {
45532 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45534 },
45535 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45536 {
45537 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45539 },
45540 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45541 {
45542 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45544 },
45545 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
45546 {
45547 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45549 },
45550 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45551 {
45552 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45554 },
45555 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45556 {
45557 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45559 },
45560 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
45561 {
45562 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45564 },
45565 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
45566 {
45567 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45569 },
45570 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
45571 {
45572 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45574 },
45575 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
45576 {
45577 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45579 },
45580 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
45581 {
45582 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45584 },
45585 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
45586 {
45587 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45589 },
45590 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
45591 {
45592 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45594 },
45595 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
45596 {
45597 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45599 },
45600 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
45601 {
45602 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45604 },
45605 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
45606 {
45607 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45609 },
45610 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
45611 {
45612 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45614 },
45615 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
45616 {
45617 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45619 },
45620 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
45621 {
45622 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45624 },
45625 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
45626 {
45627 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45629 },
45630 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
45631 {
45632 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45634 },
45635 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
45636 {
45637 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45639 },
45640 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
45641 {
45642 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45644 },
45645 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
45646 {
45647 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45649 },
45650 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
45651 {
45652 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45654 },
45655 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
45656 {
45657 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45659 },
45660 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
45661 {
45662 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45664 },
45665 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
45666 {
45667 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45669 },
45670 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
45671 {
45672 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45674 },
45675 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
45676 {
45677 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45679 },
45680 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
45681 {
45682 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45684 },
45685 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
45686 {
45687 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45689 },
45690 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
45691 {
45692 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45694 },
45695 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
45696 {
45697 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45699 },
45700 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
45701 {
45702 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45704 },
45705 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
45706 {
45707 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45709 },
45710 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
45711 {
45712 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45714 },
45715 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
45716 {
45717 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45719 },
45720 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
45721 {
45722 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45724 },
45725 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
45726 {
45727 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45729 },
45730 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
45731 {
45732 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45734 },
45735 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45736 {
45737 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45739 },
45740 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45741 {
45742 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45744 },
45745 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
45746 {
45747 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45749 },
45750 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45751 {
45752 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45754 },
45755 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45756 {
45757 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45759 },
45760 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
45761 {
45762 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45764 },
45765 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45766 {
45767 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45769 },
45770 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45771 {
45772 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45774 },
45775 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
45776 {
45777 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45779 },
45780 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45781 {
45782 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45784 },
45785 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45786 {
45787 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45789 },
45790 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
45791 {
45792 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45794 },
45795 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
45796 {
45797 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45799 },
45800 /* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
45801 {
45802 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45804 },
45805 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
45806 {
45807 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45809 },
45810 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
45811 {
45812 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45814 },
45815 /* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
45816 {
45817 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32,
45818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45819 },
45820 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
45821 {
45822 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45824 },
45825 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
45826 {
45827 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45829 },
45830 /* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
45831 {
45832 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32,
45833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45834 },
45835 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
45836 {
45837 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45839 },
45840 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
45841 {
45842 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45844 },
45845 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
45846 {
45847 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45849 },
45850 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
45851 {
45852 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45854 },
45855 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
45856 {
45857 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45859 },
45860 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
45861 {
45862 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45864 },
45865 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
45866 {
45867 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45869 },
45870 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45871 {
45872 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45874 },
45875 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45876 {
45877 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45879 },
45880 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
45881 {
45882 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45884 },
45885 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45886 {
45887 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45889 },
45890 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45891 {
45892 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45894 },
45895 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
45896 {
45897 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45899 },
45900 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45901 {
45902 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45904 },
45905 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45906 {
45907 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45909 },
45910 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
45911 {
45912 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45914 },
45915 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45916 {
45917 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45919 },
45920 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
45921 {
45922 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45924 },
45925 /* cmp.w${G} $Src16RnHI,$Dst16RnHI */
45926 {
45927 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45929 },
45930 /* cmp.w${G} $Src16AnHI,$Dst16RnHI */
45931 {
45932 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45934 },
45935 /* cmp.w${G} [$Src16An],$Dst16RnHI */
45936 {
45937 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45939 },
45940 /* cmp.w${G} $Src16RnHI,$Dst16AnHI */
45941 {
45942 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45944 },
45945 /* cmp.w${G} $Src16AnHI,$Dst16AnHI */
45946 {
45947 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45949 },
45950 /* cmp.w${G} [$Src16An],$Dst16AnHI */
45951 {
45952 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16,
45953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45954 },
45955 /* cmp.w${G} $Src16RnHI,[$Dst16An] */
45956 {
45957 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45959 },
45960 /* cmp.w${G} $Src16AnHI,[$Dst16An] */
45961 {
45962 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45964 },
45965 /* cmp.w${G} [$Src16An],[$Dst16An] */
45966 {
45967 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16,
45968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45969 },
45970 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
45971 {
45972 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45974 },
45975 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
45976 {
45977 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45979 },
45980 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
45981 {
45982 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45984 },
45985 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
45986 {
45987 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
45988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45989 },
45990 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
45991 {
45992 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
45993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45994 },
45995 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
45996 {
45997 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
45998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45999 },
46000 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
46001 {
46002 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46004 },
46005 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
46006 {
46007 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46009 },
46010 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
46011 {
46012 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46014 },
46015 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
46016 {
46017 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46019 },
46020 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
46021 {
46022 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46024 },
46025 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
46026 {
46027 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46029 },
46030 /* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
46031 {
46032 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46034 },
46035 /* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
46036 {
46037 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46039 },
46040 /* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
46041 {
46042 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46044 },
46045 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
46046 {
46047 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46049 },
46050 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
46051 {
46052 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46054 },
46055 /* cmp.w${G} [$Src16An],${Dsp-16-u16} */
46056 {
46057 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46059 },
46060 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
46061 {
46062 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46064 },
46065 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
46066 {
46067 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46069 },
46070 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
46071 {
46072 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46074 },
46075 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
46076 {
46077 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46079 },
46080 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
46081 {
46082 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46084 },
46085 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
46086 {
46087 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46089 },
46090 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
46091 {
46092 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46094 },
46095 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
46096 {
46097 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46099 },
46100 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
46101 {
46102 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46104 },
46105 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
46106 {
46107 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46109 },
46110 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
46111 {
46112 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46114 },
46115 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
46116 {
46117 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46119 },
46120 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
46121 {
46122 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46124 },
46125 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
46126 {
46127 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46129 },
46130 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
46131 {
46132 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46134 },
46135 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
46136 {
46137 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46139 },
46140 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
46141 {
46142 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46144 },
46145 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
46146 {
46147 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46149 },
46150 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
46151 {
46152 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46154 },
46155 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
46156 {
46157 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46159 },
46160 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
46161 {
46162 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46164 },
46165 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
46166 {
46167 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46169 },
46170 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
46171 {
46172 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46174 },
46175 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
46176 {
46177 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46179 },
46180 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
46181 {
46182 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46184 },
46185 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
46186 {
46187 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46189 },
46190 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
46191 {
46192 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46194 },
46195 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
46196 {
46197 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46199 },
46200 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
46201 {
46202 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46204 },
46205 /* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
46206 {
46207 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46209 },
46210 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
46211 {
46212 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
46213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46214 },
46215 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
46216 {
46217 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
46218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46219 },
46220 /* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
46221 {
46222 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32,
46223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46224 },
46225 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
46226 {
46227 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
46228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46229 },
46230 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
46231 {
46232 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
46233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46234 },
46235 /* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
46236 {
46237 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32,
46238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46239 },
46240 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
46241 {
46242 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46244 },
46245 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
46246 {
46247 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46249 },
46250 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
46251 {
46252 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46254 },
46255 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
46256 {
46257 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46259 },
46260 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
46261 {
46262 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46264 },
46265 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
46266 {
46267 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46269 },
46270 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
46271 {
46272 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46274 },
46275 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
46276 {
46277 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46279 },
46280 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
46281 {
46282 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46284 },
46285 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
46286 {
46287 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46289 },
46290 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
46291 {
46292 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46294 },
46295 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
46296 {
46297 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46299 },
46300 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
46301 {
46302 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46304 },
46305 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
46306 {
46307 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46309 },
46310 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
46311 {
46312 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46314 },
46315 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
46316 {
46317 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46319 },
46320 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
46321 {
46322 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46324 },
46325 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
46326 {
46327 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46329 },
46330 /* cmp.b${G} $Src16RnQI,$Dst16RnQI */
46331 {
46332 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46334 },
46335 /* cmp.b${G} $Src16AnQI,$Dst16RnQI */
46336 {
46337 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46339 },
46340 /* cmp.b${G} [$Src16An],$Dst16RnQI */
46341 {
46342 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46344 },
46345 /* cmp.b${G} $Src16RnQI,$Dst16AnQI */
46346 {
46347 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
46348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46349 },
46350 /* cmp.b${G} $Src16AnQI,$Dst16AnQI */
46351 {
46352 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
46353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46354 },
46355 /* cmp.b${G} [$Src16An],$Dst16AnQI */
46356 {
46357 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16,
46358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46359 },
46360 /* cmp.b${G} $Src16RnQI,[$Dst16An] */
46361 {
46362 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
46363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46364 },
46365 /* cmp.b${G} $Src16AnQI,[$Dst16An] */
46366 {
46367 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
46368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46369 },
46370 /* cmp.b${G} [$Src16An],[$Dst16An] */
46371 {
46372 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16,
46373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46374 },
46375 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
46376 {
46377 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46379 },
46380 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
46381 {
46382 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46384 },
46385 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
46386 {
46387 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46389 },
46390 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
46391 {
46392 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46394 },
46395 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
46396 {
46397 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46399 },
46400 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46401 {
46402 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46404 },
46405 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
46406 {
46407 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46409 },
46410 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
46411 {
46412 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46414 },
46415 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
46416 {
46417 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46419 },
46420 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
46421 {
46422 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46424 },
46425 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
46426 {
46427 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46429 },
46430 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
46431 {
46432 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46434 },
46435 /* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
46436 {
46437 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46439 },
46440 /* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
46441 {
46442 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46444 },
46445 /* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
46446 {
46447 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46449 },
46450 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
46451 {
46452 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46454 },
46455 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
46456 {
46457 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46459 },
46460 /* cmp.b${G} [$Src16An],${Dsp-16-u16} */
46461 {
46462 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46464 },
46465 /* cmp.b${S} #${Imm-8-QI},r0l */
46466 {
46467 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16,
46468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46469 },
46470 /* cmp.b${S} #${Imm-8-QI},r0h */
46471 {
46472 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16,
46473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46474 },
46475 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
46476 {
46477 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24,
46478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46479 },
46480 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
46481 {
46482 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24,
46483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46484 },
46485 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
46486 {
46487 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32,
46488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46489 },
46490 /* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
46491 {
46492 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
46493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46494 },
46495 /* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
46496 {
46497 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
46498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46499 },
46500 /* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46501 {
46502 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
46503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46504 },
46505 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46506 {
46507 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
46508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46509 },
46510 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46511 {
46512 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
46513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46514 },
46515 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46516 {
46517 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
46518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46519 },
46520 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46521 {
46522 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
46523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46524 },
46525 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46526 {
46527 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
46528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46529 },
46530 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46531 {
46532 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
46533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46534 },
46535 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46536 {
46537 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
46538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46539 },
46540 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
46541 {
46542 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
46543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46544 },
46545 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
46546 {
46547 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
46548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46549 },
46550 /* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
46551 {
46552 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
46553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46554 },
46555 /* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
46556 {
46557 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
46558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46559 },
46560 /* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46561 {
46562 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
46563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46564 },
46565 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46566 {
46567 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
46568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46569 },
46570 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46571 {
46572 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
46573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46574 },
46575 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46576 {
46577 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
46578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46579 },
46580 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46581 {
46582 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
46583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46584 },
46585 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46586 {
46587 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
46588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46589 },
46590 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46591 {
46592 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
46593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46594 },
46595 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46596 {
46597 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
46598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46599 },
46600 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
46601 {
46602 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
46603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46604 },
46605 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
46606 {
46607 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
46608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46609 },
46610 /* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
46611 {
46612 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16,
46613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46614 },
46615 /* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
46616 {
46617 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16,
46618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46619 },
46620 /* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
46621 {
46622 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16,
46623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46624 },
46625 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46626 {
46627 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24,
46628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46629 },
46630 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46631 {
46632 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32,
46633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46634 },
46635 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46636 {
46637 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46639 },
46640 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46641 {
46642 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46644 },
46645 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46646 {
46647 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46649 },
46650 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
46651 {
46652 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32,
46653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46654 },
46655 /* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
46656 {
46657 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16,
46658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46659 },
46660 /* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
46661 {
46662 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16,
46663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46664 },
46665 /* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
46666 {
46667 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16,
46668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46669 },
46670 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46671 {
46672 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24,
46673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46674 },
46675 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46676 {
46677 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32,
46678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46679 },
46680 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46681 {
46682 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46684 },
46685 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46686 {
46687 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46689 },
46690 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46691 {
46692 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46694 },
46695 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
46696 {
46697 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32,
46698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46699 },
46700 /* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
46701 {
46702 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
46703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46704 },
46705 /* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
46706 {
46707 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
46708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46709 },
46710 /* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
46711 {
46712 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
46713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46714 },
46715 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46716 {
46717 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40,
46718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46719 },
46720 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46721 {
46722 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
46723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46724 },
46725 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46726 {
46727 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
46728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46729 },
46730 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46731 {
46732 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48,
46733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46734 },
46735 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46736 {
46737 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
46738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46739 },
46740 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
46741 {
46742 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
46743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46744 },
46745 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46746 {
46747 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48,
46748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46749 },
46750 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46751 {
46752 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56,
46753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46754 },
46755 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
46756 {
46757 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56,
46758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46759 },
46760 /* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
46761 {
46762 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
46763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46764 },
46765 /* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
46766 {
46767 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
46768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46769 },
46770 /* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
46771 {
46772 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
46773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46774 },
46775 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46776 {
46777 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32,
46778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46779 },
46780 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46781 {
46782 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
46783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46784 },
46785 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46786 {
46787 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
46788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46789 },
46790 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46791 {
46792 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40,
46793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46794 },
46795 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46796 {
46797 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
46798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46799 },
46800 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
46801 {
46802 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
46803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46804 },
46805 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46806 {
46807 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40,
46808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46809 },
46810 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46811 {
46812 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48,
46813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46814 },
46815 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
46816 {
46817 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48,
46818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46819 },
46820 /* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
46821 {
46822 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32,
46823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46824 },
46825 /* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
46826 {
46827 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32,
46828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46829 },
46830 /* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
46831 {
46832 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32,
46833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46834 },
46835 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
46836 {
46837 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40,
46838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46839 },
46840 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46841 {
46842 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40,
46843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46844 },
46845 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46846 {
46847 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40,
46848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46849 },
46850 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
46851 {
46852 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48,
46853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46854 },
46855 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46856 {
46857 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48,
46858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46859 },
46860 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46861 {
46862 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48,
46863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46864 },
46865 /* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
46866 {
46867 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24,
46868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46869 },
46870 /* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
46871 {
46872 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24,
46873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46874 },
46875 /* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
46876 {
46877 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24,
46878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46879 },
46880 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
46881 {
46882 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32,
46883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46884 },
46885 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46886 {
46887 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32,
46888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46889 },
46890 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46891 {
46892 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32,
46893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46894 },
46895 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
46896 {
46897 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40,
46898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46899 },
46900 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46901 {
46902 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40,
46903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46904 },
46905 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46906 {
46907 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40,
46908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46909 },
46910 /* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
46911 {
46912 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48,
46913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46914 },
46915 /* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
46916 {
46917 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48,
46918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46919 },
46920 /* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
46921 {
46922 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48,
46923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46924 },
46925 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46926 {
46927 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56,
46928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46929 },
46930 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
46931 {
46932 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56,
46933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46934 },
46935 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
46936 {
46937 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56,
46938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46939 },
46940 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46941 {
46942 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64,
46943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46944 },
46945 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
46946 {
46947 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64,
46948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46949 },
46950 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
46951 {
46952 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64,
46953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46954 },
46955 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
46956 {
46957 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64,
46958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46959 },
46960 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46961 {
46962 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72,
46963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46964 },
46965 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
46966 {
46967 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72,
46968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46969 },
46970 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
46971 {
46972 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56,
46973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46974 },
46975 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
46976 {
46977 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56,
46978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46979 },
46980 /* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
46981 {
46982 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56,
46983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46984 },
46985 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
46986 {
46987 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64,
46988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46989 },
46990 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
46991 {
46992 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64,
46993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46994 },
46995 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
46996 {
46997 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64,
46998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46999 },
47000 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47001 {
47002 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72,
47003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47004 },
47005 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
47006 {
47007 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72,
47008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47009 },
47010 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
47011 {
47012 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72,
47013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47014 },
47015 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
47016 {
47017 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72,
47018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47019 },
47020 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47021 {
47022 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80,
47023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47024 },
47025 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
47026 {
47027 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80,
47028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47029 },
47030 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
47031 {
47032 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40,
47033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47034 },
47035 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
47036 {
47037 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40,
47038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47039 },
47040 /* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
47041 {
47042 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40,
47043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47044 },
47045 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
47046 {
47047 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48,
47048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47049 },
47050 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
47051 {
47052 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48,
47053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47054 },
47055 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
47056 {
47057 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48,
47058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47059 },
47060 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47061 {
47062 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56,
47063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47064 },
47065 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
47066 {
47067 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56,
47068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47069 },
47070 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
47071 {
47072 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56,
47073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47074 },
47075 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
47076 {
47077 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56,
47078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47079 },
47080 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47081 {
47082 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64,
47083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47084 },
47085 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
47086 {
47087 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64,
47088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47089 },
47090 /* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47091 {
47092 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24,
47093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47094 },
47095 /* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47096 {
47097 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24,
47098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47099 },
47100 /* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47101 {
47102 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24,
47103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47104 },
47105 /* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47106 {
47107 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32,
47108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47109 },
47110 /* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47111 {
47112 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40,
47113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47114 },
47115 /* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47116 {
47117 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48,
47118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47119 },
47120 /* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47121 {
47122 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32,
47123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47124 },
47125 /* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47126 {
47127 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40,
47128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47129 },
47130 /* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47131 {
47132 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32,
47133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47134 },
47135 /* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47136 {
47137 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40,
47138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47139 },
47140 /* bxor${X} ${BitBase32-24-u19-Prefixed} */
47141 {
47142 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40,
47143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47144 },
47145 /* bxor${X} ${BitBase32-24-u27-Prefixed} */
47146 {
47147 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48,
47148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47149 },
47150 /* bxor${X} $Bitno16R,$Bit16Rn */
47151 {
47152 M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24,
47153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47154 },
47155 /* bxor${X} $Bitno16R,$Bit16An */
47156 {
47157 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24,
47158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47159 },
47160 /* bxor${X} [$Bit16An] */
47161 {
47162 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16,
47163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47164 },
47165 /* bxor${X} ${Dsp-16-u8}[$Bit16An] */
47166 {
47167 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24,
47168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47169 },
47170 /* bxor${X} ${Dsp-16-u16}[$Bit16An] */
47171 {
47172 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32,
47173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47174 },
47175 /* bxor${X} ${BitBase16-16-u8}[sb] */
47176 {
47177 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24,
47178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47179 },
47180 /* bxor${X} ${BitBase16-16-u16}[sb] */
47181 {
47182 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32,
47183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47184 },
47185 /* bxor${X} ${BitBase16-16-s8}[fb] */
47186 {
47187 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24,
47188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47189 },
47190 /* bxor${X} ${BitBase16-16-u16} */
47191 {
47192 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32,
47193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47194 },
47195 /* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47196 {
47197 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16,
47198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47199 },
47200 /* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47201 {
47202 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16,
47203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47204 },
47205 /* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47206 {
47207 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16,
47208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47209 },
47210 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47211 {
47212 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24,
47213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47214 },
47215 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47216 {
47217 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32,
47218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47219 },
47220 /* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47221 {
47222 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40,
47223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47224 },
47225 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47226 {
47227 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24,
47228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47229 },
47230 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47231 {
47232 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32,
47233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47234 },
47235 /* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47236 {
47237 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24,
47238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47239 },
47240 /* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47241 {
47242 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32,
47243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47244 },
47245 /* btsts${X} ${BitBase32-16-u19-Unprefixed} */
47246 {
47247 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32,
47248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47249 },
47250 /* btsts${X} ${BitBase32-16-u27-Unprefixed} */
47251 {
47252 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40,
47253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47254 },
47255 /* btsts${X} $Bitno16R,$Bit16Rn */
47256 {
47257 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24,
47258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47259 },
47260 /* btsts${X} $Bitno16R,$Bit16An */
47261 {
47262 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24,
47263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47264 },
47265 /* btsts${X} [$Bit16An] */
47266 {
47267 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16,
47268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47269 },
47270 /* btsts${X} ${Dsp-16-u8}[$Bit16An] */
47271 {
47272 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24,
47273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47274 },
47275 /* btsts${X} ${Dsp-16-u16}[$Bit16An] */
47276 {
47277 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32,
47278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47279 },
47280 /* btsts${X} ${BitBase16-16-u8}[sb] */
47281 {
47282 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24,
47283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47284 },
47285 /* btsts${X} ${BitBase16-16-u16}[sb] */
47286 {
47287 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32,
47288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47289 },
47290 /* btsts${X} ${BitBase16-16-s8}[fb] */
47291 {
47292 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24,
47293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47294 },
47295 /* btsts${X} ${BitBase16-16-u16} */
47296 {
47297 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32,
47298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47299 },
47300 /* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47301 {
47302 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16,
47303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47304 },
47305 /* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47306 {
47307 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16,
47308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47309 },
47310 /* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47311 {
47312 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16,
47313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47314 },
47315 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47316 {
47317 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24,
47318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47319 },
47320 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47321 {
47322 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32,
47323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47324 },
47325 /* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47326 {
47327 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40,
47328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47329 },
47330 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47331 {
47332 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24,
47333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47334 },
47335 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47336 {
47337 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32,
47338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47339 },
47340 /* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47341 {
47342 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24,
47343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47344 },
47345 /* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47346 {
47347 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32,
47348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47349 },
47350 /* btstc${X} ${BitBase32-16-u19-Unprefixed} */
47351 {
47352 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32,
47353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47354 },
47355 /* btstc${X} ${BitBase32-16-u27-Unprefixed} */
47356 {
47357 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40,
47358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47359 },
47360 /* btstc${X} $Bitno16R,$Bit16Rn */
47361 {
47362 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24,
47363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47364 },
47365 /* btstc${X} $Bitno16R,$Bit16An */
47366 {
47367 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24,
47368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47369 },
47370 /* btstc${X} [$Bit16An] */
47371 {
47372 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16,
47373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47374 },
47375 /* btstc${X} ${Dsp-16-u8}[$Bit16An] */
47376 {
47377 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24,
47378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47379 },
47380 /* btstc${X} ${Dsp-16-u16}[$Bit16An] */
47381 {
47382 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32,
47383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47384 },
47385 /* btstc${X} ${BitBase16-16-u8}[sb] */
47386 {
47387 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24,
47388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47389 },
47390 /* btstc${X} ${BitBase16-16-u16}[sb] */
47391 {
47392 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32,
47393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47394 },
47395 /* btstc${X} ${BitBase16-16-s8}[fb] */
47396 {
47397 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24,
47398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47399 },
47400 /* btstc${X} ${BitBase16-16-u16} */
47401 {
47402 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32,
47403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47404 },
47405 /* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47406 {
47407 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16,
47408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47409 },
47410 /* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47411 {
47412 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16,
47413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47414 },
47415 /* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47416 {
47417 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16,
47418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47419 },
47420 /* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47421 {
47422 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24,
47423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47424 },
47425 /* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47426 {
47427 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32,
47428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47429 },
47430 /* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47431 {
47432 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40,
47433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47434 },
47435 /* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47436 {
47437 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24,
47438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47439 },
47440 /* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47441 {
47442 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32,
47443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47444 },
47445 /* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47446 {
47447 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24,
47448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47449 },
47450 /* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47451 {
47452 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32,
47453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47454 },
47455 /* btst${X} ${BitBase32-16-u19-Unprefixed} */
47456 {
47457 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32,
47458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47459 },
47460 /* btst${X} ${BitBase32-16-u27-Unprefixed} */
47461 {
47462 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40,
47463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47464 },
47465 /* btst${G} $Bitno16R,$Bit16Rn */
47466 {
47467 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24,
47468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47469 },
47470 /* btst${G} $Bitno16R,$Bit16An */
47471 {
47472 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24,
47473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47474 },
47475 /* btst${G} ${Dsp-16-u8}[$Bit16An] */
47476 {
47477 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24,
47478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47479 },
47480 /* btst${G} ${BitBase16-16-u8}[sb] */
47481 {
47482 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24,
47483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47484 },
47485 /* btst${G} ${BitBase16-16-s8}[fb] */
47486 {
47487 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24,
47488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47489 },
47490 /* btst${S} ${BitBase16-8-u11-S}[sb] */
47491 {
47492 M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16,
47493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47494 },
47495 /* btst${G} ${Dsp-16-u16}[$Bit16An] */
47496 {
47497 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32,
47498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47499 },
47500 /* btst${G} ${BitBase16-16-u16}[sb] */
47501 {
47502 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32,
47503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47504 },
47505 /* btst${G} ${BitBase16-16-u16} */
47506 {
47507 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32,
47508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47509 },
47510 /* btst${G} [$Bit16An] */
47511 {
47512 M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16,
47513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47514 },
47515 /* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47516 {
47517 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16,
47518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47519 },
47520 /* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47521 {
47522 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16,
47523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47524 },
47525 /* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47526 {
47527 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16,
47528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47529 },
47530 /* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47531 {
47532 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24,
47533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47534 },
47535 /* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47536 {
47537 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32,
47538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47539 },
47540 /* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47541 {
47542 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40,
47543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47544 },
47545 /* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47546 {
47547 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24,
47548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47549 },
47550 /* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47551 {
47552 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32,
47553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47554 },
47555 /* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47556 {
47557 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24,
47558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47559 },
47560 /* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47561 {
47562 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32,
47563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47564 },
47565 /* bset${X} ${BitBase32-16-u19-Unprefixed} */
47566 {
47567 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32,
47568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47569 },
47570 /* bset${X} ${BitBase32-16-u27-Unprefixed} */
47571 {
47572 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40,
47573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47574 },
47575 /* bset${G} $Bitno16R,$Bit16Rn */
47576 {
47577 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24,
47578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47579 },
47580 /* bset${G} $Bitno16R,$Bit16An */
47581 {
47582 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24,
47583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47584 },
47585 /* bset${G} ${Dsp-16-u8}[$Bit16An] */
47586 {
47587 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24,
47588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47589 },
47590 /* bset${G} ${BitBase16-16-u8}[sb] */
47591 {
47592 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24,
47593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47594 },
47595 /* bset${G} ${BitBase16-16-s8}[fb] */
47596 {
47597 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24,
47598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47599 },
47600 /* bset${S} ${BitBase16-8-u11-S}[sb] */
47601 {
47602 M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16,
47603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47604 },
47605 /* bset${G} ${Dsp-16-u16}[$Bit16An] */
47606 {
47607 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32,
47608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47609 },
47610 /* bset${G} ${BitBase16-16-u16}[sb] */
47611 {
47612 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32,
47613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47614 },
47615 /* bset${G} ${BitBase16-16-u16} */
47616 {
47617 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32,
47618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47619 },
47620 /* bset${G} [$Bit16An] */
47621 {
47622 M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16,
47623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47624 },
47625 /* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47626 {
47627 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24,
47628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47629 },
47630 /* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47631 {
47632 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24,
47633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47634 },
47635 /* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47636 {
47637 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24,
47638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47639 },
47640 /* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47641 {
47642 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32,
47643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47644 },
47645 /* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47646 {
47647 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40,
47648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47649 },
47650 /* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47651 {
47652 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48,
47653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47654 },
47655 /* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47656 {
47657 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32,
47658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47659 },
47660 /* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47661 {
47662 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40,
47663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47664 },
47665 /* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47666 {
47667 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32,
47668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47669 },
47670 /* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47671 {
47672 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40,
47673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47674 },
47675 /* bor${X} ${BitBase32-24-u19-Prefixed} */
47676 {
47677 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40,
47678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47679 },
47680 /* bor${X} ${BitBase32-24-u27-Prefixed} */
47681 {
47682 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48,
47683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47684 },
47685 /* bor${X} $Bitno16R,$Bit16Rn */
47686 {
47687 M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24,
47688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47689 },
47690 /* bor${X} $Bitno16R,$Bit16An */
47691 {
47692 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24,
47693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47694 },
47695 /* bor${X} [$Bit16An] */
47696 {
47697 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16,
47698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47699 },
47700 /* bor${X} ${Dsp-16-u8}[$Bit16An] */
47701 {
47702 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24,
47703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47704 },
47705 /* bor${X} ${Dsp-16-u16}[$Bit16An] */
47706 {
47707 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32,
47708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47709 },
47710 /* bor${X} ${BitBase16-16-u8}[sb] */
47711 {
47712 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24,
47713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47714 },
47715 /* bor${X} ${BitBase16-16-u16}[sb] */
47716 {
47717 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32,
47718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47719 },
47720 /* bor${X} ${BitBase16-16-s8}[fb] */
47721 {
47722 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24,
47723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47724 },
47725 /* bor${X} ${BitBase16-16-u16} */
47726 {
47727 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32,
47728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47729 },
47730 /* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47731 {
47732 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24,
47733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47734 },
47735 /* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47736 {
47737 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24,
47738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47739 },
47740 /* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47741 {
47742 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24,
47743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47744 },
47745 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47746 {
47747 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32,
47748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47749 },
47750 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47751 {
47752 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40,
47753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47754 },
47755 /* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47756 {
47757 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48,
47758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47759 },
47760 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47761 {
47762 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32,
47763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47764 },
47765 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47766 {
47767 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40,
47768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47769 },
47770 /* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47771 {
47772 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32,
47773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47774 },
47775 /* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47776 {
47777 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40,
47778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47779 },
47780 /* bnxor${X} ${BitBase32-24-u19-Prefixed} */
47781 {
47782 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40,
47783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47784 },
47785 /* bnxor${X} ${BitBase32-24-u27-Prefixed} */
47786 {
47787 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48,
47788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47789 },
47790 /* bnxor${X} $Bitno16R,$Bit16Rn */
47791 {
47792 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24,
47793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47794 },
47795 /* bnxor${X} $Bitno16R,$Bit16An */
47796 {
47797 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24,
47798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47799 },
47800 /* bnxor${X} [$Bit16An] */
47801 {
47802 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16,
47803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47804 },
47805 /* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
47806 {
47807 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24,
47808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47809 },
47810 /* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
47811 {
47812 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32,
47813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47814 },
47815 /* bnxor${X} ${BitBase16-16-u8}[sb] */
47816 {
47817 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24,
47818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47819 },
47820 /* bnxor${X} ${BitBase16-16-u16}[sb] */
47821 {
47822 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32,
47823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47824 },
47825 /* bnxor${X} ${BitBase16-16-s8}[fb] */
47826 {
47827 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24,
47828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47829 },
47830 /* bnxor${X} ${BitBase16-16-u16} */
47831 {
47832 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32,
47833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47834 },
47835 /* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47836 {
47837 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24,
47838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47839 },
47840 /* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47841 {
47842 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24,
47843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47844 },
47845 /* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47846 {
47847 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24,
47848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47849 },
47850 /* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47851 {
47852 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32,
47853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47854 },
47855 /* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47856 {
47857 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40,
47858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47859 },
47860 /* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47861 {
47862 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48,
47863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47864 },
47865 /* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
47866 {
47867 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32,
47868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47869 },
47870 /* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
47871 {
47872 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40,
47873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47874 },
47875 /* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
47876 {
47877 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32,
47878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47879 },
47880 /* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
47881 {
47882 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40,
47883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47884 },
47885 /* bntst${X} ${BitBase32-24-u19-Prefixed} */
47886 {
47887 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40,
47888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47889 },
47890 /* bntst${X} ${BitBase32-24-u27-Prefixed} */
47891 {
47892 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48,
47893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47894 },
47895 /* bntst${X} $Bitno16R,$Bit16Rn */
47896 {
47897 M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24,
47898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47899 },
47900 /* bntst${X} $Bitno16R,$Bit16An */
47901 {
47902 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24,
47903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47904 },
47905 /* bntst${X} [$Bit16An] */
47906 {
47907 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16,
47908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47909 },
47910 /* bntst${X} ${Dsp-16-u8}[$Bit16An] */
47911 {
47912 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24,
47913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47914 },
47915 /* bntst${X} ${Dsp-16-u16}[$Bit16An] */
47916 {
47917 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32,
47918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47919 },
47920 /* bntst${X} ${BitBase16-16-u8}[sb] */
47921 {
47922 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24,
47923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47924 },
47925 /* bntst${X} ${BitBase16-16-u16}[sb] */
47926 {
47927 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32,
47928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47929 },
47930 /* bntst${X} ${BitBase16-16-s8}[fb] */
47931 {
47932 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24,
47933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47934 },
47935 /* bntst${X} ${BitBase16-16-u16} */
47936 {
47937 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32,
47938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47939 },
47940 /* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47941 {
47942 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16,
47943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47944 },
47945 /* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47946 {
47947 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16,
47948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47949 },
47950 /* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47951 {
47952 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16,
47953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47954 },
47955 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47956 {
47957 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24,
47958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47959 },
47960 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47961 {
47962 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32,
47963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47964 },
47965 /* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47966 {
47967 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40,
47968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47969 },
47970 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47971 {
47972 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24,
47973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47974 },
47975 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47976 {
47977 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32,
47978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47979 },
47980 /* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47981 {
47982 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24,
47983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47984 },
47985 /* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47986 {
47987 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32,
47988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47989 },
47990 /* bnot${X} ${BitBase32-16-u19-Unprefixed} */
47991 {
47992 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32,
47993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47994 },
47995 /* bnot${X} ${BitBase32-16-u27-Unprefixed} */
47996 {
47997 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40,
47998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47999 },
48000 /* bnot${G} $Bitno16R,$Bit16Rn */
48001 {
48002 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24,
48003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48004 },
48005 /* bnot${G} $Bitno16R,$Bit16An */
48006 {
48007 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24,
48008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48009 },
48010 /* bnot${G} ${Dsp-16-u8}[$Bit16An] */
48011 {
48012 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24,
48013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48014 },
48015 /* bnot${G} ${BitBase16-16-u8}[sb] */
48016 {
48017 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24,
48018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48019 },
48020 /* bnot${G} ${BitBase16-16-s8}[fb] */
48021 {
48022 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24,
48023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48024 },
48025 /* bnot${S} ${BitBase16-8-u11-S}[sb] */
48026 {
48027 M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16,
48028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48029 },
48030 /* bnot${G} ${Dsp-16-u16}[$Bit16An] */
48031 {
48032 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32,
48033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48034 },
48035 /* bnot${G} ${BitBase16-16-u16}[sb] */
48036 {
48037 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32,
48038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48039 },
48040 /* bnot${G} ${BitBase16-16-u16} */
48041 {
48042 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32,
48043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48044 },
48045 /* bnot${G} [$Bit16An] */
48046 {
48047 M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16,
48048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48049 },
48050 /* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48051 {
48052 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24,
48053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48054 },
48055 /* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48056 {
48057 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24,
48058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48059 },
48060 /* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48061 {
48062 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24,
48063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48064 },
48065 /* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48066 {
48067 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32,
48068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48069 },
48070 /* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48071 {
48072 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40,
48073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48074 },
48075 /* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48076 {
48077 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48,
48078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48079 },
48080 /* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
48081 {
48082 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32,
48083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48084 },
48085 /* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
48086 {
48087 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40,
48088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48089 },
48090 /* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
48091 {
48092 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32,
48093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48094 },
48095 /* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
48096 {
48097 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40,
48098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48099 },
48100 /* bnor${X} ${BitBase32-24-u19-Prefixed} */
48101 {
48102 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40,
48103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48104 },
48105 /* bnor${X} ${BitBase32-24-u27-Prefixed} */
48106 {
48107 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48,
48108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48109 },
48110 /* bnor${X} $Bitno16R,$Bit16Rn */
48111 {
48112 M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24,
48113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48114 },
48115 /* bnor${X} $Bitno16R,$Bit16An */
48116 {
48117 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24,
48118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48119 },
48120 /* bnor${X} [$Bit16An] */
48121 {
48122 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16,
48123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48124 },
48125 /* bnor${X} ${Dsp-16-u8}[$Bit16An] */
48126 {
48127 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24,
48128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48129 },
48130 /* bnor${X} ${Dsp-16-u16}[$Bit16An] */
48131 {
48132 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32,
48133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48134 },
48135 /* bnor${X} ${BitBase16-16-u8}[sb] */
48136 {
48137 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24,
48138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48139 },
48140 /* bnor${X} ${BitBase16-16-u16}[sb] */
48141 {
48142 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32,
48143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48144 },
48145 /* bnor${X} ${BitBase16-16-s8}[fb] */
48146 {
48147 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24,
48148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48149 },
48150 /* bnor${X} ${BitBase16-16-u16} */
48151 {
48152 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32,
48153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48154 },
48155 /* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48156 {
48157 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24,
48158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48159 },
48160 /* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48161 {
48162 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24,
48163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48164 },
48165 /* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48166 {
48167 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24,
48168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48169 },
48170 /* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48171 {
48172 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32,
48173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48174 },
48175 /* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48176 {
48177 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40,
48178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48179 },
48180 /* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48181 {
48182 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48,
48183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48184 },
48185 /* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
48186 {
48187 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32,
48188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48189 },
48190 /* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
48191 {
48192 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40,
48193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48194 },
48195 /* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
48196 {
48197 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32,
48198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48199 },
48200 /* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
48201 {
48202 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40,
48203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48204 },
48205 /* bnand${X} ${BitBase32-24-u19-Prefixed} */
48206 {
48207 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40,
48208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48209 },
48210 /* bnand${X} ${BitBase32-24-u27-Prefixed} */
48211 {
48212 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48,
48213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48214 },
48215 /* bnand${X} $Bitno16R,$Bit16Rn */
48216 {
48217 M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24,
48218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48219 },
48220 /* bnand${X} $Bitno16R,$Bit16An */
48221 {
48222 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24,
48223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48224 },
48225 /* bnand${X} [$Bit16An] */
48226 {
48227 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16,
48228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48229 },
48230 /* bnand${X} ${Dsp-16-u8}[$Bit16An] */
48231 {
48232 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24,
48233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48234 },
48235 /* bnand${X} ${Dsp-16-u16}[$Bit16An] */
48236 {
48237 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32,
48238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48239 },
48240 /* bnand${X} ${BitBase16-16-u8}[sb] */
48241 {
48242 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24,
48243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48244 },
48245 /* bnand${X} ${BitBase16-16-u16}[sb] */
48246 {
48247 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32,
48248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48249 },
48250 /* bnand${X} ${BitBase16-16-s8}[fb] */
48251 {
48252 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24,
48253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48254 },
48255 /* bnand${X} ${BitBase16-16-u16} */
48256 {
48257 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32,
48258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48259 },
48260 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48261 {
48262 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24,
48263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48264 },
48265 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48266 {
48267 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24,
48268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48269 },
48270 /* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48271 {
48272 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24,
48273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48274 },
48275 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48276 {
48277 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32,
48278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48279 },
48280 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
48281 {
48282 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32,
48283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48284 },
48285 /* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
48286 {
48287 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32,
48288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48289 },
48290 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48291 {
48292 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40,
48293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48294 },
48295 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
48296 {
48297 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40,
48298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48299 },
48300 /* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
48301 {
48302 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40,
48303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48304 },
48305 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
48306 {
48307 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40,
48308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48309 },
48310 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48311 {
48312 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48,
48313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48314 },
48315 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
48316 {
48317 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48,
48318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48319 },
48320 /* bm${cond16-24} $Bitno16R,$Bit16Rn */
48321 {
48322 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32,
48323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48324 },
48325 /* bm${cond16-24} $Bitno16R,$Bit16An */
48326 {
48327 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32,
48328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48329 },
48330 /* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
48331 {
48332 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32,
48333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48334 },
48335 /* bm${cond16-24} ${BitBase16-16-u8}[sb] */
48336 {
48337 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32,
48338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48339 },
48340 /* bm${cond16-24} ${BitBase16-16-s8}[fb] */
48341 {
48342 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32,
48343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48344 },
48345 /* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
48346 {
48347 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40,
48348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48349 },
48350 /* bm${cond16-32} ${BitBase16-16-u16}[sb] */
48351 {
48352 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40,
48353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48354 },
48355 /* bm${cond16-32} ${BitBase16-16-u16} */
48356 {
48357 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40,
48358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48359 },
48360 /* bm${cond16-16} [$Bit16An] */
48361 {
48362 M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24,
48363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48364 },
48365 /* bitindex.w $Dst32RnUnprefixedHI */
48366 {
48367 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16,
48368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48369 },
48370 /* bitindex.w $Dst32AnUnprefixedHI */
48371 {
48372 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16,
48373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48374 },
48375 /* bitindex.w [$Dst32AnUnprefixed] */
48376 {
48377 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16,
48378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48379 },
48380 /* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48381 {
48382 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24,
48383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48384 },
48385 /* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48386 {
48387 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32,
48388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48389 },
48390 /* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48391 {
48392 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40,
48393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48394 },
48395 /* bitindex.w ${Dsp-16-u8}[sb] */
48396 {
48397 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24,
48398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48399 },
48400 /* bitindex.w ${Dsp-16-u16}[sb] */
48401 {
48402 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32,
48403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48404 },
48405 /* bitindex.w ${Dsp-16-s8}[fb] */
48406 {
48407 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24,
48408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48409 },
48410 /* bitindex.w ${Dsp-16-s16}[fb] */
48411 {
48412 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32,
48413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48414 },
48415 /* bitindex.w ${Dsp-16-u16} */
48416 {
48417 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32,
48418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48419 },
48420 /* bitindex.w ${Dsp-16-u24} */
48421 {
48422 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40,
48423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48424 },
48425 /* bitindex.b $Dst32RnUnprefixedQI */
48426 {
48427 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16,
48428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48429 },
48430 /* bitindex.b $Dst32AnUnprefixedQI */
48431 {
48432 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16,
48433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48434 },
48435 /* bitindex.b [$Dst32AnUnprefixed] */
48436 {
48437 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16,
48438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48439 },
48440 /* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48441 {
48442 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24,
48443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48444 },
48445 /* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48446 {
48447 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32,
48448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48449 },
48450 /* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48451 {
48452 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40,
48453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48454 },
48455 /* bitindex.b ${Dsp-16-u8}[sb] */
48456 {
48457 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24,
48458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48459 },
48460 /* bitindex.b ${Dsp-16-u16}[sb] */
48461 {
48462 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32,
48463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48464 },
48465 /* bitindex.b ${Dsp-16-s8}[fb] */
48466 {
48467 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24,
48468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48469 },
48470 /* bitindex.b ${Dsp-16-s16}[fb] */
48471 {
48472 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32,
48473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48474 },
48475 /* bitindex.b ${Dsp-16-u16} */
48476 {
48477 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32,
48478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48479 },
48480 /* bitindex.b ${Dsp-16-u24} */
48481 {
48482 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40,
48483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48484 },
48485 /* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48486 {
48487 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16,
48488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48489 },
48490 /* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48491 {
48492 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16,
48493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48494 },
48495 /* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48496 {
48497 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16,
48498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48499 },
48500 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48501 {
48502 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24,
48503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48504 },
48505 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48506 {
48507 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32,
48508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48509 },
48510 /* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48511 {
48512 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40,
48513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48514 },
48515 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
48516 {
48517 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24,
48518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48519 },
48520 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
48521 {
48522 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32,
48523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48524 },
48525 /* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
48526 {
48527 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24,
48528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48529 },
48530 /* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48531 {
48532 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32,
48533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48534 },
48535 /* bclr${X} ${BitBase32-16-u19-Unprefixed} */
48536 {
48537 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32,
48538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48539 },
48540 /* bclr${X} ${BitBase32-16-u27-Unprefixed} */
48541 {
48542 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40,
48543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48544 },
48545 /* bclr${G} $Bitno16R,$Bit16Rn */
48546 {
48547 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24,
48548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48549 },
48550 /* bclr${G} $Bitno16R,$Bit16An */
48551 {
48552 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24,
48553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48554 },
48555 /* bclr${G} ${Dsp-16-u8}[$Bit16An] */
48556 {
48557 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24,
48558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48559 },
48560 /* bclr${G} ${BitBase16-16-u8}[sb] */
48561 {
48562 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24,
48563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48564 },
48565 /* bclr${G} ${BitBase16-16-s8}[fb] */
48566 {
48567 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24,
48568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48569 },
48570 /* bclr${S} ${BitBase16-8-u11-S}[sb] */
48571 {
48572 M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16,
48573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48574 },
48575 /* bclr${G} ${Dsp-16-u16}[$Bit16An] */
48576 {
48577 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32,
48578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48579 },
48580 /* bclr${G} ${BitBase16-16-u16}[sb] */
48581 {
48582 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32,
48583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48584 },
48585 /* bclr${G} ${BitBase16-16-u16} */
48586 {
48587 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32,
48588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48589 },
48590 /* bclr${G} [$Bit16An] */
48591 {
48592 M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16,
48593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48594 },
48595 /* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48596 {
48597 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24,
48598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48599 },
48600 /* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48601 {
48602 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24,
48603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48604 },
48605 /* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48606 {
48607 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24,
48608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48609 },
48610 /* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48611 {
48612 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32,
48613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48614 },
48615 /* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48616 {
48617 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40,
48618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48619 },
48620 /* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48621 {
48622 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48,
48623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48624 },
48625 /* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
48626 {
48627 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32,
48628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48629 },
48630 /* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
48631 {
48632 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40,
48633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48634 },
48635 /* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
48636 {
48637 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32,
48638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48639 },
48640 /* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
48641 {
48642 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40,
48643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48644 },
48645 /* band${X} ${BitBase32-24-u19-Prefixed} */
48646 {
48647 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40,
48648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48649 },
48650 /* band${X} ${BitBase32-24-u27-Prefixed} */
48651 {
48652 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48,
48653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48654 },
48655 /* band${X} $Bitno16R,$Bit16Rn */
48656 {
48657 M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24,
48658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48659 },
48660 /* band${X} $Bitno16R,$Bit16An */
48661 {
48662 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24,
48663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48664 },
48665 /* band${X} [$Bit16An] */
48666 {
48667 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16,
48668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48669 },
48670 /* band${X} ${Dsp-16-u8}[$Bit16An] */
48671 {
48672 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24,
48673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48674 },
48675 /* band${X} ${Dsp-16-u16}[$Bit16An] */
48676 {
48677 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32,
48678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48679 },
48680 /* band${X} ${BitBase16-16-u8}[sb] */
48681 {
48682 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24,
48683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48684 },
48685 /* band${X} ${BitBase16-16-u16}[sb] */
48686 {
48687 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32,
48688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48689 },
48690 /* band${X} ${BitBase16-16-s8}[fb] */
48691 {
48692 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24,
48693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48694 },
48695 /* band${X} ${BitBase16-16-u16} */
48696 {
48697 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32,
48698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48699 },
48700 /* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48701 {
48702 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32,
48703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48704 },
48705 /* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48706 {
48707 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32,
48708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48709 },
48710 /* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48711 {
48712 M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40,
48713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48714 },
48715 /* and.w${S} #${Imm-8-HI},r0 */
48716 {
48717 M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24,
48718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48719 },
48720 /* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48721 {
48722 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24,
48723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48724 },
48725 /* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48726 {
48727 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24,
48728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48729 },
48730 /* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48731 {
48732 M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32,
48733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48734 },
48735 /* and.b${S} #${Imm-8-QI},r0l */
48736 {
48737 M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16,
48738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48739 },
48740 /* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
48741 {
48742 M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8,
48743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48744 },
48745 /* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
48746 {
48747 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16,
48748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48749 },
48750 /* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
48751 {
48752 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16,
48753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48754 },
48755 /* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
48756 {
48757 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24,
48758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48759 },
48760 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48761 {
48762 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48764 },
48765 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
48766 {
48767 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48769 },
48770 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
48771 {
48772 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48774 },
48775 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48776 {
48777 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48779 },
48780 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
48781 {
48782 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48784 },
48785 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
48786 {
48787 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48789 },
48790 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48791 {
48792 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48794 },
48795 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48796 {
48797 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48799 },
48800 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48801 {
48802 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48804 },
48805 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48806 {
48807 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48809 },
48810 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48811 {
48812 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48814 },
48815 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48816 {
48817 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48819 },
48820 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48821 {
48822 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48824 },
48825 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48826 {
48827 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48829 },
48830 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48831 {
48832 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48834 },
48835 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48836 {
48837 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48839 },
48840 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48841 {
48842 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48844 },
48845 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48846 {
48847 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48849 },
48850 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48851 {
48852 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48854 },
48855 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48856 {
48857 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48859 },
48860 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48861 {
48862 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48864 },
48865 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48866 {
48867 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48869 },
48870 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48871 {
48872 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48874 },
48875 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48876 {
48877 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48879 },
48880 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48881 {
48882 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48884 },
48885 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48886 {
48887 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48889 },
48890 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48891 {
48892 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48894 },
48895 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48896 {
48897 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48899 },
48900 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48901 {
48902 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48904 },
48905 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48906 {
48907 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48909 },
48910 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48911 {
48912 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48914 },
48915 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48916 {
48917 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48919 },
48920 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48921 {
48922 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48924 },
48925 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48926 {
48927 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48929 },
48930 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48931 {
48932 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48934 },
48935 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48936 {
48937 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48939 },
48940 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48941 {
48942 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48944 },
48945 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
48946 {
48947 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48949 },
48950 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
48951 {
48952 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48954 },
48955 /* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
48956 {
48957 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48959 },
48960 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48961 {
48962 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48964 },
48965 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
48966 {
48967 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48969 },
48970 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
48971 {
48972 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48974 },
48975 /* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
48976 {
48977 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48979 },
48980 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48981 {
48982 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48984 },
48985 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
48986 {
48987 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48989 },
48990 /* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
48991 {
48992 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48994 },
48995 /* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
48996 {
48997 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48999 },
49000 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49001 {
49002 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49004 },
49005 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49006 {
49007 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49009 },
49010 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49011 {
49012 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49014 },
49015 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49016 {
49017 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49019 },
49020 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49021 {
49022 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49024 },
49025 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49026 {
49027 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49029 },
49030 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49031 {
49032 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49034 },
49035 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49036 {
49037 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49039 },
49040 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49041 {
49042 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49044 },
49045 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49046 {
49047 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49049 },
49050 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49051 {
49052 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49054 },
49055 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49056 {
49057 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49059 },
49060 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49061 {
49062 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49064 },
49065 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49066 {
49067 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49069 },
49070 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49071 {
49072 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49074 },
49075 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49076 {
49077 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49079 },
49080 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49081 {
49082 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49084 },
49085 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49086 {
49087 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49089 },
49090 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49091 {
49092 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49094 },
49095 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49096 {
49097 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49099 },
49100 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49101 {
49102 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49104 },
49105 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49106 {
49107 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49109 },
49110 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49111 {
49112 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49114 },
49115 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49116 {
49117 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49119 },
49120 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49121 {
49122 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49124 },
49125 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49126 {
49127 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49129 },
49130 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49131 {
49132 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49134 },
49135 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49136 {
49137 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49139 },
49140 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49141 {
49142 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49144 },
49145 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49146 {
49147 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49149 },
49150 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49151 {
49152 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49154 },
49155 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
49156 {
49157 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49159 },
49160 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49161 {
49162 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49164 },
49165 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49166 {
49167 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49169 },
49170 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49171 {
49172 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49174 },
49175 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
49176 {
49177 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49179 },
49180 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49181 {
49182 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
49183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49184 },
49185 /* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
49186 {
49187 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
49188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49189 },
49190 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49191 {
49192 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
49193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49194 },
49195 /* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
49196 {
49197 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
49198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49199 },
49200 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49201 {
49202 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
49203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49204 },
49205 /* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49206 {
49207 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
49208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49209 },
49210 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49211 {
49212 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
49213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49214 },
49215 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49216 {
49217 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
49218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49219 },
49220 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49221 {
49222 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
49223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49224 },
49225 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49226 {
49227 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
49228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49229 },
49230 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49231 {
49232 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
49233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49234 },
49235 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49236 {
49237 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
49238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49239 },
49240 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49241 {
49242 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
49243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49244 },
49245 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49246 {
49247 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
49248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49249 },
49250 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49251 {
49252 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
49253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49254 },
49255 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49256 {
49257 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
49258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49259 },
49260 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49261 {
49262 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
49263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49264 },
49265 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49266 {
49267 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
49268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49269 },
49270 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49271 {
49272 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
49273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49274 },
49275 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49276 {
49277 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
49278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49279 },
49280 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49281 {
49282 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
49283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49284 },
49285 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
49286 {
49287 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
49288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49289 },
49290 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49291 {
49292 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
49293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49294 },
49295 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
49296 {
49297 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
49298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49299 },
49300 /* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
49301 {
49302 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49304 },
49305 /* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
49306 {
49307 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49309 },
49310 /* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49311 {
49312 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49314 },
49315 /* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
49316 {
49317 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49319 },
49320 /* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
49321 {
49322 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49324 },
49325 /* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49326 {
49327 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49329 },
49330 /* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
49331 {
49332 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49334 },
49335 /* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
49336 {
49337 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49339 },
49340 /* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49341 {
49342 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49344 },
49345 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49346 {
49347 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49349 },
49350 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49351 {
49352 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49354 },
49355 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49356 {
49357 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49359 },
49360 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49361 {
49362 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49364 },
49365 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49366 {
49367 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49369 },
49370 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49371 {
49372 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49374 },
49375 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49376 {
49377 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49379 },
49380 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49381 {
49382 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49384 },
49385 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49386 {
49387 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49389 },
49390 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49391 {
49392 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49394 },
49395 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49396 {
49397 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49399 },
49400 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49401 {
49402 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49404 },
49405 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49406 {
49407 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49409 },
49410 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49411 {
49412 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49414 },
49415 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49416 {
49417 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49419 },
49420 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49421 {
49422 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49424 },
49425 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49426 {
49427 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49429 },
49430 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49431 {
49432 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49434 },
49435 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49436 {
49437 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49439 },
49440 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49441 {
49442 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49444 },
49445 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49446 {
49447 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49449 },
49450 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49451 {
49452 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49454 },
49455 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49456 {
49457 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49459 },
49460 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49461 {
49462 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49464 },
49465 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49466 {
49467 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49469 },
49470 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49471 {
49472 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49474 },
49475 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49476 {
49477 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49479 },
49480 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49481 {
49482 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49484 },
49485 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49486 {
49487 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49489 },
49490 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49491 {
49492 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49494 },
49495 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49496 {
49497 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49499 },
49500 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49501 {
49502 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49504 },
49505 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49506 {
49507 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49509 },
49510 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49511 {
49512 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49514 },
49515 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49516 {
49517 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49519 },
49520 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49521 {
49522 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49524 },
49525 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49526 {
49527 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49529 },
49530 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49531 {
49532 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49534 },
49535 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49536 {
49537 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49539 },
49540 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49541 {
49542 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49544 },
49545 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49546 {
49547 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49549 },
49550 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49551 {
49552 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49554 },
49555 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49556 {
49557 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49559 },
49560 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49561 {
49562 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49564 },
49565 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49566 {
49567 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49569 },
49570 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49571 {
49572 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49574 },
49575 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49576 {
49577 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49579 },
49580 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49581 {
49582 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49584 },
49585 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49586 {
49587 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49589 },
49590 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49591 {
49592 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49594 },
49595 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49596 {
49597 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49599 },
49600 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49601 {
49602 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49604 },
49605 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49606 {
49607 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49609 },
49610 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49611 {
49612 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49614 },
49615 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49616 {
49617 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49619 },
49620 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49621 {
49622 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49624 },
49625 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49626 {
49627 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49629 },
49630 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49631 {
49632 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49634 },
49635 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49636 {
49637 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49639 },
49640 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49641 {
49642 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49644 },
49645 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49646 {
49647 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49649 },
49650 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49651 {
49652 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49654 },
49655 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49656 {
49657 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49659 },
49660 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49661 {
49662 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49664 },
49665 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
49666 {
49667 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49669 },
49670 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
49671 {
49672 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49674 },
49675 /* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
49676 {
49677 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49679 },
49680 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49681 {
49682 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49684 },
49685 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
49686 {
49687 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49689 },
49690 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
49691 {
49692 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49694 },
49695 /* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
49696 {
49697 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49699 },
49700 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49701 {
49702 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49704 },
49705 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49706 {
49707 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49709 },
49710 /* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49711 {
49712 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49714 },
49715 /* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49716 {
49717 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49719 },
49720 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49721 {
49722 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49724 },
49725 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49726 {
49727 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49729 },
49730 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49731 {
49732 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49734 },
49735 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49736 {
49737 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49739 },
49740 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49741 {
49742 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49744 },
49745 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49746 {
49747 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49749 },
49750 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49751 {
49752 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49754 },
49755 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49756 {
49757 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49759 },
49760 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49761 {
49762 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49764 },
49765 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49766 {
49767 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49769 },
49770 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49771 {
49772 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49774 },
49775 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49776 {
49777 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49779 },
49780 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49781 {
49782 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49784 },
49785 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49786 {
49787 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49789 },
49790 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49791 {
49792 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49794 },
49795 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49796 {
49797 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49799 },
49800 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49801 {
49802 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49804 },
49805 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49806 {
49807 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49809 },
49810 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49811 {
49812 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49814 },
49815 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49816 {
49817 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49819 },
49820 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49821 {
49822 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49824 },
49825 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49826 {
49827 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49829 },
49830 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49831 {
49832 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49834 },
49835 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49836 {
49837 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49839 },
49840 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49841 {
49842 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49844 },
49845 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49846 {
49847 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49849 },
49850 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49851 {
49852 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49854 },
49855 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49856 {
49857 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49859 },
49860 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49861 {
49862 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49864 },
49865 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49866 {
49867 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49869 },
49870 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49871 {
49872 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49874 },
49875 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
49876 {
49877 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49879 },
49880 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49881 {
49882 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49884 },
49885 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49886 {
49887 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49889 },
49890 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49891 {
49892 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49894 },
49895 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
49896 {
49897 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49899 },
49900 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49901 {
49902 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49904 },
49905 /* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
49906 {
49907 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49909 },
49910 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49911 {
49912 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49914 },
49915 /* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
49916 {
49917 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49919 },
49920 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49921 {
49922 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49924 },
49925 /* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49926 {
49927 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49929 },
49930 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49931 {
49932 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49934 },
49935 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49936 {
49937 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49939 },
49940 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49941 {
49942 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49944 },
49945 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49946 {
49947 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49949 },
49950 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49951 {
49952 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49954 },
49955 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49956 {
49957 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49959 },
49960 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49961 {
49962 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
49963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49964 },
49965 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49966 {
49967 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
49968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49969 },
49970 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49971 {
49972 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
49973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49974 },
49975 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49976 {
49977 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
49978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49979 },
49980 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49981 {
49982 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
49983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49984 },
49985 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49986 {
49987 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
49988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49989 },
49990 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49991 {
49992 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
49993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49994 },
49995 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49996 {
49997 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
49998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49999 },
50000 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
50001 {
50002 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
50003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50004 },
50005 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
50006 {
50007 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
50008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50009 },
50010 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
50011 {
50012 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
50013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50014 },
50015 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
50016 {
50017 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
50018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50019 },
50020 /* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
50021 {
50022 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50024 },
50025 /* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
50026 {
50027 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50029 },
50030 /* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50031 {
50032 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50034 },
50035 /* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
50036 {
50037 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50039 },
50040 /* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
50041 {
50042 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50044 },
50045 /* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50046 {
50047 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50049 },
50050 /* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
50051 {
50052 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50054 },
50055 /* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
50056 {
50057 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50059 },
50060 /* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50061 {
50062 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50064 },
50065 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50066 {
50067 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50069 },
50070 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50071 {
50072 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50074 },
50075 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
50076 {
50077 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50079 },
50080 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50081 {
50082 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50084 },
50085 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50086 {
50087 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50089 },
50090 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
50091 {
50092 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50094 },
50095 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50096 {
50097 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50099 },
50100 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50101 {
50102 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50104 },
50105 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
50106 {
50107 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50109 },
50110 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
50111 {
50112 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50114 },
50115 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
50116 {
50117 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50119 },
50120 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
50121 {
50122 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50124 },
50125 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
50126 {
50127 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50129 },
50130 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
50131 {
50132 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50134 },
50135 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
50136 {
50137 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50139 },
50140 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
50141 {
50142 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50144 },
50145 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
50146 {
50147 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50149 },
50150 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
50151 {
50152 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50154 },
50155 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
50156 {
50157 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50159 },
50160 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
50161 {
50162 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50164 },
50165 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
50166 {
50167 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50169 },
50170 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
50171 {
50172 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50174 },
50175 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
50176 {
50177 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50179 },
50180 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
50181 {
50182 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50184 },
50185 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
50186 {
50187 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50189 },
50190 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
50191 {
50192 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50194 },
50195 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
50196 {
50197 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50199 },
50200 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
50201 {
50202 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50204 },
50205 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
50206 {
50207 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50209 },
50210 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
50211 {
50212 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50214 },
50215 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
50216 {
50217 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24,
50218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50219 },
50220 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
50221 {
50222 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24,
50223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50224 },
50225 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
50226 {
50227 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24,
50228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50229 },
50230 /* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50231 {
50232 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50234 },
50235 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50236 {
50237 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50239 },
50240 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50241 {
50242 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50244 },
50245 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50246 {
50247 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50249 },
50250 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50251 {
50252 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50254 },
50255 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50256 {
50257 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50259 },
50260 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50261 {
50262 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50264 },
50265 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50266 {
50267 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50269 },
50270 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50271 {
50272 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50274 },
50275 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50276 {
50277 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50279 },
50280 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50281 {
50282 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50284 },
50285 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50286 {
50287 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50289 },
50290 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50291 {
50292 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50294 },
50295 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50296 {
50297 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50299 },
50300 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50301 {
50302 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50304 },
50305 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50306 {
50307 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50309 },
50310 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50311 {
50312 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50314 },
50315 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50316 {
50317 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50319 },
50320 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50321 {
50322 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50324 },
50325 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50326 {
50327 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50329 },
50330 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50331 {
50332 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50334 },
50335 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
50336 {
50337 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
50338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50339 },
50340 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
50341 {
50342 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
50343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50344 },
50345 /* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
50346 {
50347 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32,
50348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50349 },
50350 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
50351 {
50352 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32,
50353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50354 },
50355 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
50356 {
50357 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32,
50358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50359 },
50360 /* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
50361 {
50362 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32,
50363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50364 },
50365 /* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50366 {
50367 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32,
50368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50369 },
50370 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50371 {
50372 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32,
50373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50374 },
50375 /* and.w${G} ${Dsp-16-u16},[$Dst16An] */
50376 {
50377 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32,
50378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50379 },
50380 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50381 {
50382 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50384 },
50385 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50386 {
50387 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50389 },
50390 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50391 {
50392 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50394 },
50395 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50396 {
50397 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50399 },
50400 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50401 {
50402 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50404 },
50405 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50406 {
50407 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50409 },
50410 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50411 {
50412 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50414 },
50415 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50416 {
50417 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50419 },
50420 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50421 {
50422 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50424 },
50425 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50426 {
50427 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50429 },
50430 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50431 {
50432 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50434 },
50435 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50436 {
50437 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50439 },
50440 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50441 {
50442 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50444 },
50445 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50446 {
50447 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50449 },
50450 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50451 {
50452 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50454 },
50455 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50456 {
50457 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50459 },
50460 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50461 {
50462 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50464 },
50465 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
50466 {
50467 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48,
50468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50469 },
50470 /* and.w${G} $Src16RnHI,$Dst16RnHI */
50471 {
50472 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50474 },
50475 /* and.w${G} $Src16AnHI,$Dst16RnHI */
50476 {
50477 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50479 },
50480 /* and.w${G} [$Src16An],$Dst16RnHI */
50481 {
50482 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16,
50483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50484 },
50485 /* and.w${G} $Src16RnHI,$Dst16AnHI */
50486 {
50487 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16,
50488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50489 },
50490 /* and.w${G} $Src16AnHI,$Dst16AnHI */
50491 {
50492 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16,
50493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50494 },
50495 /* and.w${G} [$Src16An],$Dst16AnHI */
50496 {
50497 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16,
50498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50499 },
50500 /* and.w${G} $Src16RnHI,[$Dst16An] */
50501 {
50502 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50504 },
50505 /* and.w${G} $Src16AnHI,[$Dst16An] */
50506 {
50507 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50509 },
50510 /* and.w${G} [$Src16An],[$Dst16An] */
50511 {
50512 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16,
50513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50514 },
50515 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
50516 {
50517 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50519 },
50520 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
50521 {
50522 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50524 },
50525 /* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50526 {
50527 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50529 },
50530 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
50531 {
50532 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50534 },
50535 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
50536 {
50537 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50539 },
50540 /* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50541 {
50542 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50544 },
50545 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
50546 {
50547 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50549 },
50550 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
50551 {
50552 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50554 },
50555 /* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
50556 {
50557 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50559 },
50560 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
50561 {
50562 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50564 },
50565 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
50566 {
50567 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50569 },
50570 /* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
50571 {
50572 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50574 },
50575 /* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
50576 {
50577 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50579 },
50580 /* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
50581 {
50582 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50584 },
50585 /* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
50586 {
50587 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50589 },
50590 /* and.w${G} $Src16RnHI,${Dsp-16-u16} */
50591 {
50592 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50594 },
50595 /* and.w${G} $Src16AnHI,${Dsp-16-u16} */
50596 {
50597 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50599 },
50600 /* and.w${G} [$Src16An],${Dsp-16-u16} */
50601 {
50602 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32,
50603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50604 },
50605 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
50606 {
50607 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50609 },
50610 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
50611 {
50612 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50614 },
50615 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
50616 {
50617 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50619 },
50620 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
50621 {
50622 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24,
50623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50624 },
50625 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
50626 {
50627 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50629 },
50630 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
50631 {
50632 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50634 },
50635 /* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50636 {
50637 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50639 },
50640 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50641 {
50642 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50644 },
50645 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50646 {
50647 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50649 },
50650 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50651 {
50652 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50654 },
50655 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50656 {
50657 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50659 },
50660 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50661 {
50662 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50664 },
50665 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50666 {
50667 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50669 },
50670 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50671 {
50672 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50674 },
50675 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50676 {
50677 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50679 },
50680 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50681 {
50682 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50684 },
50685 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50686 {
50687 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50689 },
50690 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50691 {
50692 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50694 },
50695 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50696 {
50697 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50699 },
50700 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50701 {
50702 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50704 },
50705 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50706 {
50707 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50709 },
50710 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50711 {
50712 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50714 },
50715 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50716 {
50717 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50719 },
50720 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50721 {
50722 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50724 },
50725 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50726 {
50727 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50729 },
50730 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50731 {
50732 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50734 },
50735 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50736 {
50737 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50739 },
50740 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
50741 {
50742 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50744 },
50745 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
50746 {
50747 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50749 },
50750 /* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
50751 {
50752 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32,
50753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50754 },
50755 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
50756 {
50757 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32,
50758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50759 },
50760 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
50761 {
50762 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32,
50763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50764 },
50765 /* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
50766 {
50767 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32,
50768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50769 },
50770 /* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50771 {
50772 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50774 },
50775 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50776 {
50777 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50779 },
50780 /* and.b${G} ${Dsp-16-u16},[$Dst16An] */
50781 {
50782 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32,
50783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50784 },
50785 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50786 {
50787 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50789 },
50790 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50791 {
50792 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50794 },
50795 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50796 {
50797 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50799 },
50800 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50801 {
50802 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50804 },
50805 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50806 {
50807 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50809 },
50810 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50811 {
50812 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50814 },
50815 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50816 {
50817 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50819 },
50820 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50821 {
50822 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50824 },
50825 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50826 {
50827 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50829 },
50830 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50831 {
50832 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50834 },
50835 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50836 {
50837 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50839 },
50840 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50841 {
50842 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50844 },
50845 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50846 {
50847 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50849 },
50850 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50851 {
50852 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50854 },
50855 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50856 {
50857 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50859 },
50860 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50861 {
50862 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50864 },
50865 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50866 {
50867 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50869 },
50870 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
50871 {
50872 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48,
50873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50874 },
50875 /* and.b${G} $Src16RnQI,$Dst16RnQI */
50876 {
50877 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50879 },
50880 /* and.b${G} $Src16AnQI,$Dst16RnQI */
50881 {
50882 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50884 },
50885 /* and.b${G} [$Src16An],$Dst16RnQI */
50886 {
50887 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16,
50888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50889 },
50890 /* and.b${G} $Src16RnQI,$Dst16AnQI */
50891 {
50892 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16,
50893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50894 },
50895 /* and.b${G} $Src16AnQI,$Dst16AnQI */
50896 {
50897 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16,
50898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50899 },
50900 /* and.b${G} [$Src16An],$Dst16AnQI */
50901 {
50902 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16,
50903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50904 },
50905 /* and.b${G} $Src16RnQI,[$Dst16An] */
50906 {
50907 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50909 },
50910 /* and.b${G} $Src16AnQI,[$Dst16An] */
50911 {
50912 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50914 },
50915 /* and.b${G} [$Src16An],[$Dst16An] */
50916 {
50917 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16,
50918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50919 },
50920 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
50921 {
50922 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50924 },
50925 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
50926 {
50927 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50929 },
50930 /* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50931 {
50932 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50934 },
50935 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
50936 {
50937 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50939 },
50940 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
50941 {
50942 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50944 },
50945 /* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50946 {
50947 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50949 },
50950 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
50951 {
50952 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50954 },
50955 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
50956 {
50957 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50959 },
50960 /* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
50961 {
50962 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50964 },
50965 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
50966 {
50967 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50969 },
50970 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
50971 {
50972 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50974 },
50975 /* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
50976 {
50977 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50979 },
50980 /* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
50981 {
50982 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
50983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50984 },
50985 /* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
50986 {
50987 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
50988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50989 },
50990 /* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
50991 {
50992 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
50993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50994 },
50995 /* and.b${G} $Src16RnQI,${Dsp-16-u16} */
50996 {
50997 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
50998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50999 },
51000 /* and.b${G} $Src16AnQI,${Dsp-16-u16} */
51001 {
51002 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
51003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51004 },
51005 /* and.b${G} [$Src16An],${Dsp-16-u16} */
51006 {
51007 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32,
51008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51009 },
51010 /* and.b${S} #${Imm-8-QI},r0l */
51011 {
51012 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16,
51013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51014 },
51015 /* and.b${S} #${Imm-8-QI},r0h */
51016 {
51017 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16,
51018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51019 },
51020 /* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
51021 {
51022 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24,
51023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51024 },
51025 /* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
51026 {
51027 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24,
51028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51029 },
51030 /* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
51031 {
51032 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32,
51033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51034 },
51035 /* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
51036 {
51037 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
51038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51039 },
51040 /* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
51041 {
51042 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32,
51043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51044 },
51045 /* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
51046 {
51047 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
51048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51049 },
51050 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51051 {
51052 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40,
51053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51054 },
51055 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51056 {
51057 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40,
51058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51059 },
51060 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51061 {
51062 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40,
51063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51064 },
51065 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51066 {
51067 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48,
51068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51069 },
51070 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51071 {
51072 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48,
51073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51074 },
51075 /* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
51076 {
51077 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48,
51078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51079 },
51080 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51081 {
51082 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48,
51083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51084 },
51085 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51086 {
51087 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56,
51088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51089 },
51090 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
51091 {
51092 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56,
51093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51094 },
51095 /* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
51096 {
51097 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
51098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51099 },
51100 /* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
51101 {
51102 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24,
51103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51104 },
51105 /* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51106 {
51107 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
51108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51109 },
51110 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51111 {
51112 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32,
51113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51114 },
51115 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51116 {
51117 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32,
51118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51119 },
51120 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51121 {
51122 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32,
51123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51124 },
51125 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51126 {
51127 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40,
51128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51129 },
51130 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51131 {
51132 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40,
51133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51134 },
51135 /* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51136 {
51137 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40,
51138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51139 },
51140 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51141 {
51142 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40,
51143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51144 },
51145 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51146 {
51147 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48,
51148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51149 },
51150 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
51151 {
51152 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48,
51153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51154 },
51155 /* and.w${G} #${Imm-16-HI},$Dst16RnHI */
51156 {
51157 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32,
51158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51159 },
51160 /* and.w${G} #${Imm-16-HI},$Dst16AnHI */
51161 {
51162 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32,
51163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51164 },
51165 /* and.w${G} #${Imm-16-HI},[$Dst16An] */
51166 {
51167 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32,
51168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51169 },
51170 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
51171 {
51172 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40,
51173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51174 },
51175 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51176 {
51177 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40,
51178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51179 },
51180 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51181 {
51182 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40,
51183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51184 },
51185 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
51186 {
51187 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48,
51188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51189 },
51190 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51191 {
51192 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48,
51193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51194 },
51195 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51196 {
51197 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48,
51198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51199 },
51200 /* and.b${G} #${Imm-16-QI},$Dst16RnQI */
51201 {
51202 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24,
51203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51204 },
51205 /* and.b${G} #${Imm-16-QI},$Dst16AnQI */
51206 {
51207 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24,
51208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51209 },
51210 /* and.b${G} #${Imm-16-QI},[$Dst16An] */
51211 {
51212 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24,
51213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51214 },
51215 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
51216 {
51217 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32,
51218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51219 },
51220 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51221 {
51222 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32,
51223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51224 },
51225 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51226 {
51227 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32,
51228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51229 },
51230 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
51231 {
51232 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40,
51233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51234 },
51235 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51236 {
51237 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40,
51238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51239 },
51240 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51241 {
51242 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40,
51243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51244 },
51245 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51246 {
51247 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32,
51248 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51249 },
51250 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51251 {
51252 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32,
51253 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51254 },
51255 /* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51256 {
51257 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32,
51258 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51259 },
51260 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51261 {
51262 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40,
51263 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51264 },
51265 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51266 {
51267 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40,
51268 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51269 },
51270 /* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51271 {
51272 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40,
51273 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51274 },
51275 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51276 {
51277 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40,
51278 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51279 },
51280 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51281 {
51282 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48,
51283 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51284 },
51285 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51286 {
51287 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48,
51288 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51289 },
51290 /* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
51291 {
51292 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24,
51293 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51294 },
51295 /* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
51296 {
51297 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24,
51298 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51299 },
51300 /* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51301 {
51302 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24,
51303 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51304 },
51305 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51306 {
51307 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32,
51308 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51309 },
51310 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51311 {
51312 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32,
51313 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51314 },
51315 /* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51316 {
51317 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32,
51318 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51319 },
51320 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51321 {
51322 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40,
51323 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51324 },
51325 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51326 {
51327 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40,
51328 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51329 },
51330 /* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51331 {
51332 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40,
51333 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51334 },
51335 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51336 {
51337 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40,
51338 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51339 },
51340 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51341 {
51342 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48,
51343 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51344 },
51345 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51346 {
51347 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48,
51348 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51349 },
51350 /* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
51351 {
51352 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24,
51353 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51354 },
51355 /* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
51356 {
51357 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24,
51358 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51359 },
51360 /* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51361 {
51362 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24,
51363 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51364 },
51365 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51366 {
51367 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32,
51368 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51369 },
51370 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51371 {
51372 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32,
51373 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51374 },
51375 /* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51376 {
51377 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32,
51378 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51379 },
51380 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51381 {
51382 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40,
51383 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51384 },
51385 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51386 {
51387 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40,
51388 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51389 },
51390 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51391 {
51392 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40,
51393 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51394 },
51395 /* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
51396 {
51397 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24,
51398 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51399 },
51400 /* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
51401 {
51402 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24,
51403 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51404 },
51405 /* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51406 {
51407 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24,
51408 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51409 },
51410 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51411 {
51412 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32,
51413 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51414 },
51415 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51416 {
51417 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32,
51418 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51419 },
51420 /* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51421 {
51422 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32,
51423 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51424 },
51425 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51426 {
51427 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40,
51428 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51429 },
51430 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51431 {
51432 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40,
51433 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51434 },
51435 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51436 {
51437 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40,
51438 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51439 },
51440 /* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
51441 {
51442 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24,
51443 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51444 },
51445 /* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
51446 {
51447 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24,
51448 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51449 },
51450 /* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51451 {
51452 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24,
51453 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51454 },
51455 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51456 {
51457 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51459 },
51460 /* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
51461 {
51462 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51464 },
51465 /* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
51466 {
51467 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51469 },
51470 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51471 {
51472 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51474 },
51475 /* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
51476 {
51477 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51479 },
51480 /* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
51481 {
51482 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51484 },
51485 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51486 {
51487 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51489 },
51490 /* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
51491 {
51492 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51494 },
51495 /* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
51496 {
51497 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51499 },
51500 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51501 {
51502 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51504 },
51505 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51506 {
51507 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51509 },
51510 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51511 {
51512 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51514 },
51515 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51516 {
51517 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51519 },
51520 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51521 {
51522 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51524 },
51525 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51526 {
51527 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51529 },
51530 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51531 {
51532 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51534 },
51535 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51536 {
51537 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51539 },
51540 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51541 {
51542 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51544 },
51545 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
51546 {
51547 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51549 },
51550 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
51551 {
51552 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51554 },
51555 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
51556 {
51557 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51559 },
51560 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
51561 {
51562 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51564 },
51565 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
51566 {
51567 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51569 },
51570 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
51571 {
51572 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51574 },
51575 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
51576 {
51577 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51579 },
51580 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
51581 {
51582 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51584 },
51585 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51586 {
51587 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51589 },
51590 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
51591 {
51592 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51594 },
51595 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
51596 {
51597 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51599 },
51600 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
51601 {
51602 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51604 },
51605 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
51606 {
51607 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51609 },
51610 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51611 {
51612 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51614 },
51615 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51616 {
51617 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51619 },
51620 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
51621 {
51622 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51624 },
51625 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
51626 {
51627 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51629 },
51630 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
51631 {
51632 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51634 },
51635 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51636 {
51637 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51639 },
51640 /* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
51641 {
51642 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51644 },
51645 /* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
51646 {
51647 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51649 },
51650 /* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
51651 {
51652 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51654 },
51655 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51656 {
51657 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51659 },
51660 /* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
51661 {
51662 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51664 },
51665 /* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
51666 {
51667 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51669 },
51670 /* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
51671 {
51672 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51674 },
51675 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51676 {
51677 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51679 },
51680 /* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
51681 {
51682 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51684 },
51685 /* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
51686 {
51687 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51689 },
51690 /* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
51691 {
51692 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51694 },
51695 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51696 {
51697 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51699 },
51700 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51701 {
51702 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51704 },
51705 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51706 {
51707 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51709 },
51710 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
51711 {
51712 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51714 },
51715 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51716 {
51717 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51719 },
51720 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51721 {
51722 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51724 },
51725 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51726 {
51727 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51729 },
51730 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
51731 {
51732 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51734 },
51735 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51736 {
51737 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51739 },
51740 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51741 {
51742 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51744 },
51745 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51746 {
51747 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51749 },
51750 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
51751 {
51752 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51754 },
51755 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
51756 {
51757 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51759 },
51760 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51761 {
51762 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51764 },
51765 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
51766 {
51767 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51769 },
51770 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51771 {
51772 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51774 },
51775 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
51776 {
51777 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51779 },
51780 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51781 {
51782 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51784 },
51785 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
51786 {
51787 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51789 },
51790 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51791 {
51792 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51794 },
51795 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
51796 {
51797 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51799 },
51800 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51801 {
51802 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51804 },
51805 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
51806 {
51807 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51809 },
51810 /* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51811 {
51812 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51814 },
51815 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
51816 {
51817 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51819 },
51820 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
51821 {
51822 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51824 },
51825 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
51826 {
51827 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51829 },
51830 /* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
51831 {
51832 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51834 },
51835 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
51836 {
51837 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51839 },
51840 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51841 {
51842 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51844 },
51845 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
51846 {
51847 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51849 },
51850 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
51851 {
51852 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51854 },
51855 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
51856 {
51857 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51859 },
51860 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
51861 {
51862 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51864 },
51865 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
51866 {
51867 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51869 },
51870 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
51871 {
51872 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51874 },
51875 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51876 {
51877 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51879 },
51880 /* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
51881 {
51882 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51884 },
51885 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51886 {
51887 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51889 },
51890 /* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
51891 {
51892 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51894 },
51895 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51896 {
51897 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51899 },
51900 /* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
51901 {
51902 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51904 },
51905 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
51906 {
51907 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51909 },
51910 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
51911 {
51912 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51914 },
51915 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
51916 {
51917 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51919 },
51920 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
51921 {
51922 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51924 },
51925 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
51926 {
51927 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51929 },
51930 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
51931 {
51932 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51934 },
51935 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
51936 {
51937 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51939 },
51940 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
51941 {
51942 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51944 },
51945 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
51946 {
51947 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51949 },
51950 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
51951 {
51952 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51954 },
51955 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
51956 {
51957 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51959 },
51960 /* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
51961 {
51962 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51964 },
51965 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
51966 {
51967 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
51968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51969 },
51970 /* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
51971 {
51972 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
51973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51974 },
51975 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
51976 {
51977 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
51978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51979 },
51980 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
51981 {
51982 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
51983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51984 },
51985 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
51986 {
51987 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
51988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51989 },
51990 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
51991 {
51992 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
51993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51994 },
51995 /* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
51996 {
51997 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
51998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51999 },
52000 /* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
52001 {
52002 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52004 },
52005 /* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
52006 {
52007 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52009 },
52010 /* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
52011 {
52012 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52014 },
52015 /* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
52016 {
52017 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52019 },
52020 /* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
52021 {
52022 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52024 },
52025 /* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
52026 {
52027 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52029 },
52030 /* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
52031 {
52032 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52034 },
52035 /* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
52036 {
52037 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52039 },
52040 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52041 {
52042 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52044 },
52045 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52046 {
52047 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52049 },
52050 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
52051 {
52052 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52054 },
52055 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52056 {
52057 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52059 },
52060 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52061 {
52062 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52064 },
52065 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
52066 {
52067 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52069 },
52070 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52071 {
52072 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52074 },
52075 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52076 {
52077 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52079 },
52080 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
52081 {
52082 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52084 },
52085 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
52086 {
52087 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52089 },
52090 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
52091 {
52092 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52094 },
52095 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
52096 {
52097 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52099 },
52100 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
52101 {
52102 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52104 },
52105 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
52106 {
52107 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52109 },
52110 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
52111 {
52112 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52114 },
52115 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
52116 {
52117 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52119 },
52120 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
52121 {
52122 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52124 },
52125 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
52126 {
52127 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52129 },
52130 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
52131 {
52132 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52134 },
52135 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
52136 {
52137 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52139 },
52140 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
52141 {
52142 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52144 },
52145 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
52146 {
52147 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52149 },
52150 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
52151 {
52152 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52154 },
52155 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
52156 {
52157 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52159 },
52160 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
52161 {
52162 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52164 },
52165 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
52166 {
52167 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52169 },
52170 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
52171 {
52172 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52174 },
52175 /* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
52176 {
52177 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
52178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52179 },
52180 /* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
52181 {
52182 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24,
52183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52184 },
52185 /* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
52186 {
52187 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24,
52188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52189 },
52190 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
52191 {
52192 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32,
52193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52194 },
52195 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
52196 {
52197 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32,
52198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52199 },
52200 /* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
52201 {
52202 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32,
52203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52204 },
52205 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
52206 {
52207 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40,
52208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52209 },
52210 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
52211 {
52212 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40,
52213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52214 },
52215 /* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
52216 {
52217 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40,
52218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52219 },
52220 /* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
52221 {
52222 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40,
52223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52224 },
52225 /* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
52226 {
52227 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48,
52228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52229 },
52230 /* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
52231 {
52232 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48,
52233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52234 },
52235 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52236 {
52237 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52239 },
52240 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
52241 {
52242 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52244 },
52245 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
52246 {
52247 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52249 },
52250 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52251 {
52252 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52254 },
52255 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
52256 {
52257 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52259 },
52260 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
52261 {
52262 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52264 },
52265 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52266 {
52267 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52269 },
52270 /* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52271 {
52272 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52274 },
52275 /* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52276 {
52277 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52279 },
52280 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52281 {
52282 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52284 },
52285 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52286 {
52287 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52289 },
52290 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52291 {
52292 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52294 },
52295 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52296 {
52297 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52299 },
52300 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52301 {
52302 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52304 },
52305 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52306 {
52307 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52309 },
52310 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52311 {
52312 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52314 },
52315 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52316 {
52317 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52319 },
52320 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52321 {
52322 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52324 },
52325 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52326 {
52327 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52329 },
52330 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52331 {
52332 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52334 },
52335 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52336 {
52337 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52339 },
52340 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52341 {
52342 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52344 },
52345 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52346 {
52347 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52349 },
52350 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52351 {
52352 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52354 },
52355 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52356 {
52357 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52359 },
52360 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52361 {
52362 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52364 },
52365 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52366 {
52367 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52369 },
52370 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52371 {
52372 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52374 },
52375 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52376 {
52377 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52379 },
52380 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52381 {
52382 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52384 },
52385 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52386 {
52387 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52389 },
52390 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52391 {
52392 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52394 },
52395 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52396 {
52397 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52399 },
52400 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52401 {
52402 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52404 },
52405 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52406 {
52407 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52409 },
52410 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52411 {
52412 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52414 },
52415 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52416 {
52417 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52419 },
52420 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
52421 {
52422 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52424 },
52425 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
52426 {
52427 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52429 },
52430 /* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
52431 {
52432 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52434 },
52435 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52436 {
52437 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52439 },
52440 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
52441 {
52442 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52444 },
52445 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
52446 {
52447 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52449 },
52450 /* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
52451 {
52452 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52454 },
52455 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52456 {
52457 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52459 },
52460 /* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52461 {
52462 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52464 },
52465 /* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52466 {
52467 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52469 },
52470 /* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52471 {
52472 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52474 },
52475 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52476 {
52477 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52479 },
52480 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52481 {
52482 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52484 },
52485 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52486 {
52487 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52489 },
52490 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52491 {
52492 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52494 },
52495 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52496 {
52497 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52499 },
52500 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52501 {
52502 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52504 },
52505 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52506 {
52507 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52509 },
52510 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52511 {
52512 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52514 },
52515 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52516 {
52517 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52519 },
52520 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52521 {
52522 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52524 },
52525 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52526 {
52527 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52529 },
52530 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52531 {
52532 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52534 },
52535 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52536 {
52537 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52539 },
52540 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52541 {
52542 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52544 },
52545 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52546 {
52547 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52549 },
52550 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52551 {
52552 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52554 },
52555 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52556 {
52557 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52559 },
52560 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52561 {
52562 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52564 },
52565 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52566 {
52567 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52569 },
52570 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52571 {
52572 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52574 },
52575 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52576 {
52577 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52579 },
52580 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52581 {
52582 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52584 },
52585 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52586 {
52587 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52589 },
52590 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52591 {
52592 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52594 },
52595 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52596 {
52597 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52599 },
52600 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52601 {
52602 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52604 },
52605 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52606 {
52607 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52609 },
52610 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52611 {
52612 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52614 },
52615 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52616 {
52617 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52619 },
52620 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52621 {
52622 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52624 },
52625 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52626 {
52627 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52629 },
52630 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52631 {
52632 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52634 },
52635 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52636 {
52637 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52639 },
52640 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52641 {
52642 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52644 },
52645 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52646 {
52647 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52649 },
52650 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52651 {
52652 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52654 },
52655 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52656 {
52657 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52659 },
52660 /* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52661 {
52662 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52664 },
52665 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52666 {
52667 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52669 },
52670 /* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52671 {
52672 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52674 },
52675 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52676 {
52677 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52679 },
52680 /* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52681 {
52682 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52684 },
52685 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52686 {
52687 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52689 },
52690 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52691 {
52692 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52694 },
52695 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52696 {
52697 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52699 },
52700 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52701 {
52702 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52704 },
52705 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52706 {
52707 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52709 },
52710 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52711 {
52712 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52714 },
52715 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52716 {
52717 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52719 },
52720 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52721 {
52722 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52724 },
52725 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52726 {
52727 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52729 },
52730 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52731 {
52732 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52734 },
52735 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52736 {
52737 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52739 },
52740 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52741 {
52742 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52744 },
52745 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52746 {
52747 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52749 },
52750 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52751 {
52752 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52754 },
52755 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52756 {
52757 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52759 },
52760 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52761 {
52762 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52764 },
52765 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52766 {
52767 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52769 },
52770 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52771 {
52772 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52774 },
52775 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52776 {
52777 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52779 },
52780 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52781 {
52782 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52784 },
52785 /* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52786 {
52787 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52789 },
52790 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52791 {
52792 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52794 },
52795 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52796 {
52797 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52799 },
52800 /* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52801 {
52802 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52804 },
52805 /* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52806 {
52807 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52809 },
52810 /* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52811 {
52812 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52814 },
52815 /* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52816 {
52817 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52819 },
52820 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52821 {
52822 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52824 },
52825 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52826 {
52827 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52829 },
52830 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52831 {
52832 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52834 },
52835 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52836 {
52837 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52839 },
52840 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52841 {
52842 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52844 },
52845 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52846 {
52847 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52849 },
52850 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52851 {
52852 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52854 },
52855 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52856 {
52857 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52859 },
52860 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52861 {
52862 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52864 },
52865 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52866 {
52867 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52869 },
52870 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52871 {
52872 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52874 },
52875 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52876 {
52877 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52879 },
52880 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52881 {
52882 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52884 },
52885 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52886 {
52887 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52889 },
52890 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52891 {
52892 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52894 },
52895 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52896 {
52897 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52899 },
52900 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52901 {
52902 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52904 },
52905 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52906 {
52907 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52909 },
52910 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52911 {
52912 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52914 },
52915 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52916 {
52917 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52919 },
52920 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52921 {
52922 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52924 },
52925 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52926 {
52927 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52929 },
52930 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52931 {
52932 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52934 },
52935 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52936 {
52937 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52939 },
52940 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52941 {
52942 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52944 },
52945 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52946 {
52947 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52949 },
52950 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52951 {
52952 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52954 },
52955 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52956 {
52957 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52959 },
52960 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
52961 {
52962 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52964 },
52965 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
52966 {
52967 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52969 },
52970 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52971 {
52972 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52974 },
52975 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
52976 {
52977 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52979 },
52980 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
52981 {
52982 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52984 },
52985 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52986 {
52987 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
52988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52989 },
52990 /* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52991 {
52992 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
52993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52994 },
52995 /* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52996 {
52997 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
52998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52999 },
53000 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53001 {
53002 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53004 },
53005 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53006 {
53007 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53009 },
53010 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53011 {
53012 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53014 },
53015 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53016 {
53017 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53019 },
53020 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53021 {
53022 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53024 },
53025 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53026 {
53027 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53029 },
53030 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53031 {
53032 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53034 },
53035 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53036 {
53037 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53039 },
53040 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53041 {
53042 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53044 },
53045 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53046 {
53047 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53049 },
53050 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53051 {
53052 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53054 },
53055 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53056 {
53057 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53059 },
53060 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53061 {
53062 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53064 },
53065 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53066 {
53067 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53069 },
53070 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53071 {
53072 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53074 },
53075 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53076 {
53077 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53079 },
53080 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53081 {
53082 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53084 },
53085 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53086 {
53087 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53089 },
53090 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53091 {
53092 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53094 },
53095 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53096 {
53097 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53099 },
53100 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53101 {
53102 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53104 },
53105 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53106 {
53107 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53109 },
53110 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53111 {
53112 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53114 },
53115 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53116 {
53117 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53119 },
53120 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53121 {
53122 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53124 },
53125 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53126 {
53127 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53129 },
53130 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53131 {
53132 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53134 },
53135 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53136 {
53137 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53139 },
53140 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
53141 {
53142 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53144 },
53145 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
53146 {
53147 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53149 },
53150 /* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
53151 {
53152 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53154 },
53155 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53156 {
53157 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53159 },
53160 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
53161 {
53162 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53164 },
53165 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
53166 {
53167 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53169 },
53170 /* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
53171 {
53172 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53174 },
53175 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53176 {
53177 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53179 },
53180 /* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53181 {
53182 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53184 },
53185 /* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53186 {
53187 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53189 },
53190 /* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53191 {
53192 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53194 },
53195 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53196 {
53197 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53199 },
53200 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53201 {
53202 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53204 },
53205 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53206 {
53207 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53209 },
53210 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53211 {
53212 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53214 },
53215 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53216 {
53217 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53219 },
53220 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53221 {
53222 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53224 },
53225 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53226 {
53227 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53229 },
53230 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53231 {
53232 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53234 },
53235 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53236 {
53237 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53239 },
53240 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53241 {
53242 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53244 },
53245 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53246 {
53247 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53249 },
53250 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53251 {
53252 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53254 },
53255 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53256 {
53257 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53259 },
53260 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53261 {
53262 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53264 },
53265 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53266 {
53267 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53269 },
53270 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53271 {
53272 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53274 },
53275 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53276 {
53277 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53279 },
53280 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53281 {
53282 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53284 },
53285 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53286 {
53287 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53289 },
53290 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53291 {
53292 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53294 },
53295 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53296 {
53297 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53299 },
53300 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53301 {
53302 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53304 },
53305 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53306 {
53307 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53309 },
53310 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53311 {
53312 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53314 },
53315 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53316 {
53317 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53319 },
53320 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53321 {
53322 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53324 },
53325 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53326 {
53327 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53329 },
53330 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53331 {
53332 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53334 },
53335 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53336 {
53337 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53339 },
53340 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53341 {
53342 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53344 },
53345 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53346 {
53347 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53349 },
53350 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
53351 {
53352 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53354 },
53355 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53356 {
53357 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53359 },
53360 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53361 {
53362 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53364 },
53365 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53366 {
53367 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53369 },
53370 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
53371 {
53372 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53374 },
53375 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53376 {
53377 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53379 },
53380 /* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53381 {
53382 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53384 },
53385 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53386 {
53387 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53389 },
53390 /* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53391 {
53392 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53394 },
53395 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53396 {
53397 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53399 },
53400 /* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53401 {
53402 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53404 },
53405 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53406 {
53407 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53409 },
53410 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53411 {
53412 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53414 },
53415 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53416 {
53417 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53419 },
53420 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53421 {
53422 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53424 },
53425 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53426 {
53427 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53429 },
53430 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53431 {
53432 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53434 },
53435 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53436 {
53437 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53439 },
53440 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53441 {
53442 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53444 },
53445 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53446 {
53447 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53449 },
53450 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53451 {
53452 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53454 },
53455 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53456 {
53457 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53459 },
53460 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53461 {
53462 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53464 },
53465 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53466 {
53467 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53469 },
53470 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53471 {
53472 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53474 },
53475 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53476 {
53477 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53479 },
53480 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53481 {
53482 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53484 },
53485 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53486 {
53487 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53489 },
53490 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53491 {
53492 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53494 },
53495 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53496 {
53497 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53499 },
53500 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53501 {
53502 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53504 },
53505 /* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53506 {
53507 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53509 },
53510 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53511 {
53512 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53514 },
53515 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53516 {
53517 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53519 },
53520 /* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53521 {
53522 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53524 },
53525 /* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53526 {
53527 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53529 },
53530 /* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53531 {
53532 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53534 },
53535 /* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53536 {
53537 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53539 },
53540 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53541 {
53542 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53544 },
53545 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53546 {
53547 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53549 },
53550 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53551 {
53552 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53554 },
53555 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53556 {
53557 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53559 },
53560 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53561 {
53562 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53564 },
53565 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53566 {
53567 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53569 },
53570 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53571 {
53572 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53574 },
53575 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53576 {
53577 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53579 },
53580 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53581 {
53582 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53584 },
53585 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53586 {
53587 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53589 },
53590 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53591 {
53592 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53594 },
53595 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53596 {
53597 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53599 },
53600 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53601 {
53602 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53604 },
53605 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53606 {
53607 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53609 },
53610 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53611 {
53612 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53614 },
53615 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53616 {
53617 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53619 },
53620 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53621 {
53622 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53624 },
53625 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53626 {
53627 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53629 },
53630 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53631 {
53632 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53634 },
53635 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53636 {
53637 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53639 },
53640 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53641 {
53642 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53644 },
53645 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53646 {
53647 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53649 },
53650 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53651 {
53652 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53654 },
53655 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53656 {
53657 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53659 },
53660 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53661 {
53662 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53664 },
53665 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53666 {
53667 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53669 },
53670 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53671 {
53672 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53674 },
53675 /* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53676 {
53677 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
53678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53679 },
53680 /* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53681 {
53682 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
53683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53684 },
53685 /* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53686 {
53687 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
53688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53689 },
53690 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53691 {
53692 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48,
53693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53694 },
53695 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53696 {
53697 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48,
53698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53699 },
53700 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53701 {
53702 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48,
53703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53704 },
53705 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53706 {
53707 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56,
53708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53709 },
53710 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53711 {
53712 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56,
53713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53714 },
53715 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53716 {
53717 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56,
53718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53719 },
53720 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53721 {
53722 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56,
53723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53724 },
53725 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53726 {
53727 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64,
53728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53729 },
53730 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53731 {
53732 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64,
53733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53734 },
53735 /* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53736 {
53737 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
53738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53739 },
53740 /* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53741 {
53742 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53744 },
53745 /* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53746 {
53747 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53749 },
53750 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53751 {
53752 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40,
53753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53754 },
53755 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53756 {
53757 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53759 },
53760 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53761 {
53762 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53764 },
53765 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53766 {
53767 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48,
53768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53769 },
53770 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53771 {
53772 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53774 },
53775 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53776 {
53777 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53779 },
53780 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53781 {
53782 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48,
53783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53784 },
53785 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53786 {
53787 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56,
53788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53789 },
53790 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53791 {
53792 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56,
53793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53794 },
53795 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53796 {
53797 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53799 },
53800 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53801 {
53802 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53804 },
53805 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53806 {
53807 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53809 },
53810 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53811 {
53812 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53814 },
53815 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53816 {
53817 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53819 },
53820 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53821 {
53822 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53824 },
53825 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53826 {
53827 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53829 },
53830 /* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53831 {
53832 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53834 },
53835 /* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53836 {
53837 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53839 },
53840 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53841 {
53842 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53844 },
53845 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53846 {
53847 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53849 },
53850 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53851 {
53852 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53854 },
53855 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53856 {
53857 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53859 },
53860 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53861 {
53862 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53864 },
53865 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53866 {
53867 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53869 },
53870 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53871 {
53872 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53874 },
53875 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53876 {
53877 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53879 },
53880 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53881 {
53882 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53884 },
53885 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53886 {
53887 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53889 },
53890 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53891 {
53892 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53894 },
53895 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53896 {
53897 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53899 },
53900 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53901 {
53902 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53904 },
53905 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53906 {
53907 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53909 },
53910 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53911 {
53912 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53914 },
53915 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53916 {
53917 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53919 },
53920 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53921 {
53922 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53924 },
53925 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53926 {
53927 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53929 },
53930 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53931 {
53932 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53934 },
53935 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53936 {
53937 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53939 },
53940 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53941 {
53942 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53944 },
53945 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53946 {
53947 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53949 },
53950 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53951 {
53952 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53954 },
53955 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53956 {
53957 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53959 },
53960 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53961 {
53962 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53964 },
53965 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53966 {
53967 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53969 },
53970 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53971 {
53972 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53974 },
53975 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53976 {
53977 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53979 },
53980 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
53981 {
53982 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53984 },
53985 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
53986 {
53987 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53989 },
53990 /* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
53991 {
53992 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53994 },
53995 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53996 {
53997 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
53998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53999 },
54000 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
54001 {
54002 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54004 },
54005 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
54006 {
54007 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54009 },
54010 /* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
54011 {
54012 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54014 },
54015 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54016 {
54017 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54019 },
54020 /* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54021 {
54022 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54024 },
54025 /* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54026 {
54027 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54029 },
54030 /* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54031 {
54032 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54034 },
54035 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54036 {
54037 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54039 },
54040 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54041 {
54042 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54044 },
54045 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54046 {
54047 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54049 },
54050 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54051 {
54052 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54054 },
54055 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54056 {
54057 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54059 },
54060 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54061 {
54062 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54064 },
54065 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54066 {
54067 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54069 },
54070 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54071 {
54072 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54074 },
54075 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54076 {
54077 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54079 },
54080 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54081 {
54082 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54084 },
54085 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54086 {
54087 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54089 },
54090 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54091 {
54092 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54094 },
54095 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54096 {
54097 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54099 },
54100 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54101 {
54102 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54104 },
54105 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54106 {
54107 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54109 },
54110 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54111 {
54112 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54114 },
54115 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54116 {
54117 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54119 },
54120 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54121 {
54122 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54124 },
54125 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54126 {
54127 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54129 },
54130 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54131 {
54132 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54134 },
54135 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54136 {
54137 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54139 },
54140 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54141 {
54142 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54144 },
54145 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54146 {
54147 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54149 },
54150 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54151 {
54152 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54154 },
54155 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54156 {
54157 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54159 },
54160 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54161 {
54162 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54164 },
54165 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54166 {
54167 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54169 },
54170 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54171 {
54172 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54174 },
54175 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54176 {
54177 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54179 },
54180 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54181 {
54182 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54184 },
54185 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54186 {
54187 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54189 },
54190 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
54191 {
54192 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54194 },
54195 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54196 {
54197 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54199 },
54200 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54201 {
54202 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54204 },
54205 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54206 {
54207 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54209 },
54210 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
54211 {
54212 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54214 },
54215 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54216 {
54217 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
54218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54219 },
54220 /* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
54221 {
54222 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
54223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54224 },
54225 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54226 {
54227 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
54228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54229 },
54230 /* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
54231 {
54232 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
54233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54234 },
54235 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54236 {
54237 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
54238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54239 },
54240 /* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54241 {
54242 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
54243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54244 },
54245 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54246 {
54247 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
54248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54249 },
54250 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54251 {
54252 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
54253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54254 },
54255 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54256 {
54257 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
54258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54259 },
54260 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54261 {
54262 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
54263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54264 },
54265 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54266 {
54267 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
54268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54269 },
54270 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54271 {
54272 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
54273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54274 },
54275 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54276 {
54277 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
54278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54279 },
54280 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54281 {
54282 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
54283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54284 },
54285 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54286 {
54287 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
54288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54289 },
54290 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54291 {
54292 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
54293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54294 },
54295 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54296 {
54297 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
54298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54299 },
54300 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54301 {
54302 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
54303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54304 },
54305 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54306 {
54307 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
54308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54309 },
54310 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54311 {
54312 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
54313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54314 },
54315 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54316 {
54317 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
54318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54319 },
54320 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
54321 {
54322 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
54323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54324 },
54325 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54326 {
54327 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
54328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54329 },
54330 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
54331 {
54332 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
54333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54334 },
54335 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
54336 {
54337 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54339 },
54340 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
54341 {
54342 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54344 },
54345 /* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
54346 {
54347 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54349 },
54350 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
54351 {
54352 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54354 },
54355 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
54356 {
54357 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54359 },
54360 /* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
54361 {
54362 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54364 },
54365 /* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
54366 {
54367 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54369 },
54370 /* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
54371 {
54372 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54374 },
54375 /* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54376 {
54377 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54379 },
54380 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54381 {
54382 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54384 },
54385 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54386 {
54387 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54389 },
54390 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54391 {
54392 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54394 },
54395 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54396 {
54397 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54399 },
54400 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54401 {
54402 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54404 },
54405 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54406 {
54407 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54409 },
54410 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54411 {
54412 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54414 },
54415 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54416 {
54417 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54419 },
54420 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54421 {
54422 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54424 },
54425 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54426 {
54427 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54429 },
54430 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54431 {
54432 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54434 },
54435 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54436 {
54437 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54439 },
54440 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54441 {
54442 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54444 },
54445 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54446 {
54447 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54449 },
54450 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54451 {
54452 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54454 },
54455 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54456 {
54457 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54459 },
54460 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54461 {
54462 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54464 },
54465 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54466 {
54467 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54469 },
54470 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54471 {
54472 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54474 },
54475 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54476 {
54477 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54479 },
54480 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54481 {
54482 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54484 },
54485 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54486 {
54487 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54489 },
54490 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54491 {
54492 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54494 },
54495 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54496 {
54497 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54499 },
54500 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54501 {
54502 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54504 },
54505 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54506 {
54507 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54509 },
54510 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54511 {
54512 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54514 },
54515 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54516 {
54517 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54519 },
54520 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54521 {
54522 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54524 },
54525 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54526 {
54527 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54529 },
54530 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54531 {
54532 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54534 },
54535 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54536 {
54537 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54539 },
54540 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54541 {
54542 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54544 },
54545 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54546 {
54547 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54549 },
54550 /* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54551 {
54552 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54554 },
54555 /* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54556 {
54557 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54559 },
54560 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54561 {
54562 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54564 },
54565 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54566 {
54567 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54569 },
54570 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54571 {
54572 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54574 },
54575 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54576 {
54577 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54579 },
54580 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54581 {
54582 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54584 },
54585 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54586 {
54587 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54589 },
54590 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54591 {
54592 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54594 },
54595 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54596 {
54597 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54599 },
54600 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54601 {
54602 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54604 },
54605 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54606 {
54607 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54609 },
54610 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54611 {
54612 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54614 },
54615 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54616 {
54617 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54619 },
54620 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54621 {
54622 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54624 },
54625 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54626 {
54627 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54629 },
54630 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54631 {
54632 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54634 },
54635 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54636 {
54637 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54639 },
54640 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54641 {
54642 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54644 },
54645 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54646 {
54647 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54649 },
54650 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54651 {
54652 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54654 },
54655 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54656 {
54657 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54659 },
54660 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54661 {
54662 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54664 },
54665 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54666 {
54667 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54669 },
54670 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54671 {
54672 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54674 },
54675 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54676 {
54677 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54679 },
54680 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54681 {
54682 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54684 },
54685 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54686 {
54687 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54689 },
54690 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54691 {
54692 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54694 },
54695 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54696 {
54697 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54699 },
54700 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54701 {
54702 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54704 },
54705 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54706 {
54707 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54709 },
54710 /* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54711 {
54712 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54714 },
54715 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54716 {
54717 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54719 },
54720 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
54721 {
54722 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54724 },
54725 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
54726 {
54727 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54729 },
54730 /* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
54731 {
54732 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54734 },
54735 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54736 {
54737 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54739 },
54740 /* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54741 {
54742 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54744 },
54745 /* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54746 {
54747 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54749 },
54750 /* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54751 {
54752 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54754 },
54755 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54756 {
54757 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54759 },
54760 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54761 {
54762 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54764 },
54765 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54766 {
54767 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54769 },
54770 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54771 {
54772 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54774 },
54775 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54776 {
54777 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54779 },
54780 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54781 {
54782 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54784 },
54785 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54786 {
54787 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54789 },
54790 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54791 {
54792 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54794 },
54795 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54796 {
54797 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54799 },
54800 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54801 {
54802 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54804 },
54805 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54806 {
54807 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54809 },
54810 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54811 {
54812 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54814 },
54815 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54816 {
54817 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54819 },
54820 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54821 {
54822 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54824 },
54825 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54826 {
54827 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54829 },
54830 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54831 {
54832 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54834 },
54835 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54836 {
54837 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54839 },
54840 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54841 {
54842 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54844 },
54845 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54846 {
54847 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54849 },
54850 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54851 {
54852 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54854 },
54855 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54856 {
54857 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54859 },
54860 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54861 {
54862 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54864 },
54865 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54866 {
54867 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54869 },
54870 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54871 {
54872 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54874 },
54875 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54876 {
54877 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54879 },
54880 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54881 {
54882 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54884 },
54885 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54886 {
54887 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54889 },
54890 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54891 {
54892 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54894 },
54895 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54896 {
54897 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54899 },
54900 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54901 {
54902 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54904 },
54905 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54906 {
54907 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54909 },
54910 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
54911 {
54912 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54914 },
54915 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54916 {
54917 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54919 },
54920 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54921 {
54922 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54924 },
54925 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54926 {
54927 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54929 },
54930 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
54931 {
54932 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54934 },
54935 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54936 {
54937 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54939 },
54940 /* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
54941 {
54942 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54944 },
54945 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54946 {
54947 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54949 },
54950 /* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
54951 {
54952 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54954 },
54955 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54956 {
54957 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54959 },
54960 /* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54961 {
54962 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54964 },
54965 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54966 {
54967 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
54968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54969 },
54970 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54971 {
54972 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
54973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54974 },
54975 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54976 {
54977 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
54978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54979 },
54980 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54981 {
54982 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
54983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54984 },
54985 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54986 {
54987 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
54988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54989 },
54990 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54991 {
54992 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
54993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54994 },
54995 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54996 {
54997 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
54998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54999 },
55000 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55001 {
55002 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
55003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55004 },
55005 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55006 {
55007 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
55008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55009 },
55010 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55011 {
55012 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
55013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55014 },
55015 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55016 {
55017 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
55018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55019 },
55020 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55021 {
55022 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
55023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55024 },
55025 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55026 {
55027 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
55028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55029 },
55030 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55031 {
55032 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
55033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55034 },
55035 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55036 {
55037 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
55038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55039 },
55040 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
55041 {
55042 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
55043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55044 },
55045 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55046 {
55047 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
55048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55049 },
55050 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
55051 {
55052 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
55053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55054 },
55055 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
55056 {
55057 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55059 },
55060 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
55061 {
55062 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55064 },
55065 /* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
55066 {
55067 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55069 },
55070 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
55071 {
55072 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55074 },
55075 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
55076 {
55077 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55079 },
55080 /* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
55081 {
55082 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55084 },
55085 /* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
55086 {
55087 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55089 },
55090 /* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
55091 {
55092 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55094 },
55095 /* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55096 {
55097 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55099 },
55100 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55101 {
55102 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55104 },
55105 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55106 {
55107 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55109 },
55110 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55111 {
55112 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55114 },
55115 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55116 {
55117 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55119 },
55120 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55121 {
55122 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55124 },
55125 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55126 {
55127 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55129 },
55130 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55131 {
55132 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55134 },
55135 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55136 {
55137 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55139 },
55140 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55141 {
55142 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55144 },
55145 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
55146 {
55147 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55149 },
55150 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
55151 {
55152 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55154 },
55155 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55156 {
55157 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55159 },
55160 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
55161 {
55162 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55164 },
55165 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
55166 {
55167 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55169 },
55170 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55171 {
55172 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55174 },
55175 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
55176 {
55177 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55179 },
55180 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
55181 {
55182 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55184 },
55185 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55186 {
55187 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55189 },
55190 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
55191 {
55192 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55194 },
55195 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
55196 {
55197 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55199 },
55200 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55201 {
55202 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55204 },
55205 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
55206 {
55207 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55209 },
55210 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
55211 {
55212 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55214 },
55215 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55216 {
55217 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55219 },
55220 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
55221 {
55222 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55224 },
55225 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
55226 {
55227 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55229 },
55230 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55231 {
55232 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55234 },
55235 /* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
55236 {
55237 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
55238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55239 },
55240 /* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
55241 {
55242 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
55243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55244 },
55245 /* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
55246 {
55247 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
55248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55249 },
55250 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55251 {
55252 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48,
55253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55254 },
55255 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
55256 {
55257 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48,
55258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55259 },
55260 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
55261 {
55262 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48,
55263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55264 },
55265 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55266 {
55267 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56,
55268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55269 },
55270 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
55271 {
55272 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56,
55273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55274 },
55275 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
55276 {
55277 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56,
55278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55279 },
55280 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
55281 {
55282 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56,
55283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55284 },
55285 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55286 {
55287 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64,
55288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55289 },
55290 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
55291 {
55292 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64,
55293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55294 },
55295 /* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
55296 {
55297 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
55298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55299 },
55300 /* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
55301 {
55302 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
55303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55304 },
55305 /* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
55306 {
55307 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
55308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55309 },
55310 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55311 {
55312 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40,
55313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55314 },
55315 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
55316 {
55317 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40,
55318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55319 },
55320 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
55321 {
55322 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40,
55323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55324 },
55325 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55326 {
55327 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48,
55328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55329 },
55330 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
55331 {
55332 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48,
55333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55334 },
55335 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
55336 {
55337 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48,
55338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55339 },
55340 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
55341 {
55342 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48,
55343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55344 },
55345 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55346 {
55347 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56,
55348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55349 },
55350 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
55351 {
55352 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56,
55353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55354 },
55355 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55356 {
55357 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55359 },
55360 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
55361 {
55362 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55364 },
55365 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
55366 {
55367 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55369 },
55370 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55371 {
55372 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55374 },
55375 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
55376 {
55377 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55379 },
55380 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
55381 {
55382 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55384 },
55385 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55386 {
55387 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55389 },
55390 /* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
55391 {
55392 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55394 },
55395 /* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
55396 {
55397 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55399 },
55400 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
55401 {
55402 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55404 },
55405 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55406 {
55407 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55409 },
55410 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55411 {
55412 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55414 },
55415 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
55416 {
55417 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55419 },
55420 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55421 {
55422 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55424 },
55425 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55426 {
55427 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55429 },
55430 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
55431 {
55432 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55434 },
55435 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55436 {
55437 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55439 },
55440 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55441 {
55442 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55444 },
55445 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
55446 {
55447 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55449 },
55450 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
55451 {
55452 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55454 },
55455 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
55456 {
55457 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55459 },
55460 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
55461 {
55462 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55464 },
55465 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
55466 {
55467 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55469 },
55470 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
55471 {
55472 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55474 },
55475 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
55476 {
55477 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55479 },
55480 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
55481 {
55482 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55484 },
55485 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
55486 {
55487 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55489 },
55490 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
55491 {
55492 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55494 },
55495 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
55496 {
55497 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55499 },
55500 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
55501 {
55502 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55504 },
55505 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
55506 {
55507 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55509 },
55510 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
55511 {
55512 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55514 },
55515 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
55516 {
55517 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55519 },
55520 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
55521 {
55522 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55524 },
55525 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
55526 {
55527 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55529 },
55530 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
55531 {
55532 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55534 },
55535 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55536 {
55537 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55539 },
55540 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
55541 {
55542 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55544 },
55545 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
55546 {
55547 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55549 },
55550 /* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
55551 {
55552 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55554 },
55555 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55556 {
55557 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55559 },
55560 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
55561 {
55562 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55564 },
55565 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
55566 {
55567 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55569 },
55570 /* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
55571 {
55572 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55574 },
55575 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55576 {
55577 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55579 },
55580 /* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55581 {
55582 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55584 },
55585 /* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55586 {
55587 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55589 },
55590 /* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55591 {
55592 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55594 },
55595 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55596 {
55597 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55599 },
55600 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55601 {
55602 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55604 },
55605 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55606 {
55607 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55609 },
55610 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55611 {
55612 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55614 },
55615 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55616 {
55617 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55619 },
55620 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55621 {
55622 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55624 },
55625 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55626 {
55627 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55629 },
55630 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55631 {
55632 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55634 },
55635 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55636 {
55637 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55639 },
55640 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55641 {
55642 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55644 },
55645 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55646 {
55647 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55649 },
55650 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55651 {
55652 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55654 },
55655 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
55656 {
55657 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55659 },
55660 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
55661 {
55662 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55664 },
55665 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
55666 {
55667 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55669 },
55670 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
55671 {
55672 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55674 },
55675 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
55676 {
55677 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55679 },
55680 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
55681 {
55682 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55684 },
55685 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
55686 {
55687 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55689 },
55690 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
55691 {
55692 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55694 },
55695 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
55696 {
55697 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55699 },
55700 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
55701 {
55702 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55704 },
55705 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
55706 {
55707 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55709 },
55710 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
55711 {
55712 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55714 },
55715 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
55716 {
55717 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55719 },
55720 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
55721 {
55722 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55724 },
55725 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
55726 {
55727 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55729 },
55730 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
55731 {
55732 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55734 },
55735 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
55736 {
55737 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55739 },
55740 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
55741 {
55742 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55744 },
55745 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
55746 {
55747 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55749 },
55750 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
55751 {
55752 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55754 },
55755 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
55756 {
55757 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55759 },
55760 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
55761 {
55762 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55764 },
55765 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
55766 {
55767 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55769 },
55770 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
55771 {
55772 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55774 },
55775 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55776 {
55777 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55779 },
55780 /* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
55781 {
55782 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55784 },
55785 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55786 {
55787 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55789 },
55790 /* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
55791 {
55792 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55794 },
55795 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55796 {
55797 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55799 },
55800 /* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55801 {
55802 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55804 },
55805 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55806 {
55807 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55809 },
55810 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55811 {
55812 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55814 },
55815 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55816 {
55817 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55819 },
55820 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55821 {
55822 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55824 },
55825 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55826 {
55827 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55829 },
55830 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55831 {
55832 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55834 },
55835 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55836 {
55837 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55839 },
55840 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55841 {
55842 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55844 },
55845 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55846 {
55847 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55849 },
55850 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55851 {
55852 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55854 },
55855 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55856 {
55857 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55859 },
55860 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55861 {
55862 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55864 },
55865 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55866 {
55867 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55869 },
55870 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55871 {
55872 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55874 },
55875 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55876 {
55877 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55879 },
55880 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
55881 {
55882 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55884 },
55885 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55886 {
55887 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55889 },
55890 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
55891 {
55892 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55894 },
55895 /* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
55896 {
55897 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55899 },
55900 /* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
55901 {
55902 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55904 },
55905 /* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
55906 {
55907 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55909 },
55910 /* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
55911 {
55912 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55914 },
55915 /* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
55916 {
55917 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55919 },
55920 /* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
55921 {
55922 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55924 },
55925 /* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
55926 {
55927 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55929 },
55930 /* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
55931 {
55932 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55934 },
55935 /* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55936 {
55937 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55939 },
55940 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55941 {
55942 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55944 },
55945 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55946 {
55947 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55949 },
55950 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55951 {
55952 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55954 },
55955 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55956 {
55957 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55959 },
55960 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55961 {
55962 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55964 },
55965 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55966 {
55967 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55969 },
55970 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55971 {
55972 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55974 },
55975 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55976 {
55977 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55979 },
55980 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55981 {
55982 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55984 },
55985 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
55986 {
55987 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
55988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55989 },
55990 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
55991 {
55992 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
55993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55994 },
55995 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55996 {
55997 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
55998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55999 },
56000 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
56001 {
56002 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56004 },
56005 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
56006 {
56007 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56009 },
56010 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56011 {
56012 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56014 },
56015 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
56016 {
56017 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56019 },
56020 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
56021 {
56022 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56024 },
56025 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56026 {
56027 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56029 },
56030 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
56031 {
56032 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56034 },
56035 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
56036 {
56037 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56039 },
56040 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56041 {
56042 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56044 },
56045 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
56046 {
56047 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56049 },
56050 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
56051 {
56052 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56054 },
56055 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56056 {
56057 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56059 },
56060 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
56061 {
56062 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56064 },
56065 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
56066 {
56067 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56069 },
56070 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56071 {
56072 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56074 },
56075 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56076 {
56077 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56079 },
56080 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
56081 {
56082 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56084 },
56085 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
56086 {
56087 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56089 },
56090 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56091 {
56092 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56094 },
56095 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
56096 {
56097 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56099 },
56100 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
56101 {
56102 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56104 },
56105 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56106 {
56107 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56109 },
56110 /* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
56111 {
56112 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56114 },
56115 /* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
56116 {
56117 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56119 },
56120 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
56121 {
56122 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56124 },
56125 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56126 {
56127 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56129 },
56130 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56131 {
56132 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56134 },
56135 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
56136 {
56137 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56139 },
56140 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56141 {
56142 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56144 },
56145 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56146 {
56147 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56149 },
56150 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
56151 {
56152 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56154 },
56155 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56156 {
56157 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56159 },
56160 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56161 {
56162 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56164 },
56165 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
56166 {
56167 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56169 },
56170 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
56171 {
56172 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56174 },
56175 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
56176 {
56177 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56179 },
56180 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
56181 {
56182 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56184 },
56185 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
56186 {
56187 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56189 },
56190 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
56191 {
56192 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56194 },
56195 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
56196 {
56197 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56199 },
56200 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
56201 {
56202 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56204 },
56205 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
56206 {
56207 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56209 },
56210 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
56211 {
56212 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56214 },
56215 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
56216 {
56217 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56219 },
56220 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
56221 {
56222 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56224 },
56225 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
56226 {
56227 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56229 },
56230 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
56231 {
56232 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56234 },
56235 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
56236 {
56237 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56239 },
56240 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
56241 {
56242 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56244 },
56245 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
56246 {
56247 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56249 },
56250 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
56251 {
56252 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56254 },
56255 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56256 {
56257 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56259 },
56260 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
56261 {
56262 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56264 },
56265 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
56266 {
56267 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56269 },
56270 /* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
56271 {
56272 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56274 },
56275 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56276 {
56277 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56279 },
56280 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
56281 {
56282 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56284 },
56285 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
56286 {
56287 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56289 },
56290 /* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
56291 {
56292 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56294 },
56295 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56296 {
56297 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56299 },
56300 /* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
56301 {
56302 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56304 },
56305 /* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
56306 {
56307 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56309 },
56310 /* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
56311 {
56312 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56314 },
56315 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
56316 {
56317 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56319 },
56320 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56321 {
56322 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56324 },
56325 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56326 {
56327 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56329 },
56330 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
56331 {
56332 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56334 },
56335 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
56336 {
56337 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56339 },
56340 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56341 {
56342 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56344 },
56345 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56346 {
56347 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56349 },
56350 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
56351 {
56352 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56354 },
56355 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
56356 {
56357 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56359 },
56360 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56361 {
56362 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56364 },
56365 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56366 {
56367 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56369 },
56370 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
56371 {
56372 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56374 },
56375 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
56376 {
56377 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56379 },
56380 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
56381 {
56382 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56384 },
56385 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
56386 {
56387 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56389 },
56390 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
56391 {
56392 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56394 },
56395 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
56396 {
56397 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56399 },
56400 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
56401 {
56402 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56404 },
56405 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
56406 {
56407 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56409 },
56410 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
56411 {
56412 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56414 },
56415 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
56416 {
56417 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56419 },
56420 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
56421 {
56422 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56424 },
56425 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
56426 {
56427 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56429 },
56430 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
56431 {
56432 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56434 },
56435 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
56436 {
56437 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56439 },
56440 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
56441 {
56442 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56444 },
56445 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
56446 {
56447 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56449 },
56450 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
56451 {
56452 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56454 },
56455 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
56456 {
56457 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56459 },
56460 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
56461 {
56462 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56464 },
56465 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
56466 {
56467 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56469 },
56470 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
56471 {
56472 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56474 },
56475 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
56476 {
56477 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56479 },
56480 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
56481 {
56482 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56484 },
56485 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
56486 {
56487 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56489 },
56490 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
56491 {
56492 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56494 },
56495 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56496 {
56497 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56499 },
56500 /* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
56501 {
56502 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56504 },
56505 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56506 {
56507 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56509 },
56510 /* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
56511 {
56512 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56514 },
56515 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56516 {
56517 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56519 },
56520 /* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
56521 {
56522 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56524 },
56525 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
56526 {
56527 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56529 },
56530 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
56531 {
56532 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56534 },
56535 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
56536 {
56537 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56539 },
56540 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
56541 {
56542 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56544 },
56545 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
56546 {
56547 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56549 },
56550 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
56551 {
56552 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56554 },
56555 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
56556 {
56557 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56559 },
56560 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
56561 {
56562 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56564 },
56565 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
56566 {
56567 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56569 },
56570 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
56571 {
56572 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56574 },
56575 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
56576 {
56577 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56579 },
56580 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
56581 {
56582 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56584 },
56585 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
56586 {
56587 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56589 },
56590 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
56591 {
56592 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56594 },
56595 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
56596 {
56597 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56599 },
56600 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
56601 {
56602 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56604 },
56605 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
56606 {
56607 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56609 },
56610 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
56611 {
56612 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56614 },
56615 /* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
56616 {
56617 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56619 },
56620 /* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
56621 {
56622 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56624 },
56625 /* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
56626 {
56627 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56629 },
56630 /* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
56631 {
56632 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56634 },
56635 /* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
56636 {
56637 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56639 },
56640 /* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
56641 {
56642 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56644 },
56645 /* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
56646 {
56647 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56649 },
56650 /* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
56651 {
56652 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56654 },
56655 /* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
56656 {
56657 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56659 },
56660 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56661 {
56662 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56664 },
56665 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56666 {
56667 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56669 },
56670 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
56671 {
56672 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56674 },
56675 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56676 {
56677 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56679 },
56680 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56681 {
56682 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56684 },
56685 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
56686 {
56687 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56689 },
56690 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56691 {
56692 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56694 },
56695 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56696 {
56697 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56699 },
56700 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
56701 {
56702 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56704 },
56705 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
56706 {
56707 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56709 },
56710 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
56711 {
56712 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56714 },
56715 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56716 {
56717 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56719 },
56720 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
56721 {
56722 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56724 },
56725 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
56726 {
56727 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56729 },
56730 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56731 {
56732 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56734 },
56735 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
56736 {
56737 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56739 },
56740 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
56741 {
56742 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56744 },
56745 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56746 {
56747 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56749 },
56750 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
56751 {
56752 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56754 },
56755 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
56756 {
56757 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56759 },
56760 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56761 {
56762 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56764 },
56765 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
56766 {
56767 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56769 },
56770 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
56771 {
56772 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56774 },
56775 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56776 {
56777 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56779 },
56780 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
56781 {
56782 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56784 },
56785 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
56786 {
56787 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56789 },
56790 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56791 {
56792 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56794 },
56795 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
56796 {
56797 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56799 },
56800 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
56801 {
56802 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56804 },
56805 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
56806 {
56807 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56809 },
56810 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
56811 {
56812 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56814 },
56815 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
56816 {
56817 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56819 },
56820 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
56821 {
56822 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56824 },
56825 /* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
56826 {
56827 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56829 },
56830 /* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
56831 {
56832 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56834 },
56835 /* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
56836 {
56837 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56839 },
56840 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
56841 {
56842 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56844 },
56845 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
56846 {
56847 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56849 },
56850 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
56851 {
56852 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56854 },
56855 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
56856 {
56857 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56859 },
56860 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
56861 {
56862 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56864 },
56865 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
56866 {
56867 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56869 },
56870 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
56871 {
56872 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56874 },
56875 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
56876 {
56877 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56879 },
56880 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
56881 {
56882 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56884 },
56885 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
56886 {
56887 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56889 },
56890 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
56891 {
56892 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56894 },
56895 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
56896 {
56897 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56899 },
56900 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
56901 {
56902 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56904 },
56905 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
56906 {
56907 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56909 },
56910 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
56911 {
56912 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56914 },
56915 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
56916 {
56917 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56918 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56919 },
56920 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
56921 {
56922 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56924 },
56925 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
56926 {
56927 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56929 },
56930 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
56931 {
56932 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56933 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56934 },
56935 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
56936 {
56937 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56939 },
56940 /* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
56941 {
56942 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32,
56943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56944 },
56945 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
56946 {
56947 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56949 },
56950 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
56951 {
56952 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56953 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56954 },
56955 /* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
56956 {
56957 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32,
56958 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56959 },
56960 /* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
56961 {
56962 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
56963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56964 },
56965 /* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
56966 {
56967 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
56968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56969 },
56970 /* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
56971 {
56972 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32,
56973 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56974 },
56975 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
56976 {
56977 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
56978 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56979 },
56980 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
56981 {
56982 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
56983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56984 },
56985 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
56986 {
56987 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
56988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56989 },
56990 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
56991 {
56992 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
56993 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56994 },
56995 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
56996 {
56997 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
56998 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56999 },
57000 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57001 {
57002 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
57003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57004 },
57005 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57006 {
57007 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57009 },
57010 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57011 {
57012 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57014 },
57015 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57016 {
57017 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57019 },
57020 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57021 {
57022 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57024 },
57025 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57026 {
57027 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57029 },
57030 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57031 {
57032 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57034 },
57035 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57036 {
57037 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57039 },
57040 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57041 {
57042 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57044 },
57045 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57046 {
57047 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57049 },
57050 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57051 {
57052 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57054 },
57055 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57056 {
57057 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57059 },
57060 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
57061 {
57062 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57064 },
57065 /* adc.w${X} $Src16RnHI,$Dst16RnHI */
57066 {
57067 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
57068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57069 },
57070 /* adc.w${X} $Src16AnHI,$Dst16RnHI */
57071 {
57072 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
57073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57074 },
57075 /* adc.w${X} [$Src16An],$Dst16RnHI */
57076 {
57077 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16,
57078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57079 },
57080 /* adc.w${X} $Src16RnHI,$Dst16AnHI */
57081 {
57082 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16,
57083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57084 },
57085 /* adc.w${X} $Src16AnHI,$Dst16AnHI */
57086 {
57087 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16,
57088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57089 },
57090 /* adc.w${X} [$Src16An],$Dst16AnHI */
57091 {
57092 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16,
57093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57094 },
57095 /* adc.w${X} $Src16RnHI,[$Dst16An] */
57096 {
57097 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
57098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57099 },
57100 /* adc.w${X} $Src16AnHI,[$Dst16An] */
57101 {
57102 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
57103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57104 },
57105 /* adc.w${X} [$Src16An],[$Dst16An] */
57106 {
57107 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16,
57108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57109 },
57110 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
57111 {
57112 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57114 },
57115 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
57116 {
57117 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57119 },
57120 /* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57121 {
57122 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57124 },
57125 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
57126 {
57127 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57129 },
57130 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
57131 {
57132 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57134 },
57135 /* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57136 {
57137 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57139 },
57140 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
57141 {
57142 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57144 },
57145 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
57146 {
57147 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57149 },
57150 /* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
57151 {
57152 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57154 },
57155 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
57156 {
57157 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57159 },
57160 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
57161 {
57162 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57164 },
57165 /* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
57166 {
57167 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57169 },
57170 /* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
57171 {
57172 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57174 },
57175 /* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
57176 {
57177 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57179 },
57180 /* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
57181 {
57182 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57184 },
57185 /* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
57186 {
57187 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57189 },
57190 /* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
57191 {
57192 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57194 },
57195 /* adc.w${X} [$Src16An],${Dsp-16-u16} */
57196 {
57197 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57199 },
57200 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
57201 {
57202 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57204 },
57205 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
57206 {
57207 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57209 },
57210 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
57211 {
57212 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57214 },
57215 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
57216 {
57217 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57219 },
57220 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
57221 {
57222 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57224 },
57225 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
57226 {
57227 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57229 },
57230 /* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
57231 {
57232 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57234 },
57235 /* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
57236 {
57237 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57239 },
57240 /* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
57241 {
57242 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57244 },
57245 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
57246 {
57247 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57249 },
57250 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
57251 {
57252 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57254 },
57255 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
57256 {
57257 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57259 },
57260 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
57261 {
57262 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57264 },
57265 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
57266 {
57267 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57269 },
57270 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
57271 {
57272 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57274 },
57275 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
57276 {
57277 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57279 },
57280 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57281 {
57282 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57284 },
57285 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57286 {
57287 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57289 },
57290 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
57291 {
57292 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57294 },
57295 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57296 {
57297 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57299 },
57300 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57301 {
57302 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57304 },
57305 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
57306 {
57307 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57309 },
57310 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57311 {
57312 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57314 },
57315 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57316 {
57317 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57319 },
57320 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
57321 {
57322 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57324 },
57325 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57326 {
57327 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57329 },
57330 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57331 {
57332 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57334 },
57335 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
57336 {
57337 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
57338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57339 },
57340 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
57341 {
57342 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
57343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57344 },
57345 /* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
57346 {
57347 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32,
57348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57349 },
57350 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
57351 {
57352 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32,
57353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57354 },
57355 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
57356 {
57357 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32,
57358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57359 },
57360 /* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
57361 {
57362 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32,
57363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57364 },
57365 /* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
57366 {
57367 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
57368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57369 },
57370 /* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
57371 {
57372 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
57373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57374 },
57375 /* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
57376 {
57377 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32,
57378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57379 },
57380 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
57381 {
57382 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57384 },
57385 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
57386 {
57387 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57389 },
57390 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57391 {
57392 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57394 },
57395 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57396 {
57397 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57399 },
57400 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57401 {
57402 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57404 },
57405 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57406 {
57407 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57409 },
57410 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57411 {
57412 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57414 },
57415 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57416 {
57417 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57419 },
57420 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57421 {
57422 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57424 },
57425 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57426 {
57427 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57429 },
57430 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57431 {
57432 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57434 },
57435 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57436 {
57437 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57439 },
57440 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57441 {
57442 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57444 },
57445 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57446 {
57447 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57449 },
57450 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57451 {
57452 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57454 },
57455 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57456 {
57457 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57459 },
57460 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57461 {
57462 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57464 },
57465 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
57466 {
57467 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57469 },
57470 /* adc.b${X} $Src16RnQI,$Dst16RnQI */
57471 {
57472 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57474 },
57475 /* adc.b${X} $Src16AnQI,$Dst16RnQI */
57476 {
57477 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57479 },
57480 /* adc.b${X} [$Src16An],$Dst16RnQI */
57481 {
57482 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16,
57483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57484 },
57485 /* adc.b${X} $Src16RnQI,$Dst16AnQI */
57486 {
57487 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57489 },
57490 /* adc.b${X} $Src16AnQI,$Dst16AnQI */
57491 {
57492 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57494 },
57495 /* adc.b${X} [$Src16An],$Dst16AnQI */
57496 {
57497 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16,
57498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57499 },
57500 /* adc.b${X} $Src16RnQI,[$Dst16An] */
57501 {
57502 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57504 },
57505 /* adc.b${X} $Src16AnQI,[$Dst16An] */
57506 {
57507 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57509 },
57510 /* adc.b${X} [$Src16An],[$Dst16An] */
57511 {
57512 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16,
57513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57514 },
57515 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
57516 {
57517 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57519 },
57520 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
57521 {
57522 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57524 },
57525 /* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57526 {
57527 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57529 },
57530 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
57531 {
57532 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57534 },
57535 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
57536 {
57537 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57539 },
57540 /* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57541 {
57542 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57544 },
57545 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
57546 {
57547 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57549 },
57550 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
57551 {
57552 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57554 },
57555 /* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
57556 {
57557 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57559 },
57560 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
57561 {
57562 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57564 },
57565 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
57566 {
57567 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57569 },
57570 /* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
57571 {
57572 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57574 },
57575 /* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
57576 {
57577 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57579 },
57580 /* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
57581 {
57582 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57584 },
57585 /* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
57586 {
57587 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57589 },
57590 /* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
57591 {
57592 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57594 },
57595 /* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
57596 {
57597 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57599 },
57600 /* adc.b${X} [$Src16An],${Dsp-16-u16} */
57601 {
57602 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57604 },
57605 /* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
57606 {
57607 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
57608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57609 },
57610 /* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
57611 {
57612 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40,
57613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57614 },
57615 /* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
57616 {
57617 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
57618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57619 },
57620 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57621 {
57622 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48,
57623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57624 },
57625 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
57626 {
57627 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48,
57628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57629 },
57630 /* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
57631 {
57632 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48,
57633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57634 },
57635 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57636 {
57637 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56,
57638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57639 },
57640 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
57641 {
57642 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56,
57643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57644 },
57645 /* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
57646 {
57647 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56,
57648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57649 },
57650 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
57651 {
57652 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56,
57653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57654 },
57655 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57656 {
57657 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64,
57658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57659 },
57660 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
57661 {
57662 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64,
57663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57664 },
57665 /* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
57666 {
57667 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
57668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57669 },
57670 /* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
57671 {
57672 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32,
57673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57674 },
57675 /* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
57676 {
57677 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
57678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57679 },
57680 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57681 {
57682 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40,
57683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57684 },
57685 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
57686 {
57687 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40,
57688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57689 },
57690 /* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
57691 {
57692 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40,
57693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57694 },
57695 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57696 {
57697 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48,
57698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57699 },
57700 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
57701 {
57702 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48,
57703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57704 },
57705 /* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
57706 {
57707 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48,
57708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57709 },
57710 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
57711 {
57712 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48,
57713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57714 },
57715 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57716 {
57717 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56,
57718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57719 },
57720 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
57721 {
57722 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56,
57723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57724 },
57725 /* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
57726 {
57727 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32,
57728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57729 },
57730 /* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
57731 {
57732 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32,
57733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57734 },
57735 /* adc.w${X} #${Imm-16-HI},[$Dst16An] */
57736 {
57737 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32,
57738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57739 },
57740 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
57741 {
57742 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40,
57743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57744 },
57745 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
57746 {
57747 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40,
57748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57749 },
57750 /* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
57751 {
57752 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40,
57753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57754 },
57755 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
57756 {
57757 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48,
57758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57759 },
57760 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
57761 {
57762 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48,
57763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57764 },
57765 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
57766 {
57767 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48,
57768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57769 },
57770 /* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
57771 {
57772 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24,
57773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57774 },
57775 /* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
57776 {
57777 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24,
57778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57779 },
57780 /* adc.b${X} #${Imm-16-QI},[$Dst16An] */
57781 {
57782 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24,
57783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57784 },
57785 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
57786 {
57787 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32,
57788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57789 },
57790 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
57791 {
57792 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32,
57793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57794 },
57795 /* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
57796 {
57797 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32,
57798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57799 },
57800 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
57801 {
57802 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40,
57803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57804 },
57805 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
57806 {
57807 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40,
57808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57809 },
57810 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
57811 {
57812 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40,
57813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57814 },
57815 /* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
57816 {
57817 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32,
57818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57819 },
57820 /* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
57821 {
57822 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32,
57823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57824 },
57825 /* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
57826 {
57827 M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40,
57828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57829 },
57830 /* add.w${S} #${Imm-8-HI},r0 */
57831 {
57832 M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24,
57833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57834 },
57835 /* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
57836 {
57837 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24,
57838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57839 },
57840 /* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
57841 {
57842 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24,
57843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57844 },
57845 /* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
57846 {
57847 M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32,
57848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57849 },
57850 /* add.b${S} #${Imm-8-QI},r0l */
57851 {
57852 M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16,
57853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57854 },
57855 /* add.l${S} #${Imm1-S},a0 */
57856 {
57857 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8,
57858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57859 },
57860 /* add.l${S} #${Imm1-S},a1 */
57861 {
57862 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8,
57863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57864 },
57865 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57866 {
57867 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57869 },
57870 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
57871 {
57872 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57874 },
57875 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
57876 {
57877 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57879 },
57880 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57881 {
57882 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57884 },
57885 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
57886 {
57887 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57889 },
57890 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
57891 {
57892 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57894 },
57895 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57896 {
57897 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57899 },
57900 /* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57901 {
57902 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57904 },
57905 /* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57906 {
57907 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57909 },
57910 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57911 {
57912 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57914 },
57915 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57916 {
57917 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57919 },
57920 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57921 {
57922 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57924 },
57925 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57926 {
57927 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57929 },
57930 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57931 {
57932 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57934 },
57935 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57936 {
57937 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57939 },
57940 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57941 {
57942 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57944 },
57945 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57946 {
57947 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57949 },
57950 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57951 {
57952 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57954 },
57955 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
57956 {
57957 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57959 },
57960 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57961 {
57962 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57964 },
57965 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57966 {
57967 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57969 },
57970 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
57971 {
57972 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57974 },
57975 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57976 {
57977 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57979 },
57980 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57981 {
57982 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57984 },
57985 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
57986 {
57987 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
57988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57989 },
57990 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57991 {
57992 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
57993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57994 },
57995 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57996 {
57997 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
57998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57999 },
58000 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58001 {
58002 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58004 },
58005 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58006 {
58007 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58009 },
58010 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58011 {
58012 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58014 },
58015 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58016 {
58017 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58019 },
58020 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58021 {
58022 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58024 },
58025 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58026 {
58027 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58029 },
58030 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58031 {
58032 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58034 },
58035 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58036 {
58037 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58039 },
58040 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58041 {
58042 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58044 },
58045 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58046 {
58047 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58049 },
58050 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
58051 {
58052 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58054 },
58055 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
58056 {
58057 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58059 },
58060 /* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
58061 {
58062 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58064 },
58065 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58066 {
58067 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58069 },
58070 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
58071 {
58072 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58074 },
58075 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
58076 {
58077 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58079 },
58080 /* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
58081 {
58082 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58084 },
58085 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58086 {
58087 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58089 },
58090 /* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58091 {
58092 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58094 },
58095 /* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58096 {
58097 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58099 },
58100 /* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58101 {
58102 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58104 },
58105 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58106 {
58107 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58109 },
58110 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58111 {
58112 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58114 },
58115 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58116 {
58117 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58119 },
58120 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58121 {
58122 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58124 },
58125 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58126 {
58127 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58129 },
58130 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58131 {
58132 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58134 },
58135 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58136 {
58137 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58139 },
58140 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58141 {
58142 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58144 },
58145 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58146 {
58147 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58149 },
58150 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58151 {
58152 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58154 },
58155 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58156 {
58157 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58159 },
58160 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58161 {
58162 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58164 },
58165 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58166 {
58167 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58169 },
58170 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58171 {
58172 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58174 },
58175 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58176 {
58177 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58179 },
58180 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58181 {
58182 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58184 },
58185 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58186 {
58187 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58189 },
58190 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58191 {
58192 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58194 },
58195 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58196 {
58197 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58199 },
58200 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58201 {
58202 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58204 },
58205 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58206 {
58207 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58209 },
58210 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58211 {
58212 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58214 },
58215 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58216 {
58217 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58219 },
58220 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58221 {
58222 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58224 },
58225 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58226 {
58227 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58229 },
58230 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58231 {
58232 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58234 },
58235 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58236 {
58237 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58239 },
58240 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58241 {
58242 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58244 },
58245 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58246 {
58247 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58249 },
58250 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58251 {
58252 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58254 },
58255 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58256 {
58257 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58259 },
58260 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
58261 {
58262 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58264 },
58265 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58266 {
58267 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58269 },
58270 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58271 {
58272 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58274 },
58275 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58276 {
58277 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58279 },
58280 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
58281 {
58282 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58284 },
58285 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58286 {
58287 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
58288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58289 },
58290 /* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
58291 {
58292 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
58293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58294 },
58295 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58296 {
58297 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
58298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58299 },
58300 /* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
58301 {
58302 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
58303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58304 },
58305 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58306 {
58307 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
58308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58309 },
58310 /* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58311 {
58312 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
58313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58314 },
58315 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58316 {
58317 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
58318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58319 },
58320 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58321 {
58322 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
58323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58324 },
58325 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58326 {
58327 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
58328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58329 },
58330 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58331 {
58332 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
58333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58334 },
58335 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58336 {
58337 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
58338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58339 },
58340 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58341 {
58342 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
58343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58344 },
58345 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58346 {
58347 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
58348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58349 },
58350 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58351 {
58352 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
58353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58354 },
58355 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58356 {
58357 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
58358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58359 },
58360 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58361 {
58362 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
58363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58364 },
58365 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58366 {
58367 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
58368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58369 },
58370 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58371 {
58372 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
58373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58374 },
58375 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58376 {
58377 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58379 },
58380 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58381 {
58382 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58384 },
58385 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58386 {
58387 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58389 },
58390 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
58391 {
58392 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58394 },
58395 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58396 {
58397 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58399 },
58400 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
58401 {
58402 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58404 },
58405 /* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
58406 {
58407 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58409 },
58410 /* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
58411 {
58412 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58414 },
58415 /* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58416 {
58417 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58419 },
58420 /* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
58421 {
58422 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58424 },
58425 /* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
58426 {
58427 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58429 },
58430 /* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58431 {
58432 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58434 },
58435 /* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
58436 {
58437 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58439 },
58440 /* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
58441 {
58442 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58444 },
58445 /* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58446 {
58447 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58449 },
58450 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58451 {
58452 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58454 },
58455 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58456 {
58457 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58459 },
58460 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58461 {
58462 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58464 },
58465 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58466 {
58467 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58469 },
58470 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58471 {
58472 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58474 },
58475 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58476 {
58477 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58479 },
58480 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58481 {
58482 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58484 },
58485 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58486 {
58487 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58489 },
58490 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58491 {
58492 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58494 },
58495 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
58496 {
58497 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58499 },
58500 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
58501 {
58502 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58504 },
58505 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58506 {
58507 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58509 },
58510 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
58511 {
58512 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58514 },
58515 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
58516 {
58517 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58519 },
58520 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58521 {
58522 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58524 },
58525 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
58526 {
58527 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58529 },
58530 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
58531 {
58532 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58534 },
58535 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58536 {
58537 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58539 },
58540 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
58541 {
58542 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58544 },
58545 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
58546 {
58547 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58549 },
58550 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58551 {
58552 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58554 },
58555 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
58556 {
58557 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58559 },
58560 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
58561 {
58562 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58564 },
58565 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58566 {
58567 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58569 },
58570 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
58571 {
58572 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58574 },
58575 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
58576 {
58577 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58579 },
58580 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58581 {
58582 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58584 },
58585 /* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
58586 {
58587 M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8,
58588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58589 },
58590 /* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
58591 {
58592 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16,
58593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58594 },
58595 /* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
58596 {
58597 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16,
58598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58599 },
58600 /* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
58601 {
58602 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24,
58603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58604 },
58605 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58606 {
58607 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58609 },
58610 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
58611 {
58612 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58614 },
58615 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
58616 {
58617 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58619 },
58620 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58621 {
58622 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58624 },
58625 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
58626 {
58627 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58629 },
58630 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
58631 {
58632 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58634 },
58635 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58636 {
58637 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58639 },
58640 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58641 {
58642 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58644 },
58645 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58646 {
58647 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58649 },
58650 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58651 {
58652 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58654 },
58655 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58656 {
58657 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58659 },
58660 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58661 {
58662 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58664 },
58665 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58666 {
58667 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58669 },
58670 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58671 {
58672 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58674 },
58675 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58676 {
58677 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58679 },
58680 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58681 {
58682 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58684 },
58685 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58686 {
58687 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58689 },
58690 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58691 {
58692 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58694 },
58695 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58696 {
58697 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58699 },
58700 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58701 {
58702 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58704 },
58705 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58706 {
58707 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58709 },
58710 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58711 {
58712 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58714 },
58715 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58716 {
58717 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58719 },
58720 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58721 {
58722 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58724 },
58725 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58726 {
58727 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58729 },
58730 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58731 {
58732 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58734 },
58735 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58736 {
58737 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58739 },
58740 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58741 {
58742 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58744 },
58745 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58746 {
58747 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58749 },
58750 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58751 {
58752 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58754 },
58755 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58756 {
58757 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58759 },
58760 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58761 {
58762 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58764 },
58765 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58766 {
58767 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58769 },
58770 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58771 {
58772 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58774 },
58775 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58776 {
58777 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58779 },
58780 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58781 {
58782 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58784 },
58785 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58786 {
58787 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58789 },
58790 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
58791 {
58792 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58794 },
58795 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
58796 {
58797 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58799 },
58800 /* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
58801 {
58802 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58804 },
58805 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58806 {
58807 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58809 },
58810 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
58811 {
58812 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58814 },
58815 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
58816 {
58817 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58819 },
58820 /* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
58821 {
58822 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58824 },
58825 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58826 {
58827 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58829 },
58830 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58831 {
58832 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58834 },
58835 /* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58836 {
58837 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58839 },
58840 /* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58841 {
58842 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58844 },
58845 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58846 {
58847 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58849 },
58850 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58851 {
58852 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58854 },
58855 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58856 {
58857 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58859 },
58860 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58861 {
58862 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58864 },
58865 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58866 {
58867 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58869 },
58870 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58871 {
58872 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58874 },
58875 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58876 {
58877 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58879 },
58880 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58881 {
58882 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58884 },
58885 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58886 {
58887 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58889 },
58890 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58891 {
58892 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58894 },
58895 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58896 {
58897 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58899 },
58900 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58901 {
58902 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58904 },
58905 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58906 {
58907 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58909 },
58910 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58911 {
58912 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58914 },
58915 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58916 {
58917 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58919 },
58920 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58921 {
58922 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58924 },
58925 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58926 {
58927 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58929 },
58930 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58931 {
58932 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58934 },
58935 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58936 {
58937 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58939 },
58940 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58941 {
58942 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58944 },
58945 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58946 {
58947 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58949 },
58950 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58951 {
58952 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58954 },
58955 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58956 {
58957 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58959 },
58960 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58961 {
58962 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58964 },
58965 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58966 {
58967 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58969 },
58970 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58971 {
58972 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58974 },
58975 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58976 {
58977 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58979 },
58980 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58981 {
58982 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58984 },
58985 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58986 {
58987 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
58988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58989 },
58990 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58991 {
58992 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
58993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58994 },
58995 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58996 {
58997 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
58998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58999 },
59000 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
59001 {
59002 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59004 },
59005 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59006 {
59007 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59009 },
59010 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59011 {
59012 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59014 },
59015 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59016 {
59017 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59019 },
59020 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
59021 {
59022 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59024 },
59025 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59026 {
59027 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
59028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59029 },
59030 /* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
59031 {
59032 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
59033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59034 },
59035 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59036 {
59037 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
59038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59039 },
59040 /* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
59041 {
59042 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
59043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59044 },
59045 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59046 {
59047 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
59048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59049 },
59050 /* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59051 {
59052 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
59053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59054 },
59055 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59056 {
59057 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
59058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59059 },
59060 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59061 {
59062 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
59063 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59064 },
59065 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59066 {
59067 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
59068 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59069 },
59070 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59071 {
59072 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
59073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59074 },
59075 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59076 {
59077 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
59078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59079 },
59080 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59081 {
59082 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
59083 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59084 },
59085 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59086 {
59087 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
59088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59089 },
59090 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59091 {
59092 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
59093 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59094 },
59095 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59096 {
59097 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
59098 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59099 },
59100 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59101 {
59102 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
59103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59104 },
59105 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59106 {
59107 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
59108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59109 },
59110 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59111 {
59112 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
59113 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59114 },
59115 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59116 {
59117 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
59118 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59119 },
59120 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59121 {
59122 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
59123 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59124 },
59125 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59126 {
59127 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
59128 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59129 },
59130 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
59131 {
59132 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
59133 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59134 },
59135 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59136 {
59137 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
59138 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59139 },
59140 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
59141 {
59142 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
59143 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59144 },
59145 /* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
59146 {
59147 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59148 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59149 },
59150 /* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
59151 {
59152 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59154 },
59155 /* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59156 {
59157 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59159 },
59160 /* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
59161 {
59162 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59164 },
59165 /* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
59166 {
59167 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59169 },
59170 /* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59171 {
59172 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59174 },
59175 /* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
59176 {
59177 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59179 },
59180 /* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
59181 {
59182 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59184 },
59185 /* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59186 {
59187 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59189 },
59190 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59191 {
59192 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59194 },
59195 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59196 {
59197 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59199 },
59200 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59201 {
59202 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59204 },
59205 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59206 {
59207 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59209 },
59210 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59211 {
59212 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59214 },
59215 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59216 {
59217 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59219 },
59220 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59221 {
59222 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59224 },
59225 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59226 {
59227 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59229 },
59230 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59231 {
59232 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59234 },
59235 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
59236 {
59237 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59239 },
59240 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
59241 {
59242 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59244 },
59245 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59246 {
59247 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59249 },
59250 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
59251 {
59252 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59254 },
59255 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
59256 {
59257 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59259 },
59260 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59261 {
59262 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59264 },
59265 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
59266 {
59267 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59269 },
59270 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
59271 {
59272 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59273 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59274 },
59275 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59276 {
59277 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59279 },
59280 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
59281 {
59282 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59284 },
59285 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
59286 {
59287 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59289 },
59290 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59291 {
59292 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59294 },
59295 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
59296 {
59297 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59298 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59299 },
59300 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
59301 {
59302 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59303 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59304 },
59305 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59306 {
59307 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59308 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59309 },
59310 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
59311 {
59312 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59314 },
59315 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
59316 {
59317 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59318 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59319 },
59320 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59321 {
59322 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59324 },
59325 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59326 {
59327 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59329 },
59330 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
59331 {
59332 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59333 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59334 },
59335 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
59336 {
59337 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59339 },
59340 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59341 {
59342 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59344 },
59345 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
59346 {
59347 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59348 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59349 },
59350 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
59351 {
59352 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59353 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59354 },
59355 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59356 {
59357 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59359 },
59360 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
59361 {
59362 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59364 },
59365 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
59366 {
59367 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59369 },
59370 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59371 {
59372 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59374 },
59375 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59376 {
59377 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59379 },
59380 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59381 {
59382 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59384 },
59385 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59386 {
59387 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59389 },
59390 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59391 {
59392 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59394 },
59395 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59396 {
59397 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59399 },
59400 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59401 {
59402 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59404 },
59405 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59406 {
59407 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59409 },
59410 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59411 {
59412 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59414 },
59415 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
59416 {
59417 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59419 },
59420 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59421 {
59422 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59424 },
59425 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59426 {
59427 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59429 },
59430 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
59431 {
59432 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59434 },
59435 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59436 {
59437 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59439 },
59440 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59441 {
59442 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59444 },
59445 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
59446 {
59447 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59449 },
59450 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59451 {
59452 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59454 },
59455 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59456 {
59457 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59459 },
59460 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
59461 {
59462 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59464 },
59465 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
59466 {
59467 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59469 },
59470 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
59471 {
59472 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59474 },
59475 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
59476 {
59477 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59479 },
59480 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59481 {
59482 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59484 },
59485 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59486 {
59487 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59489 },
59490 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
59491 {
59492 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59494 },
59495 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
59496 {
59497 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59499 },
59500 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
59501 {
59502 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59504 },
59505 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59506 {
59507 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59509 },
59510 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
59511 {
59512 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59514 },
59515 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
59516 {
59517 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59519 },
59520 /* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
59521 {
59522 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59524 },
59525 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59526 {
59527 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59529 },
59530 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
59531 {
59532 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59534 },
59535 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
59536 {
59537 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59539 },
59540 /* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
59541 {
59542 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59544 },
59545 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59546 {
59547 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59549 },
59550 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
59551 {
59552 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59553 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59554 },
59555 /* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
59556 {
59557 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59558 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59559 },
59560 /* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
59561 {
59562 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59564 },
59565 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59566 {
59567 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59569 },
59570 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59571 {
59572 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59573 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59574 },
59575 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59576 {
59577 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59578 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59579 },
59580 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
59581 {
59582 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59583 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59584 },
59585 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59586 {
59587 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59588 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59589 },
59590 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59591 {
59592 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59593 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59594 },
59595 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59596 {
59597 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59598 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59599 },
59600 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
59601 {
59602 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59604 },
59605 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59606 {
59607 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59608 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59609 },
59610 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59611 {
59612 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59614 },
59615 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59616 {
59617 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59618 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59619 },
59620 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
59621 {
59622 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59624 },
59625 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
59626 {
59627 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59629 },
59630 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59631 {
59632 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59634 },
59635 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
59636 {
59637 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59639 },
59640 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59641 {
59642 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59644 },
59645 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
59646 {
59647 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59649 },
59650 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59651 {
59652 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59654 },
59655 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
59656 {
59657 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59659 },
59660 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59661 {
59662 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59664 },
59665 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
59666 {
59667 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59669 },
59670 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59671 {
59672 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59674 },
59675 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59676 {
59677 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59679 },
59680 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59681 {
59682 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59684 },
59685 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59686 {
59687 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59689 },
59690 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59691 {
59692 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59694 },
59695 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59696 {
59697 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59699 },
59700 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59701 {
59702 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59704 },
59705 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59706 {
59707 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59709 },
59710 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59711 {
59712 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59714 },
59715 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59716 {
59717 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59719 },
59720 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
59721 {
59722 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59724 },
59725 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59726 {
59727 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59729 },
59730 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59731 {
59732 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59734 },
59735 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59736 {
59737 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59739 },
59740 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
59741 {
59742 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59744 },
59745 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59746 {
59747 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59749 },
59750 /* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
59751 {
59752 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59753 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59754 },
59755 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59756 {
59757 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59758 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59759 },
59760 /* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
59761 {
59762 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59763 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59764 },
59765 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59766 {
59767 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59768 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59769 },
59770 /* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59771 {
59772 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59773 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59774 },
59775 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59776 {
59777 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59778 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59779 },
59780 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59781 {
59782 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59783 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59784 },
59785 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59786 {
59787 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59788 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59789 },
59790 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59791 {
59792 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59793 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59794 },
59795 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59796 {
59797 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59798 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59799 },
59800 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59801 {
59802 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59803 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59804 },
59805 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59806 {
59807 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59808 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59809 },
59810 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59811 {
59812 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59813 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59814 },
59815 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59816 {
59817 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59818 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59819 },
59820 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59821 {
59822 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59823 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59824 },
59825 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59826 {
59827 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59828 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59829 },
59830 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59831 {
59832 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59833 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59834 },
59835 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59836 {
59837 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59838 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59839 },
59840 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59841 {
59842 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59843 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59844 },
59845 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59846 {
59847 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59848 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59849 },
59850 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59851 {
59852 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59853 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59854 },
59855 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59856 {
59857 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59859 },
59860 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59861 {
59862 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59864 },
59865 /* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59866 {
59867 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59869 },
59870 /* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59871 {
59872 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59873 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59874 },
59875 /* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59876 {
59877 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59878 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59879 },
59880 /* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59881 {
59882 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59884 },
59885 /* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59886 {
59887 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59889 },
59890 /* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59891 {
59892 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59894 },
59895 /* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59896 {
59897 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59899 },
59900 /* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59901 {
59902 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59904 },
59905 /* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59906 {
59907 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59909 },
59910 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59911 {
59912 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59914 },
59915 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59916 {
59917 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59919 },
59920 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59921 {
59922 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59924 },
59925 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59926 {
59927 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59929 },
59930 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59931 {
59932 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59934 },
59935 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59936 {
59937 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59939 },
59940 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59941 {
59942 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59944 },
59945 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59946 {
59947 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59949 },
59950 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59951 {
59952 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59954 },
59955 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
59956 {
59957 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59959 },
59960 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
59961 {
59962 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59964 },
59965 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59966 {
59967 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59969 },
59970 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
59971 {
59972 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59974 },
59975 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
59976 {
59977 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59979 },
59980 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59981 {
59982 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59984 },
59985 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
59986 {
59987 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
59988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59989 },
59990 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
59991 {
59992 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
59993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59994 },
59995 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59996 {
59997 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
59998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59999 },
60000 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
60001 {
60002 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60004 },
60005 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
60006 {
60007 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60009 },
60010 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
60011 {
60012 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60014 },
60015 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
60016 {
60017 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60019 },
60020 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
60021 {
60022 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60024 },
60025 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
60026 {
60027 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60029 },
60030 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
60031 {
60032 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60034 },
60035 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
60036 {
60037 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60039 },
60040 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
60041 {
60042 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60044 },
60045 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
60046 {
60047 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60048 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60049 },
60050 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
60051 {
60052 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60053 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60054 },
60055 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
60056 {
60057 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60058 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60059 },
60060 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
60061 {
60062 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24,
60063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60064 },
60065 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
60066 {
60067 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24,
60068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60069 },
60070 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
60071 {
60072 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24,
60073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60074 },
60075 /* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60076 {
60077 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60079 },
60080 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60081 {
60082 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60084 },
60085 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60086 {
60087 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60089 },
60090 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60091 {
60092 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60094 },
60095 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60096 {
60097 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60099 },
60100 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60101 {
60102 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60104 },
60105 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60106 {
60107 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60109 },
60110 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60111 {
60112 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60114 },
60115 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60116 {
60117 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60119 },
60120 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60121 {
60122 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60124 },
60125 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60126 {
60127 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60129 },
60130 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60131 {
60132 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60134 },
60135 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60136 {
60137 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60139 },
60140 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60141 {
60142 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60144 },
60145 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60146 {
60147 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60149 },
60150 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60151 {
60152 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60153 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60154 },
60155 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60156 {
60157 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60158 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60159 },
60160 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60161 {
60162 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60163 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60164 },
60165 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60166 {
60167 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60168 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60169 },
60170 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60171 {
60172 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60173 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60174 },
60175 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60176 {
60177 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60178 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60179 },
60180 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
60181 {
60182 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
60183 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60184 },
60185 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
60186 {
60187 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
60188 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60189 },
60190 /* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
60191 {
60192 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32,
60193 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60194 },
60195 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
60196 {
60197 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32,
60198 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60199 },
60200 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
60201 {
60202 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32,
60203 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60204 },
60205 /* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
60206 {
60207 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32,
60208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60209 },
60210 /* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60211 {
60212 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32,
60213 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60214 },
60215 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60216 {
60217 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32,
60218 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60219 },
60220 /* add.w${G} ${Dsp-16-u16},[$Dst16An] */
60221 {
60222 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32,
60223 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60224 },
60225 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60226 {
60227 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60229 },
60230 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60231 {
60232 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60233 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60234 },
60235 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60236 {
60237 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60239 },
60240 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60241 {
60242 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60243 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60244 },
60245 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60246 {
60247 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60249 },
60250 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60251 {
60252 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60253 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60254 },
60255 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60256 {
60257 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60259 },
60260 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60261 {
60262 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60264 },
60265 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60266 {
60267 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60269 },
60270 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60271 {
60272 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60274 },
60275 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60276 {
60277 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60279 },
60280 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60281 {
60282 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60284 },
60285 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60286 {
60287 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60289 },
60290 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60291 {
60292 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60294 },
60295 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60296 {
60297 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60299 },
60300 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60301 {
60302 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
60303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60304 },
60305 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60306 {
60307 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
60308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60309 },
60310 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
60311 {
60312 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48,
60313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60314 },
60315 /* add.w${G} $Src16RnHI,$Dst16RnHI */
60316 {
60317 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
60318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60319 },
60320 /* add.w${G} $Src16AnHI,$Dst16RnHI */
60321 {
60322 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
60323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60324 },
60325 /* add.w${G} [$Src16An],$Dst16RnHI */
60326 {
60327 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16,
60328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60329 },
60330 /* add.w${G} $Src16RnHI,$Dst16AnHI */
60331 {
60332 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16,
60333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60334 },
60335 /* add.w${G} $Src16AnHI,$Dst16AnHI */
60336 {
60337 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16,
60338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60339 },
60340 /* add.w${G} [$Src16An],$Dst16AnHI */
60341 {
60342 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16,
60343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60344 },
60345 /* add.w${G} $Src16RnHI,[$Dst16An] */
60346 {
60347 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16,
60348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60349 },
60350 /* add.w${G} $Src16AnHI,[$Dst16An] */
60351 {
60352 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16,
60353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60354 },
60355 /* add.w${G} [$Src16An],[$Dst16An] */
60356 {
60357 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16,
60358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60359 },
60360 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
60361 {
60362 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60363 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60364 },
60365 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
60366 {
60367 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60369 },
60370 /* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60371 {
60372 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60374 },
60375 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
60376 {
60377 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60378 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60379 },
60380 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
60381 {
60382 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60383 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60384 },
60385 /* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60386 {
60387 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60388 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60389 },
60390 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
60391 {
60392 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60394 },
60395 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
60396 {
60397 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60398 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60399 },
60400 /* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
60401 {
60402 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60404 },
60405 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
60406 {
60407 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60409 },
60410 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
60411 {
60412 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60413 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60414 },
60415 /* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
60416 {
60417 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60418 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60419 },
60420 /* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
60421 {
60422 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60423 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60424 },
60425 /* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
60426 {
60427 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60428 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60429 },
60430 /* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
60431 {
60432 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60433 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60434 },
60435 /* add.w${G} $Src16RnHI,${Dsp-16-u16} */
60436 {
60437 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60438 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60439 },
60440 /* add.w${G} $Src16AnHI,${Dsp-16-u16} */
60441 {
60442 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60444 },
60445 /* add.w${G} [$Src16An],${Dsp-16-u16} */
60446 {
60447 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32,
60448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60449 },
60450 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
60451 {
60452 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60454 },
60455 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
60456 {
60457 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60459 },
60460 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
60461 {
60462 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60464 },
60465 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
60466 {
60467 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24,
60468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60469 },
60470 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
60471 {
60472 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60474 },
60475 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
60476 {
60477 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60479 },
60480 /* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60481 {
60482 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60483 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60484 },
60485 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60486 {
60487 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60488 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60489 },
60490 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60491 {
60492 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60494 },
60495 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60496 {
60497 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60499 },
60500 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60501 {
60502 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60503 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60504 },
60505 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60506 {
60507 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60508 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60509 },
60510 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60511 {
60512 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60514 },
60515 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60516 {
60517 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60519 },
60520 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60521 {
60522 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60523 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60524 },
60525 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60526 {
60527 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60529 },
60530 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60531 {
60532 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60533 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60534 },
60535 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60536 {
60537 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60538 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60539 },
60540 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60541 {
60542 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60544 },
60545 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60546 {
60547 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60549 },
60550 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60551 {
60552 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60554 },
60555 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60556 {
60557 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60559 },
60560 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60561 {
60562 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60564 },
60565 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60566 {
60567 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60569 },
60570 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60571 {
60572 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60574 },
60575 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60576 {
60577 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60579 },
60580 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60581 {
60582 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60584 },
60585 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
60586 {
60587 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60589 },
60590 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
60591 {
60592 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60594 },
60595 /* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
60596 {
60597 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32,
60598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60599 },
60600 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
60601 {
60602 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32,
60603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60604 },
60605 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
60606 {
60607 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32,
60608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60609 },
60610 /* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
60611 {
60612 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32,
60613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60614 },
60615 /* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60616 {
60617 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60619 },
60620 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60621 {
60622 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60624 },
60625 /* add.b${G} ${Dsp-16-u16},[$Dst16An] */
60626 {
60627 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32,
60628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60629 },
60630 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60631 {
60632 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60633 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60634 },
60635 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60636 {
60637 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60638 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60639 },
60640 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60641 {
60642 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60643 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60644 },
60645 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60646 {
60647 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60649 },
60650 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60651 {
60652 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60653 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60654 },
60655 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60656 {
60657 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60658 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60659 },
60660 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60661 {
60662 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60663 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60664 },
60665 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60666 {
60667 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60668 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60669 },
60670 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60671 {
60672 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60673 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60674 },
60675 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60676 {
60677 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60678 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60679 },
60680 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60681 {
60682 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60683 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60684 },
60685 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60686 {
60687 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60688 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60689 },
60690 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60691 {
60692 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60693 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60694 },
60695 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60696 {
60697 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60698 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60699 },
60700 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60701 {
60702 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60703 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60704 },
60705 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60706 {
60707 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60708 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60709 },
60710 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60711 {
60712 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60713 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60714 },
60715 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60716 {
60717 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48,
60718 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60719 },
60720 /* add.b${G} $Src16RnQI,$Dst16RnQI */
60721 {
60722 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60723 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60724 },
60725 /* add.b${G} $Src16AnQI,$Dst16RnQI */
60726 {
60727 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60728 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60729 },
60730 /* add.b${G} [$Src16An],$Dst16RnQI */
60731 {
60732 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16,
60733 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60734 },
60735 /* add.b${G} $Src16RnQI,$Dst16AnQI */
60736 {
60737 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16,
60738 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60739 },
60740 /* add.b${G} $Src16AnQI,$Dst16AnQI */
60741 {
60742 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16,
60743 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60744 },
60745 /* add.b${G} [$Src16An],$Dst16AnQI */
60746 {
60747 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16,
60748 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60749 },
60750 /* add.b${G} $Src16RnQI,[$Dst16An] */
60751 {
60752 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60754 },
60755 /* add.b${G} $Src16AnQI,[$Dst16An] */
60756 {
60757 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60759 },
60760 /* add.b${G} [$Src16An],[$Dst16An] */
60761 {
60762 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16,
60763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60764 },
60765 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60766 {
60767 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60769 },
60770 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60771 {
60772 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60774 },
60775 /* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60776 {
60777 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60779 },
60780 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60781 {
60782 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60784 },
60785 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60786 {
60787 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60789 },
60790 /* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60791 {
60792 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60794 },
60795 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60796 {
60797 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60799 },
60800 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60801 {
60802 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60804 },
60805 /* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60806 {
60807 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60809 },
60810 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60811 {
60812 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60814 },
60815 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60816 {
60817 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60819 },
60820 /* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60821 {
60822 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60824 },
60825 /* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60826 {
60827 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60829 },
60830 /* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60831 {
60832 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60834 },
60835 /* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60836 {
60837 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60839 },
60840 /* add.b${G} $Src16RnQI,${Dsp-16-u16} */
60841 {
60842 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60844 },
60845 /* add.b${G} $Src16AnQI,${Dsp-16-u16} */
60846 {
60847 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60849 },
60850 /* add.b${G} [$Src16An],${Dsp-16-u16} */
60851 {
60852 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32,
60853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60854 },
60855 /* add.b${S} #${Imm-8-QI},r0l */
60856 {
60857 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16,
60858 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60859 },
60860 /* add.b${S} #${Imm-8-QI},r0h */
60861 {
60862 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16,
60863 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60864 },
60865 /* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60866 {
60867 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24,
60868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60869 },
60870 /* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60871 {
60872 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24,
60873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60874 },
60875 /* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60876 {
60877 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32,
60878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60879 },
60880 /* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
60881 {
60882 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
60883 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60884 },
60885 /* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
60886 {
60887 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16,
60888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60889 },
60890 /* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60891 {
60892 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
60893 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60894 },
60895 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60896 {
60897 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
60898 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60899 },
60900 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60901 {
60902 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
60903 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60904 },
60905 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60906 {
60907 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
60908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60909 },
60910 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60911 {
60912 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
60913 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60914 },
60915 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60916 {
60917 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
60918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60919 },
60920 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60921 {
60922 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
60923 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60924 },
60925 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60926 {
60927 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
60928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60929 },
60930 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
60931 {
60932 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
60933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60934 },
60935 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
60936 {
60937 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
60938 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60939 },
60940 /* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60941 {
60942 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
60943 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60944 },
60945 /* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60946 {
60947 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16,
60948 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60949 },
60950 /* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60951 {
60952 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
60953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60954 },
60955 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60956 {
60957 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
60958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60959 },
60960 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60961 {
60962 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
60963 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60964 },
60965 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60966 {
60967 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
60968 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60969 },
60970 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60971 {
60972 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
60973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60974 },
60975 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60976 {
60977 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
60978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60979 },
60980 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60981 {
60982 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
60983 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60984 },
60985 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60986 {
60987 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
60988 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60989 },
60990 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
60991 {
60992 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
60993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60994 },
60995 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
60996 {
60997 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
60998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60999 },
61000 /* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
61001 {
61002 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
61003 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61004 },
61005 /* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
61006 {
61007 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16,
61008 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61009 },
61010 /* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
61011 {
61012 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
61013 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61014 },
61015 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61016 {
61017 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
61018 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61019 },
61020 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61021 {
61022 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
61023 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61024 },
61025 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61026 {
61027 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
61028 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61029 },
61030 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
61031 {
61032 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
61033 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61034 },
61035 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
61036 {
61037 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
61038 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61039 },
61040 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
61041 {
61042 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
61043 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61044 },
61045 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
61046 {
61047 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
61048 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61049 },
61050 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
61051 {
61052 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
61053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61054 },
61055 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
61056 {
61057 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
61058 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61059 },
61060 /* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
61061 {
61062 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16,
61063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61064 },
61065 /* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
61066 {
61067 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16,
61068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61069 },
61070 /* add.w${Q} #${Imm-8-s4},[$Dst16An] */
61071 {
61072 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16,
61073 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61074 },
61075 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61076 {
61077 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24,
61078 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61079 },
61080 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61081 {
61082 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32,
61083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61084 },
61085 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61086 {
61087 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24,
61088 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61089 },
61090 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61091 {
61092 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32,
61093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61094 },
61095 /* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61096 {
61097 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24,
61098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61099 },
61100 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
61101 {
61102 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32,
61103 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61104 },
61105 /* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
61106 {
61107 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16,
61108 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61109 },
61110 /* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
61111 {
61112 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16,
61113 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61114 },
61115 /* add.b${Q} #${Imm-8-s4},[$Dst16An] */
61116 {
61117 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16,
61118 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61119 },
61120 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61121 {
61122 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24,
61123 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61124 },
61125 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61126 {
61127 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32,
61128 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61129 },
61130 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61131 {
61132 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24,
61133 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61134 },
61135 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61136 {
61137 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32,
61138 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61139 },
61140 /* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61141 {
61142 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24,
61143 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61144 },
61145 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
61146 {
61147 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32,
61148 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61149 },
61150 /* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
61151 {
61152 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
61153 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61154 },
61155 /* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
61156 {
61157 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32,
61158 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61159 },
61160 /* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
61161 {
61162 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
61163 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61164 },
61165 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61166 {
61167 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40,
61168 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61169 },
61170 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61171 {
61172 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40,
61173 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61174 },
61175 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61176 {
61177 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40,
61178 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61179 },
61180 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61181 {
61182 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48,
61183 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61184 },
61185 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61186 {
61187 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48,
61188 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61189 },
61190 /* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
61191 {
61192 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48,
61193 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61194 },
61195 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61196 {
61197 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48,
61198 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61199 },
61200 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61201 {
61202 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56,
61203 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61204 },
61205 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
61206 {
61207 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56,
61208 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61209 },
61210 /* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
61211 {
61212 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
61213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61214 },
61215 /* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
61216 {
61217 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24,
61218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61219 },
61220 /* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
61221 {
61222 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
61223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61224 },
61225 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61226 {
61227 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32,
61228 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61229 },
61230 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61231 {
61232 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32,
61233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61234 },
61235 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61236 {
61237 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32,
61238 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61239 },
61240 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61241 {
61242 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40,
61243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61244 },
61245 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61246 {
61247 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40,
61248 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61249 },
61250 /* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
61251 {
61252 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40,
61253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61254 },
61255 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61256 {
61257 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40,
61258 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61259 },
61260 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61261 {
61262 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48,
61263 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61264 },
61265 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
61266 {
61267 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48,
61268 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61269 },
61270 /* add.w${G} #${Imm-16-HI},$Dst16RnHI */
61271 {
61272 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32,
61273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61274 },
61275 /* add.w${G} #${Imm-16-HI},$Dst16AnHI */
61276 {
61277 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32,
61278 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61279 },
61280 /* add.w${G} #${Imm-16-HI},[$Dst16An] */
61281 {
61282 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32,
61283 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61284 },
61285 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
61286 {
61287 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40,
61288 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61289 },
61290 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61291 {
61292 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40,
61293 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61294 },
61295 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61296 {
61297 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40,
61298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61299 },
61300 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
61301 {
61302 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48,
61303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61304 },
61305 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61306 {
61307 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48,
61308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61309 },
61310 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61311 {
61312 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48,
61313 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61314 },
61315 /* add.b${G} #${Imm-16-QI},$Dst16RnQI */
61316 {
61317 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24,
61318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61319 },
61320 /* add.b${G} #${Imm-16-QI},$Dst16AnQI */
61321 {
61322 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24,
61323 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61324 },
61325 /* add.b${G} #${Imm-16-QI},[$Dst16An] */
61326 {
61327 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24,
61328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61329 },
61330 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
61331 {
61332 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32,
61333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61334 },
61335 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61336 {
61337 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32,
61338 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61339 },
61340 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61341 {
61342 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32,
61343 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61344 },
61345 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
61346 {
61347 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40,
61348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61349 },
61350 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61351 {
61352 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40,
61353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61354 },
61355 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61356 {
61357 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40,
61358 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61359 },
61360 /* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
61361 {
61362 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48,
61363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61364 },
61365 /* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
61366 {
61367 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48,
61368 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61369 },
61370 /* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
61371 {
61372 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48,
61373 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61374 },
61375 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61376 {
61377 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56,
61378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61379 },
61380 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
61381 {
61382 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56,
61383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61384 },
61385 /* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
61386 {
61387 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56,
61388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61389 },
61390 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61391 {
61392 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64,
61393 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61394 },
61395 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
61396 {
61397 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64,
61398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61399 },
61400 /* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
61401 {
61402 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64,
61403 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61404 },
61405 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
61406 {
61407 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64,
61408 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61409 },
61410 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61411 {
61412 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72,
61413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61414 },
61415 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
61416 {
61417 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72,
61418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61419 },
61420 /* adcf.w $Dst32RnUnprefixedHI */
61421 {
61422 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16,
61423 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61424 },
61425 /* adcf.w $Dst32AnUnprefixedHI */
61426 {
61427 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16,
61428 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61429 },
61430 /* adcf.w [$Dst32AnUnprefixed] */
61431 {
61432 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16,
61433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61434 },
61435 /* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61436 {
61437 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24,
61438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61439 },
61440 /* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61441 {
61442 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32,
61443 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61444 },
61445 /* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61446 {
61447 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40,
61448 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61449 },
61450 /* adcf.w ${Dsp-16-u8}[sb] */
61451 {
61452 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24,
61453 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61454 },
61455 /* adcf.w ${Dsp-16-u16}[sb] */
61456 {
61457 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32,
61458 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61459 },
61460 /* adcf.w ${Dsp-16-s8}[fb] */
61461 {
61462 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24,
61463 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61464 },
61465 /* adcf.w ${Dsp-16-s16}[fb] */
61466 {
61467 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32,
61468 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61469 },
61470 /* adcf.w ${Dsp-16-u16} */
61471 {
61472 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32,
61473 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61474 },
61475 /* adcf.w ${Dsp-16-u24} */
61476 {
61477 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40,
61478 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61479 },
61480 /* adcf.b $Dst32RnUnprefixedQI */
61481 {
61482 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16,
61483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61484 },
61485 /* adcf.b $Dst32AnUnprefixedQI */
61486 {
61487 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16,
61488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61489 },
61490 /* adcf.b [$Dst32AnUnprefixed] */
61491 {
61492 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16,
61493 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61494 },
61495 /* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61496 {
61497 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24,
61498 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61499 },
61500 /* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61501 {
61502 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32,
61503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61504 },
61505 /* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61506 {
61507 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40,
61508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61509 },
61510 /* adcf.b ${Dsp-16-u8}[sb] */
61511 {
61512 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24,
61513 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61514 },
61515 /* adcf.b ${Dsp-16-u16}[sb] */
61516 {
61517 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32,
61518 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61519 },
61520 /* adcf.b ${Dsp-16-s8}[fb] */
61521 {
61522 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24,
61523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61524 },
61525 /* adcf.b ${Dsp-16-s16}[fb] */
61526 {
61527 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32,
61528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61529 },
61530 /* adcf.b ${Dsp-16-u16} */
61531 {
61532 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32,
61533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61534 },
61535 /* adcf.b ${Dsp-16-u24} */
61536 {
61537 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40,
61538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61539 },
61540 /* adcf.w $Dst16RnHI */
61541 {
61542 M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16,
61543 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61544 },
61545 /* adcf.w $Dst16AnHI */
61546 {
61547 M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16,
61548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61549 },
61550 /* adcf.w [$Dst16An] */
61551 {
61552 M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16,
61553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61554 },
61555 /* adcf.w ${Dsp-16-u8}[$Dst16An] */
61556 {
61557 M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24,
61558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61559 },
61560 /* adcf.w ${Dsp-16-u16}[$Dst16An] */
61561 {
61562 M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32,
61563 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61564 },
61565 /* adcf.w ${Dsp-16-u8}[sb] */
61566 {
61567 M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24,
61568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61569 },
61570 /* adcf.w ${Dsp-16-u16}[sb] */
61571 {
61572 M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32,
61573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61574 },
61575 /* adcf.w ${Dsp-16-s8}[fb] */
61576 {
61577 M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24,
61578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61579 },
61580 /* adcf.w ${Dsp-16-u16} */
61581 {
61582 M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32,
61583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61584 },
61585 /* adcf.b $Dst16RnQI */
61586 {
61587 M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16,
61588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61589 },
61590 /* adcf.b $Dst16AnQI */
61591 {
61592 M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16,
61593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61594 },
61595 /* adcf.b [$Dst16An] */
61596 {
61597 M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16,
61598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61599 },
61600 /* adcf.b ${Dsp-16-u8}[$Dst16An] */
61601 {
61602 M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24,
61603 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61604 },
61605 /* adcf.b ${Dsp-16-u16}[$Dst16An] */
61606 {
61607 M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32,
61608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61609 },
61610 /* adcf.b ${Dsp-16-u8}[sb] */
61611 {
61612 M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24,
61613 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61614 },
61615 /* adcf.b ${Dsp-16-u16}[sb] */
61616 {
61617 M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32,
61618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61619 },
61620 /* adcf.b ${Dsp-16-s8}[fb] */
61621 {
61622 M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24,
61623 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61624 },
61625 /* adcf.b ${Dsp-16-u16} */
61626 {
61627 M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32,
61628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61629 },
61630 /* abs.w $Dst32RnUnprefixedHI */
61631 {
61632 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16,
61633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61634 },
61635 /* abs.w $Dst32AnUnprefixedHI */
61636 {
61637 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16,
61638 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61639 },
61640 /* abs.w [$Dst32AnUnprefixed] */
61641 {
61642 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16,
61643 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61644 },
61645 /* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61646 {
61647 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24,
61648 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61649 },
61650 /* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61651 {
61652 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32,
61653 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61654 },
61655 /* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61656 {
61657 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40,
61658 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61659 },
61660 /* abs.w ${Dsp-16-u8}[sb] */
61661 {
61662 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24,
61663 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61664 },
61665 /* abs.w ${Dsp-16-u16}[sb] */
61666 {
61667 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32,
61668 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61669 },
61670 /* abs.w ${Dsp-16-s8}[fb] */
61671 {
61672 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24,
61673 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61674 },
61675 /* abs.w ${Dsp-16-s16}[fb] */
61676 {
61677 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32,
61678 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61679 },
61680 /* abs.w ${Dsp-16-u16} */
61681 {
61682 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32,
61683 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61684 },
61685 /* abs.w ${Dsp-16-u24} */
61686 {
61687 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40,
61688 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61689 },
61690 /* abs.b $Dst32RnUnprefixedQI */
61691 {
61692 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16,
61693 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61694 },
61695 /* abs.b $Dst32AnUnprefixedQI */
61696 {
61697 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16,
61698 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61699 },
61700 /* abs.b [$Dst32AnUnprefixed] */
61701 {
61702 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16,
61703 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61704 },
61705 /* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61706 {
61707 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24,
61708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61709 },
61710 /* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61711 {
61712 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32,
61713 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61714 },
61715 /* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61716 {
61717 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40,
61718 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61719 },
61720 /* abs.b ${Dsp-16-u8}[sb] */
61721 {
61722 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24,
61723 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61724 },
61725 /* abs.b ${Dsp-16-u16}[sb] */
61726 {
61727 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32,
61728 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61729 },
61730 /* abs.b ${Dsp-16-s8}[fb] */
61731 {
61732 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24,
61733 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61734 },
61735 /* abs.b ${Dsp-16-s16}[fb] */
61736 {
61737 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32,
61738 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61739 },
61740 /* abs.b ${Dsp-16-u16} */
61741 {
61742 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32,
61743 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61744 },
61745 /* abs.b ${Dsp-16-u24} */
61746 {
61747 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40,
61748 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61749 },
61750 /* abs.w $Dst16RnHI */
61751 {
61752 M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16,
61753 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61754 },
61755 /* abs.w $Dst16AnHI */
61756 {
61757 M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16,
61758 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61759 },
61760 /* abs.w [$Dst16An] */
61761 {
61762 M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16,
61763 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61764 },
61765 /* abs.w ${Dsp-16-u8}[$Dst16An] */
61766 {
61767 M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24,
61768 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61769 },
61770 /* abs.w ${Dsp-16-u16}[$Dst16An] */
61771 {
61772 M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32,
61773 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61774 },
61775 /* abs.w ${Dsp-16-u8}[sb] */
61776 {
61777 M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24,
61778 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61779 },
61780 /* abs.w ${Dsp-16-u16}[sb] */
61781 {
61782 M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32,
61783 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61784 },
61785 /* abs.w ${Dsp-16-s8}[fb] */
61786 {
61787 M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24,
61788 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61789 },
61790 /* abs.w ${Dsp-16-u16} */
61791 {
61792 M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32,
61793 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61794 },
61795 /* abs.b $Dst16RnQI */
61796 {
61797 M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16,
61798 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61799 },
61800 /* abs.b $Dst16AnQI */
61801 {
61802 M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16,
61803 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61804 },
61805 /* abs.b [$Dst16An] */
61806 {
61807 M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16,
61808 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61809 },
61810 /* abs.b ${Dsp-16-u8}[$Dst16An] */
61811 {
61812 M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24,
61813 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61814 },
61815 /* abs.b ${Dsp-16-u16}[$Dst16An] */
61816 {
61817 M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32,
61818 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61819 },
61820 /* abs.b ${Dsp-16-u8}[sb] */
61821 {
61822 M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24,
61823 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61824 },
61825 /* abs.b ${Dsp-16-u16}[sb] */
61826 {
61827 M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32,
61828 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61829 },
61830 /* abs.b ${Dsp-16-s8}[fb] */
61831 {
61832 M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24,
61833 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61834 },
61835 /* abs.b ${Dsp-16-u16} */
61836 {
61837 M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
61838 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61839 },
61840 /* add.w$Q #${Imm-12-s4},sp */
61841 {
61842 M32C_INSN_ADD16_WQ_SP, "add16-wQ-sp", "add.w", 16,
61843 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61844 },
61845 /* add.b$G #${Imm-16-QI},sp */
61846 {
61847 M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24,
61848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61849 },
61850 /* add.w$G #${Imm-16-HI},sp */
61851 {
61852 M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32,
61853 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61854 },
61855 /* add.l$Q #${Imm3-S},sp */
61856 {
61857 M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8,
61858 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61859 },
61860 /* add.l$S #${Imm-16-QI},sp */
61861 {
61862 M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24,
61863 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61864 },
61865 /* add.l$G #${Imm-16-HI},sp */
61866 {
61867 M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32,
61868 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61869 },
61870 /* dadc.b #${Imm-16-QI} */
61871 {
61872 M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24,
61873 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61874 },
61875 /* dadc.w #${Imm-16-HI} */
61876 {
61877 M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32,
61878 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61879 },
61880 /* dadc.b r0h,r0l */
61881 {
61882 M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16,
61883 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61884 },
61885 /* dadc.w r1,r0 */
61886 {
61887 M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16,
61888 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61889 },
61890 /* dadd.b #${Imm-16-QI} */
61891 {
61892 M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24,
61893 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61894 },
61895 /* dadd.w #${Imm-16-HI} */
61896 {
61897 M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32,
61898 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61899 },
61900 /* dadd.b r0h,r0l */
61901 {
61902 M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16,
61903 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61904 },
61905 /* dadd.w r1,r0 */
61906 {
61907 M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16,
61908 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61909 },
61910 /* bm$cond16c c */
61911 {
61912 M32C_INSN_BM16_C, "bm16-c", "bm", 16,
61913 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61914 },
61915 /* bm$cond32 c */
61916 {
61917 M32C_INSN_BM32_C, "bm32-c", "bm", 16,
61918 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61919 },
61920 /* brk */
61921 {
61922 M32C_INSN_BRK16, "brk16", "brk", 8,
61923 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61924 },
61925 /* brk */
61926 {
61927 M32C_INSN_BRK32, "brk32", "brk", 8,
61928 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61929 },
61930 /* brk2 */
61931 {
61932 M32C_INSN_BRK232, "brk232", "brk2", 8,
61933 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61934 },
61935 /* dec.w ${Dst16An-S} */
61936 {
61937 M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8,
61938 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61939 },
61940 /* div.b #${Imm-16-QI} */
61941 {
61942 M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24,
61943 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61944 },
61945 /* div.w #${Imm-16-HI} */
61946 {
61947 M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32,
61948 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61949 },
61950 /* div.b #${Imm-16-QI} */
61951 {
61952 M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24,
61953 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61954 },
61955 /* div.w #${Imm-16-HI} */
61956 {
61957 M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32,
61958 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61959 },
61960 /* divu.b #${Imm-16-QI} */
61961 {
61962 M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24,
61963 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61964 },
61965 /* divu.w #${Imm-16-HI} */
61966 {
61967 M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32,
61968 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61969 },
61970 /* divu.b #${Imm-16-QI} */
61971 {
61972 M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24,
61973 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61974 },
61975 /* divu.w #${Imm-16-HI} */
61976 {
61977 M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32,
61978 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61979 },
61980 /* divx.b #${Imm-16-QI} */
61981 {
61982 M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24,
61983 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61984 },
61985 /* divx.w #${Imm-16-HI} */
61986 {
61987 M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32,
61988 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61989 },
61990 /* divx.b #${Imm-16-QI} */
61991 {
61992 M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24,
61993 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61994 },
61995 /* divx.w #${Imm-16-HI} */
61996 {
61997 M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32,
61998 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61999 },
62000 /* dsbb.b #${Imm-16-QI} */
62001 {
62002 M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24,
62003 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62004 },
62005 /* dsbb.w #${Imm-16-HI} */
62006 {
62007 M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32,
62008 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62009 },
62010 /* dsbb.b r0h,r0l */
62011 {
62012 M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16,
62013 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62014 },
62015 /* dsbb.w r1,r0 */
62016 {
62017 M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16,
62018 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62019 },
62020 /* dsub.b #${Imm-16-QI} */
62021 {
62022 M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24,
62023 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62024 },
62025 /* dsub.w #${Imm-16-HI} */
62026 {
62027 M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32,
62028 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62029 },
62030 /* dsub.b r0h,r0l */
62031 {
62032 M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16,
62033 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62034 },
62035 /* dsub.w r1,r0 */
62036 {
62037 M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16,
62038 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62039 },
62040 /* enter #${Dsp-16-u8} */
62041 {
62042 M32C_INSN_ENTER16, "enter16", "enter", 24,
62043 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62044 },
62045 /* exitd */
62046 {
62047 M32C_INSN_EXITD16, "exitd16", "exitd", 16,
62048 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62049 },
62050 /* enter #${Dsp-8-u8} */
62051 {
62052 M32C_INSN_ENTER32, "enter32", "enter", 16,
62053 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62054 },
62055 /* exitd */
62056 {
62057 M32C_INSN_EXITD32, "exitd32", "exitd", 8,
62058 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62059 },
62060 /* fclr ${flags16} */
62061 {
62062 M32C_INSN_FCLR16, "fclr16", "fclr", 16,
62063 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62064 },
62065 /* fset ${flags16} */
62066 {
62067 M32C_INSN_FSET16, "fset16", "fset", 16,
62068 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62069 },
62070 /* fclr ${flags32} */
62071 {
62072 M32C_INSN_FCLR, "fclr", "fclr", 16,
62073 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62074 },
62075 /* fset ${flags32} */
62076 {
62077 M32C_INSN_FSET, "fset", "fset", 16,
62078 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62079 },
62080 /* inc.w ${Dst16An-S} */
62081 {
62082 M32C_INSN_INC16_W, "inc16.w", "inc.w", 8,
62083 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62084 },
62085 /* freit */
62086 {
62087 M32C_INSN_FREIT32, "freit32", "freit", 8,
62088 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62089 },
62090 /* int #${Dsp-10-u6} */
62091 {
62092 M32C_INSN_INT16, "int16", "int", 16,
62093 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62094 },
62095 /* into */
62096 {
62097 M32C_INSN_INTO16, "into16", "into", 8,
62098 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62099 },
62100 /* int #${Dsp-8-u6} */
62101 {
62102 M32C_INSN_INT32, "int32", "int", 16,
62103 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62104 },
62105 /* into */
62106 {
62107 M32C_INSN_INTO32, "into32", "into", 8,
62108 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62109 },
62110 /* j$cond16j5 ${Lab-8-8} */
62111 {
62112 M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
62113 { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62114 },
62115 /* j$cond16j ${Lab-16-8} */
62116 {
62117 M32C_INSN_JCND16, "jcnd16", "j", 24,
62118 { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62119 },
62120 /* j$cond32j ${Lab-8-8} */
62121 {
62122 M32C_INSN_JCND32, "jcnd32", "j", 16,
62123 { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62124 },
62125 /* jmp.s ${Lab-5-3} */
62126 {
62127 M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
62128 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62129 },
62130 /* jmp.b ${Lab-8-8} */
62131 {
62132 M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
62133 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62134 },
62135 /* jmp.w ${Lab-8-16} */
62136 {
62137 M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
62138 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62139 },
62140 /* jmp.a ${Lab-8-24} */
62141 {
62142 M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32,
62143 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62144 },
62145 /* jmps #${Imm-8-QI} */
62146 {
62147 M32C_INSN_JMPS16, "jmps16", "jmps", 16,
62148 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62149 },
62150 /* jmp.s ${Lab32-jmp-s} */
62151 {
62152 M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
62153 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62154 },
62155 /* jmp.b ${Lab-8-8} */
62156 {
62157 M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
62158 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62159 },
62160 /* jmp.w ${Lab-8-16} */
62161 {
62162 M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
62163 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62164 },
62165 /* jmp.a ${Lab-8-24} */
62166 {
62167 M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32,
62168 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62169 },
62170 /* jmps #${Imm-8-QI} */
62171 {
62172 M32C_INSN_JMPS32, "jmps32", "jmps", 16,
62173 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62174 },
62175 /* jsr.w ${Lab-8-16} */
62176 {
62177 M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
62178 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62179 },
62180 /* jsr.a ${Lab-8-24} */
62181 {
62182 M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32,
62183 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62184 },
62185 /* jsr.w ${Lab-8-16} */
62186 {
62187 M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
62188 { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62189 },
62190 /* jsr.a ${Lab-8-24} */
62191 {
62192 M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32,
62193 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62194 },
62195 /* jsrs #${Imm-8-QI} */
62196 {
62197 M32C_INSN_JSRS16, "jsrs16", "jsrs", 16,
62198 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62199 },
62200 /* jsrs #${Imm-8-QI} */
62201 {
62202 M32C_INSN_JSRS, "jsrs", "jsrs", 16,
62203 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62204 },
62205 /* ldc #${Imm-16-HI},${cr16} */
62206 {
62207 M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32,
62208 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62209 },
62210 /* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
62211 {
62212 M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32,
62213 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62214 },
62215 /* ldc #${Dsp-16-u24},${cr2-32} */
62216 {
62217 M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40,
62218 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62219 },
62220 /* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
62221 {
62222 M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40,
62223 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62224 },
62225 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62226 {
62227 M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56,
62228 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62229 },
62230 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62231 {
62232 M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56,
62233 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62234 },
62235 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62236 {
62237 M32C_INSN_STCTX16, "stctx16", "stctx", 56,
62238 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62239 },
62240 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62241 {
62242 M32C_INSN_STCTX32, "stctx32", "stctx", 56,
62243 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62244 },
62245 /* ldipl #${Imm-13-u3} */
62246 {
62247 M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16,
62248 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62249 },
62250 /* ldipl #${Imm-13-u3} */
62251 {
62252 M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16,
62253 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62254 },
62255 /* mov.b$S #${Imm-8-QI},a0 */
62256 {
62257 M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16,
62258 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62259 },
62260 /* mov.b$S #${Imm-8-QI},a1 */
62261 {
62262 M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16,
62263 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62264 },
62265 /* mov.w$S #${Imm-8-HI},a0 */
62266 {
62267 M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24,
62268 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62269 },
62270 /* mov.w$S #${Imm-8-HI},a1 */
62271 {
62272 M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24,
62273 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62274 },
62275 /* mov.w$S #${Imm-8-HI},a0 */
62276 {
62277 M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24,
62278 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62279 },
62280 /* mov.w$S #${Imm-8-HI},a1 */
62281 {
62282 M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
62283 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62284 },
62285 /* mov.l$S #${Dsp-8-s24},a0 */
62286 {
62287 M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
62288 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62289 },
62290 /* mov.l$S #${Dsp-8-s24},a1 */
62291 {
62292 M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
62293 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62294 },
62295 /* mov.b$S r0l,a1 */
62296 {
62297 M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8,
62298 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62299 },
62300 /* mov.b$S r0h,a0 */
62301 {
62302 M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8,
62303 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62304 },
62305 /* nop */
62306 {
62307 M32C_INSN_NOP16, "nop16", "nop", 8,
62308 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62309 },
62310 /* nop */
62311 {
62312 M32C_INSN_NOP32, "nop32", "nop", 8,
62313 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62314 },
62315 /* popc ${cr16} */
62316 {
62317 M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16,
62318 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62319 },
62320 /* popc ${cr1-Unprefixed-32} */
62321 {
62322 M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16,
62323 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62324 },
62325 /* popc ${cr2-32} */
62326 {
62327 M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16,
62328 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62329 },
62330 /* pushc ${cr16} */
62331 {
62332 M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16,
62333 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62334 },
62335 /* pushc ${cr1-Unprefixed-32} */
62336 {
62337 M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16,
62338 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62339 },
62340 /* pushc ${cr2-32} */
62341 {
62342 M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16,
62343 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62344 },
62345 /* popm ${Regsetpop} */
62346 {
62347 M32C_INSN_POPM16, "popm16", "popm", 16,
62348 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62349 },
62350 /* pushm ${Regsetpush} */
62351 {
62352 M32C_INSN_PUSHM16, "pushm16", "pushm", 16,
62353 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62354 },
62355 /* popm ${Regsetpop} */
62356 {
62357 M32C_INSN_POPM, "popm", "popm", 16,
62358 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62359 },
62360 /* pushm ${Regsetpush} */
62361 {
62362 M32C_INSN_PUSHM, "pushm", "pushm", 16,
62363 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62364 },
62365 /* push.b$G #${Imm-16-QI} */
62366 {
62367 M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24,
62368 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62369 },
62370 /* push.w$G #${Imm-16-HI} */
62371 {
62372 M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32,
62373 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62374 },
62375 /* push.b #Imm-8-QI */
62376 {
62377 M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16,
62378 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62379 },
62380 /* push.w #${Imm-8-HI} */
62381 {
62382 M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24,
62383 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62384 },
62385 /* push.l #${Imm-16-SI} */
62386 {
62387 M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48,
62388 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62389 },
62390 /* reit */
62391 {
62392 M32C_INSN_REIT16, "reit16", "reit", 8,
62393 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62394 },
62395 /* reit */
62396 {
62397 M32C_INSN_REIT32, "reit32", "reit", 8,
62398 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62399 },
62400 /* rmpa.b */
62401 {
62402 M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16,
62403 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62404 },
62405 /* rmpa.w */
62406 {
62407 M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16,
62408 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62409 },
62410 /* rmpa.b */
62411 {
62412 M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16,
62413 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62414 },
62415 /* rmpa.w */
62416 {
62417 M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16,
62418 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62419 },
62420 /* rts */
62421 {
62422 M32C_INSN_RTS16, "rts16", "rts", 8,
62423 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62424 },
62425 /* rts */
62426 {
62427 M32C_INSN_RTS32, "rts32", "rts", 8,
62428 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62429 },
62430 /* scmpu.b */
62431 {
62432 M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16,
62433 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62434 },
62435 /* scmpu.w */
62436 {
62437 M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16,
62438 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62439 },
62440 /* sha.l #${Imm-sh-12-s4},r2r0 */
62441 {
62442 M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16,
62443 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62444 },
62445 /* sha.l #${Imm-sh-12-s4},r3r1 */
62446 {
62447 M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16,
62448 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62449 },
62450 /* sha.l r1h,r2r0 */
62451 {
62452 M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16,
62453 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62454 },
62455 /* sha.l r1h,r3r1 */
62456 {
62457 M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16,
62458 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62459 },
62460 /* shl.l #${Imm-sh-12-s4},r2r0 */
62461 {
62462 M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16,
62463 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62464 },
62465 /* shl.l #${Imm-sh-12-s4},r3r1 */
62466 {
62467 M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16,
62468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62469 },
62470 /* shl.l r1h,r2r0 */
62471 {
62472 M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16,
62473 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62474 },
62475 /* shl.l r1h,r3r1 */
62476 {
62477 M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16,
62478 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62479 },
62480 /* sin.b */
62481 {
62482 M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16,
62483 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62484 },
62485 /* sin.w */
62486 {
62487 M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16,
62488 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62489 },
62490 /* smovb.b */
62491 {
62492 M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16,
62493 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62494 },
62495 /* smovb.w */
62496 {
62497 M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16,
62498 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62499 },
62500 /* smovb.b */
62501 {
62502 M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16,
62503 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62504 },
62505 /* smovb.w */
62506 {
62507 M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16,
62508 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62509 },
62510 /* smovf.b */
62511 {
62512 M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16,
62513 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62514 },
62515 /* smovf.w */
62516 {
62517 M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16,
62518 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62519 },
62520 /* smovf.b */
62521 {
62522 M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16,
62523 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62524 },
62525 /* smovf.w */
62526 {
62527 M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16,
62528 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62529 },
62530 /* smovu.b */
62531 {
62532 M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16,
62533 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62534 },
62535 /* smovu.w */
62536 {
62537 M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16,
62538 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62539 },
62540 /* sout.b */
62541 {
62542 M32C_INSN_SOUT_B, "sout.b", "sout.b", 16,
62543 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62544 },
62545 /* sout.w */
62546 {
62547 M32C_INSN_SOUT_W, "sout.w", "sout.w", 16,
62548 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62549 },
62550 /* sstr.b */
62551 {
62552 M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16,
62553 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62554 },
62555 /* sstr.w */
62556 {
62557 M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16,
62558 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62559 },
62560 /* sstr.b */
62561 {
62562 M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16,
62563 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62564 },
62565 /* sstr.w */
62566 {
62567 M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16,
62568 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62569 },
62570 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
62571 {
62572 M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24,
62573 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62574 },
62575 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
62576 {
62577 M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
62578 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62579 },
62580 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */
62581 {
62582 M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
62583 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62584 },
62585 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */
62586 {
62587 M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
62588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62589 },
62590 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */
62591 {
62592 M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
62593 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62594 },
62595 /* und */
62596 {
62597 M32C_INSN_UND16, "und16", "und", 8,
62598 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62599 },
62600 /* und */
62601 {
62602 M32C_INSN_UND32, "und32", "und", 8,
62603 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62604 },
62605 /* wait */
62606 {
62607 M32C_INSN_WAIT16, "wait16", "wait", 16,
62608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62609 },
62610 /* wait */
62611 {
62612 M32C_INSN_WAIT, "wait", "wait", 16,
62613 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62614 },
62615 /* exts.w r0 */
62616 {
62617 M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16,
62618 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62619 },
62620 /* src-indirect */
62621 {
62622 M32C_INSN_SRCIND, "srcind", "src-indirect", 8,
62623 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62624 },
62625 /* dest-indirect */
62626 {
62627 M32C_INSN_DESTIND, "destind", "dest-indirect", 8,
62628 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62629 },
62630 /* src-dest-indirect */
62631 {
62632 M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8,
62633 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62634 },
62635 };
62636
62637 #undef OP
62638 #undef A
62639
62640 /* Initialize anything needed to be done once, before any cpu_open call. */
62641
62642 static void
62643 init_tables (void)
62644 {
62645 }
62646
62647 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
62648 static void build_hw_table (CGEN_CPU_TABLE *);
62649 static void build_ifield_table (CGEN_CPU_TABLE *);
62650 static void build_operand_table (CGEN_CPU_TABLE *);
62651 static void build_insn_table (CGEN_CPU_TABLE *);
62652 static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *);
62653
62654 /* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name. */
62655
62656 static const CGEN_MACH *
62657 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
62658 {
62659 while (table->name)
62660 {
62661 if (strcmp (name, table->bfd_name) == 0)
62662 return table;
62663 ++table;
62664 }
62665 abort ();
62666 }
62667
62668 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62669
62670 static void
62671 build_hw_table (CGEN_CPU_TABLE *cd)
62672 {
62673 int i;
62674 int machs = cd->machs;
62675 const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0];
62676 /* MAX_HW is only an upper bound on the number of selected entries.
62677 However each entry is indexed by it's enum so there can be holes in
62678 the table. */
62679 const CGEN_HW_ENTRY **selected =
62680 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
62681
62682 cd->hw_table.init_entries = init;
62683 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
62684 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
62685 /* ??? For now we just use machs to determine which ones we want. */
62686 for (i = 0; init[i].name != NULL; ++i)
62687 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
62688 & machs)
62689 selected[init[i].type] = &init[i];
62690 cd->hw_table.entries = selected;
62691 cd->hw_table.num_entries = MAX_HW;
62692 }
62693
62694 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62695
62696 static void
62697 build_ifield_table (CGEN_CPU_TABLE *cd)
62698 {
62699 cd->ifld_table = & m32c_cgen_ifld_table[0];
62700 }
62701
62702 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62703
62704 static void
62705 build_operand_table (CGEN_CPU_TABLE *cd)
62706 {
62707 int i;
62708 int machs = cd->machs;
62709 const CGEN_OPERAND *init = & m32c_cgen_operand_table[0];
62710 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
62711 However each entry is indexed by it's enum so there can be holes in
62712 the table. */
62713 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
62714
62715 cd->operand_table.init_entries = init;
62716 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
62717 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
62718 /* ??? For now we just use mach to determine which ones we want. */
62719 for (i = 0; init[i].name != NULL; ++i)
62720 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
62721 & machs)
62722 selected[init[i].type] = &init[i];
62723 cd->operand_table.entries = selected;
62724 cd->operand_table.num_entries = MAX_OPERANDS;
62725 }
62726
62727 /* Subroutine of m32c_cgen_cpu_open to build the hardware table.
62728 ??? This could leave out insns not supported by the specified mach/isa,
62729 but that would cause errors like "foo only supported by bar" to become
62730 "unknown insn", so for now we include all insns and require the app to
62731 do the checking later.
62732 ??? On the other hand, parsing of such insns may require their hardware or
62733 operand elements to be in the table [which they mightn't be]. */
62734
62735 static void
62736 build_insn_table (CGEN_CPU_TABLE *cd)
62737 {
62738 int i;
62739 const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
62740 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
62741
62742 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
62743 for (i = 0; i < MAX_INSNS; ++i)
62744 insns[i].base = &ib[i];
62745 cd->insn_table.init_entries = insns;
62746 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
62747 cd->insn_table.num_init_entries = MAX_INSNS;
62748 }
62749
62750 /* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */
62751
62752 static void
62753 m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
62754 {
62755 int i;
62756 unsigned int isas = cd->isas;
62757 unsigned int machs = cd->machs;
62758
62759 cd->int_insn_p = CGEN_INT_INSN_P;
62760
62761 /* Data derived from the isa spec. */
62762 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
62763 cd->default_insn_bitsize = UNSET;
62764 cd->base_insn_bitsize = UNSET;
62765 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
62766 cd->max_insn_bitsize = 0;
62767 for (i = 0; i < MAX_ISAS; ++i)
62768 if (((1 << i) & isas) != 0)
62769 {
62770 const CGEN_ISA *isa = & m32c_cgen_isa_table[i];
62771
62772 /* Default insn sizes of all selected isas must be
62773 equal or we set the result to 0, meaning "unknown". */
62774 if (cd->default_insn_bitsize == UNSET)
62775 cd->default_insn_bitsize = isa->default_insn_bitsize;
62776 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
62777 ; /* This is ok. */
62778 else
62779 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
62780
62781 /* Base insn sizes of all selected isas must be equal
62782 or we set the result to 0, meaning "unknown". */
62783 if (cd->base_insn_bitsize == UNSET)
62784 cd->base_insn_bitsize = isa->base_insn_bitsize;
62785 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
62786 ; /* This is ok. */
62787 else
62788 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
62789
62790 /* Set min,max insn sizes. */
62791 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
62792 cd->min_insn_bitsize = isa->min_insn_bitsize;
62793 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
62794 cd->max_insn_bitsize = isa->max_insn_bitsize;
62795 }
62796
62797 /* Data derived from the mach spec. */
62798 for (i = 0; i < MAX_MACHS; ++i)
62799 if (((1 << i) & machs) != 0)
62800 {
62801 const CGEN_MACH *mach = & m32c_cgen_mach_table[i];
62802
62803 if (mach->insn_chunk_bitsize != 0)
62804 {
62805 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
62806 {
62807 fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
62808 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
62809 abort ();
62810 }
62811
62812 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
62813 }
62814 }
62815
62816 /* Determine which hw elements are used by MACH. */
62817 build_hw_table (cd);
62818
62819 /* Build the ifield table. */
62820 build_ifield_table (cd);
62821
62822 /* Determine which operands are used by MACH/ISA. */
62823 build_operand_table (cd);
62824
62825 /* Build the instruction table. */
62826 build_insn_table (cd);
62827 }
62828
62829 /* Initialize a cpu table and return a descriptor.
62830 It's much like opening a file, and must be the first function called.
62831 The arguments are a set of (type/value) pairs, terminated with
62832 CGEN_CPU_OPEN_END.
62833
62834 Currently supported values:
62835 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
62836 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
62837 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
62838 CGEN_CPU_OPEN_ENDIAN: specify endian choice
62839 CGEN_CPU_OPEN_END: terminates arguments
62840
62841 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
62842 precluded.
62843
62844 ??? We only support ISO C stdargs here, not K&R.
62845 Laziness, plus experiment to see if anything requires K&R - eventually
62846 K&R will no longer be supported - e.g. GDB is currently trying this. */
62847
62848 CGEN_CPU_DESC
62849 m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
62850 {
62851 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
62852 static int init_p;
62853 unsigned int isas = 0; /* 0 = "unspecified" */
62854 unsigned int machs = 0; /* 0 = "unspecified" */
62855 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
62856 va_list ap;
62857
62858 if (! init_p)
62859 {
62860 init_tables ();
62861 init_p = 1;
62862 }
62863
62864 memset (cd, 0, sizeof (*cd));
62865
62866 va_start (ap, arg_type);
62867 while (arg_type != CGEN_CPU_OPEN_END)
62868 {
62869 switch (arg_type)
62870 {
62871 case CGEN_CPU_OPEN_ISAS :
62872 isas = va_arg (ap, unsigned int);
62873 break;
62874 case CGEN_CPU_OPEN_MACHS :
62875 machs = va_arg (ap, unsigned int);
62876 break;
62877 case CGEN_CPU_OPEN_BFDMACH :
62878 {
62879 const char *name = va_arg (ap, const char *);
62880 const CGEN_MACH *mach =
62881 lookup_mach_via_bfd_name (m32c_cgen_mach_table, name);
62882
62883 machs |= 1 << mach->num;
62884 break;
62885 }
62886 case CGEN_CPU_OPEN_ENDIAN :
62887 endian = va_arg (ap, enum cgen_endian);
62888 break;
62889 default :
62890 fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n",
62891 arg_type);
62892 abort (); /* ??? return NULL? */
62893 }
62894 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
62895 }
62896 va_end (ap);
62897
62898 /* Mach unspecified means "all". */
62899 if (machs == 0)
62900 machs = (1 << MAX_MACHS) - 1;
62901 /* Base mach is always selected. */
62902 machs |= 1;
62903 /* ISA unspecified means "all". */
62904 if (isas == 0)
62905 isas = (1 << MAX_ISAS) - 1;
62906 if (endian == CGEN_ENDIAN_UNKNOWN)
62907 {
62908 /* ??? If target has only one, could have a default. */
62909 fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n");
62910 abort ();
62911 }
62912
62913 cd->isas = isas;
62914 cd->machs = machs;
62915 cd->endian = endian;
62916 /* FIXME: for the sparc case we can determine insn-endianness statically.
62917 The worry here is where both data and insn endian can be independently
62918 chosen, in which case this function will need another argument.
62919 Actually, will want to allow for more arguments in the future anyway. */
62920 cd->insn_endian = endian;
62921
62922 /* Table (re)builder. */
62923 cd->rebuild_tables = m32c_cgen_rebuild_tables;
62924 m32c_cgen_rebuild_tables (cd);
62925
62926 /* Default to not allowing signed overflow. */
62927 cd->signed_overflow_ok_p = 0;
62928
62929 return (CGEN_CPU_DESC) cd;
62930 }
62931
62932 /* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
62933 MACH_NAME is the bfd name of the mach. */
62934
62935 CGEN_CPU_DESC
62936 m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
62937 {
62938 return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
62939 CGEN_CPU_OPEN_ENDIAN, endian,
62940 CGEN_CPU_OPEN_END);
62941 }
62942
62943 /* Close a cpu table.
62944 ??? This can live in a machine independent file, but there's currently
62945 no place to put this file (there's no libcgen). libopcodes is the wrong
62946 place as some simulator ports use this but they don't use libopcodes. */
62947
62948 void
62949 m32c_cgen_cpu_close (CGEN_CPU_DESC cd)
62950 {
62951 unsigned int i;
62952 const CGEN_INSN *insns;
62953
62954 if (cd->macro_insn_table.init_entries)
62955 {
62956 insns = cd->macro_insn_table.init_entries;
62957 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
62958 if (CGEN_INSN_RX ((insns)))
62959 regfree (CGEN_INSN_RX (insns));
62960 }
62961
62962 if (cd->insn_table.init_entries)
62963 {
62964 insns = cd->insn_table.init_entries;
62965 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
62966 if (CGEN_INSN_RX (insns))
62967 regfree (CGEN_INSN_RX (insns));
62968 }
62969
62970 if (cd->macro_insn_table.init_entries)
62971 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
62972
62973 if (cd->insn_table.init_entries)
62974 free ((CGEN_INSN *) cd->insn_table.init_entries);
62975
62976 if (cd->hw_table.entries)
62977 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
62978
62979 if (cd->operand_table.entries)
62980 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
62981
62982 free (cd);
62983 }
62984
GDB Binutils - Deliverables
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