opcodes/m32r-asm.c

   1 /* Assembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-asm.in isn't
   6
   7 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   8
   9 This file is part of the GNU Binutils and GDB, the GNU debugger.
  10
  11 This program is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 This program is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program; if not, write to the Free Software Foundation, Inc.,
  23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <ctype.h>
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "m32r-desc.h"
  35 #include "m32r-opc.h"
  36 #include "opintl.h"
  37
  38 #undef min
  39 #define min(a,b) ((a) < (b) ? (a) : (b))
  40 #undef max
  41 #define max(a,b) ((a) > (b) ? (a) : (b))
  42
  43 static const char * parse_insn_normal
  44      PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
  45 \f
  46 /* -- assembler routines inserted here */
  47
  48 /* -- asm.c */
  49
  50 /* Handle '#' prefixes (i.e. skip over them).  */
  51
  52 static const char *
  53 parse_hash (cd, strp, opindex, valuep)
  54      CGEN_CPU_DESC cd;
  55      const char **strp;
  56      int opindex;
  57      unsigned long *valuep;
  58 {
  59   if (**strp == '#')
  60     ++*strp;
  61   return NULL;
  62 }
  63
  64 /* Handle shigh(), high().  */
  65
  66 static const char *
  67 parse_hi16 (cd, strp, opindex, valuep)
  68      CGEN_CPU_DESC cd;
  69      const char **strp;
  70      int opindex;
  71      unsigned long *valuep;
  72 {
  73   const char *errmsg;
  74   enum cgen_parse_operand_result result_type;
  75   bfd_vma value;
  76
  77   if (**strp == '#')
  78     ++*strp;
  79
  80   if (strncasecmp (*strp, "high(", 5) == 0)
  81     {
  82       *strp += 5;
  83       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
  84                                    &result_type, &value);
  85       if (**strp != ')')
  86         return "missing `)'";
  87       ++*strp;
  88       if (errmsg == NULL
  89           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
  90         value >>= 16;
  91       *valuep = value;
  92       return errmsg;
  93     }
  94   else if (strncasecmp (*strp, "shigh(", 6) == 0)
  95     {
  96       *strp += 6;
  97       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
  98                                    &result_type, &value);
  99       if (**strp != ')')
 100         return "missing `)'";
 101       ++*strp;
 102       if (errmsg == NULL
 103           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
 104         value = (value >> 16) + (value & 0x8000 ? 1 : 0);
 105       *valuep = value;
 106       return errmsg;
 107     }
 108
 109   return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
 110 }
 111
 112 /* Handle low() in a signed context.  Also handle sda().
 113    The signedness of the value doesn't matter to low(), but this also
 114    handles the case where low() isn't present.  */
 115
 116 static const char *
 117 parse_slo16 (cd, strp, opindex, valuep)
 118      CGEN_CPU_DESC cd;
 119      const char **strp;
 120      int opindex;
 121      long *valuep;
 122 {
 123   const char *errmsg;
 124   enum cgen_parse_operand_result result_type;
 125   bfd_vma value;
 126
 127   if (**strp == '#')
 128     ++*strp;
 129
 130   if (strncasecmp (*strp, "low(", 4) == 0)
 131     {
 132       *strp += 4;
 133       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
 134                                    &result_type, &value);
 135       if (**strp != ')')
 136         return "missing `)'";
 137       ++*strp;
 138       if (errmsg == NULL
 139           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
 140         value &= 0xffff;
 141       *valuep = value;
 142       return errmsg;
 143     }
 144
 145   if (strncasecmp (*strp, "sda(", 4) == 0)
 146     {
 147       *strp += 4;
 148       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
 149                                    NULL, &value);
 150       if (**strp != ')')
 151         return "missing `)'";
 152       ++*strp;
 153       *valuep = value;
 154       return errmsg;
 155     }
 156
 157   return cgen_parse_signed_integer (cd, strp, opindex, valuep);
 158 }
 159
 160 /* Handle low() in an unsigned context.
 161    The signedness of the value doesn't matter to low(), but this also
 162    handles the case where low() isn't present.  */
 163
 164 static const char *
 165 parse_ulo16 (cd, strp, opindex, valuep)
 166      CGEN_CPU_DESC cd;
 167      const char **strp;
 168      int opindex;
 169      unsigned long *valuep;
 170 {
 171   const char *errmsg;
 172   enum cgen_parse_operand_result result_type;
 173   bfd_vma value;
 174
 175   if (**strp == '#')
 176     ++*strp;
 177
 178   if (strncasecmp (*strp, "low(", 4) == 0)
 179     {
 180       *strp += 4;
 181       errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
 182                                    &result_type, &value);
 183       if (**strp != ')')
 184         return "missing `)'";
 185       ++*strp;
 186       if (errmsg == NULL
 187           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
 188         value &= 0xffff;
 189       *valuep = value;
 190       return errmsg;
 191     }
 192
 193   return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
 194 }
 195
 196 /* -- */
 197
 198 /* Main entry point for operand parsing.
 199
 200    This function is basically just a big switch statement.  Earlier versions
 201    used tables to look up the function to use, but
 202    - if the table contains both assembler and disassembler functions then
 203      the disassembler contains much of the assembler and vice-versa,
 204    - there's a lot of inlining possibilities as things grow,
 205    - using a switch statement avoids the function call overhead.
 206
 207    This function could be moved into `parse_insn_normal', but keeping it
 208    separate makes clear the interface between `parse_insn_normal' and each of
 209    the handlers.
 210 */
 211
 212 const char *
 213 m32r_cgen_parse_operand (cd, opindex, strp, fields)
 214      CGEN_CPU_DESC cd;
 215      int opindex;
 216      const char ** strp;
 217      CGEN_FIELDS * fields;
 218 {
 219   const char * errmsg = NULL;
 220   /* Used by scalar operands that still need to be parsed.  */
 221   long junk;
 222
 223   switch (opindex)
 224     {
 225     case M32R_OPERAND_DCR :
 226       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r1);
 227       break;
 228     case M32R_OPERAND_DISP16 :
 229       {
 230         bfd_vma value;
 231         errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP16, 0, NULL,  & value);
 232         fields->f_disp16 = value;
 233       }
 234       break;
 235     case M32R_OPERAND_DISP24 :
 236       {
 237         bfd_vma value;
 238         errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP24, 0, NULL,  & value);
 239         fields->f_disp24 = value;
 240       }
 241       break;
 242     case M32R_OPERAND_DISP8 :
 243       {
 244         bfd_vma value;
 245         errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP8, 0, NULL,  & value);
 246         fields->f_disp8 = value;
 247       }
 248       break;
 249     case M32R_OPERAND_DR :
 250       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1);
 251       break;
 252     case M32R_OPERAND_HASH :
 253       errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, &junk);
 254       break;
 255     case M32R_OPERAND_HI16 :
 256       errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, &fields->f_hi16);
 257       break;
 258     case M32R_OPERAND_SCR :
 259       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r2);
 260       break;
 261     case M32R_OPERAND_SIMM16 :
 262       errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM16, &fields->f_simm16);
 263       break;
 264     case M32R_OPERAND_SIMM8 :
 265       errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM8, &fields->f_simm8);
 266       break;
 267     case M32R_OPERAND_SLO16 :
 268       errmsg = parse_slo16 (cd, strp, M32R_OPERAND_SLO16, &fields->f_simm16);
 269       break;
 270     case M32R_OPERAND_SR :
 271       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2);
 272       break;
 273     case M32R_OPERAND_SRC1 :
 274       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1);
 275       break;
 276     case M32R_OPERAND_SRC2 :
 277       errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2);
 278       break;
 279     case M32R_OPERAND_UIMM16 :
 280       errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM16, &fields->f_uimm16);
 281       break;
 282     case M32R_OPERAND_UIMM24 :
 283       {
 284         bfd_vma value;
 285         errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_UIMM24, 0, NULL,  & value);
 286         fields->f_uimm24 = value;
 287       }
 288       break;
 289     case M32R_OPERAND_UIMM4 :
 290       errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4);
 291       break;
 292     case M32R_OPERAND_UIMM5 :
 293       errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5);
 294       break;
 295     case M32R_OPERAND_ULO16 :
 296       errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
 297       break;
 298
 299     default :
 300       /* xgettext:c-format */
 301       fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
 302       abort ();
 303   }
 304
 305   return errmsg;
 306 }
 307
 308 cgen_parse_fn * const m32r_cgen_parse_handlers[] =
 309 {
 310   parse_insn_normal,
 311 };
 312
 313 void
 314 m32r_cgen_init_asm (cd)
 315      CGEN_CPU_DESC cd;
 316 {
 317   m32r_cgen_init_opcode_table (cd);
 318   m32r_cgen_init_ibld_table (cd);
 319   cd->parse_handlers = & m32r_cgen_parse_handlers[0];
 320   cd->parse_operand = m32r_cgen_parse_operand;
 321 }
 322
 323 \f
 324 /* Default insn parser.
 325
 326    The syntax string is scanned and operands are parsed and stored in FIELDS.
 327    Relocs are queued as we go via other callbacks.
 328
 329    ??? Note that this is currently an all-or-nothing parser.  If we fail to
 330    parse the instruction, we return 0 and the caller will start over from
 331    the beginning.  Backtracking will be necessary in parsing subexpressions,
 332    but that can be handled there.  Not handling backtracking here may get
 333    expensive in the case of the m68k.  Deal with later.
 334
 335    Returns NULL for success, an error message for failure.
 336 */
 337
 338 static const char *
 339 parse_insn_normal (cd, insn, strp, fields)
 340      CGEN_CPU_DESC cd;
 341      const CGEN_INSN *insn;
 342      const char **strp;
 343      CGEN_FIELDS *fields;
 344 {
 345   /* ??? Runtime added insns not handled yet.  */
 346   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 347   const char *str = *strp;
 348   const char *errmsg;
 349   const char *p;
 350   const unsigned char * syn;
 351 #ifdef CGEN_MNEMONIC_OPERANDS
 352   /* FIXME: wip */
 353   int past_opcode_p;
 354 #endif
 355
 356   /* For now we assume the mnemonic is first (there are no leading operands).
 357      We can parse it without needing to set up operand parsing.
 358      GAS's input scrubber will ensure mnemonics are lowercase, but we may
 359      not be called from GAS.  */
 360   p = CGEN_INSN_MNEMONIC (insn);
 361   while (*p && tolower (*p) == tolower (*str))
 362     ++p, ++str;
 363
 364   if (* p || (* str && !isspace (* str)))
 365     return _("unrecognized instruction");
 366
 367   CGEN_INIT_PARSE (cd);
 368   cgen_init_parse_operand (cd);
 369 #ifdef CGEN_MNEMONIC_OPERANDS
 370   past_opcode_p = 0;
 371 #endif
 372
 373   /* We don't check for (*str != '\0') here because we want to parse
 374      any trailing fake arguments in the syntax string.  */
 375   syn = CGEN_SYNTAX_STRING (syntax);
 376
 377   /* Mnemonics come first for now, ensure valid string.  */
 378   if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
 379     abort ();
 380
 381   ++syn;
 382
 383   while (* syn != 0)
 384     {
 385       /* Non operand chars must match exactly.  */
 386       if (CGEN_SYNTAX_CHAR_P (* syn))
 387         {
 388           if (*str == CGEN_SYNTAX_CHAR (* syn))
 389             {
 390 #ifdef CGEN_MNEMONIC_OPERANDS
 391               if (* syn == ' ')
 392                 past_opcode_p = 1;
 393 #endif
 394               ++ syn;
 395               ++ str;
 396             }
 397           else
 398             {
 399               /* Syntax char didn't match.  Can't be this insn.  */
 400               /* FIXME: would like to return something like
 401                  "expected char `c'" */
 402               return _("syntax error");
 403             }
 404           continue;
 405         }
 406
 407       /* We have an operand of some sort.  */
 408       errmsg = m32r_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
 409                                           &str, fields);
 410       if (errmsg)
 411         return errmsg;
 412
 413       /* Done with this operand, continue with next one.  */
 414       ++ syn;
 415     }
 416
 417   /* If we're at the end of the syntax string, we're done.  */
 418   if (* syn == '\0')
 419     {
 420       /* FIXME: For the moment we assume a valid `str' can only contain
 421          blanks now.  IE: We needn't try again with a longer version of
 422          the insn and it is assumed that longer versions of insns appear
 423          before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
 424       while (isspace (* str))
 425         ++ str;
 426
 427       if (* str != '\0')
 428         return _("junk at end of line"); /* FIXME: would like to include `str' */
 429
 430       return NULL;
 431     }
 432
 433   /* We couldn't parse it.  */
 434   return _("unrecognized instruction");
 435 }
 436 \f
 437 /* Main entry point.
 438    This routine is called for each instruction to be assembled.
 439    STR points to the insn to be assembled.
 440    We assume all necessary tables have been initialized.
 441    The assembled instruction, less any fixups, is stored in BUF.
 442    Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
 443    still needs to be converted to target byte order, otherwise BUF is an array
 444    of bytes in target byte order.
 445    The result is a pointer to the insn's entry in the opcode table,
 446    or NULL if an error occured (an error message will have already been
 447    printed).
 448
 449    Note that when processing (non-alias) macro-insns,
 450    this function recurses.
 451
 452    ??? It's possible to make this cpu-independent.
 453    One would have to deal with a few minor things.
 454    At this point in time doing so would be more of a curiosity than useful
 455    [for example this file isn't _that_ big], but keeping the possibility in
 456    mind helps keep the design clean.  */
 457
 458 const CGEN_INSN *
 459 m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
 460      CGEN_CPU_DESC cd;
 461      const char *str;
 462      CGEN_FIELDS *fields;
 463      CGEN_INSN_BYTES_PTR buf;
 464      char **errmsg;
 465 {
 466   const char *start;
 467   CGEN_INSN_LIST *ilist;
 468
 469   /* Skip leading white space.  */
 470   while (isspace (* str))
 471     ++ str;
 472
 473   /* The instructions are stored in hashed lists.
 474      Get the first in the list.  */
 475   ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
 476
 477   /* Keep looking until we find a match.  */
 478
 479   start = str;
 480   for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
 481     {
 482       const CGEN_INSN *insn = ilist->insn;
 483
 484 #if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
 485       /* Is this insn supported by the selected cpu?  */
 486       if (! m32r_cgen_insn_supported (cd, insn))
 487         continue;
 488 #endif
 489
 490       /* If the RELAX attribute is set, this is an insn that shouldn't be
 491          chosen immediately.  Instead, it is used during assembler/linker
 492          relaxation if possible.  */
 493       if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
 494         continue;
 495
 496       str = start;
 497
 498       /* Allow parse/insert handlers to obtain length of insn.  */
 499       CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
 500
 501       if (! CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields))
 502         {
 503           /* ??? 0 is passed for `pc' */
 504           if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0)
 505               != NULL)
 506             continue;
 507           /* It is up to the caller to actually output the insn and any
 508              queued relocs.  */
 509           return insn;
 510         }
 511
 512       /* Try the next entry.  */
 513     }
 514
 515   /* FIXME: We can return a better error message than this.
 516      Need to track why it failed and pick the right one.  */
 517   {
 518     static char errbuf[100];
 519     if (strlen (start) > 50)
 520       /* xgettext:c-format */
 521       sprintf (errbuf, _("bad instruction `%.50s...'"), start);
 522     else
 523       /* xgettext:c-format */
 524       sprintf (errbuf, _("bad instruction `%.50s'"), start);
 525
 526     *errmsg = errbuf;
 527     return NULL;
 528   }
 529 }
 530 \f
 531 #if 0 /* This calls back to GAS which we can't do without care.  */
 532
 533 /* Record each member of OPVALS in the assembler's symbol table.
 534    This lets GAS parse registers for us.
 535    ??? Interesting idea but not currently used.  */
 536
 537 /* Record each member of OPVALS in the assembler's symbol table.
 538    FIXME: Not currently used.  */
 539
 540 void
 541 m32r_cgen_asm_hash_keywords (cd, opvals)
 542      CGEN_CPU_DESC cd;
 543      CGEN_KEYWORD *opvals;
 544 {
 545   CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
 546   const CGEN_KEYWORD_ENTRY * ke;
 547
 548   while ((ke = cgen_keyword_search_next (& search)) != NULL)
 549     {
 550 #if 0 /* Unnecessary, should be done in the search routine.  */
 551       if (! m32r_cgen_opval_supported (ke))
 552         continue;
 553 #endif
 554       cgen_asm_record_register (cd, ke->name, ke->value);
 555     }
 556 }
 557
 558 #endif /* 0 */