opcodes/m32r-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for m32r.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2020 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "m32r-desc.h"
  33 #include "m32r-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36 #include "xregex.h"
  37
  38 /* Attributes.  */
  39
  40 static const CGEN_ATTR_ENTRY bool_attr[] =
  41 {
  42   { "#f", 0 },
  43   { "#t", 1 },
  44   { 0, 0 }
  45 };
  46
  47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  48 {
  49   { "base", MACH_BASE },
  50   { "m32r", MACH_M32R },
  51   { "m32rx", MACH_M32RX },
  52   { "m32r2", MACH_M32R2 },
  53   { "max", MACH_MAX },
  54   { 0, 0 }
  55 };
  56
  57 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  58 {
  59   { "m32r", ISA_M32R },
  60   { "max", ISA_MAX },
  61   { 0, 0 }
  62 };
  63
  64 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
  65 {
  66   { "NONE", PIPE_NONE },
  67   { "O", PIPE_O },
  68   { "S", PIPE_S },
  69   { "OS", PIPE_OS },
  70   { "O_OS", PIPE_O_OS },
  71   { 0, 0 }
  72 };
  73
  74 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
  75 {
  76   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  77   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  78   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  79   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  80   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  81   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  82   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  83   { "RELOC", &bool_attr[0], &bool_attr[0] },
  84   { 0, 0, 0 }
  85 };
  86
  87 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
  88 {
  89   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  90   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  91   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  92   { "PC", &bool_attr[0], &bool_attr[0] },
  93   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  94   { 0, 0, 0 }
  95 };
  96
  97 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  98 {
  99   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 100   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 101   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 102   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 103   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 104   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 105   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 106   { "RELAX", &bool_attr[0], &bool_attr[0] },
 107   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 108   { "RELOC", &bool_attr[0], &bool_attr[0] },
 109   { 0, 0, 0 }
 110 };
 111
 112 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 113 {
 114   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 115   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 116   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 117   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 118   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 119   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 120   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 121   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 122   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 123   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 124   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 125   { "PBB", &bool_attr[0], &bool_attr[0] },
 126   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
 127   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
 128   { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
 129   { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
 130   { 0, 0, 0 }
 131 };
 132
 133 /* Instruction set variants.  */
 134
 135 static const CGEN_ISA m32r_cgen_isa_table[] = {
 136   { "m32r", 32, 32, 16, 32 },
 137   { 0, 0, 0, 0, 0 }
 138 };
 139
 140 /* Machine variants.  */
 141
 142 static const CGEN_MACH m32r_cgen_mach_table[] = {
 143   { "m32r", "m32r", MACH_M32R, 0 },
 144   { "m32rx", "m32rx", MACH_M32RX, 0 },
 145   { "m32r2", "m32r2", MACH_M32R2, 0 },
 146   { 0, 0, 0, 0 }
 147 };
 148
 149 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 150 {
 151   { "fp", 13, {0, {{{0, 0}}}}, 0, 0 },
 152   { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
 153   { "sp", 15, {0, {{{0, 0}}}}, 0, 0 },
 154   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 155   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
 156   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
 157   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
 158   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
 159   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
 160   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 161   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
 162   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
 163   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
 164   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
 165   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
 166   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
 167   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
 168   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
 169   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
 170 };
 171
 172 CGEN_KEYWORD m32r_cgen_opval_gr_names =
 173 {
 174   & m32r_cgen_opval_gr_names_entries[0],
 175   19,
 176   0, 0, 0, 0, ""
 177 };
 178
 179 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 180 {
 181   { "psw", 0, {0, {{{0, 0}}}}, 0, 0 },
 182   { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 },
 183   { "spi", 2, {0, {{{0, 0}}}}, 0, 0 },
 184   { "spu", 3, {0, {{{0, 0}}}}, 0, 0 },
 185   { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 },
 186   { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 },
 187   { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 },
 188   { "evb", 5, {0, {{{0, 0}}}}, 0, 0 },
 189   { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
 190   { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
 191   { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 192   { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 193   { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
 194   { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
 195   { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
 196   { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
 197   { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
 198   { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
 199   { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
 200   { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
 201   { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 202   { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 203   { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
 204   { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
 205 };
 206
 207 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 208 {
 209   & m32r_cgen_opval_cr_names_entries[0],
 210   24,
 211   0, 0, 0, 0, ""
 212 };
 213
 214 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 215 {
 216   { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
 217   { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
 218 };
 219
 220 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 221 {
 222   & m32r_cgen_opval_h_accums_entries[0],
 223   2,
 224   0, 0, 0, 0, ""
 225 };
 226
 227
 228 /* The hardware table.  */
 229
 230 #define A(a) (1 << CGEN_HW_##a)
 231
 232 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 233 {
 234   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 235   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 236   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 237   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 238   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 239   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
 240   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 241   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 242   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 243   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 244   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 245   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 246   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
 247   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 248   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 249   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 250   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 251   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 252   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 253 };
 254
 255 #undef A
 256
 257
 258 /* The instruction field table.  */
 259
 260 #define A(a) (1 << CGEN_IFLD_##a)
 261
 262 const CGEN_IFLD m32r_cgen_ifld_table[] =
 263 {
 264   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 265   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 266   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 267   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 268   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 269   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 270   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 271   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 272   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 273   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 274   { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 275   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 276   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 277   { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 278   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 279   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 280   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 281   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 282   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 283   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 284   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 285   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 286   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 287   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 288   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 289   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 290   { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 291   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 292   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 293   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 294 };
 295
 296 #undef A
 297
 298
 299
 300 /* multi ifield declarations */
 301
 302
 303
 304 /* multi ifield definitions */
 305
 306
 307 /* The operand table.  */
 308
 309 #define A(a) (1 << CGEN_OPERAND_##a)
 310 #define OPERAND(op) M32R_OPERAND_##op
 311
 312 const CGEN_OPERAND m32r_cgen_operand_table[] =
 313 {
 314 /* pc: program counter */
 315   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
 316     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
 317     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 318 /* sr: source register */
 319   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
 320     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 321     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 322 /* dr: destination register */
 323   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
 324     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 325     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 326 /* src1: source register 1 */
 327   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
 328     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 329     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 330 /* src2: source register 2 */
 331   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
 332     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 333     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 334 /* scr: source control register */
 335   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
 336     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 337     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 338 /* dcr: destination control register */
 339   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
 340     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 341     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 342 /* simm8: 8 bit signed immediate */
 343   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 344     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
 345     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 346 /* simm16: 16 bit signed immediate */
 347   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 348     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
 349     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 350 /* uimm3: 3 bit unsigned number */
 351   { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
 352     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
 353     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 354 /* uimm4: 4 bit trap number */
 355   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
 356     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
 357     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 358 /* uimm5: 5 bit shift count */
 359   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
 360     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
 361     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 362 /* uimm8: 8 bit unsigned immediate */
 363   { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
 364     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
 365     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 366 /* uimm16: 16 bit unsigned immediate */
 367   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 368     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
 369     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 370 /* imm1: 1 bit immediate */
 371   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
 372     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
 373     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 374 /* accd: accumulator destination register */
 375   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
 376     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
 377     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 378 /* accs: accumulator source register */
 379   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
 380     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
 381     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 382 /* acc: accumulator reg (d) */
 383   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
 384     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
 385     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 386 /* hash: # prefix */
 387   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
 388     { 0, { (const PTR) 0 } },
 389     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 390 /* hi16: high 16 bit immediate, sign optional */
 391   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
 392     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
 393     { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 394 /* slo16: 16 bit signed immediate, for low() */
 395   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
 396     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
 397     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 398 /* ulo16: 16 bit unsigned immediate, for low() */
 399   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
 400     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
 401     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 402 /* uimm24: 24 bit address */
 403   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
 404     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
 405     { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 406 /* disp8: 8 bit displacement */
 407   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
 408     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
 409     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 410 /* disp16: 16 bit displacement */
 411   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
 412     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
 413     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 414 /* disp24: 24 bit displacement */
 415   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
 416     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
 417     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 418 /* condbit: condition bit */
 419   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 420     { 0, { (const PTR) 0 } },
 421     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 422 /* accum: accumulator */
 423   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
 424     { 0, { (const PTR) 0 } },
 425     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 426 /* sentinel */
 427   { 0, 0, 0, 0, 0,
 428     { 0, { (const PTR) 0 } },
 429     { 0, { { { (1<<MACH_BASE), 0 } } } } }
 430 };
 431
 432 #undef A
 433
 434
 435 /* The instruction table.  */
 436
 437 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 438 #define A(a) (1 << CGEN_INSN_##a)
 439
 440 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 441 {
 442   /* Special null first entry.
 443      A `num' value of zero is thus invalid.
 444      Also, the special `invalid' insn resides here.  */
 445   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
 446 /* add $dr,$sr */
 447   {
 448     M32R_INSN_ADD, "add", "add", 16,
 449     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 450   },
 451 /* add3 $dr,$sr,$hash$slo16 */
 452   {
 453     M32R_INSN_ADD3, "add3", "add3", 32,
 454     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 455   },
 456 /* and $dr,$sr */
 457   {
 458     M32R_INSN_AND, "and", "and", 16,
 459     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 460   },
 461 /* and3 $dr,$sr,$uimm16 */
 462   {
 463     M32R_INSN_AND3, "and3", "and3", 32,
 464     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 465   },
 466 /* or $dr,$sr */
 467   {
 468     M32R_INSN_OR, "or", "or", 16,
 469     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 470   },
 471 /* or3 $dr,$sr,$hash$ulo16 */
 472   {
 473     M32R_INSN_OR3, "or3", "or3", 32,
 474     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 475   },
 476 /* xor $dr,$sr */
 477   {
 478     M32R_INSN_XOR, "xor", "xor", 16,
 479     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 480   },
 481 /* xor3 $dr,$sr,$uimm16 */
 482   {
 483     M32R_INSN_XOR3, "xor3", "xor3", 32,
 484     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 485   },
 486 /* addi $dr,$simm8 */
 487   {
 488     M32R_INSN_ADDI, "addi", "addi", 16,
 489     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 490   },
 491 /* addv $dr,$sr */
 492   {
 493     M32R_INSN_ADDV, "addv", "addv", 16,
 494     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 495   },
 496 /* addv3 $dr,$sr,$simm16 */
 497   {
 498     M32R_INSN_ADDV3, "addv3", "addv3", 32,
 499     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 500   },
 501 /* addx $dr,$sr */
 502   {
 503     M32R_INSN_ADDX, "addx", "addx", 16,
 504     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 505   },
 506 /* bc.s $disp8 */
 507   {
 508     M32R_INSN_BC8, "bc8", "bc.s", 16,
 509     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 510   },
 511 /* bc.l $disp24 */
 512   {
 513     M32R_INSN_BC24, "bc24", "bc.l", 32,
 514     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 515   },
 516 /* beq $src1,$src2,$disp16 */
 517   {
 518     M32R_INSN_BEQ, "beq", "beq", 32,
 519     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 520   },
 521 /* beqz $src2,$disp16 */
 522   {
 523     M32R_INSN_BEQZ, "beqz", "beqz", 32,
 524     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 525   },
 526 /* bgez $src2,$disp16 */
 527   {
 528     M32R_INSN_BGEZ, "bgez", "bgez", 32,
 529     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 530   },
 531 /* bgtz $src2,$disp16 */
 532   {
 533     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
 534     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 535   },
 536 /* blez $src2,$disp16 */
 537   {
 538     M32R_INSN_BLEZ, "blez", "blez", 32,
 539     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 540   },
 541 /* bltz $src2,$disp16 */
 542   {
 543     M32R_INSN_BLTZ, "bltz", "bltz", 32,
 544     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 545   },
 546 /* bnez $src2,$disp16 */
 547   {
 548     M32R_INSN_BNEZ, "bnez", "bnez", 32,
 549     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 550   },
 551 /* bl.s $disp8 */
 552   {
 553     M32R_INSN_BL8, "bl8", "bl.s", 16,
 554     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 555   },
 556 /* bl.l $disp24 */
 557   {
 558     M32R_INSN_BL24, "bl24", "bl.l", 32,
 559     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 560   },
 561 /* bcl.s $disp8 */
 562   {
 563     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
 564     { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 565   },
 566 /* bcl.l $disp24 */
 567   {
 568     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
 569     { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 570   },
 571 /* bnc.s $disp8 */
 572   {
 573     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
 574     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 575   },
 576 /* bnc.l $disp24 */
 577   {
 578     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
 579     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 580   },
 581 /* bne $src1,$src2,$disp16 */
 582   {
 583     M32R_INSN_BNE, "bne", "bne", 32,
 584     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 585   },
 586 /* bra.s $disp8 */
 587   {
 588     M32R_INSN_BRA8, "bra8", "bra.s", 16,
 589     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 590   },
 591 /* bra.l $disp24 */
 592   {
 593     M32R_INSN_BRA24, "bra24", "bra.l", 32,
 594     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 595   },
 596 /* bncl.s $disp8 */
 597   {
 598     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
 599     { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 600   },
 601 /* bncl.l $disp24 */
 602   {
 603     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
 604     { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 605   },
 606 /* cmp $src1,$src2 */
 607   {
 608     M32R_INSN_CMP, "cmp", "cmp", 16,
 609     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 610   },
 611 /* cmpi $src2,$simm16 */
 612   {
 613     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
 614     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 615   },
 616 /* cmpu $src1,$src2 */
 617   {
 618     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
 619     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 620   },
 621 /* cmpui $src2,$simm16 */
 622   {
 623     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
 624     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 625   },
 626 /* cmpeq $src1,$src2 */
 627   {
 628     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
 629     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
 630   },
 631 /* cmpz $src2 */
 632   {
 633     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
 634     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
 635   },
 636 /* div $dr,$sr */
 637   {
 638     M32R_INSN_DIV, "div", "div", 32,
 639     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 640   },
 641 /* divu $dr,$sr */
 642   {
 643     M32R_INSN_DIVU, "divu", "divu", 32,
 644     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 645   },
 646 /* rem $dr,$sr */
 647   {
 648     M32R_INSN_REM, "rem", "rem", 32,
 649     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 650   },
 651 /* remu $dr,$sr */
 652   {
 653     M32R_INSN_REMU, "remu", "remu", 32,
 654     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 655   },
 656 /* remh $dr,$sr */
 657   {
 658     M32R_INSN_REMH, "remh", "remh", 32,
 659     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 660   },
 661 /* remuh $dr,$sr */
 662   {
 663     M32R_INSN_REMUH, "remuh", "remuh", 32,
 664     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 665   },
 666 /* remb $dr,$sr */
 667   {
 668     M32R_INSN_REMB, "remb", "remb", 32,
 669     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 670   },
 671 /* remub $dr,$sr */
 672   {
 673     M32R_INSN_REMUB, "remub", "remub", 32,
 674     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 675   },
 676 /* divuh $dr,$sr */
 677   {
 678     M32R_INSN_DIVUH, "divuh", "divuh", 32,
 679     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 680   },
 681 /* divb $dr,$sr */
 682   {
 683     M32R_INSN_DIVB, "divb", "divb", 32,
 684     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 685   },
 686 /* divub $dr,$sr */
 687   {
 688     M32R_INSN_DIVUB, "divub", "divub", 32,
 689     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 690   },
 691 /* divh $dr,$sr */
 692   {
 693     M32R_INSN_DIVH, "divh", "divh", 32,
 694     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 695   },
 696 /* jc $sr */
 697   {
 698     M32R_INSN_JC, "jc", "jc", 16,
 699     { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 700   },
 701 /* jnc $sr */
 702   {
 703     M32R_INSN_JNC, "jnc", "jnc", 16,
 704     { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 705   },
 706 /* jl $sr */
 707   {
 708     M32R_INSN_JL, "jl", "jl", 16,
 709     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 710   },
 711 /* jmp $sr */
 712   {
 713     M32R_INSN_JMP, "jmp", "jmp", 16,
 714     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 715   },
 716 /* ld $dr,@$sr */
 717   {
 718     M32R_INSN_LD, "ld", "ld", 16,
 719     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 720   },
 721 /* ld $dr,@($slo16,$sr) */
 722   {
 723     M32R_INSN_LD_D, "ld-d", "ld", 32,
 724     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 725   },
 726 /* ldb $dr,@$sr */
 727   {
 728     M32R_INSN_LDB, "ldb", "ldb", 16,
 729     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 730   },
 731 /* ldb $dr,@($slo16,$sr) */
 732   {
 733     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
 734     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 735   },
 736 /* ldh $dr,@$sr */
 737   {
 738     M32R_INSN_LDH, "ldh", "ldh", 16,
 739     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 740   },
 741 /* ldh $dr,@($slo16,$sr) */
 742   {
 743     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
 744     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 745   },
 746 /* ldub $dr,@$sr */
 747   {
 748     M32R_INSN_LDUB, "ldub", "ldub", 16,
 749     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 750   },
 751 /* ldub $dr,@($slo16,$sr) */
 752   {
 753     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
 754     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 755   },
 756 /* lduh $dr,@$sr */
 757   {
 758     M32R_INSN_LDUH, "lduh", "lduh", 16,
 759     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 760   },
 761 /* lduh $dr,@($slo16,$sr) */
 762   {
 763     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
 764     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 765   },
 766 /* ld $dr,@$sr+ */
 767   {
 768     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
 769     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 770   },
 771 /* ld24 $dr,$uimm24 */
 772   {
 773     M32R_INSN_LD24, "ld24", "ld24", 32,
 774     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 775   },
 776 /* ldi8 $dr,$simm8 */
 777   {
 778     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
 779     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 780   },
 781 /* ldi16 $dr,$hash$slo16 */
 782   {
 783     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
 784     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 785   },
 786 /* lock $dr,@$sr */
 787   {
 788     M32R_INSN_LOCK, "lock", "lock", 16,
 789     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 790   },
 791 /* machi $src1,$src2 */
 792   {
 793     M32R_INSN_MACHI, "machi", "machi", 16,
 794     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 795   },
 796 /* machi $src1,$src2,$acc */
 797   {
 798     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
 799     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 800   },
 801 /* maclo $src1,$src2 */
 802   {
 803     M32R_INSN_MACLO, "maclo", "maclo", 16,
 804     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 805   },
 806 /* maclo $src1,$src2,$acc */
 807   {
 808     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
 809     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 810   },
 811 /* macwhi $src1,$src2 */
 812   {
 813     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
 814     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 815   },
 816 /* macwhi $src1,$src2,$acc */
 817   {
 818     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
 819     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 820   },
 821 /* macwlo $src1,$src2 */
 822   {
 823     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
 824     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 825   },
 826 /* macwlo $src1,$src2,$acc */
 827   {
 828     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
 829     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 830   },
 831 /* mul $dr,$sr */
 832   {
 833     M32R_INSN_MUL, "mul", "mul", 16,
 834     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } }
 835   },
 836 /* mulhi $src1,$src2 */
 837   {
 838     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
 839     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 840   },
 841 /* mulhi $src1,$src2,$acc */
 842   {
 843     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
 844     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 845   },
 846 /* mullo $src1,$src2 */
 847   {
 848     M32R_INSN_MULLO, "mullo", "mullo", 16,
 849     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 850   },
 851 /* mullo $src1,$src2,$acc */
 852   {
 853     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
 854     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 855   },
 856 /* mulwhi $src1,$src2 */
 857   {
 858     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
 859     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 860   },
 861 /* mulwhi $src1,$src2,$acc */
 862   {
 863     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
 864     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 865   },
 866 /* mulwlo $src1,$src2 */
 867   {
 868     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
 869     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 870   },
 871 /* mulwlo $src1,$src2,$acc */
 872   {
 873     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
 874     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 875   },
 876 /* mv $dr,$sr */
 877   {
 878     M32R_INSN_MV, "mv", "mv", 16,
 879     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 880   },
 881 /* mvfachi $dr */
 882   {
 883     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
 884     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 885   },
 886 /* mvfachi $dr,$accs */
 887   {
 888     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
 889     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 890   },
 891 /* mvfaclo $dr */
 892   {
 893     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
 894     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 895   },
 896 /* mvfaclo $dr,$accs */
 897   {
 898     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
 899     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 900   },
 901 /* mvfacmi $dr */
 902   {
 903     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
 904     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 905   },
 906 /* mvfacmi $dr,$accs */
 907   {
 908     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
 909     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 910   },
 911 /* mvfc $dr,$scr */
 912   {
 913     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
 914     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 915   },
 916 /* mvtachi $src1 */
 917   {
 918     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
 919     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 920   },
 921 /* mvtachi $src1,$accs */
 922   {
 923     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
 924     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 925   },
 926 /* mvtaclo $src1 */
 927   {
 928     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
 929     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 930   },
 931 /* mvtaclo $src1,$accs */
 932   {
 933     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
 934     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 935   },
 936 /* mvtc $sr,$dcr */
 937   {
 938     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
 939     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 940   },
 941 /* neg $dr,$sr */
 942   {
 943     M32R_INSN_NEG, "neg", "neg", 16,
 944     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 945   },
 946 /* nop */
 947   {
 948     M32R_INSN_NOP, "nop", "nop", 16,
 949     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 950   },
 951 /* not $dr,$sr */
 952   {
 953     M32R_INSN_NOT, "not", "not", 16,
 954     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 955   },
 956 /* rac */
 957   {
 958     M32R_INSN_RAC, "rac", "rac", 16,
 959     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 960   },
 961 /* rac $accd,$accs,$imm1 */
 962   {
 963     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
 964     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 965   },
 966 /* rach */
 967   {
 968     M32R_INSN_RACH, "rach", "rach", 16,
 969     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 970   },
 971 /* rach $accd,$accs,$imm1 */
 972   {
 973     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
 974     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 975   },
 976 /* rte */
 977   {
 978     M32R_INSN_RTE, "rte", "rte", 16,
 979     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 980   },
 981 /* seth $dr,$hash$hi16 */
 982   {
 983     M32R_INSN_SETH, "seth", "seth", 32,
 984     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 985   },
 986 /* sll $dr,$sr */
 987   {
 988     M32R_INSN_SLL, "sll", "sll", 16,
 989     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
 990   },
 991 /* sll3 $dr,$sr,$simm16 */
 992   {
 993     M32R_INSN_SLL3, "sll3", "sll3", 32,
 994     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 995   },
 996 /* slli $dr,$uimm5 */
 997   {
 998     M32R_INSN_SLLI, "slli", "slli", 16,
 999     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1000   },
1001 /* sra $dr,$sr */
1002   {
1003     M32R_INSN_SRA, "sra", "sra", 16,
1004     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1005   },
1006 /* sra3 $dr,$sr,$simm16 */
1007   {
1008     M32R_INSN_SRA3, "sra3", "sra3", 32,
1009     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1010   },
1011 /* srai $dr,$uimm5 */
1012   {
1013     M32R_INSN_SRAI, "srai", "srai", 16,
1014     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1015   },
1016 /* srl $dr,$sr */
1017   {
1018     M32R_INSN_SRL, "srl", "srl", 16,
1019     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1020   },
1021 /* srl3 $dr,$sr,$simm16 */
1022   {
1023     M32R_INSN_SRL3, "srl3", "srl3", 32,
1024     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1025   },
1026 /* srli $dr,$uimm5 */
1027   {
1028     M32R_INSN_SRLI, "srli", "srli", 16,
1029     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1030   },
1031 /* st $src1,@$src2 */
1032   {
1033     M32R_INSN_ST, "st", "st", 16,
1034     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1035   },
1036 /* st $src1,@($slo16,$src2) */
1037   {
1038     M32R_INSN_ST_D, "st-d", "st", 32,
1039     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1040   },
1041 /* stb $src1,@$src2 */
1042   {
1043     M32R_INSN_STB, "stb", "stb", 16,
1044     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1045   },
1046 /* stb $src1,@($slo16,$src2) */
1047   {
1048     M32R_INSN_STB_D, "stb-d", "stb", 32,
1049     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1050   },
1051 /* sth $src1,@$src2 */
1052   {
1053     M32R_INSN_STH, "sth", "sth", 16,
1054     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1055   },
1056 /* sth $src1,@($slo16,$src2) */
1057   {
1058     M32R_INSN_STH_D, "sth-d", "sth", 32,
1059     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1060   },
1061 /* st $src1,@+$src2 */
1062   {
1063     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1064     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1065   },
1066 /* sth $src1,@$src2+ */
1067   {
1068     M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
1069     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1070   },
1071 /* stb $src1,@$src2+ */
1072   {
1073     M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
1074     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1075   },
1076 /* st $src1,@-$src2 */
1077   {
1078     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1079     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1080   },
1081 /* sub $dr,$sr */
1082   {
1083     M32R_INSN_SUB, "sub", "sub", 16,
1084     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1085   },
1086 /* subv $dr,$sr */
1087   {
1088     M32R_INSN_SUBV, "subv", "subv", 16,
1089     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1090   },
1091 /* subx $dr,$sr */
1092   {
1093     M32R_INSN_SUBX, "subx", "subx", 16,
1094     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1095   },
1096 /* trap $uimm4 */
1097   {
1098     M32R_INSN_TRAP, "trap", "trap", 16,
1099     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1100   },
1101 /* unlock $src1,@$src2 */
1102   {
1103     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1104     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1105   },
1106 /* satb $dr,$sr */
1107   {
1108     M32R_INSN_SATB, "satb", "satb", 32,
1109     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1110   },
1111 /* sath $dr,$sr */
1112   {
1113     M32R_INSN_SATH, "sath", "sath", 32,
1114     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1115   },
1116 /* sat $dr,$sr */
1117   {
1118     M32R_INSN_SAT, "sat", "sat", 32,
1119     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1120   },
1121 /* pcmpbz $src2 */
1122   {
1123     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1124     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
1125   },
1126 /* sadd */
1127   {
1128     M32R_INSN_SADD, "sadd", "sadd", 16,
1129     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1130   },
1131 /* macwu1 $src1,$src2 */
1132   {
1133     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1134     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1135   },
1136 /* msblo $src1,$src2 */
1137   {
1138     M32R_INSN_MSBLO, "msblo", "msblo", 16,
1139     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1140   },
1141 /* mulwu1 $src1,$src2 */
1142   {
1143     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1144     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1145   },
1146 /* maclh1 $src1,$src2 */
1147   {
1148     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1149     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1150   },
1151 /* sc */
1152   {
1153     M32R_INSN_SC, "sc", "sc", 16,
1154     { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1155   },
1156 /* snc */
1157   {
1158     M32R_INSN_SNC, "snc", "snc", 16,
1159     { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1160   },
1161 /* clrpsw $uimm8 */
1162   {
1163     M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
1164     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1165   },
1166 /* setpsw $uimm8 */
1167   {
1168     M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
1169     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1170   },
1171 /* bset $uimm3,@($slo16,$sr) */
1172   {
1173     M32R_INSN_BSET, "bset", "bset", 32,
1174     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1175   },
1176 /* bclr $uimm3,@($slo16,$sr) */
1177   {
1178     M32R_INSN_BCLR, "bclr", "bclr", 32,
1179     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1180   },
1181 /* btst $uimm3,$sr */
1182   {
1183     M32R_INSN_BTST, "btst", "btst", 16,
1184     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1185   },
1186 };
1187
1188 #undef OP
1189 #undef A
1190
1191 /* Initialize anything needed to be done once, before any cpu_open call.  */
1192
1193 static void
1194 init_tables (void)
1195 {
1196 }
1197
1198 #ifndef opcodes_error_handler
1199 #define opcodes_error_handler(...) \
1200   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1201 #endif
1202
1203 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1204 static void build_hw_table      (CGEN_CPU_TABLE *);
1205 static void build_ifield_table  (CGEN_CPU_TABLE *);
1206 static void build_operand_table (CGEN_CPU_TABLE *);
1207 static void build_insn_table    (CGEN_CPU_TABLE *);
1208 static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1209
1210 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1211
1212 static const CGEN_MACH *
1213 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1214 {
1215   while (table->name)
1216     {
1217       if (strcmp (name, table->bfd_name) == 0)
1218         return table;
1219       ++table;
1220     }
1221   return NULL;
1222 }
1223
1224 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1225
1226 static void
1227 build_hw_table (CGEN_CPU_TABLE *cd)
1228 {
1229   int i;
1230   int machs = cd->machs;
1231   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1232   /* MAX_HW is only an upper bound on the number of selected entries.
1233      However each entry is indexed by it's enum so there can be holes in
1234      the table.  */
1235   const CGEN_HW_ENTRY **selected =
1236     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1237
1238   cd->hw_table.init_entries = init;
1239   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1240   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1241   /* ??? For now we just use machs to determine which ones we want.  */
1242   for (i = 0; init[i].name != NULL; ++i)
1243     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1244         & machs)
1245       selected[init[i].type] = &init[i];
1246   cd->hw_table.entries = selected;
1247   cd->hw_table.num_entries = MAX_HW;
1248 }
1249
1250 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1251
1252 static void
1253 build_ifield_table (CGEN_CPU_TABLE *cd)
1254 {
1255   cd->ifld_table = & m32r_cgen_ifld_table[0];
1256 }
1257
1258 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1259
1260 static void
1261 build_operand_table (CGEN_CPU_TABLE *cd)
1262 {
1263   int i;
1264   int machs = cd->machs;
1265   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1266   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1267      However each entry is indexed by it's enum so there can be holes in
1268      the table.  */
1269   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1270
1271   cd->operand_table.init_entries = init;
1272   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1273   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1274   /* ??? For now we just use mach to determine which ones we want.  */
1275   for (i = 0; init[i].name != NULL; ++i)
1276     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1277         & machs)
1278       selected[init[i].type] = &init[i];
1279   cd->operand_table.entries = selected;
1280   cd->operand_table.num_entries = MAX_OPERANDS;
1281 }
1282
1283 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1284    ??? This could leave out insns not supported by the specified mach/isa,
1285    but that would cause errors like "foo only supported by bar" to become
1286    "unknown insn", so for now we include all insns and require the app to
1287    do the checking later.
1288    ??? On the other hand, parsing of such insns may require their hardware or
1289    operand elements to be in the table [which they mightn't be].  */
1290
1291 static void
1292 build_insn_table (CGEN_CPU_TABLE *cd)
1293 {
1294   int i;
1295   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1296   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1297
1298   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1299   for (i = 0; i < MAX_INSNS; ++i)
1300     insns[i].base = &ib[i];
1301   cd->insn_table.init_entries = insns;
1302   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1303   cd->insn_table.num_init_entries = MAX_INSNS;
1304 }
1305
1306 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1307
1308 static void
1309 m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1310 {
1311   int i;
1312   CGEN_BITSET *isas = cd->isas;
1313   unsigned int machs = cd->machs;
1314
1315   cd->int_insn_p = CGEN_INT_INSN_P;
1316
1317   /* Data derived from the isa spec.  */
1318 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1319   cd->default_insn_bitsize = UNSET;
1320   cd->base_insn_bitsize = UNSET;
1321   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1322   cd->max_insn_bitsize = 0;
1323   for (i = 0; i < MAX_ISAS; ++i)
1324     if (cgen_bitset_contains (isas, i))
1325       {
1326         const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1327
1328         /* Default insn sizes of all selected isas must be
1329            equal or we set the result to 0, meaning "unknown".  */
1330         if (cd->default_insn_bitsize == UNSET)
1331           cd->default_insn_bitsize = isa->default_insn_bitsize;
1332         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1333           ; /* This is ok.  */
1334         else
1335           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1336
1337         /* Base insn sizes of all selected isas must be equal
1338            or we set the result to 0, meaning "unknown".  */
1339         if (cd->base_insn_bitsize == UNSET)
1340           cd->base_insn_bitsize = isa->base_insn_bitsize;
1341         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1342           ; /* This is ok.  */
1343         else
1344           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1345
1346         /* Set min,max insn sizes.  */
1347         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1348           cd->min_insn_bitsize = isa->min_insn_bitsize;
1349         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1350           cd->max_insn_bitsize = isa->max_insn_bitsize;
1351       }
1352
1353   /* Data derived from the mach spec.  */
1354   for (i = 0; i < MAX_MACHS; ++i)
1355     if (((1 << i) & machs) != 0)
1356       {
1357         const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1358
1359         if (mach->insn_chunk_bitsize != 0)
1360         {
1361           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1362             {
1363               opcodes_error_handler
1364                 (/* xgettext:c-format */
1365                  _("internal error: m32r_cgen_rebuild_tables: "
1366                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1367                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1368               abort ();
1369             }
1370
1371           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1372         }
1373       }
1374
1375   /* Determine which hw elements are used by MACH.  */
1376   build_hw_table (cd);
1377
1378   /* Build the ifield table.  */
1379   build_ifield_table (cd);
1380
1381   /* Determine which operands are used by MACH/ISA.  */
1382   build_operand_table (cd);
1383
1384   /* Build the instruction table.  */
1385   build_insn_table (cd);
1386 }
1387
1388 /* Initialize a cpu table and return a descriptor.
1389    It's much like opening a file, and must be the first function called.
1390    The arguments are a set of (type/value) pairs, terminated with
1391    CGEN_CPU_OPEN_END.
1392
1393    Currently supported values:
1394    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1395    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1396    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1397    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1398    CGEN_CPU_OPEN_END:     terminates arguments
1399
1400    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1401    precluded.  */
1402
1403 CGEN_CPU_DESC
1404 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1405 {
1406   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1407   static int init_p;
1408   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1409   unsigned int machs = 0; /* 0 = "unspecified" */
1410   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1411   va_list ap;
1412
1413   if (! init_p)
1414     {
1415       init_tables ();
1416       init_p = 1;
1417     }
1418
1419   memset (cd, 0, sizeof (*cd));
1420
1421   va_start (ap, arg_type);
1422   while (arg_type != CGEN_CPU_OPEN_END)
1423     {
1424       switch (arg_type)
1425         {
1426         case CGEN_CPU_OPEN_ISAS :
1427           isas = va_arg (ap, CGEN_BITSET *);
1428           break;
1429         case CGEN_CPU_OPEN_MACHS :
1430           machs = va_arg (ap, unsigned int);
1431           break;
1432         case CGEN_CPU_OPEN_BFDMACH :
1433           {
1434             const char *name = va_arg (ap, const char *);
1435             const CGEN_MACH *mach =
1436               lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1437
1438             if (mach != NULL)
1439               machs |= 1 << mach->num;
1440             break;
1441           }
1442         case CGEN_CPU_OPEN_ENDIAN :
1443           endian = va_arg (ap, enum cgen_endian);
1444           break;
1445         default :
1446           opcodes_error_handler
1447             (/* xgettext:c-format */
1448              _("internal error: m32r_cgen_cpu_open: "
1449                "unsupported argument `%d'"),
1450              arg_type);
1451           abort (); /* ??? return NULL? */
1452         }
1453       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1454     }
1455   va_end (ap);
1456
1457   /* Mach unspecified means "all".  */
1458   if (machs == 0)
1459     machs = (1 << MAX_MACHS) - 1;
1460   /* Base mach is always selected.  */
1461   machs |= 1;
1462   if (endian == CGEN_ENDIAN_UNKNOWN)
1463     {
1464       /* ??? If target has only one, could have a default.  */
1465       opcodes_error_handler
1466         (/* xgettext:c-format */
1467          _("internal error: m32r_cgen_cpu_open: no endianness specified"));
1468       abort ();
1469     }
1470
1471   cd->isas = cgen_bitset_copy (isas);
1472   cd->machs = machs;
1473   cd->endian = endian;
1474   /* FIXME: for the sparc case we can determine insn-endianness statically.
1475      The worry here is where both data and insn endian can be independently
1476      chosen, in which case this function will need another argument.
1477      Actually, will want to allow for more arguments in the future anyway.  */
1478   cd->insn_endian = endian;
1479
1480   /* Table (re)builder.  */
1481   cd->rebuild_tables = m32r_cgen_rebuild_tables;
1482   m32r_cgen_rebuild_tables (cd);
1483
1484   /* Default to not allowing signed overflow.  */
1485   cd->signed_overflow_ok_p = 0;
1486
1487   return (CGEN_CPU_DESC) cd;
1488 }
1489
1490 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1491    MACH_NAME is the bfd name of the mach.  */
1492
1493 CGEN_CPU_DESC
1494 m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1495 {
1496   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1497                                CGEN_CPU_OPEN_ENDIAN, endian,
1498                                CGEN_CPU_OPEN_END);
1499 }
1500
1501 /* Close a cpu table.
1502    ??? This can live in a machine independent file, but there's currently
1503    no place to put this file (there's no libcgen).  libopcodes is the wrong
1504    place as some simulator ports use this but they don't use libopcodes.  */
1505
1506 void
1507 m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
1508 {
1509   unsigned int i;
1510   const CGEN_INSN *insns;
1511
1512   if (cd->macro_insn_table.init_entries)
1513     {
1514       insns = cd->macro_insn_table.init_entries;
1515       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1516         if (CGEN_INSN_RX ((insns)))
1517           regfree (CGEN_INSN_RX (insns));
1518     }
1519
1520   if (cd->insn_table.init_entries)
1521     {
1522       insns = cd->insn_table.init_entries;
1523       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1524         if (CGEN_INSN_RX (insns))
1525           regfree (CGEN_INSN_RX (insns));
1526     }
1527
1528   if (cd->macro_insn_table.init_entries)
1529     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1530
1531   if (cd->insn_table.init_entries)
1532     free ((CGEN_INSN *) cd->insn_table.init_entries);
1533
1534   if (cd->hw_table.entries)
1535     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1536
1537   if (cd->operand_table.entries)
1538     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1539
1540   free (cd);
1541 }
1542