opcodes/m32r-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
   8 Free Software Foundation, Inc.
   9
  10 This file is part of the GNU Binutils and GDB, the GNU debugger.
  11
  12 This program is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2, or (at your option)
  15 any later version.
  16
  17 This program is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with this program; if not, write to the Free Software Foundation, Inc.,
  24 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "m32r-desc.h"
  37 #include "m32r-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
  45 static void print_address
  46   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
  47 static void print_keyword
  48   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
  49 static void print_insn_normal
  50   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
  51 static int print_insn
  52   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
  53 static int default_print_insn
  54   (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
  55 static int read_insn
  56   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
  57    unsigned long *);
  58 \f
  59 /* -- disassembler routines inserted here */
  60
  61 /* -- dis.c */
  62 static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  63 static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  64
  65 /* Immediate values are prefixed with '#'.  */
  66
  67 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)   \
  68   do                                                            \
  69     {                                                           \
  70       if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX))   \
  71         (*info->fprintf_func) (info->stream, "#");              \
  72     }                                                           \
  73   while (0)
  74
  75 /* Handle '#' prefixes as operands.  */
  76
  77 static void
  78 print_hash (cd, dis_info, value, attrs, pc, length)
  79      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
  80      PTR dis_info;
  81      long value ATTRIBUTE_UNUSED;
  82      unsigned int attrs ATTRIBUTE_UNUSED;
  83      bfd_vma pc ATTRIBUTE_UNUSED;
  84      int length ATTRIBUTE_UNUSED;
  85 {
  86   disassemble_info *info = (disassemble_info *) dis_info;
  87   (*info->fprintf_func) (info->stream, "#");
  88 }
  89
  90 #undef  CGEN_PRINT_INSN
  91 #define CGEN_PRINT_INSN my_print_insn
  92
  93 static int
  94 my_print_insn (cd, pc, info)
  95      CGEN_CPU_DESC cd;
  96      bfd_vma pc;
  97      disassemble_info *info;
  98 {
  99   char buffer[CGEN_MAX_INSN_SIZE];
 100   char *buf = buffer;
 101   int status;
 102   int buflen = (pc & 3) == 0 ? 4 : 2;
 103   int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
 104   char *x;
 105
 106   /* Read the base part of the insn.  */
 107
 108   status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
 109                                       buf, buflen, info);
 110   if (status != 0)
 111     {
 112       (*info->memory_error_func) (status, pc, info);
 113       return -1;
 114     }
 115
 116   /* 32 bit insn?  */
 117   x = (big_p ? &buf[0] : &buf[3]);
 118   if ((pc & 3) == 0 && (*x & 0x80) != 0)
 119     return print_insn (cd, pc, info, buf, buflen);
 120
 121   /* Print the first insn.  */
 122   if ((pc & 3) == 0)
 123     {
 124       buf += (big_p ? 0 : 2);
 125       if (print_insn (cd, pc, info, buf, 2) == 0)
 126         (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 127       buf += (big_p ? 2 : -2);
 128     }
 129
 130   x = (big_p ? &buf[0] : &buf[1]);
 131   if (*x & 0x80)
 132     {
 133       /* Parallel.  */
 134       (*info->fprintf_func) (info->stream, " || ");
 135       *x &= 0x7f;
 136     }
 137   else
 138     (*info->fprintf_func) (info->stream, " -> ");
 139
 140   /* The "& 3" is to pass a consistent address.
 141      Parallel insns arguably both begin on the word boundary.
 142      Also, branch insns are calculated relative to the word boundary.  */
 143   if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
 144     (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 145
 146   return (pc & 3) ? 2 : 4;
 147 }
 148
 149 /* -- */
 150
 151 void m32r_cgen_print_operand
 152   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
 153            void const *, bfd_vma, int));
 154
 155 /* Main entry point for printing operands.
 156    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 157    of dis-asm.h on cgen.h.
 158
 159    This function is basically just a big switch statement.  Earlier versions
 160    used tables to look up the function to use, but
 161    - if the table contains both assembler and disassembler functions then
 162      the disassembler contains much of the assembler and vice-versa,
 163    - there's a lot of inlining possibilities as things grow,
 164    - using a switch statement avoids the function call overhead.
 165
 166    This function could be moved into `print_insn_normal', but keeping it
 167    separate makes clear the interface between `print_insn_normal' and each of
 168    the handlers.  */
 169
 170 void
 171 m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 172      CGEN_CPU_DESC cd;
 173      int opindex;
 174      PTR xinfo;
 175      CGEN_FIELDS *fields;
 176      void const *attrs ATTRIBUTE_UNUSED;
 177      bfd_vma pc;
 178      int length;
 179 {
 180  disassemble_info *info = (disassemble_info *) xinfo;
 181
 182   switch (opindex)
 183     {
 184     case M32R_OPERAND_ACC :
 185       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
 186       break;
 187     case M32R_OPERAND_ACCD :
 188       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
 189       break;
 190     case M32R_OPERAND_ACCS :
 191       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
 192       break;
 193     case M32R_OPERAND_DCR :
 194       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
 195       break;
 196     case M32R_OPERAND_DISP16 :
 197       print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 198       break;
 199     case M32R_OPERAND_DISP24 :
 200       print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 201       break;
 202     case M32R_OPERAND_DISP8 :
 203       print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 204       break;
 205     case M32R_OPERAND_DR :
 206       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 207       break;
 208     case M32R_OPERAND_HASH :
 209       print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 210       break;
 211     case M32R_OPERAND_HI16 :
 212       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 213       break;
 214     case M32R_OPERAND_IMM1 :
 215       print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 216       break;
 217     case M32R_OPERAND_SCR :
 218       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
 219       break;
 220     case M32R_OPERAND_SIMM16 :
 221       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 222       break;
 223     case M32R_OPERAND_SIMM8 :
 224       print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 225       break;
 226     case M32R_OPERAND_SLO16 :
 227       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 228       break;
 229     case M32R_OPERAND_SR :
 230       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 231       break;
 232     case M32R_OPERAND_SRC1 :
 233       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 234       break;
 235     case M32R_OPERAND_SRC2 :
 236       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 237       break;
 238     case M32R_OPERAND_UIMM16 :
 239       print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 240       break;
 241     case M32R_OPERAND_UIMM24 :
 242       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 243       break;
 244     case M32R_OPERAND_UIMM3 :
 245       print_normal (cd, info, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 246       break;
 247     case M32R_OPERAND_UIMM4 :
 248       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 249       break;
 250     case M32R_OPERAND_UIMM5 :
 251       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 252       break;
 253     case M32R_OPERAND_UIMM8 :
 254       print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 255       break;
 256     case M32R_OPERAND_ULO16 :
 257       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 258       break;
 259
 260     default :
 261       /* xgettext:c-format */
 262       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 263                opindex);
 264     abort ();
 265   }
 266 }
 267
 268 cgen_print_fn * const m32r_cgen_print_handlers[] =
 269 {
 270   print_insn_normal,
 271 };
 272
 273
 274 void
 275 m32r_cgen_init_dis (cd)
 276      CGEN_CPU_DESC cd;
 277 {
 278   m32r_cgen_init_opcode_table (cd);
 279   m32r_cgen_init_ibld_table (cd);
 280   cd->print_handlers = & m32r_cgen_print_handlers[0];
 281   cd->print_operand = m32r_cgen_print_operand;
 282 }
 283
 284 \f
 285 /* Default print handler.  */
 286
 287 static void
 288 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 289               void *dis_info,
 290               long value,
 291               unsigned int attrs,
 292               bfd_vma pc ATTRIBUTE_UNUSED,
 293               int length ATTRIBUTE_UNUSED)
 294 {
 295   disassemble_info *info = (disassemble_info *) dis_info;
 296
 297 #ifdef CGEN_PRINT_NORMAL
 298   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 299 #endif
 300
 301   /* Print the operand as directed by the attributes.  */
 302   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 303     ; /* nothing to do */
 304   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 305     (*info->fprintf_func) (info->stream, "%ld", value);
 306   else
 307     (*info->fprintf_func) (info->stream, "0x%lx", value);
 308 }
 309
 310 /* Default address handler.  */
 311
 312 static void
 313 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 314                void *dis_info,
 315                bfd_vma value,
 316                unsigned int attrs,
 317                bfd_vma pc ATTRIBUTE_UNUSED,
 318                int length ATTRIBUTE_UNUSED)
 319 {
 320   disassemble_info *info = (disassemble_info *) dis_info;
 321
 322 #ifdef CGEN_PRINT_ADDRESS
 323   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 324 #endif
 325
 326   /* Print the operand as directed by the attributes.  */
 327   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 328     ; /* nothing to do */
 329   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 330     (*info->print_address_func) (value, info);
 331   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 332     (*info->print_address_func) (value, info);
 333   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 334     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 335   else
 336     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 337 }
 338
 339 /* Keyword print handler.  */
 340
 341 static void
 342 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 343                void *dis_info,
 344                CGEN_KEYWORD *keyword_table,
 345                long value,
 346                unsigned int attrs ATTRIBUTE_UNUSED)
 347 {
 348   disassemble_info *info = (disassemble_info *) dis_info;
 349   const CGEN_KEYWORD_ENTRY *ke;
 350
 351   ke = cgen_keyword_lookup_value (keyword_table, value);
 352   if (ke != NULL)
 353     (*info->fprintf_func) (info->stream, "%s", ke->name);
 354   else
 355     (*info->fprintf_func) (info->stream, "???");
 356 }
 357 \f
 358 /* Default insn printer.
 359
 360    DIS_INFO is defined as `void *' so the disassembler needn't know anything
 361    about disassemble_info.  */
 362
 363 static void
 364 print_insn_normal (CGEN_CPU_DESC cd,
 365                    void *dis_info,
 366                    const CGEN_INSN *insn,
 367                    CGEN_FIELDS *fields,
 368                    bfd_vma pc,
 369                    int length)
 370 {
 371   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 372   disassemble_info *info = (disassemble_info *) dis_info;
 373   const CGEN_SYNTAX_CHAR_TYPE *syn;
 374
 375   CGEN_INIT_PRINT (cd);
 376
 377   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 378     {
 379       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 380         {
 381           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 382           continue;
 383         }
 384       if (CGEN_SYNTAX_CHAR_P (*syn))
 385         {
 386           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 387           continue;
 388         }
 389
 390       /* We have an operand.  */
 391       m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 392                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 393     }
 394 }
 395 \f
 396 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 397    the extract info.
 398    Returns 0 if all is well, non-zero otherwise.  */
 399
 400 static int
 401 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 402            bfd_vma pc,
 403            disassemble_info *info,
 404            char *buf,
 405            int buflen,
 406            CGEN_EXTRACT_INFO *ex_info,
 407            unsigned long *insn_value)
 408 {
 409   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 410   if (status != 0)
 411     {
 412       (*info->memory_error_func) (status, pc, info);
 413       return -1;
 414     }
 415
 416   ex_info->dis_info = info;
 417   ex_info->valid = (1 << buflen) - 1;
 418   ex_info->insn_bytes = buf;
 419
 420   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 421   return 0;
 422 }
 423
 424 /* Utility to print an insn.
 425    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 426    The result is the size of the insn in bytes or zero for an unknown insn
 427    or -1 if an error occurs fetching data (memory_error_func will have
 428    been called).  */
 429
 430 static int
 431 print_insn (CGEN_CPU_DESC cd,
 432             bfd_vma pc,
 433             disassemble_info *info,
 434             char *buf,
 435             unsigned int buflen)
 436 {
 437   CGEN_INSN_INT insn_value;
 438   const CGEN_INSN_LIST *insn_list;
 439   CGEN_EXTRACT_INFO ex_info;
 440   int basesize;
 441
 442   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 443   basesize = cd->base_insn_bitsize < buflen * 8 ?
 444                                      cd->base_insn_bitsize : buflen * 8;
 445   insn_value = cgen_get_insn_value (cd, buf, basesize);
 446
 447
 448   /* Fill in ex_info fields like read_insn would.  Don't actually call
 449      read_insn, since the incoming buffer is already read (and possibly
 450      modified a la m32r).  */
 451   ex_info.valid = (1 << buflen) - 1;
 452   ex_info.dis_info = info;
 453   ex_info.insn_bytes = buf;
 454
 455   /* The instructions are stored in hash lists.
 456      Pick the first one and keep trying until we find the right one.  */
 457
 458   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 459   while (insn_list != NULL)
 460     {
 461       const CGEN_INSN *insn = insn_list->insn;
 462       CGEN_FIELDS fields;
 463       int length;
 464       unsigned long insn_value_cropped;
 465
 466 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 467       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 468       /* Supported by this cpu?  */
 469       if (! m32r_cgen_insn_supported (cd, insn))
 470         {
 471           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 472           continue;
 473         }
 474 #endif
 475
 476       /* Basic bit mask must be correct.  */
 477       /* ??? May wish to allow target to defer this check until the extract
 478          handler.  */
 479
 480       /* Base size may exceed this instruction's size.  Extract the
 481          relevant part from the buffer. */
 482       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 483           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 484         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 485                                            info->endian == BFD_ENDIAN_BIG);
 486       else
 487         insn_value_cropped = insn_value;
 488
 489       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 490           == CGEN_INSN_BASE_VALUE (insn))
 491         {
 492           /* Printing is handled in two passes.  The first pass parses the
 493              machine insn and extracts the fields.  The second pass prints
 494              them.  */
 495
 496           /* Make sure the entire insn is loaded into insn_value, if it
 497              can fit.  */
 498           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 499               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 500             {
 501               unsigned long full_insn_value;
 502               int rc = read_insn (cd, pc, info, buf,
 503                                   CGEN_INSN_BITSIZE (insn) / 8,
 504                                   & ex_info, & full_insn_value);
 505               if (rc != 0)
 506                 return rc;
 507               length = CGEN_EXTRACT_FN (cd, insn)
 508                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 509             }
 510           else
 511             length = CGEN_EXTRACT_FN (cd, insn)
 512               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 513
 514           /* length < 0 -> error */
 515           if (length < 0)
 516             return length;
 517           if (length > 0)
 518             {
 519               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 520               /* length is in bits, result is in bytes */
 521               return length / 8;
 522             }
 523         }
 524
 525       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 526     }
 527
 528   return 0;
 529 }
 530
 531 /* Default value for CGEN_PRINT_INSN.
 532    The result is the size of the insn in bytes or zero for an unknown insn
 533    or -1 if an error occured fetching bytes.  */
 534
 535 #ifndef CGEN_PRINT_INSN
 536 #define CGEN_PRINT_INSN default_print_insn
 537 #endif
 538
 539 static int
 540 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 541 {
 542   char buf[CGEN_MAX_INSN_SIZE];
 543   int buflen;
 544   int status;
 545
 546   /* Attempt to read the base part of the insn.  */
 547   buflen = cd->base_insn_bitsize / 8;
 548   status = (*info->read_memory_func) (pc, buf, buflen, info);
 549
 550   /* Try again with the minimum part, if min < base.  */
 551   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 552     {
 553       buflen = cd->min_insn_bitsize / 8;
 554       status = (*info->read_memory_func) (pc, buf, buflen, info);
 555     }
 556
 557   if (status != 0)
 558     {
 559       (*info->memory_error_func) (status, pc, info);
 560       return -1;
 561     }
 562
 563   return print_insn (cd, pc, info, buf, buflen);
 564 }
 565
 566 /* Main entry point.
 567    Print one instruction from PC on INFO->STREAM.
 568    Return the size of the instruction (in bytes).  */
 569
 570 typedef struct cpu_desc_list {
 571   struct cpu_desc_list *next;
 572   int isa;
 573   int mach;
 574   int endian;
 575   CGEN_CPU_DESC cd;
 576 } cpu_desc_list;
 577
 578 int
 579 print_insn_m32r (bfd_vma pc, disassemble_info *info)
 580 {
 581   static cpu_desc_list *cd_list = 0;
 582   cpu_desc_list *cl = 0;
 583   static CGEN_CPU_DESC cd = 0;
 584   static int prev_isa;
 585   static int prev_mach;
 586   static int prev_endian;
 587   int length;
 588   int isa,mach;
 589   int endian = (info->endian == BFD_ENDIAN_BIG
 590                 ? CGEN_ENDIAN_BIG
 591                 : CGEN_ENDIAN_LITTLE);
 592   enum bfd_architecture arch;
 593
 594   /* ??? gdb will set mach but leave the architecture as "unknown" */
 595 #ifndef CGEN_BFD_ARCH
 596 #define CGEN_BFD_ARCH bfd_arch_m32r
 597 #endif
 598   arch = info->arch;
 599   if (arch == bfd_arch_unknown)
 600     arch = CGEN_BFD_ARCH;
 601
 602   /* There's no standard way to compute the machine or isa number
 603      so we leave it to the target.  */
 604 #ifdef CGEN_COMPUTE_MACH
 605   mach = CGEN_COMPUTE_MACH (info);
 606 #else
 607   mach = info->mach;
 608 #endif
 609
 610 #ifdef CGEN_COMPUTE_ISA
 611   isa = CGEN_COMPUTE_ISA (info);
 612 #else
 613   isa = info->insn_sets;
 614 #endif
 615
 616   /* If we've switched cpu's, try to find a handle we've used before */
 617   if (cd
 618       && (isa != prev_isa
 619           || mach != prev_mach
 620           || endian != prev_endian))
 621     {
 622       cd = 0;
 623       for (cl = cd_list; cl; cl = cl->next)
 624         {
 625           if (cl->isa == isa &&
 626               cl->mach == mach &&
 627               cl->endian == endian)
 628             {
 629               cd = cl->cd;
 630               break;
 631             }
 632         }
 633     }
 634
 635   /* If we haven't initialized yet, initialize the opcode table.  */
 636   if (! cd)
 637     {
 638       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 639       const char *mach_name;
 640
 641       if (!arch_type)
 642         abort ();
 643       mach_name = arch_type->printable_name;
 644
 645       prev_isa = isa;
 646       prev_mach = mach;
 647       prev_endian = endian;
 648       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 649                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 650                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 651                                  CGEN_CPU_OPEN_END);
 652       if (!cd)
 653         abort ();
 654
 655       /* save this away for future reference */
 656       cl = xmalloc (sizeof (struct cpu_desc_list));
 657       cl->cd = cd;
 658       cl->isa = isa;
 659       cl->mach = mach;
 660       cl->endian = endian;
 661       cl->next = cd_list;
 662       cd_list = cl;
 663
 664       m32r_cgen_init_dis (cd);
 665     }
 666
 667   /* We try to have as much common code as possible.
 668      But at this point some targets need to take over.  */
 669   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 670      but if not possible try to move this hook elsewhere rather than
 671      have two hooks.  */
 672   length = CGEN_PRINT_INSN (cd, pc, info);
 673   if (length > 0)
 674     return length;
 675   if (length < 0)
 676     return -1;
 677
 678   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 679   return cd->default_insn_bitsize / 8;
 680 }