opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 This file is used to generate m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software
  22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31
  32 /* Look up instruction INSN_VALUE and extract its fields.
  33    INSN, if non-null, is the insn table entry.
  34    Otherwise INSN_VALUE is examined to compute it.
  35    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  36    0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
  37    If INSN != NULL, LENGTH must be valid.
  38    ALIAS_P is non-zero if alias insns are to be included in the search.
  39
  40    The result a pointer to the insn table entry, or NULL if the instruction
  41    wasn't recognized.  */
  42
  43 const CGEN_INSN *
  44 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  45      const CGEN_INSN *insn;
  46      cgen_insn_t insn_value;
  47      int length;
  48      CGEN_FIELDS *fields;
  49      int alias_p;
  50 {
  51   char buf[16];
  52
  53   if (!insn)
  54     {
  55       const CGEN_INSN_LIST *insn_list;
  56
  57 #ifdef CGEN_INT_INSN
  58       switch (length)
  59         {
  60         case 8:
  61           buf[0] = insn_value;
  62           break;
  63         case 16:
  64           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  65             bfd_putb16 (insn_value, buf);
  66           else
  67             bfd_putl16 (insn_value, buf);
  68           break;
  69         case 32:
  70           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  71             bfd_putb32 (insn_value, buf);
  72           else
  73             bfd_putl32 (insn_value, buf);
  74           break;
  75         default:
  76           abort ();
  77         }
  78 #else
  79       abort (); /* FIXME: unfinished */
  80 #endif
  81
  82       /* The instructions are stored in hash lists.
  83          Pick the first one and keep trying until we find the right one.  */
  84
  85       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  86       while (insn_list != NULL)
  87         {
  88           insn = insn_list->insn;
  89
  90           if (alias_p
  91               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  92             {
  93               /* Basic bit mask must be correct.  */
  94               /* ??? May wish to allow target to defer this check until the
  95                  extract handler.  */
  96               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  97                 {
  98                   int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
  99                                                            insn_value, fields);
 100                   if (elength > 0)
 101                     {
 102                       /* sanity check */
 103                       if (length != 0 && length != elength)
 104                         abort ();
 105                       return insn;
 106                     }
 107                 }
 108             }
 109
 110           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 111         }
 112     }
 113   else
 114     {
 115       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 116       if (! alias_p
 117           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 118         abort ();
 119       /* Sanity check: length must be correct.  */
 120       if (length != CGEN_INSN_BITSIZE (insn))
 121         abort ();
 122
 123       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
 124       /* Sanity check: must succeed.
 125          Could relax this later if it ever proves useful.  */
 126       if (length == 0)
 127         abort ();
 128       return insn;
 129     }
 130
 131   return NULL;
 132 }
 133
 134 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 135    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 136    in.  */
 137
 138 void
 139 m32r_cgen_get_insn_operands (insn, fields, indices)
 140      const CGEN_INSN * insn;
 141      const CGEN_FIELDS * fields;
 142      int *indices;
 143 {
 144   const CGEN_OPERAND_INSTANCE *opinst;
 145   int i;
 146
 147   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 148        opinst != NULL
 149          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 150        ++i, ++opinst)
 151     {
 152       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 153       if (op == NULL)
 154         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 155       else
 156         indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), fields);
 157     }
 158 }
 159
 160 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
 161    isn't known.
 162    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 163    m32r_cgen_lookup_insn unchanged.
 164
 165    The result is the insn table entry or NULL if the instruction wasn't
 166    recognized.  */
 167
 168 const CGEN_INSN *
 169 m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
 170      const CGEN_INSN *insn;
 171      cgen_insn_t insn_value;
 172      int length;
 173      int *indices;
 174 {
 175   CGEN_FIELDS fields;
 176
 177   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 178      If INSN == NULL, we want a real insn.  */
 179   insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields,
 180                                   insn != NULL);
 181   if (! insn)
 182     return NULL;
 183
 184   m32r_cgen_get_insn_operands (insn, &fields, indices);
 185   return insn;
 186 }
 187 /* Attributes.  */
 188
 189 static const CGEN_ATTR_ENTRY MACH_attr[] =
 190 {
 191   { "m32r", MACH_M32R },
 192 /* start-sanitize-m32rx */
 193   { "m32rx", MACH_M32RX },
 194 /* end-sanitize-m32rx */
 195   { "max", MACH_MAX },
 196   { 0, 0 }
 197 };
 198
 199 /* start-sanitize-m32rx */
 200 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 201 {
 202   { "NONE", PIPE_NONE },
 203   { "O", PIPE_O },
 204   { "S", PIPE_S },
 205   { "OS", PIPE_OS },
 206   { 0, 0 }
 207 };
 208
 209 /* end-sanitize-m32rx */
 210 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 211 {
 212   { "ABS-ADDR", NULL },
 213   { "FAKE", NULL },
 214   { "HASH-PREFIX", NULL },
 215   { "NEGATIVE", NULL },
 216   { "PC", NULL },
 217   { "PCREL-ADDR", NULL },
 218   { "RELAX", NULL },
 219   { "RELOC", NULL },
 220   { "SIGN-OPT", NULL },
 221   { "UNSIGNED", NULL },
 222   { 0, 0 }
 223 };
 224
 225 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 226 {
 227   { "MACH", & MACH_attr[0] },
 228 /* start-sanitize-m32rx */
 229   { "PIPE", & PIPE_attr[0] },
 230 /* end-sanitize-m32rx */
 231   { "ALIAS", NULL },
 232   { "COND-CTI", NULL },
 233   { "FILL-SLOT", NULL },
 234   { "NO-DIS", NULL },
 235   { "PARALLEL", NULL },
 236   { "RELAX", NULL },
 237   { "RELAXABLE", NULL },
 238   { "UNCOND-CTI", NULL },
 239   { 0, 0 }
 240 };
 241
 242 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 243 {
 244   { "fp", 13 },
 245   { "lr", 14 },
 246   { "sp", 15 },
 247   { "r0", 0 },
 248   { "r1", 1 },
 249   { "r2", 2 },
 250   { "r3", 3 },
 251   { "r4", 4 },
 252   { "r5", 5 },
 253   { "r6", 6 },
 254   { "r7", 7 },
 255   { "r8", 8 },
 256   { "r9", 9 },
 257   { "r10", 10 },
 258   { "r11", 11 },
 259   { "r12", 12 },
 260   { "r13", 13 },
 261   { "r14", 14 },
 262   { "r15", 15 }
 263 };
 264
 265 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 266 {
 267   & m32r_cgen_opval_h_gr_entries[0],
 268   19
 269 };
 270
 271 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 272 {
 273   { "psw", 0 },
 274   { "cbr", 1 },
 275   { "spi", 2 },
 276   { "spu", 3 },
 277   { "bpc", 6 },
 278   { "cr0", 0 },
 279   { "cr1", 1 },
 280   { "cr2", 2 },
 281   { "cr3", 3 },
 282   { "cr4", 4 },
 283   { "cr5", 5 },
 284   { "cr6", 6 },
 285   { "cr7", 7 },
 286   { "cr8", 8 },
 287   { "cr9", 9 },
 288   { "cr10", 10 },
 289   { "cr11", 11 },
 290   { "cr12", 12 },
 291   { "cr13", 13 },
 292   { "cr14", 14 },
 293   { "cr15", 15 }
 294 };
 295
 296 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 297 {
 298   & m32r_cgen_opval_h_cr_entries[0],
 299   21
 300 };
 301
 302 /* start-sanitize-m32rx */
 303 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 304 {
 305   { "a0", 0 },
 306   { "a1", 1 }
 307 };
 308
 309 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 310 {
 311   & m32r_cgen_opval_h_accums_entries[0],
 312   2
 313 };
 314
 315 /* end-sanitize-m32rx */
 316
 317 /* The hardware table.  */
 318
 319 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 320 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 321 {
 322   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 323   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 324   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 325   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 326   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 327   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 328   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 329   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 330   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 331   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 332   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 333   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 334 /* start-sanitize-m32rx */
 335   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 336 /* end-sanitize-m32rx */
 337 /* start-sanitize-m32rx */
 338   { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
 339 /* end-sanitize-m32rx */
 340   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 341   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 342   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 343   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 344   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 345   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 346   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 347   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
 348   { 0 }
 349 };
 350
 351 /* The operand table.  */
 352
 353 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 354 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 355
 356 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 357 {
 358 /* pc: program counter */
 359   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 360     { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 361 /* sr: source register */
 362   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 363     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 364 /* dr: destination register */
 365   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 366     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 367 /* src1: source register 1 */
 368   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 369     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 370 /* src2: source register 2 */
 371   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 372     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 373 /* scr: source control register */
 374   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 375     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 376 /* dcr: destination control register */
 377   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 378     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 379 /* simm8: 8 bit signed immediate */
 380   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 381     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 382 /* simm16: 16 bit signed immediate */
 383   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 384     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 385 /* uimm4: 4 bit trap number */
 386   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 387     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 388 /* uimm5: 5 bit shift count */
 389   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 390     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 391 /* uimm16: 16 bit unsigned immediate */
 392   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 393     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 394 /* start-sanitize-m32rx */
 395 /* imm1: 1 bit immediate */
 396   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 397     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 398 /* end-sanitize-m32rx */
 399 /* start-sanitize-m32rx */
 400 /* accd: accumulator destination register */
 401   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 402     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 403 /* end-sanitize-m32rx */
 404 /* start-sanitize-m32rx */
 405 /* accs: accumulator source register */
 406   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 407     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 408 /* end-sanitize-m32rx */
 409 /* start-sanitize-m32rx */
 410 /* acc: accumulator reg (d) */
 411   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 412     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 413 /* end-sanitize-m32rx */
 414 /* hash: # prefix */
 415   { "hash", & HW_ENT (HW_H_SINT), 0, 0,
 416     { 0, 0, { 0 } }  },
 417 /* hi16: high 16 bit immediate, sign optional */
 418   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 419     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 420 /* slo16: 16 bit signed immediate, for low() */
 421   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 422     { 0, 0, { 0 } }  },
 423 /* ulo16: 16 bit unsigned immediate, for low() */
 424   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 425     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 426 /* uimm24: 24 bit address */
 427   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 428     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 429 /* disp8: 8 bit displacement */
 430   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 431     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 432 /* disp16: 16 bit displacement */
 433   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 434     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 435 /* disp24: 24 bit displacement */
 436   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 437     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 438 /* condbit: condition bit */
 439   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 440     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 441 /* accum: accumulator */
 442   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 443     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 444 };
 445
 446 /* Operand references.  */
 447
 448 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 449 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 450
 451 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 452   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 453   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 454   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 455   { 0 }
 456 };
 457
 458 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
 459   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 460   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 461   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 462   { 0 }
 463 };
 464
 465 static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
 466   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 467   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 468   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 469   { 0 }
 470 };
 471
 472 static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
 473   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 474   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 475   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 476   { 0 }
 477 };
 478
 479 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 480   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 481   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 482   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 483   { 0 }
 484 };
 485
 486 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
 487   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 488   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 489   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 490   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 491   { 0 }
 492 };
 493
 494 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
 495   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 496   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 497   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 498   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 499   { 0 }
 500 };
 501
 502 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
 503   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 504   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 505   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 506   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 507   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 508   { 0 }
 509 };
 510
 511 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
 512   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 513   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 514   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 515   { 0 }
 516 };
 517
 518 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
 519   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 520   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 521   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 522   { 0 }
 523 };
 524
 525 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
 526   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 527   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 528   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 529   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 530   { 0 }
 531 };
 532
 533 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
 534   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 535   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 536   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 537   { 0 }
 538 };
 539
 540 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
 541   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 542   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 543   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 544   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 545   { 0 }
 546 };
 547
 548 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
 549   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 550   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 551   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 552   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 553   { 0 }
 554 };
 555
 556 /* start-sanitize-m32rx */
 557 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
 558   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 559   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 560   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 561   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 562   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 563   { 0 }
 564 };
 565
 566 /* end-sanitize-m32rx */
 567 /* start-sanitize-m32rx */
 568 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
 569   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 570   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 571   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 572   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 573   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 574   { 0 }
 575 };
 576
 577 /* end-sanitize-m32rx */
 578 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
 579   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 580   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 581   { 0 }
 582 };
 583
 584 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
 585   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 586   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 587   { 0 }
 588 };
 589
 590 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 591   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 592   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 593   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 594   { 0 }
 595 };
 596
 597 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 598   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 599   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 600   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 601   { 0 }
 602 };
 603
 604 /* start-sanitize-m32rx */
 605 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
 606   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 607   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 608   { 0 }
 609 };
 610
 611 /* end-sanitize-m32rx */
 612 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
 613   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 614   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 615   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 616   { 0 }
 617 };
 618
 619 /* start-sanitize-m32rx */
 620 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
 621   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 622   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 623   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 624   { 0 }
 625 };
 626
 627 /* end-sanitize-m32rx */
 628 static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
 629   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 630   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 631   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 632   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 633   { 0 }
 634 };
 635
 636 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
 637   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 638   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 639   { 0 }
 640 };
 641
 642 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
 643   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 644   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 645   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 646   { 0 }
 647 };
 648
 649 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
 650   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 651   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 652   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 653   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 654   { 0 }
 655 };
 656
 657 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
 658   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 659   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 660   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 661   { 0 }
 662 };
 663
 664 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
 665   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 666   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 667   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 668   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 669   { 0 }
 670 };
 671
 672 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
 673   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 674   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 675   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 676   { 0 }
 677 };
 678
 679 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
 680   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 681   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 682   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 683   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 684   { 0 }
 685 };
 686
 687 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
 688   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 689   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 690   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 691   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 692   { 0 }
 693 };
 694
 695 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
 696   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
 697   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 698   { 0 }
 699 };
 700
 701 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
 702   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 703   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 704   { 0 }
 705 };
 706
 707 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
 708   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 709   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 710   { 0 }
 711 };
 712
 713 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
 714   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 715   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 716   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 717   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 718   { 0 }
 719 };
 720
 721 static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
 722   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 723   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 724   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 725   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 726   { 0 }
 727 };
 728
 729 /* start-sanitize-m32rx */
 730 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
 731   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 732   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 733   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 734   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 735   { 0 }
 736 };
 737
 738 /* end-sanitize-m32rx */
 739 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
 740   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 741   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 742   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 743   { 0 }
 744 };
 745
 746 /* start-sanitize-m32rx */
 747 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
 748   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 749   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 750   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 751   { 0 }
 752 };
 753
 754 /* end-sanitize-m32rx */
 755 static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
 756   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 757   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 758   { 0 }
 759 };
 760
 761 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
 762   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 763   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 764   { 0 }
 765 };
 766
 767 /* start-sanitize-m32rx */
 768 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
 769   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 770   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 771   { 0 }
 772 };
 773
 774 /* end-sanitize-m32rx */
 775 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
 776   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 777   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 778   { 0 }
 779 };
 780
 781 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
 782   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 783   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 784   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 785   { 0 }
 786 };
 787
 788 /* start-sanitize-m32rx */
 789 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
 790   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 791   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 792   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 793   { 0 }
 794 };
 795
 796 /* end-sanitize-m32rx */
 797 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
 798   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 799   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 800   { 0 }
 801 };
 802
 803 static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
 804   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 805   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 806   { 0 }
 807 };
 808
 809 /* start-sanitize-m32rx */
 810 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
 811   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 812   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 813   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 814   { 0 }
 815 };
 816
 817 /* end-sanitize-m32rx */
 818 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
 819   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
 820   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
 821   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
 822   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
 823   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 824   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 825   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
 826   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
 827   { 0 }
 828 };
 829
 830 static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
 831   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
 832   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 833   { 0 }
 834 };
 835
 836 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
 837   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 838   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 839   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 840   { 0 }
 841 };
 842
 843 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
 844   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 845   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 846   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 847   { 0 }
 848 };
 849
 850 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
 851   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 852   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 853   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 854   { 0 }
 855 };
 856
 857 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
 858   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 859   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 860   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 861   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 862   { 0 }
 863 };
 864
 865 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
 866   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 867   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 868   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 869   { 0 }
 870 };
 871
 872 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
 873   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 874   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 875   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 876   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 877   { 0 }
 878 };
 879
 880 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
 881   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 882   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 883   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 884   { 0 }
 885 };
 886
 887 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
 888   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 889   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 890   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 891   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 892   { 0 }
 893 };
 894
 895 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
 896   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 897   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 898   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 899   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 900   { 0 }
 901 };
 902
 903 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
 904   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 905   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 906   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
 907   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 908   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 909   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 6 },
 910   { 0 }
 911 };
 912
 913 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
 914   { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 915   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 916   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 917   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 918   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 919   { 0 }
 920 };
 921
 922 /* start-sanitize-m32rx */
 923 static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
 924   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 925   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 926   { 0 }
 927 };
 928
 929 /* end-sanitize-m32rx */
 930 /* start-sanitize-m32rx */
 931 static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
 932   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 933   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 934   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 935   { 0 }
 936 };
 937
 938 /* end-sanitize-m32rx */
 939 /* start-sanitize-m32rx */
 940 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
 941   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 942   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 943   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 944   { 0 }
 945 };
 946
 947 /* end-sanitize-m32rx */
 948 /* start-sanitize-m32rx */
 949 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
 950   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 951   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 952   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 953   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 954   { 0 }
 955 };
 956
 957 /* end-sanitize-m32rx */
 958 /* start-sanitize-m32rx */
 959 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
 960   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 961   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 962   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 963   { 0 }
 964 };
 965
 966 /* end-sanitize-m32rx */
 967 /* start-sanitize-m32rx */
 968 static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
 969   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 970   { 0 }
 971 };
 972
 973 /* end-sanitize-m32rx */
 974 #undef INPUT
 975 #undef OUTPUT
 976
 977 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 978 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 979 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 980
 981 /* The instruction table.
 982    This is currently non-static because the simulator accesses it
 983    directly.  */
 984
 985 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
 986 {
 987   /* Special null first entry.
 988      A `num' value of zero is thus illegal.
 989      Also, the special `illegal' insn resides here.  */
 990   { { 0 }, 0 },
 991 /* add $dr,$sr */
 992   {
 993     { 1, 1, 1, 1 },
 994     M32R_INSN_ADD, "add", "add",
 995     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 996     { 16, 16, 0xf0f0 }, 0xa0,
 997     (PTR) & fmt_add_ops[0],
 998     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
 999   },
1000 /* add3 $dr,$sr,$hash$slo16 */
1001   {
1002     { 1, 1, 1, 1 },
1003     M32R_INSN_ADD3, "add3", "add3",
1004     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
1005     { 32, 32, 0xf0f00000 }, 0x80a00000,
1006     (PTR) & fmt_add3_ops[0],
1007     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1008   },
1009 /* and $dr,$sr */
1010   {
1011     { 1, 1, 1, 1 },
1012     M32R_INSN_AND, "and", "and",
1013     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1014     { 16, 16, 0xf0f0 }, 0xc0,
1015     (PTR) & fmt_add_ops[0],
1016     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1017   },
1018 /* and3 $dr,$sr,$uimm16 */
1019   {
1020     { 1, 1, 1, 1 },
1021     M32R_INSN_AND3, "and3", "and3",
1022     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1023     { 32, 32, 0xf0f00000 }, 0x80c00000,
1024     (PTR) & fmt_and3_ops[0],
1025     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1026   },
1027 /* or $dr,$sr */
1028   {
1029     { 1, 1, 1, 1 },
1030     M32R_INSN_OR, "or", "or",
1031     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1032     { 16, 16, 0xf0f0 }, 0xe0,
1033     (PTR) & fmt_add_ops[0],
1034     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1035   },
1036 /* or3 $dr,$sr,$hash$ulo16 */
1037   {
1038     { 1, 1, 1, 1 },
1039     M32R_INSN_OR3, "or3", "or3",
1040     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
1041     { 32, 32, 0xf0f00000 }, 0x80e00000,
1042     (PTR) & fmt_or3_ops[0],
1043     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1044   },
1045 /* xor $dr,$sr */
1046   {
1047     { 1, 1, 1, 1 },
1048     M32R_INSN_XOR, "xor", "xor",
1049     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1050     { 16, 16, 0xf0f0 }, 0xd0,
1051     (PTR) & fmt_add_ops[0],
1052     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1053   },
1054 /* xor3 $dr,$sr,$uimm16 */
1055   {
1056     { 1, 1, 1, 1 },
1057     M32R_INSN_XOR3, "xor3", "xor3",
1058     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1059     { 32, 32, 0xf0f00000 }, 0x80d00000,
1060     (PTR) & fmt_and3_ops[0],
1061     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1062   },
1063 /* addi $dr,$simm8 */
1064   {
1065     { 1, 1, 1, 1 },
1066     M32R_INSN_ADDI, "addi", "addi",
1067     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1068     { 16, 16, 0xf000 }, 0x4000,
1069     (PTR) & fmt_addi_ops[0],
1070     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1071   },
1072 /* addv $dr,$sr */
1073   {
1074     { 1, 1, 1, 1 },
1075     M32R_INSN_ADDV, "addv", "addv",
1076     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1077     { 16, 16, 0xf0f0 }, 0x80,
1078     (PTR) & fmt_addv_ops[0],
1079     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1080   },
1081 /* addv3 $dr,$sr,$simm16 */
1082   {
1083     { 1, 1, 1, 1 },
1084     M32R_INSN_ADDV3, "addv3", "addv3",
1085     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1086     { 32, 32, 0xf0f00000 }, 0x80800000,
1087     (PTR) & fmt_addv3_ops[0],
1088     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1089   },
1090 /* addx $dr,$sr */
1091   {
1092     { 1, 1, 1, 1 },
1093     M32R_INSN_ADDX, "addx", "addx",
1094     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1095     { 16, 16, 0xf0f0 }, 0x90,
1096     (PTR) & fmt_addx_ops[0],
1097     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1098   },
1099 /* bc.s $disp8 */
1100   {
1101     { 1, 1, 1, 1 },
1102     M32R_INSN_BC8, "bc8", "bc.s",
1103     { MNEM, ' ', OP (DISP8), 0 },
1104     { 16, 16, 0xff00 }, 0x7c00,
1105     (PTR) & fmt_bc8_ops[0],
1106     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1107   },
1108 /* bc.l $disp24 */
1109   {
1110     { 1, 1, 1, 1 },
1111     M32R_INSN_BC24, "bc24", "bc.l",
1112     { MNEM, ' ', OP (DISP24), 0 },
1113     { 32, 32, 0xff000000 }, 0xfc000000,
1114     (PTR) & fmt_bc24_ops[0],
1115     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1116   },
1117 /* beq $src1,$src2,$disp16 */
1118   {
1119     { 1, 1, 1, 1 },
1120     M32R_INSN_BEQ, "beq", "beq",
1121     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1122     { 32, 32, 0xf0f00000 }, 0xb0000000,
1123     (PTR) & fmt_beq_ops[0],
1124     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1125   },
1126 /* beqz $src2,$disp16 */
1127   {
1128     { 1, 1, 1, 1 },
1129     M32R_INSN_BEQZ, "beqz", "beqz",
1130     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1131     { 32, 32, 0xfff00000 }, 0xb0800000,
1132     (PTR) & fmt_beqz_ops[0],
1133     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1134   },
1135 /* bgez $src2,$disp16 */
1136   {
1137     { 1, 1, 1, 1 },
1138     M32R_INSN_BGEZ, "bgez", "bgez",
1139     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1140     { 32, 32, 0xfff00000 }, 0xb0b00000,
1141     (PTR) & fmt_beqz_ops[0],
1142     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1143   },
1144 /* bgtz $src2,$disp16 */
1145   {
1146     { 1, 1, 1, 1 },
1147     M32R_INSN_BGTZ, "bgtz", "bgtz",
1148     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1149     { 32, 32, 0xfff00000 }, 0xb0d00000,
1150     (PTR) & fmt_beqz_ops[0],
1151     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1152   },
1153 /* blez $src2,$disp16 */
1154   {
1155     { 1, 1, 1, 1 },
1156     M32R_INSN_BLEZ, "blez", "blez",
1157     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1158     { 32, 32, 0xfff00000 }, 0xb0c00000,
1159     (PTR) & fmt_beqz_ops[0],
1160     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1161   },
1162 /* bltz $src2,$disp16 */
1163   {
1164     { 1, 1, 1, 1 },
1165     M32R_INSN_BLTZ, "bltz", "bltz",
1166     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1167     { 32, 32, 0xfff00000 }, 0xb0a00000,
1168     (PTR) & fmt_beqz_ops[0],
1169     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1170   },
1171 /* bnez $src2,$disp16 */
1172   {
1173     { 1, 1, 1, 1 },
1174     M32R_INSN_BNEZ, "bnez", "bnez",
1175     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1176     { 32, 32, 0xfff00000 }, 0xb0900000,
1177     (PTR) & fmt_beqz_ops[0],
1178     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1179   },
1180 /* bl.s $disp8 */
1181   {
1182     { 1, 1, 1, 1 },
1183     M32R_INSN_BL8, "bl8", "bl.s",
1184     { MNEM, ' ', OP (DISP8), 0 },
1185     { 16, 16, 0xff00 }, 0x7e00,
1186     (PTR) & fmt_bl8_ops[0],
1187     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1188   },
1189 /* bl.l $disp24 */
1190   {
1191     { 1, 1, 1, 1 },
1192     M32R_INSN_BL24, "bl24", "bl.l",
1193     { MNEM, ' ', OP (DISP24), 0 },
1194     { 32, 32, 0xff000000 }, 0xfe000000,
1195     (PTR) & fmt_bl24_ops[0],
1196     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1197   },
1198 /* start-sanitize-m32rx */
1199 /* bcl.s $disp8 */
1200   {
1201     { 1, 1, 1, 1 },
1202     M32R_INSN_BCL8, "bcl8", "bcl.s",
1203     { MNEM, ' ', OP (DISP8), 0 },
1204     { 16, 16, 0xff00 }, 0x7800,
1205     (PTR) & fmt_bcl8_ops[0],
1206     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1207   },
1208 /* end-sanitize-m32rx */
1209 /* start-sanitize-m32rx */
1210 /* bcl.l $disp24 */
1211   {
1212     { 1, 1, 1, 1 },
1213     M32R_INSN_BCL24, "bcl24", "bcl.l",
1214     { MNEM, ' ', OP (DISP24), 0 },
1215     { 32, 32, 0xff000000 }, 0xf8000000,
1216     (PTR) & fmt_bcl24_ops[0],
1217     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1218   },
1219 /* end-sanitize-m32rx */
1220 /* bnc.s $disp8 */
1221   {
1222     { 1, 1, 1, 1 },
1223     M32R_INSN_BNC8, "bnc8", "bnc.s",
1224     { MNEM, ' ', OP (DISP8), 0 },
1225     { 16, 16, 0xff00 }, 0x7d00,
1226     (PTR) & fmt_bc8_ops[0],
1227     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1228   },
1229 /* bnc.l $disp24 */
1230   {
1231     { 1, 1, 1, 1 },
1232     M32R_INSN_BNC24, "bnc24", "bnc.l",
1233     { MNEM, ' ', OP (DISP24), 0 },
1234     { 32, 32, 0xff000000 }, 0xfd000000,
1235     (PTR) & fmt_bc24_ops[0],
1236     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1237   },
1238 /* bne $src1,$src2,$disp16 */
1239   {
1240     { 1, 1, 1, 1 },
1241     M32R_INSN_BNE, "bne", "bne",
1242     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1243     { 32, 32, 0xf0f00000 }, 0xb0100000,
1244     (PTR) & fmt_beq_ops[0],
1245     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1246   },
1247 /* bra.s $disp8 */
1248   {
1249     { 1, 1, 1, 1 },
1250     M32R_INSN_BRA8, "bra8", "bra.s",
1251     { MNEM, ' ', OP (DISP8), 0 },
1252     { 16, 16, 0xff00 }, 0x7f00,
1253     (PTR) & fmt_bra8_ops[0],
1254     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1255   },
1256 /* bra.l $disp24 */
1257   {
1258     { 1, 1, 1, 1 },
1259     M32R_INSN_BRA24, "bra24", "bra.l",
1260     { MNEM, ' ', OP (DISP24), 0 },
1261     { 32, 32, 0xff000000 }, 0xff000000,
1262     (PTR) & fmt_bra24_ops[0],
1263     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1264   },
1265 /* start-sanitize-m32rx */
1266 /* bncl.s $disp8 */
1267   {
1268     { 1, 1, 1, 1 },
1269     M32R_INSN_BNCL8, "bncl8", "bncl.s",
1270     { MNEM, ' ', OP (DISP8), 0 },
1271     { 16, 16, 0xff00 }, 0x7900,
1272     (PTR) & fmt_bcl8_ops[0],
1273     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1274   },
1275 /* end-sanitize-m32rx */
1276 /* start-sanitize-m32rx */
1277 /* bncl.l $disp24 */
1278   {
1279     { 1, 1, 1, 1 },
1280     M32R_INSN_BNCL24, "bncl24", "bncl.l",
1281     { MNEM, ' ', OP (DISP24), 0 },
1282     { 32, 32, 0xff000000 }, 0xf9000000,
1283     (PTR) & fmt_bcl24_ops[0],
1284     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1285   },
1286 /* end-sanitize-m32rx */
1287 /* cmp $src1,$src2 */
1288   {
1289     { 1, 1, 1, 1 },
1290     M32R_INSN_CMP, "cmp", "cmp",
1291     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1292     { 16, 16, 0xf0f0 }, 0x40,
1293     (PTR) & fmt_cmp_ops[0],
1294     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1295   },
1296 /* cmpi $src2,$simm16 */
1297   {
1298     { 1, 1, 1, 1 },
1299     M32R_INSN_CMPI, "cmpi", "cmpi",
1300     { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1301     { 32, 32, 0xfff00000 }, 0x80400000,
1302     (PTR) & fmt_cmpi_ops[0],
1303     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1304   },
1305 /* cmpu $src1,$src2 */
1306   {
1307     { 1, 1, 1, 1 },
1308     M32R_INSN_CMPU, "cmpu", "cmpu",
1309     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1310     { 16, 16, 0xf0f0 }, 0x50,
1311     (PTR) & fmt_cmp_ops[0],
1312     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1313   },
1314 /* cmpui $src2,$simm16 */
1315   {
1316     { 1, 1, 1, 1 },
1317     M32R_INSN_CMPUI, "cmpui", "cmpui",
1318     { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1319     { 32, 32, 0xfff00000 }, 0x80500000,
1320     (PTR) & fmt_cmpi_ops[0],
1321     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1322   },
1323 /* start-sanitize-m32rx */
1324 /* cmpeq $src1,$src2 */
1325   {
1326     { 1, 1, 1, 1 },
1327     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
1328     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1329     { 16, 16, 0xf0f0 }, 0x60,
1330     (PTR) & fmt_cmp_ops[0],
1331     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1332   },
1333 /* end-sanitize-m32rx */
1334 /* start-sanitize-m32rx */
1335 /* cmpz $src2 */
1336   {
1337     { 1, 1, 1, 1 },
1338     M32R_INSN_CMPZ, "cmpz", "cmpz",
1339     { MNEM, ' ', OP (SRC2), 0 },
1340     { 16, 16, 0xfff0 }, 0x70,
1341     (PTR) & fmt_cmpz_ops[0],
1342     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1343   },
1344 /* end-sanitize-m32rx */
1345 /* div $dr,$sr */
1346   {
1347     { 1, 1, 1, 1 },
1348     M32R_INSN_DIV, "div", "div",
1349     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1350     { 32, 32, 0xf0f0ffff }, 0x90000000,
1351     (PTR) & fmt_div_ops[0],
1352     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1353   },
1354 /* divu $dr,$sr */
1355   {
1356     { 1, 1, 1, 1 },
1357     M32R_INSN_DIVU, "divu", "divu",
1358     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1359     { 32, 32, 0xf0f0ffff }, 0x90100000,
1360     (PTR) & fmt_div_ops[0],
1361     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1362   },
1363 /* rem $dr,$sr */
1364   {
1365     { 1, 1, 1, 1 },
1366     M32R_INSN_REM, "rem", "rem",
1367     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1368     { 32, 32, 0xf0f0ffff }, 0x90200000,
1369     (PTR) & fmt_div_ops[0],
1370     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1371   },
1372 /* remu $dr,$sr */
1373   {
1374     { 1, 1, 1, 1 },
1375     M32R_INSN_REMU, "remu", "remu",
1376     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1377     { 32, 32, 0xf0f0ffff }, 0x90300000,
1378     (PTR) & fmt_div_ops[0],
1379     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1380   },
1381 /* start-sanitize-m32rx */
1382 /* divh $dr,$sr */
1383   {
1384     { 1, 1, 1, 1 },
1385     M32R_INSN_DIVH, "divh", "divh",
1386     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1387     { 32, 32, 0xf0f0ffff }, 0x90000010,
1388     (PTR) & fmt_div_ops[0],
1389     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1390   },
1391 /* end-sanitize-m32rx */
1392 /* start-sanitize-m32rx */
1393 /* jc $sr */
1394   {
1395     { 1, 1, 1, 1 },
1396     M32R_INSN_JC, "jc", "jc",
1397     { MNEM, ' ', OP (SR), 0 },
1398     { 16, 16, 0xfff0 }, 0x1cc0,
1399     (PTR) & fmt_jc_ops[0],
1400     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1401   },
1402 /* end-sanitize-m32rx */
1403 /* start-sanitize-m32rx */
1404 /* jnc $sr */
1405   {
1406     { 1, 1, 1, 1 },
1407     M32R_INSN_JNC, "jnc", "jnc",
1408     { MNEM, ' ', OP (SR), 0 },
1409     { 16, 16, 0xfff0 }, 0x1dc0,
1410     (PTR) & fmt_jc_ops[0],
1411     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1412   },
1413 /* end-sanitize-m32rx */
1414 /* jl $sr */
1415   {
1416     { 1, 1, 1, 1 },
1417     M32R_INSN_JL, "jl", "jl",
1418     { MNEM, ' ', OP (SR), 0 },
1419     { 16, 16, 0xfff0 }, 0x1ec0,
1420     (PTR) & fmt_jl_ops[0],
1421     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1422   },
1423 /* jmp $sr */
1424   {
1425     { 1, 1, 1, 1 },
1426     M32R_INSN_JMP, "jmp", "jmp",
1427     { MNEM, ' ', OP (SR), 0 },
1428     { 16, 16, 0xfff0 }, 0x1fc0,
1429     (PTR) & fmt_jmp_ops[0],
1430     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1431   },
1432 /* ld $dr,@$sr */
1433   {
1434     { 1, 1, 1, 1 },
1435     M32R_INSN_LD, "ld", "ld",
1436     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1437     { 16, 16, 0xf0f0 }, 0x20c0,
1438     (PTR) & fmt_ld_ops[0],
1439     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1440   },
1441 /* ld $dr,@($slo16,$sr) */
1442   {
1443     { 1, 1, 1, 1 },
1444     M32R_INSN_LD_D, "ld-d", "ld",
1445     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1446     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1447     (PTR) & fmt_ld_d_ops[0],
1448     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1449   },
1450 /* ldb $dr,@$sr */
1451   {
1452     { 1, 1, 1, 1 },
1453     M32R_INSN_LDB, "ldb", "ldb",
1454     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1455     { 16, 16, 0xf0f0 }, 0x2080,
1456     (PTR) & fmt_ldb_ops[0],
1457     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1458   },
1459 /* ldb $dr,@($slo16,$sr) */
1460   {
1461     { 1, 1, 1, 1 },
1462     M32R_INSN_LDB_D, "ldb-d", "ldb",
1463     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1464     { 32, 32, 0xf0f00000 }, 0xa0800000,
1465     (PTR) & fmt_ldb_d_ops[0],
1466     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1467   },
1468 /* ldh $dr,@$sr */
1469   {
1470     { 1, 1, 1, 1 },
1471     M32R_INSN_LDH, "ldh", "ldh",
1472     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1473     { 16, 16, 0xf0f0 }, 0x20a0,
1474     (PTR) & fmt_ldh_ops[0],
1475     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1476   },
1477 /* ldh $dr,@($slo16,$sr) */
1478   {
1479     { 1, 1, 1, 1 },
1480     M32R_INSN_LDH_D, "ldh-d", "ldh",
1481     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1482     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1483     (PTR) & fmt_ldh_d_ops[0],
1484     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1485   },
1486 /* ldub $dr,@$sr */
1487   {
1488     { 1, 1, 1, 1 },
1489     M32R_INSN_LDUB, "ldub", "ldub",
1490     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1491     { 16, 16, 0xf0f0 }, 0x2090,
1492     (PTR) & fmt_ldb_ops[0],
1493     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1494   },
1495 /* ldub $dr,@($slo16,$sr) */
1496   {
1497     { 1, 1, 1, 1 },
1498     M32R_INSN_LDUB_D, "ldub-d", "ldub",
1499     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1500     { 32, 32, 0xf0f00000 }, 0xa0900000,
1501     (PTR) & fmt_ldb_d_ops[0],
1502     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1503   },
1504 /* lduh $dr,@$sr */
1505   {
1506     { 1, 1, 1, 1 },
1507     M32R_INSN_LDUH, "lduh", "lduh",
1508     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1509     { 16, 16, 0xf0f0 }, 0x20b0,
1510     (PTR) & fmt_ldh_ops[0],
1511     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1512   },
1513 /* lduh $dr,@($slo16,$sr) */
1514   {
1515     { 1, 1, 1, 1 },
1516     M32R_INSN_LDUH_D, "lduh-d", "lduh",
1517     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1518     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1519     (PTR) & fmt_ldh_d_ops[0],
1520     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1521   },
1522 /* ld $dr,@$sr+ */
1523   {
1524     { 1, 1, 1, 1 },
1525     M32R_INSN_LD_PLUS, "ld-plus", "ld",
1526     { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1527     { 16, 16, 0xf0f0 }, 0x20e0,
1528     (PTR) & fmt_ld_plus_ops[0],
1529     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1530   },
1531 /* ld24 $dr,$uimm24 */
1532   {
1533     { 1, 1, 1, 1 },
1534     M32R_INSN_LD24, "ld24", "ld24",
1535     { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1536     { 32, 32, 0xf0000000 }, 0xe0000000,
1537     (PTR) & fmt_ld24_ops[0],
1538     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1539   },
1540 /* ldi8 $dr,$simm8 */
1541   {
1542     { 1, 1, 1, 1 },
1543     M32R_INSN_LDI8, "ldi8", "ldi8",
1544     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1545     { 16, 16, 0xf000 }, 0x6000,
1546     (PTR) & fmt_ldi8_ops[0],
1547     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1548   },
1549 /* ldi16 $dr,$hash$slo16 */
1550   {
1551     { 1, 1, 1, 1 },
1552     M32R_INSN_LDI16, "ldi16", "ldi16",
1553     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1554     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1555     (PTR) & fmt_ldi16_ops[0],
1556     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1557   },
1558 /* lock $dr,@$sr */
1559   {
1560     { 1, 1, 1, 1 },
1561     M32R_INSN_LOCK, "lock", "lock",
1562     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1563     { 16, 16, 0xf0f0 }, 0x20d0,
1564     (PTR) & fmt_lock_ops[0],
1565     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1566   },
1567 /* machi $src1,$src2 */
1568   {
1569     { 1, 1, 1, 1 },
1570     M32R_INSN_MACHI, "machi", "machi",
1571     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1572     { 16, 16, 0xf0f0 }, 0x3040,
1573     (PTR) & fmt_machi_ops[0],
1574     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1575   },
1576 /* start-sanitize-m32rx */
1577 /* machi $src1,$src2,$acc */
1578   {
1579     { 1, 1, 1, 1 },
1580     M32R_INSN_MACHI_A, "machi-a", "machi",
1581     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1582     { 16, 16, 0xf070 }, 0x3040,
1583     (PTR) & fmt_machi_a_ops[0],
1584     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1585   },
1586 /* end-sanitize-m32rx */
1587 /* maclo $src1,$src2 */
1588   {
1589     { 1, 1, 1, 1 },
1590     M32R_INSN_MACLO, "maclo", "maclo",
1591     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1592     { 16, 16, 0xf0f0 }, 0x3050,
1593     (PTR) & fmt_machi_ops[0],
1594     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1595   },
1596 /* start-sanitize-m32rx */
1597 /* maclo $src1,$src2,$acc */
1598   {
1599     { 1, 1, 1, 1 },
1600     M32R_INSN_MACLO_A, "maclo-a", "maclo",
1601     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1602     { 16, 16, 0xf070 }, 0x3050,
1603     (PTR) & fmt_machi_a_ops[0],
1604     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1605   },
1606 /* end-sanitize-m32rx */
1607 /* macwhi $src1,$src2 */
1608   {
1609     { 1, 1, 1, 1 },
1610     M32R_INSN_MACWHI, "macwhi", "macwhi",
1611     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1612     { 16, 16, 0xf0f0 }, 0x3060,
1613     (PTR) & fmt_machi_ops[0],
1614     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1615   },
1616 /* macwlo $src1,$src2 */
1617   {
1618     { 1, 1, 1, 1 },
1619     M32R_INSN_MACWLO, "macwlo", "macwlo",
1620     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1621     { 16, 16, 0xf0f0 }, 0x3070,
1622     (PTR) & fmt_machi_ops[0],
1623     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1624   },
1625 /* mul $dr,$sr */
1626   {
1627     { 1, 1, 1, 1 },
1628     M32R_INSN_MUL, "mul", "mul",
1629     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1630     { 16, 16, 0xf0f0 }, 0x1060,
1631     (PTR) & fmt_add_ops[0],
1632     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1633   },
1634 /* mulhi $src1,$src2 */
1635   {
1636     { 1, 1, 1, 1 },
1637     M32R_INSN_MULHI, "mulhi", "mulhi",
1638     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1639     { 16, 16, 0xf0f0 }, 0x3000,
1640     (PTR) & fmt_mulhi_ops[0],
1641     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1642   },
1643 /* start-sanitize-m32rx */
1644 /* mulhi $src1,$src2,$acc */
1645   {
1646     { 1, 1, 1, 1 },
1647     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
1648     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1649     { 16, 16, 0xf070 }, 0x3000,
1650     (PTR) & fmt_mulhi_a_ops[0],
1651     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1652   },
1653 /* end-sanitize-m32rx */
1654 /* mullo $src1,$src2 */
1655   {
1656     { 1, 1, 1, 1 },
1657     M32R_INSN_MULLO, "mullo", "mullo",
1658     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1659     { 16, 16, 0xf0f0 }, 0x3010,
1660     (PTR) & fmt_mulhi_ops[0],
1661     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1662   },
1663 /* start-sanitize-m32rx */
1664 /* mullo $src1,$src2,$acc */
1665   {
1666     { 1, 1, 1, 1 },
1667     M32R_INSN_MULLO_A, "mullo-a", "mullo",
1668     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1669     { 16, 16, 0xf070 }, 0x3010,
1670     (PTR) & fmt_mulhi_a_ops[0],
1671     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1672   },
1673 /* end-sanitize-m32rx */
1674 /* mulwhi $src1,$src2 */
1675   {
1676     { 1, 1, 1, 1 },
1677     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
1678     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1679     { 16, 16, 0xf0f0 }, 0x3020,
1680     (PTR) & fmt_mulhi_ops[0],
1681     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1682   },
1683 /* mulwlo $src1,$src2 */
1684   {
1685     { 1, 1, 1, 1 },
1686     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
1687     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1688     { 16, 16, 0xf0f0 }, 0x3030,
1689     (PTR) & fmt_mulhi_ops[0],
1690     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1691   },
1692 /* mv $dr,$sr */
1693   {
1694     { 1, 1, 1, 1 },
1695     M32R_INSN_MV, "mv", "mv",
1696     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1697     { 16, 16, 0xf0f0 }, 0x1080,
1698     (PTR) & fmt_mv_ops[0],
1699     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1700   },
1701 /* mvfachi $dr */
1702   {
1703     { 1, 1, 1, 1 },
1704     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
1705     { MNEM, ' ', OP (DR), 0 },
1706     { 16, 16, 0xf0ff }, 0x50f0,
1707     (PTR) & fmt_mvfachi_ops[0],
1708     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1709   },
1710 /* start-sanitize-m32rx */
1711 /* mvfachi $dr,$accs */
1712   {
1713     { 1, 1, 1, 1 },
1714     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
1715     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1716     { 16, 16, 0xf0f3 }, 0x50f0,
1717     (PTR) & fmt_mvfachi_a_ops[0],
1718     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1719   },
1720 /* end-sanitize-m32rx */
1721 /* mvfaclo $dr */
1722   {
1723     { 1, 1, 1, 1 },
1724     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
1725     { MNEM, ' ', OP (DR), 0 },
1726     { 16, 16, 0xf0ff }, 0x50f1,
1727     (PTR) & fmt_mvfachi_ops[0],
1728     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1729   },
1730 /* start-sanitize-m32rx */
1731 /* mvfaclo $dr,$accs */
1732   {
1733     { 1, 1, 1, 1 },
1734     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
1735     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1736     { 16, 16, 0xf0f3 }, 0x50f1,
1737     (PTR) & fmt_mvfachi_a_ops[0],
1738     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1739   },
1740 /* end-sanitize-m32rx */
1741 /* mvfacmi $dr */
1742   {
1743     { 1, 1, 1, 1 },
1744     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
1745     { MNEM, ' ', OP (DR), 0 },
1746     { 16, 16, 0xf0ff }, 0x50f2,
1747     (PTR) & fmt_mvfachi_ops[0],
1748     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1749   },
1750 /* start-sanitize-m32rx */
1751 /* mvfacmi $dr,$accs */
1752   {
1753     { 1, 1, 1, 1 },
1754     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
1755     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1756     { 16, 16, 0xf0f3 }, 0x50f2,
1757     (PTR) & fmt_mvfachi_a_ops[0],
1758     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1759   },
1760 /* end-sanitize-m32rx */
1761 /* mvfc $dr,$scr */
1762   {
1763     { 1, 1, 1, 1 },
1764     M32R_INSN_MVFC, "mvfc", "mvfc",
1765     { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
1766     { 16, 16, 0xf0f0 }, 0x1090,
1767     (PTR) & fmt_mvfc_ops[0],
1768     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1769   },
1770 /* mvtachi $src1 */
1771   {
1772     { 1, 1, 1, 1 },
1773     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
1774     { MNEM, ' ', OP (SRC1), 0 },
1775     { 16, 16, 0xf0ff }, 0x5070,
1776     (PTR) & fmt_mvtachi_ops[0],
1777     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1778   },
1779 /* start-sanitize-m32rx */
1780 /* mvtachi $src1,$accs */
1781   {
1782     { 1, 1, 1, 1 },
1783     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
1784     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1785     { 16, 16, 0xf0f3 }, 0x5070,
1786     (PTR) & fmt_mvtachi_a_ops[0],
1787     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1788   },
1789 /* end-sanitize-m32rx */
1790 /* mvtaclo $src1 */
1791   {
1792     { 1, 1, 1, 1 },
1793     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
1794     { MNEM, ' ', OP (SRC1), 0 },
1795     { 16, 16, 0xf0ff }, 0x5071,
1796     (PTR) & fmt_mvtachi_ops[0],
1797     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1798   },
1799 /* start-sanitize-m32rx */
1800 /* mvtaclo $src1,$accs */
1801   {
1802     { 1, 1, 1, 1 },
1803     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
1804     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1805     { 16, 16, 0xf0f3 }, 0x5071,
1806     (PTR) & fmt_mvtachi_a_ops[0],
1807     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1808   },
1809 /* end-sanitize-m32rx */
1810 /* mvtc $sr,$dcr */
1811   {
1812     { 1, 1, 1, 1 },
1813     M32R_INSN_MVTC, "mvtc", "mvtc",
1814     { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
1815     { 16, 16, 0xf0f0 }, 0x10a0,
1816     (PTR) & fmt_mvtc_ops[0],
1817     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1818   },
1819 /* neg $dr,$sr */
1820   {
1821     { 1, 1, 1, 1 },
1822     M32R_INSN_NEG, "neg", "neg",
1823     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1824     { 16, 16, 0xf0f0 }, 0x30,
1825     (PTR) & fmt_mv_ops[0],
1826     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1827   },
1828 /* nop */
1829   {
1830     { 1, 1, 1, 1 },
1831     M32R_INSN_NOP, "nop", "nop",
1832     { MNEM, 0 },
1833     { 16, 16, 0xffff }, 0x7000,
1834     (PTR) 0,
1835     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1836   },
1837 /* not $dr,$sr */
1838   {
1839     { 1, 1, 1, 1 },
1840     M32R_INSN_NOT, "not", "not",
1841     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1842     { 16, 16, 0xf0f0 }, 0xb0,
1843     (PTR) & fmt_mv_ops[0],
1844     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1845   },
1846 /* rac */
1847   {
1848     { 1, 1, 1, 1 },
1849     M32R_INSN_RAC, "rac", "rac",
1850     { MNEM, 0 },
1851     { 16, 16, 0xffff }, 0x5090,
1852     (PTR) & fmt_rac_ops[0],
1853     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1854   },
1855 /* start-sanitize-m32rx */
1856 /* rac $accd,$accs,$imm1 */
1857   {
1858     { 1, 1, 1, 1 },
1859     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
1860     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
1861     { 16, 16, 0xf3f2 }, 0x5090,
1862     (PTR) & fmt_rac_dsi_ops[0],
1863     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1864   },
1865 /* end-sanitize-m32rx */
1866 /* rach */
1867   {
1868     { 1, 1, 1, 1 },
1869     M32R_INSN_RACH, "rach", "rach",
1870     { MNEM, 0 },
1871     { 16, 16, 0xffff }, 0x5080,
1872     (PTR) & fmt_rac_ops[0],
1873     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1874   },
1875 /* start-sanitize-m32rx */
1876 /* rach $accd,$accs,$imm1 */
1877   {
1878     { 1, 1, 1, 1 },
1879     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
1880     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
1881     { 16, 16, 0xf3f2 }, 0x5080,
1882     (PTR) & fmt_rac_dsi_ops[0],
1883     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1884   },
1885 /* end-sanitize-m32rx */
1886 /* rte */
1887   {
1888     { 1, 1, 1, 1 },
1889     M32R_INSN_RTE, "rte", "rte",
1890     { MNEM, 0 },
1891     { 16, 16, 0xffff }, 0x10d6,
1892     (PTR) & fmt_rte_ops[0],
1893     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1894   },
1895 /* seth $dr,$hash$hi16 */
1896   {
1897     { 1, 1, 1, 1 },
1898     M32R_INSN_SETH, "seth", "seth",
1899     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
1900     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
1901     (PTR) & fmt_seth_ops[0],
1902     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1903   },
1904 /* sll $dr,$sr */
1905   {
1906     { 1, 1, 1, 1 },
1907     M32R_INSN_SLL, "sll", "sll",
1908     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1909     { 16, 16, 0xf0f0 }, 0x1040,
1910     (PTR) & fmt_add_ops[0],
1911     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1912   },
1913 /* sll3 $dr,$sr,$simm16 */
1914   {
1915     { 1, 1, 1, 1 },
1916     M32R_INSN_SLL3, "sll3", "sll3",
1917     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1918     { 32, 32, 0xf0f00000 }, 0x90c00000,
1919     (PTR) & fmt_sll3_ops[0],
1920     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1921   },
1922 /* slli $dr,$uimm5 */
1923   {
1924     { 1, 1, 1, 1 },
1925     M32R_INSN_SLLI, "slli", "slli",
1926     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1927     { 16, 16, 0xf0e0 }, 0x5040,
1928     (PTR) & fmt_slli_ops[0],
1929     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1930   },
1931 /* sra $dr,$sr */
1932   {
1933     { 1, 1, 1, 1 },
1934     M32R_INSN_SRA, "sra", "sra",
1935     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1936     { 16, 16, 0xf0f0 }, 0x1020,
1937     (PTR) & fmt_add_ops[0],
1938     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1939   },
1940 /* sra3 $dr,$sr,$simm16 */
1941   {
1942     { 1, 1, 1, 1 },
1943     M32R_INSN_SRA3, "sra3", "sra3",
1944     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1945     { 32, 32, 0xf0f00000 }, 0x90a00000,
1946     (PTR) & fmt_sll3_ops[0],
1947     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1948   },
1949 /* srai $dr,$uimm5 */
1950   {
1951     { 1, 1, 1, 1 },
1952     M32R_INSN_SRAI, "srai", "srai",
1953     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1954     { 16, 16, 0xf0e0 }, 0x5020,
1955     (PTR) & fmt_slli_ops[0],
1956     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1957   },
1958 /* srl $dr,$sr */
1959   {
1960     { 1, 1, 1, 1 },
1961     M32R_INSN_SRL, "srl", "srl",
1962     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1963     { 16, 16, 0xf0f0 }, 0x1000,
1964     (PTR) & fmt_add_ops[0],
1965     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1966   },
1967 /* srl3 $dr,$sr,$simm16 */
1968   {
1969     { 1, 1, 1, 1 },
1970     M32R_INSN_SRL3, "srl3", "srl3",
1971     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1972     { 32, 32, 0xf0f00000 }, 0x90800000,
1973     (PTR) & fmt_sll3_ops[0],
1974     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1975   },
1976 /* srli $dr,$uimm5 */
1977   {
1978     { 1, 1, 1, 1 },
1979     M32R_INSN_SRLI, "srli", "srli",
1980     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1981     { 16, 16, 0xf0e0 }, 0x5000,
1982     (PTR) & fmt_slli_ops[0],
1983     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1984   },
1985 /* st $src1,@$src2 */
1986   {
1987     { 1, 1, 1, 1 },
1988     M32R_INSN_ST, "st", "st",
1989     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
1990     { 16, 16, 0xf0f0 }, 0x2040,
1991     (PTR) & fmt_st_ops[0],
1992     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1993   },
1994 /* st $src1,@($slo16,$src2) */
1995   {
1996     { 1, 1, 1, 1 },
1997     M32R_INSN_ST_D, "st-d", "st",
1998     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
1999     { 32, 32, 0xf0f00000 }, 0xa0400000,
2000     (PTR) & fmt_st_d_ops[0],
2001     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2002   },
2003 /* stb $src1,@$src2 */
2004   {
2005     { 1, 1, 1, 1 },
2006     M32R_INSN_STB, "stb", "stb",
2007     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2008     { 16, 16, 0xf0f0 }, 0x2000,
2009     (PTR) & fmt_stb_ops[0],
2010     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2011   },
2012 /* stb $src1,@($slo16,$src2) */
2013   {
2014     { 1, 1, 1, 1 },
2015     M32R_INSN_STB_D, "stb-d", "stb",
2016     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2017     { 32, 32, 0xf0f00000 }, 0xa0000000,
2018     (PTR) & fmt_stb_d_ops[0],
2019     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2020   },
2021 /* sth $src1,@$src2 */
2022   {
2023     { 1, 1, 1, 1 },
2024     M32R_INSN_STH, "sth", "sth",
2025     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2026     { 16, 16, 0xf0f0 }, 0x2020,
2027     (PTR) & fmt_sth_ops[0],
2028     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2029   },
2030 /* sth $src1,@($slo16,$src2) */
2031   {
2032     { 1, 1, 1, 1 },
2033     M32R_INSN_STH_D, "sth-d", "sth",
2034     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2035     { 32, 32, 0xf0f00000 }, 0xa0200000,
2036     (PTR) & fmt_sth_d_ops[0],
2037     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2038   },
2039 /* st $src1,@+$src2 */
2040   {
2041     { 1, 1, 1, 1 },
2042     M32R_INSN_ST_PLUS, "st-plus", "st",
2043     { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2044     { 16, 16, 0xf0f0 }, 0x2060,
2045     (PTR) & fmt_st_plus_ops[0],
2046     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2047   },
2048 /* st $src1,@-$src2 */
2049   {
2050     { 1, 1, 1, 1 },
2051     M32R_INSN_ST_MINUS, "st-minus", "st",
2052     { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2053     { 16, 16, 0xf0f0 }, 0x2070,
2054     (PTR) & fmt_st_plus_ops[0],
2055     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2056   },
2057 /* sub $dr,$sr */
2058   {
2059     { 1, 1, 1, 1 },
2060     M32R_INSN_SUB, "sub", "sub",
2061     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2062     { 16, 16, 0xf0f0 }, 0x20,
2063     (PTR) & fmt_add_ops[0],
2064     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2065   },
2066 /* subv $dr,$sr */
2067   {
2068     { 1, 1, 1, 1 },
2069     M32R_INSN_SUBV, "subv", "subv",
2070     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2071     { 16, 16, 0xf0f0 }, 0x0,
2072     (PTR) & fmt_addv_ops[0],
2073     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2074   },
2075 /* subx $dr,$sr */
2076   {
2077     { 1, 1, 1, 1 },
2078     M32R_INSN_SUBX, "subx", "subx",
2079     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2080     { 16, 16, 0xf0f0 }, 0x10,
2081     (PTR) & fmt_addx_ops[0],
2082     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2083   },
2084 /* trap $uimm4 */
2085   {
2086     { 1, 1, 1, 1 },
2087     M32R_INSN_TRAP, "trap", "trap",
2088     { MNEM, ' ', OP (UIMM4), 0 },
2089     { 16, 16, 0xfff0 }, 0x10f0,
2090     (PTR) & fmt_trap_ops[0],
2091     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2092   },
2093 /* unlock $src1,@$src2 */
2094   {
2095     { 1, 1, 1, 1 },
2096     M32R_INSN_UNLOCK, "unlock", "unlock",
2097     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2098     { 16, 16, 0xf0f0 }, 0x2050,
2099     (PTR) & fmt_unlock_ops[0],
2100     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2101   },
2102 /* start-sanitize-m32rx */
2103 /* satb $dr,$sr */
2104   {
2105     { 1, 1, 1, 1 },
2106     M32R_INSN_SATB, "satb", "satb",
2107     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2108     { 32, 32, 0xf0f0ffff }, 0x80600300,
2109     (PTR) & fmt_satb_ops[0],
2110     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2111   },
2112 /* end-sanitize-m32rx */
2113 /* start-sanitize-m32rx */
2114 /* sath $dr,$sr */
2115   {
2116     { 1, 1, 1, 1 },
2117     M32R_INSN_SATH, "sath", "sath",
2118     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2119     { 32, 32, 0xf0f0ffff }, 0x80600200,
2120     (PTR) & fmt_satb_ops[0],
2121     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2122   },
2123 /* end-sanitize-m32rx */
2124 /* start-sanitize-m32rx */
2125 /* sat $dr,$sr */
2126   {
2127     { 1, 1, 1, 1 },
2128     M32R_INSN_SAT, "sat", "sat",
2129     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2130     { 32, 32, 0xf0f0ffff }, 0x80600000,
2131     (PTR) & fmt_sat_ops[0],
2132     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2133   },
2134 /* end-sanitize-m32rx */
2135 /* start-sanitize-m32rx */
2136 /* pcmpbz $src2 */
2137   {
2138     { 1, 1, 1, 1 },
2139     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2140     { MNEM, ' ', OP (SRC2), 0 },
2141     { 16, 16, 0xfff0 }, 0x370,
2142     (PTR) & fmt_cmpz_ops[0],
2143     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2144   },
2145 /* end-sanitize-m32rx */
2146 /* start-sanitize-m32rx */
2147 /* sadd */
2148   {
2149     { 1, 1, 1, 1 },
2150     M32R_INSN_SADD, "sadd", "sadd",
2151     { MNEM, 0 },
2152     { 16, 16, 0xffff }, 0x50e4,
2153     (PTR) & fmt_sadd_ops[0],
2154     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2155   },
2156 /* end-sanitize-m32rx */
2157 /* start-sanitize-m32rx */
2158 /* macwu1 $src1,$src2 */
2159   {
2160     { 1, 1, 1, 1 },
2161     M32R_INSN_MACWU1, "macwu1", "macwu1",
2162     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2163     { 16, 16, 0xf0f0 }, 0x50b0,
2164     (PTR) & fmt_macwu1_ops[0],
2165     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2166   },
2167 /* end-sanitize-m32rx */
2168 /* start-sanitize-m32rx */
2169 /* msblo $src1,$src2 */
2170   {
2171     { 1, 1, 1, 1 },
2172     M32R_INSN_MSBLO, "msblo", "msblo",
2173     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2174     { 16, 16, 0xf0f0 }, 0x50d0,
2175     (PTR) & fmt_machi_ops[0],
2176     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2177   },
2178 /* end-sanitize-m32rx */
2179 /* start-sanitize-m32rx */
2180 /* mulwu1 $src1,$src2 */
2181   {
2182     { 1, 1, 1, 1 },
2183     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2184     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2185     { 16, 16, 0xf0f0 }, 0x50a0,
2186     (PTR) & fmt_mulwu1_ops[0],
2187     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2188   },
2189 /* end-sanitize-m32rx */
2190 /* start-sanitize-m32rx */
2191 /* maclh1 $src1,$src2 */
2192   {
2193     { 1, 1, 1, 1 },
2194     M32R_INSN_MACLH1, "maclh1", "maclh1",
2195     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2196     { 16, 16, 0xf0f0 }, 0x50c0,
2197     (PTR) & fmt_macwu1_ops[0],
2198     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2199   },
2200 /* end-sanitize-m32rx */
2201 /* start-sanitize-m32rx */
2202 /* sc */
2203   {
2204     { 1, 1, 1, 1 },
2205     M32R_INSN_SC, "sc", "sc",
2206     { MNEM, 0 },
2207     { 16, 16, 0xffff }, 0x7401,
2208     (PTR) & fmt_sc_ops[0],
2209     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2210   },
2211 /* end-sanitize-m32rx */
2212 /* start-sanitize-m32rx */
2213 /* snc */
2214   {
2215     { 1, 1, 1, 1 },
2216     M32R_INSN_SNC, "snc", "snc",
2217     { MNEM, 0 },
2218     { 16, 16, 0xffff }, 0x7501,
2219     (PTR) & fmt_sc_ops[0],
2220     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2221   },
2222 /* end-sanitize-m32rx */
2223 };
2224
2225 #undef A
2226 #undef MNEM
2227 #undef OP
2228
2229 static CGEN_INSN_TABLE insn_table =
2230 {
2231   & m32r_cgen_insn_table_entries[0],
2232   sizeof (CGEN_INSN),
2233   MAX_INSNS,
2234   NULL
2235 };
2236
2237 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2238
2239 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2240 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2241 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2242
2243 /* The macro instruction table.  */
2244
2245 static const CGEN_INSN macro_insn_table_entries[] =
2246 {
2247 /* bc $disp8 */
2248   {
2249     { 1, 1, 1, 1 },
2250     -1, "bc8r", "bc",
2251     { MNEM, ' ', OP (DISP8), 0 },
2252     { 16, 16, 0xff00 }, 0x7c00,
2253     (PTR) 0,
2254     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2255   },
2256 /* bc $disp24 */
2257   {
2258     { 1, 1, 1, 1 },
2259     -1, "bc24r", "bc",
2260     { MNEM, ' ', OP (DISP24), 0 },
2261     { 32, 32, 0xff000000 }, 0xfc000000,
2262     (PTR) 0,
2263     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2264   },
2265 /* bl $disp8 */
2266   {
2267     { 1, 1, 1, 1 },
2268     -1, "bl8r", "bl",
2269     { MNEM, ' ', OP (DISP8), 0 },
2270     { 16, 16, 0xff00 }, 0x7e00,
2271     (PTR) 0,
2272     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2273   },
2274 /* bl $disp24 */
2275   {
2276     { 1, 1, 1, 1 },
2277     -1, "bl24r", "bl",
2278     { MNEM, ' ', OP (DISP24), 0 },
2279     { 32, 32, 0xff000000 }, 0xfe000000,
2280     (PTR) 0,
2281     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2282   },
2283 /* bcl $disp8 */
2284   {
2285     { 1, 1, 1, 1 },
2286     -1, "bcl8r", "bcl",
2287     { MNEM, ' ', OP (DISP8), 0 },
2288     { 16, 16, 0xff00 }, 0x7800,
2289     (PTR) 0,
2290     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2291   },
2292 /* bcl $disp24 */
2293   {
2294     { 1, 1, 1, 1 },
2295     -1, "bcl24r", "bcl",
2296     { MNEM, ' ', OP (DISP24), 0 },
2297     { 32, 32, 0xff000000 }, 0xf8000000,
2298     (PTR) 0,
2299     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2300   },
2301 /* bnc $disp8 */
2302   {
2303     { 1, 1, 1, 1 },
2304     -1, "bnc8r", "bnc",
2305     { MNEM, ' ', OP (DISP8), 0 },
2306     { 16, 16, 0xff00 }, 0x7d00,
2307     (PTR) 0,
2308     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2309   },
2310 /* bnc $disp24 */
2311   {
2312     { 1, 1, 1, 1 },
2313     -1, "bnc24r", "bnc",
2314     { MNEM, ' ', OP (DISP24), 0 },
2315     { 32, 32, 0xff000000 }, 0xfd000000,
2316     (PTR) 0,
2317     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2318   },
2319 /* bra $disp8 */
2320   {
2321     { 1, 1, 1, 1 },
2322     -1, "bra8r", "bra",
2323     { MNEM, ' ', OP (DISP8), 0 },
2324     { 16, 16, 0xff00 }, 0x7f00,
2325     (PTR) 0,
2326     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2327   },
2328 /* bra $disp24 */
2329   {
2330     { 1, 1, 1, 1 },
2331     -1, "bra24r", "bra",
2332     { MNEM, ' ', OP (DISP24), 0 },
2333     { 32, 32, 0xff000000 }, 0xff000000,
2334     (PTR) 0,
2335     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2336   },
2337 /* bncl $disp8 */
2338   {
2339     { 1, 1, 1, 1 },
2340     -1, "bncl8r", "bncl",
2341     { MNEM, ' ', OP (DISP8), 0 },
2342     { 16, 16, 0xff00 }, 0x7900,
2343     (PTR) 0,
2344     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2345   },
2346 /* bncl $disp24 */
2347   {
2348     { 1, 1, 1, 1 },
2349     -1, "bncl24r", "bncl",
2350     { MNEM, ' ', OP (DISP24), 0 },
2351     { 32, 32, 0xff000000 }, 0xf9000000,
2352     (PTR) 0,
2353     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2354   },
2355 /* ld $dr,@($sr) */
2356   {
2357     { 1, 1, 1, 1 },
2358     -1, "ld-2", "ld",
2359     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2360     { 16, 16, 0xf0f0 }, 0x20c0,
2361     (PTR) 0,
2362     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2363   },
2364 /* ld $dr,@($sr,$slo16) */
2365   {
2366     { 1, 1, 1, 1 },
2367     -1, "ld-d2", "ld",
2368     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2369     { 32, 32, 0xf0f00000 }, 0xa0c00000,
2370     (PTR) 0,
2371     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2372   },
2373 /* ldb $dr,@($sr) */
2374   {
2375     { 1, 1, 1, 1 },
2376     -1, "ldb-2", "ldb",
2377     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2378     { 16, 16, 0xf0f0 }, 0x2080,
2379     (PTR) 0,
2380     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2381   },
2382 /* ldb $dr,@($sr,$slo16) */
2383   {
2384     { 1, 1, 1, 1 },
2385     -1, "ldb-d2", "ldb",
2386     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2387     { 32, 32, 0xf0f00000 }, 0xa0800000,
2388     (PTR) 0,
2389     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2390   },
2391 /* ldh $dr,@($sr) */
2392   {
2393     { 1, 1, 1, 1 },
2394     -1, "ldh-2", "ldh",
2395     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2396     { 16, 16, 0xf0f0 }, 0x20a0,
2397     (PTR) 0,
2398     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2399   },
2400 /* ldh $dr,@($sr,$slo16) */
2401   {
2402     { 1, 1, 1, 1 },
2403     -1, "ldh-d2", "ldh",
2404     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2405     { 32, 32, 0xf0f00000 }, 0xa0a00000,
2406     (PTR) 0,
2407     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2408   },
2409 /* ldub $dr,@($sr) */
2410   {
2411     { 1, 1, 1, 1 },
2412     -1, "ldub-2", "ldub",
2413     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2414     { 16, 16, 0xf0f0 }, 0x2090,
2415     (PTR) 0,
2416     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2417   },
2418 /* ldub $dr,@($sr,$slo16) */
2419   {
2420     { 1, 1, 1, 1 },
2421     -1, "ldub-d2", "ldub",
2422     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2423     { 32, 32, 0xf0f00000 }, 0xa0900000,
2424     (PTR) 0,
2425     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2426   },
2427 /* lduh $dr,@($sr) */
2428   {
2429     { 1, 1, 1, 1 },
2430     -1, "lduh-2", "lduh",
2431     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2432     { 16, 16, 0xf0f0 }, 0x20b0,
2433     (PTR) 0,
2434     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2435   },
2436 /* lduh $dr,@($sr,$slo16) */
2437   {
2438     { 1, 1, 1, 1 },
2439     -1, "lduh-d2", "lduh",
2440     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2441     { 32, 32, 0xf0f00000 }, 0xa0b00000,
2442     (PTR) 0,
2443     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2444   },
2445 /* pop $dr */
2446   {
2447     { 1, 1, 1, 1 },
2448     -1, "pop", "pop",
2449     { MNEM, ' ', OP (DR), 0 },
2450     { 16, 16, 0xf0ff }, 0x20ef,
2451     (PTR) 0,
2452     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2453   },
2454 /* ldi $dr,$simm8 */
2455   {
2456     { 1, 1, 1, 1 },
2457     -1, "ldi8a", "ldi",
2458     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
2459     { 16, 16, 0xf000 }, 0x6000,
2460     (PTR) 0,
2461     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2462   },
2463 /* ldi $dr,$hash$slo16 */
2464   {
2465     { 1, 1, 1, 1 },
2466     -1, "ldi16a", "ldi",
2467     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
2468     { 32, 32, 0xf0ff0000 }, 0x90f00000,
2469     (PTR) 0,
2470     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2471   },
2472 /* rac $accd */
2473   {
2474     { 1, 1, 1, 1 },
2475     -1, "rac-d", "rac",
2476     { MNEM, ' ', OP (ACCD), 0 },
2477     { 16, 16, 0xf3ff }, 0x5090,
2478     (PTR) 0,
2479     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2480   },
2481 /* rac $accd,$accs */
2482   {
2483     { 1, 1, 1, 1 },
2484     -1, "rac-ds", "rac",
2485     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2486     { 16, 16, 0xf3f3 }, 0x5090,
2487     (PTR) 0,
2488     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2489   },
2490 /* rach $accd */
2491   {
2492     { 1, 1, 1, 1 },
2493     -1, "rach-d", "rach",
2494     { MNEM, ' ', OP (ACCD), 0 },
2495     { 16, 16, 0xf3ff }, 0x5080,
2496     (PTR) 0,
2497     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2498   },
2499 /* rach $accd,$accs */
2500   {
2501     { 1, 1, 1, 1 },
2502     -1, "rach-ds", "rach",
2503     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2504     { 16, 16, 0xf3f3 }, 0x5080,
2505     (PTR) 0,
2506     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2507   },
2508 /* st $src1,@($src2) */
2509   {
2510     { 1, 1, 1, 1 },
2511     -1, "st-2", "st",
2512     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2513     { 16, 16, 0xf0f0 }, 0x2040,
2514     (PTR) 0,
2515     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2516   },
2517 /* st $src1,@($src2,$slo16) */
2518   {
2519     { 1, 1, 1, 1 },
2520     -1, "st-d2", "st",
2521     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2522     { 32, 32, 0xf0f00000 }, 0xa0400000,
2523     (PTR) 0,
2524     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2525   },
2526 /* stb $src1,@($src2) */
2527   {
2528     { 1, 1, 1, 1 },
2529     -1, "stb-2", "stb",
2530     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2531     { 16, 16, 0xf0f0 }, 0x2000,
2532     (PTR) 0,
2533     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2534   },
2535 /* stb $src1,@($src2,$slo16) */
2536   {
2537     { 1, 1, 1, 1 },
2538     -1, "stb-d2", "stb",
2539     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2540     { 32, 32, 0xf0f00000 }, 0xa0000000,
2541     (PTR) 0,
2542     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2543   },
2544 /* sth $src1,@($src2) */
2545   {
2546     { 1, 1, 1, 1 },
2547     -1, "sth-2", "sth",
2548     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2549     { 16, 16, 0xf0f0 }, 0x2020,
2550     (PTR) 0,
2551     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2552   },
2553 /* sth $src1,@($src2,$slo16) */
2554   {
2555     { 1, 1, 1, 1 },
2556     -1, "sth-d2", "sth",
2557     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2558     { 32, 32, 0xf0f00000 }, 0xa0200000,
2559     (PTR) 0,
2560     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2561   },
2562 /* push $src1 */
2563   {
2564     { 1, 1, 1, 1 },
2565     -1, "push", "push",
2566     { MNEM, ' ', OP (SRC1), 0 },
2567     { 16, 16, 0xf0ff }, 0x207f,
2568     (PTR) 0,
2569     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2570   },
2571 };
2572
2573 #undef A
2574 #undef MNEM
2575 #undef OP
2576
2577 static CGEN_INSN_TABLE macro_insn_table =
2578 {
2579   & macro_insn_table_entries[0],
2580   sizeof (CGEN_INSN),
2581   (sizeof (macro_insn_table_entries) /
2582    sizeof (macro_insn_table_entries[0])),
2583   NULL
2584 };
2585
2586 /* The hash functions are recorded here to help keep assembler code out of
2587    the disassembler and vice versa.
2588
2589 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
2590 static unsigned int asm_hash_insn PARAMS ((const char *));
2591 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
2592 static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
2593
2594 /* Return non-zero if INSN is to be added to the hash table.
2595    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2596
2597 static int
2598 asm_hash_insn_p (insn)
2599      const CGEN_INSN * insn;
2600 {
2601   return CGEN_ASM_HASH_P (insn);
2602 }
2603
2604 static int
2605 dis_hash_insn_p (insn)
2606      const CGEN_INSN * insn;
2607 {
2608   /* If building the hash table and the NO-DIS attribute is present,
2609      ignore.  */
2610   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2611     return 0;
2612   return CGEN_DIS_HASH_P (insn);
2613 }
2614
2615 /* The result is the hash value of the insn.
2616    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2617
2618 static unsigned int
2619 asm_hash_insn (mnem)
2620      const char * mnem;
2621 {
2622   return CGEN_ASM_HASH (mnem);
2623 }
2624
2625 static unsigned int
2626 dis_hash_insn (buf, value)
2627      const char * buf;
2628      unsigned long value;
2629 {
2630   return CGEN_DIS_HASH (buf, value);
2631 }
2632
2633 const CGEN_OPCODE_TABLE m32r_cgen_opcode_table =
2634 {
2635   & m32r_cgen_hw_entries[0],
2636   /*& m32r_cgen_operand_table[0], - FIXME:wip */
2637   & insn_table,
2638   & macro_insn_table,
2639   asm_hash_insn_p, asm_hash_insn, CGEN_ASM_HASH_SIZE,
2640   dis_hash_insn_p, dis_hash_insn, CGEN_DIS_HASH_SIZE
2641 };
2642
2643 void
2644 m32r_cgen_init_tables (mach)
2645     int mach;
2646 {
2647 }
2648
2649 /* Main entry point for stuffing values in cgen_fields.  */
2650
2651 void
2652 m32r_cgen_set_operand (opindex, valuep, fields)
2653      int opindex;
2654      const long * valuep;
2655      CGEN_FIELDS * fields;
2656 {
2657   switch (opindex)
2658     {
2659     case M32R_OPERAND_SR :
2660       fields->f_r2 = * valuep;
2661       break;
2662     case M32R_OPERAND_DR :
2663       fields->f_r1 = * valuep;
2664       break;
2665     case M32R_OPERAND_SRC1 :
2666       fields->f_r1 = * valuep;
2667       break;
2668     case M32R_OPERAND_SRC2 :
2669       fields->f_r2 = * valuep;
2670       break;
2671     case M32R_OPERAND_SCR :
2672       fields->f_r2 = * valuep;
2673       break;
2674     case M32R_OPERAND_DCR :
2675       fields->f_r1 = * valuep;
2676       break;
2677     case M32R_OPERAND_SIMM8 :
2678       fields->f_simm8 = * valuep;
2679       break;
2680     case M32R_OPERAND_SIMM16 :
2681       fields->f_simm16 = * valuep;
2682       break;
2683     case M32R_OPERAND_UIMM4 :
2684       fields->f_uimm4 = * valuep;
2685       break;
2686     case M32R_OPERAND_UIMM5 :
2687       fields->f_uimm5 = * valuep;
2688       break;
2689     case M32R_OPERAND_UIMM16 :
2690       fields->f_uimm16 = * valuep;
2691       break;
2692 /* start-sanitize-m32rx */
2693     case M32R_OPERAND_IMM1 :
2694       fields->f_imm1 = * valuep;
2695       break;
2696 /* end-sanitize-m32rx */
2697 /* start-sanitize-m32rx */
2698     case M32R_OPERAND_ACCD :
2699       fields->f_accd = * valuep;
2700       break;
2701 /* end-sanitize-m32rx */
2702 /* start-sanitize-m32rx */
2703     case M32R_OPERAND_ACCS :
2704       fields->f_accs = * valuep;
2705       break;
2706 /* end-sanitize-m32rx */
2707 /* start-sanitize-m32rx */
2708     case M32R_OPERAND_ACC :
2709       fields->f_acc = * valuep;
2710       break;
2711 /* end-sanitize-m32rx */
2712     case M32R_OPERAND_HASH :
2713       fields->f_nil = * valuep;
2714       break;
2715     case M32R_OPERAND_HI16 :
2716       fields->f_hi16 = * valuep;
2717       break;
2718     case M32R_OPERAND_SLO16 :
2719       fields->f_simm16 = * valuep;
2720       break;
2721     case M32R_OPERAND_ULO16 :
2722       fields->f_uimm16 = * valuep;
2723       break;
2724     case M32R_OPERAND_UIMM24 :
2725       fields->f_uimm24 = * valuep;
2726       break;
2727     case M32R_OPERAND_DISP8 :
2728       fields->f_disp8 = * valuep;
2729       break;
2730     case M32R_OPERAND_DISP16 :
2731       fields->f_disp16 = * valuep;
2732       break;
2733     case M32R_OPERAND_DISP24 :
2734       fields->f_disp24 = * valuep;
2735       break;
2736
2737     default :
2738       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2739                        opindex);
2740       abort ();
2741   }
2742 }
2743
2744 /* Main entry point for getting values from cgen_fields.  */
2745
2746 long
2747 m32r_cgen_get_operand (opindex, fields)
2748      int opindex;
2749      const CGEN_FIELDS * fields;
2750 {
2751   long value;
2752
2753   switch (opindex)
2754     {
2755     case M32R_OPERAND_SR :
2756       value = fields->f_r2;
2757       break;
2758     case M32R_OPERAND_DR :
2759       value = fields->f_r1;
2760       break;
2761     case M32R_OPERAND_SRC1 :
2762       value = fields->f_r1;
2763       break;
2764     case M32R_OPERAND_SRC2 :
2765       value = fields->f_r2;
2766       break;
2767     case M32R_OPERAND_SCR :
2768       value = fields->f_r2;
2769       break;
2770     case M32R_OPERAND_DCR :
2771       value = fields->f_r1;
2772       break;
2773     case M32R_OPERAND_SIMM8 :
2774       value = fields->f_simm8;
2775       break;
2776     case M32R_OPERAND_SIMM16 :
2777       value = fields->f_simm16;
2778       break;
2779     case M32R_OPERAND_UIMM4 :
2780       value = fields->f_uimm4;
2781       break;
2782     case M32R_OPERAND_UIMM5 :
2783       value = fields->f_uimm5;
2784       break;
2785     case M32R_OPERAND_UIMM16 :
2786       value = fields->f_uimm16;
2787       break;
2788 /* start-sanitize-m32rx */
2789     case M32R_OPERAND_IMM1 :
2790       value = fields->f_imm1;
2791       break;
2792 /* end-sanitize-m32rx */
2793 /* start-sanitize-m32rx */
2794     case M32R_OPERAND_ACCD :
2795       value = fields->f_accd;
2796       break;
2797 /* end-sanitize-m32rx */
2798 /* start-sanitize-m32rx */
2799     case M32R_OPERAND_ACCS :
2800       value = fields->f_accs;
2801       break;
2802 /* end-sanitize-m32rx */
2803 /* start-sanitize-m32rx */
2804     case M32R_OPERAND_ACC :
2805       value = fields->f_acc;
2806       break;
2807 /* end-sanitize-m32rx */
2808     case M32R_OPERAND_HASH :
2809       value = fields->f_nil;
2810       break;
2811     case M32R_OPERAND_HI16 :
2812       value = fields->f_hi16;
2813       break;
2814     case M32R_OPERAND_SLO16 :
2815       value = fields->f_simm16;
2816       break;
2817     case M32R_OPERAND_ULO16 :
2818       value = fields->f_uimm16;
2819       break;
2820     case M32R_OPERAND_UIMM24 :
2821       value = fields->f_uimm24;
2822       break;
2823     case M32R_OPERAND_DISP8 :
2824       value = fields->f_disp8;
2825       break;
2826     case M32R_OPERAND_DISP16 :
2827       value = fields->f_disp16;
2828       break;
2829     case M32R_OPERAND_DISP24 :
2830       value = fields->f_disp24;
2831       break;
2832
2833     default :
2834       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2835                        opindex);
2836       abort ();
2837   }
2838
2839   return value;
2840 }
2841