opcodes/m32r-opc.c

   1 /* CGEN opcode support for m32r.
   2
   3 This file is machine generated.
   4
   5 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include "ansidecl.h"
  29 #include "libiberty.h"
  30 #include "bfd.h"
  31 #include "m32r-opc.h"
  32
  33 /* Attributes.  */
  34
  35 static const CGEN_ATTR_ENTRY MACH_attr[] = {
  36   { "m32r", MACH_M32R },
  37   { "m32rx", MACH_M32RX },
  38   { 0, 0 }
  39 };
  40
  41 static const CGEN_ATTR_ENTRY PIPE_attr[] = {
  42   { "NONE", PIPE_NONE },
  43   { "O", PIPE_O },
  44   { "S", PIPE_S },
  45   { "OS", PIPE_OS },
  46   { 0, 0 }
  47 };
  48
  49 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = {
  50   { "ABS-ADDR", NULL },
  51   { "FAKE", NULL },
  52   { "NEGATIVE", NULL },
  53   { "PC", NULL },
  54   { "PCREL-ADDR", NULL },
  55   { "RELAX", NULL },
  56   { "RELOC", NULL },
  57   { "SIGN-OPT", NULL },
  58   { "UNSIGNED", NULL },
  59   { 0, 0 }
  60 };
  61
  62 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = {
  63   { "MACH", & MACH_attr[0] },
  64   { "PIPE", & PIPE_attr[0] },
  65   { "ALIAS", NULL },
  66   { "COND-CTI", NULL },
  67   { "FILL-SLOT", NULL },
  68   { "PARALLEL", NULL },
  69   { "RELAX", NULL },
  70   { "RELAX-BC", NULL },
  71   { "RELAX-BCL", NULL },
  72   { "RELAX-BL", NULL },
  73   { "RELAX-BNC", NULL },
  74   { "RELAX-BNCL", NULL },
  75   { "RELAX-BRA", NULL },
  76   { "RELAXABLE", NULL },
  77   { "UNCOND-CTI", NULL },
  78   { 0, 0 }
  79 };
  80
  81 CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] = {
  82   { "m32r", MACH_M32R },
  83   { "m32rx", MACH_M32RX }
  84 };
  85
  86 CGEN_KEYWORD m32r_cgen_opval_mach = {
  87   & m32r_cgen_opval_mach_entries[0],
  88   2
  89 };
  90
  91 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] = {
  92   { "fp", 13 },
  93   { "lr", 14 },
  94   { "sp", 15 },
  95   { "r0", 0 },
  96   { "r1", 1 },
  97   { "r2", 2 },
  98   { "r3", 3 },
  99   { "r4", 4 },
 100   { "r5", 5 },
 101   { "r6", 6 },
 102   { "r7", 7 },
 103   { "r8", 8 },
 104   { "r9", 9 },
 105   { "r10", 10 },
 106   { "r11", 11 },
 107   { "r12", 12 },
 108   { "r13", 13 },
 109   { "r14", 14 },
 110   { "r15", 15 }
 111 };
 112
 113 CGEN_KEYWORD m32r_cgen_opval_h_gr = {
 114   & m32r_cgen_opval_h_gr_entries[0],
 115   19
 116 };
 117
 118 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] = {
 119   { "psw", 0 },
 120   { "cbr", 1 },
 121   { "spi", 2 },
 122   { "spu", 3 },
 123   { "bpc", 6 },
 124   { "cr0", 0 },
 125   { "cr1", 1 },
 126   { "cr2", 2 },
 127   { "cr3", 3 },
 128   { "cr4", 4 },
 129   { "cr5", 5 },
 130   { "cr6", 6 }
 131 };
 132
 133 CGEN_KEYWORD m32r_cgen_opval_h_cr = {
 134   & m32r_cgen_opval_h_cr_entries[0],
 135   12
 136 };
 137
 138 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = {
 139   { "a0", 0 },
 140   { "a1", 1 }
 141 };
 142
 143 CGEN_KEYWORD m32r_cgen_opval_h_accums = {
 144   & m32r_cgen_opval_h_accums_entries[0],
 145   2
 146 };
 147
 148
 149 static CGEN_HW_ENTRY m32r_cgen_hw_entries[] = {
 150   { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 151   { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 152   { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 153   { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 154   { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 155   { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 156   { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 157   { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 158   { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 159   { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr },
 160   { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr },
 161   { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 162   { & m32r_cgen_hw_entries[13], "h-accums", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_accums },
 163   { & m32r_cgen_hw_entries[14], "h-abort", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 164   { & m32r_cgen_hw_entries[15], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 165   { & m32r_cgen_hw_entries[16], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 166   { & m32r_cgen_hw_entries[17], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 167   { & m32r_cgen_hw_entries[18], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 168   { & m32r_cgen_hw_entries[19], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 169   { & m32r_cgen_hw_entries[20], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 170   { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }
 171 };
 172
 173
 174 const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
 175 {
 176 /* pc: program counter */
 177   { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 178 /* sr: source register */
 179   { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 180 /* dr: destination register */
 181   { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 182 /* src1: source register 1 */
 183   { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 184 /* src2: source register 2 */
 185   { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 186 /* scr: source control register */
 187   { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 188 /* dcr: destination control register */
 189   { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 190 /* simm8: 8 bit signed immediate */
 191   { "simm8", 8, 8, { 0, 0, { 0 } }  },
 192 /* simm16: 16 bit signed immediate */
 193   { "simm16", 16, 16, { 0, 0, { 0 } }  },
 194 /* uimm4: 4 bit trap number */
 195   { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 196 /* uimm5: 5 bit shift count */
 197   { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 198 /* uimm16: 16 bit unsigned immediate */
 199   { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 200 /* acc-s: accumulator register */
 201   { "acc-s", 12, 2, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 202 /* acc: accumulator reg (d) */
 203   { "acc", 8, 1, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 204 /* hi16: high 16 bit immediate, sign optional */
 205   { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 206 /* slo16: 16 bit signed immediate, for low() */
 207   { "slo16", 16, 16, { 0, 0, { 0 } }  },
 208 /* ulo16: 16 bit unsigned immediate, for low() */
 209   { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 210 /* uimm24: 24 bit address */
 211   { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 212 /* disp8: 8 bit displacement */
 213   { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 214 /* disp16: 16 bit displacement */
 215   { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 216 /* disp24: 24 bit displacement */
 217   { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 218 /* condbit: condition bit */
 219   { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 220 /* accum: accumulator */
 221   { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 222 /* abort-parallel-execution: abort parallel execution */
 223   { "abort-parallel-execution", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 224 };
 225
 226 #define OP 1 /* syntax value for mnemonic */
 227
 228 static const CGEN_SYNTAX syntax_table[] = {
 229 /* <op> $dr,$sr */
 230 /*   0 */  { OP, ' ', 130, ',', 129, 0 },
 231 /* <op> $dr,$sr,$slo16 */
 232 /*   1 */  { OP, ' ', 130, ',', 129, ',', 143, 0 },
 233 /* <op> $dr,$sr,$uimm16 */
 234 /*   2 */  { OP, ' ', 130, ',', 129, ',', 139, 0 },
 235 /* <op> $dr,$sr,$ulo16 */
 236 /*   3 */  { OP, ' ', 130, ',', 129, ',', 144, 0 },
 237 /* <op> $dr,$simm8 */
 238 /*   4 */  { OP, ' ', 130, ',', 135, 0 },
 239 /* <op> $dr,$sr,$simm16 */
 240 /*   5 */  { OP, ' ', 130, ',', 129, ',', 136, 0 },
 241 /* <op> $disp8 */
 242 /*   6 */  { OP, ' ', 146, 0 },
 243 /* <op> $disp24 */
 244 /*   7 */  { OP, ' ', 148, 0 },
 245 /* <op> $src1,$src2,$disp16 */
 246 /*   8 */  { OP, ' ', 131, ',', 132, ',', 147, 0 },
 247 /* <op> $src2,$disp16 */
 248 /*   9 */  { OP, ' ', 132, ',', 147, 0 },
 249 /* <op> $src1,$src2 */
 250 /*  10 */  { OP, ' ', 131, ',', 132, 0 },
 251 /* <op> $src2,$simm16 */
 252 /*  11 */  { OP, ' ', 132, ',', 136, 0 },
 253 /* <op> $src2,$uimm16 */
 254 /*  12 */  { OP, ' ', 132, ',', 139, 0 },
 255 /* <op> $src2 */
 256 /*  13 */  { OP, ' ', 132, 0 },
 257 /* <op> $sr */
 258 /*  14 */  { OP, ' ', 129, 0 },
 259 /* <op> $dr,@$sr */
 260 /*  15 */  { OP, ' ', 130, ',', '@', 129, 0 },
 261 /* <op> $dr,@($sr) */
 262 /*  16 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
 263 /* <op> $dr,@($slo16,$sr) */
 264 /*  17 */  { OP, ' ', 130, ',', '@', '(', 143, ',', 129, ')', 0 },
 265 /* <op> $dr,@($sr,$slo16) */
 266 /*  18 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 143, ')', 0 },
 267 /* <op> $dr,@$sr+ */
 268 /*  19 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
 269 /* <op> $dr,$uimm24 */
 270 /*  20 */  { OP, ' ', 130, ',', 145, 0 },
 271 /* <op> $dr,$slo16 */
 272 /*  21 */  { OP, ' ', 130, ',', 143, 0 },
 273 /* <op> $src1,$src2,$acc */
 274 /*  22 */  { OP, ' ', 131, ',', 132, ',', 141, 0 },
 275 /* <op> $dr */
 276 /*  23 */  { OP, ' ', 130, 0 },
 277 /* <op> $dr,$accs */
 278 /*  24 */  { OP, ' ', 130, ',', 141, 0 },
 279 /* <op> $dr,$scr */
 280 /*  25 */  { OP, ' ', 130, ',', 133, 0 },
 281 /* <op> $src1 */
 282 /*  26 */  { OP, ' ', 131, 0 },
 283 /* <op> $src1,$accs */
 284 /*  27 */  { OP, ' ', 131, ',', 141, 0 },
 285 /* <op> $sr,$dcr */
 286 /*  28 */  { OP, ' ', 129, ',', 134, 0 },
 287 /* <op> */
 288 /*  29 */  { OP, 0 },
 289 /* <op> $acc-s */
 290 /*  30 */  { OP, ' ', 141, 0 },
 291 /* <op> $dr,$hi16 */
 292 /*  31 */  { OP, ' ', 130, ',', 142, 0 },
 293 /* <op> $dr,$uimm5 */
 294 /*  32 */  { OP, ' ', 130, ',', 138, 0 },
 295 /* <op> $src1,@$src2 */
 296 /*  33 */  { OP, ' ', 131, ',', '@', 132, 0 },
 297 /* <op> $src1,@($src2) */
 298 /*  34 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
 299 /* <op> $src1,@($slo16,$src2) */
 300 /*  35 */  { OP, ' ', 131, ',', '@', '(', 143, ',', 132, ')', 0 },
 301 /* <op> $src1,@($src2,$slo16) */
 302 /*  36 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 143, ')', 0 },
 303 /* <op> $src1,@+$src2 */
 304 /*  37 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
 305 /* <op> $src1,@-$src2 */
 306 /*  38 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
 307 /* <op> $uimm4 */
 308 /*  39 */  { OP, ' ', 137, 0 },
 309 /* <op> $dr,$src2 */
 310 /*  40 */  { OP, ' ', 130, ',', 132, 0 },
 311 };
 312
 313 #undef OP
 314
 315 static const CGEN_FORMAT format_table[] = {
 316 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
 317 /*   0 */  { 16, 16, 0xf0f0 },
 318 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
 319 /*   1 */  { 32, 32, 0xf0f00000 },
 320 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */
 321 /*   2 */  { 32, 32, 0xf0f00000 },
 322 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */
 323 /*   3 */  { 32, 32, 0xf0f00000 },
 324 /* f-op1.number.f-r1.dr.f-simm8.simm8. */
 325 /*   4 */  { 16, 16, 0xf000 },
 326 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */
 327 /*   5 */  { 32, 32, 0xf0f00000 },
 328 /* f-op1.number.f-r1.number.f-disp8.disp8. */
 329 /*   6 */  { 16, 16, 0xff00 },
 330 /* f-op1.number.f-r1.number.f-disp24.disp24. */
 331 /*   7 */  { 32, 32, 0xff000000 },
 332 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */
 333 /*   8 */  { 32, 32, 0xf0f00000 },
 334 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */
 335 /*   9 */  { 32, 32, 0xfff00000 },
 336 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
 337 /*  10 */  { 16, 16, 0xf0f0 },
 338 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */
 339 /*  11 */  { 32, 32, 0xfff00000 },
 340 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
 341 /*  12 */  { 32, 32, 0xfff00000 },
 342 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2. */
 343 /*  13 */  { 16, 16, 0xfff0 },
 344 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
 345 /*  14 */  { 32, 32, 0xf0f0ffff },
 346 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
 347 /*  15 */  { 16, 16, 0xfff0 },
 348 /* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
 349 /*  16 */  { 32, 32, 0xf0000000 },
 350 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
 351 /*  17 */  { 32, 32, 0xf0ff0000 },
 352 /* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2. */
 353 /*  18 */  { 16, 16, 0xf070 },
 354 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
 355 /*  19 */  { 16, 16, 0xf0ff },
 356 /* f-op1.number.f-r1.dr.f-op2.number.f-acc-s.acc-s.f-op3.number. */
 357 /*  20 */  { 16, 16, 0xf0f3 },
 358 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
 359 /*  21 */  { 16, 16, 0xf0f0 },
 360 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
 361 /*  22 */  { 16, 16, 0xf0ff },
 362 /* f-op1.number.f-r1.src1.f-op2.number.f-acc-s.acc-s.f-op3.number. */
 363 /*  23 */  { 16, 16, 0xf0f3 },
 364 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
 365 /*  24 */  { 16, 16, 0xf0f0 },
 366 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
 367 /*  25 */  { 16, 16, 0xffff },
 368 /* f-op1.number.f-r1.number.f-op2.number.f-acc-s.acc-s.f-op3.number. */
 369 /*  26 */  { 16, 16, 0xfff3 },
 370 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
 371 /*  27 */  { 32, 32, 0xf0ff0000 },
 372 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
 373 /*  28 */  { 16, 16, 0xf0e0 },
 374 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
 375 /*  29 */  { 32, 32, 0xf0f00000 },
 376 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
 377 /*  30 */  { 16, 16, 0xfff0 },
 378 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number. */
 379 /*  31 */  { 32, 32, 0xf0f0ffff },
 380 };
 381
 382 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
 383 #define SYN(n) (& syntax_table[n])
 384 #define FMT(n) (& format_table[n])
 385
 386 const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] = {
 387 /* null first entry, end of all hash chains */
 388   { { 0 }, 0 },
 389 /* add $dr,$sr */
 390   {
 391     { 1, 1, 1, 1 },
 392     "add", "add", SYN (0), FMT (0), 0xa0,
 393     { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
 394   },
 395 /* add3 $dr,$sr,$slo16 */
 396   {
 397     { 1, 1, 1, 1 },
 398     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
 399     { 2, 0, { 0 } }
 400   },
 401 /* and $dr,$sr */
 402   {
 403     { 1, 1, 1, 1 },
 404     "and", "and", SYN (0), FMT (0), 0xc0,
 405     { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
 406   },
 407 /* and3 $dr,$sr,$uimm16 */
 408   {
 409     { 1, 1, 1, 1 },
 410     "and3", "and3", SYN (2), FMT (2), 0x80c00000,
 411     { 2, 0, { 0 } }
 412   },
 413 /* or $dr,$sr */
 414   {
 415     { 1, 1, 1, 1 },
 416     "or", "or", SYN (0), FMT (0), 0xe0,
 417     { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
 418   },
 419 /* or3 $dr,$sr,$ulo16 */
 420   {
 421     { 1, 1, 1, 1 },
 422     "or3", "or3", SYN (3), FMT (3), 0x80e00000,
 423     { 2, 0, { 0 } }
 424   },
 425 /* xor $dr,$sr */
 426   {
 427     { 1, 1, 1, 1 },
 428     "xor", "xor", SYN (0), FMT (0), 0xd0,
 429     { 2, 0|A(PARALLEL), { [CGEN_INSN_PIPE] = PIPE_OS } }
 430   },
 431 /* xor3 $dr,$sr,$uimm16 */
 432   {
 433     { 1, 1, 1, 1 },
 434     "xor3", "xor3", SYN (2), FMT (2), 0x80d00000,
 435     { 2, 0, { 0 } }
 436   },
 437 /* addi $dr,$simm8 */
 438   {
 439     { 1, 1, 1, 1 },
 440     "addi", "addi", SYN (4), FMT (4), 0x4000,
 441     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
 442   },
 443 /* addv $dr,$sr */
 444   {
 445     { 1, 1, 1, 1 },
 446     "addv", "addv", SYN (0), FMT (0), 0x80,
 447     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
 448   },
 449 /* addv3 $dr,$sr,$simm16 */
 450   {
 451     { 1, 1, 1, 1 },
 452     "addv3", "addv3", SYN (5), FMT (5), 0x80800000,
 453     { 2, 0, { 0 } }
 454   },
 455 /* addx $dr,$sr */
 456   {
 457     { 1, 1, 1, 1 },
 458     "addx", "addx", SYN (0), FMT (0), 0x90,
 459     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
 460   },
 461 /* bc $disp8 */
 462   {
 463     { 1, 1, 1, 1 },
 464     "bc8", "bc", SYN (6), FMT (6), 0x7c00,
 465     { 2, 0|A(RELAX_BC)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 466   },
 467 /* bc.s $disp8 */
 468   {
 469     { 1, 1, 1, 1 },
 470     "bc8.s", "bc.s", SYN (6), FMT (6), 0x7c00,
 471     { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 472   },
 473 /* bc $disp24 */
 474   {
 475     { 1, 1, 1, 1 },
 476     "bc24", "bc", SYN (7), FMT (7), 0xfc000000,
 477     { 2, 0|A(RELAX_BC)|A(RELAX)|A(COND_CTI), { 0 } }
 478   },
 479 /* bc.l $disp24 */
 480   {
 481     { 1, 1, 1, 1 },
 482     "bc24.l", "bc.l", SYN (7), FMT (7), 0xfc000000,
 483     { 2, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 484   },
 485 /* beq $src1,$src2,$disp16 */
 486   {
 487     { 1, 1, 1, 1 },
 488     "beq", "beq", SYN (8), FMT (8), 0xb0000000,
 489     { 2, 0|A(COND_CTI), { 0 } }
 490   },
 491 /* beqz $src2,$disp16 */
 492   {
 493     { 1, 1, 1, 1 },
 494     "beqz", "beqz", SYN (9), FMT (9), 0xb0800000,
 495     { 2, 0|A(COND_CTI), { 0 } }
 496   },
 497 /* bgez $src2,$disp16 */
 498   {
 499     { 1, 1, 1, 1 },
 500     "bgez", "bgez", SYN (9), FMT (9), 0xb0b00000,
 501     { 2, 0|A(COND_CTI), { 0 } }
 502   },
 503 /* bgtz $src2,$disp16 */
 504   {
 505     { 1, 1, 1, 1 },
 506     "bgtz", "bgtz", SYN (9), FMT (9), 0xb0d00000,
 507     { 2, 0|A(COND_CTI), { 0 } }
 508   },
 509 /* blez $src2,$disp16 */
 510   {
 511     { 1, 1, 1, 1 },
 512     "blez", "blez", SYN (9), FMT (9), 0xb0c00000,
 513     { 2, 0|A(COND_CTI), { 0 } }
 514   },
 515 /* bltz $src2,$disp16 */
 516   {
 517     { 1, 1, 1, 1 },
 518     "bltz", "bltz", SYN (9), FMT (9), 0xb0a00000,
 519     { 2, 0|A(COND_CTI), { 0 } }
 520   },
 521 /* bnez $src2,$disp16 */
 522   {
 523     { 1, 1, 1, 1 },
 524     "bnez", "bnez", SYN (9), FMT (9), 0xb0900000,
 525     { 2, 0|A(COND_CTI), { 0 } }
 526   },
 527 /* bl $disp8 */
 528   {
 529     { 1, 1, 1, 1 },
 530     "bl8", "bl", SYN (6), FMT (6), 0x7e00,
 531     { 2, 0|A(FILL_SLOT)|A(RELAX_BL)|A(RELAXABLE)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 532   },
 533 /* bl.s $disp8 */
 534   {
 535     { 1, 1, 1, 1 },
 536     "bl8.s", "bl.s", SYN (6), FMT (6), 0x7e00,
 537     { 2, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 538   },
 539 /* bl $disp24 */
 540   {
 541     { 1, 1, 1, 1 },
 542     "bl24", "bl", SYN (7), FMT (7), 0xfe000000,
 543     { 2, 0|A(RELAX_BL)|A(RELAX)|A(UNCOND_CTI), { 0 } }
 544   },
 545 /* bl.l $disp24 */
 546   {
 547     { 1, 1, 1, 1 },
 548     "bl24.l", "bl.l", SYN (7), FMT (7), 0xfe000000,
 549     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 550   },
 551 /* bcl $disp8 */
 552   {
 553     { 1, 1, 1, 1 },
 554     "bcl8", "bcl", SYN (6), FMT (6), 0x7800,
 555     { 2, 0|A(RELAX_BCL)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 556   },
 557 /* bcl.s $disp8 */
 558   {
 559     { 1, 1, 1, 1 },
 560     "bcl8.s", "bcl.s", SYN (6), FMT (6), 0x7800,
 561     { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 562   },
 563 /* bcl $disp24 */
 564   {
 565     { 1, 1, 1, 1 },
 566     "bcl24", "bcl", SYN (7), FMT (7), 0xf8000000,
 567     { 2, 0|A(RELAX_BCL)|A(RELAX)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 568   },
 569 /* bcl.l $disp24 */
 570   {
 571     { 1, 1, 1, 1 },
 572     "bcl24.l", "bcl.l", SYN (7), FMT (7), 0xf8000000,
 573     { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 574   },
 575 /* bnc $disp8 */
 576   {
 577     { 1, 1, 1, 1 },
 578     "bnc8", "bnc", SYN (6), FMT (6), 0x7d00,
 579     { 2, 0|A(RELAX_BNC)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 580   },
 581 /* bnc.s $disp8 */
 582   {
 583     { 1, 1, 1, 1 },
 584     "bnc8.s", "bnc.s", SYN (6), FMT (6), 0x7d00,
 585     { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 586   },
 587 /* bnc $disp24 */
 588   {
 589     { 1, 1, 1, 1 },
 590     "bnc24", "bnc", SYN (7), FMT (7), 0xfd000000,
 591     { 2, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { 0 } }
 592   },
 593 /* bnc.l $disp24 */
 594   {
 595     { 1, 1, 1, 1 },
 596     "bnc24.l", "bnc.l", SYN (7), FMT (7), 0xfd000000,
 597     { 2, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 598   },
 599 /* bne $src1,$src2,$disp16 */
 600   {
 601     { 1, 1, 1, 1 },
 602     "bne", "bne", SYN (8), FMT (8), 0xb0100000,
 603     { 2, 0|A(COND_CTI), { 0 } }
 604   },
 605 /* bra $disp8 */
 606   {
 607     { 1, 1, 1, 1 },
 608     "bra8", "bra", SYN (6), FMT (6), 0x7f00,
 609     { 2, 0|A(FILL_SLOT)|A(RELAX_BRA)|A(RELAXABLE)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 610   },
 611 /* bra.s $disp8 */
 612   {
 613     { 1, 1, 1, 1 },
 614     "bra8.s", "bra.s", SYN (6), FMT (6), 0x7f00,
 615     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 616   },
 617 /* bra $disp24 */
 618   {
 619     { 1, 1, 1, 1 },
 620     "bra24", "bra", SYN (7), FMT (7), 0xff000000,
 621     { 2, 0|A(RELAX_BRA)|A(RELAX)|A(UNCOND_CTI), { 0 } }
 622   },
 623 /* bra.l $disp24 */
 624   {
 625     { 1, 1, 1, 1 },
 626     "bra24.l", "bra.l", SYN (7), FMT (7), 0xff000000,
 627     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 628   },
 629 /* bncl $disp8 */
 630   {
 631     { 1, 1, 1, 1 },
 632     "bncl8", "bncl", SYN (6), FMT (6), 0x7900,
 633     { 2, 0|A(RELAX_BNCL)|A(RELAXABLE)|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 634   },
 635 /* bncl.s $disp8 */
 636   {
 637     { 1, 1, 1, 1 },
 638     "bncl8.s", "bncl.s", SYN (6), FMT (6), 0x7900,
 639     { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 640   },
 641 /* bncl $disp24 */
 642   {
 643     { 1, 1, 1, 1 },
 644     "bncl24", "bncl", SYN (7), FMT (7), 0xf9000000,
 645     { 2, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 646   },
 647 /* bncl.l $disp24 */
 648   {
 649     { 1, 1, 1, 1 },
 650     "bncl24.l", "bncl.l", SYN (7), FMT (7), 0xf9000000,
 651     { 2, 0|A(ALIAS)|A(COND_CTI), { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 652   },
 653 /* cmp $src1,$src2 */
 654   {
 655     { 1, 1, 1, 1 },
 656     "cmp", "cmp", SYN (10), FMT (10), 0x40,
 657     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
 658   },
 659 /* cmpi $src2,$simm16 */
 660   {
 661     { 1, 1, 1, 1 },
 662     "cmpi", "cmpi", SYN (11), FMT (11), 0x80400000,
 663     { 2, 0, { 0 } }
 664   },
 665 /* cmpu $src1,$src2 */
 666   {
 667     { 1, 1, 1, 1 },
 668     "cmpu", "cmpu", SYN (10), FMT (10), 0x50,
 669     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
 670   },
 671 /* cmpui $src2,$uimm16 */
 672   {
 673     { 1, 1, 1, 1 },
 674     "cmpui", "cmpui", SYN (12), FMT (12), 0x80500000,
 675     { 2, 0, { [CGEN_INSN_MACH] = (1 << MACH_M32R) | (1 << MACH_M32RX) } }
 676   },
 677 /* cmpeq $src1,$src2 */
 678   {
 679     { 1, 1, 1, 1 },
 680     "cmpeq", "cmpeq", SYN (10), FMT (10), 0x60,
 681     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 682   },
 683 /* cmpz $src2 */
 684   {
 685     { 1, 1, 1, 1 },
 686     "cmpz", "cmpz", SYN (13), FMT (13), 0x70,
 687     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 688   },
 689 /* div $dr,$sr */
 690   {
 691     { 1, 1, 1, 1 },
 692     "div", "div", SYN (0), FMT (14), 0x90000000,
 693     { 2, 0, { 0 } }
 694   },
 695 /* divu $dr,$sr */
 696   {
 697     { 1, 1, 1, 1 },
 698     "divu", "divu", SYN (0), FMT (14), 0x90100000,
 699     { 2, 0, { 0 } }
 700   },
 701 /* rem $dr,$sr */
 702   {
 703     { 1, 1, 1, 1 },
 704     "rem", "rem", SYN (0), FMT (14), 0x90200000,
 705     { 2, 0, { 0 } }
 706   },
 707 /* remu $dr,$sr */
 708   {
 709     { 1, 1, 1, 1 },
 710     "remu", "remu", SYN (0), FMT (14), 0x90300000,
 711     { 2, 0, { 0 } }
 712   },
 713 /* jc $sr */
 714   {
 715     { 1, 1, 1, 1 },
 716     "jc", "jc", SYN (14), FMT (15), 0x1cc0,
 717     { 2, 0|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 718   },
 719 /* jnc $sr */
 720   {
 721     { 1, 1, 1, 1 },
 722     "jnc", "jnc", SYN (14), FMT (15), 0x1cc0,
 723     { 2, 0|A(COND_CTI), { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 724   },
 725 /* jl $sr */
 726   {
 727     { 1, 1, 1, 1 },
 728     "jl", "jl", SYN (14), FMT (15), 0x1ec0,
 729     { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 730   },
 731 /* jmp $sr */
 732   {
 733     { 1, 1, 1, 1 },
 734     "jmp", "jmp", SYN (14), FMT (15), 0x1fc0,
 735     { 2, 0|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
 736   },
 737 /* ld $dr,@$sr */
 738   {
 739     { 1, 1, 1, 1 },
 740     "ld", "ld", SYN (15), FMT (0), 0x20c0,
 741     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
 742   },
 743 /* ld $dr,@($sr) */
 744   {
 745     { 1, 1, 1, 1 },
 746     "ld-2", "ld", SYN (16), FMT (0), 0x20c0,
 747     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
 748   },
 749 /* ld $dr,@($slo16,$sr) */
 750   {
 751     { 1, 1, 1, 1 },
 752     "ld-d", "ld", SYN (17), FMT (1), 0xa0c00000,
 753     { 2, 0, { 0 } }
 754   },
 755 /* ld $dr,@($sr,$slo16) */
 756   {
 757     { 1, 1, 1, 1 },
 758     "ld-d2", "ld", SYN (18), FMT (1), 0xa0c00000,
 759     { 2, 0|A(ALIAS), { 0 } }
 760   },
 761 /* ldb $dr,@$sr */
 762   {
 763     { 1, 1, 1, 1 },
 764     "ldb", "ldb", SYN (15), FMT (0), 0x2080,
 765     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
 766   },
 767 /* ldb $dr,@($sr) */
 768   {
 769     { 1, 1, 1, 1 },
 770     "ldb-2", "ldb", SYN (16), FMT (0), 0x2080,
 771     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
 772   },
 773 /* ldb $dr,@($slo16,$sr) */
 774   {
 775     { 1, 1, 1, 1 },
 776     "ldb-d", "ldb", SYN (17), FMT (1), 0xa0800000,
 777     { 2, 0, { 0 } }
 778   },
 779 /* ldb $dr,@($sr,$slo16) */
 780   {
 781     { 1, 1, 1, 1 },
 782     "ldb-d2", "ldb", SYN (18), FMT (1), 0xa0800000,
 783     { 2, 0|A(ALIAS), { 0 } }
 784   },
 785 /* ldh $dr,@$sr */
 786   {
 787     { 1, 1, 1, 1 },
 788     "ldh", "ldh", SYN (15), FMT (0), 0x20a0,
 789     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
 790   },
 791 /* ldh $dr,@($sr) */
 792   {
 793     { 1, 1, 1, 1 },
 794     "ldh-2", "ldh", SYN (16), FMT (0), 0x20a0,
 795     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
 796   },
 797 /* ldh $dr,@($slo16,$sr) */
 798   {
 799     { 1, 1, 1, 1 },
 800     "ldh-d", "ldh", SYN (17), FMT (1), 0xa0a00000,
 801     { 2, 0, { 0 } }
 802   },
 803 /* ldh $dr,@($sr,$slo16) */
 804   {
 805     { 1, 1, 1, 1 },
 806     "ldh-d2", "ldh", SYN (18), FMT (1), 0xa0a00000,
 807     { 2, 0|A(ALIAS), { 0 } }
 808   },
 809 /* ldub $dr,@$sr */
 810   {
 811     { 1, 1, 1, 1 },
 812     "ldub", "ldub", SYN (15), FMT (0), 0x2090,
 813     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
 814   },
 815 /* ldub $dr,@($sr) */
 816   {
 817     { 1, 1, 1, 1 },
 818     "ldub-2", "ldub", SYN (16), FMT (0), 0x2090,
 819     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
 820   },
 821 /* ldub $dr,@($slo16,$sr) */
 822   {
 823     { 1, 1, 1, 1 },
 824     "ldub-d", "ldub", SYN (17), FMT (1), 0xa0900000,
 825     { 2, 0, { 0 } }
 826   },
 827 /* ldub $dr,@($sr,$slo16) */
 828   {
 829     { 1, 1, 1, 1 },
 830     "ldub-d2", "ldub", SYN (18), FMT (1), 0xa0900000,
 831     { 2, 0|A(ALIAS), { 0 } }
 832   },
 833 /* lduh $dr,@$sr */
 834   {
 835     { 1, 1, 1, 1 },
 836     "lduh", "lduh", SYN (15), FMT (0), 0x20b0,
 837     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
 838   },
 839 /* lduh $dr,@($sr) */
 840   {
 841     { 1, 1, 1, 1 },
 842     "lduh-2", "lduh", SYN (16), FMT (0), 0x20b0,
 843     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
 844   },
 845 /* lduh $dr,@($slo16,$sr) */
 846   {
 847     { 1, 1, 1, 1 },
 848     "lduh-d", "lduh", SYN (17), FMT (1), 0xa0b00000,
 849     { 2, 0, { 0 } }
 850   },
 851 /* lduh $dr,@($sr,$slo16) */
 852   {
 853     { 1, 1, 1, 1 },
 854     "lduh-d2", "lduh", SYN (18), FMT (1), 0xa0b00000,
 855     { 2, 0|A(ALIAS), { 0 } }
 856   },
 857 /* ld $dr,@$sr+ */
 858   {
 859     { 1, 1, 1, 1 },
 860     "ld-plus", "ld", SYN (19), FMT (0), 0x20e0,
 861     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
 862   },
 863 /* ld24 $dr,$uimm24 */
 864   {
 865     { 1, 1, 1, 1 },
 866     "ld24", "ld24", SYN (20), FMT (16), 0xe0000000,
 867     { 2, 0, { 0 } }
 868   },
 869 /* ldi $dr,$simm8 */
 870   {
 871     { 1, 1, 1, 1 },
 872     "ldi8", "ldi", SYN (4), FMT (4), 0x6000,
 873     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
 874   },
 875 /* ldi8 $dr,$simm8 */
 876   {
 877     { 1, 1, 1, 1 },
 878     "ldi8a", "ldi8", SYN (4), FMT (4), 0x6000,
 879     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_OS } }
 880   },
 881 /* ldi $dr,$slo16 */
 882   {
 883     { 1, 1, 1, 1 },
 884     "ldi16", "ldi", SYN (21), FMT (17), 0x90f00000,
 885     { 2, 0, { 0 } }
 886   },
 887 /* ldi16 $dr,$slo16 */
 888   {
 889     { 1, 1, 1, 1 },
 890     "ldi16a", "ldi16", SYN (21), FMT (17), 0x90f00000,
 891     { 2, 0|A(ALIAS), { 0 } }
 892   },
 893 /* lock $dr,@$sr */
 894   {
 895     { 1, 1, 1, 1 },
 896     "lock", "lock", SYN (15), FMT (0), 0x20d0,
 897     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
 898   },
 899 /* machi $src1,$src2 */
 900   {
 901     { 1, 1, 1, 1 },
 902     "machi", "machi", SYN (10), FMT (10), 0x3040,
 903     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 904   },
 905 /* machi $src1,$src2,$acc */
 906   {
 907     { 1, 1, 1, 1 },
 908     "machi-a", "machi", SYN (22), FMT (18), 0x3040,
 909     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 910   },
 911 /* maclo $src1,$src2 */
 912   {
 913     { 1, 1, 1, 1 },
 914     "maclo", "maclo", SYN (10), FMT (10), 0x3050,
 915     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 916   },
 917 /* maclo $src1,$src2,$acc */
 918   {
 919     { 1, 1, 1, 1 },
 920     "maclo-a", "maclo", SYN (22), FMT (18), 0x3050,
 921     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 922   },
 923 /* macwhi $src1,$src2 */
 924   {
 925     { 1, 1, 1, 1 },
 926     "macwhi", "macwhi", SYN (10), FMT (10), 0x3060,
 927     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 928   },
 929 /* macwhi $src1,$src2,$acc */
 930   {
 931     { 1, 1, 1, 1 },
 932     "macwhi-a", "macwhi", SYN (22), FMT (18), 0x3060,
 933     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 934   },
 935 /* macwlo $src1,$src2 */
 936   {
 937     { 1, 1, 1, 1 },
 938     "macwlo", "macwlo", SYN (10), FMT (10), 0x3070,
 939     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 940   },
 941 /* macwlo $src1,$src2,$acc */
 942   {
 943     { 1, 1, 1, 1 },
 944     "macwlo-a", "macwlo", SYN (22), FMT (18), 0x3070,
 945     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 946   },
 947 /* mul $dr,$sr */
 948   {
 949     { 1, 1, 1, 1 },
 950     "mul", "mul", SYN (0), FMT (0), 0x1060,
 951     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 952   },
 953 /* mulhi $src1,$src2 */
 954   {
 955     { 1, 1, 1, 1 },
 956     "mulhi", "mulhi", SYN (10), FMT (10), 0x3000,
 957     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 958   },
 959 /* mulhi $src1,$src2,$acc */
 960   {
 961     { 1, 1, 1, 1 },
 962     "mulhi-a", "mulhi", SYN (22), FMT (18), 0x3000,
 963     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 964   },
 965 /* mullo $src1,$src2 */
 966   {
 967     { 1, 1, 1, 1 },
 968     "mullo", "mullo", SYN (10), FMT (10), 0x3010,
 969     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 970   },
 971 /* mullo $src1,$src2,$acc */
 972   {
 973     { 1, 1, 1, 1 },
 974     "mullo-a", "mullo", SYN (22), FMT (18), 0x3010,
 975     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 976   },
 977 /* mulwhi $src1,$src2 */
 978   {
 979     { 1, 1, 1, 1 },
 980     "mulwhi", "mulwhi", SYN (10), FMT (10), 0x3020,
 981     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 982   },
 983 /* mulwhi $src1,$src2,$acc */
 984   {
 985     { 1, 1, 1, 1 },
 986     "mulwhi-a", "mulwhi", SYN (22), FMT (18), 0x3020,
 987     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
 988   },
 989 /* mulwlo $src1,$src2 */
 990   {
 991     { 1, 1, 1, 1 },
 992     "mulwlo", "mulwlo", SYN (10), FMT (10), 0x3030,
 993     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
 994   },
 995 /* mulwlo $src1,$src2,$acc */
 996   {
 997     { 1, 1, 1, 1 },
 998     "mulwlo-a", "mulwlo", SYN (22), FMT (18), 0x3030,
 999     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1000   },
1001 /* mv $dr,$sr */
1002   {
1003     { 1, 1, 1, 1 },
1004     "mv", "mv", SYN (0), FMT (0), 0x1080,
1005     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
1006   },
1007 /* mvfachi $dr */
1008   {
1009     { 1, 1, 1, 1 },
1010     "mvfachi", "mvfachi", SYN (23), FMT (19), 0x50f0,
1011     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
1012   },
1013 /* mvfachi $dr,$accs */
1014   {
1015     { 1, 1, 1, 1 },
1016     "mvfachi-a", "mvfachi", SYN (24), FMT (20), 0x50f0,
1017     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1018   },
1019 /* mvfaclo $dr */
1020   {
1021     { 1, 1, 1, 1 },
1022     "mvfaclo", "mvfaclo", SYN (23), FMT (19), 0x50f1,
1023     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
1024   },
1025 /* mvfaclo $dr,$acc-s */
1026   {
1027     { 1, 1, 1, 1 },
1028     "mvfaclo-a", "mvfaclo", SYN (24), FMT (20), 0x50f1,
1029     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1030   },
1031 /* mvfacmi $dr */
1032   {
1033     { 1, 1, 1, 1 },
1034     "mvfacmi", "mvfacmi", SYN (23), FMT (19), 0x50f2,
1035     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
1036   },
1037 /* mvfacmi $dr,$acc-s */
1038   {
1039     { 1, 1, 1, 1 },
1040     "mvfacmi-a", "mvfacmi", SYN (24), FMT (20), 0x50f2,
1041     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1042   },
1043 /* mvfc $dr,$scr */
1044   {
1045     { 1, 1, 1, 1 },
1046     "mvfc", "mvfc", SYN (25), FMT (21), 0x1090,
1047     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1048   },
1049 /* mvtachi $src1 */
1050   {
1051     { 1, 1, 1, 1 },
1052     "mvtachi", "mvtachi", SYN (26), FMT (22), 0x5070,
1053     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
1054   },
1055 /* mvtachi $src1,$acc-s */
1056   {
1057     { 1, 1, 1, 1 },
1058     "mvtachi-a", "mvtachi", SYN (27), FMT (23), 0x5070,
1059     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1060   },
1061 /* mvtaclo $src1 */
1062   {
1063     { 1, 1, 1, 1 },
1064     "mvtaclo", "mvtaclo", SYN (26), FMT (22), 0x5071,
1065     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
1066   },
1067 /* mvtaclo $src1,$acc-s */
1068   {
1069     { 1, 1, 1, 1 },
1070     "mvtaclo-a", "mvtaclo", SYN (27), FMT (23), 0x5071,
1071     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1072   },
1073 /* mvtc $sr,$dcr */
1074   {
1075     { 1, 1, 1, 1 },
1076     "mvtc", "mvtc", SYN (28), FMT (24), 0x10a0,
1077     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1078   },
1079 /* neg $dr,$sr */
1080   {
1081     { 1, 1, 1, 1 },
1082     "neg", "neg", SYN (0), FMT (0), 0x30,
1083     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
1084   },
1085 /* nop */
1086   {
1087     { 1, 1, 1, 1 },
1088     "nop", "nop", SYN (29), FMT (25), 0x7000,
1089     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
1090   },
1091 /* not $dr,$sr */
1092   {
1093     { 1, 1, 1, 1 },
1094     "not", "not", SYN (0), FMT (0), 0xb0,
1095     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
1096   },
1097 /* rac */
1098   {
1099     { 1, 1, 1, 1 },
1100     "rac", "rac", SYN (29), FMT (25), 0x5090,
1101     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
1102   },
1103 /* rac $acc-s */
1104   {
1105     { 1, 1, 1, 1 },
1106     "rac-a", "rac", SYN (30), FMT (26), 0x5090,
1107     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1108   },
1109 /* rach */
1110   {
1111     { 1, 1, 1, 1 },
1112     "rach", "rach", SYN (29), FMT (25), 0x5080,
1113     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S } }
1114   },
1115 /* rach $acc-s */
1116   {
1117     { 1, 1, 1, 1 },
1118     "rach-a", "rach", SYN (30), FMT (26), 0x5080,
1119     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1120   },
1121 /* rte */
1122   {
1123     { 1, 1, 1, 1 },
1124     "rte", "rte", SYN (29), FMT (25), 0x10d6,
1125     { 2, 0|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
1126   },
1127 /* seth $dr,$hi16 */
1128   {
1129     { 1, 1, 1, 1 },
1130     "seth", "seth", SYN (31), FMT (27), 0xd0c00000,
1131     { 2, 0, { 0 } }
1132   },
1133 /* sll $dr,$sr */
1134   {
1135     { 1, 1, 1, 1 },
1136     "sll", "sll", SYN (0), FMT (0), 0x1040,
1137     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1138   },
1139 /* sll3 $dr,$sr,$simm16 */
1140   {
1141     { 1, 1, 1, 1 },
1142     "sll3", "sll3", SYN (5), FMT (5), 0x90c00000,
1143     { 2, 0, { 0 } }
1144   },
1145 /* slli $dr,$uimm5 */
1146   {
1147     { 1, 1, 1, 1 },
1148     "slli", "slli", SYN (32), FMT (28), 0x5040,
1149     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1150   },
1151 /* sra $dr,$sr */
1152   {
1153     { 1, 1, 1, 1 },
1154     "sra", "sra", SYN (0), FMT (0), 0x1020,
1155     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1156   },
1157 /* sra3 $dr,$sr,$simm16 */
1158   {
1159     { 1, 1, 1, 1 },
1160     "sra3", "sra3", SYN (5), FMT (5), 0x90a00000,
1161     { 2, 0, { 0 } }
1162   },
1163 /* srai $dr,$uimm5 */
1164   {
1165     { 1, 1, 1, 1 },
1166     "srai", "srai", SYN (32), FMT (28), 0x5020,
1167     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1168   },
1169 /* srl $dr,$sr */
1170   {
1171     { 1, 1, 1, 1 },
1172     "srl", "srl", SYN (0), FMT (0), 0x1000,
1173     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1174   },
1175 /* srl3 $dr,$sr,$simm16 */
1176   {
1177     { 1, 1, 1, 1 },
1178     "srl3", "srl3", SYN (5), FMT (5), 0x90800000,
1179     { 2, 0, { 0 } }
1180   },
1181 /* srli $dr,$uimm5 */
1182   {
1183     { 1, 1, 1, 1 },
1184     "srli", "srli", SYN (32), FMT (28), 0x5000,
1185     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1186   },
1187 /* st $src1,@$src2 */
1188   {
1189     { 1, 1, 1, 1 },
1190     "st", "st", SYN (33), FMT (10), 0x2040,
1191     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1192   },
1193 /* st $src1,@($src2) */
1194   {
1195     { 1, 1, 1, 1 },
1196     "st-2", "st", SYN (34), FMT (10), 0x2040,
1197     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
1198   },
1199 /* st $src1,@($slo16,$src2) */
1200   {
1201     { 1, 1, 1, 1 },
1202     "st-d", "st", SYN (35), FMT (29), 0xa0400000,
1203     { 2, 0, { 0 } }
1204   },
1205 /* st $src1,@($src2,$slo16) */
1206   {
1207     { 1, 1, 1, 1 },
1208     "st-d2", "st", SYN (36), FMT (29), 0xa0400000,
1209     { 2, 0|A(ALIAS), { 0 } }
1210   },
1211 /* stb $src1,@$src2 */
1212   {
1213     { 1, 1, 1, 1 },
1214     "stb", "stb", SYN (33), FMT (10), 0x2000,
1215     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1216   },
1217 /* stb $src1,@($src2) */
1218   {
1219     { 1, 1, 1, 1 },
1220     "stb-2", "stb", SYN (34), FMT (10), 0x2000,
1221     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
1222   },
1223 /* stb $src1,@($slo16,$src2) */
1224   {
1225     { 1, 1, 1, 1 },
1226     "stb-d", "stb", SYN (35), FMT (29), 0xa0000000,
1227     { 2, 0, { 0 } }
1228   },
1229 /* stb $src1,@($src2,$slo16) */
1230   {
1231     { 1, 1, 1, 1 },
1232     "stb-d2", "stb", SYN (36), FMT (29), 0xa0000000,
1233     { 2, 0|A(ALIAS), { 0 } }
1234   },
1235 /* sth $src1,@$src2 */
1236   {
1237     { 1, 1, 1, 1 },
1238     "sth", "sth", SYN (33), FMT (10), 0x2020,
1239     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1240   },
1241 /* sth $src1,@($src2) */
1242   {
1243     { 1, 1, 1, 1 },
1244     "sth-2", "sth", SYN (34), FMT (10), 0x2020,
1245     { 2, 0|A(ALIAS), { [CGEN_INSN_PIPE] = PIPE_O } }
1246   },
1247 /* sth $src1,@($slo16,$src2) */
1248   {
1249     { 1, 1, 1, 1 },
1250     "sth-d", "sth", SYN (35), FMT (29), 0xa0200000,
1251     { 2, 0, { 0 } }
1252   },
1253 /* sth $src1,@($src2,$slo16) */
1254   {
1255     { 1, 1, 1, 1 },
1256     "sth-d2", "sth", SYN (36), FMT (29), 0xa0200000,
1257     { 2, 0|A(ALIAS), { 0 } }
1258   },
1259 /* st $src1,@+$src2 */
1260   {
1261     { 1, 1, 1, 1 },
1262     "st-plus", "st", SYN (37), FMT (10), 0x2060,
1263     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1264   },
1265 /* st $src1,@-$src2 */
1266   {
1267     { 1, 1, 1, 1 },
1268     "st-minus", "st", SYN (38), FMT (10), 0x2070,
1269     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1270   },
1271 /* sub $dr,$sr */
1272   {
1273     { 1, 1, 1, 1 },
1274     "sub", "sub", SYN (0), FMT (0), 0x20,
1275     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
1276   },
1277 /* subv $dr,$sr */
1278   {
1279     { 1, 1, 1, 1 },
1280     "subv", "subv", SYN (0), FMT (0), 0x0,
1281     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
1282   },
1283 /* subx $dr,$sr */
1284   {
1285     { 1, 1, 1, 1 },
1286     "subx", "subx", SYN (0), FMT (0), 0x10,
1287     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS } }
1288   },
1289 /* trap $uimm4 */
1290   {
1291     { 1, 1, 1, 1 },
1292     "trap", "trap", SYN (39), FMT (30), 0x10f0,
1293     { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { [CGEN_INSN_PIPE] = PIPE_O } }
1294   },
1295 /* unlock $src1,@$src2 */
1296   {
1297     { 1, 1, 1, 1 },
1298     "unlock", "unlock", SYN (33), FMT (10), 0x2050,
1299     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O } }
1300   },
1301 /* push $src1 */
1302   {
1303     { 1, 1, 1, 1 },
1304     "push", "push", SYN (26), FMT (22), 0x207f,
1305     { 2, 0|A(ALIAS), { 0 } }
1306   },
1307 /* pop $dr */
1308   {
1309     { 1, 1, 1, 1 },
1310     "pop", "pop", SYN (23), FMT (19), 0x20ef,
1311     { 2, 0|A(ALIAS), { 0 } }
1312   },
1313 /* satb $dr,$src2 */
1314   {
1315     { 1, 1, 1, 1 },
1316     "satb", "satb", SYN (40), FMT (31), 0x80000100,
1317     { 2, 0, { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1318   },
1319 /* sath $dr,$src2 */
1320   {
1321     { 1, 1, 1, 1 },
1322     "sath", "sath", SYN (40), FMT (31), 0x80000200,
1323     { 2, 0, { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1324   },
1325 /* sat $dr,$src2 */
1326   {
1327     { 1, 1, 1, 1 },
1328     "sat", "sat", SYN (40), FMT (31), 0x80000000,
1329     { 2, 0, { [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1330   },
1331 /* pcmpbz $src2 */
1332   {
1333     { 1, 1, 1, 1 },
1334     "pcmpbz", "pcmpbz", SYN (13), FMT (13), 0x370,
1335     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_OS, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1336   },
1337 /* sadd */
1338   {
1339     { 1, 1, 1, 1 },
1340     "sadd", "sadd", SYN (29), FMT (25), 0x50e4,
1341     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1342   },
1343 /* macwu1 $src1,$src2 */
1344   {
1345     { 1, 1, 1, 1 },
1346     "macwu1", "macwu1", SYN (10), FMT (10), 0x50b0,
1347     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1348   },
1349 /* msblo $src1,$src2 */
1350   {
1351     { 1, 1, 1, 1 },
1352     "msblo", "msblo", SYN (10), FMT (10), 0x50d0,
1353     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1354   },
1355 /* mulwu1 $src1,$src2 */
1356   {
1357     { 1, 1, 1, 1 },
1358     "mulwu1", "mulwu1", SYN (10), FMT (10), 0x50a0,
1359     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1360   },
1361 /* machl1 $src1,$src2 */
1362   {
1363     { 1, 1, 1, 1 },
1364     "machl1", "machl1", SYN (10), FMT (10), 0x50c0,
1365     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_S, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1366   },
1367 /* sc */
1368   {
1369     { 1, 1, 1, 1 },
1370     "sc", "sc", SYN (29), FMT (25), 0x7401,
1371     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1372   },
1373 /* snc */
1374   {
1375     { 1, 1, 1, 1 },
1376     "snc", "snc", SYN (29), FMT (25), 0x7501,
1377     { 2, 0, { [CGEN_INSN_PIPE] = PIPE_O, [CGEN_INSN_MACH] = 1 << MACH_M32RX } }
1378   },
1379 };
1380
1381 #undef A
1382 #undef SYN
1383 #undef FMT
1384
1385 CGEN_INSN_TABLE m32r_cgen_insn_table = {
1386   & m32r_cgen_insn_table_entries[0],
1387   sizeof (CGEN_INSN),
1388   CGEN_NUM_INSNS,
1389   NULL,
1390   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
1391   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
1392 };
1393
1394 /* The hash functions are recorded here to help keep assembler code out of
1395    the disassembler and vice versa.  */
1396
1397 unsigned int
1398 m32r_cgen_asm_hash_insn (insn)
1399      const char *insn;
1400 {
1401   return CGEN_ASM_HASH (insn);
1402 }
1403
1404 unsigned int
1405 m32r_cgen_dis_hash_insn (buf, value)
1406      const char *buf;
1407      unsigned long value;
1408 {
1409   return CGEN_DIS_HASH (buf, value);
1410 }
1411
1412 CGEN_OPCODE_DATA m32r_cgen_opcode_data = {
1413   & m32r_cgen_hw_entries[0],
1414   & m32r_cgen_insn_table,
1415 };
1416
1417 void
1418 m32r_cgen_init_tables (mach)
1419     int mach;
1420 {
1421 }
1422
1423 /* Main entry point for stuffing values in cgen_fields.  */
1424
1425 CGEN_INLINE void
1426 m32r_cgen_set_operand (opindex, valuep, fields)
1427      int opindex;
1428      const long *valuep;
1429      CGEN_FIELDS *fields;
1430 {
1431   switch (opindex)
1432     {
1433     case M32R_OPERAND_SR :
1434       fields->f_r2 = *valuep;
1435       break;
1436     case M32R_OPERAND_DR :
1437       fields->f_r1 = *valuep;
1438       break;
1439     case M32R_OPERAND_SRC1 :
1440       fields->f_r1 = *valuep;
1441       break;
1442     case M32R_OPERAND_SRC2 :
1443       fields->f_r2 = *valuep;
1444       break;
1445     case M32R_OPERAND_SCR :
1446       fields->f_r2 = *valuep;
1447       break;
1448     case M32R_OPERAND_DCR :
1449       fields->f_r1 = *valuep;
1450       break;
1451     case M32R_OPERAND_SIMM8 :
1452       fields->f_simm8 = *valuep;
1453       break;
1454     case M32R_OPERAND_SIMM16 :
1455       fields->f_simm16 = *valuep;
1456       break;
1457     case M32R_OPERAND_UIMM4 :
1458       fields->f_uimm4 = *valuep;
1459       break;
1460     case M32R_OPERAND_UIMM5 :
1461       fields->f_uimm5 = *valuep;
1462       break;
1463     case M32R_OPERAND_UIMM16 :
1464       fields->f_uimm16 = *valuep;
1465       break;
1466     case M32R_OPERAND_ACC_S :
1467       fields->f_acc_s = *valuep;
1468       break;
1469     case M32R_OPERAND_ACC :
1470       fields->f_acc = *valuep;
1471       break;
1472     case M32R_OPERAND_HI16 :
1473       fields->f_hi16 = *valuep;
1474       break;
1475     case M32R_OPERAND_SLO16 :
1476       fields->f_simm16 = *valuep;
1477       break;
1478     case M32R_OPERAND_ULO16 :
1479       fields->f_uimm16 = *valuep;
1480       break;
1481     case M32R_OPERAND_UIMM24 :
1482       fields->f_uimm24 = *valuep;
1483       break;
1484     case M32R_OPERAND_DISP8 :
1485       fields->f_disp8 = *valuep;
1486       break;
1487     case M32R_OPERAND_DISP16 :
1488       fields->f_disp16 = *valuep;
1489       break;
1490     case M32R_OPERAND_DISP24 :
1491       fields->f_disp24 = *valuep;
1492       break;
1493
1494     default :
1495       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
1496                        opindex);
1497       abort ();
1498   }
1499 }
1500
1501 /* Main entry point for getting values from cgen_fields.  */
1502
1503 CGEN_INLINE long
1504 m32r_cgen_get_operand (opindex, fields)
1505      int opindex;
1506      const CGEN_FIELDS *fields;
1507 {
1508   long value;
1509
1510   switch (opindex)
1511     {
1512     case M32R_OPERAND_SR :
1513       value = fields->f_r2;
1514       break;
1515     case M32R_OPERAND_DR :
1516       value = fields->f_r1;
1517       break;
1518     case M32R_OPERAND_SRC1 :
1519       value = fields->f_r1;
1520       break;
1521     case M32R_OPERAND_SRC2 :
1522       value = fields->f_r2;
1523       break;
1524     case M32R_OPERAND_SCR :
1525       value = fields->f_r2;
1526       break;
1527     case M32R_OPERAND_DCR :
1528       value = fields->f_r1;
1529       break;
1530     case M32R_OPERAND_SIMM8 :
1531       value = fields->f_simm8;
1532       break;
1533     case M32R_OPERAND_SIMM16 :
1534       value = fields->f_simm16;
1535       break;
1536     case M32R_OPERAND_UIMM4 :
1537       value = fields->f_uimm4;
1538       break;
1539     case M32R_OPERAND_UIMM5 :
1540       value = fields->f_uimm5;
1541       break;
1542     case M32R_OPERAND_UIMM16 :
1543       value = fields->f_uimm16;
1544       break;
1545     case M32R_OPERAND_ACC_S :
1546       value = fields->f_acc_s;
1547       break;
1548     case M32R_OPERAND_ACC :
1549       value = fields->f_acc;
1550       break;
1551     case M32R_OPERAND_HI16 :
1552       value = fields->f_hi16;
1553       break;
1554     case M32R_OPERAND_SLO16 :
1555       value = fields->f_simm16;
1556       break;
1557     case M32R_OPERAND_ULO16 :
1558       value = fields->f_uimm16;
1559       break;
1560     case M32R_OPERAND_UIMM24 :
1561       value = fields->f_uimm24;
1562       break;
1563     case M32R_OPERAND_DISP8 :
1564       value = fields->f_disp8;
1565       break;
1566     case M32R_OPERAND_DISP16 :
1567       value = fields->f_disp16;
1568       break;
1569     case M32R_OPERAND_DISP24 :
1570       value = fields->f_disp24;
1571       break;
1572
1573     default :
1574       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
1575                        opindex);
1576       abort ();
1577   }
1578
1579   return value;
1580 }
1581