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* cgen-asm.in (insert_normal): Use CGEN_BOOL_ATTR.
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE m32r-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "m32r-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 m32r_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 m32r_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 m32r_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY bool_attr[] =
206 {
207 { "#f", 0 },
208 { "#t", 1 },
209 { 0, 0 }
210 };
211
212 static const CGEN_ATTR_ENTRY MACH_attr[] =
213 {
214 { "base", MACH_BASE },
215 { "m32r", MACH_M32R },
216 /* start-sanitize-m32rx */
217 { "m32rx", MACH_M32RX },
218 /* end-sanitize-m32rx */
219 { "max", MACH_MAX },
220 { 0, 0 }
221 };
222
223 /* start-sanitize-m32rx */
224 static const CGEN_ATTR_ENTRY PIPE_attr[] =
225 {
226 { "NONE", PIPE_NONE },
227 { "O", PIPE_O },
228 { "S", PIPE_S },
229 { "OS", PIPE_OS },
230 { 0, 0 }
231 };
232
233 /* end-sanitize-m32rx */
234 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
235 {
236 { "MACH", & MACH_attr[0] },
237 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
238 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
239 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
240 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
241 { "RESERVED", &bool_attr[0], &bool_attr[0] },
242 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
243 { "RELOC", &bool_attr[0], &bool_attr[0] },
244 { 0, 0, 0 }
245 };
246
247 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
248 {
249 { "MACH", & MACH_attr[0] },
250 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
251 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
252 { "SIGNED", &bool_attr[0], &bool_attr[0] },
253 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
254 { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
255 { "PC", &bool_attr[0], &bool_attr[0] },
256 { "PROFILE", &bool_attr[0], &bool_attr[0] },
257 { 0, 0, 0 }
258 };
259
260 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
261 {
262 { "MACH", & MACH_attr[0] },
263 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
264 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
265 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
266 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
267 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
268 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
269 { "RELAX", &bool_attr[0], &bool_attr[0] },
270 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
271 { "RELOC", &bool_attr[0], &bool_attr[0] },
272 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
273 { 0, 0, 0 }
274 };
275
276 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
277 {
278 { "MACH", & MACH_attr[0] },
279 /* start-sanitize-m32rx */
280 { "PIPE", & PIPE_attr[0] },
281 /* end-sanitize-m32rx */
282 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
283 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
284 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
285 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
286 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
287 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
288 { "RELAX", &bool_attr[0], &bool_attr[0] },
289 { "ALIAS", &bool_attr[0], &bool_attr[0] },
290 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
291 { "PBB", &bool_attr[0], &bool_attr[0] },
292 { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
293 /* start-sanitize-m32rx */
294 { "SPECIAL", &bool_attr[0], &bool_attr[0] },
295 /* end-sanitize-m32rx */
296 { 0, 0, 0 }
297 };
298
299 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
300 {
301 { "fp", 13 },
302 { "lr", 14 },
303 { "sp", 15 },
304 { "r0", 0 },
305 { "r1", 1 },
306 { "r2", 2 },
307 { "r3", 3 },
308 { "r4", 4 },
309 { "r5", 5 },
310 { "r6", 6 },
311 { "r7", 7 },
312 { "r8", 8 },
313 { "r9", 9 },
314 { "r10", 10 },
315 { "r11", 11 },
316 { "r12", 12 },
317 { "r13", 13 },
318 { "r14", 14 },
319 { "r15", 15 }
320 };
321
322 CGEN_KEYWORD m32r_cgen_opval_h_gr =
323 {
324 & m32r_cgen_opval_h_gr_entries[0],
325 19
326 };
327
328 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
329 {
330 { "psw", 0 },
331 { "cbr", 1 },
332 { "spi", 2 },
333 { "spu", 3 },
334 { "bpc", 6 },
335 { "bbpsw", 8 },
336 { "bbpc", 14 },
337 { "cr0", 0 },
338 { "cr1", 1 },
339 { "cr2", 2 },
340 { "cr3", 3 },
341 { "cr4", 4 },
342 { "cr5", 5 },
343 { "cr6", 6 },
344 { "cr7", 7 },
345 { "cr8", 8 },
346 { "cr9", 9 },
347 { "cr10", 10 },
348 { "cr11", 11 },
349 { "cr12", 12 },
350 { "cr13", 13 },
351 { "cr14", 14 },
352 { "cr15", 15 }
353 };
354
355 CGEN_KEYWORD m32r_cgen_opval_h_cr =
356 {
357 & m32r_cgen_opval_h_cr_entries[0],
358 23
359 };
360
361 /* start-sanitize-m32rx */
362 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
363 {
364 { "a0", 0 },
365 { "a1", 1 }
366 };
367
368 CGEN_KEYWORD m32r_cgen_opval_h_accums =
369 {
370 & m32r_cgen_opval_h_accums_entries[0],
371 2
372 };
373
374 /* end-sanitize-m32rx */
375
376 /* The hardware table. */
377
378 #define HW_ENT(n) m32r_cgen_hw_entries[n]
379 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
380 {
381 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
382 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
383 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
384 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
385 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
386 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
387 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
388 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
389 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
390 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
391 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
392 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
393 /* start-sanitize-m32rx */
394 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_M32RX) } } },
395 /* end-sanitize-m32rx */
396 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
397 { HW_H_PSW, & HW_ENT (HW_H_PSW + 1), "h-psw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
398 { HW_H_BPSW, & HW_ENT (HW_H_BPSW + 1), "h-bpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
399 { HW_H_BBPSW, & HW_ENT (HW_H_BBPSW + 1), "h-bbpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
400 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
401 { 0 }
402 };
403
404 /* The instruction field table. */
405
406 static const CGEN_IFLD m32r_cgen_ifld_table[] =
407 {
408 { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
409 { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
410 { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
411 { M32R_F_COND, "f-cond", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
412 { M32R_F_R1, "f-r1", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
413 { M32R_F_R2, "f-r2", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
414 { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
415 { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
416 { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
417 { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
418 { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
419 { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
420 { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
421 { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
422 { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
423 { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
424 { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
425 /* start-sanitize-m32rx */
426 { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
427 /* end-sanitize-m32rx */
428 /* start-sanitize-m32rx */
429 { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
430 /* end-sanitize-m32rx */
431 /* start-sanitize-m32rx */
432 { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
433 /* end-sanitize-m32rx */
434 /* start-sanitize-m32rx */
435 { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
436 /* end-sanitize-m32rx */
437 /* start-sanitize-m32rx */
438 { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
439 /* end-sanitize-m32rx */
440 /* start-sanitize-m32rx */
441 { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
442 /* end-sanitize-m32rx */
443 /* start-sanitize-m32rx */
444 { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
445 /* end-sanitize-m32rx */
446 /* start-sanitize-m32rx */
447 { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
448 /* end-sanitize-m32rx */
449 { 0 }
450 };
451
452 /* The operand table. */
453
454 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
455 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
456
457 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
458 {
459 /* pc: program counter */
460 { "pc", & HW_ENT (HW_H_PC), 0, 0,
461 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
462 /* sr: source register */
463 { "sr", & HW_ENT (HW_H_GR), 12, 4,
464 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
465 /* dr: destination register */
466 { "dr", & HW_ENT (HW_H_GR), 4, 4,
467 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
468 /* src1: source register 1 */
469 { "src1", & HW_ENT (HW_H_GR), 4, 4,
470 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
471 /* src2: source register 2 */
472 { "src2", & HW_ENT (HW_H_GR), 12, 4,
473 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
474 /* scr: source control register */
475 { "scr", & HW_ENT (HW_H_CR), 12, 4,
476 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
477 /* dcr: destination control register */
478 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
479 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
480 /* simm8: 8 bit signed immediate */
481 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
482 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
483 /* simm16: 16 bit signed immediate */
484 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
485 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
486 /* uimm4: 4 bit trap number */
487 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
488 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
489 /* uimm5: 5 bit shift count */
490 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
491 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
492 /* uimm16: 16 bit unsigned immediate */
493 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
494 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
495 /* start-sanitize-m32rx */
496 /* imm1: 1 bit immediate */
497 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
498 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
499 /* end-sanitize-m32rx */
500 /* start-sanitize-m32rx */
501 /* accd: accumulator destination register */
502 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
503 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
504 /* end-sanitize-m32rx */
505 /* start-sanitize-m32rx */
506 /* accs: accumulator source register */
507 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
508 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
509 /* end-sanitize-m32rx */
510 /* start-sanitize-m32rx */
511 /* acc: accumulator reg (d) */
512 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
513 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
514 /* end-sanitize-m32rx */
515 /* hash: # prefix */
516 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
517 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
518 /* hi16: high 16 bit immediate, sign optional */
519 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
520 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
521 /* slo16: 16 bit signed immediate, for low() */
522 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
523 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
524 /* ulo16: 16 bit unsigned immediate, for low() */
525 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
526 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
527 /* uimm24: 24 bit address */
528 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
529 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
530 /* disp8: 8 bit displacement */
531 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
532 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
533 /* disp16: 16 bit displacement */
534 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
535 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
536 /* disp24: 24 bit displacement */
537 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
538 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
539 /* condbit: condition bit */
540 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
541 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
542 /* accum: accumulator */
543 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
544 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
545 };
546
547 /* Operand references. */
548
549 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
550 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
551 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
552
553 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
554 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
555 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
556 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
557 { 0 }
558 };
559
560 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
561 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
562 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
563 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
564 { 0 }
565 };
566
567 static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
568 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
569 { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0, 0 },
570 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
571 { 0 }
572 };
573
574 static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
575 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
576 { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0, 0 },
577 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
578 { 0 }
579 };
580
581 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
582 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
583 { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 },
584 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
585 { 0 }
586 };
587
588 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
589 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
590 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
591 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
592 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
593 { 0 }
594 };
595
596 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
597 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
598 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
599 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
600 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
601 { 0 }
602 };
603
604 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
605 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
606 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
607 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
608 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
609 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
610 { 0 }
611 };
612
613 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
614 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
615 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF },
616 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
617 { 0 }
618 };
619
620 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
621 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
622 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF },
623 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
624 { 0 }
625 };
626
627 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
628 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
629 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
630 { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
631 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
632 { 0 }
633 };
634
635 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
636 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
637 { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
638 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
639 { 0 }
640 };
641
642 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
643 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
644 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 },
645 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
646 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
647 { 0 }
648 };
649
650 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
651 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
652 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 },
653 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
654 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
655 { 0 }
656 };
657
658 /* start-sanitize-m32rx */
659 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
660 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
661 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
662 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF },
663 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
664 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
665 { 0 }
666 };
667
668 /* end-sanitize-m32rx */
669 /* start-sanitize-m32rx */
670 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
671 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
672 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
673 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF },
674 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
675 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
676 { 0 }
677 };
678
679 /* end-sanitize-m32rx */
680 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
681 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 },
682 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
683 { 0 }
684 };
685
686 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
687 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 },
688 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
689 { 0 }
690 };
691
692 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
693 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
694 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
695 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
696 { 0 }
697 };
698
699 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
700 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
701 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
702 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
703 { 0 }
704 };
705
706 /* start-sanitize-m32rx */
707 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
708 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
709 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
710 { 0 }
711 };
712
713 /* end-sanitize-m32rx */
714 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
715 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
716 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
717 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
718 { 0 }
719 };
720
721 /* start-sanitize-m32rx */
722 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
723 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
724 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF },
725 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
726 { 0 }
727 };
728
729 /* end-sanitize-m32rx */
730 static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
731 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
732 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
733 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
734 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
735 { 0 }
736 };
737
738 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
739 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
740 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
741 { 0 }
742 };
743
744 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
745 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
746 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
747 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
748 { 0 }
749 };
750
751 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
752 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
753 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
754 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
755 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
756 { 0 }
757 };
758
759 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
760 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
761 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
762 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
763 { 0 }
764 };
765
766 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
767 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
768 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
769 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
770 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
771 { 0 }
772 };
773
774 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
775 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
776 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
777 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
778 { 0 }
779 };
780
781 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
782 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
783 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
784 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
785 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
786 { 0 }
787 };
788
789 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
790 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
791 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
792 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
793 { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
794 { 0 }
795 };
796
797 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
798 { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0, 0 },
799 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
800 { 0 }
801 };
802
803 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
804 { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 },
805 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
806 { 0 }
807 };
808
809 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
810 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
811 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
812 { 0 }
813 };
814
815 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
816 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
817 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
818 { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
819 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
820 { 0 }
821 };
822
823 static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
824 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
825 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
826 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
827 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
828 { 0 }
829 };
830
831 /* start-sanitize-m32rx */
832 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
833 { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
834 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
835 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
836 { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
837 { 0 }
838 };
839
840 /* end-sanitize-m32rx */
841 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
842 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
843 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
844 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
845 { 0 }
846 };
847
848 /* start-sanitize-m32rx */
849 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
850 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
851 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
852 { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
853 { 0 }
854 };
855
856 /* end-sanitize-m32rx */
857 static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
858 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
859 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
860 { 0 }
861 };
862
863 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
864 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
865 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
866 { 0 }
867 };
868
869 /* start-sanitize-m32rx */
870 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
871 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
872 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
873 { 0 }
874 };
875
876 /* end-sanitize-m32rx */
877 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
878 { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0, 0 },
879 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
880 { 0 }
881 };
882
883 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
884 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
885 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
886 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
887 { 0 }
888 };
889
890 /* start-sanitize-m32rx */
891 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
892 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
893 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
894 { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
895 { 0 }
896 };
897
898 /* end-sanitize-m32rx */
899 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
900 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
901 { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0, 0 },
902 { 0 }
903 };
904
905 static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
906 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
907 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
908 { 0 }
909 };
910
911 /* start-sanitize-m32rx */
912 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
913 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
914 { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0, 0 },
915 { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0, 0 },
916 { 0 }
917 };
918
919 /* end-sanitize-m32rx */
920 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
921 { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
922 { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
923 { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
924 { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
925 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
926 { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
927 { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
928 { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
929 { 0 }
930 };
931
932 static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
933 { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0, 0 },
934 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
935 { 0 }
936 };
937
938 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
939 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
940 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
941 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
942 { 0 }
943 };
944
945 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
946 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
947 { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0, 0 },
948 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
949 { 0 }
950 };
951
952 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
953 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
954 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
955 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
956 { 0 }
957 };
958
959 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
960 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
961 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
962 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
963 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
964 { 0 }
965 };
966
967 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
968 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
969 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
970 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
971 { 0 }
972 };
973
974 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
975 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
976 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
977 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
978 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
979 { 0 }
980 };
981
982 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
983 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
984 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
985 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
986 { 0 }
987 };
988
989 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
990 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
991 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
992 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
993 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
994 { 0 }
995 };
996
997 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
998 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
999 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1000 { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
1001 { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
1002 { 0 }
1003 };
1004
1005 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
1006 { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
1007 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
1008 { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
1009 { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
1010 { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0, 0 },
1011 { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
1012 { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
1013 { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
1014 { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
1015 { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
1016 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
1017 { 0 }
1018 };
1019
1020 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
1021 { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
1022 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF },
1023 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, COND_REF },
1024 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
1025 { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
1026 { 0 }
1027 };
1028
1029 /* start-sanitize-m32rx */
1030 static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
1031 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
1032 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
1033 { 0 }
1034 };
1035
1036 /* end-sanitize-m32rx */
1037 /* start-sanitize-m32rx */
1038 static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
1039 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
1040 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF },
1041 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
1042 { 0 }
1043 };
1044
1045 /* end-sanitize-m32rx */
1046 /* start-sanitize-m32rx */
1047 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
1048 { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
1049 { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
1050 { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
1051 { 0 }
1052 };
1053
1054 /* end-sanitize-m32rx */
1055 /* start-sanitize-m32rx */
1056 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
1057 { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
1058 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1059 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
1060 { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
1061 { 0 }
1062 };
1063
1064 /* end-sanitize-m32rx */
1065 /* start-sanitize-m32rx */
1066 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
1067 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
1068 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
1069 { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
1070 { 0 }
1071 };
1072
1073 /* end-sanitize-m32rx */
1074 /* start-sanitize-m32rx */
1075 static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
1076 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
1077 { 0 }
1078 };
1079
1080 /* end-sanitize-m32rx */
1081 #undef INPUT
1082 #undef OUTPUT
1083 #undef COND_REF
1084
1085 /* Instruction formats. */
1086
1087 #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
1088
1089 static const CGEN_IFMT fmt_empty = {
1090 0, 0, 0x0, { 0 }
1091 };
1092
1093 static const CGEN_IFMT fmt_add = {
1094 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1095 };
1096
1097 static const CGEN_IFMT fmt_add3 = {
1098 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1099 };
1100
1101 static const CGEN_IFMT fmt_and3 = {
1102 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1103 };
1104
1105 static const CGEN_IFMT fmt_or3 = {
1106 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1107 };
1108
1109 static const CGEN_IFMT fmt_addi = {
1110 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
1111 };
1112
1113 static const CGEN_IFMT fmt_addv = {
1114 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1115 };
1116
1117 static const CGEN_IFMT fmt_addv3 = {
1118 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1119 };
1120
1121 static const CGEN_IFMT fmt_addx = {
1122 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1123 };
1124
1125 static const CGEN_IFMT fmt_bc8 = {
1126 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1127 };
1128
1129 static const CGEN_IFMT fmt_bc24 = {
1130 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1131 };
1132
1133 static const CGEN_IFMT fmt_beq = {
1134 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
1135 };
1136
1137 static const CGEN_IFMT fmt_beqz = {
1138 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
1139 };
1140
1141 static const CGEN_IFMT fmt_bl8 = {
1142 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1143 };
1144
1145 static const CGEN_IFMT fmt_bl24 = {
1146 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1147 };
1148
1149 /* start-sanitize-m32rx */
1150 static const CGEN_IFMT fmt_bcl8 = {
1151 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1152 };
1153
1154 /* end-sanitize-m32rx */
1155 /* start-sanitize-m32rx */
1156 static const CGEN_IFMT fmt_bcl24 = {
1157 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1158 };
1159
1160 /* end-sanitize-m32rx */
1161 static const CGEN_IFMT fmt_bra8 = {
1162 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
1163 };
1164
1165 static const CGEN_IFMT fmt_bra24 = {
1166 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
1167 };
1168
1169 static const CGEN_IFMT fmt_cmp = {
1170 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1171 };
1172
1173 static const CGEN_IFMT fmt_cmpi = {
1174 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1175 };
1176
1177 /* start-sanitize-m32rx */
1178 static const CGEN_IFMT fmt_cmpz = {
1179 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1180 };
1181
1182 /* end-sanitize-m32rx */
1183 static const CGEN_IFMT fmt_div = {
1184 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1185 };
1186
1187 /* start-sanitize-m32rx */
1188 static const CGEN_IFMT fmt_jc = {
1189 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1190 };
1191
1192 /* end-sanitize-m32rx */
1193 static const CGEN_IFMT fmt_jl = {
1194 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1195 };
1196
1197 static const CGEN_IFMT fmt_jmp = {
1198 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1199 };
1200
1201 static const CGEN_IFMT fmt_ld = {
1202 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1203 };
1204
1205 static const CGEN_IFMT fmt_ld_d = {
1206 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1207 };
1208
1209 static const CGEN_IFMT fmt_ldb = {
1210 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1211 };
1212
1213 static const CGEN_IFMT fmt_ldb_d = {
1214 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1215 };
1216
1217 static const CGEN_IFMT fmt_ldh = {
1218 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1219 };
1220
1221 static const CGEN_IFMT fmt_ldh_d = {
1222 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1223 };
1224
1225 static const CGEN_IFMT fmt_ld_plus = {
1226 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1227 };
1228
1229 static const CGEN_IFMT fmt_ld24 = {
1230 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 }
1231 };
1232
1233 static const CGEN_IFMT fmt_ldi8 = {
1234 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
1235 };
1236
1237 static const CGEN_IFMT fmt_ldi16 = {
1238 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1239 };
1240
1241 static const CGEN_IFMT fmt_lock = {
1242 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1243 };
1244
1245 static const CGEN_IFMT fmt_machi = {
1246 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1247 };
1248
1249 /* start-sanitize-m32rx */
1250 static const CGEN_IFMT fmt_machi_a = {
1251 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
1252 };
1253
1254 /* end-sanitize-m32rx */
1255 static const CGEN_IFMT fmt_mulhi = {
1256 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1257 };
1258
1259 /* start-sanitize-m32rx */
1260 static const CGEN_IFMT fmt_mulhi_a = {
1261 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
1262 };
1263
1264 /* end-sanitize-m32rx */
1265 static const CGEN_IFMT fmt_mv = {
1266 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1267 };
1268
1269 static const CGEN_IFMT fmt_mvfachi = {
1270 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1271 };
1272
1273 /* start-sanitize-m32rx */
1274 static const CGEN_IFMT fmt_mvfachi_a = {
1275 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
1276 };
1277
1278 /* end-sanitize-m32rx */
1279 static const CGEN_IFMT fmt_mvfc = {
1280 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1281 };
1282
1283 static const CGEN_IFMT fmt_mvtachi = {
1284 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1285 };
1286
1287 /* start-sanitize-m32rx */
1288 static const CGEN_IFMT fmt_mvtachi_a = {
1289 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
1290 };
1291
1292 /* end-sanitize-m32rx */
1293 static const CGEN_IFMT fmt_mvtc = {
1294 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1295 };
1296
1297 static const CGEN_IFMT fmt_nop = {
1298 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1299 };
1300
1301 static const CGEN_IFMT fmt_rac = {
1302 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1303 };
1304
1305 /* start-sanitize-m32rx */
1306 static const CGEN_IFMT fmt_rac_dsi = {
1307 16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
1308 };
1309
1310 /* end-sanitize-m32rx */
1311 static const CGEN_IFMT fmt_rte = {
1312 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1313 };
1314
1315 static const CGEN_IFMT fmt_seth = {
1316 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 }
1317 };
1318
1319 static const CGEN_IFMT fmt_sll3 = {
1320 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1321 };
1322
1323 static const CGEN_IFMT fmt_slli = {
1324 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 }
1325 };
1326
1327 static const CGEN_IFMT fmt_st = {
1328 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1329 };
1330
1331 static const CGEN_IFMT fmt_st_d = {
1332 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1333 };
1334
1335 static const CGEN_IFMT fmt_stb = {
1336 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1337 };
1338
1339 static const CGEN_IFMT fmt_stb_d = {
1340 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1341 };
1342
1343 static const CGEN_IFMT fmt_sth = {
1344 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1345 };
1346
1347 static const CGEN_IFMT fmt_sth_d = {
1348 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
1349 };
1350
1351 static const CGEN_IFMT fmt_st_plus = {
1352 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1353 };
1354
1355 static const CGEN_IFMT fmt_trap = {
1356 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 }
1357 };
1358
1359 static const CGEN_IFMT fmt_unlock = {
1360 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1361 };
1362
1363 /* start-sanitize-m32rx */
1364 static const CGEN_IFMT fmt_satb = {
1365 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1366 };
1367
1368 /* end-sanitize-m32rx */
1369 /* start-sanitize-m32rx */
1370 static const CGEN_IFMT fmt_sat = {
1371 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
1372 };
1373
1374 /* end-sanitize-m32rx */
1375 /* start-sanitize-m32rx */
1376 static const CGEN_IFMT fmt_sadd = {
1377 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1378 };
1379
1380 /* end-sanitize-m32rx */
1381 /* start-sanitize-m32rx */
1382 static const CGEN_IFMT fmt_macwu1 = {
1383 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1384 };
1385
1386 /* end-sanitize-m32rx */
1387 /* start-sanitize-m32rx */
1388 static const CGEN_IFMT fmt_mulwu1 = {
1389 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1390 };
1391
1392 /* end-sanitize-m32rx */
1393 /* start-sanitize-m32rx */
1394 static const CGEN_IFMT fmt_sc = {
1395 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
1396 };
1397
1398 /* end-sanitize-m32rx */
1399 #undef F
1400
1401 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1402 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1403 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1404
1405 /* The instruction table.
1406 This is currently non-static because the simulator accesses it
1407 directly. */
1408
1409 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1410 {
1411 /* Special null first entry.
1412 A `num' value of zero is thus invalid.
1413 Also, the special `invalid' insn resides here. */
1414 { { 0 }, 0 },
1415 /* add $dr,$sr */
1416 {
1417 { 1, 1, 1, 1 },
1418 M32R_INSN_ADD, "add", "add",
1419 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1420 & fmt_add, { 0xa0 },
1421 (PTR) & fmt_add_ops[0],
1422 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1423 },
1424 /* add3 $dr,$sr,$hash$slo16 */
1425 {
1426 { 1, 1, 1, 1 },
1427 M32R_INSN_ADD3, "add3", "add3",
1428 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
1429 & fmt_add3, { 0x80a00000 },
1430 (PTR) & fmt_add3_ops[0],
1431 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1432 },
1433 /* and $dr,$sr */
1434 {
1435 { 1, 1, 1, 1 },
1436 M32R_INSN_AND, "and", "and",
1437 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1438 & fmt_add, { 0xc0 },
1439 (PTR) & fmt_add_ops[0],
1440 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1441 },
1442 /* and3 $dr,$sr,$uimm16 */
1443 {
1444 { 1, 1, 1, 1 },
1445 M32R_INSN_AND3, "and3", "and3",
1446 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1447 & fmt_and3, { 0x80c00000 },
1448 (PTR) & fmt_and3_ops[0],
1449 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1450 },
1451 /* or $dr,$sr */
1452 {
1453 { 1, 1, 1, 1 },
1454 M32R_INSN_OR, "or", "or",
1455 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1456 & fmt_add, { 0xe0 },
1457 (PTR) & fmt_add_ops[0],
1458 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1459 },
1460 /* or3 $dr,$sr,$hash$ulo16 */
1461 {
1462 { 1, 1, 1, 1 },
1463 M32R_INSN_OR3, "or3", "or3",
1464 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
1465 & fmt_or3, { 0x80e00000 },
1466 (PTR) & fmt_or3_ops[0],
1467 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1468 },
1469 /* xor $dr,$sr */
1470 {
1471 { 1, 1, 1, 1 },
1472 M32R_INSN_XOR, "xor", "xor",
1473 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1474 & fmt_add, { 0xd0 },
1475 (PTR) & fmt_add_ops[0],
1476 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1477 },
1478 /* xor3 $dr,$sr,$uimm16 */
1479 {
1480 { 1, 1, 1, 1 },
1481 M32R_INSN_XOR3, "xor3", "xor3",
1482 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1483 & fmt_and3, { 0x80d00000 },
1484 (PTR) & fmt_and3_ops[0],
1485 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1486 },
1487 /* addi $dr,$simm8 */
1488 {
1489 { 1, 1, 1, 1 },
1490 M32R_INSN_ADDI, "addi", "addi",
1491 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1492 & fmt_addi, { 0x4000 },
1493 (PTR) & fmt_addi_ops[0],
1494 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1495 },
1496 /* addv $dr,$sr */
1497 {
1498 { 1, 1, 1, 1 },
1499 M32R_INSN_ADDV, "addv", "addv",
1500 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1501 & fmt_addv, { 0x80 },
1502 (PTR) & fmt_addv_ops[0],
1503 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1504 },
1505 /* addv3 $dr,$sr,$simm16 */
1506 {
1507 { 1, 1, 1, 1 },
1508 M32R_INSN_ADDV3, "addv3", "addv3",
1509 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
1510 & fmt_addv3, { 0x80800000 },
1511 (PTR) & fmt_addv3_ops[0],
1512 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1513 },
1514 /* addx $dr,$sr */
1515 {
1516 { 1, 1, 1, 1 },
1517 M32R_INSN_ADDX, "addx", "addx",
1518 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1519 & fmt_addx, { 0x90 },
1520 (PTR) & fmt_addx_ops[0],
1521 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1522 },
1523 /* bc.s $disp8 */
1524 {
1525 { 1, 1, 1, 1 },
1526 M32R_INSN_BC8, "bc8", "bc.s",
1527 { { MNEM, ' ', OP (DISP8), 0 } },
1528 & fmt_bc8, { 0x7c00 },
1529 (PTR) & fmt_bc8_ops[0],
1530 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
1531 },
1532 /* bc.l $disp24 */
1533 {
1534 { 1, 1, 1, 1 },
1535 M32R_INSN_BC24, "bc24", "bc.l",
1536 { { MNEM, ' ', OP (DISP24), 0 } },
1537 & fmt_bc24, { 0xfc000000 },
1538 (PTR) & fmt_bc24_ops[0],
1539 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1540 },
1541 /* beq $src1,$src2,$disp16 */
1542 {
1543 { 1, 1, 1, 1 },
1544 M32R_INSN_BEQ, "beq", "beq",
1545 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1546 & fmt_beq, { 0xb0000000 },
1547 (PTR) & fmt_beq_ops[0],
1548 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1549 },
1550 /* beqz $src2,$disp16 */
1551 {
1552 { 1, 1, 1, 1 },
1553 M32R_INSN_BEQZ, "beqz", "beqz",
1554 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1555 & fmt_beqz, { 0xb0800000 },
1556 (PTR) & fmt_beqz_ops[0],
1557 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1558 },
1559 /* bgez $src2,$disp16 */
1560 {
1561 { 1, 1, 1, 1 },
1562 M32R_INSN_BGEZ, "bgez", "bgez",
1563 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1564 & fmt_beqz, { 0xb0b00000 },
1565 (PTR) & fmt_beqz_ops[0],
1566 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1567 },
1568 /* bgtz $src2,$disp16 */
1569 {
1570 { 1, 1, 1, 1 },
1571 M32R_INSN_BGTZ, "bgtz", "bgtz",
1572 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1573 & fmt_beqz, { 0xb0d00000 },
1574 (PTR) & fmt_beqz_ops[0],
1575 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1576 },
1577 /* blez $src2,$disp16 */
1578 {
1579 { 1, 1, 1, 1 },
1580 M32R_INSN_BLEZ, "blez", "blez",
1581 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1582 & fmt_beqz, { 0xb0c00000 },
1583 (PTR) & fmt_beqz_ops[0],
1584 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1585 },
1586 /* bltz $src2,$disp16 */
1587 {
1588 { 1, 1, 1, 1 },
1589 M32R_INSN_BLTZ, "bltz", "bltz",
1590 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1591 & fmt_beqz, { 0xb0a00000 },
1592 (PTR) & fmt_beqz_ops[0],
1593 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1594 },
1595 /* bnez $src2,$disp16 */
1596 {
1597 { 1, 1, 1, 1 },
1598 M32R_INSN_BNEZ, "bnez", "bnez",
1599 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1600 & fmt_beqz, { 0xb0900000 },
1601 (PTR) & fmt_beqz_ops[0],
1602 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1603 },
1604 /* bl.s $disp8 */
1605 {
1606 { 1, 1, 1, 1 },
1607 M32R_INSN_BL8, "bl8", "bl.s",
1608 { { MNEM, ' ', OP (DISP8), 0 } },
1609 & fmt_bl8, { 0x7e00 },
1610 (PTR) & fmt_bl8_ops[0],
1611 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1612 },
1613 /* bl.l $disp24 */
1614 {
1615 { 1, 1, 1, 1 },
1616 M32R_INSN_BL24, "bl24", "bl.l",
1617 { { MNEM, ' ', OP (DISP24), 0 } },
1618 & fmt_bl24, { 0xfe000000 },
1619 (PTR) & fmt_bl24_ops[0],
1620 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1621 },
1622 /* start-sanitize-m32rx */
1623 /* bcl.s $disp8 */
1624 {
1625 { 1, 1, 1, 1 },
1626 M32R_INSN_BCL8, "bcl8", "bcl.s",
1627 { { MNEM, ' ', OP (DISP8), 0 } },
1628 & fmt_bcl8, { 0x7800 },
1629 (PTR) & fmt_bcl8_ops[0],
1630 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1631 },
1632 /* end-sanitize-m32rx */
1633 /* start-sanitize-m32rx */
1634 /* bcl.l $disp24 */
1635 {
1636 { 1, 1, 1, 1 },
1637 M32R_INSN_BCL24, "bcl24", "bcl.l",
1638 { { MNEM, ' ', OP (DISP24), 0 } },
1639 & fmt_bcl24, { 0xf8000000 },
1640 (PTR) & fmt_bcl24_ops[0],
1641 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1642 },
1643 /* end-sanitize-m32rx */
1644 /* bnc.s $disp8 */
1645 {
1646 { 1, 1, 1, 1 },
1647 M32R_INSN_BNC8, "bnc8", "bnc.s",
1648 { { MNEM, ' ', OP (DISP8), 0 } },
1649 & fmt_bc8, { 0x7d00 },
1650 (PTR) & fmt_bc8_ops[0],
1651 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
1652 },
1653 /* bnc.l $disp24 */
1654 {
1655 { 1, 1, 1, 1 },
1656 M32R_INSN_BNC24, "bnc24", "bnc.l",
1657 { { MNEM, ' ', OP (DISP24), 0 } },
1658 & fmt_bc24, { 0xfd000000 },
1659 (PTR) & fmt_bc24_ops[0],
1660 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1661 },
1662 /* bne $src1,$src2,$disp16 */
1663 {
1664 { 1, 1, 1, 1 },
1665 M32R_INSN_BNE, "bne", "bne",
1666 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1667 & fmt_beq, { 0xb0100000 },
1668 (PTR) & fmt_beq_ops[0],
1669 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1670 },
1671 /* bra.s $disp8 */
1672 {
1673 { 1, 1, 1, 1 },
1674 M32R_INSN_BRA8, "bra8", "bra.s",
1675 { { MNEM, ' ', OP (DISP8), 0 } },
1676 & fmt_bra8, { 0x7f00 },
1677 (PTR) & fmt_bra8_ops[0],
1678 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1679 },
1680 /* bra.l $disp24 */
1681 {
1682 { 1, 1, 1, 1 },
1683 M32R_INSN_BRA24, "bra24", "bra.l",
1684 { { MNEM, ' ', OP (DISP24), 0 } },
1685 & fmt_bra24, { 0xff000000 },
1686 (PTR) & fmt_bra24_ops[0],
1687 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1688 },
1689 /* start-sanitize-m32rx */
1690 /* bncl.s $disp8 */
1691 {
1692 { 1, 1, 1, 1 },
1693 M32R_INSN_BNCL8, "bncl8", "bncl.s",
1694 { { MNEM, ' ', OP (DISP8), 0 } },
1695 & fmt_bcl8, { 0x7900 },
1696 (PTR) & fmt_bcl8_ops[0],
1697 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1698 },
1699 /* end-sanitize-m32rx */
1700 /* start-sanitize-m32rx */
1701 /* bncl.l $disp24 */
1702 {
1703 { 1, 1, 1, 1 },
1704 M32R_INSN_BNCL24, "bncl24", "bncl.l",
1705 { { MNEM, ' ', OP (DISP24), 0 } },
1706 & fmt_bcl24, { 0xf9000000 },
1707 (PTR) & fmt_bcl24_ops[0],
1708 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1709 },
1710 /* end-sanitize-m32rx */
1711 /* cmp $src1,$src2 */
1712 {
1713 { 1, 1, 1, 1 },
1714 M32R_INSN_CMP, "cmp", "cmp",
1715 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1716 & fmt_cmp, { 0x40 },
1717 (PTR) & fmt_cmp_ops[0],
1718 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1719 },
1720 /* cmpi $src2,$simm16 */
1721 {
1722 { 1, 1, 1, 1 },
1723 M32R_INSN_CMPI, "cmpi", "cmpi",
1724 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1725 & fmt_cmpi, { 0x80400000 },
1726 (PTR) & fmt_cmpi_ops[0],
1727 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1728 },
1729 /* cmpu $src1,$src2 */
1730 {
1731 { 1, 1, 1, 1 },
1732 M32R_INSN_CMPU, "cmpu", "cmpu",
1733 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1734 & fmt_cmp, { 0x50 },
1735 (PTR) & fmt_cmp_ops[0],
1736 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1737 },
1738 /* cmpui $src2,$simm16 */
1739 {
1740 { 1, 1, 1, 1 },
1741 M32R_INSN_CMPUI, "cmpui", "cmpui",
1742 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1743 & fmt_cmpi, { 0x80500000 },
1744 (PTR) & fmt_cmpi_ops[0],
1745 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1746 },
1747 /* start-sanitize-m32rx */
1748 /* cmpeq $src1,$src2 */
1749 {
1750 { 1, 1, 1, 1 },
1751 M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
1752 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1753 & fmt_cmp, { 0x60 },
1754 (PTR) & fmt_cmp_ops[0],
1755 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1756 },
1757 /* end-sanitize-m32rx */
1758 /* start-sanitize-m32rx */
1759 /* cmpz $src2 */
1760 {
1761 { 1, 1, 1, 1 },
1762 M32R_INSN_CMPZ, "cmpz", "cmpz",
1763 { { MNEM, ' ', OP (SRC2), 0 } },
1764 & fmt_cmpz, { 0x70 },
1765 (PTR) & fmt_cmpz_ops[0],
1766 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1767 },
1768 /* end-sanitize-m32rx */
1769 /* div $dr,$sr */
1770 {
1771 { 1, 1, 1, 1 },
1772 M32R_INSN_DIV, "div", "div",
1773 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1774 & fmt_div, { 0x90000000 },
1775 (PTR) & fmt_div_ops[0],
1776 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1777 },
1778 /* divu $dr,$sr */
1779 {
1780 { 1, 1, 1, 1 },
1781 M32R_INSN_DIVU, "divu", "divu",
1782 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1783 & fmt_div, { 0x90100000 },
1784 (PTR) & fmt_div_ops[0],
1785 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1786 },
1787 /* rem $dr,$sr */
1788 {
1789 { 1, 1, 1, 1 },
1790 M32R_INSN_REM, "rem", "rem",
1791 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1792 & fmt_div, { 0x90200000 },
1793 (PTR) & fmt_div_ops[0],
1794 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1795 },
1796 /* remu $dr,$sr */
1797 {
1798 { 1, 1, 1, 1 },
1799 M32R_INSN_REMU, "remu", "remu",
1800 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1801 & fmt_div, { 0x90300000 },
1802 (PTR) & fmt_div_ops[0],
1803 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1804 },
1805 /* start-sanitize-m32rx */
1806 /* divh $dr,$sr */
1807 {
1808 { 1, 1, 1, 1 },
1809 M32R_INSN_DIVH, "divh", "divh",
1810 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1811 & fmt_div, { 0x90000010 },
1812 (PTR) & fmt_div_ops[0],
1813 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1814 },
1815 /* end-sanitize-m32rx */
1816 /* start-sanitize-m32rx */
1817 /* jc $sr */
1818 {
1819 { 1, 1, 1, 1 },
1820 M32R_INSN_JC, "jc", "jc",
1821 { { MNEM, ' ', OP (SR), 0 } },
1822 & fmt_jc, { 0x1cc0 },
1823 (PTR) & fmt_jc_ops[0],
1824 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1825 },
1826 /* end-sanitize-m32rx */
1827 /* start-sanitize-m32rx */
1828 /* jnc $sr */
1829 {
1830 { 1, 1, 1, 1 },
1831 M32R_INSN_JNC, "jnc", "jnc",
1832 { { MNEM, ' ', OP (SR), 0 } },
1833 & fmt_jc, { 0x1dc0 },
1834 (PTR) & fmt_jc_ops[0],
1835 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1836 },
1837 /* end-sanitize-m32rx */
1838 /* jl $sr */
1839 {
1840 { 1, 1, 1, 1 },
1841 M32R_INSN_JL, "jl", "jl",
1842 { { MNEM, ' ', OP (SR), 0 } },
1843 & fmt_jl, { 0x1ec0 },
1844 (PTR) & fmt_jl_ops[0],
1845 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1846 },
1847 /* jmp $sr */
1848 {
1849 { 1, 1, 1, 1 },
1850 M32R_INSN_JMP, "jmp", "jmp",
1851 { { MNEM, ' ', OP (SR), 0 } },
1852 & fmt_jmp, { 0x1fc0 },
1853 (PTR) & fmt_jmp_ops[0],
1854 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1855 },
1856 /* ld $dr,@$sr */
1857 {
1858 { 1, 1, 1, 1 },
1859 M32R_INSN_LD, "ld", "ld",
1860 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1861 & fmt_ld, { 0x20c0 },
1862 (PTR) & fmt_ld_ops[0],
1863 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1864 },
1865 /* ld $dr,@($slo16,$sr) */
1866 {
1867 { 1, 1, 1, 1 },
1868 M32R_INSN_LD_D, "ld-d", "ld",
1869 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1870 & fmt_ld_d, { 0xa0c00000 },
1871 (PTR) & fmt_ld_d_ops[0],
1872 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1873 },
1874 /* ldb $dr,@$sr */
1875 {
1876 { 1, 1, 1, 1 },
1877 M32R_INSN_LDB, "ldb", "ldb",
1878 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1879 & fmt_ldb, { 0x2080 },
1880 (PTR) & fmt_ldb_ops[0],
1881 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1882 },
1883 /* ldb $dr,@($slo16,$sr) */
1884 {
1885 { 1, 1, 1, 1 },
1886 M32R_INSN_LDB_D, "ldb-d", "ldb",
1887 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1888 & fmt_ldb_d, { 0xa0800000 },
1889 (PTR) & fmt_ldb_d_ops[0],
1890 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1891 },
1892 /* ldh $dr,@$sr */
1893 {
1894 { 1, 1, 1, 1 },
1895 M32R_INSN_LDH, "ldh", "ldh",
1896 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1897 & fmt_ldh, { 0x20a0 },
1898 (PTR) & fmt_ldh_ops[0],
1899 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1900 },
1901 /* ldh $dr,@($slo16,$sr) */
1902 {
1903 { 1, 1, 1, 1 },
1904 M32R_INSN_LDH_D, "ldh-d", "ldh",
1905 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1906 & fmt_ldh_d, { 0xa0a00000 },
1907 (PTR) & fmt_ldh_d_ops[0],
1908 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1909 },
1910 /* ldub $dr,@$sr */
1911 {
1912 { 1, 1, 1, 1 },
1913 M32R_INSN_LDUB, "ldub", "ldub",
1914 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1915 & fmt_ldb, { 0x2090 },
1916 (PTR) & fmt_ldb_ops[0],
1917 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1918 },
1919 /* ldub $dr,@($slo16,$sr) */
1920 {
1921 { 1, 1, 1, 1 },
1922 M32R_INSN_LDUB_D, "ldub-d", "ldub",
1923 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1924 & fmt_ldb_d, { 0xa0900000 },
1925 (PTR) & fmt_ldb_d_ops[0],
1926 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1927 },
1928 /* lduh $dr,@$sr */
1929 {
1930 { 1, 1, 1, 1 },
1931 M32R_INSN_LDUH, "lduh", "lduh",
1932 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1933 & fmt_ldh, { 0x20b0 },
1934 (PTR) & fmt_ldh_ops[0],
1935 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1936 },
1937 /* lduh $dr,@($slo16,$sr) */
1938 {
1939 { 1, 1, 1, 1 },
1940 M32R_INSN_LDUH_D, "lduh-d", "lduh",
1941 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1942 & fmt_ldh_d, { 0xa0b00000 },
1943 (PTR) & fmt_ldh_d_ops[0],
1944 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1945 },
1946 /* ld $dr,@$sr+ */
1947 {
1948 { 1, 1, 1, 1 },
1949 M32R_INSN_LD_PLUS, "ld-plus", "ld",
1950 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
1951 & fmt_ld_plus, { 0x20e0 },
1952 (PTR) & fmt_ld_plus_ops[0],
1953 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1954 },
1955 /* ld24 $dr,$uimm24 */
1956 {
1957 { 1, 1, 1, 1 },
1958 M32R_INSN_LD24, "ld24", "ld24",
1959 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
1960 & fmt_ld24, { 0xe0000000 },
1961 (PTR) & fmt_ld24_ops[0],
1962 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1963 },
1964 /* ldi8 $dr,$simm8 */
1965 {
1966 { 1, 1, 1, 1 },
1967 M32R_INSN_LDI8, "ldi8", "ldi8",
1968 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1969 & fmt_ldi8, { 0x6000 },
1970 (PTR) & fmt_ldi8_ops[0],
1971 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1972 },
1973 /* ldi16 $dr,$hash$slo16 */
1974 {
1975 { 1, 1, 1, 1 },
1976 M32R_INSN_LDI16, "ldi16", "ldi16",
1977 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1978 & fmt_ldi16, { 0x90f00000 },
1979 (PTR) & fmt_ldi16_ops[0],
1980 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1981 },
1982 /* lock $dr,@$sr */
1983 {
1984 { 1, 1, 1, 1 },
1985 M32R_INSN_LOCK, "lock", "lock",
1986 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1987 & fmt_lock, { 0x20d0 },
1988 (PTR) & fmt_lock_ops[0],
1989 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1990 },
1991 /* machi $src1,$src2 */
1992 {
1993 { 1, 1, 1, 1 },
1994 M32R_INSN_MACHI, "machi", "machi",
1995 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1996 & fmt_machi, { 0x3040 },
1997 (PTR) & fmt_machi_ops[0],
1998 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1999 },
2000 /* start-sanitize-m32rx */
2001 /* machi $src1,$src2,$acc */
2002 {
2003 { 1, 1, 1, 1 },
2004 M32R_INSN_MACHI_A, "machi-a", "machi",
2005 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2006 & fmt_machi_a, { 0x3040 },
2007 (PTR) & fmt_machi_a_ops[0],
2008 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2009 },
2010 /* end-sanitize-m32rx */
2011 /* maclo $src1,$src2 */
2012 {
2013 { 1, 1, 1, 1 },
2014 M32R_INSN_MACLO, "maclo", "maclo",
2015 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2016 & fmt_machi, { 0x3050 },
2017 (PTR) & fmt_machi_ops[0],
2018 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2019 },
2020 /* start-sanitize-m32rx */
2021 /* maclo $src1,$src2,$acc */
2022 {
2023 { 1, 1, 1, 1 },
2024 M32R_INSN_MACLO_A, "maclo-a", "maclo",
2025 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2026 & fmt_machi_a, { 0x3050 },
2027 (PTR) & fmt_machi_a_ops[0],
2028 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2029 },
2030 /* end-sanitize-m32rx */
2031 /* macwhi $src1,$src2 */
2032 {
2033 { 1, 1, 1, 1 },
2034 M32R_INSN_MACWHI, "macwhi", "macwhi",
2035 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2036 & fmt_machi, { 0x3060 },
2037 (PTR) & fmt_machi_ops[0],
2038 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2039 },
2040 /* start-sanitize-m32rx */
2041 /* macwhi $src1,$src2,$acc */
2042 {
2043 { 1, 1, 1, 1 },
2044 M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
2045 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2046 & fmt_machi_a, { 0x3060 },
2047 (PTR) & fmt_machi_a_ops[0],
2048 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2049 },
2050 /* end-sanitize-m32rx */
2051 /* macwlo $src1,$src2 */
2052 {
2053 { 1, 1, 1, 1 },
2054 M32R_INSN_MACWLO, "macwlo", "macwlo",
2055 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2056 & fmt_machi, { 0x3070 },
2057 (PTR) & fmt_machi_ops[0],
2058 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2059 },
2060 /* start-sanitize-m32rx */
2061 /* macwlo $src1,$src2,$acc */
2062 {
2063 { 1, 1, 1, 1 },
2064 M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
2065 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2066 & fmt_machi_a, { 0x3070 },
2067 (PTR) & fmt_machi_a_ops[0],
2068 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2069 },
2070 /* end-sanitize-m32rx */
2071 /* mul $dr,$sr */
2072 {
2073 { 1, 1, 1, 1 },
2074 M32R_INSN_MUL, "mul", "mul",
2075 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2076 & fmt_add, { 0x1060 },
2077 (PTR) & fmt_add_ops[0],
2078 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } }
2079 },
2080 /* mulhi $src1,$src2 */
2081 {
2082 { 1, 1, 1, 1 },
2083 M32R_INSN_MULHI, "mulhi", "mulhi",
2084 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2085 & fmt_mulhi, { 0x3000 },
2086 (PTR) & fmt_mulhi_ops[0],
2087 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2088 },
2089 /* start-sanitize-m32rx */
2090 /* mulhi $src1,$src2,$acc */
2091 {
2092 { 1, 1, 1, 1 },
2093 M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
2094 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2095 & fmt_mulhi_a, { 0x3000 },
2096 (PTR) & fmt_mulhi_a_ops[0],
2097 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2098 },
2099 /* end-sanitize-m32rx */
2100 /* mullo $src1,$src2 */
2101 {
2102 { 1, 1, 1, 1 },
2103 M32R_INSN_MULLO, "mullo", "mullo",
2104 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2105 & fmt_mulhi, { 0x3010 },
2106 (PTR) & fmt_mulhi_ops[0],
2107 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2108 },
2109 /* start-sanitize-m32rx */
2110 /* mullo $src1,$src2,$acc */
2111 {
2112 { 1, 1, 1, 1 },
2113 M32R_INSN_MULLO_A, "mullo-a", "mullo",
2114 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2115 & fmt_mulhi_a, { 0x3010 },
2116 (PTR) & fmt_mulhi_a_ops[0],
2117 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2118 },
2119 /* end-sanitize-m32rx */
2120 /* mulwhi $src1,$src2 */
2121 {
2122 { 1, 1, 1, 1 },
2123 M32R_INSN_MULWHI, "mulwhi", "mulwhi",
2124 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2125 & fmt_mulhi, { 0x3020 },
2126 (PTR) & fmt_mulhi_ops[0],
2127 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2128 },
2129 /* start-sanitize-m32rx */
2130 /* mulwhi $src1,$src2,$acc */
2131 {
2132 { 1, 1, 1, 1 },
2133 M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
2134 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2135 & fmt_mulhi_a, { 0x3020 },
2136 (PTR) & fmt_mulhi_a_ops[0],
2137 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2138 },
2139 /* end-sanitize-m32rx */
2140 /* mulwlo $src1,$src2 */
2141 {
2142 { 1, 1, 1, 1 },
2143 M32R_INSN_MULWLO, "mulwlo", "mulwlo",
2144 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2145 & fmt_mulhi, { 0x3030 },
2146 (PTR) & fmt_mulhi_ops[0],
2147 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2148 },
2149 /* start-sanitize-m32rx */
2150 /* mulwlo $src1,$src2,$acc */
2151 {
2152 { 1, 1, 1, 1 },
2153 M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
2154 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
2155 & fmt_mulhi_a, { 0x3030 },
2156 (PTR) & fmt_mulhi_a_ops[0],
2157 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
2158 },
2159 /* end-sanitize-m32rx */
2160 /* mv $dr,$sr */
2161 {
2162 { 1, 1, 1, 1 },
2163 M32R_INSN_MV, "mv", "mv",
2164 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2165 & fmt_mv, { 0x1080 },
2166 (PTR) & fmt_mv_ops[0],
2167 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2168 },
2169 /* mvfachi $dr */
2170 {
2171 { 1, 1, 1, 1 },
2172 M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
2173 { { MNEM, ' ', OP (DR), 0 } },
2174 & fmt_mvfachi, { 0x50f0 },
2175 (PTR) & fmt_mvfachi_ops[0],
2176 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2177 },
2178 /* start-sanitize-m32rx */
2179 /* mvfachi $dr,$accs */
2180 {
2181 { 1, 1, 1, 1 },
2182 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
2183 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
2184 & fmt_mvfachi_a, { 0x50f0 },
2185 (PTR) & fmt_mvfachi_a_ops[0],
2186 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2187 },
2188 /* end-sanitize-m32rx */
2189 /* mvfaclo $dr */
2190 {
2191 { 1, 1, 1, 1 },
2192 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
2193 { { MNEM, ' ', OP (DR), 0 } },
2194 & fmt_mvfachi, { 0x50f1 },
2195 (PTR) & fmt_mvfachi_ops[0],
2196 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2197 },
2198 /* start-sanitize-m32rx */
2199 /* mvfaclo $dr,$accs */
2200 {
2201 { 1, 1, 1, 1 },
2202 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
2203 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
2204 & fmt_mvfachi_a, { 0x50f1 },
2205 (PTR) & fmt_mvfachi_a_ops[0],
2206 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2207 },
2208 /* end-sanitize-m32rx */
2209 /* mvfacmi $dr */
2210 {
2211 { 1, 1, 1, 1 },
2212 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
2213 { { MNEM, ' ', OP (DR), 0 } },
2214 & fmt_mvfachi, { 0x50f2 },
2215 (PTR) & fmt_mvfachi_ops[0],
2216 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2217 },
2218 /* start-sanitize-m32rx */
2219 /* mvfacmi $dr,$accs */
2220 {
2221 { 1, 1, 1, 1 },
2222 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
2223 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
2224 & fmt_mvfachi_a, { 0x50f2 },
2225 (PTR) & fmt_mvfachi_a_ops[0],
2226 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2227 },
2228 /* end-sanitize-m32rx */
2229 /* mvfc $dr,$scr */
2230 {
2231 { 1, 1, 1, 1 },
2232 M32R_INSN_MVFC, "mvfc", "mvfc",
2233 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
2234 & fmt_mvfc, { 0x1090 },
2235 (PTR) & fmt_mvfc_ops[0],
2236 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2237 },
2238 /* mvtachi $src1 */
2239 {
2240 { 1, 1, 1, 1 },
2241 M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
2242 { { MNEM, ' ', OP (SRC1), 0 } },
2243 & fmt_mvtachi, { 0x5070 },
2244 (PTR) & fmt_mvtachi_ops[0],
2245 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2246 },
2247 /* start-sanitize-m32rx */
2248 /* mvtachi $src1,$accs */
2249 {
2250 { 1, 1, 1, 1 },
2251 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
2252 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
2253 & fmt_mvtachi_a, { 0x5070 },
2254 (PTR) & fmt_mvtachi_a_ops[0],
2255 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2256 },
2257 /* end-sanitize-m32rx */
2258 /* mvtaclo $src1 */
2259 {
2260 { 1, 1, 1, 1 },
2261 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
2262 { { MNEM, ' ', OP (SRC1), 0 } },
2263 & fmt_mvtachi, { 0x5071 },
2264 (PTR) & fmt_mvtachi_ops[0],
2265 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2266 },
2267 /* start-sanitize-m32rx */
2268 /* mvtaclo $src1,$accs */
2269 {
2270 { 1, 1, 1, 1 },
2271 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
2272 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
2273 & fmt_mvtachi_a, { 0x5071 },
2274 (PTR) & fmt_mvtachi_a_ops[0],
2275 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2276 },
2277 /* end-sanitize-m32rx */
2278 /* mvtc $sr,$dcr */
2279 {
2280 { 1, 1, 1, 1 },
2281 M32R_INSN_MVTC, "mvtc", "mvtc",
2282 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
2283 & fmt_mvtc, { 0x10a0 },
2284 (PTR) & fmt_mvtc_ops[0],
2285 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2286 },
2287 /* neg $dr,$sr */
2288 {
2289 { 1, 1, 1, 1 },
2290 M32R_INSN_NEG, "neg", "neg",
2291 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2292 & fmt_mv, { 0x30 },
2293 (PTR) & fmt_mv_ops[0],
2294 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2295 },
2296 /* nop */
2297 {
2298 { 1, 1, 1, 1 },
2299 M32R_INSN_NOP, "nop", "nop",
2300 { { MNEM, 0 } },
2301 & fmt_nop, { 0x7000 },
2302 (PTR) 0,
2303 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2304 },
2305 /* not $dr,$sr */
2306 {
2307 { 1, 1, 1, 1 },
2308 M32R_INSN_NOT, "not", "not",
2309 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2310 & fmt_mv, { 0xb0 },
2311 (PTR) & fmt_mv_ops[0],
2312 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2313 },
2314 /* rac */
2315 {
2316 { 1, 1, 1, 1 },
2317 M32R_INSN_RAC, "rac", "rac",
2318 { { MNEM, 0 } },
2319 & fmt_rac, { 0x5090 },
2320 (PTR) & fmt_rac_ops[0],
2321 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2322 },
2323 /* start-sanitize-m32rx */
2324 /* rac $accd,$accs,$imm1 */
2325 {
2326 { 1, 1, 1, 1 },
2327 M32R_INSN_RAC_DSI, "rac-dsi", "rac",
2328 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
2329 & fmt_rac_dsi, { 0x5090 },
2330 (PTR) & fmt_rac_dsi_ops[0],
2331 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2332 },
2333 /* end-sanitize-m32rx */
2334 /* rach */
2335 {
2336 { 1, 1, 1, 1 },
2337 M32R_INSN_RACH, "rach", "rach",
2338 { { MNEM, 0 } },
2339 & fmt_rac, { 0x5080 },
2340 (PTR) & fmt_rac_ops[0],
2341 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2342 },
2343 /* start-sanitize-m32rx */
2344 /* rach $accd,$accs,$imm1 */
2345 {
2346 { 1, 1, 1, 1 },
2347 M32R_INSN_RACH_DSI, "rach-dsi", "rach",
2348 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
2349 & fmt_rac_dsi, { 0x5080 },
2350 (PTR) & fmt_rac_dsi_ops[0],
2351 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2352 },
2353 /* end-sanitize-m32rx */
2354 /* rte */
2355 {
2356 { 1, 1, 1, 1 },
2357 M32R_INSN_RTE, "rte", "rte",
2358 { { MNEM, 0 } },
2359 & fmt_rte, { 0x10d6 },
2360 (PTR) & fmt_rte_ops[0],
2361 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
2362 },
2363 /* seth $dr,$hash$hi16 */
2364 {
2365 { 1, 1, 1, 1 },
2366 M32R_INSN_SETH, "seth", "seth",
2367 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
2368 & fmt_seth, { 0xd0c00000 },
2369 (PTR) & fmt_seth_ops[0],
2370 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2371 },
2372 /* sll $dr,$sr */
2373 {
2374 { 1, 1, 1, 1 },
2375 M32R_INSN_SLL, "sll", "sll",
2376 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2377 & fmt_add, { 0x1040 },
2378 (PTR) & fmt_add_ops[0],
2379 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2380 },
2381 /* sll3 $dr,$sr,$simm16 */
2382 {
2383 { 1, 1, 1, 1 },
2384 M32R_INSN_SLL3, "sll3", "sll3",
2385 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2386 & fmt_sll3, { 0x90c00000 },
2387 (PTR) & fmt_sll3_ops[0],
2388 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2389 },
2390 /* slli $dr,$uimm5 */
2391 {
2392 { 1, 1, 1, 1 },
2393 M32R_INSN_SLLI, "slli", "slli",
2394 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2395 & fmt_slli, { 0x5040 },
2396 (PTR) & fmt_slli_ops[0],
2397 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2398 },
2399 /* sra $dr,$sr */
2400 {
2401 { 1, 1, 1, 1 },
2402 M32R_INSN_SRA, "sra", "sra",
2403 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2404 & fmt_add, { 0x1020 },
2405 (PTR) & fmt_add_ops[0],
2406 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2407 },
2408 /* sra3 $dr,$sr,$simm16 */
2409 {
2410 { 1, 1, 1, 1 },
2411 M32R_INSN_SRA3, "sra3", "sra3",
2412 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2413 & fmt_sll3, { 0x90a00000 },
2414 (PTR) & fmt_sll3_ops[0],
2415 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2416 },
2417 /* srai $dr,$uimm5 */
2418 {
2419 { 1, 1, 1, 1 },
2420 M32R_INSN_SRAI, "srai", "srai",
2421 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2422 & fmt_slli, { 0x5020 },
2423 (PTR) & fmt_slli_ops[0],
2424 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2425 },
2426 /* srl $dr,$sr */
2427 {
2428 { 1, 1, 1, 1 },
2429 M32R_INSN_SRL, "srl", "srl",
2430 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2431 & fmt_add, { 0x1000 },
2432 (PTR) & fmt_add_ops[0],
2433 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2434 },
2435 /* srl3 $dr,$sr,$simm16 */
2436 {
2437 { 1, 1, 1, 1 },
2438 M32R_INSN_SRL3, "srl3", "srl3",
2439 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2440 & fmt_sll3, { 0x90800000 },
2441 (PTR) & fmt_sll3_ops[0],
2442 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2443 },
2444 /* srli $dr,$uimm5 */
2445 {
2446 { 1, 1, 1, 1 },
2447 M32R_INSN_SRLI, "srli", "srli",
2448 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2449 & fmt_slli, { 0x5000 },
2450 (PTR) & fmt_slli_ops[0],
2451 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2452 },
2453 /* st $src1,@$src2 */
2454 {
2455 { 1, 1, 1, 1 },
2456 M32R_INSN_ST, "st", "st",
2457 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2458 & fmt_st, { 0x2040 },
2459 (PTR) & fmt_st_ops[0],
2460 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2461 },
2462 /* st $src1,@($slo16,$src2) */
2463 {
2464 { 1, 1, 1, 1 },
2465 M32R_INSN_ST_D, "st-d", "st",
2466 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2467 & fmt_st_d, { 0xa0400000 },
2468 (PTR) & fmt_st_d_ops[0],
2469 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2470 },
2471 /* stb $src1,@$src2 */
2472 {
2473 { 1, 1, 1, 1 },
2474 M32R_INSN_STB, "stb", "stb",
2475 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2476 & fmt_stb, { 0x2000 },
2477 (PTR) & fmt_stb_ops[0],
2478 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2479 },
2480 /* stb $src1,@($slo16,$src2) */
2481 {
2482 { 1, 1, 1, 1 },
2483 M32R_INSN_STB_D, "stb-d", "stb",
2484 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2485 & fmt_stb_d, { 0xa0000000 },
2486 (PTR) & fmt_stb_d_ops[0],
2487 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2488 },
2489 /* sth $src1,@$src2 */
2490 {
2491 { 1, 1, 1, 1 },
2492 M32R_INSN_STH, "sth", "sth",
2493 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2494 & fmt_sth, { 0x2020 },
2495 (PTR) & fmt_sth_ops[0],
2496 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2497 },
2498 /* sth $src1,@($slo16,$src2) */
2499 {
2500 { 1, 1, 1, 1 },
2501 M32R_INSN_STH_D, "sth-d", "sth",
2502 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2503 & fmt_sth_d, { 0xa0200000 },
2504 (PTR) & fmt_sth_d_ops[0],
2505 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2506 },
2507 /* st $src1,@+$src2 */
2508 {
2509 { 1, 1, 1, 1 },
2510 M32R_INSN_ST_PLUS, "st-plus", "st",
2511 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
2512 & fmt_st_plus, { 0x2060 },
2513 (PTR) & fmt_st_plus_ops[0],
2514 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2515 },
2516 /* st $src1,@-$src2 */
2517 {
2518 { 1, 1, 1, 1 },
2519 M32R_INSN_ST_MINUS, "st-minus", "st",
2520 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
2521 & fmt_st_plus, { 0x2070 },
2522 (PTR) & fmt_st_plus_ops[0],
2523 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2524 },
2525 /* sub $dr,$sr */
2526 {
2527 { 1, 1, 1, 1 },
2528 M32R_INSN_SUB, "sub", "sub",
2529 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2530 & fmt_add, { 0x20 },
2531 (PTR) & fmt_add_ops[0],
2532 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2533 },
2534 /* subv $dr,$sr */
2535 {
2536 { 1, 1, 1, 1 },
2537 M32R_INSN_SUBV, "subv", "subv",
2538 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2539 & fmt_addv, { 0x0 },
2540 (PTR) & fmt_addv_ops[0],
2541 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2542 },
2543 /* subx $dr,$sr */
2544 {
2545 { 1, 1, 1, 1 },
2546 M32R_INSN_SUBX, "subx", "subx",
2547 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2548 & fmt_addx, { 0x10 },
2549 (PTR) & fmt_addx_ops[0],
2550 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2551 },
2552 /* trap $uimm4 */
2553 {
2554 { 1, 1, 1, 1 },
2555 M32R_INSN_TRAP, "trap", "trap",
2556 { { MNEM, ' ', OP (UIMM4), 0 } },
2557 & fmt_trap, { 0x10f0 },
2558 (PTR) & fmt_trap_ops[0],
2559 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
2560 },
2561 /* unlock $src1,@$src2 */
2562 {
2563 { 1, 1, 1, 1 },
2564 M32R_INSN_UNLOCK, "unlock", "unlock",
2565 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2566 & fmt_unlock, { 0x2050 },
2567 (PTR) & fmt_unlock_ops[0],
2568 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2569 },
2570 /* start-sanitize-m32rx */
2571 /* satb $dr,$sr */
2572 {
2573 { 1, 1, 1, 1 },
2574 M32R_INSN_SATB, "satb", "satb",
2575 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2576 & fmt_satb, { 0x80600300 },
2577 (PTR) & fmt_satb_ops[0],
2578 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2579 },
2580 /* end-sanitize-m32rx */
2581 /* start-sanitize-m32rx */
2582 /* sath $dr,$sr */
2583 {
2584 { 1, 1, 1, 1 },
2585 M32R_INSN_SATH, "sath", "sath",
2586 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2587 & fmt_satb, { 0x80600200 },
2588 (PTR) & fmt_satb_ops[0],
2589 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2590 },
2591 /* end-sanitize-m32rx */
2592 /* start-sanitize-m32rx */
2593 /* sat $dr,$sr */
2594 {
2595 { 1, 1, 1, 1 },
2596 M32R_INSN_SAT, "sat", "sat",
2597 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2598 & fmt_sat, { 0x80600000 },
2599 (PTR) & fmt_sat_ops[0],
2600 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
2601 },
2602 /* end-sanitize-m32rx */
2603 /* start-sanitize-m32rx */
2604 /* pcmpbz $src2 */
2605 {
2606 { 1, 1, 1, 1 },
2607 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2608 { { MNEM, ' ', OP (SRC2), 0 } },
2609 & fmt_cmpz, { 0x370 },
2610 (PTR) & fmt_cmpz_ops[0],
2611 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2612 },
2613 /* end-sanitize-m32rx */
2614 /* start-sanitize-m32rx */
2615 /* sadd */
2616 {
2617 { 1, 1, 1, 1 },
2618 M32R_INSN_SADD, "sadd", "sadd",
2619 { { MNEM, 0 } },
2620 & fmt_sadd, { 0x50e4 },
2621 (PTR) & fmt_sadd_ops[0],
2622 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2623 },
2624 /* end-sanitize-m32rx */
2625 /* start-sanitize-m32rx */
2626 /* macwu1 $src1,$src2 */
2627 {
2628 { 1, 1, 1, 1 },
2629 M32R_INSN_MACWU1, "macwu1", "macwu1",
2630 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2631 & fmt_macwu1, { 0x50b0 },
2632 (PTR) & fmt_macwu1_ops[0],
2633 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2634 },
2635 /* end-sanitize-m32rx */
2636 /* start-sanitize-m32rx */
2637 /* msblo $src1,$src2 */
2638 {
2639 { 1, 1, 1, 1 },
2640 M32R_INSN_MSBLO, "msblo", "msblo",
2641 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2642 & fmt_machi, { 0x50d0 },
2643 (PTR) & fmt_machi_ops[0],
2644 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2645 },
2646 /* end-sanitize-m32rx */
2647 /* start-sanitize-m32rx */
2648 /* mulwu1 $src1,$src2 */
2649 {
2650 { 1, 1, 1, 1 },
2651 M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2652 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2653 & fmt_mulwu1, { 0x50a0 },
2654 (PTR) & fmt_mulwu1_ops[0],
2655 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2656 },
2657 /* end-sanitize-m32rx */
2658 /* start-sanitize-m32rx */
2659 /* maclh1 $src1,$src2 */
2660 {
2661 { 1, 1, 1, 1 },
2662 M32R_INSN_MACLH1, "maclh1", "maclh1",
2663 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2664 & fmt_macwu1, { 0x50c0 },
2665 (PTR) & fmt_macwu1_ops[0],
2666 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2667 },
2668 /* end-sanitize-m32rx */
2669 /* start-sanitize-m32rx */
2670 /* sc */
2671 {
2672 { 1, 1, 1, 1 },
2673 M32R_INSN_SC, "sc", "sc",
2674 { { MNEM, 0 } },
2675 & fmt_sc, { 0x7401 },
2676 (PTR) & fmt_sc_ops[0],
2677 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
2678 },
2679 /* end-sanitize-m32rx */
2680 /* start-sanitize-m32rx */
2681 /* snc */
2682 {
2683 { 1, 1, 1, 1 },
2684 M32R_INSN_SNC, "snc", "snc",
2685 { { MNEM, 0 } },
2686 & fmt_sc, { 0x7501 },
2687 (PTR) & fmt_sc_ops[0],
2688 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
2689 },
2690 /* end-sanitize-m32rx */
2691 };
2692
2693 #undef A
2694 #undef MNEM
2695 #undef OP
2696
2697 static const CGEN_INSN_TABLE insn_table =
2698 {
2699 & m32r_cgen_insn_table_entries[0],
2700 sizeof (CGEN_INSN),
2701 MAX_INSNS,
2702 NULL
2703 };
2704
2705 /* Formats for ALIAS macro-insns. */
2706
2707 #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
2708
2709 static const CGEN_IFMT fmt_bc8r = {
2710 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2711 };
2712
2713 static const CGEN_IFMT fmt_bc24r = {
2714 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2715 };
2716
2717 static const CGEN_IFMT fmt_bl8r = {
2718 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2719 };
2720
2721 static const CGEN_IFMT fmt_bl24r = {
2722 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2723 };
2724
2725 /* start-sanitize-m32rx */
2726 static const CGEN_IFMT fmt_bcl8r = {
2727 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2728 };
2729
2730 /* end-sanitize-m32rx */
2731 /* start-sanitize-m32rx */
2732 static const CGEN_IFMT fmt_bcl24r = {
2733 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2734 };
2735
2736 /* end-sanitize-m32rx */
2737 static const CGEN_IFMT fmt_bnc8r = {
2738 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2739 };
2740
2741 static const CGEN_IFMT fmt_bnc24r = {
2742 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2743 };
2744
2745 static const CGEN_IFMT fmt_bra8r = {
2746 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2747 };
2748
2749 static const CGEN_IFMT fmt_bra24r = {
2750 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2751 };
2752
2753 /* start-sanitize-m32rx */
2754 static const CGEN_IFMT fmt_bncl8r = {
2755 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
2756 };
2757
2758 /* end-sanitize-m32rx */
2759 /* start-sanitize-m32rx */
2760 static const CGEN_IFMT fmt_bncl24r = {
2761 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
2762 };
2763
2764 /* end-sanitize-m32rx */
2765 static const CGEN_IFMT fmt_ld_2 = {
2766 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2767 };
2768
2769 static const CGEN_IFMT fmt_ld_d2 = {
2770 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2771 };
2772
2773 static const CGEN_IFMT fmt_ldb_2 = {
2774 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2775 };
2776
2777 static const CGEN_IFMT fmt_ldb_d2 = {
2778 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2779 };
2780
2781 static const CGEN_IFMT fmt_ldh_2 = {
2782 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2783 };
2784
2785 static const CGEN_IFMT fmt_ldh_d2 = {
2786 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2787 };
2788
2789 static const CGEN_IFMT fmt_ldub_2 = {
2790 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2791 };
2792
2793 static const CGEN_IFMT fmt_ldub_d2 = {
2794 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2795 };
2796
2797 static const CGEN_IFMT fmt_lduh_2 = {
2798 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2799 };
2800
2801 static const CGEN_IFMT fmt_lduh_d2 = {
2802 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2803 };
2804
2805 static const CGEN_IFMT fmt_pop = {
2806 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2807 };
2808
2809 static const CGEN_IFMT fmt_ldi8a = {
2810 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
2811 };
2812
2813 static const CGEN_IFMT fmt_ldi16a = {
2814 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2815 };
2816
2817 /* start-sanitize-m32rx */
2818 static const CGEN_IFMT fmt_rac_d = {
2819 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2820 };
2821
2822 /* end-sanitize-m32rx */
2823 /* start-sanitize-m32rx */
2824 static const CGEN_IFMT fmt_rac_ds = {
2825 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2826 };
2827
2828 /* end-sanitize-m32rx */
2829 /* start-sanitize-m32rx */
2830 static const CGEN_IFMT fmt_rach_d = {
2831 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2832 };
2833
2834 /* end-sanitize-m32rx */
2835 /* start-sanitize-m32rx */
2836 static const CGEN_IFMT fmt_rach_ds = {
2837 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
2838 };
2839
2840 /* end-sanitize-m32rx */
2841 static const CGEN_IFMT fmt_st_2 = {
2842 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2843 };
2844
2845 static const CGEN_IFMT fmt_st_d2 = {
2846 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2847 };
2848
2849 static const CGEN_IFMT fmt_stb_2 = {
2850 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2851 };
2852
2853 static const CGEN_IFMT fmt_stb_d2 = {
2854 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2855 };
2856
2857 static const CGEN_IFMT fmt_sth_2 = {
2858 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2859 };
2860
2861 static const CGEN_IFMT fmt_sth_d2 = {
2862 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
2863 };
2864
2865 static const CGEN_IFMT fmt_push = {
2866 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
2867 };
2868
2869 #undef F
2870
2871 /* Each non-simple macro entry points to an array of expansion possibilities. */
2872
2873 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2874 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2875 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2876
2877 /* The macro instruction table. */
2878
2879 static const CGEN_INSN macro_insn_table_entries[] =
2880 {
2881 /* bc $disp8 */
2882 {
2883 { 1, 1, 1, 1 },
2884 -1, "bc8r", "bc",
2885 { { MNEM, ' ', OP (DISP8), 0 } },
2886 & fmt_bc8r, { 0x7c00 },
2887 (PTR) 0,
2888 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2889 },
2890 /* bc $disp24 */
2891 {
2892 { 1, 1, 1, 1 },
2893 -1, "bc24r", "bc",
2894 { { MNEM, ' ', OP (DISP24), 0 } },
2895 & fmt_bc24r, { 0xfc000000 },
2896 (PTR) 0,
2897 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2898 },
2899 /* bl $disp8 */
2900 {
2901 { 1, 1, 1, 1 },
2902 -1, "bl8r", "bl",
2903 { { MNEM, ' ', OP (DISP8), 0 } },
2904 & fmt_bl8r, { 0x7e00 },
2905 (PTR) 0,
2906 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2907 },
2908 /* bl $disp24 */
2909 {
2910 { 1, 1, 1, 1 },
2911 -1, "bl24r", "bl",
2912 { { MNEM, ' ', OP (DISP24), 0 } },
2913 & fmt_bl24r, { 0xfe000000 },
2914 (PTR) 0,
2915 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2916 },
2917 /* start-sanitize-m32rx */
2918 /* bcl $disp8 */
2919 {
2920 { 1, 1, 1, 1 },
2921 -1, "bcl8r", "bcl",
2922 { { MNEM, ' ', OP (DISP8), 0 } },
2923 & fmt_bcl8r, { 0x7800 },
2924 (PTR) 0,
2925 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2926 },
2927 /* end-sanitize-m32rx */
2928 /* start-sanitize-m32rx */
2929 /* bcl $disp24 */
2930 {
2931 { 1, 1, 1, 1 },
2932 -1, "bcl24r", "bcl",
2933 { { MNEM, ' ', OP (DISP24), 0 } },
2934 & fmt_bcl24r, { 0xf8000000 },
2935 (PTR) 0,
2936 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2937 },
2938 /* end-sanitize-m32rx */
2939 /* bnc $disp8 */
2940 {
2941 { 1, 1, 1, 1 },
2942 -1, "bnc8r", "bnc",
2943 { { MNEM, ' ', OP (DISP8), 0 } },
2944 & fmt_bnc8r, { 0x7d00 },
2945 (PTR) 0,
2946 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2947 },
2948 /* bnc $disp24 */
2949 {
2950 { 1, 1, 1, 1 },
2951 -1, "bnc24r", "bnc",
2952 { { MNEM, ' ', OP (DISP24), 0 } },
2953 & fmt_bnc24r, { 0xfd000000 },
2954 (PTR) 0,
2955 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2956 },
2957 /* bra $disp8 */
2958 {
2959 { 1, 1, 1, 1 },
2960 -1, "bra8r", "bra",
2961 { { MNEM, ' ', OP (DISP8), 0 } },
2962 & fmt_bra8r, { 0x7f00 },
2963 (PTR) 0,
2964 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2965 },
2966 /* bra $disp24 */
2967 {
2968 { 1, 1, 1, 1 },
2969 -1, "bra24r", "bra",
2970 { { MNEM, ' ', OP (DISP24), 0 } },
2971 & fmt_bra24r, { 0xff000000 },
2972 (PTR) 0,
2973 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2974 },
2975 /* start-sanitize-m32rx */
2976 /* bncl $disp8 */
2977 {
2978 { 1, 1, 1, 1 },
2979 -1, "bncl8r", "bncl",
2980 { { MNEM, ' ', OP (DISP8), 0 } },
2981 & fmt_bncl8r, { 0x7900 },
2982 (PTR) 0,
2983 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2984 },
2985 /* end-sanitize-m32rx */
2986 /* start-sanitize-m32rx */
2987 /* bncl $disp24 */
2988 {
2989 { 1, 1, 1, 1 },
2990 -1, "bncl24r", "bncl",
2991 { { MNEM, ' ', OP (DISP24), 0 } },
2992 & fmt_bncl24r, { 0xf9000000 },
2993 (PTR) 0,
2994 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2995 },
2996 /* end-sanitize-m32rx */
2997 /* ld $dr,@($sr) */
2998 {
2999 { 1, 1, 1, 1 },
3000 -1, "ld-2", "ld",
3001 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
3002 & fmt_ld_2, { 0x20c0 },
3003 (PTR) 0,
3004 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3005 },
3006 /* ld $dr,@($sr,$slo16) */
3007 {
3008 { 1, 1, 1, 1 },
3009 -1, "ld-d2", "ld",
3010 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
3011 & fmt_ld_d2, { 0xa0c00000 },
3012 (PTR) 0,
3013 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3014 },
3015 /* ldb $dr,@($sr) */
3016 {
3017 { 1, 1, 1, 1 },
3018 -1, "ldb-2", "ldb",
3019 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
3020 & fmt_ldb_2, { 0x2080 },
3021 (PTR) 0,
3022 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3023 },
3024 /* ldb $dr,@($sr,$slo16) */
3025 {
3026 { 1, 1, 1, 1 },
3027 -1, "ldb-d2", "ldb",
3028 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
3029 & fmt_ldb_d2, { 0xa0800000 },
3030 (PTR) 0,
3031 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3032 },
3033 /* ldh $dr,@($sr) */
3034 {
3035 { 1, 1, 1, 1 },
3036 -1, "ldh-2", "ldh",
3037 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
3038 & fmt_ldh_2, { 0x20a0 },
3039 (PTR) 0,
3040 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3041 },
3042 /* ldh $dr,@($sr,$slo16) */
3043 {
3044 { 1, 1, 1, 1 },
3045 -1, "ldh-d2", "ldh",
3046 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
3047 & fmt_ldh_d2, { 0xa0a00000 },
3048 (PTR) 0,
3049 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3050 },
3051 /* ldub $dr,@($sr) */
3052 {
3053 { 1, 1, 1, 1 },
3054 -1, "ldub-2", "ldub",
3055 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
3056 & fmt_ldub_2, { 0x2090 },
3057 (PTR) 0,
3058 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3059 },
3060 /* ldub $dr,@($sr,$slo16) */
3061 {
3062 { 1, 1, 1, 1 },
3063 -1, "ldub-d2", "ldub",
3064 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
3065 & fmt_ldub_d2, { 0xa0900000 },
3066 (PTR) 0,
3067 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3068 },
3069 /* lduh $dr,@($sr) */
3070 {
3071 { 1, 1, 1, 1 },
3072 -1, "lduh-2", "lduh",
3073 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
3074 & fmt_lduh_2, { 0x20b0 },
3075 (PTR) 0,
3076 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3077 },
3078 /* lduh $dr,@($sr,$slo16) */
3079 {
3080 { 1, 1, 1, 1 },
3081 -1, "lduh-d2", "lduh",
3082 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
3083 & fmt_lduh_d2, { 0xa0b00000 },
3084 (PTR) 0,
3085 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3086 },
3087 /* pop $dr */
3088 {
3089 { 1, 1, 1, 1 },
3090 -1, "pop", "pop",
3091 { { MNEM, ' ', OP (DR), 0 } },
3092 & fmt_pop, { 0x20ef },
3093 (PTR) 0,
3094 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3095 },
3096 /* ldi $dr,$simm8 */
3097 {
3098 { 1, 1, 1, 1 },
3099 -1, "ldi8a", "ldi",
3100 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
3101 & fmt_ldi8a, { 0x6000 },
3102 (PTR) 0,
3103 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
3104 },
3105 /* ldi $dr,$hash$slo16 */
3106 {
3107 { 1, 1, 1, 1 },
3108 -1, "ldi16a", "ldi",
3109 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
3110 & fmt_ldi16a, { 0x90f00000 },
3111 (PTR) 0,
3112 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3113 },
3114 /* start-sanitize-m32rx */
3115 /* rac $accd */
3116 {
3117 { 1, 1, 1, 1 },
3118 -1, "rac-d", "rac",
3119 { { MNEM, ' ', OP (ACCD), 0 } },
3120 & fmt_rac_d, { 0x5090 },
3121 (PTR) 0,
3122 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3123 },
3124 /* end-sanitize-m32rx */
3125 /* start-sanitize-m32rx */
3126 /* rac $accd,$accs */
3127 {
3128 { 1, 1, 1, 1 },
3129 -1, "rac-ds", "rac",
3130 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
3131 & fmt_rac_ds, { 0x5090 },
3132 (PTR) 0,
3133 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3134 },
3135 /* end-sanitize-m32rx */
3136 /* start-sanitize-m32rx */
3137 /* rach $accd */
3138 {
3139 { 1, 1, 1, 1 },
3140 -1, "rach-d", "rach",
3141 { { MNEM, ' ', OP (ACCD), 0 } },
3142 & fmt_rach_d, { 0x5080 },
3143 (PTR) 0,
3144 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3145 },
3146 /* end-sanitize-m32rx */
3147 /* start-sanitize-m32rx */
3148 /* rach $accd,$accs */
3149 {
3150 { 1, 1, 1, 1 },
3151 -1, "rach-ds", "rach",
3152 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
3153 & fmt_rach_ds, { 0x5080 },
3154 (PTR) 0,
3155 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
3156 },
3157 /* end-sanitize-m32rx */
3158 /* st $src1,@($src2) */
3159 {
3160 { 1, 1, 1, 1 },
3161 -1, "st-2", "st",
3162 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
3163 & fmt_st_2, { 0x2040 },
3164 (PTR) 0,
3165 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3166 },
3167 /* st $src1,@($src2,$slo16) */
3168 {
3169 { 1, 1, 1, 1 },
3170 -1, "st-d2", "st",
3171 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
3172 & fmt_st_d2, { 0xa0400000 },
3173 (PTR) 0,
3174 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3175 },
3176 /* stb $src1,@($src2) */
3177 {
3178 { 1, 1, 1, 1 },
3179 -1, "stb-2", "stb",
3180 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
3181 & fmt_stb_2, { 0x2000 },
3182 (PTR) 0,
3183 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3184 },
3185 /* stb $src1,@($src2,$slo16) */
3186 {
3187 { 1, 1, 1, 1 },
3188 -1, "stb-d2", "stb",
3189 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
3190 & fmt_stb_d2, { 0xa0000000 },
3191 (PTR) 0,
3192 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3193 },
3194 /* sth $src1,@($src2) */
3195 {
3196 { 1, 1, 1, 1 },
3197 -1, "sth-2", "sth",
3198 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
3199 & fmt_sth_2, { 0x2020 },
3200 (PTR) 0,
3201 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
3202 },
3203 /* sth $src1,@($src2,$slo16) */
3204 {
3205 { 1, 1, 1, 1 },
3206 -1, "sth-d2", "sth",
3207 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
3208 & fmt_sth_d2, { 0xa0200000 },
3209 (PTR) 0,
3210 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3211 },
3212 /* push $src1 */
3213 {
3214 { 1, 1, 1, 1 },
3215 -1, "push", "push",
3216 { { MNEM, ' ', OP (SRC1), 0 } },
3217 & fmt_push, { 0x207f },
3218 (PTR) 0,
3219 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
3220 },
3221 };
3222
3223 #undef A
3224 #undef MNEM
3225 #undef OP
3226
3227 static const CGEN_INSN_TABLE macro_insn_table =
3228 {
3229 & macro_insn_table_entries[0],
3230 sizeof (CGEN_INSN),
3231 (sizeof (macro_insn_table_entries) /
3232 sizeof (macro_insn_table_entries[0])),
3233 NULL
3234 };
3235
3236 static void
3237 init_tables ()
3238 {
3239 }
3240
3241 /* Return non-zero if INSN is to be added to the hash table.
3242 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3243
3244 static int
3245 asm_hash_insn_p (insn)
3246 const CGEN_INSN * insn;
3247 {
3248 return CGEN_ASM_HASH_P (insn);
3249 }
3250
3251 static int
3252 dis_hash_insn_p (insn)
3253 const CGEN_INSN * insn;
3254 {
3255 /* If building the hash table and the NO-DIS attribute is present,
3256 ignore. */
3257 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3258 return 0;
3259 return CGEN_DIS_HASH_P (insn);
3260 }
3261
3262 /* The result is the hash value of the insn.
3263 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3264
3265 static unsigned int
3266 asm_hash_insn (mnem)
3267 const char * mnem;
3268 {
3269 return CGEN_ASM_HASH (mnem);
3270 }
3271
3272 /* BUF is a pointer to the insn's bytes in target order.
3273 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3274 host order. */
3275
3276 static unsigned int
3277 dis_hash_insn (buf, value)
3278 const char * buf;
3279 CGEN_INSN_INT value;
3280 {
3281 return CGEN_DIS_HASH (buf, value);
3282 }
3283
3284 /* Initialize an opcode table and return a descriptor.
3285 It's much like opening a file, and must be the first function called. */
3286
3287 CGEN_OPCODE_DESC
3288 m32r_cgen_opcode_open (mach, endian)
3289 int mach;
3290 enum cgen_endian endian;
3291 {
3292 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3293 static int init_p;
3294
3295 if (! init_p)
3296 {
3297 init_tables ();
3298 init_p = 1;
3299 }
3300
3301 memset (table, 0, sizeof (*table));
3302
3303 CGEN_OPCODE_MACH (table) = mach;
3304 CGEN_OPCODE_ENDIAN (table) = endian;
3305 /* FIXME: for the sparc case we can determine insn-endianness statically.
3306 The worry here is where both data and insn endian can be independently
3307 chosen, in which case this function will need another argument.
3308 Actually, will want to allow for more arguments in the future anyway. */
3309 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3310
3311 CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
3312
3313 CGEN_OPCODE_IFLD_TABLE (table) = & m32r_cgen_ifld_table[0];
3314
3315 CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
3316
3317 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3318
3319 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3320
3321 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3322 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3323 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3324
3325 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3326 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3327 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3328
3329 return (CGEN_OPCODE_DESC) table;
3330 }
3331
3332 /* Close an opcode table. */
3333
3334 void
3335 m32r_cgen_opcode_close (desc)
3336 CGEN_OPCODE_DESC desc;
3337 {
3338 free (desc);
3339 }
3340
3341 /* Getting values from cgen_fields is handled by a collection of functions.
3342 They are distinguished by the type of the VALUE argument they return.
3343 TODO: floating point, inlining support, remove cases where result type
3344 not appropriate. */
3345
3346 int
3347 m32r_cgen_get_int_operand (opindex, fields)
3348 int opindex;
3349 const CGEN_FIELDS * fields;
3350 {
3351 int value;
3352
3353 switch (opindex)
3354 {
3355 case M32R_OPERAND_SR :
3356 value = fields->f_r2;
3357 break;
3358 case M32R_OPERAND_DR :
3359 value = fields->f_r1;
3360 break;
3361 case M32R_OPERAND_SRC1 :
3362 value = fields->f_r1;
3363 break;
3364 case M32R_OPERAND_SRC2 :
3365 value = fields->f_r2;
3366 break;
3367 case M32R_OPERAND_SCR :
3368 value = fields->f_r2;
3369 break;
3370 case M32R_OPERAND_DCR :
3371 value = fields->f_r1;
3372 break;
3373 case M32R_OPERAND_SIMM8 :
3374 value = fields->f_simm8;
3375 break;
3376 case M32R_OPERAND_SIMM16 :
3377 value = fields->f_simm16;
3378 break;
3379 case M32R_OPERAND_UIMM4 :
3380 value = fields->f_uimm4;
3381 break;
3382 case M32R_OPERAND_UIMM5 :
3383 value = fields->f_uimm5;
3384 break;
3385 case M32R_OPERAND_UIMM16 :
3386 value = fields->f_uimm16;
3387 break;
3388 /* start-sanitize-m32rx */
3389 case M32R_OPERAND_IMM1 :
3390 value = fields->f_imm1;
3391 break;
3392 /* end-sanitize-m32rx */
3393 /* start-sanitize-m32rx */
3394 case M32R_OPERAND_ACCD :
3395 value = fields->f_accd;
3396 break;
3397 /* end-sanitize-m32rx */
3398 /* start-sanitize-m32rx */
3399 case M32R_OPERAND_ACCS :
3400 value = fields->f_accs;
3401 break;
3402 /* end-sanitize-m32rx */
3403 /* start-sanitize-m32rx */
3404 case M32R_OPERAND_ACC :
3405 value = fields->f_acc;
3406 break;
3407 /* end-sanitize-m32rx */
3408 case M32R_OPERAND_HASH :
3409 value = fields->f_nil;
3410 break;
3411 case M32R_OPERAND_HI16 :
3412 value = fields->f_hi16;
3413 break;
3414 case M32R_OPERAND_SLO16 :
3415 value = fields->f_simm16;
3416 break;
3417 case M32R_OPERAND_ULO16 :
3418 value = fields->f_uimm16;
3419 break;
3420 case M32R_OPERAND_UIMM24 :
3421 value = fields->f_uimm24;
3422 break;
3423 case M32R_OPERAND_DISP8 :
3424 value = fields->f_disp8;
3425 break;
3426 case M32R_OPERAND_DISP16 :
3427 value = fields->f_disp16;
3428 break;
3429 case M32R_OPERAND_DISP24 :
3430 value = fields->f_disp24;
3431 break;
3432
3433 default :
3434 /* xgettext:c-format */
3435 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3436 opindex);
3437 abort ();
3438 }
3439
3440 return value;
3441 }
3442
3443 bfd_vma
3444 m32r_cgen_get_vma_operand (opindex, fields)
3445 int opindex;
3446 const CGEN_FIELDS * fields;
3447 {
3448 bfd_vma value;
3449
3450 switch (opindex)
3451 {
3452 case M32R_OPERAND_SR :
3453 value = fields->f_r2;
3454 break;
3455 case M32R_OPERAND_DR :
3456 value = fields->f_r1;
3457 break;
3458 case M32R_OPERAND_SRC1 :
3459 value = fields->f_r1;
3460 break;
3461 case M32R_OPERAND_SRC2 :
3462 value = fields->f_r2;
3463 break;
3464 case M32R_OPERAND_SCR :
3465 value = fields->f_r2;
3466 break;
3467 case M32R_OPERAND_DCR :
3468 value = fields->f_r1;
3469 break;
3470 case M32R_OPERAND_SIMM8 :
3471 value = fields->f_simm8;
3472 break;
3473 case M32R_OPERAND_SIMM16 :
3474 value = fields->f_simm16;
3475 break;
3476 case M32R_OPERAND_UIMM4 :
3477 value = fields->f_uimm4;
3478 break;
3479 case M32R_OPERAND_UIMM5 :
3480 value = fields->f_uimm5;
3481 break;
3482 case M32R_OPERAND_UIMM16 :
3483 value = fields->f_uimm16;
3484 break;
3485 /* start-sanitize-m32rx */
3486 case M32R_OPERAND_IMM1 :
3487 value = fields->f_imm1;
3488 break;
3489 /* end-sanitize-m32rx */
3490 /* start-sanitize-m32rx */
3491 case M32R_OPERAND_ACCD :
3492 value = fields->f_accd;
3493 break;
3494 /* end-sanitize-m32rx */
3495 /* start-sanitize-m32rx */
3496 case M32R_OPERAND_ACCS :
3497 value = fields->f_accs;
3498 break;
3499 /* end-sanitize-m32rx */
3500 /* start-sanitize-m32rx */
3501 case M32R_OPERAND_ACC :
3502 value = fields->f_acc;
3503 break;
3504 /* end-sanitize-m32rx */
3505 case M32R_OPERAND_HASH :
3506 value = fields->f_nil;
3507 break;
3508 case M32R_OPERAND_HI16 :
3509 value = fields->f_hi16;
3510 break;
3511 case M32R_OPERAND_SLO16 :
3512 value = fields->f_simm16;
3513 break;
3514 case M32R_OPERAND_ULO16 :
3515 value = fields->f_uimm16;
3516 break;
3517 case M32R_OPERAND_UIMM24 :
3518 value = fields->f_uimm24;
3519 break;
3520 case M32R_OPERAND_DISP8 :
3521 value = fields->f_disp8;
3522 break;
3523 case M32R_OPERAND_DISP16 :
3524 value = fields->f_disp16;
3525 break;
3526 case M32R_OPERAND_DISP24 :
3527 value = fields->f_disp24;
3528 break;
3529
3530 default :
3531 /* xgettext:c-format */
3532 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3533 opindex);
3534 abort ();
3535 }
3536
3537 return value;
3538 }
3539
3540 /* Stuffing values in cgen_fields is handled by a collection of functions.
3541 They are distinguished by the type of the VALUE argument they accept.
3542 TODO: floating point, inlining support, remove cases where argument type
3543 not appropriate. */
3544
3545 void
3546 m32r_cgen_set_int_operand (opindex, fields, value)
3547 int opindex;
3548 CGEN_FIELDS * fields;
3549 int value;
3550 {
3551 switch (opindex)
3552 {
3553 case M32R_OPERAND_SR :
3554 fields->f_r2 = value;
3555 break;
3556 case M32R_OPERAND_DR :
3557 fields->f_r1 = value;
3558 break;
3559 case M32R_OPERAND_SRC1 :
3560 fields->f_r1 = value;
3561 break;
3562 case M32R_OPERAND_SRC2 :
3563 fields->f_r2 = value;
3564 break;
3565 case M32R_OPERAND_SCR :
3566 fields->f_r2 = value;
3567 break;
3568 case M32R_OPERAND_DCR :
3569 fields->f_r1 = value;
3570 break;
3571 case M32R_OPERAND_SIMM8 :
3572 fields->f_simm8 = value;
3573 break;
3574 case M32R_OPERAND_SIMM16 :
3575 fields->f_simm16 = value;
3576 break;
3577 case M32R_OPERAND_UIMM4 :
3578 fields->f_uimm4 = value;
3579 break;
3580 case M32R_OPERAND_UIMM5 :
3581 fields->f_uimm5 = value;
3582 break;
3583 case M32R_OPERAND_UIMM16 :
3584 fields->f_uimm16 = value;
3585 break;
3586 /* start-sanitize-m32rx */
3587 case M32R_OPERAND_IMM1 :
3588 fields->f_imm1 = value;
3589 break;
3590 /* end-sanitize-m32rx */
3591 /* start-sanitize-m32rx */
3592 case M32R_OPERAND_ACCD :
3593 fields->f_accd = value;
3594 break;
3595 /* end-sanitize-m32rx */
3596 /* start-sanitize-m32rx */
3597 case M32R_OPERAND_ACCS :
3598 fields->f_accs = value;
3599 break;
3600 /* end-sanitize-m32rx */
3601 /* start-sanitize-m32rx */
3602 case M32R_OPERAND_ACC :
3603 fields->f_acc = value;
3604 break;
3605 /* end-sanitize-m32rx */
3606 case M32R_OPERAND_HASH :
3607 fields->f_nil = value;
3608 break;
3609 case M32R_OPERAND_HI16 :
3610 fields->f_hi16 = value;
3611 break;
3612 case M32R_OPERAND_SLO16 :
3613 fields->f_simm16 = value;
3614 break;
3615 case M32R_OPERAND_ULO16 :
3616 fields->f_uimm16 = value;
3617 break;
3618 case M32R_OPERAND_UIMM24 :
3619 fields->f_uimm24 = value;
3620 break;
3621 case M32R_OPERAND_DISP8 :
3622 fields->f_disp8 = value;
3623 break;
3624 case M32R_OPERAND_DISP16 :
3625 fields->f_disp16 = value;
3626 break;
3627 case M32R_OPERAND_DISP24 :
3628 fields->f_disp24 = value;
3629 break;
3630
3631 default :
3632 /* xgettext:c-format */
3633 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3634 opindex);
3635 abort ();
3636 }
3637 }
3638
3639 void
3640 m32r_cgen_set_vma_operand (opindex, fields, value)
3641 int opindex;
3642 CGEN_FIELDS * fields;
3643 bfd_vma value;
3644 {
3645 switch (opindex)
3646 {
3647 case M32R_OPERAND_SR :
3648 fields->f_r2 = value;
3649 break;
3650 case M32R_OPERAND_DR :
3651 fields->f_r1 = value;
3652 break;
3653 case M32R_OPERAND_SRC1 :
3654 fields->f_r1 = value;
3655 break;
3656 case M32R_OPERAND_SRC2 :
3657 fields->f_r2 = value;
3658 break;
3659 case M32R_OPERAND_SCR :
3660 fields->f_r2 = value;
3661 break;
3662 case M32R_OPERAND_DCR :
3663 fields->f_r1 = value;
3664 break;
3665 case M32R_OPERAND_SIMM8 :
3666 fields->f_simm8 = value;
3667 break;
3668 case M32R_OPERAND_SIMM16 :
3669 fields->f_simm16 = value;
3670 break;
3671 case M32R_OPERAND_UIMM4 :
3672 fields->f_uimm4 = value;
3673 break;
3674 case M32R_OPERAND_UIMM5 :
3675 fields->f_uimm5 = value;
3676 break;
3677 case M32R_OPERAND_UIMM16 :
3678 fields->f_uimm16 = value;
3679 break;
3680 /* start-sanitize-m32rx */
3681 case M32R_OPERAND_IMM1 :
3682 fields->f_imm1 = value;
3683 break;
3684 /* end-sanitize-m32rx */
3685 /* start-sanitize-m32rx */
3686 case M32R_OPERAND_ACCD :
3687 fields->f_accd = value;
3688 break;
3689 /* end-sanitize-m32rx */
3690 /* start-sanitize-m32rx */
3691 case M32R_OPERAND_ACCS :
3692 fields->f_accs = value;
3693 break;
3694 /* end-sanitize-m32rx */
3695 /* start-sanitize-m32rx */
3696 case M32R_OPERAND_ACC :
3697 fields->f_acc = value;
3698 break;
3699 /* end-sanitize-m32rx */
3700 case M32R_OPERAND_HASH :
3701 fields->f_nil = value;
3702 break;
3703 case M32R_OPERAND_HI16 :
3704 fields->f_hi16 = value;
3705 break;
3706 case M32R_OPERAND_SLO16 :
3707 fields->f_simm16 = value;
3708 break;
3709 case M32R_OPERAND_ULO16 :
3710 fields->f_uimm16 = value;
3711 break;
3712 case M32R_OPERAND_UIMM24 :
3713 fields->f_uimm24 = value;
3714 break;
3715 case M32R_OPERAND_DISP8 :
3716 fields->f_disp8 = value;
3717 break;
3718 case M32R_OPERAND_DISP16 :
3719 fields->f_disp16 = value;
3720 break;
3721 case M32R_OPERAND_DISP24 :
3722 fields->f_disp24 = value;
3723 break;
3724
3725 default :
3726 /* xgettext:c-format */
3727 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3728 opindex);
3729 abort ();
3730 }
3731 }
3732
GDB Binutils - Deliverables
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