opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 This file is used to generate m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software
  22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31
  32 /* Look up instruction INSN_VALUE and extract its fields.
  33    If non-null INSN is the insn table entry.
  34    Otherwise INSN_VALUE is examined to compute it.
  35    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  36    ALIAS_P is non-zero if alias insns are to be included in the search.
  37    The result a pointer to the insn table entry, or NULL if the instruction
  38    wasn't recognized.  */
  39
  40 const CGEN_INSN *
  41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  42      const CGEN_INSN *insn;
  43      cgen_insn_t insn_value;
  44      int length;
  45      CGEN_FIELDS *fields;
  46 {
  47   char buf[16];
  48
  49   if (!insn)
  50     {
  51       const CGEN_INSN_LIST *insn_list;
  52
  53 #ifdef CGEN_INT_INSN
  54       switch (length)
  55         {
  56         case 8:
  57           buf[0] = insn_value;
  58           break;
  59         case 16:
  60           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  61             bfd_putb16 (insn_value, buf);
  62           else
  63             bfd_putl16 (insn_value, buf);
  64           break;
  65         case 32:
  66           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  67             bfd_putb32 (insn_value, buf);
  68           else
  69             bfd_putl32 (insn_value, buf);
  70           break;
  71         default:
  72           abort ();
  73         }
  74 #else
  75       abort (); /* FIXME: unfinished */
  76 #endif
  77
  78       /* The instructions are stored in hash lists.
  79          Pick the first one and keep trying until we find the right one.  */
  80
  81       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  82       while (insn_list != NULL)
  83         {
  84           insn = insn_list->insn;
  85
  86           if (alias_p
  87               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  88             {
  89               /* Basic bit mask must be correct.  */
  90               /* ??? May wish to allow target to defer this check until the
  91                  extract handler.  */
  92               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  93                 {
  94                   length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
  95                   if (length > 0)
  96                     return insn;
  97                 }
  98             }
  99
 100           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 101         }
 102     }
 103   else
 104     {
 105       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 106       if (! alias_p
 107           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 108         abort ();
 109
 110       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
 111       if (length > 0)
 112         return insn;
 113     }
 114
 115   return NULL;
 116 }
 117
 118 /* Fill in the operand instances used by insn INSN_VALUE.
 119    If non-null INS is the insn table entry.
 120    Otherwise INSN_VALUE is examined to compute it.
 121    LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
 122    INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
 123    The result a pointer to the insn table entry, or NULL if the instruction
 124    wasn't recognized.  */
 125
 126 const CGEN_INSN *
 127 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
 128      const CGEN_INSN *insn;
 129      cgen_insn_t insn_value;
 130      int length;
 131      int *indices;
 132 {
 133   CGEN_FIELDS fields;
 134   const CGEN_OPERAND_INSTANCE *opinst;
 135   int i;
 136
 137   /* FIXME: ALIAS insns are in transition from being record in the insn table
 138      to being recorded separately as macros.  They don't have semantic code
 139      so they can't be used here.  Thus we currently always ignore the INSN
 140      argument.  */
 141   insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
 142   if (! insn)
 143     return NULL;
 144
 145   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 146        CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 147        ++i, ++opinst)
 148     {
 149       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 150       if (op == NULL)
 151         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 152       else
 153         indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
 154     }
 155
 156   return insn;
 157 }
 158 /* Attributes.  */
 159
 160 static const CGEN_ATTR_ENTRY MACH_attr[] =
 161 {
 162   { "m32r", MACH_M32R },
 163 /* start-sanitize-m32rx */
 164   { "m32rx", MACH_M32RX },
 165 /* end-sanitize-m32rx */
 166   { "max", MACH_MAX },
 167   { 0, 0 }
 168 };
 169
 170 /* start-sanitize-m32rx */
 171 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 172 {
 173   { "NONE", PIPE_NONE },
 174   { "O", PIPE_O },
 175   { "S", PIPE_S },
 176   { "OS", PIPE_OS },
 177   { 0, 0 }
 178 };
 179
 180 /* end-sanitize-m32rx */
 181 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 182 {
 183   { "ABS-ADDR", NULL },
 184   { "FAKE", NULL },
 185   { "NEGATIVE", NULL },
 186   { "PC", NULL },
 187   { "PCREL-ADDR", NULL },
 188   { "RELAX", NULL },
 189   { "RELOC", NULL },
 190   { "SIGN-OPT", NULL },
 191   { "UNSIGNED", NULL },
 192   { 0, 0 }
 193 };
 194
 195 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 196 {
 197   { "MACH", & MACH_attr[0] },
 198 /* start-sanitize-m32rx */
 199   { "PIPE", & PIPE_attr[0] },
 200 /* end-sanitize-m32rx */
 201   { "ALIAS", NULL },
 202   { "COND-CTI", NULL },
 203   { "FILL-SLOT", NULL },
 204   { "PARALLEL", NULL },
 205   { "RELAX", NULL },
 206   { "RELAXABLE", NULL },
 207   { "UNCOND-CTI", NULL },
 208   { 0, 0 }
 209 };
 210
 211 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 212 {
 213   { "fp", 13 },
 214   { "lr", 14 },
 215   { "sp", 15 },
 216   { "r0", 0 },
 217   { "r1", 1 },
 218   { "r2", 2 },
 219   { "r3", 3 },
 220   { "r4", 4 },
 221   { "r5", 5 },
 222   { "r6", 6 },
 223   { "r7", 7 },
 224   { "r8", 8 },
 225   { "r9", 9 },
 226   { "r10", 10 },
 227   { "r11", 11 },
 228   { "r12", 12 },
 229   { "r13", 13 },
 230   { "r14", 14 },
 231   { "r15", 15 }
 232 };
 233
 234 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 235 {
 236   & m32r_cgen_opval_h_gr_entries[0],
 237   19
 238 };
 239
 240 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 241 {
 242   { "psw", 0 },
 243   { "cbr", 1 },
 244   { "spi", 2 },
 245   { "spu", 3 },
 246   { "bpc", 6 },
 247   { "cr0", 0 },
 248   { "cr1", 1 },
 249   { "cr2", 2 },
 250   { "cr3", 3 },
 251   { "cr4", 4 },
 252   { "cr5", 5 },
 253   { "cr6", 6 }
 254 };
 255
 256 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 257 {
 258   & m32r_cgen_opval_h_cr_entries[0],
 259   12
 260 };
 261
 262 /* start-sanitize-m32rx */
 263 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 264 {
 265   { "a0", 0 },
 266   { "a1", 1 }
 267 };
 268
 269 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 270 {
 271   & m32r_cgen_opval_h_accums_entries[0],
 272   2
 273 };
 274
 275 /* end-sanitize-m32rx */
 276
 277 /* The hardware table.  */
 278
 279 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 280 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 281 {
 282   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 283   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 284   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 285   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 286   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 287   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 288   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 289   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 290   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 291   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 292   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 293   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 294 /* start-sanitize-m32rx */
 295   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 296 /* end-sanitize-m32rx */
 297 /* start-sanitize-m32rx */
 298   { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
 299 /* end-sanitize-m32rx */
 300   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 301   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 302   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 303   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 304   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 305   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 306   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 307   { 0 }
 308 };
 309
 310 /* The operand table.  */
 311
 312 #define OP_ENT(op) m32r_cgen_operand_table[CONCAT2 (M32R_OPERAND_,op)]
 313 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 314 {
 315 /* pc: program counter */
 316   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 317     { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 318 /* sr: source register */
 319   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 320     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 321 /* dr: destination register */
 322   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 323     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 324 /* src1: source register 1 */
 325   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 326     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 327 /* src2: source register 2 */
 328   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 329     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 330 /* scr: source control register */
 331   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 332     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 333 /* dcr: destination control register */
 334   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 335     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 336 /* simm8: 8 bit signed immediate */
 337   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 338     { 0, 0, { 0 } }  },
 339 /* simm16: 16 bit signed immediate */
 340   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 341     { 0, 0, { 0 } }  },
 342 /* uimm4: 4 bit trap number */
 343   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 344     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 345 /* uimm5: 5 bit shift count */
 346   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 347     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 348 /* uimm16: 16 bit unsigned immediate */
 349   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 350     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 351 /* start-sanitize-m32rx */
 352 /* imm1: 1 bit immediate */
 353   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 354     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 355 /* end-sanitize-m32rx */
 356 /* start-sanitize-m32rx */
 357 /* accd: accumulator destination register */
 358   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 359     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 360 /* end-sanitize-m32rx */
 361 /* start-sanitize-m32rx */
 362 /* accs: accumulator source register */
 363   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 364     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 365 /* end-sanitize-m32rx */
 366 /* start-sanitize-m32rx */
 367 /* acc: accumulator reg (d) */
 368   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 369     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 370 /* end-sanitize-m32rx */
 371 /* hi16: high 16 bit immediate, sign optional */
 372   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 373     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 374 /* slo16: 16 bit signed immediate, for low() */
 375   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 376     { 0, 0, { 0 } }  },
 377 /* ulo16: 16 bit unsigned immediate, for low() */
 378   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 379     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 380 /* uimm24: 24 bit address */
 381   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 382     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 383 /* disp8: 8 bit displacement */
 384   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 385     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 386 /* disp16: 16 bit displacement */
 387   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 388     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 389 /* disp24: 24 bit displacement */
 390   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 391     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 392 /* condbit: condition bit */
 393   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 394     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 395 /* accum: accumulator */
 396   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 397     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 398 /* start-sanitize-m32rx */
 399 /* abort-parallel-execution: abort parallel execution */
 400   { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
 401     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 402 /* end-sanitize-m32rx */
 403 };
 404
 405 /* Operand references.  */
 406
 407 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 408 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 409
 410 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
 411   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 412   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 413   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 414   { 0 }
 415 };
 416
 417 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
 418   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 419   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 420   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 421   { 0 }
 422 };
 423
 424 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
 425   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 426   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 427   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 428   { 0 }
 429 };
 430
 431 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
 432   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 433   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 434   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 435   { 0 }
 436 };
 437
 438 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
 439   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 440   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 441   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 442   { 0 }
 443 };
 444
 445 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
 446   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 447   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 448   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 449   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 450   { 0 }
 451 };
 452
 453 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
 454   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 455   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 456   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 457   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 458   { 0 }
 459 };
 460
 461 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
 462   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 463   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 464   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 465   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 466   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 467   { 0 }
 468 };
 469
 470 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
 471   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 472   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 473   { 0 }
 474 };
 475
 476 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
 477   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 478   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 479   { 0 }
 480 };
 481
 482 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
 483   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 484   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 485   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 486   { 0 }
 487 };
 488
 489 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
 490   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 491   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 492   { 0 }
 493 };
 494
 495 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
 496   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 497   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 498   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 499   { 0 }
 500 };
 501
 502 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
 503   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 504   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 505   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 506   { 0 }
 507 };
 508
 509 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
 510   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 511   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 512   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 513   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 514   { 0 }
 515 };
 516
 517 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
 518   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 519   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 520   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 521   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 522   { 0 }
 523 };
 524
 525 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
 526   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 527   { 0 }
 528 };
 529
 530 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
 531   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 532   { 0 }
 533 };
 534
 535 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
 536   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 537   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 538   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 539   { 0 }
 540 };
 541
 542 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
 543   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 544   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 545   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 546   { 0 }
 547 };
 548
 549 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
 550   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 551   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 552   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 553   { 0 }
 554 };
 555
 556 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
 557   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 558   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 559   { 0 }
 560 };
 561
 562 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
 563   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 564   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 565   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 566   { 0 }
 567 };
 568
 569 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
 570   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 571   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 572   { 0 }
 573 };
 574
 575 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
 576   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 577   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 578   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 579   { 0 }
 580 };
 581
 582 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
 583   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 584   { 0 }
 585 };
 586
 587 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
 588   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 589   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 590   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 591   { 0 }
 592 };
 593
 594 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
 595   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 596   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 597   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 598   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 599   { 0 }
 600 };
 601
 602 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
 603   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 604   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 605   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 606   { 0 }
 607 };
 608
 609 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
 610   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 611   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 612   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 613   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 614   { 0 }
 615 };
 616
 617 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
 618   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 619   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 620   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 621   { 0 }
 622 };
 623
 624 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
 625   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 626   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 627   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 628   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 629   { 0 }
 630 };
 631
 632 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
 633   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 634   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 635   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 636   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 637   { 0 }
 638 };
 639
 640 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
 641   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
 642   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 643   { 0 }
 644 };
 645
 646 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
 647   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 648   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 649   { 0 }
 650 };
 651
 652 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
 653   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 654   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 655   { 0 }
 656 };
 657
 658 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
 659   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 660   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 661   { 0 }
 662 };
 663
 664 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
 665   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 666   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 667   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 668   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 669   { 0 }
 670 };
 671
 672 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
 673   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 674   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 675   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 676   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 677   { 0 }
 678 };
 679
 680 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
 681   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 682   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 683   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 684   { 0 }
 685 };
 686
 687 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
 688   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 689   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 690   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 691   { 0 }
 692 };
 693
 694 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
 695   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 696   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 697   { 0 }
 698 };
 699
 700 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
 701   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 702   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 703   { 0 }
 704 };
 705
 706 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
 707   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 708   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 709   { 0 }
 710 };
 711
 712 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
 713   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (SCR), 0 },
 714   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 715   { 0 }
 716 };
 717
 718 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
 719   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 720   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 721   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 722   { 0 }
 723 };
 724
 725 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
 726   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 727   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 728   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 729   { 0 }
 730 };
 731
 732 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
 733   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 734   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (DCR), 0 },
 735   { 0 }
 736 };
 737
 738 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
 739   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 740   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 741   { 0 }
 742 };
 743
 744 static const CGEN_OPERAND_INSTANCE fmt_54_rac_d_ops[] = {
 745   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 746   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 747   { 0 }
 748 };
 749
 750 static const CGEN_OPERAND_INSTANCE fmt_55_rac_ds_ops[] = {
 751   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 752   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 753   { 0 }
 754 };
 755
 756 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
 757   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 758   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 759   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 760   { 0 }
 761 };
 762
 763 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
 764   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
 765   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
 766   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
 767   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
 768   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 769   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 770   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
 771   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
 772   { 0 }
 773 };
 774
 775 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
 776   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
 777   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 778   { 0 }
 779 };
 780
 781 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
 782   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 783   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 784   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 785   { 0 }
 786 };
 787
 788 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
 789   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 790   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 791   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 792   { 0 }
 793 };
 794
 795 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
 796   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 797   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 798   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 799   { 0 }
 800 };
 801
 802 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
 803   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 804   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 805   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 806   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 807   { 0 }
 808 };
 809
 810 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
 811   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 812   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 813   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 814   { 0 }
 815 };
 816
 817 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
 818   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 819   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 820   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 821   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 822   { 0 }
 823 };
 824
 825 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
 826   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 827   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 828   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 829   { 0 }
 830 };
 831
 832 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
 833   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 834   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 835   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 836   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 837   { 0 }
 838 };
 839
 840 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
 841   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 842   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 843   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 844   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 845   { 0 }
 846 };
 847
 848 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
 849   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
 850   { 0 }
 851 };
 852
 853 static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
 854   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 855   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 856   { 0 }
 857 };
 858
 859 static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
 860   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 861   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 862   { 0 }
 863 };
 864
 865 static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
 866   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 867   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 868   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 869   { 0 }
 870 };
 871
 872 static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
 873   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 874   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 875   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 876   { 0 }
 877 };
 878
 879 static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
 880   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 881   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 882   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 883   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 884   { 0 }
 885 };
 886
 887 static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
 888   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 889   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 890   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 891   { 0 }
 892 };
 893
 894 static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
 895   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 896   { OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, 0, 0 },
 897   { 0 }
 898 };
 899
 900 #undef INPUT
 901 #undef OUTPUT
 902
 903 #define OP 1 /* syntax value for mnemonic */
 904
 905 static const CGEN_SYNTAX syntax_table[] =
 906 {
 907 /* <op> $dr,$sr */
 908 /*   0 */  { OP, ' ', 130, ',', 129, 0 },
 909 /* <op> $dr,$sr,#$slo16 */
 910 /*   1 */  { OP, ' ', 130, ',', 129, ',', '#', 145, 0 },
 911 /* <op> $dr,$sr,$slo16 */
 912 /*   2 */  { OP, ' ', 130, ',', 129, ',', 145, 0 },
 913 /* <op> $dr,$sr,#$uimm16 */
 914 /*   3 */  { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
 915 /* <op> $dr,$sr,$uimm16 */
 916 /*   4 */  { OP, ' ', 130, ',', 129, ',', 139, 0 },
 917 /* <op> $dr,$sr,#$ulo16 */
 918 /*   5 */  { OP, ' ', 130, ',', 129, ',', '#', 146, 0 },
 919 /* <op> $dr,$sr,$ulo16 */
 920 /*   6 */  { OP, ' ', 130, ',', 129, ',', 146, 0 },
 921 /* <op> $dr,#$simm8 */
 922 /*   7 */  { OP, ' ', 130, ',', '#', 135, 0 },
 923 /* <op> $dr,$simm8 */
 924 /*   8 */  { OP, ' ', 130, ',', 135, 0 },
 925 /* <op> $dr,$sr,#$simm16 */
 926 /*   9 */  { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
 927 /* <op> $dr,$sr,$simm16 */
 928 /*  10 */  { OP, ' ', 130, ',', 129, ',', 136, 0 },
 929 /* <op> $disp8 */
 930 /*  11 */  { OP, ' ', 148, 0 },
 931 /* <op> $disp24 */
 932 /*  12 */  { OP, ' ', 150, 0 },
 933 /* <op> $src1,$src2,$disp16 */
 934 /*  13 */  { OP, ' ', 131, ',', 132, ',', 149, 0 },
 935 /* <op> $src2,$disp16 */
 936 /*  14 */  { OP, ' ', 132, ',', 149, 0 },
 937 /* <op> $src1,$src2 */
 938 /*  15 */  { OP, ' ', 131, ',', 132, 0 },
 939 /* <op> $src2,#$simm16 */
 940 /*  16 */  { OP, ' ', 132, ',', '#', 136, 0 },
 941 /* <op> $src2,$simm16 */
 942 /*  17 */  { OP, ' ', 132, ',', 136, 0 },
 943 /* <op> $src2,#$uimm16 */
 944 /*  18 */  { OP, ' ', 132, ',', '#', 139, 0 },
 945 /* <op> $src2,$uimm16 */
 946 /*  19 */  { OP, ' ', 132, ',', 139, 0 },
 947 /* <op> $src2 */
 948 /*  20 */  { OP, ' ', 132, 0 },
 949 /* <op> $sr */
 950 /*  21 */  { OP, ' ', 129, 0 },
 951 /* <op> $dr,@$sr */
 952 /*  22 */  { OP, ' ', 130, ',', '@', 129, 0 },
 953 /* <op> $dr,@($sr) */
 954 /*  23 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
 955 /* <op> $dr,@($slo16,$sr) */
 956 /*  24 */  { OP, ' ', 130, ',', '@', '(', 145, ',', 129, ')', 0 },
 957 /* <op> $dr,@($sr,$slo16) */
 958 /*  25 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 145, ')', 0 },
 959 /* <op> $dr,@$sr+ */
 960 /*  26 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
 961 /* <op> $dr,#$uimm24 */
 962 /*  27 */  { OP, ' ', 130, ',', '#', 147, 0 },
 963 /* <op> $dr,$uimm24 */
 964 /*  28 */  { OP, ' ', 130, ',', 147, 0 },
 965 /* <op> $dr,$slo16 */
 966 /*  29 */  { OP, ' ', 130, ',', 145, 0 },
 967 /* <op> $src1,$src2,$acc */
 968 /*  30 */  { OP, ' ', 131, ',', 132, ',', 143, 0 },
 969 /* <op> $dr */
 970 /*  31 */  { OP, ' ', 130, 0 },
 971 /* <op> $dr,$accs */
 972 /*  32 */  { OP, ' ', 130, ',', 142, 0 },
 973 /* <op> $dr,$scr */
 974 /*  33 */  { OP, ' ', 130, ',', 133, 0 },
 975 /* <op> $src1 */
 976 /*  34 */  { OP, ' ', 131, 0 },
 977 /* <op> $src1,$accs */
 978 /*  35 */  { OP, ' ', 131, ',', 142, 0 },
 979 /* <op> $sr,$dcr */
 980 /*  36 */  { OP, ' ', 129, ',', 134, 0 },
 981 /* <op> */
 982 /*  37 */  { OP, 0 },
 983 /* <op> $accd */
 984 /*  38 */  { OP, ' ', 141, 0 },
 985 /* <op> $accd,$accs */
 986 /*  39 */  { OP, ' ', 141, ',', 142, 0 },
 987 /* <op> $accd,$accs,#$imm1 */
 988 /*  40 */  { OP, ' ', 141, ',', 142, ',', '#', 140, 0 },
 989 /* <op> $dr,#$hi16 */
 990 /*  41 */  { OP, ' ', 130, ',', '#', 144, 0 },
 991 /* <op> $dr,$hi16 */
 992 /*  42 */  { OP, ' ', 130, ',', 144, 0 },
 993 /* <op> $dr,#$uimm5 */
 994 /*  43 */  { OP, ' ', 130, ',', '#', 138, 0 },
 995 /* <op> $dr,$uimm5 */
 996 /*  44 */  { OP, ' ', 130, ',', 138, 0 },
 997 /* <op> $src1,@$src2 */
 998 /*  45 */  { OP, ' ', 131, ',', '@', 132, 0 },
 999 /* <op> $src1,@($src2) */
1000 /*  46 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
1001 /* <op> $src1,@($slo16,$src2) */
1002 /*  47 */  { OP, ' ', 131, ',', '@', '(', 145, ',', 132, ')', 0 },
1003 /* <op> $src1,@($src2,$slo16) */
1004 /*  48 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 145, ')', 0 },
1005 /* <op> $src1,@+$src2 */
1006 /*  49 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
1007 /* <op> $src1,@-$src2 */
1008 /*  50 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
1009 /* <op> #$uimm4 */
1010 /*  51 */  { OP, ' ', '#', 137, 0 },
1011 /* <op> $uimm4 */
1012 /*  52 */  { OP, ' ', 137, 0 },
1013 /* <op> $dr,$src2 */
1014 /*  53 */  { OP, ' ', 130, ',', 132, 0 },
1015 };
1016
1017 #undef OP
1018
1019 static const CGEN_FORMAT format_table[] =
1020 {
1021 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(dr SI) */
1022 /*   0 */  { 16, 16, 0xf0f0 },
1023 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(slo16 HI)(sr SI)(dr SI) */
1024 /*   1 */  { 32, 32, 0xf0f00000 },
1025 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 uimm16)(sr SI)(uimm16 USI)(dr SI) */
1026 /*   2 */  { 32, 32, 0xf0f00000 },
1027 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 ulo16)(sr SI)(ulo16 UHI)(dr SI) */
1028 /*   3 */  { 32, 32, 0xf0f00000 },
1029 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(dr SI)(simm8 SI)(dr SI) */
1030 /*   4 */  { 16, 16, 0xf000 },
1031 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1032 /*   5 */  { 16, 16, 0xf0f0 },
1033 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(condbit UBI)(dr SI) */
1034 /*   6 */  { 32, 32, 0xf0f00000 },
1035 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1036 /*   7 */  { 16, 16, 0xf0f0 },
1037 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM) */
1038 /*   8 */  { 16, 16, 0xff00 },
1039 /* (f-op1 #)(f-r1 #)(f-disp8 disp8) */
1040 /*   9 */  { 16, 16, 0xff00 },
1041 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM) */
1042 /*  10 */  { 32, 32, 0xff000000 },
1043 /* (f-op1 #)(f-r1 #)(f-disp24 disp24) */
1044 /*  11 */  { 32, 32, 0xff000000 },
1045 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI) */
1046 /*  12 */  { 32, 32, 0xf0f00000 },
1047 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI) */
1048 /*  13 */  { 32, 32, 0xfff00000 },
1049 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(h-gr-14 SI) */
1050 /*  14 */  { 16, 16, 0xff00 },
1051 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(h-gr-14 SI) */
1052 /*  15 */  { 32, 32, 0xff000000 },
1053 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(h-gr-14 SI) */
1054 /*  16 */  { 16, 16, 0xff00 },
1055 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(h-gr-14 SI) */
1056 /*  17 */  { 32, 32, 0xff000000 },
1057 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM) */
1058 /*  18 */  { 16, 16, 0xff00 },
1059 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM) */
1060 /*  19 */  { 32, 32, 0xff000000 },
1061 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */
1062 /*  20 */  { 16, 16, 0xf0f0 },
1063 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-simm16 simm16)(simm16 SI)(src2 SI)(condbit UBI) */
1064 /*  21 */  { 32, 32, 0xfff00000 },
1065 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-uimm16 uimm16)(src2 SI)(uimm16 USI)(condbit UBI) */
1066 /*  22 */  { 32, 32, 0xfff00000 },
1067 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(src2 SI)(condbit UBI) */
1068 /*  23 */  { 16, 16, 0xfff0 },
1069 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */
1070 /*  24 */  { 32, 32, 0xf0f0ffff },
1071 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI) */
1072 /*  25 */  { 16, 16, 0xfff0 },
1073 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(h-gr-14 SI) */
1074 /*  26 */  { 16, 16, 0xfff0 },
1075 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI) */
1076 /*  27 */  { 16, 16, 0xfff0 },
1077 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */
1078 /*  28 */  { 16, 16, 0xf0f0 },
1079 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr) */
1080 /*  29 */  { 16, 16, 0xf0f0 },
1081 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 SI)(slo16 HI)(sr SI)(dr SI) */
1082 /*  30 */  { 32, 32, 0xf0f00000 },
1083 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16) */
1084 /*  31 */  { 32, 32, 0xf0f00000 },
1085 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr QI)(sr SI)(dr SI) */
1086 /*  32 */  { 16, 16, 0xf0f0 },
1087 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 QI)(slo16 HI)(sr SI)(dr SI) */
1088 /*  33 */  { 32, 32, 0xf0f00000 },
1089 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr HI)(sr SI)(dr SI) */
1090 /*  34 */  { 16, 16, 0xf0f0 },
1091 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 HI)(slo16 HI)(sr SI)(dr SI) */
1092 /*  35 */  { 32, 32, 0xf0f00000 },
1093 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(sr SI) */
1094 /*  36 */  { 16, 16, 0xf0f0 },
1095 /* (f-op1 #)(f-r1 dr)(f-uimm24 uimm24)(uimm24 VM)(dr SI) */
1096 /*  37 */  { 32, 32, 0xf0000000 },
1097 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(simm8 SI)(dr SI) */
1098 /*  38 */  { 16, 16, 0xf000 },
1099 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */
1100 /*  39 */  { 32, 32, 0xf0ff0000 },
1101 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI) */
1102 /*  40 */  { 16, 16, 0xf0f0 },
1103 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */
1104 /*  41 */  { 16, 16, 0xf0f0 },
1105 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(acc DI)(src1 SI)(src2 SI)(acc DI) */
1106 /*  42 */  { 16, 16, 0xf070 },
1107 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(accum DI) */
1108 /*  43 */  { 16, 16, 0xf0f0 },
1109 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(src1 SI)(src2 SI)(acc DI) */
1110 /*  44 */  { 16, 16, 0xf070 },
1111 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(sr SI)(dr SI) */
1112 /*  45 */  { 16, 16, 0xf0f0 },
1113 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(accum DI)(dr SI) */
1114 /*  46 */  { 16, 16, 0xf0ff },
1115 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */
1116 /*  47 */  { 16, 16, 0xf0f3 },
1117 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr SI)(dr SI) */
1118 /*  48 */  { 16, 16, 0xf0f0 },
1119 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */
1120 /*  49 */  { 16, 16, 0xf0ff },
1121 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */
1122 /*  50 */  { 16, 16, 0xf0f3 },
1123 /* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr SI) */
1124 /*  51 */  { 16, 16, 0xf0f0 },
1125 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */
1126 /*  52 */  { 16, 16, 0xffff },
1127 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */
1128 /*  53 */  { 16, 16, 0xffff },
1129 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #)(accum DI)(accd DI) */
1130 /*  54 */  { 16, 16, 0xf3ff },
1131 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #)(accs DI)(accd DI) */
1132 /*  55 */  { 16, 16, 0xf3f3 },
1133 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */
1134 /*  56 */  { 16, 16, 0xf3f2 },
1135 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-bcond-0 VM)(h-bie-0 VM)(h-bpc-0 VM)(h-bsm-0 VM)(condbit UBI)(pc USI)(h-ie-0 VM)(h-sm-0 VM) */
1136 /*  57 */  { 16, 16, 0xffff },
1137 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-hi16 hi16)(hi16 UHI)(dr SI) */
1138 /*  58 */  { 32, 32, 0xf0ff0000 },
1139 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(dr SI) */
1140 /*  59 */  { 32, 32, 0xf0f00000 },
1141 /* (f-op1 #)(f-r1 dr)(f-shift-op2 #)(f-uimm5 uimm5)(dr SI)(uimm5 USI)(dr SI) */
1142 /*  60 */  { 16, 16, 0xf0e0 },
1143 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI) */
1144 /*  61 */  { 16, 16, 0xf0f0 },
1145 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2) */
1146 /*  62 */  { 16, 16, 0xf0f0 },
1147 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 SI) */
1148 /*  63 */  { 32, 32, 0xf0f00000 },
1149 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16) */
1150 /*  64 */  { 32, 32, 0xf0f00000 },
1151 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 QI) */
1152 /*  65 */  { 16, 16, 0xf0f0 },
1153 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 QI) */
1154 /*  66 */  { 32, 32, 0xf0f00000 },
1155 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 HI) */
1156 /*  67 */  { 16, 16, 0xf0f0 },
1157 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 HI) */
1158 /*  68 */  { 32, 32, 0xf0f00000 },
1159 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */
1160 /*  69 */  { 16, 16, 0xf0f0 },
1161 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(uimm4 USI) */
1162 /*  70 */  { 16, 16, 0xfff0 },
1163 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI) */
1164 /*  71 */  { 16, 16, 0xf0f0 },
1165 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */
1166 /*  72 */  { 16, 16, 0xf0ff },
1167 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
1168 /*  73 */  { 16, 16, 0xf0ff },
1169 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(src2 SI)(dr SI) */
1170 /*  74 */  { 32, 32, 0xf0f0ffff },
1171 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 src2)(f-uimm16 #)(condbit UBI)(src2 SI)(dr SI) */
1172 /*  75 */  { 32, 32, 0xf0f0ffff },
1173 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
1174 /*  76 */  { 16, 16, 0xffff },
1175 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */
1176 /*  77 */  { 16, 16, 0xf0f0 },
1177 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
1178 /*  78 */  { 16, 16, 0xf0f0 },
1179 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */
1180 /*  79 */  { 16, 16, 0xffff },
1181 };
1182
1183 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
1184 #define SYN(n) (& syntax_table[n])
1185 #define FMT(n) (& format_table[n])
1186
1187 /* The instruction table.  */
1188
1189 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1190 {
1191   /* null first entry, end of all hash chains */
1192   { { 0 }, 0 },
1193 /* add $dr,$sr */
1194   {
1195     { 1, 1, 1, 1 },
1196     "add", "add", SYN (0), FMT (0), 0xa0,
1197     & fmt_0_add_ops[0],
1198     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1199   },
1200 /* add3 $dr,$sr,#$slo16 */
1201   {
1202     { 1, 1, 1, 1 },
1203     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
1204     & fmt_1_add3_ops[0],
1205     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1206   },
1207 /* add3 $dr,$sr,$slo16 */
1208   {
1209     { 1, 1, 1, 1 },
1210     "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
1211     & fmt_1_add3_ops[0],
1212     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1213   },
1214 /* and $dr,$sr */
1215   {
1216     { 1, 1, 1, 1 },
1217     "and", "and", SYN (0), FMT (0), 0xc0,
1218     & fmt_0_add_ops[0],
1219     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1220   },
1221 /* and3 $dr,$sr,#$uimm16 */
1222   {
1223     { 1, 1, 1, 1 },
1224     "and3", "and3", SYN (3), FMT (2), 0x80c00000,
1225     & fmt_2_and3_ops[0],
1226     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1227   },
1228 /* and3 $dr,$sr,$uimm16 */
1229   {
1230     { 1, 1, 1, 1 },
1231     "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
1232     & fmt_2_and3_ops[0],
1233     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1234   },
1235 /* or $dr,$sr */
1236   {
1237     { 1, 1, 1, 1 },
1238     "or", "or", SYN (0), FMT (0), 0xe0,
1239     & fmt_0_add_ops[0],
1240     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1241   },
1242 /* or3 $dr,$sr,#$ulo16 */
1243   {
1244     { 1, 1, 1, 1 },
1245     "or3", "or3", SYN (5), FMT (3), 0x80e00000,
1246     & fmt_3_or3_ops[0],
1247     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1248   },
1249 /* or3 $dr,$sr,$ulo16 */
1250   {
1251     { 1, 1, 1, 1 },
1252     "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
1253     & fmt_3_or3_ops[0],
1254     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1255   },
1256 /* xor $dr,$sr */
1257   {
1258     { 1, 1, 1, 1 },
1259     "xor", "xor", SYN (0), FMT (0), 0xd0,
1260     & fmt_0_add_ops[0],
1261     { 2, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1262   },
1263 /* xor3 $dr,$sr,#$uimm16 */
1264   {
1265     { 1, 1, 1, 1 },
1266     "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
1267     & fmt_2_and3_ops[0],
1268     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1269   },
1270 /* xor3 $dr,$sr,$uimm16 */
1271   {
1272     { 1, 1, 1, 1 },
1273     "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
1274     & fmt_2_and3_ops[0],
1275     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1276   },
1277 /* addi $dr,#$simm8 */
1278   {
1279     { 1, 1, 1, 1 },
1280     "addi", "addi", SYN (7), FMT (4), 0x4000,
1281     & fmt_4_addi_ops[0],
1282     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1283   },
1284 /* addi $dr,$simm8 */
1285   {
1286     { 1, 1, 1, 1 },
1287     "addi.a", "addi", SYN (8), FMT (4), 0x4000,
1288     & fmt_4_addi_ops[0],
1289     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1290   },
1291 /* addv $dr,$sr */
1292   {
1293     { 1, 1, 1, 1 },
1294     "addv", "addv", SYN (0), FMT (5), 0x80,
1295     & fmt_5_addv_ops[0],
1296     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1297   },
1298 /* addv3 $dr,$sr,#$simm16 */
1299   {
1300     { 1, 1, 1, 1 },
1301     "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
1302     & fmt_6_addv3_ops[0],
1303     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1304   },
1305 /* addv3 $dr,$sr,$simm16 */
1306   {
1307     { 1, 1, 1, 1 },
1308     "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
1309     & fmt_6_addv3_ops[0],
1310     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1311   },
1312 /* addx $dr,$sr */
1313   {
1314     { 1, 1, 1, 1 },
1315     "addx", "addx", SYN (0), FMT (7), 0x90,
1316     & fmt_7_addx_ops[0],
1317     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1318   },
1319 /* bc $disp8 */
1320   {
1321     { 1, 1, 1, 1 },
1322     "bc8", "bc", SYN (11), FMT (8), 0x7c00,
1323     & fmt_8_bc8_ops[0],
1324     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1325   },
1326 /* bc.s $disp8 */
1327   {
1328     { 1, 1, 1, 1 },
1329     "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
1330     0,
1331     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1332   },
1333 /* bc $disp24 */
1334   {
1335     { 1, 1, 1, 1 },
1336     "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
1337     & fmt_10_bc24_ops[0],
1338     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1339   },
1340 /* bc.l $disp24 */
1341   {
1342     { 1, 1, 1, 1 },
1343     "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
1344     0,
1345     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1346   },
1347 /* beq $src1,$src2,$disp16 */
1348   {
1349     { 1, 1, 1, 1 },
1350     "beq", "beq", SYN (13), FMT (12), 0xb0000000,
1351     & fmt_12_beq_ops[0],
1352     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1353   },
1354 /* beqz $src2,$disp16 */
1355   {
1356     { 1, 1, 1, 1 },
1357     "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
1358     & fmt_13_beqz_ops[0],
1359     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1360   },
1361 /* bgez $src2,$disp16 */
1362   {
1363     { 1, 1, 1, 1 },
1364     "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
1365     & fmt_13_beqz_ops[0],
1366     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1367   },
1368 /* bgtz $src2,$disp16 */
1369   {
1370     { 1, 1, 1, 1 },
1371     "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
1372     & fmt_13_beqz_ops[0],
1373     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1374   },
1375 /* blez $src2,$disp16 */
1376   {
1377     { 1, 1, 1, 1 },
1378     "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
1379     & fmt_13_beqz_ops[0],
1380     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1381   },
1382 /* bltz $src2,$disp16 */
1383   {
1384     { 1, 1, 1, 1 },
1385     "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
1386     & fmt_13_beqz_ops[0],
1387     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1388   },
1389 /* bnez $src2,$disp16 */
1390   {
1391     { 1, 1, 1, 1 },
1392     "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
1393     & fmt_13_beqz_ops[0],
1394     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1395   },
1396 /* bl $disp8 */
1397   {
1398     { 1, 1, 1, 1 },
1399     "bl8", "bl", SYN (11), FMT (14), 0x7e00,
1400     & fmt_14_bl8_ops[0],
1401     { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1402   },
1403 /* bl.s $disp8 */
1404   {
1405     { 1, 1, 1, 1 },
1406     "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
1407     0,
1408     { 2, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1409   },
1410 /* bl $disp24 */
1411   {
1412     { 1, 1, 1, 1 },
1413     "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
1414     & fmt_15_bl24_ops[0],
1415     { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1416   },
1417 /* bl.l $disp24 */
1418   {
1419     { 1, 1, 1, 1 },
1420     "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
1421     0,
1422     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1423   },
1424 /* start-sanitize-m32rx */
1425 /* bcl $disp8 */
1426   {
1427     { 1, 1, 1, 1 },
1428     "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
1429     & fmt_16_bcl8_ops[0],
1430     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1431   },
1432 /* end-sanitize-m32rx */
1433 /* start-sanitize-m32rx */
1434 /* bcl.s $disp8 */
1435   {
1436     { 1, 1, 1, 1 },
1437     "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
1438     0,
1439     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1440   },
1441 /* end-sanitize-m32rx */
1442 /* start-sanitize-m32rx */
1443 /* bcl $disp24 */
1444   {
1445     { 1, 1, 1, 1 },
1446     "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
1447     & fmt_17_bcl24_ops[0],
1448     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1449   },
1450 /* end-sanitize-m32rx */
1451 /* start-sanitize-m32rx */
1452 /* bcl.l $disp24 */
1453   {
1454     { 1, 1, 1, 1 },
1455     "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
1456     0,
1457     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1458   },
1459 /* end-sanitize-m32rx */
1460 /* bnc $disp8 */
1461   {
1462     { 1, 1, 1, 1 },
1463     "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
1464     & fmt_8_bc8_ops[0],
1465     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1466   },
1467 /* bnc.s $disp8 */
1468   {
1469     { 1, 1, 1, 1 },
1470     "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
1471     0,
1472     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1473   },
1474 /* bnc $disp24 */
1475   {
1476     { 1, 1, 1, 1 },
1477     "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
1478     & fmt_10_bc24_ops[0],
1479     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1480   },
1481 /* bnc.l $disp24 */
1482   {
1483     { 1, 1, 1, 1 },
1484     "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
1485     0,
1486     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1487   },
1488 /* bne $src1,$src2,$disp16 */
1489   {
1490     { 1, 1, 1, 1 },
1491     "bne", "bne", SYN (13), FMT (12), 0xb0100000,
1492     & fmt_12_beq_ops[0],
1493     { 2, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1494   },
1495 /* bra $disp8 */
1496   {
1497     { 1, 1, 1, 1 },
1498     "bra8", "bra", SYN (11), FMT (18), 0x7f00,
1499     & fmt_18_bra8_ops[0],
1500     { 2, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1501   },
1502 /* bra.s $disp8 */
1503   {
1504     { 1, 1, 1, 1 },
1505     "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
1506     0,
1507     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1508   },
1509 /* bra $disp24 */
1510   {
1511     { 1, 1, 1, 1 },
1512     "bra24", "bra", SYN (12), FMT (19), 0xff000000,
1513     & fmt_19_bra24_ops[0],
1514     { 2, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1515   },
1516 /* bra.l $disp24 */
1517   {
1518     { 1, 1, 1, 1 },
1519     "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
1520     0,
1521     { 2, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1522   },
1523 /* start-sanitize-m32rx */
1524 /* bncl $disp8 */
1525   {
1526     { 1, 1, 1, 1 },
1527     "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
1528     & fmt_16_bcl8_ops[0],
1529     { 2, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1530   },
1531 /* end-sanitize-m32rx */
1532 /* start-sanitize-m32rx */
1533 /* bncl.s $disp8 */
1534   {
1535     { 1, 1, 1, 1 },
1536     "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
1537     0,
1538     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1539   },
1540 /* end-sanitize-m32rx */
1541 /* start-sanitize-m32rx */
1542 /* bncl $disp24 */
1543   {
1544     { 1, 1, 1, 1 },
1545     "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
1546     & fmt_17_bcl24_ops[0],
1547     { 2, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1548   },
1549 /* end-sanitize-m32rx */
1550 /* start-sanitize-m32rx */
1551 /* bncl.l $disp24 */
1552   {
1553     { 1, 1, 1, 1 },
1554     "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
1555     0,
1556     { 2, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1557   },
1558 /* end-sanitize-m32rx */
1559 /* cmp $src1,$src2 */
1560   {
1561     { 1, 1, 1, 1 },
1562     "cmp", "cmp", SYN (15), FMT (20), 0x40,
1563     & fmt_20_cmp_ops[0],
1564     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1565   },
1566 /* cmpi $src2,#$simm16 */
1567   {
1568     { 1, 1, 1, 1 },
1569     "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
1570     & fmt_21_cmpi_ops[0],
1571     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1572   },
1573 /* cmpi $src2,$simm16 */
1574   {
1575     { 1, 1, 1, 1 },
1576     "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
1577     & fmt_21_cmpi_ops[0],
1578     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1579   },
1580 /* cmpu $src1,$src2 */
1581   {
1582     { 1, 1, 1, 1 },
1583     "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
1584     & fmt_20_cmp_ops[0],
1585     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1586   },
1587 /* cmpui $src2,#$uimm16 */
1588   {
1589     { 1, 1, 1, 1 },
1590     "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
1591     & fmt_22_cmpui_ops[0],
1592     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1593   },
1594 /* cmpui $src2,$uimm16 */
1595   {
1596     { 1, 1, 1, 1 },
1597     "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
1598     & fmt_22_cmpui_ops[0],
1599     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1600   },
1601 /* start-sanitize-m32rx */
1602 /* cmpeq $src1,$src2 */
1603   {
1604     { 1, 1, 1, 1 },
1605     "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
1606     & fmt_20_cmp_ops[0],
1607     { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
1608   },
1609 /* end-sanitize-m32rx */
1610 /* start-sanitize-m32rx */
1611 /* cmpz $src2 */
1612   {
1613     { 1, 1, 1, 1 },
1614     "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
1615     & fmt_23_cmpz_ops[0],
1616     { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
1617   },
1618 /* end-sanitize-m32rx */
1619 /* div $dr,$sr */
1620   {
1621     { 1, 1, 1, 1 },
1622     "div", "div", SYN (0), FMT (24), 0x90000000,
1623     & fmt_24_div_ops[0],
1624     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1625   },
1626 /* divu $dr,$sr */
1627   {
1628     { 1, 1, 1, 1 },
1629     "divu", "divu", SYN (0), FMT (24), 0x90100000,
1630     & fmt_24_div_ops[0],
1631     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1632   },
1633 /* rem $dr,$sr */
1634   {
1635     { 1, 1, 1, 1 },
1636     "rem", "rem", SYN (0), FMT (24), 0x90200000,
1637     & fmt_24_div_ops[0],
1638     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1639   },
1640 /* remu $dr,$sr */
1641   {
1642     { 1, 1, 1, 1 },
1643     "remu", "remu", SYN (0), FMT (24), 0x90300000,
1644     & fmt_24_div_ops[0],
1645     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1646   },
1647 /* start-sanitize-m32rx */
1648 /* divh $dr,$sr */
1649   {
1650     { 1, 1, 1, 1 },
1651     "divh", "divh", SYN (0), FMT (24), 0x90000010,
1652     & fmt_24_div_ops[0],
1653     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1654   },
1655 /* end-sanitize-m32rx */
1656 /* start-sanitize-m32rx */
1657 /* jc $sr */
1658   {
1659     { 1, 1, 1, 1 },
1660     "jc", "jc", SYN (21), FMT (25), 0x1cc0,
1661     & fmt_25_jc_ops[0],
1662     { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1663   },
1664 /* end-sanitize-m32rx */
1665 /* start-sanitize-m32rx */
1666 /* jnc $sr */
1667   {
1668     { 1, 1, 1, 1 },
1669     "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
1670     & fmt_25_jc_ops[0],
1671     { 2, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1672   },
1673 /* end-sanitize-m32rx */
1674 /* jl $sr */
1675   {
1676     { 1, 1, 1, 1 },
1677     "jl", "jl", SYN (21), FMT (26), 0x1ec0,
1678     & fmt_26_jl_ops[0],
1679     { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1680   },
1681 /* jmp $sr */
1682   {
1683     { 1, 1, 1, 1 },
1684     "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
1685     & fmt_27_jmp_ops[0],
1686     { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1687   },
1688 /* ld $dr,@$sr */
1689   {
1690     { 1, 1, 1, 1 },
1691     "ld", "ld", SYN (22), FMT (28), 0x20c0,
1692     & fmt_28_ld_ops[0],
1693     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1694   },
1695 /* ld $dr,@($sr) */
1696   {
1697     { 1, 1, 1, 1 },
1698     "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
1699     0,
1700     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1701   },
1702 /* ld $dr,@($slo16,$sr) */
1703   {
1704     { 1, 1, 1, 1 },
1705     "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
1706     & fmt_30_ld_d_ops[0],
1707     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1708   },
1709 /* ld $dr,@($sr,$slo16) */
1710   {
1711     { 1, 1, 1, 1 },
1712     "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
1713     0,
1714     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1715   },
1716 /* ldb $dr,@$sr */
1717   {
1718     { 1, 1, 1, 1 },
1719     "ldb", "ldb", SYN (22), FMT (32), 0x2080,
1720     & fmt_32_ldb_ops[0],
1721     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1722   },
1723 /* ldb $dr,@($sr) */
1724   {
1725     { 1, 1, 1, 1 },
1726     "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
1727     0,
1728     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1729   },
1730 /* ldb $dr,@($slo16,$sr) */
1731   {
1732     { 1, 1, 1, 1 },
1733     "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
1734     & fmt_33_ldb_d_ops[0],
1735     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1736   },
1737 /* ldb $dr,@($sr,$slo16) */
1738   {
1739     { 1, 1, 1, 1 },
1740     "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
1741     0,
1742     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1743   },
1744 /* ldh $dr,@$sr */
1745   {
1746     { 1, 1, 1, 1 },
1747     "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
1748     & fmt_34_ldh_ops[0],
1749     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1750   },
1751 /* ldh $dr,@($sr) */
1752   {
1753     { 1, 1, 1, 1 },
1754     "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
1755     0,
1756     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1757   },
1758 /* ldh $dr,@($slo16,$sr) */
1759   {
1760     { 1, 1, 1, 1 },
1761     "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
1762     & fmt_35_ldh_d_ops[0],
1763     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1764   },
1765 /* ldh $dr,@($sr,$slo16) */
1766   {
1767     { 1, 1, 1, 1 },
1768     "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
1769     0,
1770     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1771   },
1772 /* ldub $dr,@$sr */
1773   {
1774     { 1, 1, 1, 1 },
1775     "ldub", "ldub", SYN (22), FMT (32), 0x2090,
1776     & fmt_32_ldb_ops[0],
1777     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1778   },
1779 /* ldub $dr,@($sr) */
1780   {
1781     { 1, 1, 1, 1 },
1782     "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
1783     0,
1784     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1785   },
1786 /* ldub $dr,@($slo16,$sr) */
1787   {
1788     { 1, 1, 1, 1 },
1789     "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
1790     & fmt_33_ldb_d_ops[0],
1791     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1792   },
1793 /* ldub $dr,@($sr,$slo16) */
1794   {
1795     { 1, 1, 1, 1 },
1796     "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
1797     0,
1798     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1799   },
1800 /* lduh $dr,@$sr */
1801   {
1802     { 1, 1, 1, 1 },
1803     "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
1804     & fmt_34_ldh_ops[0],
1805     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1806   },
1807 /* lduh $dr,@($sr) */
1808   {
1809     { 1, 1, 1, 1 },
1810     "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
1811     0,
1812     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1813   },
1814 /* lduh $dr,@($slo16,$sr) */
1815   {
1816     { 1, 1, 1, 1 },
1817     "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
1818     & fmt_35_ldh_d_ops[0],
1819     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1820   },
1821 /* lduh $dr,@($sr,$slo16) */
1822   {
1823     { 1, 1, 1, 1 },
1824     "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
1825     0,
1826     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1827   },
1828 /* ld $dr,@$sr+ */
1829   {
1830     { 1, 1, 1, 1 },
1831     "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
1832     & fmt_36_ld_plus_ops[0],
1833     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1834   },
1835 /* ld24 $dr,#$uimm24 */
1836   {
1837     { 1, 1, 1, 1 },
1838     "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
1839     & fmt_37_ld24_ops[0],
1840     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1841   },
1842 /* ld24 $dr,$uimm24 */
1843   {
1844     { 1, 1, 1, 1 },
1845     "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
1846     & fmt_37_ld24_ops[0],
1847     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1848   },
1849 /* ldi $dr,#$simm8 */
1850   {
1851     { 1, 1, 1, 1 },
1852     "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
1853     & fmt_38_ldi8_ops[0],
1854     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
1855   },
1856 /* ldi $dr,$simm8 */
1857   {
1858     { 1, 1, 1, 1 },
1859     "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
1860     & fmt_38_ldi8_ops[0],
1861     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1862   },
1863 /* ldi8 $dr,#$simm8 */
1864   {
1865     { 1, 1, 1, 1 },
1866     "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
1867     & fmt_38_ldi8_ops[0],
1868     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1869   },
1870 /* ldi8 $dr,$simm8 */
1871   {
1872     { 1, 1, 1, 1 },
1873     "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
1874     & fmt_38_ldi8_ops[0],
1875     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1876   },
1877 /* ldi $dr,$slo16 */
1878   {
1879     { 1, 1, 1, 1 },
1880     "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
1881     & fmt_39_ldi16_ops[0],
1882     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
1883   },
1884 /* ldi16 $dr,$slo16 */
1885   {
1886     { 1, 1, 1, 1 },
1887     "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
1888     & fmt_39_ldi16_ops[0],
1889     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1890   },
1891 /* lock $dr,@$sr */
1892   {
1893     { 1, 1, 1, 1 },
1894     "lock", "lock", SYN (22), FMT (40), 0x20d0,
1895     & fmt_40_lock_ops[0],
1896     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
1897   },
1898 /* machi $src1,$src2 */
1899   {
1900     { 1, 1, 1, 1 },
1901     "machi", "machi", SYN (15), FMT (41), 0x3040,
1902     & fmt_41_machi_ops[0],
1903     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1904   },
1905 /* start-sanitize-m32rx */
1906 /* machi $src1,$src2,$acc */
1907   {
1908     { 1, 1, 1, 1 },
1909     "machi-a", "machi", SYN (30), FMT (42), 0x3040,
1910     & fmt_42_machi_a_ops[0],
1911     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1912   },
1913 /* end-sanitize-m32rx */
1914 /* maclo $src1,$src2 */
1915   {
1916     { 1, 1, 1, 1 },
1917     "maclo", "maclo", SYN (15), FMT (41), 0x3050,
1918     & fmt_41_machi_ops[0],
1919     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1920   },
1921 /* start-sanitize-m32rx */
1922 /* maclo $src1,$src2,$acc */
1923   {
1924     { 1, 1, 1, 1 },
1925     "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
1926     & fmt_42_machi_a_ops[0],
1927     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1928   },
1929 /* end-sanitize-m32rx */
1930 /* macwhi $src1,$src2 */
1931   {
1932     { 1, 1, 1, 1 },
1933     "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
1934     & fmt_41_machi_ops[0],
1935     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1936   },
1937 /* macwlo $src1,$src2 */
1938   {
1939     { 1, 1, 1, 1 },
1940     "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
1941     & fmt_41_machi_ops[0],
1942     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1943   },
1944 /* mul $dr,$sr */
1945   {
1946     { 1, 1, 1, 1 },
1947     "mul", "mul", SYN (0), FMT (0), 0x1060,
1948     & fmt_0_add_ops[0],
1949     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1950   },
1951 /* mulhi $src1,$src2 */
1952   {
1953     { 1, 1, 1, 1 },
1954     "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
1955     & fmt_43_mulhi_ops[0],
1956     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1957   },
1958 /* start-sanitize-m32rx */
1959 /* mulhi $src1,$src2,$acc */
1960   {
1961     { 1, 1, 1, 1 },
1962     "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
1963     & fmt_44_mulhi_a_ops[0],
1964     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1965   },
1966 /* end-sanitize-m32rx */
1967 /* mullo $src1,$src2 */
1968   {
1969     { 1, 1, 1, 1 },
1970     "mullo", "mullo", SYN (15), FMT (43), 0x3010,
1971     & fmt_43_mulhi_ops[0],
1972     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1973   },
1974 /* start-sanitize-m32rx */
1975 /* mullo $src1,$src2,$acc */
1976   {
1977     { 1, 1, 1, 1 },
1978     "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
1979     & fmt_44_mulhi_a_ops[0],
1980     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
1981   },
1982 /* end-sanitize-m32rx */
1983 /* mulwhi $src1,$src2 */
1984   {
1985     { 1, 1, 1, 1 },
1986     "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
1987     & fmt_43_mulhi_ops[0],
1988     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1989   },
1990 /* mulwlo $src1,$src2 */
1991   {
1992     { 1, 1, 1, 1 },
1993     "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
1994     & fmt_43_mulhi_ops[0],
1995     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
1996   },
1997 /* mv $dr,$sr */
1998   {
1999     { 1, 1, 1, 1 },
2000     "mv", "mv", SYN (0), FMT (45), 0x1080,
2001     & fmt_45_mv_ops[0],
2002     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2003   },
2004 /* mvfachi $dr */
2005   {
2006     { 1, 1, 1, 1 },
2007     "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
2008     & fmt_46_mvfachi_ops[0],
2009     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2010   },
2011 /* start-sanitize-m32rx */
2012 /* mvfachi $dr,$accs */
2013   {
2014     { 1, 1, 1, 1 },
2015     "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
2016     & fmt_47_mvfachi_a_ops[0],
2017     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2018   },
2019 /* end-sanitize-m32rx */
2020 /* mvfaclo $dr */
2021   {
2022     { 1, 1, 1, 1 },
2023     "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
2024     & fmt_46_mvfachi_ops[0],
2025     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2026   },
2027 /* start-sanitize-m32rx */
2028 /* mvfaclo $dr,$accs */
2029   {
2030     { 1, 1, 1, 1 },
2031     "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
2032     & fmt_47_mvfachi_a_ops[0],
2033     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2034   },
2035 /* end-sanitize-m32rx */
2036 /* mvfacmi $dr */
2037   {
2038     { 1, 1, 1, 1 },
2039     "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
2040     & fmt_46_mvfachi_ops[0],
2041     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2042   },
2043 /* start-sanitize-m32rx */
2044 /* mvfacmi $dr,$accs */
2045   {
2046     { 1, 1, 1, 1 },
2047     "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
2048     & fmt_47_mvfachi_a_ops[0],
2049     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2050   },
2051 /* end-sanitize-m32rx */
2052 /* mvfc $dr,$scr */
2053   {
2054     { 1, 1, 1, 1 },
2055     "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
2056     & fmt_48_mvfc_ops[0],
2057     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2058   },
2059 /* mvtachi $src1 */
2060   {
2061     { 1, 1, 1, 1 },
2062     "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
2063     & fmt_49_mvtachi_ops[0],
2064     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2065   },
2066 /* start-sanitize-m32rx */
2067 /* mvtachi $src1,$accs */
2068   {
2069     { 1, 1, 1, 1 },
2070     "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
2071     & fmt_50_mvtachi_a_ops[0],
2072     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2073   },
2074 /* end-sanitize-m32rx */
2075 /* mvtaclo $src1 */
2076   {
2077     { 1, 1, 1, 1 },
2078     "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
2079     & fmt_49_mvtachi_ops[0],
2080     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2081   },
2082 /* start-sanitize-m32rx */
2083 /* mvtaclo $src1,$accs */
2084   {
2085     { 1, 1, 1, 1 },
2086     "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
2087     & fmt_50_mvtachi_a_ops[0],
2088     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2089   },
2090 /* end-sanitize-m32rx */
2091 /* mvtc $sr,$dcr */
2092   {
2093     { 1, 1, 1, 1 },
2094     "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
2095     & fmt_51_mvtc_ops[0],
2096     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2097   },
2098 /* neg $dr,$sr */
2099   {
2100     { 1, 1, 1, 1 },
2101     "neg", "neg", SYN (0), FMT (45), 0x30,
2102     & fmt_45_mv_ops[0],
2103     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2104   },
2105 /* nop */
2106   {
2107     { 1, 1, 1, 1 },
2108     "nop", "nop", SYN (37), FMT (52), 0x7000,
2109     0,
2110     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2111   },
2112 /* not $dr,$sr */
2113   {
2114     { 1, 1, 1, 1 },
2115     "not", "not", SYN (0), FMT (45), 0xb0,
2116     & fmt_45_mv_ops[0],
2117     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2118   },
2119 /* rac */
2120   {
2121     { 1, 1, 1, 1 },
2122     "rac", "rac", SYN (37), FMT (53), 0x5090,
2123     & fmt_53_rac_ops[0],
2124     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2125   },
2126 /* start-sanitize-m32rx */
2127 /* rac $accd */
2128   {
2129     { 1, 1, 1, 1 },
2130     "rac-d", "rac", SYN (38), FMT (54), 0x5090,
2131     & fmt_54_rac_d_ops[0],
2132     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2133   },
2134 /* end-sanitize-m32rx */
2135 /* start-sanitize-m32rx */
2136 /* rac $accd,$accs */
2137   {
2138     { 1, 1, 1, 1 },
2139     "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
2140     & fmt_55_rac_ds_ops[0],
2141     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2142   },
2143 /* end-sanitize-m32rx */
2144 /* start-sanitize-m32rx */
2145 /* rac $accd,$accs,#$imm1 */
2146   {
2147     { 1, 1, 1, 1 },
2148     "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
2149     & fmt_56_rac_dsi_ops[0],
2150     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2151   },
2152 /* end-sanitize-m32rx */
2153 /* rach */
2154   {
2155     { 1, 1, 1, 1 },
2156     "rach", "rach", SYN (37), FMT (53), 0x5080,
2157     & fmt_53_rac_ops[0],
2158     { 2, 0, { (1<<MACH_M32R), PIPE_S } }
2159   },
2160 /* start-sanitize-m32rx */
2161 /* rach $accd */
2162   {
2163     { 1, 1, 1, 1 },
2164     "rach-d", "rach", SYN (38), FMT (54), 0x5080,
2165     & fmt_54_rac_d_ops[0],
2166     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2167   },
2168 /* end-sanitize-m32rx */
2169 /* start-sanitize-m32rx */
2170 /* rach $accd,$accs */
2171   {
2172     { 1, 1, 1, 1 },
2173     "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
2174     & fmt_55_rac_ds_ops[0],
2175     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2176   },
2177 /* end-sanitize-m32rx */
2178 /* start-sanitize-m32rx */
2179 /* rach $accd,$accs,#$imm1 */
2180   {
2181     { 1, 1, 1, 1 },
2182     "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
2183     & fmt_56_rac_dsi_ops[0],
2184     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2185   },
2186 /* end-sanitize-m32rx */
2187 /* rte */
2188   {
2189     { 1, 1, 1, 1 },
2190     "rte", "rte", SYN (37), FMT (57), 0x10d6,
2191     & fmt_57_rte_ops[0],
2192     { 2, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2193   },
2194 /* seth $dr,#$hi16 */
2195   {
2196     { 1, 1, 1, 1 },
2197     "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
2198     & fmt_58_seth_ops[0],
2199     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2200   },
2201 /* seth $dr,$hi16 */
2202   {
2203     { 1, 1, 1, 1 },
2204     "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
2205     & fmt_58_seth_ops[0],
2206     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2207   },
2208 /* sll $dr,$sr */
2209   {
2210     { 1, 1, 1, 1 },
2211     "sll", "sll", SYN (0), FMT (0), 0x1040,
2212     & fmt_0_add_ops[0],
2213     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2214   },
2215 /* sll3 $dr,$sr,#$simm16 */
2216   {
2217     { 1, 1, 1, 1 },
2218     "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
2219     & fmt_59_sll3_ops[0],
2220     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2221   },
2222 /* sll3 $dr,$sr,$simm16 */
2223   {
2224     { 1, 1, 1, 1 },
2225     "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
2226     & fmt_59_sll3_ops[0],
2227     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2228   },
2229 /* slli $dr,#$uimm5 */
2230   {
2231     { 1, 1, 1, 1 },
2232     "slli", "slli", SYN (43), FMT (60), 0x5040,
2233     & fmt_60_slli_ops[0],
2234     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2235   },
2236 /* slli $dr,$uimm5 */
2237   {
2238     { 1, 1, 1, 1 },
2239     "slli.a", "slli", SYN (44), FMT (60), 0x5040,
2240     & fmt_60_slli_ops[0],
2241     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2242   },
2243 /* sra $dr,$sr */
2244   {
2245     { 1, 1, 1, 1 },
2246     "sra", "sra", SYN (0), FMT (0), 0x1020,
2247     & fmt_0_add_ops[0],
2248     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2249   },
2250 /* sra3 $dr,$sr,#$simm16 */
2251   {
2252     { 1, 1, 1, 1 },
2253     "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
2254     & fmt_59_sll3_ops[0],
2255     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2256   },
2257 /* sra3 $dr,$sr,$simm16 */
2258   {
2259     { 1, 1, 1, 1 },
2260     "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
2261     & fmt_59_sll3_ops[0],
2262     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2263   },
2264 /* srai $dr,#$uimm5 */
2265   {
2266     { 1, 1, 1, 1 },
2267     "srai", "srai", SYN (43), FMT (60), 0x5020,
2268     & fmt_60_slli_ops[0],
2269     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2270   },
2271 /* srai $dr,$uimm5 */
2272   {
2273     { 1, 1, 1, 1 },
2274     "srai.a", "srai", SYN (44), FMT (60), 0x5020,
2275     & fmt_60_slli_ops[0],
2276     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2277   },
2278 /* srl $dr,$sr */
2279   {
2280     { 1, 1, 1, 1 },
2281     "srl", "srl", SYN (0), FMT (0), 0x1000,
2282     & fmt_0_add_ops[0],
2283     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2284   },
2285 /* srl3 $dr,$sr,#$simm16 */
2286   {
2287     { 1, 1, 1, 1 },
2288     "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
2289     & fmt_59_sll3_ops[0],
2290     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2291   },
2292 /* srl3 $dr,$sr,$simm16 */
2293   {
2294     { 1, 1, 1, 1 },
2295     "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
2296     & fmt_59_sll3_ops[0],
2297     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2298   },
2299 /* srli $dr,#$uimm5 */
2300   {
2301     { 1, 1, 1, 1 },
2302     "srli", "srli", SYN (43), FMT (60), 0x5000,
2303     & fmt_60_slli_ops[0],
2304     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2305   },
2306 /* srli $dr,$uimm5 */
2307   {
2308     { 1, 1, 1, 1 },
2309     "srli.a", "srli", SYN (44), FMT (60), 0x5000,
2310     & fmt_60_slli_ops[0],
2311     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2312   },
2313 /* st $src1,@$src2 */
2314   {
2315     { 1, 1, 1, 1 },
2316     "st", "st", SYN (45), FMT (61), 0x2040,
2317     & fmt_61_st_ops[0],
2318     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2319   },
2320 /* st $src1,@($src2) */
2321   {
2322     { 1, 1, 1, 1 },
2323     "st-2", "st", SYN (46), FMT (62), 0x2040,
2324     0,
2325     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2326   },
2327 /* st $src1,@($slo16,$src2) */
2328   {
2329     { 1, 1, 1, 1 },
2330     "st-d", "st", SYN (47), FMT (63), 0xa0400000,
2331     & fmt_63_st_d_ops[0],
2332     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2333   },
2334 /* st $src1,@($src2,$slo16) */
2335   {
2336     { 1, 1, 1, 1 },
2337     "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
2338     0,
2339     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2340   },
2341 /* stb $src1,@$src2 */
2342   {
2343     { 1, 1, 1, 1 },
2344     "stb", "stb", SYN (45), FMT (65), 0x2000,
2345     & fmt_65_stb_ops[0],
2346     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2347   },
2348 /* stb $src1,@($src2) */
2349   {
2350     { 1, 1, 1, 1 },
2351     "stb-2", "stb", SYN (46), FMT (62), 0x2000,
2352     0,
2353     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2354   },
2355 /* stb $src1,@($slo16,$src2) */
2356   {
2357     { 1, 1, 1, 1 },
2358     "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
2359     & fmt_66_stb_d_ops[0],
2360     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2361   },
2362 /* stb $src1,@($src2,$slo16) */
2363   {
2364     { 1, 1, 1, 1 },
2365     "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
2366     0,
2367     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2368   },
2369 /* sth $src1,@$src2 */
2370   {
2371     { 1, 1, 1, 1 },
2372     "sth", "sth", SYN (45), FMT (67), 0x2020,
2373     & fmt_67_sth_ops[0],
2374     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2375   },
2376 /* sth $src1,@($src2) */
2377   {
2378     { 1, 1, 1, 1 },
2379     "sth-2", "sth", SYN (46), FMT (62), 0x2020,
2380     0,
2381     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2382   },
2383 /* sth $src1,@($slo16,$src2) */
2384   {
2385     { 1, 1, 1, 1 },
2386     "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
2387     & fmt_68_sth_d_ops[0],
2388     { 2, 0, { (1<<MACH_M32R), PIPE_NONE } }
2389   },
2390 /* sth $src1,@($src2,$slo16) */
2391   {
2392     { 1, 1, 1, 1 },
2393     "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
2394     0,
2395     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2396   },
2397 /* st $src1,@+$src2 */
2398   {
2399     { 1, 1, 1, 1 },
2400     "st-plus", "st", SYN (49), FMT (69), 0x2060,
2401     & fmt_69_st_plus_ops[0],
2402     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2403   },
2404 /* st $src1,@-$src2 */
2405   {
2406     { 1, 1, 1, 1 },
2407     "st-minus", "st", SYN (50), FMT (69), 0x2070,
2408     & fmt_69_st_plus_ops[0],
2409     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2410   },
2411 /* sub $dr,$sr */
2412   {
2413     { 1, 1, 1, 1 },
2414     "sub", "sub", SYN (0), FMT (0), 0x20,
2415     & fmt_0_add_ops[0],
2416     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2417   },
2418 /* subv $dr,$sr */
2419   {
2420     { 1, 1, 1, 1 },
2421     "subv", "subv", SYN (0), FMT (5), 0x0,
2422     & fmt_5_addv_ops[0],
2423     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2424   },
2425 /* subx $dr,$sr */
2426   {
2427     { 1, 1, 1, 1 },
2428     "subx", "subx", SYN (0), FMT (7), 0x10,
2429     & fmt_7_addx_ops[0],
2430     { 2, 0, { (1<<MACH_M32R), PIPE_OS } }
2431   },
2432 /* trap #$uimm4 */
2433   {
2434     { 1, 1, 1, 1 },
2435     "trap", "trap", SYN (51), FMT (70), 0x10f0,
2436     & fmt_70_trap_ops[0],
2437     { 2, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2438   },
2439 /* trap $uimm4 */
2440   {
2441     { 1, 1, 1, 1 },
2442     "trap.a", "trap", SYN (52), FMT (70), 0x10f0,
2443     & fmt_70_trap_ops[0],
2444     { 2, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2445   },
2446 /* unlock $src1,@$src2 */
2447   {
2448     { 1, 1, 1, 1 },
2449     "unlock", "unlock", SYN (45), FMT (71), 0x2050,
2450     & fmt_71_unlock_ops[0],
2451     { 2, 0, { (1<<MACH_M32R), PIPE_O } }
2452   },
2453 /* push $src1 */
2454   {
2455     { 1, 1, 1, 1 },
2456     "push", "push", SYN (34), FMT (72), 0x207f,
2457     0,
2458     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2459   },
2460 /* pop $dr */
2461   {
2462     { 1, 1, 1, 1 },
2463     "pop", "pop", SYN (31), FMT (73), 0x20ef,
2464     0,
2465     { 2, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2466   },
2467 /* start-sanitize-m32rx */
2468 /* satb $dr,$src2 */
2469   {
2470     { 1, 1, 1, 1 },
2471     "satb", "satb", SYN (53), FMT (74), 0x80000100,
2472     & fmt_74_satb_ops[0],
2473     { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2474   },
2475 /* end-sanitize-m32rx */
2476 /* start-sanitize-m32rx */
2477 /* sath $dr,$src2 */
2478   {
2479     { 1, 1, 1, 1 },
2480     "sath", "sath", SYN (53), FMT (74), 0x80000200,
2481     & fmt_74_satb_ops[0],
2482     { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2483   },
2484 /* end-sanitize-m32rx */
2485 /* start-sanitize-m32rx */
2486 /* sat $dr,$src2 */
2487   {
2488     { 1, 1, 1, 1 },
2489     "sat", "sat", SYN (53), FMT (75), 0x80000000,
2490     & fmt_75_sat_ops[0],
2491     { 2, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2492   },
2493 /* end-sanitize-m32rx */
2494 /* start-sanitize-m32rx */
2495 /* pcmpbz $src2 */
2496   {
2497     { 1, 1, 1, 1 },
2498     "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
2499     & fmt_23_cmpz_ops[0],
2500     { 2, 0, { (1<<MACH_M32RX), PIPE_OS } }
2501   },
2502 /* end-sanitize-m32rx */
2503 /* start-sanitize-m32rx */
2504 /* sadd */
2505   {
2506     { 1, 1, 1, 1 },
2507     "sadd", "sadd", SYN (37), FMT (76), 0x50e4,
2508     & fmt_76_sadd_ops[0],
2509     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2510   },
2511 /* end-sanitize-m32rx */
2512 /* start-sanitize-m32rx */
2513 /* macwu1 $src1,$src2 */
2514   {
2515     { 1, 1, 1, 1 },
2516     "macwu1", "macwu1", SYN (15), FMT (77), 0x50b0,
2517     & fmt_77_macwu1_ops[0],
2518     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2519   },
2520 /* end-sanitize-m32rx */
2521 /* start-sanitize-m32rx */
2522 /* msblo $src1,$src2 */
2523   {
2524     { 1, 1, 1, 1 },
2525     "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
2526     & fmt_41_machi_ops[0],
2527     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2528   },
2529 /* end-sanitize-m32rx */
2530 /* start-sanitize-m32rx */
2531 /* mulwu1 $src1,$src2 */
2532   {
2533     { 1, 1, 1, 1 },
2534     "mulwu1", "mulwu1", SYN (15), FMT (78), 0x50a0,
2535     & fmt_78_mulwu1_ops[0],
2536     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2537   },
2538 /* end-sanitize-m32rx */
2539 /* start-sanitize-m32rx */
2540 /* maclh1 $src1,$src2 */
2541   {
2542     { 1, 1, 1, 1 },
2543     "maclh1", "maclh1", SYN (15), FMT (77), 0x50c0,
2544     & fmt_77_macwu1_ops[0],
2545     { 2, 0, { (1<<MACH_M32RX), PIPE_S } }
2546   },
2547 /* end-sanitize-m32rx */
2548 /* start-sanitize-m32rx */
2549 /* sc */
2550   {
2551     { 1, 1, 1, 1 },
2552     "sc", "sc", SYN (37), FMT (79), 0x7401,
2553     & fmt_79_sc_ops[0],
2554     { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
2555   },
2556 /* end-sanitize-m32rx */
2557 /* start-sanitize-m32rx */
2558 /* snc */
2559   {
2560     { 1, 1, 1, 1 },
2561     "snc", "snc", SYN (37), FMT (79), 0x7501,
2562     & fmt_79_sc_ops[0],
2563     { 2, 0, { (1<<MACH_M32RX), PIPE_O } }
2564   },
2565 /* end-sanitize-m32rx */
2566 };
2567
2568 #undef A
2569 #undef SYN
2570 #undef FMT
2571
2572 CGEN_INSN_TABLE m32r_cgen_insn_table =
2573 {
2574   & m32r_cgen_insn_table_entries[0],
2575   sizeof (CGEN_INSN),
2576   MAX_INSNS,
2577   NULL,
2578   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2579   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2580 };
2581
2582 /* The hash functions are recorded here to help keep assembler code out of
2583    the disassembler and vice versa.  */
2584
2585 unsigned int
2586 m32r_cgen_asm_hash_insn (insn)
2587      const char * insn;
2588 {
2589   return CGEN_ASM_HASH (insn);
2590 }
2591
2592 unsigned int
2593 m32r_cgen_dis_hash_insn (buf, value)
2594      const char * buf;
2595      unsigned long value;
2596 {
2597   return CGEN_DIS_HASH (buf, value);
2598 }
2599
2600 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2601 {
2602   & m32r_cgen_hw_entries[0],
2603   & m32r_cgen_insn_table,
2604 };
2605
2606 void
2607 m32r_cgen_init_tables (mach)
2608     int mach;
2609 {
2610 }
2611
2612 /* Main entry point for stuffing values in cgen_fields.  */
2613
2614 CGEN_INLINE void
2615 m32r_cgen_set_operand (opindex, valuep, fields)
2616      int opindex;
2617      const long * valuep;
2618      CGEN_FIELDS * fields;
2619 {
2620   switch (opindex)
2621     {
2622     case M32R_OPERAND_SR :
2623       fields->f_r2 = * valuep;
2624       break;
2625     case M32R_OPERAND_DR :
2626       fields->f_r1 = * valuep;
2627       break;
2628     case M32R_OPERAND_SRC1 :
2629       fields->f_r1 = * valuep;
2630       break;
2631     case M32R_OPERAND_SRC2 :
2632       fields->f_r2 = * valuep;
2633       break;
2634     case M32R_OPERAND_SCR :
2635       fields->f_r2 = * valuep;
2636       break;
2637     case M32R_OPERAND_DCR :
2638       fields->f_r1 = * valuep;
2639       break;
2640     case M32R_OPERAND_SIMM8 :
2641       fields->f_simm8 = * valuep;
2642       break;
2643     case M32R_OPERAND_SIMM16 :
2644       fields->f_simm16 = * valuep;
2645       break;
2646     case M32R_OPERAND_UIMM4 :
2647       fields->f_uimm4 = * valuep;
2648       break;
2649     case M32R_OPERAND_UIMM5 :
2650       fields->f_uimm5 = * valuep;
2651       break;
2652     case M32R_OPERAND_UIMM16 :
2653       fields->f_uimm16 = * valuep;
2654       break;
2655 /* start-sanitize-m32rx */
2656     case M32R_OPERAND_IMM1 :
2657       fields->f_imm1 = * valuep;
2658       break;
2659 /* end-sanitize-m32rx */
2660 /* start-sanitize-m32rx */
2661     case M32R_OPERAND_ACCD :
2662       fields->f_accd = * valuep;
2663       break;
2664 /* end-sanitize-m32rx */
2665 /* start-sanitize-m32rx */
2666     case M32R_OPERAND_ACCS :
2667       fields->f_accs = * valuep;
2668       break;
2669 /* end-sanitize-m32rx */
2670 /* start-sanitize-m32rx */
2671     case M32R_OPERAND_ACC :
2672       fields->f_acc = * valuep;
2673       break;
2674 /* end-sanitize-m32rx */
2675     case M32R_OPERAND_HI16 :
2676       fields->f_hi16 = * valuep;
2677       break;
2678     case M32R_OPERAND_SLO16 :
2679       fields->f_simm16 = * valuep;
2680       break;
2681     case M32R_OPERAND_ULO16 :
2682       fields->f_uimm16 = * valuep;
2683       break;
2684     case M32R_OPERAND_UIMM24 :
2685       fields->f_uimm24 = * valuep;
2686       break;
2687     case M32R_OPERAND_DISP8 :
2688       fields->f_disp8 = * valuep;
2689       break;
2690     case M32R_OPERAND_DISP16 :
2691       fields->f_disp16 = * valuep;
2692       break;
2693     case M32R_OPERAND_DISP24 :
2694       fields->f_disp24 = * valuep;
2695       break;
2696
2697     default :
2698       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2699                        opindex);
2700       abort ();
2701   }
2702 }
2703
2704 /* Main entry point for getting values from cgen_fields.  */
2705
2706 CGEN_INLINE long
2707 m32r_cgen_get_operand (opindex, fields)
2708      int opindex;
2709      const CGEN_FIELDS * fields;
2710 {
2711   long value;
2712
2713   switch (opindex)
2714     {
2715     case M32R_OPERAND_SR :
2716       value = fields->f_r2;
2717       break;
2718     case M32R_OPERAND_DR :
2719       value = fields->f_r1;
2720       break;
2721     case M32R_OPERAND_SRC1 :
2722       value = fields->f_r1;
2723       break;
2724     case M32R_OPERAND_SRC2 :
2725       value = fields->f_r2;
2726       break;
2727     case M32R_OPERAND_SCR :
2728       value = fields->f_r2;
2729       break;
2730     case M32R_OPERAND_DCR :
2731       value = fields->f_r1;
2732       break;
2733     case M32R_OPERAND_SIMM8 :
2734       value = fields->f_simm8;
2735       break;
2736     case M32R_OPERAND_SIMM16 :
2737       value = fields->f_simm16;
2738       break;
2739     case M32R_OPERAND_UIMM4 :
2740       value = fields->f_uimm4;
2741       break;
2742     case M32R_OPERAND_UIMM5 :
2743       value = fields->f_uimm5;
2744       break;
2745     case M32R_OPERAND_UIMM16 :
2746       value = fields->f_uimm16;
2747       break;
2748 /* start-sanitize-m32rx */
2749     case M32R_OPERAND_IMM1 :
2750       value = fields->f_imm1;
2751       break;
2752 /* end-sanitize-m32rx */
2753 /* start-sanitize-m32rx */
2754     case M32R_OPERAND_ACCD :
2755       value = fields->f_accd;
2756       break;
2757 /* end-sanitize-m32rx */
2758 /* start-sanitize-m32rx */
2759     case M32R_OPERAND_ACCS :
2760       value = fields->f_accs;
2761       break;
2762 /* end-sanitize-m32rx */
2763 /* start-sanitize-m32rx */
2764     case M32R_OPERAND_ACC :
2765       value = fields->f_acc;
2766       break;
2767 /* end-sanitize-m32rx */
2768     case M32R_OPERAND_HI16 :
2769       value = fields->f_hi16;
2770       break;
2771     case M32R_OPERAND_SLO16 :
2772       value = fields->f_simm16;
2773       break;
2774     case M32R_OPERAND_ULO16 :
2775       value = fields->f_uimm16;
2776       break;
2777     case M32R_OPERAND_UIMM24 :
2778       value = fields->f_uimm24;
2779       break;
2780     case M32R_OPERAND_DISP8 :
2781       value = fields->f_disp8;
2782       break;
2783     case M32R_OPERAND_DISP16 :
2784       value = fields->f_disp16;
2785       break;
2786     case M32R_OPERAND_DISP24 :
2787       value = fields->f_disp24;
2788       break;
2789
2790     default :
2791       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2792                        opindex);
2793       abort ();
2794   }
2795
2796   return value;
2797 }
2798