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Regenerate with less verbose operand instance tables.
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 This file is used to generate m32r-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "m32r-opc.h"
31
32 /* Look up instruction INSN_VALUE and extract its fields.
33 If non-null INSN is the insn table entry.
34 Otherwise INSN_VALUE is examined to compute it.
35 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
36 The result a pointer to the insn table entry, or NULL if the instruction
37 wasn't recognized. */
38
39 const CGEN_INSN *
40 m32r_cgen_lookup_insn (insn, insn_value, length, fields)
41 const CGEN_INSN *insn;
42 cgen_insn_t insn_value;
43 int length;
44 CGEN_FIELDS *fields;
45 {
46 char buf[4];
47
48 if (!insn)
49 {
50 const CGEN_INSN_LIST *insn_list;
51
52 #ifdef CGEN_INT_INSN
53 switch (length)
54 {
55 case 8:
56 buf[0] = insn_value;
57 break;
58 case 16:
59 if (cgen_current_endian == CGEN_ENDIAN_BIG)
60 bfd_putb16 (insn_value, buf);
61 else
62 bfd_putl16 (insn_value, buf);
63 break;
64 case 32:
65 if (cgen_current_endian == CGEN_ENDIAN_BIG)
66 bfd_putb32 (insn_value, buf);
67 else
68 bfd_putl32 (insn_value, buf);
69 break;
70 default:
71 abort ();
72 }
73 #else
74 abort (); /* FIXME: unfinished */
75 #endif
76
77 /* The instructions are stored in hash lists.
78 Pick the first one and keep trying until we find the right one. */
79
80 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
81 while (insn_list != NULL)
82 {
83 insn = insn_list->insn;
84
85 /* Basic bit mask must be correct. */
86 /* ??? May wish to allow target to defer this check until the extract
87 handler. */
88 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
89 {
90 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
91 if (length > 0)
92 return insn;
93 }
94
95 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
96 }
97 }
98 else
99 {
100 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
101 if (length > 0)
102 return insn;
103 }
104
105 return NULL;
106 }
107
108 /* Fill in the operand instances used by insn INSN_VALUE.
109 If non-null INS is the insn table entry.
110 Otherwise INSN_VALUE is examined to compute it.
111 LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
112 INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
113 The result a pointer to the insn table entry, or NULL if the instruction
114 wasn't recognized. */
115
116 const CGEN_INSN *
117 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
118 const CGEN_INSN *insn;
119 cgen_insn_t insn_value;
120 int length;
121 int *indices;
122 {
123 CGEN_FIELDS fields;
124 const CGEN_OPERAND_INSTANCE *opinst;
125 int i;
126
127 insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields);
128 if (! insn)
129 return NULL;
130
131 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
132 CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
133 ++i, ++opinst)
134 {
135 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
136 if (op == NULL)
137 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
138 else
139 indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
140 }
141
142 return insn;
143 }
144 /* Attributes. */
145
146 static const CGEN_ATTR_ENTRY MACH_attr[] =
147 {
148 { "m32r", MACH_M32R },
149 /* start-sanitize-m32rx */
150 { "m32rx", MACH_M32RX },
151 /* end-sanitize-m32rx */
152 { "max", MACH_MAX },
153 { 0, 0 }
154 };
155
156 static const CGEN_ATTR_ENTRY WRITE_LR_attr[] =
157 {
158 { "NO", WRITE_LR_NO },
159 { "YES", WRITE_LR_YES },
160 { 0, 0 }
161 };
162
163 static const CGEN_ATTR_ENTRY WRITE_SRC_attr[] =
164 {
165 { "NO", WRITE_SRC_NO },
166 { "YES", WRITE_SRC_YES },
167 { 0, 0 }
168 };
169
170 /* start-sanitize-m32rx */
171 static const CGEN_ATTR_ENTRY PIPE_attr[] =
172 {
173 { "NONE", PIPE_NONE },
174 { "O", PIPE_O },
175 { "S", PIPE_S },
176 { "OS", PIPE_OS },
177 { 0, 0 }
178 };
179
180 /* end-sanitize-m32rx */
181 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
182 {
183 { "ABS-ADDR", NULL },
184 { "FAKE", NULL },
185 { "NEGATIVE", NULL },
186 { "PC", NULL },
187 { "PCREL-ADDR", NULL },
188 { "RELAX", NULL },
189 { "RELOC", NULL },
190 { "SIGN-OPT", NULL },
191 { "UNSIGNED", NULL },
192 { 0, 0 }
193 };
194
195 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
196 {
197 { "MACH", & MACH_attr[0] },
198 /* start-sanitize-m32rx */
199 { "PIPE", & PIPE_attr[0] },
200 /* end-sanitize-m32rx */
201 { "WRITE_LR", & WRITE_LR_attr[0] },
202 { "WRITE_SRC", & WRITE_SRC_attr[0] },
203 { "ALIAS", NULL },
204 { "COND-CTI", NULL },
205 { "FILL-SLOT", NULL },
206 { "PARALLEL", NULL },
207 { "RELAX", NULL },
208 { "RELAXABLE", NULL },
209 { "UNCOND-CTI", NULL },
210 { 0, 0 }
211 };
212
213 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
214 {
215 { "fp", 13 },
216 { "lr", 14 },
217 { "sp", 15 },
218 { "r0", 0 },
219 { "r1", 1 },
220 { "r2", 2 },
221 { "r3", 3 },
222 { "r4", 4 },
223 { "r5", 5 },
224 { "r6", 6 },
225 { "r7", 7 },
226 { "r8", 8 },
227 { "r9", 9 },
228 { "r10", 10 },
229 { "r11", 11 },
230 { "r12", 12 },
231 { "r13", 13 },
232 { "r14", 14 },
233 { "r15", 15 }
234 };
235
236 CGEN_KEYWORD m32r_cgen_opval_h_gr =
237 {
238 & m32r_cgen_opval_h_gr_entries[0],
239 19
240 };
241
242 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
243 {
244 { "psw", 0 },
245 { "cbr", 1 },
246 { "spi", 2 },
247 { "spu", 3 },
248 { "bpc", 6 },
249 { "cr0", 0 },
250 { "cr1", 1 },
251 { "cr2", 2 },
252 { "cr3", 3 },
253 { "cr4", 4 },
254 { "cr5", 5 },
255 { "cr6", 6 }
256 };
257
258 CGEN_KEYWORD m32r_cgen_opval_h_cr =
259 {
260 & m32r_cgen_opval_h_cr_entries[0],
261 12
262 };
263
264 /* start-sanitize-m32rx */
265 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
266 {
267 { "a0", 0 },
268 { "a1", 1 }
269 };
270
271 CGEN_KEYWORD m32r_cgen_opval_h_accums =
272 {
273 & m32r_cgen_opval_h_accums_entries[0],
274 2
275 };
276
277 /* end-sanitize-m32rx */
278
279 /* The hardware table. */
280
281 #define HW_ENT(n) m32r_cgen_hw_entries[n]
282 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
283 {
284 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
285 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
286 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
287 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
288 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
289 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
290 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
291 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
292 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
293 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
294 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
295 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
296 /* start-sanitize-m32rx */
297 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
298 /* end-sanitize-m32rx */
299 /* start-sanitize-m32rx */
300 { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
301 /* end-sanitize-m32rx */
302 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
303 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
304 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
305 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
306 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
307 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
308 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
309 { 0 }
310 };
311
312 /* The operand table. */
313
314 #define OP_ENT(op) m32r_cgen_operand_table[CONCAT2 (M32R_OPERAND_,op)]
315 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
316 {
317 /* pc: program counter */
318 { "pc", & HW_ENT (HW_H_PC), 0, 0,
319 { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
320 /* sr: source register */
321 { "sr", & HW_ENT (HW_H_GR), 12, 4,
322 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
323 /* dr: destination register */
324 { "dr", & HW_ENT (HW_H_GR), 4, 4,
325 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
326 /* src1: source register 1 */
327 { "src1", & HW_ENT (HW_H_GR), 4, 4,
328 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
329 /* src2: source register 2 */
330 { "src2", & HW_ENT (HW_H_GR), 12, 4,
331 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
332 /* scr: source control register */
333 { "scr", & HW_ENT (HW_H_CR), 12, 4,
334 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
335 /* dcr: destination control register */
336 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
337 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
338 /* simm8: 8 bit signed immediate */
339 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
340 { 0, 0, { 0 } } },
341 /* simm16: 16 bit signed immediate */
342 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
343 { 0, 0, { 0 } } },
344 /* uimm4: 4 bit trap number */
345 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
346 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
347 /* uimm5: 5 bit shift count */
348 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
349 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
350 /* uimm16: 16 bit unsigned immediate */
351 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
352 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
353 /* start-sanitize-m32rx */
354 /* imm1: 1 bit immediate */
355 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
356 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
357 /* end-sanitize-m32rx */
358 /* start-sanitize-m32rx */
359 /* accd: accumulator destination register */
360 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
361 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
362 /* end-sanitize-m32rx */
363 /* start-sanitize-m32rx */
364 /* accs: accumulator source register */
365 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
366 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
367 /* end-sanitize-m32rx */
368 /* start-sanitize-m32rx */
369 /* acc: accumulator reg (d) */
370 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
371 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
372 /* end-sanitize-m32rx */
373 /* hi16: high 16 bit immediate, sign optional */
374 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
375 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
376 /* slo16: 16 bit signed immediate, for low() */
377 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
378 { 0, 0, { 0 } } },
379 /* ulo16: 16 bit unsigned immediate, for low() */
380 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
381 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
382 /* uimm24: 24 bit address */
383 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
384 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
385 /* disp8: 8 bit displacement */
386 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
387 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
388 /* disp16: 16 bit displacement */
389 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
390 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
391 /* disp24: 24 bit displacement */
392 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
393 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
394 /* condbit: condition bit */
395 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
396 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
397 /* accum: accumulator */
398 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
399 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
400 /* start-sanitize-m32rx */
401 /* abort-parallel-execution: abort parallel execution */
402 { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
403 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
404 /* end-sanitize-m32rx */
405 };
406
407 /* Operand references. */
408
409 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
410 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
411
412 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
413 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
414 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
415 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
416 { 0 }
417 };
418
419 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
420 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
421 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
422 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
423 { 0 }
424 };
425
426 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
427 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
428 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
429 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
430 { 0 }
431 };
432
433 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
434 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
435 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
436 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
437 { 0 }
438 };
439
440 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
441 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
442 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
443 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
444 { 0 }
445 };
446
447 static const CGEN_OPERAND_INSTANCE fmt_5_addv3_ops[] = {
448 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
449 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
450 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
451 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
452 { 0 }
453 };
454
455 static const CGEN_OPERAND_INSTANCE fmt_6_addx_ops[] = {
456 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
457 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
458 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
459 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
460 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
461 { 0 }
462 };
463
464 static const CGEN_OPERAND_INSTANCE fmt_7_bc8_ops[] = {
465 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
466 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
467 { 0 }
468 };
469
470 static const CGEN_OPERAND_INSTANCE fmt_9_bc24_ops[] = {
471 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
472 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
473 { 0 }
474 };
475
476 static const CGEN_OPERAND_INSTANCE fmt_11_beq_ops[] = {
477 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
478 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
479 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
480 { 0 }
481 };
482
483 static const CGEN_OPERAND_INSTANCE fmt_12_beqz_ops[] = {
484 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
485 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
486 { 0 }
487 };
488
489 static const CGEN_OPERAND_INSTANCE fmt_13_bl8_ops[] = {
490 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
491 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
492 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
493 { 0 }
494 };
495
496 static const CGEN_OPERAND_INSTANCE fmt_14_bl24_ops[] = {
497 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
498 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
499 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
500 { 0 }
501 };
502
503 static const CGEN_OPERAND_INSTANCE fmt_15_bcl8_ops[] = {
504 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
505 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
506 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
507 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
508 { 0 }
509 };
510
511 static const CGEN_OPERAND_INSTANCE fmt_16_bcl24_ops[] = {
512 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
513 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
514 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
515 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
516 { 0 }
517 };
518
519 static const CGEN_OPERAND_INSTANCE fmt_17_bra8_ops[] = {
520 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
521 { 0 }
522 };
523
524 static const CGEN_OPERAND_INSTANCE fmt_18_bra24_ops[] = {
525 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
526 { 0 }
527 };
528
529 static const CGEN_OPERAND_INSTANCE fmt_19_cmp_ops[] = {
530 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
531 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
532 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
533 { 0 }
534 };
535
536 static const CGEN_OPERAND_INSTANCE fmt_20_cmpi_ops[] = {
537 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
538 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
539 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
540 { 0 }
541 };
542
543 static const CGEN_OPERAND_INSTANCE fmt_21_cmpui_ops[] = {
544 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
545 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
546 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
547 { 0 }
548 };
549
550 static const CGEN_OPERAND_INSTANCE fmt_22_cmpz_ops[] = {
551 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
552 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
553 { 0 }
554 };
555
556 static const CGEN_OPERAND_INSTANCE fmt_23_div_ops[] = {
557 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
558 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
559 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
560 { 0 }
561 };
562
563 static const CGEN_OPERAND_INSTANCE fmt_24_jc_ops[] = {
564 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
565 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
566 { 0 }
567 };
568
569 static const CGEN_OPERAND_INSTANCE fmt_25_jl_ops[] = {
570 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
571 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
572 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
573 { 0 }
574 };
575
576 static const CGEN_OPERAND_INSTANCE fmt_26_jmp_ops[] = {
577 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
578 { 0 }
579 };
580
581 static const CGEN_OPERAND_INSTANCE fmt_27_ld_ops[] = {
582 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
583 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
584 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
585 { 0 }
586 };
587
588 static const CGEN_OPERAND_INSTANCE fmt_29_ld_d_ops[] = {
589 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
590 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
591 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
592 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
593 { 0 }
594 };
595
596 static const CGEN_OPERAND_INSTANCE fmt_31_ldb_ops[] = {
597 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
598 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
599 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
600 { 0 }
601 };
602
603 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_d_ops[] = {
604 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
605 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
606 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
607 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
608 { 0 }
609 };
610
611 static const CGEN_OPERAND_INSTANCE fmt_33_ldh_ops[] = {
612 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
613 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
614 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
615 { 0 }
616 };
617
618 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_d_ops[] = {
619 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
620 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
621 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
622 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
623 { 0 }
624 };
625
626 static const CGEN_OPERAND_INSTANCE fmt_35_ld24_ops[] = {
627 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
628 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
629 { 0 }
630 };
631
632 static const CGEN_OPERAND_INSTANCE fmt_36_ldi8_ops[] = {
633 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
634 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
635 { 0 }
636 };
637
638 static const CGEN_OPERAND_INSTANCE fmt_37_ldi16_ops[] = {
639 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
640 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
641 { 0 }
642 };
643
644 static const CGEN_OPERAND_INSTANCE fmt_38_machi_ops[] = {
645 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
646 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
647 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
648 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
649 { 0 }
650 };
651
652 static const CGEN_OPERAND_INSTANCE fmt_39_machi_a_ops[] = {
653 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
654 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
655 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
656 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
657 { 0 }
658 };
659
660 static const CGEN_OPERAND_INSTANCE fmt_40_mulhi_a_ops[] = {
661 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
662 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
663 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
664 { 0 }
665 };
666
667 static const CGEN_OPERAND_INSTANCE fmt_41_mv_ops[] = {
668 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
669 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
670 { 0 }
671 };
672
673 static const CGEN_OPERAND_INSTANCE fmt_42_mvfachi_ops[] = {
674 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
675 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
676 { 0 }
677 };
678
679 static const CGEN_OPERAND_INSTANCE fmt_43_mvfachi_a_ops[] = {
680 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
681 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
682 { 0 }
683 };
684
685 static const CGEN_OPERAND_INSTANCE fmt_44_mvfc_ops[] = {
686 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (SCR), 0 },
687 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
688 { 0 }
689 };
690
691 static const CGEN_OPERAND_INSTANCE fmt_45_mvtachi_ops[] = {
692 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
693 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
694 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
695 { 0 }
696 };
697
698 static const CGEN_OPERAND_INSTANCE fmt_46_mvtachi_a_ops[] = {
699 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
700 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
701 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
702 { 0 }
703 };
704
705 static const CGEN_OPERAND_INSTANCE fmt_47_mvtc_ops[] = {
706 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
707 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (DCR), 0 },
708 { 0 }
709 };
710
711 static const CGEN_OPERAND_INSTANCE fmt_49_rac_ops[] = {
712 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
713 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
714 { 0 }
715 };
716
717 static const CGEN_OPERAND_INSTANCE fmt_50_rac_d_ops[] = {
718 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
719 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
720 { 0 }
721 };
722
723 static const CGEN_OPERAND_INSTANCE fmt_51_rac_ds_ops[] = {
724 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
725 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
726 { 0 }
727 };
728
729 static const CGEN_OPERAND_INSTANCE fmt_52_rac_dsi_ops[] = {
730 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
731 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
732 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
733 { 0 }
734 };
735
736 static const CGEN_OPERAND_INSTANCE fmt_53_rte_ops[] = {
737 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
738 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
739 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
740 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
741 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
742 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
743 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
744 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
745 { 0 }
746 };
747
748 static const CGEN_OPERAND_INSTANCE fmt_54_seth_ops[] = {
749 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
750 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
751 { 0 }
752 };
753
754 static const CGEN_OPERAND_INSTANCE fmt_55_slli_ops[] = {
755 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
756 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
757 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
758 { 0 }
759 };
760
761 static const CGEN_OPERAND_INSTANCE fmt_57_st_d_ops[] = {
762 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
763 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
764 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
765 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
766 { 0 }
767 };
768
769 static const CGEN_OPERAND_INSTANCE fmt_59_trap_ops[] = {
770 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
771 { 0 }
772 };
773
774 static const CGEN_OPERAND_INSTANCE fmt_62_satb_ops[] = {
775 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
776 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
777 { 0 }
778 };
779
780 static const CGEN_OPERAND_INSTANCE fmt_63_sat_ops[] = {
781 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
782 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
783 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
784 { 0 }
785 };
786
787 static const CGEN_OPERAND_INSTANCE fmt_64_sadd_ops[] = {
788 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
789 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
790 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
791 { 0 }
792 };
793
794 static const CGEN_OPERAND_INSTANCE fmt_65_macwu1_ops[] = {
795 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
796 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
797 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
798 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
799 { 0 }
800 };
801
802 static const CGEN_OPERAND_INSTANCE fmt_66_sc_ops[] = {
803 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
804 { OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, & OP_ENT (ABORT_PARALLEL_EXECUTION), 0 },
805 { 0 }
806 };
807
808 #undef INPUT
809 #undef OUTPUT
810
811 #define OP 1 /* syntax value for mnemonic */
812
813 static const CGEN_SYNTAX syntax_table[] =
814 {
815 /* <op> $dr,$sr */
816 /* 0 */ { OP, ' ', 130, ',', 129, 0 },
817 /* <op> $dr,$sr,#$slo16 */
818 /* 1 */ { OP, ' ', 130, ',', 129, ',', '#', 145, 0 },
819 /* <op> $dr,$sr,$slo16 */
820 /* 2 */ { OP, ' ', 130, ',', 129, ',', 145, 0 },
821 /* <op> $dr,$sr,#$uimm16 */
822 /* 3 */ { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
823 /* <op> $dr,$sr,$uimm16 */
824 /* 4 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
825 /* <op> $dr,$sr,#$ulo16 */
826 /* 5 */ { OP, ' ', 130, ',', 129, ',', '#', 146, 0 },
827 /* <op> $dr,$sr,$ulo16 */
828 /* 6 */ { OP, ' ', 130, ',', 129, ',', 146, 0 },
829 /* <op> $dr,#$simm8 */
830 /* 7 */ { OP, ' ', 130, ',', '#', 135, 0 },
831 /* <op> $dr,$simm8 */
832 /* 8 */ { OP, ' ', 130, ',', 135, 0 },
833 /* <op> $dr,$sr,#$simm16 */
834 /* 9 */ { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
835 /* <op> $dr,$sr,$simm16 */
836 /* 10 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
837 /* <op> $disp8 */
838 /* 11 */ { OP, ' ', 148, 0 },
839 /* <op> $disp24 */
840 /* 12 */ { OP, ' ', 150, 0 },
841 /* <op> $src1,$src2,$disp16 */
842 /* 13 */ { OP, ' ', 131, ',', 132, ',', 149, 0 },
843 /* <op> $src2,$disp16 */
844 /* 14 */ { OP, ' ', 132, ',', 149, 0 },
845 /* <op> $src1,$src2 */
846 /* 15 */ { OP, ' ', 131, ',', 132, 0 },
847 /* <op> $src2,#$simm16 */
848 /* 16 */ { OP, ' ', 132, ',', '#', 136, 0 },
849 /* <op> $src2,$simm16 */
850 /* 17 */ { OP, ' ', 132, ',', 136, 0 },
851 /* <op> $src2,#$uimm16 */
852 /* 18 */ { OP, ' ', 132, ',', '#', 139, 0 },
853 /* <op> $src2,$uimm16 */
854 /* 19 */ { OP, ' ', 132, ',', 139, 0 },
855 /* <op> $src2 */
856 /* 20 */ { OP, ' ', 132, 0 },
857 /* <op> $sr */
858 /* 21 */ { OP, ' ', 129, 0 },
859 /* <op> $dr,@$sr */
860 /* 22 */ { OP, ' ', 130, ',', '@', 129, 0 },
861 /* <op> $dr,@($sr) */
862 /* 23 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
863 /* <op> $dr,@($slo16,$sr) */
864 /* 24 */ { OP, ' ', 130, ',', '@', '(', 145, ',', 129, ')', 0 },
865 /* <op> $dr,@($sr,$slo16) */
866 /* 25 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 145, ')', 0 },
867 /* <op> $dr,@$sr+ */
868 /* 26 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
869 /* <op> $dr,#$uimm24 */
870 /* 27 */ { OP, ' ', 130, ',', '#', 147, 0 },
871 /* <op> $dr,$uimm24 */
872 /* 28 */ { OP, ' ', 130, ',', 147, 0 },
873 /* <op> $dr,$slo16 */
874 /* 29 */ { OP, ' ', 130, ',', 145, 0 },
875 /* <op> $src1,$src2,$acc */
876 /* 30 */ { OP, ' ', 131, ',', 132, ',', 143, 0 },
877 /* <op> $dr */
878 /* 31 */ { OP, ' ', 130, 0 },
879 /* <op> $dr,$accs */
880 /* 32 */ { OP, ' ', 130, ',', 142, 0 },
881 /* <op> $dr,$scr */
882 /* 33 */ { OP, ' ', 130, ',', 133, 0 },
883 /* <op> $src1 */
884 /* 34 */ { OP, ' ', 131, 0 },
885 /* <op> $src1,$accs */
886 /* 35 */ { OP, ' ', 131, ',', 142, 0 },
887 /* <op> $sr,$dcr */
888 /* 36 */ { OP, ' ', 129, ',', 134, 0 },
889 /* <op> */
890 /* 37 */ { OP, 0 },
891 /* <op> $accd */
892 /* 38 */ { OP, ' ', 141, 0 },
893 /* <op> $accd,$accs */
894 /* 39 */ { OP, ' ', 141, ',', 142, 0 },
895 /* <op> $accd,$accs,#$imm1 */
896 /* 40 */ { OP, ' ', 141, ',', 142, ',', '#', 140, 0 },
897 /* <op> $dr,#$hi16 */
898 /* 41 */ { OP, ' ', 130, ',', '#', 144, 0 },
899 /* <op> $dr,$hi16 */
900 /* 42 */ { OP, ' ', 130, ',', 144, 0 },
901 /* <op> $dr,#$uimm5 */
902 /* 43 */ { OP, ' ', 130, ',', '#', 138, 0 },
903 /* <op> $dr,$uimm5 */
904 /* 44 */ { OP, ' ', 130, ',', 138, 0 },
905 /* <op> $src1,@$src2 */
906 /* 45 */ { OP, ' ', 131, ',', '@', 132, 0 },
907 /* <op> $src1,@($src2) */
908 /* 46 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
909 /* <op> $src1,@($slo16,$src2) */
910 /* 47 */ { OP, ' ', 131, ',', '@', '(', 145, ',', 132, ')', 0 },
911 /* <op> $src1,@($src2,$slo16) */
912 /* 48 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 145, ')', 0 },
913 /* <op> $src1,@+$src2 */
914 /* 49 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
915 /* <op> $src1,@-$src2 */
916 /* 50 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
917 /* <op> #$uimm4 */
918 /* 51 */ { OP, ' ', '#', 137, 0 },
919 /* <op> $uimm4 */
920 /* 52 */ { OP, ' ', 137, 0 },
921 /* <op> $dr,$src2 */
922 /* 53 */ { OP, ' ', 130, ',', 132, 0 },
923 };
924
925 #undef OP
926
927 static const CGEN_FORMAT format_table[] =
928 {
929 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.dr.SI.sr.SI. */
930 /* 0 */ { 16, 16, 0xf0f0 },
931 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.slo16.HI.sr.SI. */
932 /* 1 */ { 32, 32, 0xf0f00000 },
933 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16.sr.SI.uimm16.USI. */
934 /* 2 */ { 32, 32, 0xf0f00000 },
935 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16.sr.SI.ulo16.UHI. */
936 /* 3 */ { 32, 32, 0xf0f00000 },
937 /* f-op1.number.f-r1.dr.f-simm8.simm8.dr.SI.simm8.SI. */
938 /* 4 */ { 16, 16, 0xf000 },
939 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16.simm16.SI.sr.SI. */
940 /* 5 */ { 32, 32, 0xf0f00000 },
941 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.condbit.UBI.dr.SI.sr.SI. */
942 /* 6 */ { 16, 16, 0xf0f0 },
943 /* f-op1.number.f-r1.number.f-disp8.disp8.condbit.UBI.disp8.VM. */
944 /* 7 */ { 16, 16, 0xff00 },
945 /* f-op1.number.f-r1.number.f-disp8.disp8. */
946 /* 8 */ { 16, 16, 0xff00 },
947 /* f-op1.number.f-r1.number.f-disp24.disp24.condbit.UBI.disp24.VM. */
948 /* 9 */ { 32, 32, 0xff000000 },
949 /* f-op1.number.f-r1.number.f-disp24.disp24. */
950 /* 10 */ { 32, 32, 0xff000000 },
951 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16.disp16.VM.src1.SI.src2.SI. */
952 /* 11 */ { 32, 32, 0xf0f00000 },
953 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16.disp16.VM.src2.SI. */
954 /* 12 */ { 32, 32, 0xfff00000 },
955 /* f-op1.number.f-r1.number.f-disp8.disp8.disp8.VM.pc.USI. */
956 /* 13 */ { 16, 16, 0xff00 },
957 /* f-op1.number.f-r1.number.f-disp24.disp24.disp24.VM.pc.USI. */
958 /* 14 */ { 32, 32, 0xff000000 },
959 /* f-op1.number.f-r1.number.f-disp8.disp8.condbit.UBI.disp8.VM.pc.USI. */
960 /* 15 */ { 16, 16, 0xff00 },
961 /* f-op1.number.f-r1.number.f-disp24.disp24.condbit.UBI.disp24.VM.pc.USI. */
962 /* 16 */ { 32, 32, 0xff000000 },
963 /* f-op1.number.f-r1.number.f-disp8.disp8.disp8.VM. */
964 /* 17 */ { 16, 16, 0xff00 },
965 /* f-op1.number.f-r1.number.f-disp24.disp24.disp24.VM. */
966 /* 18 */ { 32, 32, 0xff000000 },
967 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.src1.SI.src2.SI. */
968 /* 19 */ { 16, 16, 0xf0f0 },
969 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16.simm16.SI.src2.SI. */
970 /* 20 */ { 32, 32, 0xfff00000 },
971 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16.src2.SI.uimm16.USI. */
972 /* 21 */ { 32, 32, 0xfff00000 },
973 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.src2.SI. */
974 /* 22 */ { 16, 16, 0xfff0 },
975 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number.dr.SI.sr.SI. */
976 /* 23 */ { 32, 32, 0xf0f0ffff },
977 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.condbit.UBI.sr.SI. */
978 /* 24 */ { 16, 16, 0xfff0 },
979 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.pc.USI.sr.SI. */
980 /* 25 */ { 16, 16, 0xfff0 },
981 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.sr.SI. */
982 /* 26 */ { 16, 16, 0xfff0 },
983 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.SI.sr.SI. */
984 /* 27 */ { 16, 16, 0xf0f0 },
985 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
986 /* 28 */ { 16, 16, 0xf0f0 },
987 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.SI.slo16.HI.sr.SI. */
988 /* 29 */ { 32, 32, 0xf0f00000 },
989 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
990 /* 30 */ { 32, 32, 0xf0f00000 },
991 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.QI.sr.SI. */
992 /* 31 */ { 16, 16, 0xf0f0 },
993 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.QI.slo16.HI.sr.SI. */
994 /* 32 */ { 32, 32, 0xf0f00000 },
995 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.HI.sr.SI. */
996 /* 33 */ { 16, 16, 0xf0f0 },
997 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.HI.slo16.HI.sr.SI. */
998 /* 34 */ { 32, 32, 0xf0f00000 },
999 /* f-op1.number.f-r1.dr.f-uimm24.uimm24.uimm24.VM. */
1000 /* 35 */ { 32, 32, 0xf0000000 },
1001 /* f-op1.number.f-r1.dr.f-simm8.simm8.simm8.SI. */
1002 /* 36 */ { 16, 16, 0xf000 },
1003 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16.slo16.HI. */
1004 /* 37 */ { 32, 32, 0xf0ff0000 },
1005 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.accum.DI.src1.SI.src2.SI. */
1006 /* 38 */ { 16, 16, 0xf0f0 },
1007 /* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2.acc.DI.src1.SI.src2.SI. */
1008 /* 39 */ { 16, 16, 0xf070 },
1009 /* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2.src1.SI.src2.SI. */
1010 /* 40 */ { 16, 16, 0xf070 },
1011 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.sr.SI. */
1012 /* 41 */ { 16, 16, 0xf0f0 },
1013 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.accum.DI. */
1014 /* 42 */ { 16, 16, 0xf0ff },
1015 /* f-op1.number.f-r1.dr.f-op2.number.f-accs.accs.f-op3.number.accs.DI. */
1016 /* 43 */ { 16, 16, 0xf0f3 },
1017 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr.scr.SI. */
1018 /* 44 */ { 16, 16, 0xf0f0 },
1019 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number.accum.DI.src1.SI. */
1020 /* 45 */ { 16, 16, 0xf0ff },
1021 /* f-op1.number.f-r1.src1.f-op2.number.f-accs.accs.f-op3.number.accs.DI.src1.SI. */
1022 /* 46 */ { 16, 16, 0xf0f3 },
1023 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr.sr.SI. */
1024 /* 47 */ { 16, 16, 0xf0f0 },
1025 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
1026 /* 48 */ { 16, 16, 0xffff },
1027 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.accum.DI. */
1028 /* 49 */ { 16, 16, 0xffff },
1029 /* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.number.f-bit14.number.f-imm1.number.accum.DI. */
1030 /* 50 */ { 16, 16, 0xf3ff },
1031 /* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.accs.f-bit14.number.f-imm1.number.accs.DI. */
1032 /* 51 */ { 16, 16, 0xf3f3 },
1033 /* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.accs.f-bit14.number.f-imm1.imm1.accs.DI.imm1.USI. */
1034 /* 52 */ { 16, 16, 0xf3f2 },
1035 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.h-bcond-0.VM.h-bie-0.VM.h-bpc-0.VM.h-bsm-0.VM. */
1036 /* 53 */ { 16, 16, 0xffff },
1037 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16.hi16.UHI. */
1038 /* 54 */ { 32, 32, 0xf0ff0000 },
1039 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5.dr.SI.uimm5.USI. */
1040 /* 55 */ { 16, 16, 0xf0e0 },
1041 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
1042 /* 56 */ { 16, 16, 0xf0f0 },
1043 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16.slo16.HI.src1.SI.src2.SI. */
1044 /* 57 */ { 32, 32, 0xf0f00000 },
1045 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
1046 /* 58 */ { 32, 32, 0xf0f00000 },
1047 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4.uimm4.USI. */
1048 /* 59 */ { 16, 16, 0xfff0 },
1049 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
1050 /* 60 */ { 16, 16, 0xf0ff },
1051 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
1052 /* 61 */ { 16, 16, 0xf0ff },
1053 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number.src2.SI. */
1054 /* 62 */ { 32, 32, 0xf0f0ffff },
1055 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number.condbit.UBI.src2.SI. */
1056 /* 63 */ { 32, 32, 0xf0f0ffff },
1057 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.h-accums-0.DI.h-accums-1.DI. */
1058 /* 64 */ { 16, 16, 0xffff },
1059 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.h-accums-1.DI.src1.SI.src2.SI. */
1060 /* 65 */ { 16, 16, 0xf0f0 },
1061 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.condbit.UBI. */
1062 /* 66 */ { 16, 16, 0xffff },
1063 };
1064
1065 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
1066 #define SYN(n) (& syntax_table[n])
1067 #define FMT(n) (& format_table[n])
1068
1069 /* The instruction table. */
1070
1071 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1072 {
1073 /* null first entry, end of all hash chains */
1074 { { 0 }, 0 },
1075 /* add $dr,$sr */
1076 {
1077 { 1, 1, 1, 1 },
1078 "add", "add", SYN (0), FMT (0), 0xa0,
1079 & fmt_0_add_ops[0],
1080 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1081 },
1082 /* add3 $dr,$sr,#$slo16 */
1083 {
1084 { 1, 1, 1, 1 },
1085 "add3", "add3", SYN (1), FMT (1), 0x80a00000,
1086 & fmt_1_add3_ops[0],
1087 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1088 },
1089 /* add3 $dr,$sr,$slo16 */
1090 {
1091 { 1, 1, 1, 1 },
1092 "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
1093 & fmt_1_add3_ops[0],
1094 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1095 },
1096 /* and $dr,$sr */
1097 {
1098 { 1, 1, 1, 1 },
1099 "and", "and", SYN (0), FMT (0), 0xc0,
1100 & fmt_0_add_ops[0],
1101 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1102 },
1103 /* and3 $dr,$sr,#$uimm16 */
1104 {
1105 { 1, 1, 1, 1 },
1106 "and3", "and3", SYN (3), FMT (2), 0x80c00000,
1107 & fmt_2_and3_ops[0],
1108 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1109 },
1110 /* and3 $dr,$sr,$uimm16 */
1111 {
1112 { 1, 1, 1, 1 },
1113 "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
1114 & fmt_2_and3_ops[0],
1115 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1116 },
1117 /* or $dr,$sr */
1118 {
1119 { 1, 1, 1, 1 },
1120 "or", "or", SYN (0), FMT (0), 0xe0,
1121 & fmt_0_add_ops[0],
1122 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1123 },
1124 /* or3 $dr,$sr,#$ulo16 */
1125 {
1126 { 1, 1, 1, 1 },
1127 "or3", "or3", SYN (5), FMT (3), 0x80e00000,
1128 & fmt_3_or3_ops[0],
1129 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1130 },
1131 /* or3 $dr,$sr,$ulo16 */
1132 {
1133 { 1, 1, 1, 1 },
1134 "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
1135 & fmt_3_or3_ops[0],
1136 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1137 },
1138 /* xor $dr,$sr */
1139 {
1140 { 1, 1, 1, 1 },
1141 "xor", "xor", SYN (0), FMT (0), 0xd0,
1142 & fmt_0_add_ops[0],
1143 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1144 },
1145 /* xor3 $dr,$sr,#$uimm16 */
1146 {
1147 { 1, 1, 1, 1 },
1148 "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
1149 & fmt_2_and3_ops[0],
1150 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1151 },
1152 /* xor3 $dr,$sr,$uimm16 */
1153 {
1154 { 1, 1, 1, 1 },
1155 "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
1156 & fmt_2_and3_ops[0],
1157 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1158 },
1159 /* addi $dr,#$simm8 */
1160 {
1161 { 1, 1, 1, 1 },
1162 "addi", "addi", SYN (7), FMT (4), 0x4000,
1163 & fmt_4_addi_ops[0],
1164 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1165 },
1166 /* addi $dr,$simm8 */
1167 {
1168 { 1, 1, 1, 1 },
1169 "addi.a", "addi", SYN (8), FMT (4), 0x4000,
1170 & fmt_4_addi_ops[0],
1171 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1172 },
1173 /* addv $dr,$sr */
1174 {
1175 { 1, 1, 1, 1 },
1176 "addv", "addv", SYN (0), FMT (0), 0x80,
1177 & fmt_0_add_ops[0],
1178 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1179 },
1180 /* addv3 $dr,$sr,#$simm16 */
1181 {
1182 { 1, 1, 1, 1 },
1183 "addv3", "addv3", SYN (9), FMT (5), 0x80800000,
1184 & fmt_5_addv3_ops[0],
1185 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1186 },
1187 /* addv3 $dr,$sr,$simm16 */
1188 {
1189 { 1, 1, 1, 1 },
1190 "addv3.a", "addv3", SYN (10), FMT (5), 0x80800000,
1191 & fmt_5_addv3_ops[0],
1192 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1193 },
1194 /* addx $dr,$sr */
1195 {
1196 { 1, 1, 1, 1 },
1197 "addx", "addx", SYN (0), FMT (6), 0x90,
1198 & fmt_6_addx_ops[0],
1199 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1200 },
1201 /* bc $disp8 */
1202 {
1203 { 1, 1, 1, 1 },
1204 "bc8", "bc", SYN (11), FMT (7), 0x7c00,
1205 & fmt_7_bc8_ops[0],
1206 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1207 },
1208 /* bc.s $disp8 */
1209 {
1210 { 1, 1, 1, 1 },
1211 "bc8.s", "bc.s", SYN (11), FMT (8), 0x7c00,
1212 0,
1213 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1214 },
1215 /* bc $disp24 */
1216 {
1217 { 1, 1, 1, 1 },
1218 "bc24", "bc", SYN (12), FMT (9), 0xfc000000,
1219 & fmt_9_bc24_ops[0],
1220 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1221 },
1222 /* bc.l $disp24 */
1223 {
1224 { 1, 1, 1, 1 },
1225 "bc24.l", "bc.l", SYN (12), FMT (10), 0xfc000000,
1226 0,
1227 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1228 },
1229 /* beq $src1,$src2,$disp16 */
1230 {
1231 { 1, 1, 1, 1 },
1232 "beq", "beq", SYN (13), FMT (11), 0xb0000000,
1233 & fmt_11_beq_ops[0],
1234 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1235 },
1236 /* beqz $src2,$disp16 */
1237 {
1238 { 1, 1, 1, 1 },
1239 "beqz", "beqz", SYN (14), FMT (12), 0xb0800000,
1240 & fmt_12_beqz_ops[0],
1241 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1242 },
1243 /* bgez $src2,$disp16 */
1244 {
1245 { 1, 1, 1, 1 },
1246 "bgez", "bgez", SYN (14), FMT (12), 0xb0b00000,
1247 & fmt_12_beqz_ops[0],
1248 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1249 },
1250 /* bgtz $src2,$disp16 */
1251 {
1252 { 1, 1, 1, 1 },
1253 "bgtz", "bgtz", SYN (14), FMT (12), 0xb0d00000,
1254 & fmt_12_beqz_ops[0],
1255 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1256 },
1257 /* blez $src2,$disp16 */
1258 {
1259 { 1, 1, 1, 1 },
1260 "blez", "blez", SYN (14), FMT (12), 0xb0c00000,
1261 & fmt_12_beqz_ops[0],
1262 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1263 },
1264 /* bltz $src2,$disp16 */
1265 {
1266 { 1, 1, 1, 1 },
1267 "bltz", "bltz", SYN (14), FMT (12), 0xb0a00000,
1268 & fmt_12_beqz_ops[0],
1269 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1270 },
1271 /* bnez $src2,$disp16 */
1272 {
1273 { 1, 1, 1, 1 },
1274 "bnez", "bnez", SYN (14), FMT (12), 0xb0900000,
1275 & fmt_12_beqz_ops[0],
1276 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1277 },
1278 /* bl $disp8 */
1279 {
1280 { 1, 1, 1, 1 },
1281 "bl8", "bl", SYN (11), FMT (13), 0x7e00,
1282 & fmt_13_bl8_ops[0],
1283 { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1284 },
1285 /* bl.s $disp8 */
1286 {
1287 { 1, 1, 1, 1 },
1288 "bl8.s", "bl.s", SYN (11), FMT (8), 0x7e00,
1289 0,
1290 { 4, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1291 },
1292 /* bl $disp24 */
1293 {
1294 { 1, 1, 1, 1 },
1295 "bl24", "bl", SYN (12), FMT (14), 0xfe000000,
1296 & fmt_14_bl24_ops[0],
1297 { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1298 },
1299 /* bl.l $disp24 */
1300 {
1301 { 1, 1, 1, 1 },
1302 "bl24.l", "bl.l", SYN (12), FMT (10), 0xfe000000,
1303 0,
1304 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1305 },
1306 /* start-sanitize-m32rx */
1307 /* bcl $disp8 */
1308 {
1309 { 1, 1, 1, 1 },
1310 "bcl8", "bcl", SYN (11), FMT (15), 0x7800,
1311 & fmt_15_bcl8_ops[0],
1312 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1313 },
1314 /* end-sanitize-m32rx */
1315 /* start-sanitize-m32rx */
1316 /* bcl.s $disp8 */
1317 {
1318 { 1, 1, 1, 1 },
1319 "bcl8.s", "bcl.s", SYN (11), FMT (8), 0x7800,
1320 0,
1321 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1322 },
1323 /* end-sanitize-m32rx */
1324 /* start-sanitize-m32rx */
1325 /* bcl $disp24 */
1326 {
1327 { 1, 1, 1, 1 },
1328 "bcl24", "bcl", SYN (12), FMT (16), 0xf8000000,
1329 & fmt_16_bcl24_ops[0],
1330 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1331 },
1332 /* end-sanitize-m32rx */
1333 /* start-sanitize-m32rx */
1334 /* bcl.l $disp24 */
1335 {
1336 { 1, 1, 1, 1 },
1337 "bcl24.l", "bcl.l", SYN (12), FMT (10), 0xf8000000,
1338 0,
1339 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1340 },
1341 /* end-sanitize-m32rx */
1342 /* bnc $disp8 */
1343 {
1344 { 1, 1, 1, 1 },
1345 "bnc8", "bnc", SYN (11), FMT (7), 0x7d00,
1346 & fmt_7_bc8_ops[0],
1347 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1348 },
1349 /* bnc.s $disp8 */
1350 {
1351 { 1, 1, 1, 1 },
1352 "bnc8.s", "bnc.s", SYN (11), FMT (8), 0x7d00,
1353 0,
1354 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1355 },
1356 /* bnc $disp24 */
1357 {
1358 { 1, 1, 1, 1 },
1359 "bnc24", "bnc", SYN (12), FMT (9), 0xfd000000,
1360 & fmt_9_bc24_ops[0],
1361 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1362 },
1363 /* bnc.l $disp24 */
1364 {
1365 { 1, 1, 1, 1 },
1366 "bnc24.l", "bnc.l", SYN (12), FMT (10), 0xfd000000,
1367 0,
1368 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1369 },
1370 /* bne $src1,$src2,$disp16 */
1371 {
1372 { 1, 1, 1, 1 },
1373 "bne", "bne", SYN (13), FMT (11), 0xb0100000,
1374 & fmt_11_beq_ops[0],
1375 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1376 },
1377 /* bra $disp8 */
1378 {
1379 { 1, 1, 1, 1 },
1380 "bra8", "bra", SYN (11), FMT (17), 0x7f00,
1381 & fmt_17_bra8_ops[0],
1382 { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1383 },
1384 /* bra.s $disp8 */
1385 {
1386 { 1, 1, 1, 1 },
1387 "bra8.s", "bra.s", SYN (11), FMT (8), 0x7f00,
1388 0,
1389 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1390 },
1391 /* bra $disp24 */
1392 {
1393 { 1, 1, 1, 1 },
1394 "bra24", "bra", SYN (12), FMT (18), 0xff000000,
1395 & fmt_18_bra24_ops[0],
1396 { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1397 },
1398 /* bra.l $disp24 */
1399 {
1400 { 1, 1, 1, 1 },
1401 "bra24.l", "bra.l", SYN (12), FMT (10), 0xff000000,
1402 0,
1403 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1404 },
1405 /* start-sanitize-m32rx */
1406 /* bncl $disp8 */
1407 {
1408 { 1, 1, 1, 1 },
1409 "bncl8", "bncl", SYN (11), FMT (15), 0x7900,
1410 & fmt_15_bcl8_ops[0],
1411 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1412 },
1413 /* end-sanitize-m32rx */
1414 /* start-sanitize-m32rx */
1415 /* bncl.s $disp8 */
1416 {
1417 { 1, 1, 1, 1 },
1418 "bncl8.s", "bncl.s", SYN (11), FMT (8), 0x7900,
1419 0,
1420 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1421 },
1422 /* end-sanitize-m32rx */
1423 /* start-sanitize-m32rx */
1424 /* bncl $disp24 */
1425 {
1426 { 1, 1, 1, 1 },
1427 "bncl24", "bncl", SYN (12), FMT (16), 0xf9000000,
1428 & fmt_16_bcl24_ops[0],
1429 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1430 },
1431 /* end-sanitize-m32rx */
1432 /* start-sanitize-m32rx */
1433 /* bncl.l $disp24 */
1434 {
1435 { 1, 1, 1, 1 },
1436 "bncl24.l", "bncl.l", SYN (12), FMT (10), 0xf9000000,
1437 0,
1438 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1439 },
1440 /* end-sanitize-m32rx */
1441 /* cmp $src1,$src2 */
1442 {
1443 { 1, 1, 1, 1 },
1444 "cmp", "cmp", SYN (15), FMT (19), 0x40,
1445 & fmt_19_cmp_ops[0],
1446 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1447 },
1448 /* cmpi $src2,#$simm16 */
1449 {
1450 { 1, 1, 1, 1 },
1451 "cmpi", "cmpi", SYN (16), FMT (20), 0x80400000,
1452 & fmt_20_cmpi_ops[0],
1453 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1454 },
1455 /* cmpi $src2,$simm16 */
1456 {
1457 { 1, 1, 1, 1 },
1458 "cmpi.a", "cmpi", SYN (17), FMT (20), 0x80400000,
1459 & fmt_20_cmpi_ops[0],
1460 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1461 },
1462 /* cmpu $src1,$src2 */
1463 {
1464 { 1, 1, 1, 1 },
1465 "cmpu", "cmpu", SYN (15), FMT (19), 0x50,
1466 & fmt_19_cmp_ops[0],
1467 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1468 },
1469 /* cmpui $src2,#$uimm16 */
1470 {
1471 { 1, 1, 1, 1 },
1472 "cmpui", "cmpui", SYN (18), FMT (21), 0x80500000,
1473 & fmt_21_cmpui_ops[0],
1474 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1475 },
1476 /* cmpui $src2,$uimm16 */
1477 {
1478 { 1, 1, 1, 1 },
1479 "cmpui.a", "cmpui", SYN (19), FMT (21), 0x80500000,
1480 & fmt_21_cmpui_ops[0],
1481 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1482 },
1483 /* start-sanitize-m32rx */
1484 /* cmpeq $src1,$src2 */
1485 {
1486 { 1, 1, 1, 1 },
1487 "cmpeq", "cmpeq", SYN (15), FMT (19), 0x60,
1488 & fmt_19_cmp_ops[0],
1489 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1490 },
1491 /* end-sanitize-m32rx */
1492 /* start-sanitize-m32rx */
1493 /* cmpz $src2 */
1494 {
1495 { 1, 1, 1, 1 },
1496 "cmpz", "cmpz", SYN (20), FMT (22), 0x70,
1497 & fmt_22_cmpz_ops[0],
1498 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1499 },
1500 /* end-sanitize-m32rx */
1501 /* div $dr,$sr */
1502 {
1503 { 1, 1, 1, 1 },
1504 "div", "div", SYN (0), FMT (23), 0x90000000,
1505 & fmt_23_div_ops[0],
1506 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1507 },
1508 /* divu $dr,$sr */
1509 {
1510 { 1, 1, 1, 1 },
1511 "divu", "divu", SYN (0), FMT (23), 0x90100000,
1512 & fmt_23_div_ops[0],
1513 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1514 },
1515 /* rem $dr,$sr */
1516 {
1517 { 1, 1, 1, 1 },
1518 "rem", "rem", SYN (0), FMT (23), 0x90200000,
1519 & fmt_23_div_ops[0],
1520 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1521 },
1522 /* remu $dr,$sr */
1523 {
1524 { 1, 1, 1, 1 },
1525 "remu", "remu", SYN (0), FMT (23), 0x90300000,
1526 & fmt_23_div_ops[0],
1527 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1528 },
1529 /* start-sanitize-m32rx */
1530 /* divh $dr,$sr */
1531 {
1532 { 1, 1, 1, 1 },
1533 "divh", "divh", SYN (0), FMT (23), 0x90000010,
1534 & fmt_23_div_ops[0],
1535 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1536 },
1537 /* end-sanitize-m32rx */
1538 /* start-sanitize-m32rx */
1539 /* jc $sr */
1540 {
1541 { 1, 1, 1, 1 },
1542 "jc", "jc", SYN (21), FMT (24), 0x1cc0,
1543 & fmt_24_jc_ops[0],
1544 { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1545 },
1546 /* end-sanitize-m32rx */
1547 /* start-sanitize-m32rx */
1548 /* jnc $sr */
1549 {
1550 { 1, 1, 1, 1 },
1551 "jnc", "jnc", SYN (21), FMT (24), 0x1dc0,
1552 & fmt_24_jc_ops[0],
1553 { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1554 },
1555 /* end-sanitize-m32rx */
1556 /* jl $sr */
1557 {
1558 { 1, 1, 1, 1 },
1559 "jl", "jl", SYN (21), FMT (25), 0x1ec0,
1560 & fmt_25_jl_ops[0],
1561 { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1562 },
1563 /* jmp $sr */
1564 {
1565 { 1, 1, 1, 1 },
1566 "jmp", "jmp", SYN (21), FMT (26), 0x1fc0,
1567 & fmt_26_jmp_ops[0],
1568 { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1569 },
1570 /* ld $dr,@$sr */
1571 {
1572 { 1, 1, 1, 1 },
1573 "ld", "ld", SYN (22), FMT (27), 0x20c0,
1574 & fmt_27_ld_ops[0],
1575 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1576 },
1577 /* ld $dr,@($sr) */
1578 {
1579 { 1, 1, 1, 1 },
1580 "ld-2", "ld", SYN (23), FMT (28), 0x20c0,
1581 0,
1582 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1583 },
1584 /* ld $dr,@($slo16,$sr) */
1585 {
1586 { 1, 1, 1, 1 },
1587 "ld-d", "ld", SYN (24), FMT (29), 0xa0c00000,
1588 & fmt_29_ld_d_ops[0],
1589 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1590 },
1591 /* ld $dr,@($sr,$slo16) */
1592 {
1593 { 1, 1, 1, 1 },
1594 "ld-d2", "ld", SYN (25), FMT (30), 0xa0c00000,
1595 0,
1596 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1597 },
1598 /* ldb $dr,@$sr */
1599 {
1600 { 1, 1, 1, 1 },
1601 "ldb", "ldb", SYN (22), FMT (31), 0x2080,
1602 & fmt_31_ldb_ops[0],
1603 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1604 },
1605 /* ldb $dr,@($sr) */
1606 {
1607 { 1, 1, 1, 1 },
1608 "ldb-2", "ldb", SYN (23), FMT (28), 0x2080,
1609 0,
1610 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1611 },
1612 /* ldb $dr,@($slo16,$sr) */
1613 {
1614 { 1, 1, 1, 1 },
1615 "ldb-d", "ldb", SYN (24), FMT (32), 0xa0800000,
1616 & fmt_32_ldb_d_ops[0],
1617 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1618 },
1619 /* ldb $dr,@($sr,$slo16) */
1620 {
1621 { 1, 1, 1, 1 },
1622 "ldb-d2", "ldb", SYN (25), FMT (30), 0xa0800000,
1623 0,
1624 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1625 },
1626 /* ldh $dr,@$sr */
1627 {
1628 { 1, 1, 1, 1 },
1629 "ldh", "ldh", SYN (22), FMT (33), 0x20a0,
1630 & fmt_33_ldh_ops[0],
1631 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1632 },
1633 /* ldh $dr,@($sr) */
1634 {
1635 { 1, 1, 1, 1 },
1636 "ldh-2", "ldh", SYN (23), FMT (28), 0x20a0,
1637 0,
1638 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1639 },
1640 /* ldh $dr,@($slo16,$sr) */
1641 {
1642 { 1, 1, 1, 1 },
1643 "ldh-d", "ldh", SYN (24), FMT (34), 0xa0a00000,
1644 & fmt_34_ldh_d_ops[0],
1645 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1646 },
1647 /* ldh $dr,@($sr,$slo16) */
1648 {
1649 { 1, 1, 1, 1 },
1650 "ldh-d2", "ldh", SYN (25), FMT (30), 0xa0a00000,
1651 0,
1652 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1653 },
1654 /* ldub $dr,@$sr */
1655 {
1656 { 1, 1, 1, 1 },
1657 "ldub", "ldub", SYN (22), FMT (31), 0x2090,
1658 & fmt_31_ldb_ops[0],
1659 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1660 },
1661 /* ldub $dr,@($sr) */
1662 {
1663 { 1, 1, 1, 1 },
1664 "ldub-2", "ldub", SYN (23), FMT (28), 0x2090,
1665 0,
1666 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1667 },
1668 /* ldub $dr,@($slo16,$sr) */
1669 {
1670 { 1, 1, 1, 1 },
1671 "ldub-d", "ldub", SYN (24), FMT (32), 0xa0900000,
1672 & fmt_32_ldb_d_ops[0],
1673 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1674 },
1675 /* ldub $dr,@($sr,$slo16) */
1676 {
1677 { 1, 1, 1, 1 },
1678 "ldub-d2", "ldub", SYN (25), FMT (30), 0xa0900000,
1679 0,
1680 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1681 },
1682 /* lduh $dr,@$sr */
1683 {
1684 { 1, 1, 1, 1 },
1685 "lduh", "lduh", SYN (22), FMT (33), 0x20b0,
1686 & fmt_33_ldh_ops[0],
1687 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1688 },
1689 /* lduh $dr,@($sr) */
1690 {
1691 { 1, 1, 1, 1 },
1692 "lduh-2", "lduh", SYN (23), FMT (28), 0x20b0,
1693 0,
1694 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1695 },
1696 /* lduh $dr,@($slo16,$sr) */
1697 {
1698 { 1, 1, 1, 1 },
1699 "lduh-d", "lduh", SYN (24), FMT (34), 0xa0b00000,
1700 & fmt_34_ldh_d_ops[0],
1701 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1702 },
1703 /* lduh $dr,@($sr,$slo16) */
1704 {
1705 { 1, 1, 1, 1 },
1706 "lduh-d2", "lduh", SYN (25), FMT (30), 0xa0b00000,
1707 0,
1708 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1709 },
1710 /* ld $dr,@$sr+ */
1711 {
1712 { 1, 1, 1, 1 },
1713 "ld-plus", "ld", SYN (26), FMT (27), 0x20e0,
1714 & fmt_27_ld_ops[0],
1715 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
1716 },
1717 /* ld24 $dr,#$uimm24 */
1718 {
1719 { 1, 1, 1, 1 },
1720 "ld24", "ld24", SYN (27), FMT (35), 0xe0000000,
1721 & fmt_35_ld24_ops[0],
1722 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1723 },
1724 /* ld24 $dr,$uimm24 */
1725 {
1726 { 1, 1, 1, 1 },
1727 "ld24.a", "ld24", SYN (28), FMT (35), 0xe0000000,
1728 & fmt_35_ld24_ops[0],
1729 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1730 },
1731 /* ldi $dr,#$simm8 */
1732 {
1733 { 1, 1, 1, 1 },
1734 "ldi8", "ldi", SYN (7), FMT (36), 0x6000,
1735 & fmt_36_ldi8_ops[0],
1736 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1737 },
1738 /* ldi $dr,$simm8 */
1739 {
1740 { 1, 1, 1, 1 },
1741 "ldi8.a", "ldi", SYN (8), FMT (36), 0x6000,
1742 & fmt_36_ldi8_ops[0],
1743 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1744 },
1745 /* ldi8 $dr,#$simm8 */
1746 {
1747 { 1, 1, 1, 1 },
1748 "ldi8a", "ldi8", SYN (7), FMT (36), 0x6000,
1749 & fmt_36_ldi8_ops[0],
1750 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1751 },
1752 /* ldi8 $dr,$simm8 */
1753 {
1754 { 1, 1, 1, 1 },
1755 "ldi8a.a", "ldi8", SYN (8), FMT (36), 0x6000,
1756 & fmt_36_ldi8_ops[0],
1757 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1758 },
1759 /* ldi $dr,$slo16 */
1760 {
1761 { 1, 1, 1, 1 },
1762 "ldi16", "ldi", SYN (29), FMT (37), 0x90f00000,
1763 & fmt_37_ldi16_ops[0],
1764 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1765 },
1766 /* ldi16 $dr,$slo16 */
1767 {
1768 { 1, 1, 1, 1 },
1769 "ldi16a", "ldi16", SYN (29), FMT (37), 0x90f00000,
1770 & fmt_37_ldi16_ops[0],
1771 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1772 },
1773 /* lock $dr,@$sr */
1774 {
1775 { 1, 1, 1, 1 },
1776 "lock", "lock", SYN (22), FMT (0), 0x20d0,
1777 & fmt_0_add_ops[0],
1778 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1779 },
1780 /* machi $src1,$src2 */
1781 {
1782 { 1, 1, 1, 1 },
1783 "machi", "machi", SYN (15), FMT (38), 0x3040,
1784 & fmt_38_machi_ops[0],
1785 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1786 },
1787 /* start-sanitize-m32rx */
1788 /* machi $src1,$src2,$acc */
1789 {
1790 { 1, 1, 1, 1 },
1791 "machi-a", "machi", SYN (30), FMT (39), 0x3040,
1792 & fmt_39_machi_a_ops[0],
1793 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1794 },
1795 /* end-sanitize-m32rx */
1796 /* maclo $src1,$src2 */
1797 {
1798 { 1, 1, 1, 1 },
1799 "maclo", "maclo", SYN (15), FMT (38), 0x3050,
1800 & fmt_38_machi_ops[0],
1801 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1802 },
1803 /* start-sanitize-m32rx */
1804 /* maclo $src1,$src2,$acc */
1805 {
1806 { 1, 1, 1, 1 },
1807 "maclo-a", "maclo", SYN (30), FMT (39), 0x3050,
1808 & fmt_39_machi_a_ops[0],
1809 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1810 },
1811 /* end-sanitize-m32rx */
1812 /* macwhi $src1,$src2 */
1813 {
1814 { 1, 1, 1, 1 },
1815 "macwhi", "macwhi", SYN (15), FMT (38), 0x3060,
1816 & fmt_38_machi_ops[0],
1817 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1818 },
1819 /* macwlo $src1,$src2 */
1820 {
1821 { 1, 1, 1, 1 },
1822 "macwlo", "macwlo", SYN (15), FMT (38), 0x3070,
1823 & fmt_38_machi_ops[0],
1824 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1825 },
1826 /* mul $dr,$sr */
1827 {
1828 { 1, 1, 1, 1 },
1829 "mul", "mul", SYN (0), FMT (0), 0x1060,
1830 & fmt_0_add_ops[0],
1831 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1832 },
1833 /* mulhi $src1,$src2 */
1834 {
1835 { 1, 1, 1, 1 },
1836 "mulhi", "mulhi", SYN (15), FMT (19), 0x3000,
1837 & fmt_19_cmp_ops[0],
1838 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1839 },
1840 /* start-sanitize-m32rx */
1841 /* mulhi $src1,$src2,$acc */
1842 {
1843 { 1, 1, 1, 1 },
1844 "mulhi-a", "mulhi", SYN (30), FMT (40), 0x3000,
1845 & fmt_40_mulhi_a_ops[0],
1846 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1847 },
1848 /* end-sanitize-m32rx */
1849 /* mullo $src1,$src2 */
1850 {
1851 { 1, 1, 1, 1 },
1852 "mullo", "mullo", SYN (15), FMT (19), 0x3010,
1853 & fmt_19_cmp_ops[0],
1854 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1855 },
1856 /* start-sanitize-m32rx */
1857 /* mullo $src1,$src2,$acc */
1858 {
1859 { 1, 1, 1, 1 },
1860 "mullo-a", "mullo", SYN (30), FMT (40), 0x3010,
1861 & fmt_40_mulhi_a_ops[0],
1862 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1863 },
1864 /* end-sanitize-m32rx */
1865 /* mulwhi $src1,$src2 */
1866 {
1867 { 1, 1, 1, 1 },
1868 "mulwhi", "mulwhi", SYN (15), FMT (19), 0x3020,
1869 & fmt_19_cmp_ops[0],
1870 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1871 },
1872 /* mulwlo $src1,$src2 */
1873 {
1874 { 1, 1, 1, 1 },
1875 "mulwlo", "mulwlo", SYN (15), FMT (19), 0x3030,
1876 & fmt_19_cmp_ops[0],
1877 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1878 },
1879 /* mv $dr,$sr */
1880 {
1881 { 1, 1, 1, 1 },
1882 "mv", "mv", SYN (0), FMT (41), 0x1080,
1883 & fmt_41_mv_ops[0],
1884 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1885 },
1886 /* mvfachi $dr */
1887 {
1888 { 1, 1, 1, 1 },
1889 "mvfachi", "mvfachi", SYN (31), FMT (42), 0x50f0,
1890 & fmt_42_mvfachi_ops[0],
1891 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1892 },
1893 /* start-sanitize-m32rx */
1894 /* mvfachi $dr,$accs */
1895 {
1896 { 1, 1, 1, 1 },
1897 "mvfachi-a", "mvfachi", SYN (32), FMT (43), 0x50f0,
1898 & fmt_43_mvfachi_a_ops[0],
1899 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1900 },
1901 /* end-sanitize-m32rx */
1902 /* mvfaclo $dr */
1903 {
1904 { 1, 1, 1, 1 },
1905 "mvfaclo", "mvfaclo", SYN (31), FMT (42), 0x50f1,
1906 & fmt_42_mvfachi_ops[0],
1907 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1908 },
1909 /* start-sanitize-m32rx */
1910 /* mvfaclo $dr,$accs */
1911 {
1912 { 1, 1, 1, 1 },
1913 "mvfaclo-a", "mvfaclo", SYN (32), FMT (43), 0x50f1,
1914 & fmt_43_mvfachi_a_ops[0],
1915 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1916 },
1917 /* end-sanitize-m32rx */
1918 /* mvfacmi $dr */
1919 {
1920 { 1, 1, 1, 1 },
1921 "mvfacmi", "mvfacmi", SYN (31), FMT (42), 0x50f2,
1922 & fmt_42_mvfachi_ops[0],
1923 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1924 },
1925 /* start-sanitize-m32rx */
1926 /* mvfacmi $dr,$accs */
1927 {
1928 { 1, 1, 1, 1 },
1929 "mvfacmi-a", "mvfacmi", SYN (32), FMT (43), 0x50f2,
1930 & fmt_43_mvfachi_a_ops[0],
1931 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1932 },
1933 /* end-sanitize-m32rx */
1934 /* mvfc $dr,$scr */
1935 {
1936 { 1, 1, 1, 1 },
1937 "mvfc", "mvfc", SYN (33), FMT (44), 0x1090,
1938 & fmt_44_mvfc_ops[0],
1939 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1940 },
1941 /* mvtachi $src1 */
1942 {
1943 { 1, 1, 1, 1 },
1944 "mvtachi", "mvtachi", SYN (34), FMT (45), 0x5070,
1945 & fmt_45_mvtachi_ops[0],
1946 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1947 },
1948 /* start-sanitize-m32rx */
1949 /* mvtachi $src1,$accs */
1950 {
1951 { 1, 1, 1, 1 },
1952 "mvtachi-a", "mvtachi", SYN (35), FMT (46), 0x5070,
1953 & fmt_46_mvtachi_a_ops[0],
1954 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1955 },
1956 /* end-sanitize-m32rx */
1957 /* mvtaclo $src1 */
1958 {
1959 { 1, 1, 1, 1 },
1960 "mvtaclo", "mvtaclo", SYN (34), FMT (45), 0x5071,
1961 & fmt_45_mvtachi_ops[0],
1962 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1963 },
1964 /* start-sanitize-m32rx */
1965 /* mvtaclo $src1,$accs */
1966 {
1967 { 1, 1, 1, 1 },
1968 "mvtaclo-a", "mvtaclo", SYN (35), FMT (46), 0x5071,
1969 & fmt_46_mvtachi_a_ops[0],
1970 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1971 },
1972 /* end-sanitize-m32rx */
1973 /* mvtc $sr,$dcr */
1974 {
1975 { 1, 1, 1, 1 },
1976 "mvtc", "mvtc", SYN (36), FMT (47), 0x10a0,
1977 & fmt_47_mvtc_ops[0],
1978 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1979 },
1980 /* neg $dr,$sr */
1981 {
1982 { 1, 1, 1, 1 },
1983 "neg", "neg", SYN (0), FMT (41), 0x30,
1984 & fmt_41_mv_ops[0],
1985 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1986 },
1987 /* nop */
1988 {
1989 { 1, 1, 1, 1 },
1990 "nop", "nop", SYN (37), FMT (48), 0x7000,
1991 0,
1992 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1993 },
1994 /* not $dr,$sr */
1995 {
1996 { 1, 1, 1, 1 },
1997 "not", "not", SYN (0), FMT (41), 0xb0,
1998 & fmt_41_mv_ops[0],
1999 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2000 },
2001 /* rac */
2002 {
2003 { 1, 1, 1, 1 },
2004 "rac", "rac", SYN (37), FMT (49), 0x5090,
2005 & fmt_49_rac_ops[0],
2006 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2007 },
2008 /* start-sanitize-m32rx */
2009 /* rac $accd */
2010 {
2011 { 1, 1, 1, 1 },
2012 "rac-d", "rac", SYN (38), FMT (50), 0x5090,
2013 & fmt_50_rac_d_ops[0],
2014 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2015 },
2016 /* end-sanitize-m32rx */
2017 /* start-sanitize-m32rx */
2018 /* rac $accd,$accs */
2019 {
2020 { 1, 1, 1, 1 },
2021 "rac-ds", "rac", SYN (39), FMT (51), 0x5090,
2022 & fmt_51_rac_ds_ops[0],
2023 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2024 },
2025 /* end-sanitize-m32rx */
2026 /* start-sanitize-m32rx */
2027 /* rac $accd,$accs,#$imm1 */
2028 {
2029 { 1, 1, 1, 1 },
2030 "rac-dsi", "rac", SYN (40), FMT (52), 0x5090,
2031 & fmt_52_rac_dsi_ops[0],
2032 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2033 },
2034 /* end-sanitize-m32rx */
2035 /* rach */
2036 {
2037 { 1, 1, 1, 1 },
2038 "rach", "rach", SYN (37), FMT (49), 0x5080,
2039 & fmt_49_rac_ops[0],
2040 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2041 },
2042 /* start-sanitize-m32rx */
2043 /* rach $accd */
2044 {
2045 { 1, 1, 1, 1 },
2046 "rach-d", "rach", SYN (38), FMT (50), 0x5080,
2047 & fmt_50_rac_d_ops[0],
2048 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2049 },
2050 /* end-sanitize-m32rx */
2051 /* start-sanitize-m32rx */
2052 /* rach $accd,$accs */
2053 {
2054 { 1, 1, 1, 1 },
2055 "rach-ds", "rach", SYN (39), FMT (51), 0x5080,
2056 & fmt_51_rac_ds_ops[0],
2057 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2058 },
2059 /* end-sanitize-m32rx */
2060 /* start-sanitize-m32rx */
2061 /* rach $accd,$accs,#$imm1 */
2062 {
2063 { 1, 1, 1, 1 },
2064 "rach-dsi", "rach", SYN (40), FMT (52), 0x5080,
2065 & fmt_52_rac_dsi_ops[0],
2066 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2067 },
2068 /* end-sanitize-m32rx */
2069 /* rte */
2070 {
2071 { 1, 1, 1, 1 },
2072 "rte", "rte", SYN (37), FMT (53), 0x10d6,
2073 & fmt_53_rte_ops[0],
2074 { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2075 },
2076 /* seth $dr,#$hi16 */
2077 {
2078 { 1, 1, 1, 1 },
2079 "seth", "seth", SYN (41), FMT (54), 0xd0c00000,
2080 & fmt_54_seth_ops[0],
2081 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2082 },
2083 /* seth $dr,$hi16 */
2084 {
2085 { 1, 1, 1, 1 },
2086 "seth.a", "seth", SYN (42), FMT (54), 0xd0c00000,
2087 & fmt_54_seth_ops[0],
2088 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2089 },
2090 /* sll $dr,$sr */
2091 {
2092 { 1, 1, 1, 1 },
2093 "sll", "sll", SYN (0), FMT (0), 0x1040,
2094 & fmt_0_add_ops[0],
2095 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2096 },
2097 /* sll3 $dr,$sr,#$simm16 */
2098 {
2099 { 1, 1, 1, 1 },
2100 "sll3", "sll3", SYN (9), FMT (5), 0x90c00000,
2101 & fmt_5_addv3_ops[0],
2102 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2103 },
2104 /* sll3 $dr,$sr,$simm16 */
2105 {
2106 { 1, 1, 1, 1 },
2107 "sll3.a", "sll3", SYN (10), FMT (5), 0x90c00000,
2108 & fmt_5_addv3_ops[0],
2109 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2110 },
2111 /* slli $dr,#$uimm5 */
2112 {
2113 { 1, 1, 1, 1 },
2114 "slli", "slli", SYN (43), FMT (55), 0x5040,
2115 & fmt_55_slli_ops[0],
2116 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2117 },
2118 /* slli $dr,$uimm5 */
2119 {
2120 { 1, 1, 1, 1 },
2121 "slli.a", "slli", SYN (44), FMT (55), 0x5040,
2122 & fmt_55_slli_ops[0],
2123 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2124 },
2125 /* sra $dr,$sr */
2126 {
2127 { 1, 1, 1, 1 },
2128 "sra", "sra", SYN (0), FMT (0), 0x1020,
2129 & fmt_0_add_ops[0],
2130 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2131 },
2132 /* sra3 $dr,$sr,#$simm16 */
2133 {
2134 { 1, 1, 1, 1 },
2135 "sra3", "sra3", SYN (9), FMT (5), 0x90a00000,
2136 & fmt_5_addv3_ops[0],
2137 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2138 },
2139 /* sra3 $dr,$sr,$simm16 */
2140 {
2141 { 1, 1, 1, 1 },
2142 "sra3.a", "sra3", SYN (10), FMT (5), 0x90a00000,
2143 & fmt_5_addv3_ops[0],
2144 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2145 },
2146 /* srai $dr,#$uimm5 */
2147 {
2148 { 1, 1, 1, 1 },
2149 "srai", "srai", SYN (43), FMT (55), 0x5020,
2150 & fmt_55_slli_ops[0],
2151 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2152 },
2153 /* srai $dr,$uimm5 */
2154 {
2155 { 1, 1, 1, 1 },
2156 "srai.a", "srai", SYN (44), FMT (55), 0x5020,
2157 & fmt_55_slli_ops[0],
2158 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2159 },
2160 /* srl $dr,$sr */
2161 {
2162 { 1, 1, 1, 1 },
2163 "srl", "srl", SYN (0), FMT (0), 0x1000,
2164 & fmt_0_add_ops[0],
2165 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2166 },
2167 /* srl3 $dr,$sr,#$simm16 */
2168 {
2169 { 1, 1, 1, 1 },
2170 "srl3", "srl3", SYN (9), FMT (5), 0x90800000,
2171 & fmt_5_addv3_ops[0],
2172 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2173 },
2174 /* srl3 $dr,$sr,$simm16 */
2175 {
2176 { 1, 1, 1, 1 },
2177 "srl3.a", "srl3", SYN (10), FMT (5), 0x90800000,
2178 & fmt_5_addv3_ops[0],
2179 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2180 },
2181 /* srli $dr,#$uimm5 */
2182 {
2183 { 1, 1, 1, 1 },
2184 "srli", "srli", SYN (43), FMT (55), 0x5000,
2185 & fmt_55_slli_ops[0],
2186 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2187 },
2188 /* srli $dr,$uimm5 */
2189 {
2190 { 1, 1, 1, 1 },
2191 "srli.a", "srli", SYN (44), FMT (55), 0x5000,
2192 & fmt_55_slli_ops[0],
2193 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2194 },
2195 /* st $src1,@$src2 */
2196 {
2197 { 1, 1, 1, 1 },
2198 "st", "st", SYN (45), FMT (19), 0x2040,
2199 & fmt_19_cmp_ops[0],
2200 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2201 },
2202 /* st $src1,@($src2) */
2203 {
2204 { 1, 1, 1, 1 },
2205 "st-2", "st", SYN (46), FMT (56), 0x2040,
2206 0,
2207 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2208 },
2209 /* st $src1,@($slo16,$src2) */
2210 {
2211 { 1, 1, 1, 1 },
2212 "st-d", "st", SYN (47), FMT (57), 0xa0400000,
2213 & fmt_57_st_d_ops[0],
2214 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2215 },
2216 /* st $src1,@($src2,$slo16) */
2217 {
2218 { 1, 1, 1, 1 },
2219 "st-d2", "st", SYN (48), FMT (58), 0xa0400000,
2220 0,
2221 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2222 },
2223 /* stb $src1,@$src2 */
2224 {
2225 { 1, 1, 1, 1 },
2226 "stb", "stb", SYN (45), FMT (19), 0x2000,
2227 & fmt_19_cmp_ops[0],
2228 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2229 },
2230 /* stb $src1,@($src2) */
2231 {
2232 { 1, 1, 1, 1 },
2233 "stb-2", "stb", SYN (46), FMT (56), 0x2000,
2234 0,
2235 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2236 },
2237 /* stb $src1,@($slo16,$src2) */
2238 {
2239 { 1, 1, 1, 1 },
2240 "stb-d", "stb", SYN (47), FMT (57), 0xa0000000,
2241 & fmt_57_st_d_ops[0],
2242 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2243 },
2244 /* stb $src1,@($src2,$slo16) */
2245 {
2246 { 1, 1, 1, 1 },
2247 "stb-d2", "stb", SYN (48), FMT (58), 0xa0000000,
2248 0,
2249 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2250 },
2251 /* sth $src1,@$src2 */
2252 {
2253 { 1, 1, 1, 1 },
2254 "sth", "sth", SYN (45), FMT (19), 0x2020,
2255 & fmt_19_cmp_ops[0],
2256 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2257 },
2258 /* sth $src1,@($src2) */
2259 {
2260 { 1, 1, 1, 1 },
2261 "sth-2", "sth", SYN (46), FMT (56), 0x2020,
2262 0,
2263 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2264 },
2265 /* sth $src1,@($slo16,$src2) */
2266 {
2267 { 1, 1, 1, 1 },
2268 "sth-d", "sth", SYN (47), FMT (57), 0xa0200000,
2269 & fmt_57_st_d_ops[0],
2270 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2271 },
2272 /* sth $src1,@($src2,$slo16) */
2273 {
2274 { 1, 1, 1, 1 },
2275 "sth-d2", "sth", SYN (48), FMT (58), 0xa0200000,
2276 0,
2277 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2278 },
2279 /* st $src1,@+$src2 */
2280 {
2281 { 1, 1, 1, 1 },
2282 "st-plus", "st", SYN (49), FMT (19), 0x2060,
2283 & fmt_19_cmp_ops[0],
2284 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
2285 },
2286 /* st $src1,@-$src2 */
2287 {
2288 { 1, 1, 1, 1 },
2289 "st-minus", "st", SYN (50), FMT (19), 0x2070,
2290 & fmt_19_cmp_ops[0],
2291 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
2292 },
2293 /* sub $dr,$sr */
2294 {
2295 { 1, 1, 1, 1 },
2296 "sub", "sub", SYN (0), FMT (0), 0x20,
2297 & fmt_0_add_ops[0],
2298 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2299 },
2300 /* subv $dr,$sr */
2301 {
2302 { 1, 1, 1, 1 },
2303 "subv", "subv", SYN (0), FMT (0), 0x0,
2304 & fmt_0_add_ops[0],
2305 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2306 },
2307 /* subx $dr,$sr */
2308 {
2309 { 1, 1, 1, 1 },
2310 "subx", "subx", SYN (0), FMT (6), 0x10,
2311 & fmt_6_addx_ops[0],
2312 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2313 },
2314 /* trap #$uimm4 */
2315 {
2316 { 1, 1, 1, 1 },
2317 "trap", "trap", SYN (51), FMT (59), 0x10f0,
2318 & fmt_59_trap_ops[0],
2319 { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2320 },
2321 /* trap $uimm4 */
2322 {
2323 { 1, 1, 1, 1 },
2324 "trap.a", "trap", SYN (52), FMT (59), 0x10f0,
2325 & fmt_59_trap_ops[0],
2326 { 4, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2327 },
2328 /* unlock $src1,@$src2 */
2329 {
2330 { 1, 1, 1, 1 },
2331 "unlock", "unlock", SYN (45), FMT (19), 0x2050,
2332 & fmt_19_cmp_ops[0],
2333 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2334 },
2335 /* push $src1 */
2336 {
2337 { 1, 1, 1, 1 },
2338 "push", "push", SYN (34), FMT (60), 0x207f,
2339 0,
2340 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2341 },
2342 /* pop $dr */
2343 {
2344 { 1, 1, 1, 1 },
2345 "pop", "pop", SYN (31), FMT (61), 0x20ef,
2346 0,
2347 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2348 },
2349 /* start-sanitize-m32rx */
2350 /* satb $dr,$src2 */
2351 {
2352 { 1, 1, 1, 1 },
2353 "satb", "satb", SYN (53), FMT (62), 0x80000100,
2354 & fmt_62_satb_ops[0],
2355 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2356 },
2357 /* end-sanitize-m32rx */
2358 /* start-sanitize-m32rx */
2359 /* sath $dr,$src2 */
2360 {
2361 { 1, 1, 1, 1 },
2362 "sath", "sath", SYN (53), FMT (62), 0x80000200,
2363 & fmt_62_satb_ops[0],
2364 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2365 },
2366 /* end-sanitize-m32rx */
2367 /* start-sanitize-m32rx */
2368 /* sat $dr,$src2 */
2369 {
2370 { 1, 1, 1, 1 },
2371 "sat", "sat", SYN (53), FMT (63), 0x80000000,
2372 & fmt_63_sat_ops[0],
2373 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2374 },
2375 /* end-sanitize-m32rx */
2376 /* start-sanitize-m32rx */
2377 /* pcmpbz $src2 */
2378 {
2379 { 1, 1, 1, 1 },
2380 "pcmpbz", "pcmpbz", SYN (20), FMT (22), 0x370,
2381 & fmt_22_cmpz_ops[0],
2382 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2383 },
2384 /* end-sanitize-m32rx */
2385 /* start-sanitize-m32rx */
2386 /* sadd */
2387 {
2388 { 1, 1, 1, 1 },
2389 "sadd", "sadd", SYN (37), FMT (64), 0x50e4,
2390 & fmt_64_sadd_ops[0],
2391 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2392 },
2393 /* end-sanitize-m32rx */
2394 /* start-sanitize-m32rx */
2395 /* macwu1 $src1,$src2 */
2396 {
2397 { 1, 1, 1, 1 },
2398 "macwu1", "macwu1", SYN (15), FMT (65), 0x50b0,
2399 & fmt_65_macwu1_ops[0],
2400 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2401 },
2402 /* end-sanitize-m32rx */
2403 /* start-sanitize-m32rx */
2404 /* msblo $src1,$src2 */
2405 {
2406 { 1, 1, 1, 1 },
2407 "msblo", "msblo", SYN (15), FMT (38), 0x50d0,
2408 & fmt_38_machi_ops[0],
2409 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2410 },
2411 /* end-sanitize-m32rx */
2412 /* start-sanitize-m32rx */
2413 /* mulwu1 $src1,$src2 */
2414 {
2415 { 1, 1, 1, 1 },
2416 "mulwu1", "mulwu1", SYN (15), FMT (19), 0x50a0,
2417 & fmt_19_cmp_ops[0],
2418 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2419 },
2420 /* end-sanitize-m32rx */
2421 /* start-sanitize-m32rx */
2422 /* maclh1 $src1,$src2 */
2423 {
2424 { 1, 1, 1, 1 },
2425 "maclh1", "maclh1", SYN (15), FMT (65), 0x50c0,
2426 & fmt_65_macwu1_ops[0],
2427 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2428 },
2429 /* end-sanitize-m32rx */
2430 /* start-sanitize-m32rx */
2431 /* sc */
2432 {
2433 { 1, 1, 1, 1 },
2434 "sc", "sc", SYN (37), FMT (66), 0x7401,
2435 & fmt_66_sc_ops[0],
2436 { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2437 },
2438 /* end-sanitize-m32rx */
2439 /* start-sanitize-m32rx */
2440 /* snc */
2441 {
2442 { 1, 1, 1, 1 },
2443 "snc", "snc", SYN (37), FMT (66), 0x7501,
2444 & fmt_66_sc_ops[0],
2445 { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2446 },
2447 /* end-sanitize-m32rx */
2448 };
2449
2450 #undef A
2451 #undef SYN
2452 #undef FMT
2453
2454 CGEN_INSN_TABLE m32r_cgen_insn_table =
2455 {
2456 & m32r_cgen_insn_table_entries[0],
2457 sizeof (CGEN_INSN),
2458 MAX_INSNS,
2459 NULL,
2460 m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2461 m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2462 };
2463
2464 /* The hash functions are recorded here to help keep assembler code out of
2465 the disassembler and vice versa. */
2466
2467 unsigned int
2468 m32r_cgen_asm_hash_insn (insn)
2469 const char * insn;
2470 {
2471 return CGEN_ASM_HASH (insn);
2472 }
2473
2474 unsigned int
2475 m32r_cgen_dis_hash_insn (buf, value)
2476 const char * buf;
2477 unsigned long value;
2478 {
2479 return CGEN_DIS_HASH (buf, value);
2480 }
2481
2482 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2483 {
2484 & m32r_cgen_hw_entries[0],
2485 & m32r_cgen_insn_table,
2486 };
2487
2488 void
2489 m32r_cgen_init_tables (mach)
2490 int mach;
2491 {
2492 }
2493
2494 /* Main entry point for stuffing values in cgen_fields. */
2495
2496 CGEN_INLINE void
2497 m32r_cgen_set_operand (opindex, valuep, fields)
2498 int opindex;
2499 const long * valuep;
2500 CGEN_FIELDS * fields;
2501 {
2502 switch (opindex)
2503 {
2504 case M32R_OPERAND_SR :
2505 fields->f_r2 = * valuep;
2506 break;
2507 case M32R_OPERAND_DR :
2508 fields->f_r1 = * valuep;
2509 break;
2510 case M32R_OPERAND_SRC1 :
2511 fields->f_r1 = * valuep;
2512 break;
2513 case M32R_OPERAND_SRC2 :
2514 fields->f_r2 = * valuep;
2515 break;
2516 case M32R_OPERAND_SCR :
2517 fields->f_r2 = * valuep;
2518 break;
2519 case M32R_OPERAND_DCR :
2520 fields->f_r1 = * valuep;
2521 break;
2522 case M32R_OPERAND_SIMM8 :
2523 fields->f_simm8 = * valuep;
2524 break;
2525 case M32R_OPERAND_SIMM16 :
2526 fields->f_simm16 = * valuep;
2527 break;
2528 case M32R_OPERAND_UIMM4 :
2529 fields->f_uimm4 = * valuep;
2530 break;
2531 case M32R_OPERAND_UIMM5 :
2532 fields->f_uimm5 = * valuep;
2533 break;
2534 case M32R_OPERAND_UIMM16 :
2535 fields->f_uimm16 = * valuep;
2536 break;
2537 /* start-sanitize-m32rx */
2538 case M32R_OPERAND_IMM1 :
2539 fields->f_imm1 = * valuep;
2540 break;
2541 /* end-sanitize-m32rx */
2542 /* start-sanitize-m32rx */
2543 case M32R_OPERAND_ACCD :
2544 fields->f_accd = * valuep;
2545 break;
2546 /* end-sanitize-m32rx */
2547 /* start-sanitize-m32rx */
2548 case M32R_OPERAND_ACCS :
2549 fields->f_accs = * valuep;
2550 break;
2551 /* end-sanitize-m32rx */
2552 /* start-sanitize-m32rx */
2553 case M32R_OPERAND_ACC :
2554 fields->f_acc = * valuep;
2555 break;
2556 /* end-sanitize-m32rx */
2557 case M32R_OPERAND_HI16 :
2558 fields->f_hi16 = * valuep;
2559 break;
2560 case M32R_OPERAND_SLO16 :
2561 fields->f_simm16 = * valuep;
2562 break;
2563 case M32R_OPERAND_ULO16 :
2564 fields->f_uimm16 = * valuep;
2565 break;
2566 case M32R_OPERAND_UIMM24 :
2567 fields->f_uimm24 = * valuep;
2568 break;
2569 case M32R_OPERAND_DISP8 :
2570 fields->f_disp8 = * valuep;
2571 break;
2572 case M32R_OPERAND_DISP16 :
2573 fields->f_disp16 = * valuep;
2574 break;
2575 case M32R_OPERAND_DISP24 :
2576 fields->f_disp24 = * valuep;
2577 break;
2578
2579 default :
2580 fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2581 opindex);
2582 abort ();
2583 }
2584 }
2585
2586 /* Main entry point for getting values from cgen_fields. */
2587
2588 CGEN_INLINE long
2589 m32r_cgen_get_operand (opindex, fields)
2590 int opindex;
2591 const CGEN_FIELDS * fields;
2592 {
2593 long value;
2594
2595 switch (opindex)
2596 {
2597 case M32R_OPERAND_SR :
2598 value = fields->f_r2;
2599 break;
2600 case M32R_OPERAND_DR :
2601 value = fields->f_r1;
2602 break;
2603 case M32R_OPERAND_SRC1 :
2604 value = fields->f_r1;
2605 break;
2606 case M32R_OPERAND_SRC2 :
2607 value = fields->f_r2;
2608 break;
2609 case M32R_OPERAND_SCR :
2610 value = fields->f_r2;
2611 break;
2612 case M32R_OPERAND_DCR :
2613 value = fields->f_r1;
2614 break;
2615 case M32R_OPERAND_SIMM8 :
2616 value = fields->f_simm8;
2617 break;
2618 case M32R_OPERAND_SIMM16 :
2619 value = fields->f_simm16;
2620 break;
2621 case M32R_OPERAND_UIMM4 :
2622 value = fields->f_uimm4;
2623 break;
2624 case M32R_OPERAND_UIMM5 :
2625 value = fields->f_uimm5;
2626 break;
2627 case M32R_OPERAND_UIMM16 :
2628 value = fields->f_uimm16;
2629 break;
2630 /* start-sanitize-m32rx */
2631 case M32R_OPERAND_IMM1 :
2632 value = fields->f_imm1;
2633 break;
2634 /* end-sanitize-m32rx */
2635 /* start-sanitize-m32rx */
2636 case M32R_OPERAND_ACCD :
2637 value = fields->f_accd;
2638 break;
2639 /* end-sanitize-m32rx */
2640 /* start-sanitize-m32rx */
2641 case M32R_OPERAND_ACCS :
2642 value = fields->f_accs;
2643 break;
2644 /* end-sanitize-m32rx */
2645 /* start-sanitize-m32rx */
2646 case M32R_OPERAND_ACC :
2647 value = fields->f_acc;
2648 break;
2649 /* end-sanitize-m32rx */
2650 case M32R_OPERAND_HI16 :
2651 value = fields->f_hi16;
2652 break;
2653 case M32R_OPERAND_SLO16 :
2654 value = fields->f_simm16;
2655 break;
2656 case M32R_OPERAND_ULO16 :
2657 value = fields->f_uimm16;
2658 break;
2659 case M32R_OPERAND_UIMM24 :
2660 value = fields->f_uimm24;
2661 break;
2662 case M32R_OPERAND_DISP8 :
2663 value = fields->f_disp8;
2664 break;
2665 case M32R_OPERAND_DISP16 :
2666 value = fields->f_disp16;
2667 break;
2668 case M32R_OPERAND_DISP24 :
2669 value = fields->f_disp24;
2670 break;
2671
2672 default :
2673 fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2674 opindex);
2675 abort ();
2676 }
2677
2678 return value;
2679 }
2680
GDB Binutils - Deliverables
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