opcodes/m32r-opc.c

   1 /* CGEN opcode support for m32r.
   2
   3 This file is machine generated.
   4
   5 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include "ansidecl.h"
  29 #include "libiberty.h"
  30 #include "bfd.h"
  31 #include "m32r-opc.h"
  32
  33 /* Attributes.  */
  34
  35 static const CGEN_ATTR_ENTRY MACH_attr[] =
  36 {  { "m32r", MACH_M32R },
  37   { 0, 0 }
  38 };
  39
  40 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  41 {  { "ABS-ADDR", NULL },
  42   { "FAKE", NULL },
  43   { "NEGATIVE", NULL },
  44   { "PC", NULL },
  45   { "PCREL-ADDR", NULL },
  46   { "RELAX", NULL },
  47   { "RELOC", NULL },
  48   { "SIGN-OPT", NULL },
  49   { "UNSIGNED", NULL },
  50   { 0, 0 }
  51 };
  52
  53 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
  54 {  { "ALIAS", NULL },
  55   { "COND-CTI", NULL },
  56   { "FILL-SLOT", NULL },
  57   { "RELAX", NULL },
  58   { "RELAX-BC", NULL },
  59   { "RELAX-BL", NULL },
  60   { "RELAX-BNC", NULL },
  61   { "RELAX-BRA", NULL },
  62   { "RELAXABLE", NULL },
  63   { "UNCOND-CTI", NULL },
  64   { 0, 0 }
  65 };
  66
  67 CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] =
  68 {  { "m32r", MACH_M32R }
  69 };
  70
  71 CGEN_KEYWORD m32r_cgen_opval_mach =
  72 {  & m32r_cgen_opval_mach_entries[0],
  73   1
  74 };
  75
  76 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
  77 {  { "fp", 13 },
  78   { "lr", 14 },
  79   { "sp", 15 },
  80   { "r0", 0 },
  81   { "r1", 1 },
  82   { "r2", 2 },
  83   { "r3", 3 },
  84   { "r4", 4 },
  85   { "r5", 5 },
  86   { "r6", 6 },
  87   { "r7", 7 },
  88   { "r8", 8 },
  89   { "r9", 9 },
  90   { "r10", 10 },
  91   { "r11", 11 },
  92   { "r12", 12 },
  93   { "r13", 13 },
  94   { "r14", 14 },
  95   { "r15", 15 }
  96 };
  97
  98 CGEN_KEYWORD m32r_cgen_opval_h_gr =
  99 {  & m32r_cgen_opval_h_gr_entries[0],
 100   19
 101 };
 102
 103 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 104 {  { "psw", 0 },
 105   { "cbr", 1 },
 106   { "spi", 2 },
 107   { "spu", 3 },
 108   { "bpc", 6 },
 109   { "cr0", 0 },
 110   { "cr1", 1 },
 111   { "cr2", 2 },
 112   { "cr3", 3 },
 113   { "cr4", 4 },
 114   { "cr5", 5 },
 115   { "cr6", 6 }
 116 };
 117
 118 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 119 {  & m32r_cgen_opval_h_cr_entries[0],
 120   12
 121 };
 122
 123
 124 static CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 125 {  { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 126   { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 127   { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 128   { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 129   { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 130   { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 131   { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 132   { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 133   { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 134   { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr },
 135   { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr },
 136   { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 137   { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 138   { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 139   { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 140   { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 141   { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 142   { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 143   { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }
 144 };
 145
 146
 147 const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
 148 {
 149 /* pc: program counter */
 150   { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 151 /* sr: source register */
 152   { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 153 /* dr: destination register */
 154   { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 155 /* src1: source register 1 */
 156   { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 157 /* src2: source register 2 */
 158   { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 159 /* scr: source control register */
 160   { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 161 /* dcr: destination control register */
 162   { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 163 /* simm8: 8 bit signed immediate */
 164   { "simm8", 8, 8, { 0, 0, { 0 } }  },
 165 /* simm16: 16 bit signed immediate */
 166   { "simm16", 16, 16, { 0, 0, { 0 } }  },
 167 /* uimm4: 4 bit trap number */
 168   { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 169 /* uimm5: 5 bit shift count */
 170   { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 171 /* uimm16: 16 bit unsigned immediate */
 172   { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 173 /* hi16: high 16 bit immediate, sign optional */
 174   { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 175 /* slo16: 16 bit signed immediate, for low() */
 176   { "slo16", 16, 16, { 0, 0, { 0 } }  },
 177 /* ulo16: 16 bit unsigned immediate, for low() */
 178   { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 179 /* uimm24: 24 bit address */
 180   { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 181 /* disp8: 8 bit displacement */
 182   { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 183 /* disp16: 16 bit displacement */
 184   { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 185 /* disp24: 24 bit displacement */
 186   { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 187 /* condbit: condition bit */
 188   { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 189 /* accum: accumulator */
 190   { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 191 };
 192
 193 #define OP 1 /* syntax value for mnemonic */
 194
 195 static const CGEN_SYNTAX syntax_table[] =
 196 {/* <op> $dr,$sr */
 197 /*   0 */  { OP, ' ', 130, ',', 129, 0 },
 198 /* <op> $dr,$sr,$slo16 */
 199 /*   1 */  { OP, ' ', 130, ',', 129, ',', 141, 0 },
 200 /* <op> $dr,$sr,$uimm16 */
 201 /*   2 */  { OP, ' ', 130, ',', 129, ',', 139, 0 },
 202 /* <op> $dr,$sr,$ulo16 */
 203 /*   3 */  { OP, ' ', 130, ',', 129, ',', 142, 0 },
 204 /* <op> $dr,$simm8 */
 205 /*   4 */  { OP, ' ', 130, ',', 135, 0 },
 206 /* <op> $dr,$sr,$simm16 */
 207 /*   5 */  { OP, ' ', 130, ',', 129, ',', 136, 0 },
 208 /* <op> $disp8 */
 209 /*   6 */  { OP, ' ', 144, 0 },
 210 /* <op> $disp24 */
 211 /*   7 */  { OP, ' ', 146, 0 },
 212 /* <op> $src1,$src2,$disp16 */
 213 /*   8 */  { OP, ' ', 131, ',', 132, ',', 145, 0 },
 214 /* <op> $src2,$disp16 */
 215 /*   9 */  { OP, ' ', 132, ',', 145, 0 },
 216 /* <op> $src1,$src2 */
 217 /*  10 */  { OP, ' ', 131, ',', 132, 0 },
 218 /* <op> $src2,$simm16 */
 219 /*  11 */  { OP, ' ', 132, ',', 136, 0 },
 220 /* <op> $src2,$uimm16 */
 221 /*  12 */  { OP, ' ', 132, ',', 139, 0 },
 222 /* <op> $sr */
 223 /*  13 */  { OP, ' ', 129, 0 },
 224 /* <op> $dr,@$sr */
 225 /*  14 */  { OP, ' ', 130, ',', '@', 129, 0 },
 226 /* <op> $dr,@($sr) */
 227 /*  15 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
 228 /* <op> $dr,@($slo16,$sr) */
 229 /*  16 */  { OP, ' ', 130, ',', '@', '(', 141, ',', 129, ')', 0 },
 230 /* <op> $dr,@($sr,$slo16) */
 231 /*  17 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 141, ')', 0 },
 232 /* <op> $dr,@$sr+ */
 233 /*  18 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
 234 /* <op> $dr,$uimm24 */
 235 /*  19 */  { OP, ' ', 130, ',', 143, 0 },
 236 /* <op> $dr,$slo16 */
 237 /*  20 */  { OP, ' ', 130, ',', 141, 0 },
 238 /* <op> $dr */
 239 /*  21 */  { OP, ' ', 130, 0 },
 240 /* <op> $dr,$scr */
 241 /*  22 */  { OP, ' ', 130, ',', 133, 0 },
 242 /* <op> $src1 */
 243 /*  23 */  { OP, ' ', 131, 0 },
 244 /* <op> $sr,$dcr */
 245 /*  24 */  { OP, ' ', 129, ',', 134, 0 },
 246 /* <op> */
 247 /*  25 */  { OP, 0 },
 248 /* <op> $dr,$hi16 */
 249 /*  26 */  { OP, ' ', 130, ',', 140, 0 },
 250 /* <op> $dr,$uimm5 */
 251 /*  27 */  { OP, ' ', 130, ',', 138, 0 },
 252 /* <op> $src1,@$src2 */
 253 /*  28 */  { OP, ' ', 131, ',', '@', 132, 0 },
 254 /* <op> $src1,@($src2) */
 255 /*  29 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
 256 /* <op> $src1,@($slo16,$src2) */
 257 /*  30 */  { OP, ' ', 131, ',', '@', '(', 141, ',', 132, ')', 0 },
 258 /* <op> $src1,@($src2,$slo16) */
 259 /*  31 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 141, ')', 0 },
 260 /* <op> $src1,@+$src2 */
 261 /*  32 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
 262 /* <op> $src1,@-$src2 */
 263 /*  33 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
 264 /* <op> $uimm4 */
 265 /*  34 */  { OP, ' ', 137, 0 },
 266 };
 267
 268 #undef OP
 269
 270 static const CGEN_FORMAT format_table[] =
 271 {/* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
 272 /*   0 */  { 16, 16, 0xf0f0 },
 273 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
 274 /*   1 */  { 32, 32, 0xf0f00000 },
 275 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */
 276 /*   2 */  { 32, 32, 0xf0f00000 },
 277 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */
 278 /*   3 */  { 32, 32, 0xf0f00000 },
 279 /* f-op1.number.f-r1.dr.f-simm8.simm8. */
 280 /*   4 */  { 16, 16, 0xf000 },
 281 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */
 282 /*   5 */  { 32, 32, 0xf0f00000 },
 283 /* f-op1.number.f-r1.number.f-disp8.disp8. */
 284 /*   6 */  { 16, 16, 0xff00 },
 285 /* f-op1.number.f-r1.number.f-disp24.disp24. */
 286 /*   7 */  { 32, 32, 0xff000000 },
 287 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */
 288 /*   8 */  { 32, 32, 0xf0f00000 },
 289 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */
 290 /*   9 */  { 32, 32, 0xfff00000 },
 291 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
 292 /*  10 */  { 16, 16, 0xf0f0 },
 293 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */
 294 /*  11 */  { 32, 32, 0xfff00000 },
 295 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
 296 /*  12 */  { 32, 32, 0xfff00000 },
 297 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
 298 /*  13 */  { 32, 32, 0xf0f0ffff },
 299 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
 300 /*  14 */  { 16, 16, 0xfff0 },
 301 /* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
 302 /*  15 */  { 32, 32, 0xf0000000 },
 303 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
 304 /*  16 */  { 32, 32, 0xf0ff0000 },
 305 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
 306 /*  17 */  { 16, 16, 0xf0ff },
 307 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
 308 /*  18 */  { 16, 16, 0xf0f0 },
 309 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
 310 /*  19 */  { 16, 16, 0xf0ff },
 311 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
 312 /*  20 */  { 16, 16, 0xf0f0 },
 313 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
 314 /*  21 */  { 16, 16, 0xffff },
 315 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
 316 /*  22 */  { 32, 32, 0xf0ff0000 },
 317 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
 318 /*  23 */  { 16, 16, 0xf0e0 },
 319 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
 320 /*  24 */  { 32, 32, 0xf0f00000 },
 321 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
 322 /*  25 */  { 16, 16, 0xfff0 },
 323 };
 324
 325 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
 326 #define SYN(n) (& syntax_table[n])
 327 #define FMT(n) (& format_table[n])
 328
 329 const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] =
 330 { /* null first entry, end of all hash chains */
 331   { { 0 }, 0 },
 332 /* add $dr,$sr */
 333   {
 334     { 1, 1, 1, 1 },
 335     "add", "add", SYN (0), FMT (0), 0xa0,
 336     { 0, 0, { 0 } }
 337   },
 338 /* add3 $dr,$sr,$slo16 */
 339   {
 340     { 1, 1, 1, 1 },
 341     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
 342     { 0, 0, { 0 } }
 343   },
 344 /* and $dr,$sr */
 345   {
 346     { 1, 1, 1, 1 },
 347     "and", "and", SYN (0), FMT (0), 0xc0,
 348     { 0, 0, { 0 } }
 349   },
 350 /* and3 $dr,$sr,$uimm16 */
 351   {
 352     { 1, 1, 1, 1 },
 353     "and3", "and3", SYN (2), FMT (2), 0x80c00000,
 354     { 0, 0, { 0 } }
 355   },
 356 /* or $dr,$sr */
 357   {
 358     { 1, 1, 1, 1 },
 359     "or", "or", SYN (0), FMT (0), 0xe0,
 360     { 0, 0, { 0 } }
 361   },
 362 /* or3 $dr,$sr,$ulo16 */
 363   {
 364     { 1, 1, 1, 1 },
 365     "or3", "or3", SYN (3), FMT (3), 0x80e00000,
 366     { 0, 0, { 0 } }
 367   },
 368 /* xor $dr,$sr */
 369   {
 370     { 1, 1, 1, 1 },
 371     "xor", "xor", SYN (0), FMT (0), 0xd0,
 372     { 0, 0, { 0 } }
 373   },
 374 /* xor3 $dr,$sr,$uimm16 */
 375   {
 376     { 1, 1, 1, 1 },
 377     "xor3", "xor3", SYN (2), FMT (2), 0x80d00000,
 378     { 0, 0, { 0 } }
 379   },
 380 /* addi $dr,$simm8 */
 381   {
 382     { 1, 1, 1, 1 },
 383     "addi", "addi", SYN (4), FMT (4), 0x4000,
 384     { 0, 0, { 0 } }
 385   },
 386 /* addv $dr,$sr */
 387   {
 388     { 1, 1, 1, 1 },
 389     "addv", "addv", SYN (0), FMT (0), 0x80,
 390     { 0, 0, { 0 } }
 391   },
 392 /* addv3 $dr,$sr,$simm16 */
 393   {
 394     { 1, 1, 1, 1 },
 395     "addv3", "addv3", SYN (5), FMT (5), 0x80800000,
 396     { 0, 0, { 0 } }
 397   },
 398 /* addx $dr,$sr */
 399   {
 400     { 1, 1, 1, 1 },
 401     "addx", "addx", SYN (0), FMT (0), 0x90,
 402     { 0, 0, { 0 } }
 403   },
 404 /* bc $disp8 */
 405   {
 406     { 1, 1, 1, 1 },
 407     "bc8", "bc", SYN (6), FMT (6), 0x7c00,
 408     { 0, 0|A(RELAX_BC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
 409   },
 410 /* bc.s $disp8 */
 411   {
 412     { 1, 1, 1, 1 },
 413     "bc8.s", "bc.s", SYN (6), FMT (6), 0x7c00,
 414     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 415   },
 416 /* bc $disp24 */
 417   {
 418     { 1, 1, 1, 1 },
 419     "bc24", "bc", SYN (7), FMT (7), 0xfc000000,
 420     { 0, 0|A(RELAX_BC)|A(RELAX)|A(COND_CTI), { 0 } }
 421   },
 422 /* bc.l $disp24 */
 423   {
 424     { 1, 1, 1, 1 },
 425     "bc24.l", "bc.l", SYN (7), FMT (7), 0xfc000000,
 426     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 427   },
 428 /* beq $src1,$src2,$disp16 */
 429   {
 430     { 1, 1, 1, 1 },
 431     "beq", "beq", SYN (8), FMT (8), 0xb0000000,
 432     { 0, 0|A(COND_CTI), { 0 } }
 433   },
 434 /* beqz $src2,$disp16 */
 435   {
 436     { 1, 1, 1, 1 },
 437     "beqz", "beqz", SYN (9), FMT (9), 0xb0800000,
 438     { 0, 0|A(COND_CTI), { 0 } }
 439   },
 440 /* bgez $src2,$disp16 */
 441   {
 442     { 1, 1, 1, 1 },
 443     "bgez", "bgez", SYN (9), FMT (9), 0xb0b00000,
 444     { 0, 0|A(COND_CTI), { 0 } }
 445   },
 446 /* bgtz $src2,$disp16 */
 447   {
 448     { 1, 1, 1, 1 },
 449     "bgtz", "bgtz", SYN (9), FMT (9), 0xb0d00000,
 450     { 0, 0|A(COND_CTI), { 0 } }
 451   },
 452 /* blez $src2,$disp16 */
 453   {
 454     { 1, 1, 1, 1 },
 455     "blez", "blez", SYN (9), FMT (9), 0xb0c00000,
 456     { 0, 0|A(COND_CTI), { 0 } }
 457   },
 458 /* bltz $src2,$disp16 */
 459   {
 460     { 1, 1, 1, 1 },
 461     "bltz", "bltz", SYN (9), FMT (9), 0xb0a00000,
 462     { 0, 0|A(COND_CTI), { 0 } }
 463   },
 464 /* bnez $src2,$disp16 */
 465   {
 466     { 1, 1, 1, 1 },
 467     "bnez", "bnez", SYN (9), FMT (9), 0xb0900000,
 468     { 0, 0|A(COND_CTI), { 0 } }
 469   },
 470 /* bl $disp8 */
 471   {
 472     { 1, 1, 1, 1 },
 473     "bl8", "bl", SYN (6), FMT (6), 0x7e00,
 474     { 0, 0|A(FILL_SLOT)|A(RELAX_BL)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
 475   },
 476 /* bl.s $disp8 */
 477   {
 478     { 1, 1, 1, 1 },
 479     "bl8.s", "bl.s", SYN (6), FMT (6), 0x7e00,
 480     { 0, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 481   },
 482 /* bl $disp24 */
 483   {
 484     { 1, 1, 1, 1 },
 485     "bl24", "bl", SYN (7), FMT (7), 0xfe000000,
 486     { 0, 0|A(RELAX_BL)|A(RELAX)|A(UNCOND_CTI), { 0 } }
 487   },
 488 /* bl.l $disp24 */
 489   {
 490     { 1, 1, 1, 1 },
 491     "bl24.l", "bl.l", SYN (7), FMT (7), 0xfe000000,
 492     { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 493   },
 494 /* bnc $disp8 */
 495   {
 496     { 1, 1, 1, 1 },
 497     "bnc8", "bnc", SYN (6), FMT (6), 0x7d00,
 498     { 0, 0|A(RELAX_BNC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
 499   },
 500 /* bnc.s $disp8 */
 501   {
 502     { 1, 1, 1, 1 },
 503     "bnc8.s", "bnc.s", SYN (6), FMT (6), 0x7d00,
 504     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 505   },
 506 /* bnc $disp24 */
 507   {
 508     { 1, 1, 1, 1 },
 509     "bnc24", "bnc", SYN (7), FMT (7), 0xfd000000,
 510     { 0, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { 0 } }
 511   },
 512 /* bnc.l $disp24 */
 513   {
 514     { 1, 1, 1, 1 },
 515     "bnc24.l", "bnc.l", SYN (7), FMT (7), 0xfd000000,
 516     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 517   },
 518 /* bne $src1,$src2,$disp16 */
 519   {
 520     { 1, 1, 1, 1 },
 521     "bne", "bne", SYN (8), FMT (8), 0xb0100000,
 522     { 0, 0|A(COND_CTI), { 0 } }
 523   },
 524 /* bra $disp8 */
 525   {
 526     { 1, 1, 1, 1 },
 527     "bra8", "bra", SYN (6), FMT (6), 0x7f00,
 528     { 0, 0|A(RELAX_BRA)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
 529   },
 530 /* bra.s $disp8 */
 531   {
 532     { 1, 1, 1, 1 },
 533     "bra8.s", "bra.s", SYN (6), FMT (6), 0x7f00,
 534     { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 535   },
 536 /* bra $disp24 */
 537   {
 538     { 1, 1, 1, 1 },
 539     "bra24", "bra", SYN (7), FMT (7), 0xff000000,
 540     { 0, 0|A(RELAX_BRA)|A(RELAX)|A(UNCOND_CTI), { 0 } }
 541   },
 542 /* bra.l $disp24 */
 543   {
 544     { 1, 1, 1, 1 },
 545     "bra24.l", "bra.l", SYN (7), FMT (7), 0xff000000,
 546     { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 547   },
 548 /* cmp $src1,$src2 */
 549   {
 550     { 1, 1, 1, 1 },
 551     "cmp", "cmp", SYN (10), FMT (10), 0x40,
 552     { 0, 0, { 0 } }
 553   },
 554 /* cmpi $src2,$simm16 */
 555   {
 556     { 1, 1, 1, 1 },
 557     "cmpi", "cmpi", SYN (11), FMT (11), 0x80400000,
 558     { 0, 0, { 0 } }
 559   },
 560 /* cmpu $src1,$src2 */
 561   {
 562     { 1, 1, 1, 1 },
 563     "cmpu", "cmpu", SYN (10), FMT (10), 0x50,
 564     { 0, 0, { 0 } }
 565   },
 566 /* cmpui $src2,$uimm16 */
 567   {
 568     { 1, 1, 1, 1 },
 569     "cmpui", "cmpui", SYN (12), FMT (12), 0x80500000,
 570     { 0, 0, { 0 } }
 571   },
 572 /* div $dr,$sr */
 573   {
 574     { 1, 1, 1, 1 },
 575     "div", "div", SYN (0), FMT (13), 0x90000000,
 576     { 0, 0, { 0 } }
 577   },
 578 /* divu $dr,$sr */
 579   {
 580     { 1, 1, 1, 1 },
 581     "divu", "divu", SYN (0), FMT (13), 0x90100000,
 582     { 0, 0, { 0 } }
 583   },
 584 /* rem $dr,$sr */
 585   {
 586     { 1, 1, 1, 1 },
 587     "rem", "rem", SYN (0), FMT (13), 0x90200000,
 588     { 0, 0, { 0 } }
 589   },
 590 /* remu $dr,$sr */
 591   {
 592     { 1, 1, 1, 1 },
 593     "remu", "remu", SYN (0), FMT (13), 0x90300000,
 594     { 0, 0, { 0 } }
 595   },
 596 /* jl $sr */
 597   {
 598     { 1, 1, 1, 1 },
 599     "jl", "jl", SYN (13), FMT (14), 0x1ec0,
 600     { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
 601   },
 602 /* jmp $sr */
 603   {
 604     { 1, 1, 1, 1 },
 605     "jmp", "jmp", SYN (13), FMT (14), 0x1fc0,
 606     { 0, 0|A(UNCOND_CTI), { 0 } }
 607   },
 608 /* ld $dr,@$sr */
 609   {
 610     { 1, 1, 1, 1 },
 611     "ld", "ld", SYN (14), FMT (0), 0x20c0,
 612     { 0, 0, { 0 } }
 613   },
 614 /* ld $dr,@($sr) */
 615   {
 616     { 1, 1, 1, 1 },
 617     "ld-2", "ld", SYN (15), FMT (0), 0x20c0,
 618     { 0, 0|A(ALIAS), { 0 } }
 619   },
 620 /* ld $dr,@($slo16,$sr) */
 621   {
 622     { 1, 1, 1, 1 },
 623     "ld-d", "ld", SYN (16), FMT (1), 0xa0c00000,
 624     { 0, 0, { 0 } }
 625   },
 626 /* ld $dr,@($sr,$slo16) */
 627   {
 628     { 1, 1, 1, 1 },
 629     "ld-d2", "ld", SYN (17), FMT (1), 0xa0c00000,
 630     { 0, 0|A(ALIAS), { 0 } }
 631   },
 632 /* ldb $dr,@$sr */
 633   {
 634     { 1, 1, 1, 1 },
 635     "ldb", "ldb", SYN (14), FMT (0), 0x2080,
 636     { 0, 0, { 0 } }
 637   },
 638 /* ldb $dr,@($sr) */
 639   {
 640     { 1, 1, 1, 1 },
 641     "ldb-2", "ldb", SYN (15), FMT (0), 0x2080,
 642     { 0, 0|A(ALIAS), { 0 } }
 643   },
 644 /* ldb $dr,@($slo16,$sr) */
 645   {
 646     { 1, 1, 1, 1 },
 647     "ldb-d", "ldb", SYN (16), FMT (1), 0xa0800000,
 648     { 0, 0, { 0 } }
 649   },
 650 /* ldb $dr,@($sr,$slo16) */
 651   {
 652     { 1, 1, 1, 1 },
 653     "ldb-d2", "ldb", SYN (17), FMT (1), 0xa0800000,
 654     { 0, 0|A(ALIAS), { 0 } }
 655   },
 656 /* ldh $dr,@$sr */
 657   {
 658     { 1, 1, 1, 1 },
 659     "ldh", "ldh", SYN (14), FMT (0), 0x20a0,
 660     { 0, 0, { 0 } }
 661   },
 662 /* ldh $dr,@($sr) */
 663   {
 664     { 1, 1, 1, 1 },
 665     "ldh-2", "ldh", SYN (15), FMT (0), 0x20a0,
 666     { 0, 0|A(ALIAS), { 0 } }
 667   },
 668 /* ldh $dr,@($slo16,$sr) */
 669   {
 670     { 1, 1, 1, 1 },
 671     "ldh-d", "ldh", SYN (16), FMT (1), 0xa0a00000,
 672     { 0, 0, { 0 } }
 673   },
 674 /* ldh $dr,@($sr,$slo16) */
 675   {
 676     { 1, 1, 1, 1 },
 677     "ldh-d2", "ldh", SYN (17), FMT (1), 0xa0a00000,
 678     { 0, 0|A(ALIAS), { 0 } }
 679   },
 680 /* ldub $dr,@$sr */
 681   {
 682     { 1, 1, 1, 1 },
 683     "ldub", "ldub", SYN (14), FMT (0), 0x2090,
 684     { 0, 0, { 0 } }
 685   },
 686 /* ldub $dr,@($sr) */
 687   {
 688     { 1, 1, 1, 1 },
 689     "ldub-2", "ldub", SYN (15), FMT (0), 0x2090,
 690     { 0, 0|A(ALIAS), { 0 } }
 691   },
 692 /* ldub $dr,@($slo16,$sr) */
 693   {
 694     { 1, 1, 1, 1 },
 695     "ldub-d", "ldub", SYN (16), FMT (1), 0xa0900000,
 696     { 0, 0, { 0 } }
 697   },
 698 /* ldub $dr,@($sr,$slo16) */
 699   {
 700     { 1, 1, 1, 1 },
 701     "ldub-d2", "ldub", SYN (17), FMT (1), 0xa0900000,
 702     { 0, 0|A(ALIAS), { 0 } }
 703   },
 704 /* lduh $dr,@$sr */
 705   {
 706     { 1, 1, 1, 1 },
 707     "lduh", "lduh", SYN (14), FMT (0), 0x20b0,
 708     { 0, 0, { 0 } }
 709   },
 710 /* lduh $dr,@($sr) */
 711   {
 712     { 1, 1, 1, 1 },
 713     "lduh-2", "lduh", SYN (15), FMT (0), 0x20b0,
 714     { 0, 0|A(ALIAS), { 0 } }
 715   },
 716 /* lduh $dr,@($slo16,$sr) */
 717   {
 718     { 1, 1, 1, 1 },
 719     "lduh-d", "lduh", SYN (16), FMT (1), 0xa0b00000,
 720     { 0, 0, { 0 } }
 721   },
 722 /* lduh $dr,@($sr,$slo16) */
 723   {
 724     { 1, 1, 1, 1 },
 725     "lduh-d2", "lduh", SYN (17), FMT (1), 0xa0b00000,
 726     { 0, 0|A(ALIAS), { 0 } }
 727   },
 728 /* ld $dr,@$sr+ */
 729   {
 730     { 1, 1, 1, 1 },
 731     "ld-plus", "ld", SYN (18), FMT (0), 0x20e0,
 732     { 0, 0, { 0 } }
 733   },
 734 /* ld24 $dr,$uimm24 */
 735   {
 736     { 1, 1, 1, 1 },
 737     "ld24", "ld24", SYN (19), FMT (15), 0xe0000000,
 738     { 0, 0, { 0 } }
 739   },
 740 /* ldi $dr,$simm8 */
 741   {
 742     { 1, 1, 1, 1 },
 743     "ldi8", "ldi", SYN (4), FMT (4), 0x6000,
 744     { 0, 0, { 0 } }
 745   },
 746 /* ldi8 $dr,$simm8 */
 747   {
 748     { 1, 1, 1, 1 },
 749     "ldi8a", "ldi8", SYN (4), FMT (4), 0x6000,
 750     { 0, 0|A(ALIAS), { 0 } }
 751   },
 752 /* ldi $dr,$slo16 */
 753   {
 754     { 1, 1, 1, 1 },
 755     "ldi16", "ldi", SYN (20), FMT (16), 0x90f00000,
 756     { 0, 0, { 0 } }
 757   },
 758 /* ldi16 $dr,$slo16 */
 759   {
 760     { 1, 1, 1, 1 },
 761     "ldi16a", "ldi16", SYN (20), FMT (16), 0x90f00000,
 762     { 0, 0|A(ALIAS), { 0 } }
 763   },
 764 /* lock $dr,@$sr */
 765   {
 766     { 1, 1, 1, 1 },
 767     "lock", "lock", SYN (14), FMT (0), 0x20d0,
 768     { 0, 0, { 0 } }
 769   },
 770 /* machi $src1,$src2 */
 771   {
 772     { 1, 1, 1, 1 },
 773     "machi", "machi", SYN (10), FMT (10), 0x3040,
 774     { 0, 0, { 0 } }
 775   },
 776 /* maclo $src1,$src2 */
 777   {
 778     { 1, 1, 1, 1 },
 779     "maclo", "maclo", SYN (10), FMT (10), 0x3050,
 780     { 0, 0, { 0 } }
 781   },
 782 /* macwhi $src1,$src2 */
 783   {
 784     { 1, 1, 1, 1 },
 785     "macwhi", "macwhi", SYN (10), FMT (10), 0x3060,
 786     { 0, 0, { 0 } }
 787   },
 788 /* macwlo $src1,$src2 */
 789   {
 790     { 1, 1, 1, 1 },
 791     "macwlo", "macwlo", SYN (10), FMT (10), 0x3070,
 792     { 0, 0, { 0 } }
 793   },
 794 /* mul $dr,$sr */
 795   {
 796     { 1, 1, 1, 1 },
 797     "mul", "mul", SYN (0), FMT (0), 0x1060,
 798     { 0, 0, { 0 } }
 799   },
 800 /* mulhi $src1,$src2 */
 801   {
 802     { 1, 1, 1, 1 },
 803     "mulhi", "mulhi", SYN (10), FMT (10), 0x3000,
 804     { 0, 0, { 0 } }
 805   },
 806 /* mullo $src1,$src2 */
 807   {
 808     { 1, 1, 1, 1 },
 809     "mullo", "mullo", SYN (10), FMT (10), 0x3010,
 810     { 0, 0, { 0 } }
 811   },
 812 /* mulwhi $src1,$src2 */
 813   {
 814     { 1, 1, 1, 1 },
 815     "mulwhi", "mulwhi", SYN (10), FMT (10), 0x3020,
 816     { 0, 0, { 0 } }
 817   },
 818 /* mulwlo $src1,$src2 */
 819   {
 820     { 1, 1, 1, 1 },
 821     "mulwlo", "mulwlo", SYN (10), FMT (10), 0x3030,
 822     { 0, 0, { 0 } }
 823   },
 824 /* mv $dr,$sr */
 825   {
 826     { 1, 1, 1, 1 },
 827     "mv", "mv", SYN (0), FMT (0), 0x1080,
 828     { 0, 0, { 0 } }
 829   },
 830 /* mvfachi $dr */
 831   {
 832     { 1, 1, 1, 1 },
 833     "mvfachi", "mvfachi", SYN (21), FMT (17), 0x50f0,
 834     { 0, 0, { 0 } }
 835   },
 836 /* mvfaclo $dr */
 837   {
 838     { 1, 1, 1, 1 },
 839     "mvfaclo", "mvfaclo", SYN (21), FMT (17), 0x50f1,
 840     { 0, 0, { 0 } }
 841   },
 842 /* mvfacmi $dr */
 843   {
 844     { 1, 1, 1, 1 },
 845     "mvfacmi", "mvfacmi", SYN (21), FMT (17), 0x50f2,
 846     { 0, 0, { 0 } }
 847   },
 848 /* mvfc $dr,$scr */
 849   {
 850     { 1, 1, 1, 1 },
 851     "mvfc", "mvfc", SYN (22), FMT (18), 0x1090,
 852     { 0, 0, { 0 } }
 853   },
 854 /* mvtachi $src1 */
 855   {
 856     { 1, 1, 1, 1 },
 857     "mvtachi", "mvtachi", SYN (23), FMT (19), 0x5070,
 858     { 0, 0, { 0 } }
 859   },
 860 /* mvtaclo $src1 */
 861   {
 862     { 1, 1, 1, 1 },
 863     "mvtaclo", "mvtaclo", SYN (23), FMT (19), 0x5071,
 864     { 0, 0, { 0 } }
 865   },
 866 /* mvtc $sr,$dcr */
 867   {
 868     { 1, 1, 1, 1 },
 869     "mvtc", "mvtc", SYN (24), FMT (20), 0x10a0,
 870     { 0, 0, { 0 } }
 871   },
 872 /* neg $dr,$sr */
 873   {
 874     { 1, 1, 1, 1 },
 875     "neg", "neg", SYN (0), FMT (0), 0x30,
 876     { 0, 0, { 0 } }
 877   },
 878 /* nop */
 879   {
 880     { 1, 1, 1, 1 },
 881     "nop", "nop", SYN (25), FMT (21), 0x7000,
 882     { 0, 0, { 0 } }
 883   },
 884 /* not $dr,$sr */
 885   {
 886     { 1, 1, 1, 1 },
 887     "not", "not", SYN (0), FMT (0), 0xb0,
 888     { 0, 0, { 0 } }
 889   },
 890 /* rac */
 891   {
 892     { 1, 1, 1, 1 },
 893     "rac", "rac", SYN (25), FMT (21), 0x5090,
 894     { 0, 0, { 0 } }
 895   },
 896 /* rach */
 897   {
 898     { 1, 1, 1, 1 },
 899     "rach", "rach", SYN (25), FMT (21), 0x5080,
 900     { 0, 0, { 0 } }
 901   },
 902 /* rte */
 903   {
 904     { 1, 1, 1, 1 },
 905     "rte", "rte", SYN (25), FMT (21), 0x10d6,
 906     { 0, 0|A(UNCOND_CTI), { 0 } }
 907   },
 908 /* seth $dr,$hi16 */
 909   {
 910     { 1, 1, 1, 1 },
 911     "seth", "seth", SYN (26), FMT (22), 0xd0c00000,
 912     { 0, 0, { 0 } }
 913   },
 914 /* sll $dr,$sr */
 915   {
 916     { 1, 1, 1, 1 },
 917     "sll", "sll", SYN (0), FMT (0), 0x1040,
 918     { 0, 0, { 0 } }
 919   },
 920 /* sll3 $dr,$sr,$simm16 */
 921   {
 922     { 1, 1, 1, 1 },
 923     "sll3", "sll3", SYN (5), FMT (5), 0x90c00000,
 924     { 0, 0, { 0 } }
 925   },
 926 /* slli $dr,$uimm5 */
 927   {
 928     { 1, 1, 1, 1 },
 929     "slli", "slli", SYN (27), FMT (23), 0x5040,
 930     { 0, 0, { 0 } }
 931   },
 932 /* sra $dr,$sr */
 933   {
 934     { 1, 1, 1, 1 },
 935     "sra", "sra", SYN (0), FMT (0), 0x1020,
 936     { 0, 0, { 0 } }
 937   },
 938 /* sra3 $dr,$sr,$simm16 */
 939   {
 940     { 1, 1, 1, 1 },
 941     "sra3", "sra3", SYN (5), FMT (5), 0x90a00000,
 942     { 0, 0, { 0 } }
 943   },
 944 /* srai $dr,$uimm5 */
 945   {
 946     { 1, 1, 1, 1 },
 947     "srai", "srai", SYN (27), FMT (23), 0x5020,
 948     { 0, 0, { 0 } }
 949   },
 950 /* srl $dr,$sr */
 951   {
 952     { 1, 1, 1, 1 },
 953     "srl", "srl", SYN (0), FMT (0), 0x1000,
 954     { 0, 0, { 0 } }
 955   },
 956 /* srl3 $dr,$sr,$simm16 */
 957   {
 958     { 1, 1, 1, 1 },
 959     "srl3", "srl3", SYN (5), FMT (5), 0x90800000,
 960     { 0, 0, { 0 } }
 961   },
 962 /* srli $dr,$uimm5 */
 963   {
 964     { 1, 1, 1, 1 },
 965     "srli", "srli", SYN (27), FMT (23), 0x5000,
 966     { 0, 0, { 0 } }
 967   },
 968 /* st $src1,@$src2 */
 969   {
 970     { 1, 1, 1, 1 },
 971     "st", "st", SYN (28), FMT (10), 0x2040,
 972     { 0, 0, { 0 } }
 973   },
 974 /* st $src1,@($src2) */
 975   {
 976     { 1, 1, 1, 1 },
 977     "st-2", "st", SYN (29), FMT (10), 0x2040,
 978     { 0, 0|A(ALIAS), { 0 } }
 979   },
 980 /* st $src1,@($slo16,$src2) */
 981   {
 982     { 1, 1, 1, 1 },
 983     "st-d", "st", SYN (30), FMT (24), 0xa0400000,
 984     { 0, 0, { 0 } }
 985   },
 986 /* st $src1,@($src2,$slo16) */
 987   {
 988     { 1, 1, 1, 1 },
 989     "st-d2", "st", SYN (31), FMT (24), 0xa0400000,
 990     { 0, 0|A(ALIAS), { 0 } }
 991   },
 992 /* stb $src1,@$src2 */
 993   {
 994     { 1, 1, 1, 1 },
 995     "stb", "stb", SYN (28), FMT (10), 0x2000,
 996     { 0, 0, { 0 } }
 997   },
 998 /* stb $src1,@($src2) */
 999   {
1000     { 1, 1, 1, 1 },
1001     "stb-2", "stb", SYN (29), FMT (10), 0x2000,
1002     { 0, 0|A(ALIAS), { 0 } }
1003   },
1004 /* stb $src1,@($slo16,$src2) */
1005   {
1006     { 1, 1, 1, 1 },
1007     "stb-d", "stb", SYN (30), FMT (24), 0xa0000000,
1008     { 0, 0, { 0 } }
1009   },
1010 /* stb $src1,@($src2,$slo16) */
1011   {
1012     { 1, 1, 1, 1 },
1013     "stb-d2", "stb", SYN (31), FMT (24), 0xa0000000,
1014     { 0, 0|A(ALIAS), { 0 } }
1015   },
1016 /* sth $src1,@$src2 */
1017   {
1018     { 1, 1, 1, 1 },
1019     "sth", "sth", SYN (28), FMT (10), 0x2020,
1020     { 0, 0, { 0 } }
1021   },
1022 /* sth $src1,@($src2) */
1023   {
1024     { 1, 1, 1, 1 },
1025     "sth-2", "sth", SYN (29), FMT (10), 0x2020,
1026     { 0, 0|A(ALIAS), { 0 } }
1027   },
1028 /* sth $src1,@($slo16,$src2) */
1029   {
1030     { 1, 1, 1, 1 },
1031     "sth-d", "sth", SYN (30), FMT (24), 0xa0200000,
1032     { 0, 0, { 0 } }
1033   },
1034 /* sth $src1,@($src2,$slo16) */
1035   {
1036     { 1, 1, 1, 1 },
1037     "sth-d2", "sth", SYN (31), FMT (24), 0xa0200000,
1038     { 0, 0|A(ALIAS), { 0 } }
1039   },
1040 /* st $src1,@+$src2 */
1041   {
1042     { 1, 1, 1, 1 },
1043     "st-plus", "st", SYN (32), FMT (10), 0x2060,
1044     { 0, 0, { 0 } }
1045   },
1046 /* st $src1,@-$src2 */
1047   {
1048     { 1, 1, 1, 1 },
1049     "st-minus", "st", SYN (33), FMT (10), 0x2070,
1050     { 0, 0, { 0 } }
1051   },
1052 /* sub $dr,$sr */
1053   {
1054     { 1, 1, 1, 1 },
1055     "sub", "sub", SYN (0), FMT (0), 0x20,
1056     { 0, 0, { 0 } }
1057   },
1058 /* subv $dr,$sr */
1059   {
1060     { 1, 1, 1, 1 },
1061     "subv", "subv", SYN (0), FMT (0), 0x0,
1062     { 0, 0, { 0 } }
1063   },
1064 /* subx $dr,$sr */
1065   {
1066     { 1, 1, 1, 1 },
1067     "subx", "subx", SYN (0), FMT (0), 0x10,
1068     { 0, 0, { 0 } }
1069   },
1070 /* trap $uimm4 */
1071   {
1072     { 1, 1, 1, 1 },
1073     "trap", "trap", SYN (34), FMT (25), 0x10f0,
1074     { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
1075   },
1076 /* unlock $src1,@$src2 */
1077   {
1078     { 1, 1, 1, 1 },
1079     "unlock", "unlock", SYN (28), FMT (10), 0x2050,
1080     { 0, 0, { 0 } }
1081   },
1082 /* push $src1 */
1083   {
1084     { 1, 1, 1, 1 },
1085     "push", "push", SYN (23), FMT (19), 0x207f,
1086     { 0, 0|A(ALIAS), { 0 } }
1087   },
1088 /* pop $dr */
1089   {
1090     { 1, 1, 1, 1 },
1091     "pop", "pop", SYN (21), FMT (17), 0x20ef,
1092     { 0, 0|A(ALIAS), { 0 } }
1093   },
1094 };
1095
1096 #undef A
1097 #undef SYN
1098 #undef FMT
1099
1100 CGEN_INSN_TABLE m32r_cgen_insn_table =
1101 {
1102   & m32r_cgen_insn_table_entries[0],
1103   sizeof (CGEN_INSN),
1104   CGEN_NUM_INSNS,
1105   NULL,
1106   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
1107   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
1108 };
1109
1110 /* The hash functions are recorded here to help keep assembler code out of
1111    the disassembler and vice versa.  */
1112
1113 unsigned int
1114 m32r_cgen_asm_hash_insn (insn)
1115      const char * insn;
1116 {
1117   return CGEN_ASM_HASH (insn);
1118 }
1119
1120 unsigned int
1121 m32r_cgen_dis_hash_insn (buf, value)
1122      const char *  buf;
1123      unsigned long value;
1124 {
1125   return CGEN_DIS_HASH (buf, value);
1126 }
1127
1128 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
1129 {  & m32r_cgen_hw_entries[0],
1130   & m32r_cgen_insn_table,
1131 };
1132
1133 void
1134 m32r_cgen_init_tables (mach)
1135     int mach;
1136 {
1137 }
1138
1139 /* Main entry point for stuffing values in cgen_fields.  */
1140
1141 CGEN_INLINE void
1142 m32r_cgen_set_operand (opindex, valuep, fields)
1143      int opindex;
1144      const long *  valuep;
1145      CGEN_FIELDS * fields;
1146 {
1147   switch (opindex)
1148     {
1149     case M32R_OPERAND_SR :
1150       fields->f_r2 = * valuep;
1151       break;
1152     case M32R_OPERAND_DR :
1153       fields->f_r1 = * valuep;
1154       break;
1155     case M32R_OPERAND_SRC1 :
1156       fields->f_r1 = * valuep;
1157       break;
1158     case M32R_OPERAND_SRC2 :
1159       fields->f_r2 = * valuep;
1160       break;
1161     case M32R_OPERAND_SCR :
1162       fields->f_r2 = * valuep;
1163       break;
1164     case M32R_OPERAND_DCR :
1165       fields->f_r1 = * valuep;
1166       break;
1167     case M32R_OPERAND_SIMM8 :
1168       fields->f_simm8 = * valuep;
1169       break;
1170     case M32R_OPERAND_SIMM16 :
1171       fields->f_simm16 = * valuep;
1172       break;
1173     case M32R_OPERAND_UIMM4 :
1174       fields->f_uimm4 = * valuep;
1175       break;
1176     case M32R_OPERAND_UIMM5 :
1177       fields->f_uimm5 = * valuep;
1178       break;
1179     case M32R_OPERAND_UIMM16 :
1180       fields->f_uimm16 = * valuep;
1181       break;
1182     case M32R_OPERAND_HI16 :
1183       fields->f_hi16 = * valuep;
1184       break;
1185     case M32R_OPERAND_SLO16 :
1186       fields->f_simm16 = * valuep;
1187       break;
1188     case M32R_OPERAND_ULO16 :
1189       fields->f_uimm16 = * valuep;
1190       break;
1191     case M32R_OPERAND_UIMM24 :
1192       fields->f_uimm24 = * valuep;
1193       break;
1194     case M32R_OPERAND_DISP8 :
1195       fields->f_disp8 = * valuep;
1196       break;
1197     case M32R_OPERAND_DISP16 :
1198       fields->f_disp16 = * valuep;
1199       break;
1200     case M32R_OPERAND_DISP24 :
1201       fields->f_disp24 = * valuep;
1202       break;
1203
1204     default :
1205       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
1206                        opindex);
1207       abort ();
1208   }
1209 }
1210
1211 /* Main entry point for getting values from cgen_fields.  */
1212
1213 CGEN_INLINE long
1214 m32r_cgen_get_operand (opindex, fields)
1215      int                 opindex;
1216      const CGEN_FIELDS * fields;
1217 {
1218   long value;
1219
1220   switch (opindex)
1221     {
1222     case M32R_OPERAND_SR :
1223       value = fields->f_r2;
1224       break;
1225     case M32R_OPERAND_DR :
1226       value = fields->f_r1;
1227       break;
1228     case M32R_OPERAND_SRC1 :
1229       value = fields->f_r1;
1230       break;
1231     case M32R_OPERAND_SRC2 :
1232       value = fields->f_r2;
1233       break;
1234     case M32R_OPERAND_SCR :
1235       value = fields->f_r2;
1236       break;
1237     case M32R_OPERAND_DCR :
1238       value = fields->f_r1;
1239       break;
1240     case M32R_OPERAND_SIMM8 :
1241       value = fields->f_simm8;
1242       break;
1243     case M32R_OPERAND_SIMM16 :
1244       value = fields->f_simm16;
1245       break;
1246     case M32R_OPERAND_UIMM4 :
1247       value = fields->f_uimm4;
1248       break;
1249     case M32R_OPERAND_UIMM5 :
1250       value = fields->f_uimm5;
1251       break;
1252     case M32R_OPERAND_UIMM16 :
1253       value = fields->f_uimm16;
1254       break;
1255     case M32R_OPERAND_HI16 :
1256       value = fields->f_hi16;
1257       break;
1258     case M32R_OPERAND_SLO16 :
1259       value = fields->f_simm16;
1260       break;
1261     case M32R_OPERAND_ULO16 :
1262       value = fields->f_uimm16;
1263       break;
1264     case M32R_OPERAND_UIMM24 :
1265       value = fields->f_uimm24;
1266       break;
1267     case M32R_OPERAND_DISP8 :
1268       value = fields->f_disp8;
1269       break;
1270     case M32R_OPERAND_DISP16 :
1271       value = fields->f_disp16;
1272       break;
1273     case M32R_OPERAND_DISP24 :
1274       value = fields->f_disp24;
1275       break;
1276
1277     default :
1278       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
1279                        opindex);
1280       abort ();
1281   }
1282
1283   return value;
1284 }
1285