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* cgen-opc.in: New file.
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 This file is used to generate m32r-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "m32r-opc.h"
31
32 /* Look up instruction INSN_VALUE and extract its fields.
33 If non-null INSN is the insn table entry.
34 Otherwise INSN_VALUE is examined to compute it.
35 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
36 The result a pointer to the insn table entry, or NULL if the instruction
37 wasn't recognized. */
38
39 const CGEN_INSN *
40 m32r_cgen_lookup_insn (insn, insn_value, length, fields)
41 const CGEN_INSN *insn;
42 cgen_insn_t insn_value;
43 int length;
44 CGEN_FIELDS *fields;
45 {
46 char buf[4];
47
48 if (!insn)
49 {
50 const CGEN_INSN_LIST *insn_list;
51
52 #ifdef CGEN_INT_INSN
53 switch (length)
54 {
55 case 8:
56 buf[0] = insn_value;
57 break;
58 case 16:
59 if (cgen_current_endian == CGEN_ENDIAN_BIG)
60 bfd_putb16 (insn_value, buf);
61 else
62 bfd_putl16 (insn_value, buf);
63 break;
64 case 32:
65 if (cgen_current_endian == CGEN_ENDIAN_BIG)
66 bfd_putb32 (insn_value, buf);
67 else
68 bfd_putl32 (insn_value, buf);
69 break;
70 default:
71 abort ();
72 }
73 #else
74 abort (); /* FIXME: unfinished */
75 #endif
76
77 /* The instructions are stored in hash lists.
78 Pick the first one and keep trying until we find the right one. */
79
80 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
81 while (insn_list != NULL)
82 {
83 insn = insn_list->insn;
84
85 /* Basic bit mask must be correct. */
86 /* ??? May wish to allow target to defer this check until the extract
87 handler. */
88 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
89 {
90 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
91 if (length > 0)
92 return insn;
93 }
94
95 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
96 }
97 }
98 else
99 {
100 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
101 if (length > 0)
102 return insn;
103 }
104
105 return NULL;
106 }
107
108 /* Fill in the operand instances used by insn INSN_VALUE.
109 If non-null INS is the insn table entry.
110 Otherwise INSN_VALUE is examined to compute it.
111 LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
112 INDICES is a pointer to a buffer of MAX_OPERANDS ints to be filled in.
113 The result a pointer to the insn table entry, or NULL if the instruction
114 wasn't recognized. */
115
116 const CGEN_INSN *
117 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
118 const CGEN_INSN *insn;
119 cgen_insn_t insn_value;
120 int length;
121 int *indices;
122 {
123 CGEN_FIELDS fields;
124 const CGEN_OPERAND_INSTANCE *opinst;
125 int i;
126
127 insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields);
128 if (! insn)
129 return NULL;
130
131 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
132 CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
133 ++i, ++opinst)
134 {
135 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
136 if (op == NULL)
137 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
138 else
139 indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
140 }
141
142 return insn;
143 }
144 /* Attributes. */
145
146 static const CGEN_ATTR_ENTRY MACH_attr[] =
147 {
148 { "m32r", MACH_M32R },
149 /* start-sanitize-m32rx */
150 { "m32rx", MACH_M32RX },
151 /* end-sanitize-m32rx */
152 { "max", MACH_MAX },
153 { 0, 0 }
154 };
155
156 static const CGEN_ATTR_ENTRY WRITE_LR_attr[] =
157 {
158 { "NO", WRITE_LR_NO },
159 { "YES", WRITE_LR_YES },
160 { 0, 0 }
161 };
162
163 static const CGEN_ATTR_ENTRY WRITE_SRC_attr[] =
164 {
165 { "NO", WRITE_SRC_NO },
166 { "YES", WRITE_SRC_YES },
167 { 0, 0 }
168 };
169
170 /* start-sanitize-m32rx */
171 static const CGEN_ATTR_ENTRY PIPE_attr[] =
172 {
173 { "NONE", PIPE_NONE },
174 { "O", PIPE_O },
175 { "S", PIPE_S },
176 { "OS", PIPE_OS },
177 { 0, 0 }
178 };
179
180 /* end-sanitize-m32rx */
181 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
182 {
183 { "ABS-ADDR", NULL },
184 { "FAKE", NULL },
185 { "NEGATIVE", NULL },
186 { "PC", NULL },
187 { "PCREL-ADDR", NULL },
188 { "RELAX", NULL },
189 { "RELOC", NULL },
190 { "SIGN-OPT", NULL },
191 { "UNSIGNED", NULL },
192 { 0, 0 }
193 };
194
195 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
196 {
197 { "MACH", & MACH_attr[0] },
198 /* start-sanitize-m32rx */
199 { "PIPE", & PIPE_attr[0] },
200 /* end-sanitize-m32rx */
201 { "WRITE_LR", & WRITE_LR_attr[0] },
202 { "WRITE_SRC", & WRITE_SRC_attr[0] },
203 { "ALIAS", NULL },
204 { "COND-CTI", NULL },
205 { "FILL-SLOT", NULL },
206 { "PARALLEL", NULL },
207 { "RELAX", NULL },
208 { "RELAXABLE", NULL },
209 { "UNCOND-CTI", NULL },
210 { 0, 0 }
211 };
212
213 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
214 {
215 { "fp", 13 },
216 { "lr", 14 },
217 { "sp", 15 },
218 { "r0", 0 },
219 { "r1", 1 },
220 { "r2", 2 },
221 { "r3", 3 },
222 { "r4", 4 },
223 { "r5", 5 },
224 { "r6", 6 },
225 { "r7", 7 },
226 { "r8", 8 },
227 { "r9", 9 },
228 { "r10", 10 },
229 { "r11", 11 },
230 { "r12", 12 },
231 { "r13", 13 },
232 { "r14", 14 },
233 { "r15", 15 }
234 };
235
236 CGEN_KEYWORD m32r_cgen_opval_h_gr =
237 {
238 & m32r_cgen_opval_h_gr_entries[0],
239 19
240 };
241
242 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
243 {
244 { "psw", 0 },
245 { "cbr", 1 },
246 { "spi", 2 },
247 { "spu", 3 },
248 { "bpc", 6 },
249 { "cr0", 0 },
250 { "cr1", 1 },
251 { "cr2", 2 },
252 { "cr3", 3 },
253 { "cr4", 4 },
254 { "cr5", 5 },
255 { "cr6", 6 }
256 };
257
258 CGEN_KEYWORD m32r_cgen_opval_h_cr =
259 {
260 & m32r_cgen_opval_h_cr_entries[0],
261 12
262 };
263
264 /* start-sanitize-m32rx */
265 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
266 {
267 { "a0", 0 },
268 { "a1", 1 }
269 };
270
271 CGEN_KEYWORD m32r_cgen_opval_h_accums =
272 {
273 & m32r_cgen_opval_h_accums_entries[0],
274 2
275 };
276
277 /* end-sanitize-m32rx */
278
279 /* The hardware table. */
280
281 #define HW_ENT(n) m32r_cgen_hw_entries[n]
282 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
283 {
284 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
285 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
286 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
287 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
288 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
289 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
290 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
291 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
292 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
293 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
294 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
295 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
296 /* start-sanitize-m32rx */
297 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
298 /* end-sanitize-m32rx */
299 /* start-sanitize-m32rx */
300 { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
301 /* end-sanitize-m32rx */
302 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
303 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
304 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
305 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
306 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
307 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
308 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
309 { 0 }
310 };
311
312 /* The operand table. */
313
314 #define OP_ENT(op) m32r_cgen_operand_table[SYMCAT2 (M32R_OPERAND_,op)]
315 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
316 {
317 /* pc: program counter */
318 { "pc", & HW_ENT (HW_H_PC), 0, 0,
319 { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
320 /* sr: source register */
321 { "sr", & HW_ENT (HW_H_GR), 12, 4,
322 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
323 /* dr: destination register */
324 { "dr", & HW_ENT (HW_H_GR), 4, 4,
325 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
326 /* src1: source register 1 */
327 { "src1", & HW_ENT (HW_H_GR), 4, 4,
328 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
329 /* src2: source register 2 */
330 { "src2", & HW_ENT (HW_H_GR), 12, 4,
331 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
332 /* scr: source control register */
333 { "scr", & HW_ENT (HW_H_CR), 12, 4,
334 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
335 /* dcr: destination control register */
336 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
337 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
338 /* simm8: 8 bit signed immediate */
339 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
340 { 0, 0, { 0 } } },
341 /* simm16: 16 bit signed immediate */
342 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
343 { 0, 0, { 0 } } },
344 /* uimm4: 4 bit trap number */
345 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
346 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
347 /* uimm5: 5 bit shift count */
348 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
349 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
350 /* uimm16: 16 bit unsigned immediate */
351 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
352 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
353 /* start-sanitize-m32rx */
354 /* imm1: 1 bit immediate */
355 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
356 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
357 /* end-sanitize-m32rx */
358 /* start-sanitize-m32rx */
359 /* accd: accumulator destination register */
360 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
361 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
362 /* end-sanitize-m32rx */
363 /* start-sanitize-m32rx */
364 /* accs: accumulator source register */
365 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
366 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
367 /* end-sanitize-m32rx */
368 /* start-sanitize-m32rx */
369 /* acc: accumulator reg (d) */
370 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
371 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
372 /* end-sanitize-m32rx */
373 /* hi16: high 16 bit immediate, sign optional */
374 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
375 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
376 /* slo16: 16 bit signed immediate, for low() */
377 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
378 { 0, 0, { 0 } } },
379 /* ulo16: 16 bit unsigned immediate, for low() */
380 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
381 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
382 /* uimm24: 24 bit address */
383 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
384 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
385 /* disp8: 8 bit displacement */
386 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
387 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
388 /* disp16: 16 bit displacement */
389 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
390 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
391 /* disp24: 24 bit displacement */
392 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
393 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
394 /* condbit: condition bit */
395 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
396 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
397 /* accum: accumulator */
398 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
399 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
400 /* start-sanitize-m32rx */
401 /* abort-parallel-execution: abort parallel execution */
402 { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
403 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
404 /* end-sanitize-m32rx */
405 };
406
407 /* Operand references. */
408
409 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
410 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
411 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
412 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
413 { 0 }
414 };
415
416 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
417 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
418 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
419 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
420 { 0 }
421 };
422
423 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
424 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
425 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
426 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
427 { 0 }
428 };
429
430 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
431 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
432 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
433 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
434 { 0 }
435 };
436
437 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
438 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
439 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
440 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
441 { 0 }
442 };
443
444 static const CGEN_OPERAND_INSTANCE fmt_5_addv3_ops[] = {
445 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
446 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
447 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
448 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
449 { 0 }
450 };
451
452 static const CGEN_OPERAND_INSTANCE fmt_6_addx_ops[] = {
453 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
454 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
455 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
456 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
457 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
458 { 0 }
459 };
460
461 static const CGEN_OPERAND_INSTANCE fmt_7_bc8_ops[] = {
462 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
463 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
464 { 0 }
465 };
466
467 static const CGEN_OPERAND_INSTANCE fmt_9_bc24_ops[] = {
468 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
469 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
470 { 0 }
471 };
472
473 static const CGEN_OPERAND_INSTANCE fmt_11_beq_ops[] = {
474 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
475 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
476 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
477 { 0 }
478 };
479
480 static const CGEN_OPERAND_INSTANCE fmt_12_beqz_ops[] = {
481 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
482 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
483 { 0 }
484 };
485
486 static const CGEN_OPERAND_INSTANCE fmt_13_bl8_ops[] = {
487 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
488 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
489 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
490 { 0 }
491 };
492
493 static const CGEN_OPERAND_INSTANCE fmt_14_bl24_ops[] = {
494 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
495 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
496 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
497 { 0 }
498 };
499
500 static const CGEN_OPERAND_INSTANCE fmt_15_bcl8_ops[] = {
501 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
502 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
503 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
504 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
505 { 0 }
506 };
507
508 static const CGEN_OPERAND_INSTANCE fmt_16_bcl24_ops[] = {
509 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
510 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
511 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
512 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
513 { 0 }
514 };
515
516 static const CGEN_OPERAND_INSTANCE fmt_17_bra8_ops[] = {
517 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
518 { 0 }
519 };
520
521 static const CGEN_OPERAND_INSTANCE fmt_18_bra24_ops[] = {
522 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
523 { 0 }
524 };
525
526 static const CGEN_OPERAND_INSTANCE fmt_19_cmp_ops[] = {
527 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
528 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
529 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
530 { 0 }
531 };
532
533 static const CGEN_OPERAND_INSTANCE fmt_20_cmpi_ops[] = {
534 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
535 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
536 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
537 { 0 }
538 };
539
540 static const CGEN_OPERAND_INSTANCE fmt_21_cmpui_ops[] = {
541 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
542 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
543 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
544 { 0 }
545 };
546
547 static const CGEN_OPERAND_INSTANCE fmt_22_cmpz_ops[] = {
548 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
549 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
550 { 0 }
551 };
552
553 static const CGEN_OPERAND_INSTANCE fmt_23_div_ops[] = {
554 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
555 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
556 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
557 { 0 }
558 };
559
560 static const CGEN_OPERAND_INSTANCE fmt_24_jc_ops[] = {
561 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
562 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
563 { 0 }
564 };
565
566 static const CGEN_OPERAND_INSTANCE fmt_25_jl_ops[] = {
567 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
568 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
569 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
570 { 0 }
571 };
572
573 static const CGEN_OPERAND_INSTANCE fmt_26_jmp_ops[] = {
574 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
575 { 0 }
576 };
577
578 static const CGEN_OPERAND_INSTANCE fmt_27_ld_ops[] = {
579 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
580 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
581 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
582 { 0 }
583 };
584
585 static const CGEN_OPERAND_INSTANCE fmt_29_ld_d_ops[] = {
586 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
587 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
588 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
589 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
590 { 0 }
591 };
592
593 static const CGEN_OPERAND_INSTANCE fmt_31_ldb_ops[] = {
594 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
595 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
596 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
597 { 0 }
598 };
599
600 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_d_ops[] = {
601 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
602 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
603 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
604 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
605 { 0 }
606 };
607
608 static const CGEN_OPERAND_INSTANCE fmt_33_ldh_ops[] = {
609 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
610 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
611 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
612 { 0 }
613 };
614
615 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_d_ops[] = {
616 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
617 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
618 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
619 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
620 { 0 }
621 };
622
623 static const CGEN_OPERAND_INSTANCE fmt_35_ld24_ops[] = {
624 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
625 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
626 { 0 }
627 };
628
629 static const CGEN_OPERAND_INSTANCE fmt_36_ldi8_ops[] = {
630 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
631 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
632 { 0 }
633 };
634
635 static const CGEN_OPERAND_INSTANCE fmt_37_ldi16_ops[] = {
636 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
637 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
638 { 0 }
639 };
640
641 static const CGEN_OPERAND_INSTANCE fmt_38_machi_ops[] = {
642 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
643 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
644 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
645 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
646 { 0 }
647 };
648
649 static const CGEN_OPERAND_INSTANCE fmt_39_machi_a_ops[] = {
650 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
651 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
652 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
653 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
654 { 0 }
655 };
656
657 static const CGEN_OPERAND_INSTANCE fmt_40_mulhi_a_ops[] = {
658 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
659 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
660 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
661 { 0 }
662 };
663
664 static const CGEN_OPERAND_INSTANCE fmt_41_mv_ops[] = {
665 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
666 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
667 { 0 }
668 };
669
670 static const CGEN_OPERAND_INSTANCE fmt_42_mvfachi_ops[] = {
671 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
672 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
673 { 0 }
674 };
675
676 static const CGEN_OPERAND_INSTANCE fmt_43_mvfachi_a_ops[] = {
677 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
678 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
679 { 0 }
680 };
681
682 static const CGEN_OPERAND_INSTANCE fmt_44_mvfc_ops[] = {
683 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (SCR), 0 },
684 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
685 { 0 }
686 };
687
688 static const CGEN_OPERAND_INSTANCE fmt_45_mvtachi_ops[] = {
689 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
690 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
691 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
692 { 0 }
693 };
694
695 static const CGEN_OPERAND_INSTANCE fmt_46_mvtachi_a_ops[] = {
696 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
697 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
698 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
699 { 0 }
700 };
701
702 static const CGEN_OPERAND_INSTANCE fmt_47_mvtc_ops[] = {
703 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
704 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, & OP_ENT (DCR), 0 },
705 { 0 }
706 };
707
708 static const CGEN_OPERAND_INSTANCE fmt_49_rac_ops[] = {
709 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
710 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
711 { 0 }
712 };
713
714 static const CGEN_OPERAND_INSTANCE fmt_50_rac_d_ops[] = {
715 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, & OP_ENT (ACCUM), 0 },
716 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
717 { 0 }
718 };
719
720 static const CGEN_OPERAND_INSTANCE fmt_51_rac_ds_ops[] = {
721 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
722 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
723 { 0 }
724 };
725
726 static const CGEN_OPERAND_INSTANCE fmt_52_rac_dsi_ops[] = {
727 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
728 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
729 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
730 { 0 }
731 };
732
733 static const CGEN_OPERAND_INSTANCE fmt_53_rte_ops[] = {
734 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
735 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
736 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
737 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
738 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
739 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, & OP_ENT (PC), 0 },
740 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
741 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
742 { 0 }
743 };
744
745 static const CGEN_OPERAND_INSTANCE fmt_54_seth_ops[] = {
746 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
747 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
748 { 0 }
749 };
750
751 static const CGEN_OPERAND_INSTANCE fmt_55_slli_ops[] = {
752 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
753 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
754 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
755 { 0 }
756 };
757
758 static const CGEN_OPERAND_INSTANCE fmt_57_st_d_ops[] = {
759 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
760 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
761 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
762 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
763 { 0 }
764 };
765
766 static const CGEN_OPERAND_INSTANCE fmt_59_trap_ops[] = {
767 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
768 { 0 }
769 };
770
771 static const CGEN_OPERAND_INSTANCE fmt_62_satb_ops[] = {
772 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
773 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
774 { 0 }
775 };
776
777 static const CGEN_OPERAND_INSTANCE fmt_63_sat_ops[] = {
778 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
779 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
780 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
781 { 0 }
782 };
783
784 static const CGEN_OPERAND_INSTANCE fmt_64_sadd_ops[] = {
785 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
786 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
787 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
788 { 0 }
789 };
790
791 static const CGEN_OPERAND_INSTANCE fmt_65_macwu1_ops[] = {
792 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
793 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
794 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
795 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
796 { 0 }
797 };
798
799 static const CGEN_OPERAND_INSTANCE fmt_66_sc_ops[] = {
800 { CGEN_OPERAND_INSTANCE_INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, & OP_ENT (CONDBIT), 0 },
801 { CGEN_OPERAND_INSTANCE_OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, & OP_ENT (ABORT_PARALLEL_EXECUTION), 0 },
802 { 0 }
803 };
804
805 #define OP 1 /* syntax value for mnemonic */
806
807 static const CGEN_SYNTAX syntax_table[] =
808 {
809 /* <op> $dr,$sr */
810 /* 0 */ { OP, ' ', 130, ',', 129, 0 },
811 /* <op> $dr,$sr,#$slo16 */
812 /* 1 */ { OP, ' ', 130, ',', 129, ',', '#', 145, 0 },
813 /* <op> $dr,$sr,$slo16 */
814 /* 2 */ { OP, ' ', 130, ',', 129, ',', 145, 0 },
815 /* <op> $dr,$sr,#$uimm16 */
816 /* 3 */ { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
817 /* <op> $dr,$sr,$uimm16 */
818 /* 4 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
819 /* <op> $dr,$sr,#$ulo16 */
820 /* 5 */ { OP, ' ', 130, ',', 129, ',', '#', 146, 0 },
821 /* <op> $dr,$sr,$ulo16 */
822 /* 6 */ { OP, ' ', 130, ',', 129, ',', 146, 0 },
823 /* <op> $dr,#$simm8 */
824 /* 7 */ { OP, ' ', 130, ',', '#', 135, 0 },
825 /* <op> $dr,$simm8 */
826 /* 8 */ { OP, ' ', 130, ',', 135, 0 },
827 /* <op> $dr,$sr,#$simm16 */
828 /* 9 */ { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
829 /* <op> $dr,$sr,$simm16 */
830 /* 10 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
831 /* <op> $disp8 */
832 /* 11 */ { OP, ' ', 148, 0 },
833 /* <op> $disp24 */
834 /* 12 */ { OP, ' ', 150, 0 },
835 /* <op> $src1,$src2,$disp16 */
836 /* 13 */ { OP, ' ', 131, ',', 132, ',', 149, 0 },
837 /* <op> $src2,$disp16 */
838 /* 14 */ { OP, ' ', 132, ',', 149, 0 },
839 /* <op> $src1,$src2 */
840 /* 15 */ { OP, ' ', 131, ',', 132, 0 },
841 /* <op> $src2,#$simm16 */
842 /* 16 */ { OP, ' ', 132, ',', '#', 136, 0 },
843 /* <op> $src2,$simm16 */
844 /* 17 */ { OP, ' ', 132, ',', 136, 0 },
845 /* <op> $src2,#$uimm16 */
846 /* 18 */ { OP, ' ', 132, ',', '#', 139, 0 },
847 /* <op> $src2,$uimm16 */
848 /* 19 */ { OP, ' ', 132, ',', 139, 0 },
849 /* <op> $src2 */
850 /* 20 */ { OP, ' ', 132, 0 },
851 /* <op> $sr */
852 /* 21 */ { OP, ' ', 129, 0 },
853 /* <op> $dr,@$sr */
854 /* 22 */ { OP, ' ', 130, ',', '@', 129, 0 },
855 /* <op> $dr,@($sr) */
856 /* 23 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
857 /* <op> $dr,@($slo16,$sr) */
858 /* 24 */ { OP, ' ', 130, ',', '@', '(', 145, ',', 129, ')', 0 },
859 /* <op> $dr,@($sr,$slo16) */
860 /* 25 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 145, ')', 0 },
861 /* <op> $dr,@$sr+ */
862 /* 26 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
863 /* <op> $dr,#$uimm24 */
864 /* 27 */ { OP, ' ', 130, ',', '#', 147, 0 },
865 /* <op> $dr,$uimm24 */
866 /* 28 */ { OP, ' ', 130, ',', 147, 0 },
867 /* <op> $dr,$slo16 */
868 /* 29 */ { OP, ' ', 130, ',', 145, 0 },
869 /* <op> $src1,$src2,$acc */
870 /* 30 */ { OP, ' ', 131, ',', 132, ',', 143, 0 },
871 /* <op> $dr */
872 /* 31 */ { OP, ' ', 130, 0 },
873 /* <op> $dr,$accs */
874 /* 32 */ { OP, ' ', 130, ',', 142, 0 },
875 /* <op> $dr,$scr */
876 /* 33 */ { OP, ' ', 130, ',', 133, 0 },
877 /* <op> $src1 */
878 /* 34 */ { OP, ' ', 131, 0 },
879 /* <op> $src1,$accs */
880 /* 35 */ { OP, ' ', 131, ',', 142, 0 },
881 /* <op> $sr,$dcr */
882 /* 36 */ { OP, ' ', 129, ',', 134, 0 },
883 /* <op> */
884 /* 37 */ { OP, 0 },
885 /* <op> $accd */
886 /* 38 */ { OP, ' ', 141, 0 },
887 /* <op> $accd,$accs */
888 /* 39 */ { OP, ' ', 141, ',', 142, 0 },
889 /* <op> $accd,$accs,#$imm1 */
890 /* 40 */ { OP, ' ', 141, ',', 142, ',', '#', 140, 0 },
891 /* <op> $dr,#$hi16 */
892 /* 41 */ { OP, ' ', 130, ',', '#', 144, 0 },
893 /* <op> $dr,$hi16 */
894 /* 42 */ { OP, ' ', 130, ',', 144, 0 },
895 /* <op> $dr,#$uimm5 */
896 /* 43 */ { OP, ' ', 130, ',', '#', 138, 0 },
897 /* <op> $dr,$uimm5 */
898 /* 44 */ { OP, ' ', 130, ',', 138, 0 },
899 /* <op> $src1,@$src2 */
900 /* 45 */ { OP, ' ', 131, ',', '@', 132, 0 },
901 /* <op> $src1,@($src2) */
902 /* 46 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
903 /* <op> $src1,@($slo16,$src2) */
904 /* 47 */ { OP, ' ', 131, ',', '@', '(', 145, ',', 132, ')', 0 },
905 /* <op> $src1,@($src2,$slo16) */
906 /* 48 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 145, ')', 0 },
907 /* <op> $src1,@+$src2 */
908 /* 49 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
909 /* <op> $src1,@-$src2 */
910 /* 50 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
911 /* <op> #$uimm4 */
912 /* 51 */ { OP, ' ', '#', 137, 0 },
913 /* <op> $uimm4 */
914 /* 52 */ { OP, ' ', 137, 0 },
915 /* <op> $dr,$src2 */
916 /* 53 */ { OP, ' ', 130, ',', 132, 0 },
917 };
918
919 #undef OP
920
921 static const CGEN_FORMAT format_table[] =
922 {
923 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.dr.SI.sr.SI. */
924 /* 0 */ { 16, 16, 0xf0f0 },
925 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.slo16.HI.sr.SI. */
926 /* 1 */ { 32, 32, 0xf0f00000 },
927 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16.sr.SI.uimm16.USI. */
928 /* 2 */ { 32, 32, 0xf0f00000 },
929 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16.sr.SI.ulo16.UHI. */
930 /* 3 */ { 32, 32, 0xf0f00000 },
931 /* f-op1.number.f-r1.dr.f-simm8.simm8.dr.SI.simm8.SI. */
932 /* 4 */ { 16, 16, 0xf000 },
933 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16.simm16.SI.sr.SI. */
934 /* 5 */ { 32, 32, 0xf0f00000 },
935 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.condbit.UBI.dr.SI.sr.SI. */
936 /* 6 */ { 16, 16, 0xf0f0 },
937 /* f-op1.number.f-r1.number.f-disp8.disp8.condbit.UBI.disp8.VM. */
938 /* 7 */ { 16, 16, 0xff00 },
939 /* f-op1.number.f-r1.number.f-disp8.disp8. */
940 /* 8 */ { 16, 16, 0xff00 },
941 /* f-op1.number.f-r1.number.f-disp24.disp24.condbit.UBI.disp24.VM. */
942 /* 9 */ { 32, 32, 0xff000000 },
943 /* f-op1.number.f-r1.number.f-disp24.disp24. */
944 /* 10 */ { 32, 32, 0xff000000 },
945 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16.disp16.VM.src1.SI.src2.SI. */
946 /* 11 */ { 32, 32, 0xf0f00000 },
947 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16.disp16.VM.src2.SI. */
948 /* 12 */ { 32, 32, 0xfff00000 },
949 /* f-op1.number.f-r1.number.f-disp8.disp8.disp8.VM.pc.USI. */
950 /* 13 */ { 16, 16, 0xff00 },
951 /* f-op1.number.f-r1.number.f-disp24.disp24.disp24.VM.pc.USI. */
952 /* 14 */ { 32, 32, 0xff000000 },
953 /* f-op1.number.f-r1.number.f-disp8.disp8.condbit.UBI.disp8.VM.pc.USI. */
954 /* 15 */ { 16, 16, 0xff00 },
955 /* f-op1.number.f-r1.number.f-disp24.disp24.condbit.UBI.disp24.VM.pc.USI. */
956 /* 16 */ { 32, 32, 0xff000000 },
957 /* f-op1.number.f-r1.number.f-disp8.disp8.disp8.VM. */
958 /* 17 */ { 16, 16, 0xff00 },
959 /* f-op1.number.f-r1.number.f-disp24.disp24.disp24.VM. */
960 /* 18 */ { 32, 32, 0xff000000 },
961 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.src1.SI.src2.SI. */
962 /* 19 */ { 16, 16, 0xf0f0 },
963 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16.simm16.SI.src2.SI. */
964 /* 20 */ { 32, 32, 0xfff00000 },
965 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16.src2.SI.uimm16.USI. */
966 /* 21 */ { 32, 32, 0xfff00000 },
967 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.src2.SI. */
968 /* 22 */ { 16, 16, 0xfff0 },
969 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number.dr.SI.sr.SI. */
970 /* 23 */ { 32, 32, 0xf0f0ffff },
971 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.condbit.UBI.sr.SI. */
972 /* 24 */ { 16, 16, 0xfff0 },
973 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.pc.USI.sr.SI. */
974 /* 25 */ { 16, 16, 0xfff0 },
975 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr.sr.SI. */
976 /* 26 */ { 16, 16, 0xfff0 },
977 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.SI.sr.SI. */
978 /* 27 */ { 16, 16, 0xf0f0 },
979 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
980 /* 28 */ { 16, 16, 0xf0f0 },
981 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.SI.slo16.HI.sr.SI. */
982 /* 29 */ { 32, 32, 0xf0f00000 },
983 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
984 /* 30 */ { 32, 32, 0xf0f00000 },
985 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.QI.sr.SI. */
986 /* 31 */ { 16, 16, 0xf0f0 },
987 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.QI.slo16.HI.sr.SI. */
988 /* 32 */ { 32, 32, 0xf0f00000 },
989 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.h-memory-sr.HI.sr.SI. */
990 /* 33 */ { 16, 16, 0xf0f0 },
991 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16.h-memory-add-WI-sr-slo16.HI.slo16.HI.sr.SI. */
992 /* 34 */ { 32, 32, 0xf0f00000 },
993 /* f-op1.number.f-r1.dr.f-uimm24.uimm24.uimm24.VM. */
994 /* 35 */ { 32, 32, 0xf0000000 },
995 /* f-op1.number.f-r1.dr.f-simm8.simm8.simm8.SI. */
996 /* 36 */ { 16, 16, 0xf000 },
997 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16.slo16.HI. */
998 /* 37 */ { 32, 32, 0xf0ff0000 },
999 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.accum.DI.src1.SI.src2.SI. */
1000 /* 38 */ { 16, 16, 0xf0f0 },
1001 /* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2.acc.DI.src1.SI.src2.SI. */
1002 /* 39 */ { 16, 16, 0xf070 },
1003 /* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2.src1.SI.src2.SI. */
1004 /* 40 */ { 16, 16, 0xf070 },
1005 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.sr.SI. */
1006 /* 41 */ { 16, 16, 0xf0f0 },
1007 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.accum.DI. */
1008 /* 42 */ { 16, 16, 0xf0ff },
1009 /* f-op1.number.f-r1.dr.f-op2.number.f-accs.accs.f-op3.number.accs.DI. */
1010 /* 43 */ { 16, 16, 0xf0f3 },
1011 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr.scr.SI. */
1012 /* 44 */ { 16, 16, 0xf0f0 },
1013 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number.accum.DI.src1.SI. */
1014 /* 45 */ { 16, 16, 0xf0ff },
1015 /* f-op1.number.f-r1.src1.f-op2.number.f-accs.accs.f-op3.number.accs.DI.src1.SI. */
1016 /* 46 */ { 16, 16, 0xf0f3 },
1017 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr.sr.SI. */
1018 /* 47 */ { 16, 16, 0xf0f0 },
1019 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
1020 /* 48 */ { 16, 16, 0xffff },
1021 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.accum.DI. */
1022 /* 49 */ { 16, 16, 0xffff },
1023 /* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.number.f-bit14.number.f-imm1.number.accum.DI. */
1024 /* 50 */ { 16, 16, 0xf3ff },
1025 /* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.accs.f-bit14.number.f-imm1.number.accs.DI. */
1026 /* 51 */ { 16, 16, 0xf3f3 },
1027 /* f-op1.number.f-accd.accd.f-bits67.number.f-op2.number.f-accs.accs.f-bit14.number.f-imm1.imm1.accs.DI.imm1.USI. */
1028 /* 52 */ { 16, 16, 0xf3f2 },
1029 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.h-bcond-0.VM.h-bie-0.VM.h-bpc-0.VM.h-bsm-0.VM. */
1030 /* 53 */ { 16, 16, 0xffff },
1031 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16.hi16.UHI. */
1032 /* 54 */ { 32, 32, 0xf0ff0000 },
1033 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5.dr.SI.uimm5.USI. */
1034 /* 55 */ { 16, 16, 0xf0e0 },
1035 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
1036 /* 56 */ { 16, 16, 0xf0f0 },
1037 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16.slo16.HI.src1.SI.src2.SI. */
1038 /* 57 */ { 32, 32, 0xf0f00000 },
1039 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
1040 /* 58 */ { 32, 32, 0xf0f00000 },
1041 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4.uimm4.USI. */
1042 /* 59 */ { 16, 16, 0xfff0 },
1043 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
1044 /* 60 */ { 16, 16, 0xf0ff },
1045 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
1046 /* 61 */ { 16, 16, 0xf0ff },
1047 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number.src2.SI. */
1048 /* 62 */ { 32, 32, 0xf0f0ffff },
1049 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number.condbit.UBI.src2.SI. */
1050 /* 63 */ { 32, 32, 0xf0f0ffff },
1051 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.h-accums-0.DI.h-accums-1.DI. */
1052 /* 64 */ { 16, 16, 0xffff },
1053 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.h-accums-1.DI.src1.SI.src2.SI. */
1054 /* 65 */ { 16, 16, 0xf0f0 },
1055 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number.condbit.UBI. */
1056 /* 66 */ { 16, 16, 0xffff },
1057 };
1058
1059 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
1060 #define SYN(n) (& syntax_table[n])
1061 #define FMT(n) (& format_table[n])
1062
1063 /* The instruction table. */
1064
1065 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1066 {
1067 /* null first entry, end of all hash chains */
1068 { { 0 }, 0 },
1069 /* add $dr,$sr */
1070 {
1071 { 1, 1, 1, 1 },
1072 "add", "add", SYN (0), FMT (0), 0xa0,
1073 & fmt_0_add_ops[0],
1074 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1075 },
1076 /* add3 $dr,$sr,#$slo16 */
1077 {
1078 { 1, 1, 1, 1 },
1079 "add3", "add3", SYN (1), FMT (1), 0x80a00000,
1080 & fmt_1_add3_ops[0],
1081 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1082 },
1083 /* add3 $dr,$sr,$slo16 */
1084 {
1085 { 1, 1, 1, 1 },
1086 "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
1087 & fmt_1_add3_ops[0],
1088 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1089 },
1090 /* and $dr,$sr */
1091 {
1092 { 1, 1, 1, 1 },
1093 "and", "and", SYN (0), FMT (0), 0xc0,
1094 & fmt_0_add_ops[0],
1095 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1096 },
1097 /* and3 $dr,$sr,#$uimm16 */
1098 {
1099 { 1, 1, 1, 1 },
1100 "and3", "and3", SYN (3), FMT (2), 0x80c00000,
1101 & fmt_2_and3_ops[0],
1102 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1103 },
1104 /* and3 $dr,$sr,$uimm16 */
1105 {
1106 { 1, 1, 1, 1 },
1107 "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
1108 & fmt_2_and3_ops[0],
1109 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1110 },
1111 /* or $dr,$sr */
1112 {
1113 { 1, 1, 1, 1 },
1114 "or", "or", SYN (0), FMT (0), 0xe0,
1115 & fmt_0_add_ops[0],
1116 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1117 },
1118 /* or3 $dr,$sr,#$ulo16 */
1119 {
1120 { 1, 1, 1, 1 },
1121 "or3", "or3", SYN (5), FMT (3), 0x80e00000,
1122 & fmt_3_or3_ops[0],
1123 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1124 },
1125 /* or3 $dr,$sr,$ulo16 */
1126 {
1127 { 1, 1, 1, 1 },
1128 "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
1129 & fmt_3_or3_ops[0],
1130 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1131 },
1132 /* xor $dr,$sr */
1133 {
1134 { 1, 1, 1, 1 },
1135 "xor", "xor", SYN (0), FMT (0), 0xd0,
1136 & fmt_0_add_ops[0],
1137 { 4, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1138 },
1139 /* xor3 $dr,$sr,#$uimm16 */
1140 {
1141 { 1, 1, 1, 1 },
1142 "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
1143 & fmt_2_and3_ops[0],
1144 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1145 },
1146 /* xor3 $dr,$sr,$uimm16 */
1147 {
1148 { 1, 1, 1, 1 },
1149 "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
1150 & fmt_2_and3_ops[0],
1151 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1152 },
1153 /* addi $dr,#$simm8 */
1154 {
1155 { 1, 1, 1, 1 },
1156 "addi", "addi", SYN (7), FMT (4), 0x4000,
1157 & fmt_4_addi_ops[0],
1158 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1159 },
1160 /* addi $dr,$simm8 */
1161 {
1162 { 1, 1, 1, 1 },
1163 "addi.a", "addi", SYN (8), FMT (4), 0x4000,
1164 & fmt_4_addi_ops[0],
1165 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1166 },
1167 /* addv $dr,$sr */
1168 {
1169 { 1, 1, 1, 1 },
1170 "addv", "addv", SYN (0), FMT (0), 0x80,
1171 & fmt_0_add_ops[0],
1172 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1173 },
1174 /* addv3 $dr,$sr,#$simm16 */
1175 {
1176 { 1, 1, 1, 1 },
1177 "addv3", "addv3", SYN (9), FMT (5), 0x80800000,
1178 & fmt_5_addv3_ops[0],
1179 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1180 },
1181 /* addv3 $dr,$sr,$simm16 */
1182 {
1183 { 1, 1, 1, 1 },
1184 "addv3.a", "addv3", SYN (10), FMT (5), 0x80800000,
1185 & fmt_5_addv3_ops[0],
1186 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1187 },
1188 /* addx $dr,$sr */
1189 {
1190 { 1, 1, 1, 1 },
1191 "addx", "addx", SYN (0), FMT (6), 0x90,
1192 & fmt_6_addx_ops[0],
1193 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1194 },
1195 /* bc $disp8 */
1196 {
1197 { 1, 1, 1, 1 },
1198 "bc8", "bc", SYN (11), FMT (7), 0x7c00,
1199 & fmt_7_bc8_ops[0],
1200 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1201 },
1202 /* bc.s $disp8 */
1203 {
1204 { 1, 1, 1, 1 },
1205 "bc8.s", "bc.s", SYN (11), FMT (8), 0x7c00,
1206 0,
1207 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1208 },
1209 /* bc $disp24 */
1210 {
1211 { 1, 1, 1, 1 },
1212 "bc24", "bc", SYN (12), FMT (9), 0xfc000000,
1213 & fmt_9_bc24_ops[0],
1214 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1215 },
1216 /* bc.l $disp24 */
1217 {
1218 { 1, 1, 1, 1 },
1219 "bc24.l", "bc.l", SYN (12), FMT (10), 0xfc000000,
1220 0,
1221 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1222 },
1223 /* beq $src1,$src2,$disp16 */
1224 {
1225 { 1, 1, 1, 1 },
1226 "beq", "beq", SYN (13), FMT (11), 0xb0000000,
1227 & fmt_11_beq_ops[0],
1228 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1229 },
1230 /* beqz $src2,$disp16 */
1231 {
1232 { 1, 1, 1, 1 },
1233 "beqz", "beqz", SYN (14), FMT (12), 0xb0800000,
1234 & fmt_12_beqz_ops[0],
1235 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1236 },
1237 /* bgez $src2,$disp16 */
1238 {
1239 { 1, 1, 1, 1 },
1240 "bgez", "bgez", SYN (14), FMT (12), 0xb0b00000,
1241 & fmt_12_beqz_ops[0],
1242 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1243 },
1244 /* bgtz $src2,$disp16 */
1245 {
1246 { 1, 1, 1, 1 },
1247 "bgtz", "bgtz", SYN (14), FMT (12), 0xb0d00000,
1248 & fmt_12_beqz_ops[0],
1249 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1250 },
1251 /* blez $src2,$disp16 */
1252 {
1253 { 1, 1, 1, 1 },
1254 "blez", "blez", SYN (14), FMT (12), 0xb0c00000,
1255 & fmt_12_beqz_ops[0],
1256 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1257 },
1258 /* bltz $src2,$disp16 */
1259 {
1260 { 1, 1, 1, 1 },
1261 "bltz", "bltz", SYN (14), FMT (12), 0xb0a00000,
1262 & fmt_12_beqz_ops[0],
1263 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1264 },
1265 /* bnez $src2,$disp16 */
1266 {
1267 { 1, 1, 1, 1 },
1268 "bnez", "bnez", SYN (14), FMT (12), 0xb0900000,
1269 & fmt_12_beqz_ops[0],
1270 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1271 },
1272 /* bl $disp8 */
1273 {
1274 { 1, 1, 1, 1 },
1275 "bl8", "bl", SYN (11), FMT (13), 0x7e00,
1276 & fmt_13_bl8_ops[0],
1277 { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1278 },
1279 /* bl.s $disp8 */
1280 {
1281 { 1, 1, 1, 1 },
1282 "bl8.s", "bl.s", SYN (11), FMT (8), 0x7e00,
1283 0,
1284 { 4, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1285 },
1286 /* bl $disp24 */
1287 {
1288 { 1, 1, 1, 1 },
1289 "bl24", "bl", SYN (12), FMT (14), 0xfe000000,
1290 & fmt_14_bl24_ops[0],
1291 { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1292 },
1293 /* bl.l $disp24 */
1294 {
1295 { 1, 1, 1, 1 },
1296 "bl24.l", "bl.l", SYN (12), FMT (10), 0xfe000000,
1297 0,
1298 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1299 },
1300 /* start-sanitize-m32rx */
1301 /* bcl $disp8 */
1302 {
1303 { 1, 1, 1, 1 },
1304 "bcl8", "bcl", SYN (11), FMT (15), 0x7800,
1305 & fmt_15_bcl8_ops[0],
1306 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1307 },
1308 /* end-sanitize-m32rx */
1309 /* start-sanitize-m32rx */
1310 /* bcl.s $disp8 */
1311 {
1312 { 1, 1, 1, 1 },
1313 "bcl8.s", "bcl.s", SYN (11), FMT (8), 0x7800,
1314 0,
1315 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1316 },
1317 /* end-sanitize-m32rx */
1318 /* start-sanitize-m32rx */
1319 /* bcl $disp24 */
1320 {
1321 { 1, 1, 1, 1 },
1322 "bcl24", "bcl", SYN (12), FMT (16), 0xf8000000,
1323 & fmt_16_bcl24_ops[0],
1324 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1325 },
1326 /* end-sanitize-m32rx */
1327 /* start-sanitize-m32rx */
1328 /* bcl.l $disp24 */
1329 {
1330 { 1, 1, 1, 1 },
1331 "bcl24.l", "bcl.l", SYN (12), FMT (10), 0xf8000000,
1332 0,
1333 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1334 },
1335 /* end-sanitize-m32rx */
1336 /* bnc $disp8 */
1337 {
1338 { 1, 1, 1, 1 },
1339 "bnc8", "bnc", SYN (11), FMT (7), 0x7d00,
1340 & fmt_7_bc8_ops[0],
1341 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1342 },
1343 /* bnc.s $disp8 */
1344 {
1345 { 1, 1, 1, 1 },
1346 "bnc8.s", "bnc.s", SYN (11), FMT (8), 0x7d00,
1347 0,
1348 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1349 },
1350 /* bnc $disp24 */
1351 {
1352 { 1, 1, 1, 1 },
1353 "bnc24", "bnc", SYN (12), FMT (9), 0xfd000000,
1354 & fmt_9_bc24_ops[0],
1355 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1356 },
1357 /* bnc.l $disp24 */
1358 {
1359 { 1, 1, 1, 1 },
1360 "bnc24.l", "bnc.l", SYN (12), FMT (10), 0xfd000000,
1361 0,
1362 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1363 },
1364 /* bne $src1,$src2,$disp16 */
1365 {
1366 { 1, 1, 1, 1 },
1367 "bne", "bne", SYN (13), FMT (11), 0xb0100000,
1368 & fmt_11_beq_ops[0],
1369 { 4, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1370 },
1371 /* bra $disp8 */
1372 {
1373 { 1, 1, 1, 1 },
1374 "bra8", "bra", SYN (11), FMT (17), 0x7f00,
1375 & fmt_17_bra8_ops[0],
1376 { 4, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1377 },
1378 /* bra.s $disp8 */
1379 {
1380 { 1, 1, 1, 1 },
1381 "bra8.s", "bra.s", SYN (11), FMT (8), 0x7f00,
1382 0,
1383 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1384 },
1385 /* bra $disp24 */
1386 {
1387 { 1, 1, 1, 1 },
1388 "bra24", "bra", SYN (12), FMT (18), 0xff000000,
1389 & fmt_18_bra24_ops[0],
1390 { 4, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1391 },
1392 /* bra.l $disp24 */
1393 {
1394 { 1, 1, 1, 1 },
1395 "bra24.l", "bra.l", SYN (12), FMT (10), 0xff000000,
1396 0,
1397 { 4, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1398 },
1399 /* start-sanitize-m32rx */
1400 /* bncl $disp8 */
1401 {
1402 { 1, 1, 1, 1 },
1403 "bncl8", "bncl", SYN (11), FMT (15), 0x7900,
1404 & fmt_15_bcl8_ops[0],
1405 { 4, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1406 },
1407 /* end-sanitize-m32rx */
1408 /* start-sanitize-m32rx */
1409 /* bncl.s $disp8 */
1410 {
1411 { 1, 1, 1, 1 },
1412 "bncl8.s", "bncl.s", SYN (11), FMT (8), 0x7900,
1413 0,
1414 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1415 },
1416 /* end-sanitize-m32rx */
1417 /* start-sanitize-m32rx */
1418 /* bncl $disp24 */
1419 {
1420 { 1, 1, 1, 1 },
1421 "bncl24", "bncl", SYN (12), FMT (16), 0xf9000000,
1422 & fmt_16_bcl24_ops[0],
1423 { 4, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1424 },
1425 /* end-sanitize-m32rx */
1426 /* start-sanitize-m32rx */
1427 /* bncl.l $disp24 */
1428 {
1429 { 1, 1, 1, 1 },
1430 "bncl24.l", "bncl.l", SYN (12), FMT (10), 0xf9000000,
1431 0,
1432 { 4, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_YES, WRITE_SRC_NO } }
1433 },
1434 /* end-sanitize-m32rx */
1435 /* cmp $src1,$src2 */
1436 {
1437 { 1, 1, 1, 1 },
1438 "cmp", "cmp", SYN (15), FMT (19), 0x40,
1439 & fmt_19_cmp_ops[0],
1440 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1441 },
1442 /* cmpi $src2,#$simm16 */
1443 {
1444 { 1, 1, 1, 1 },
1445 "cmpi", "cmpi", SYN (16), FMT (20), 0x80400000,
1446 & fmt_20_cmpi_ops[0],
1447 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1448 },
1449 /* cmpi $src2,$simm16 */
1450 {
1451 { 1, 1, 1, 1 },
1452 "cmpi.a", "cmpi", SYN (17), FMT (20), 0x80400000,
1453 & fmt_20_cmpi_ops[0],
1454 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1455 },
1456 /* cmpu $src1,$src2 */
1457 {
1458 { 1, 1, 1, 1 },
1459 "cmpu", "cmpu", SYN (15), FMT (19), 0x50,
1460 & fmt_19_cmp_ops[0],
1461 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1462 },
1463 /* cmpui $src2,#$uimm16 */
1464 {
1465 { 1, 1, 1, 1 },
1466 "cmpui", "cmpui", SYN (18), FMT (21), 0x80500000,
1467 & fmt_21_cmpui_ops[0],
1468 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1469 },
1470 /* cmpui $src2,$uimm16 */
1471 {
1472 { 1, 1, 1, 1 },
1473 "cmpui.a", "cmpui", SYN (19), FMT (21), 0x80500000,
1474 & fmt_21_cmpui_ops[0],
1475 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1476 },
1477 /* start-sanitize-m32rx */
1478 /* cmpeq $src1,$src2 */
1479 {
1480 { 1, 1, 1, 1 },
1481 "cmpeq", "cmpeq", SYN (15), FMT (19), 0x60,
1482 & fmt_19_cmp_ops[0],
1483 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1484 },
1485 /* end-sanitize-m32rx */
1486 /* start-sanitize-m32rx */
1487 /* cmpz $src2 */
1488 {
1489 { 1, 1, 1, 1 },
1490 "cmpz", "cmpz", SYN (20), FMT (22), 0x70,
1491 & fmt_22_cmpz_ops[0],
1492 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1493 },
1494 /* end-sanitize-m32rx */
1495 /* div $dr,$sr */
1496 {
1497 { 1, 1, 1, 1 },
1498 "div", "div", SYN (0), FMT (23), 0x90000000,
1499 & fmt_23_div_ops[0],
1500 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1501 },
1502 /* divu $dr,$sr */
1503 {
1504 { 1, 1, 1, 1 },
1505 "divu", "divu", SYN (0), FMT (23), 0x90100000,
1506 & fmt_23_div_ops[0],
1507 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1508 },
1509 /* rem $dr,$sr */
1510 {
1511 { 1, 1, 1, 1 },
1512 "rem", "rem", SYN (0), FMT (23), 0x90200000,
1513 & fmt_23_div_ops[0],
1514 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1515 },
1516 /* remu $dr,$sr */
1517 {
1518 { 1, 1, 1, 1 },
1519 "remu", "remu", SYN (0), FMT (23), 0x90300000,
1520 & fmt_23_div_ops[0],
1521 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1522 },
1523 /* start-sanitize-m32rx */
1524 /* divh $dr,$sr */
1525 {
1526 { 1, 1, 1, 1 },
1527 "divh", "divh", SYN (0), FMT (23), 0x90000010,
1528 & fmt_23_div_ops[0],
1529 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1530 },
1531 /* end-sanitize-m32rx */
1532 /* start-sanitize-m32rx */
1533 /* jc $sr */
1534 {
1535 { 1, 1, 1, 1 },
1536 "jc", "jc", SYN (21), FMT (24), 0x1cc0,
1537 & fmt_24_jc_ops[0],
1538 { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1539 },
1540 /* end-sanitize-m32rx */
1541 /* start-sanitize-m32rx */
1542 /* jnc $sr */
1543 {
1544 { 1, 1, 1, 1 },
1545 "jnc", "jnc", SYN (21), FMT (24), 0x1dc0,
1546 & fmt_24_jc_ops[0],
1547 { 4, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1548 },
1549 /* end-sanitize-m32rx */
1550 /* jl $sr */
1551 {
1552 { 1, 1, 1, 1 },
1553 "jl", "jl", SYN (21), FMT (25), 0x1ec0,
1554 & fmt_25_jl_ops[0],
1555 { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_YES, WRITE_SRC_NO } }
1556 },
1557 /* jmp $sr */
1558 {
1559 { 1, 1, 1, 1 },
1560 "jmp", "jmp", SYN (21), FMT (26), 0x1fc0,
1561 & fmt_26_jmp_ops[0],
1562 { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1563 },
1564 /* ld $dr,@$sr */
1565 {
1566 { 1, 1, 1, 1 },
1567 "ld", "ld", SYN (22), FMT (27), 0x20c0,
1568 & fmt_27_ld_ops[0],
1569 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1570 },
1571 /* ld $dr,@($sr) */
1572 {
1573 { 1, 1, 1, 1 },
1574 "ld-2", "ld", SYN (23), FMT (28), 0x20c0,
1575 0,
1576 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1577 },
1578 /* ld $dr,@($slo16,$sr) */
1579 {
1580 { 1, 1, 1, 1 },
1581 "ld-d", "ld", SYN (24), FMT (29), 0xa0c00000,
1582 & fmt_29_ld_d_ops[0],
1583 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1584 },
1585 /* ld $dr,@($sr,$slo16) */
1586 {
1587 { 1, 1, 1, 1 },
1588 "ld-d2", "ld", SYN (25), FMT (30), 0xa0c00000,
1589 0,
1590 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1591 },
1592 /* ldb $dr,@$sr */
1593 {
1594 { 1, 1, 1, 1 },
1595 "ldb", "ldb", SYN (22), FMT (31), 0x2080,
1596 & fmt_31_ldb_ops[0],
1597 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1598 },
1599 /* ldb $dr,@($sr) */
1600 {
1601 { 1, 1, 1, 1 },
1602 "ldb-2", "ldb", SYN (23), FMT (28), 0x2080,
1603 0,
1604 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1605 },
1606 /* ldb $dr,@($slo16,$sr) */
1607 {
1608 { 1, 1, 1, 1 },
1609 "ldb-d", "ldb", SYN (24), FMT (32), 0xa0800000,
1610 & fmt_32_ldb_d_ops[0],
1611 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1612 },
1613 /* ldb $dr,@($sr,$slo16) */
1614 {
1615 { 1, 1, 1, 1 },
1616 "ldb-d2", "ldb", SYN (25), FMT (30), 0xa0800000,
1617 0,
1618 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1619 },
1620 /* ldh $dr,@$sr */
1621 {
1622 { 1, 1, 1, 1 },
1623 "ldh", "ldh", SYN (22), FMT (33), 0x20a0,
1624 & fmt_33_ldh_ops[0],
1625 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1626 },
1627 /* ldh $dr,@($sr) */
1628 {
1629 { 1, 1, 1, 1 },
1630 "ldh-2", "ldh", SYN (23), FMT (28), 0x20a0,
1631 0,
1632 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1633 },
1634 /* ldh $dr,@($slo16,$sr) */
1635 {
1636 { 1, 1, 1, 1 },
1637 "ldh-d", "ldh", SYN (24), FMT (34), 0xa0a00000,
1638 & fmt_34_ldh_d_ops[0],
1639 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1640 },
1641 /* ldh $dr,@($sr,$slo16) */
1642 {
1643 { 1, 1, 1, 1 },
1644 "ldh-d2", "ldh", SYN (25), FMT (30), 0xa0a00000,
1645 0,
1646 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1647 },
1648 /* ldub $dr,@$sr */
1649 {
1650 { 1, 1, 1, 1 },
1651 "ldub", "ldub", SYN (22), FMT (31), 0x2090,
1652 & fmt_31_ldb_ops[0],
1653 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1654 },
1655 /* ldub $dr,@($sr) */
1656 {
1657 { 1, 1, 1, 1 },
1658 "ldub-2", "ldub", SYN (23), FMT (28), 0x2090,
1659 0,
1660 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1661 },
1662 /* ldub $dr,@($slo16,$sr) */
1663 {
1664 { 1, 1, 1, 1 },
1665 "ldub-d", "ldub", SYN (24), FMT (32), 0xa0900000,
1666 & fmt_32_ldb_d_ops[0],
1667 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1668 },
1669 /* ldub $dr,@($sr,$slo16) */
1670 {
1671 { 1, 1, 1, 1 },
1672 "ldub-d2", "ldub", SYN (25), FMT (30), 0xa0900000,
1673 0,
1674 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1675 },
1676 /* lduh $dr,@$sr */
1677 {
1678 { 1, 1, 1, 1 },
1679 "lduh", "lduh", SYN (22), FMT (33), 0x20b0,
1680 & fmt_33_ldh_ops[0],
1681 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1682 },
1683 /* lduh $dr,@($sr) */
1684 {
1685 { 1, 1, 1, 1 },
1686 "lduh-2", "lduh", SYN (23), FMT (28), 0x20b0,
1687 0,
1688 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1689 },
1690 /* lduh $dr,@($slo16,$sr) */
1691 {
1692 { 1, 1, 1, 1 },
1693 "lduh-d", "lduh", SYN (24), FMT (34), 0xa0b00000,
1694 & fmt_34_ldh_d_ops[0],
1695 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1696 },
1697 /* lduh $dr,@($sr,$slo16) */
1698 {
1699 { 1, 1, 1, 1 },
1700 "lduh-d2", "lduh", SYN (25), FMT (30), 0xa0b00000,
1701 0,
1702 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1703 },
1704 /* ld $dr,@$sr+ */
1705 {
1706 { 1, 1, 1, 1 },
1707 "ld-plus", "ld", SYN (26), FMT (27), 0x20e0,
1708 & fmt_27_ld_ops[0],
1709 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
1710 },
1711 /* ld24 $dr,#$uimm24 */
1712 {
1713 { 1, 1, 1, 1 },
1714 "ld24", "ld24", SYN (27), FMT (35), 0xe0000000,
1715 & fmt_35_ld24_ops[0],
1716 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1717 },
1718 /* ld24 $dr,$uimm24 */
1719 {
1720 { 1, 1, 1, 1 },
1721 "ld24.a", "ld24", SYN (28), FMT (35), 0xe0000000,
1722 & fmt_35_ld24_ops[0],
1723 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1724 },
1725 /* ldi $dr,#$simm8 */
1726 {
1727 { 1, 1, 1, 1 },
1728 "ldi8", "ldi", SYN (7), FMT (36), 0x6000,
1729 & fmt_36_ldi8_ops[0],
1730 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1731 },
1732 /* ldi $dr,$simm8 */
1733 {
1734 { 1, 1, 1, 1 },
1735 "ldi8.a", "ldi", SYN (8), FMT (36), 0x6000,
1736 & fmt_36_ldi8_ops[0],
1737 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1738 },
1739 /* ldi8 $dr,#$simm8 */
1740 {
1741 { 1, 1, 1, 1 },
1742 "ldi8a", "ldi8", SYN (7), FMT (36), 0x6000,
1743 & fmt_36_ldi8_ops[0],
1744 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1745 },
1746 /* ldi8 $dr,$simm8 */
1747 {
1748 { 1, 1, 1, 1 },
1749 "ldi8a.a", "ldi8", SYN (8), FMT (36), 0x6000,
1750 & fmt_36_ldi8_ops[0],
1751 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1752 },
1753 /* ldi $dr,$slo16 */
1754 {
1755 { 1, 1, 1, 1 },
1756 "ldi16", "ldi", SYN (29), FMT (37), 0x90f00000,
1757 & fmt_37_ldi16_ops[0],
1758 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1759 },
1760 /* ldi16 $dr,$slo16 */
1761 {
1762 { 1, 1, 1, 1 },
1763 "ldi16a", "ldi16", SYN (29), FMT (37), 0x90f00000,
1764 & fmt_37_ldi16_ops[0],
1765 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
1766 },
1767 /* lock $dr,@$sr */
1768 {
1769 { 1, 1, 1, 1 },
1770 "lock", "lock", SYN (22), FMT (0), 0x20d0,
1771 & fmt_0_add_ops[0],
1772 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1773 },
1774 /* machi $src1,$src2 */
1775 {
1776 { 1, 1, 1, 1 },
1777 "machi", "machi", SYN (15), FMT (38), 0x3040,
1778 & fmt_38_machi_ops[0],
1779 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1780 },
1781 /* start-sanitize-m32rx */
1782 /* machi $src1,$src2,$acc */
1783 {
1784 { 1, 1, 1, 1 },
1785 "machi-a", "machi", SYN (30), FMT (39), 0x3040,
1786 & fmt_39_machi_a_ops[0],
1787 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1788 },
1789 /* end-sanitize-m32rx */
1790 /* maclo $src1,$src2 */
1791 {
1792 { 1, 1, 1, 1 },
1793 "maclo", "maclo", SYN (15), FMT (38), 0x3050,
1794 & fmt_38_machi_ops[0],
1795 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1796 },
1797 /* start-sanitize-m32rx */
1798 /* maclo $src1,$src2,$acc */
1799 {
1800 { 1, 1, 1, 1 },
1801 "maclo-a", "maclo", SYN (30), FMT (39), 0x3050,
1802 & fmt_39_machi_a_ops[0],
1803 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1804 },
1805 /* end-sanitize-m32rx */
1806 /* macwhi $src1,$src2 */
1807 {
1808 { 1, 1, 1, 1 },
1809 "macwhi", "macwhi", SYN (15), FMT (38), 0x3060,
1810 & fmt_38_machi_ops[0],
1811 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1812 },
1813 /* macwlo $src1,$src2 */
1814 {
1815 { 1, 1, 1, 1 },
1816 "macwlo", "macwlo", SYN (15), FMT (38), 0x3070,
1817 & fmt_38_machi_ops[0],
1818 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1819 },
1820 /* mul $dr,$sr */
1821 {
1822 { 1, 1, 1, 1 },
1823 "mul", "mul", SYN (0), FMT (0), 0x1060,
1824 & fmt_0_add_ops[0],
1825 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1826 },
1827 /* mulhi $src1,$src2 */
1828 {
1829 { 1, 1, 1, 1 },
1830 "mulhi", "mulhi", SYN (15), FMT (19), 0x3000,
1831 & fmt_19_cmp_ops[0],
1832 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1833 },
1834 /* start-sanitize-m32rx */
1835 /* mulhi $src1,$src2,$acc */
1836 {
1837 { 1, 1, 1, 1 },
1838 "mulhi-a", "mulhi", SYN (30), FMT (40), 0x3000,
1839 & fmt_40_mulhi_a_ops[0],
1840 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1841 },
1842 /* end-sanitize-m32rx */
1843 /* mullo $src1,$src2 */
1844 {
1845 { 1, 1, 1, 1 },
1846 "mullo", "mullo", SYN (15), FMT (19), 0x3010,
1847 & fmt_19_cmp_ops[0],
1848 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1849 },
1850 /* start-sanitize-m32rx */
1851 /* mullo $src1,$src2,$acc */
1852 {
1853 { 1, 1, 1, 1 },
1854 "mullo-a", "mullo", SYN (30), FMT (40), 0x3010,
1855 & fmt_40_mulhi_a_ops[0],
1856 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1857 },
1858 /* end-sanitize-m32rx */
1859 /* mulwhi $src1,$src2 */
1860 {
1861 { 1, 1, 1, 1 },
1862 "mulwhi", "mulwhi", SYN (15), FMT (19), 0x3020,
1863 & fmt_19_cmp_ops[0],
1864 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1865 },
1866 /* mulwlo $src1,$src2 */
1867 {
1868 { 1, 1, 1, 1 },
1869 "mulwlo", "mulwlo", SYN (15), FMT (19), 0x3030,
1870 & fmt_19_cmp_ops[0],
1871 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1872 },
1873 /* mv $dr,$sr */
1874 {
1875 { 1, 1, 1, 1 },
1876 "mv", "mv", SYN (0), FMT (41), 0x1080,
1877 & fmt_41_mv_ops[0],
1878 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1879 },
1880 /* mvfachi $dr */
1881 {
1882 { 1, 1, 1, 1 },
1883 "mvfachi", "mvfachi", SYN (31), FMT (42), 0x50f0,
1884 & fmt_42_mvfachi_ops[0],
1885 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1886 },
1887 /* start-sanitize-m32rx */
1888 /* mvfachi $dr,$accs */
1889 {
1890 { 1, 1, 1, 1 },
1891 "mvfachi-a", "mvfachi", SYN (32), FMT (43), 0x50f0,
1892 & fmt_43_mvfachi_a_ops[0],
1893 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1894 },
1895 /* end-sanitize-m32rx */
1896 /* mvfaclo $dr */
1897 {
1898 { 1, 1, 1, 1 },
1899 "mvfaclo", "mvfaclo", SYN (31), FMT (42), 0x50f1,
1900 & fmt_42_mvfachi_ops[0],
1901 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1902 },
1903 /* start-sanitize-m32rx */
1904 /* mvfaclo $dr,$accs */
1905 {
1906 { 1, 1, 1, 1 },
1907 "mvfaclo-a", "mvfaclo", SYN (32), FMT (43), 0x50f1,
1908 & fmt_43_mvfachi_a_ops[0],
1909 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1910 },
1911 /* end-sanitize-m32rx */
1912 /* mvfacmi $dr */
1913 {
1914 { 1, 1, 1, 1 },
1915 "mvfacmi", "mvfacmi", SYN (31), FMT (42), 0x50f2,
1916 & fmt_42_mvfachi_ops[0],
1917 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1918 },
1919 /* start-sanitize-m32rx */
1920 /* mvfacmi $dr,$accs */
1921 {
1922 { 1, 1, 1, 1 },
1923 "mvfacmi-a", "mvfacmi", SYN (32), FMT (43), 0x50f2,
1924 & fmt_43_mvfachi_a_ops[0],
1925 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1926 },
1927 /* end-sanitize-m32rx */
1928 /* mvfc $dr,$scr */
1929 {
1930 { 1, 1, 1, 1 },
1931 "mvfc", "mvfc", SYN (33), FMT (44), 0x1090,
1932 & fmt_44_mvfc_ops[0],
1933 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1934 },
1935 /* mvtachi $src1 */
1936 {
1937 { 1, 1, 1, 1 },
1938 "mvtachi", "mvtachi", SYN (34), FMT (45), 0x5070,
1939 & fmt_45_mvtachi_ops[0],
1940 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1941 },
1942 /* start-sanitize-m32rx */
1943 /* mvtachi $src1,$accs */
1944 {
1945 { 1, 1, 1, 1 },
1946 "mvtachi-a", "mvtachi", SYN (35), FMT (46), 0x5070,
1947 & fmt_46_mvtachi_a_ops[0],
1948 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1949 },
1950 /* end-sanitize-m32rx */
1951 /* mvtaclo $src1 */
1952 {
1953 { 1, 1, 1, 1 },
1954 "mvtaclo", "mvtaclo", SYN (34), FMT (45), 0x5071,
1955 & fmt_45_mvtachi_ops[0],
1956 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1957 },
1958 /* start-sanitize-m32rx */
1959 /* mvtaclo $src1,$accs */
1960 {
1961 { 1, 1, 1, 1 },
1962 "mvtaclo-a", "mvtaclo", SYN (35), FMT (46), 0x5071,
1963 & fmt_46_mvtachi_a_ops[0],
1964 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
1965 },
1966 /* end-sanitize-m32rx */
1967 /* mvtc $sr,$dcr */
1968 {
1969 { 1, 1, 1, 1 },
1970 "mvtc", "mvtc", SYN (36), FMT (47), 0x10a0,
1971 & fmt_47_mvtc_ops[0],
1972 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
1973 },
1974 /* neg $dr,$sr */
1975 {
1976 { 1, 1, 1, 1 },
1977 "neg", "neg", SYN (0), FMT (41), 0x30,
1978 & fmt_41_mv_ops[0],
1979 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1980 },
1981 /* nop */
1982 {
1983 { 1, 1, 1, 1 },
1984 "nop", "nop", SYN (37), FMT (48), 0x7000,
1985 0,
1986 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1987 },
1988 /* not $dr,$sr */
1989 {
1990 { 1, 1, 1, 1 },
1991 "not", "not", SYN (0), FMT (41), 0xb0,
1992 & fmt_41_mv_ops[0],
1993 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
1994 },
1995 /* rac */
1996 {
1997 { 1, 1, 1, 1 },
1998 "rac", "rac", SYN (37), FMT (49), 0x5090,
1999 & fmt_49_rac_ops[0],
2000 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2001 },
2002 /* start-sanitize-m32rx */
2003 /* rac $accd */
2004 {
2005 { 1, 1, 1, 1 },
2006 "rac-d", "rac", SYN (38), FMT (50), 0x5090,
2007 & fmt_50_rac_d_ops[0],
2008 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2009 },
2010 /* end-sanitize-m32rx */
2011 /* start-sanitize-m32rx */
2012 /* rac $accd,$accs */
2013 {
2014 { 1, 1, 1, 1 },
2015 "rac-ds", "rac", SYN (39), FMT (51), 0x5090,
2016 & fmt_51_rac_ds_ops[0],
2017 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2018 },
2019 /* end-sanitize-m32rx */
2020 /* start-sanitize-m32rx */
2021 /* rac $accd,$accs,#$imm1 */
2022 {
2023 { 1, 1, 1, 1 },
2024 "rac-dsi", "rac", SYN (40), FMT (52), 0x5090,
2025 & fmt_52_rac_dsi_ops[0],
2026 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2027 },
2028 /* end-sanitize-m32rx */
2029 /* rach */
2030 {
2031 { 1, 1, 1, 1 },
2032 "rach", "rach", SYN (37), FMT (49), 0x5080,
2033 & fmt_49_rac_ops[0],
2034 { 4, 0, { (1<<MACH_M32R), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2035 },
2036 /* start-sanitize-m32rx */
2037 /* rach $accd */
2038 {
2039 { 1, 1, 1, 1 },
2040 "rach-d", "rach", SYN (38), FMT (50), 0x5080,
2041 & fmt_50_rac_d_ops[0],
2042 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2043 },
2044 /* end-sanitize-m32rx */
2045 /* start-sanitize-m32rx */
2046 /* rach $accd,$accs */
2047 {
2048 { 1, 1, 1, 1 },
2049 "rach-ds", "rach", SYN (39), FMT (51), 0x5080,
2050 & fmt_51_rac_ds_ops[0],
2051 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2052 },
2053 /* end-sanitize-m32rx */
2054 /* start-sanitize-m32rx */
2055 /* rach $accd,$accs,#$imm1 */
2056 {
2057 { 1, 1, 1, 1 },
2058 "rach-dsi", "rach", SYN (40), FMT (52), 0x5080,
2059 & fmt_52_rac_dsi_ops[0],
2060 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2061 },
2062 /* end-sanitize-m32rx */
2063 /* rte */
2064 {
2065 { 1, 1, 1, 1 },
2066 "rte", "rte", SYN (37), FMT (53), 0x10d6,
2067 & fmt_53_rte_ops[0],
2068 { 4, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2069 },
2070 /* seth $dr,#$hi16 */
2071 {
2072 { 1, 1, 1, 1 },
2073 "seth", "seth", SYN (41), FMT (54), 0xd0c00000,
2074 & fmt_54_seth_ops[0],
2075 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2076 },
2077 /* seth $dr,$hi16 */
2078 {
2079 { 1, 1, 1, 1 },
2080 "seth.a", "seth", SYN (42), FMT (54), 0xd0c00000,
2081 & fmt_54_seth_ops[0],
2082 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2083 },
2084 /* sll $dr,$sr */
2085 {
2086 { 1, 1, 1, 1 },
2087 "sll", "sll", SYN (0), FMT (0), 0x1040,
2088 & fmt_0_add_ops[0],
2089 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2090 },
2091 /* sll3 $dr,$sr,#$simm16 */
2092 {
2093 { 1, 1, 1, 1 },
2094 "sll3", "sll3", SYN (9), FMT (5), 0x90c00000,
2095 & fmt_5_addv3_ops[0],
2096 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2097 },
2098 /* sll3 $dr,$sr,$simm16 */
2099 {
2100 { 1, 1, 1, 1 },
2101 "sll3.a", "sll3", SYN (10), FMT (5), 0x90c00000,
2102 & fmt_5_addv3_ops[0],
2103 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2104 },
2105 /* slli $dr,#$uimm5 */
2106 {
2107 { 1, 1, 1, 1 },
2108 "slli", "slli", SYN (43), FMT (55), 0x5040,
2109 & fmt_55_slli_ops[0],
2110 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2111 },
2112 /* slli $dr,$uimm5 */
2113 {
2114 { 1, 1, 1, 1 },
2115 "slli.a", "slli", SYN (44), FMT (55), 0x5040,
2116 & fmt_55_slli_ops[0],
2117 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2118 },
2119 /* sra $dr,$sr */
2120 {
2121 { 1, 1, 1, 1 },
2122 "sra", "sra", SYN (0), FMT (0), 0x1020,
2123 & fmt_0_add_ops[0],
2124 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2125 },
2126 /* sra3 $dr,$sr,#$simm16 */
2127 {
2128 { 1, 1, 1, 1 },
2129 "sra3", "sra3", SYN (9), FMT (5), 0x90a00000,
2130 & fmt_5_addv3_ops[0],
2131 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2132 },
2133 /* sra3 $dr,$sr,$simm16 */
2134 {
2135 { 1, 1, 1, 1 },
2136 "sra3.a", "sra3", SYN (10), FMT (5), 0x90a00000,
2137 & fmt_5_addv3_ops[0],
2138 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2139 },
2140 /* srai $dr,#$uimm5 */
2141 {
2142 { 1, 1, 1, 1 },
2143 "srai", "srai", SYN (43), FMT (55), 0x5020,
2144 & fmt_55_slli_ops[0],
2145 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2146 },
2147 /* srai $dr,$uimm5 */
2148 {
2149 { 1, 1, 1, 1 },
2150 "srai.a", "srai", SYN (44), FMT (55), 0x5020,
2151 & fmt_55_slli_ops[0],
2152 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2153 },
2154 /* srl $dr,$sr */
2155 {
2156 { 1, 1, 1, 1 },
2157 "srl", "srl", SYN (0), FMT (0), 0x1000,
2158 & fmt_0_add_ops[0],
2159 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2160 },
2161 /* srl3 $dr,$sr,#$simm16 */
2162 {
2163 { 1, 1, 1, 1 },
2164 "srl3", "srl3", SYN (9), FMT (5), 0x90800000,
2165 & fmt_5_addv3_ops[0],
2166 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2167 },
2168 /* srl3 $dr,$sr,$simm16 */
2169 {
2170 { 1, 1, 1, 1 },
2171 "srl3.a", "srl3", SYN (10), FMT (5), 0x90800000,
2172 & fmt_5_addv3_ops[0],
2173 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2174 },
2175 /* srli $dr,#$uimm5 */
2176 {
2177 { 1, 1, 1, 1 },
2178 "srli", "srli", SYN (43), FMT (55), 0x5000,
2179 & fmt_55_slli_ops[0],
2180 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2181 },
2182 /* srli $dr,$uimm5 */
2183 {
2184 { 1, 1, 1, 1 },
2185 "srli.a", "srli", SYN (44), FMT (55), 0x5000,
2186 & fmt_55_slli_ops[0],
2187 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2188 },
2189 /* st $src1,@$src2 */
2190 {
2191 { 1, 1, 1, 1 },
2192 "st", "st", SYN (45), FMT (19), 0x2040,
2193 & fmt_19_cmp_ops[0],
2194 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2195 },
2196 /* st $src1,@($src2) */
2197 {
2198 { 1, 1, 1, 1 },
2199 "st-2", "st", SYN (46), FMT (56), 0x2040,
2200 0,
2201 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2202 },
2203 /* st $src1,@($slo16,$src2) */
2204 {
2205 { 1, 1, 1, 1 },
2206 "st-d", "st", SYN (47), FMT (57), 0xa0400000,
2207 & fmt_57_st_d_ops[0],
2208 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2209 },
2210 /* st $src1,@($src2,$slo16) */
2211 {
2212 { 1, 1, 1, 1 },
2213 "st-d2", "st", SYN (48), FMT (58), 0xa0400000,
2214 0,
2215 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2216 },
2217 /* stb $src1,@$src2 */
2218 {
2219 { 1, 1, 1, 1 },
2220 "stb", "stb", SYN (45), FMT (19), 0x2000,
2221 & fmt_19_cmp_ops[0],
2222 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2223 },
2224 /* stb $src1,@($src2) */
2225 {
2226 { 1, 1, 1, 1 },
2227 "stb-2", "stb", SYN (46), FMT (56), 0x2000,
2228 0,
2229 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2230 },
2231 /* stb $src1,@($slo16,$src2) */
2232 {
2233 { 1, 1, 1, 1 },
2234 "stb-d", "stb", SYN (47), FMT (57), 0xa0000000,
2235 & fmt_57_st_d_ops[0],
2236 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2237 },
2238 /* stb $src1,@($src2,$slo16) */
2239 {
2240 { 1, 1, 1, 1 },
2241 "stb-d2", "stb", SYN (48), FMT (58), 0xa0000000,
2242 0,
2243 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2244 },
2245 /* sth $src1,@$src2 */
2246 {
2247 { 1, 1, 1, 1 },
2248 "sth", "sth", SYN (45), FMT (19), 0x2020,
2249 & fmt_19_cmp_ops[0],
2250 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2251 },
2252 /* sth $src1,@($src2) */
2253 {
2254 { 1, 1, 1, 1 },
2255 "sth-2", "sth", SYN (46), FMT (56), 0x2020,
2256 0,
2257 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2258 },
2259 /* sth $src1,@($slo16,$src2) */
2260 {
2261 { 1, 1, 1, 1 },
2262 "sth-d", "sth", SYN (47), FMT (57), 0xa0200000,
2263 & fmt_57_st_d_ops[0],
2264 { 4, 0, { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2265 },
2266 /* sth $src1,@($src2,$slo16) */
2267 {
2268 { 1, 1, 1, 1 },
2269 "sth-d2", "sth", SYN (48), FMT (58), 0xa0200000,
2270 0,
2271 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2272 },
2273 /* st $src1,@+$src2 */
2274 {
2275 { 1, 1, 1, 1 },
2276 "st-plus", "st", SYN (49), FMT (19), 0x2060,
2277 & fmt_19_cmp_ops[0],
2278 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
2279 },
2280 /* st $src1,@-$src2 */
2281 {
2282 { 1, 1, 1, 1 },
2283 "st-minus", "st", SYN (50), FMT (19), 0x2070,
2284 & fmt_19_cmp_ops[0],
2285 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_YES } }
2286 },
2287 /* sub $dr,$sr */
2288 {
2289 { 1, 1, 1, 1 },
2290 "sub", "sub", SYN (0), FMT (0), 0x20,
2291 & fmt_0_add_ops[0],
2292 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2293 },
2294 /* subv $dr,$sr */
2295 {
2296 { 1, 1, 1, 1 },
2297 "subv", "subv", SYN (0), FMT (0), 0x0,
2298 & fmt_0_add_ops[0],
2299 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2300 },
2301 /* subx $dr,$sr */
2302 {
2303 { 1, 1, 1, 1 },
2304 "subx", "subx", SYN (0), FMT (6), 0x10,
2305 & fmt_6_addx_ops[0],
2306 { 4, 0, { (1<<MACH_M32R), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2307 },
2308 /* trap #$uimm4 */
2309 {
2310 { 1, 1, 1, 1 },
2311 "trap", "trap", SYN (51), FMT (59), 0x10f0,
2312 & fmt_59_trap_ops[0],
2313 { 4, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2314 },
2315 /* trap $uimm4 */
2316 {
2317 { 1, 1, 1, 1 },
2318 "trap.a", "trap", SYN (52), FMT (59), 0x10f0,
2319 & fmt_59_trap_ops[0],
2320 { 4, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2321 },
2322 /* unlock $src1,@$src2 */
2323 {
2324 { 1, 1, 1, 1 },
2325 "unlock", "unlock", SYN (45), FMT (19), 0x2050,
2326 & fmt_19_cmp_ops[0],
2327 { 4, 0, { (1<<MACH_M32R), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2328 },
2329 /* push $src1 */
2330 {
2331 { 1, 1, 1, 1 },
2332 "push", "push", SYN (34), FMT (60), 0x207f,
2333 0,
2334 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2335 },
2336 /* pop $dr */
2337 {
2338 { 1, 1, 1, 1 },
2339 "pop", "pop", SYN (31), FMT (61), 0x20ef,
2340 0,
2341 { 4, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2342 },
2343 /* start-sanitize-m32rx */
2344 /* satb $dr,$src2 */
2345 {
2346 { 1, 1, 1, 1 },
2347 "satb", "satb", SYN (53), FMT (62), 0x80000100,
2348 & fmt_62_satb_ops[0],
2349 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2350 },
2351 /* end-sanitize-m32rx */
2352 /* start-sanitize-m32rx */
2353 /* sath $dr,$src2 */
2354 {
2355 { 1, 1, 1, 1 },
2356 "sath", "sath", SYN (53), FMT (62), 0x80000200,
2357 & fmt_62_satb_ops[0],
2358 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2359 },
2360 /* end-sanitize-m32rx */
2361 /* start-sanitize-m32rx */
2362 /* sat $dr,$src2 */
2363 {
2364 { 1, 1, 1, 1 },
2365 "sat", "sat", SYN (53), FMT (63), 0x80000000,
2366 & fmt_63_sat_ops[0],
2367 { 4, 0, { (1<<MACH_M32RX), PIPE_NONE, WRITE_LR_NO, WRITE_SRC_NO } }
2368 },
2369 /* end-sanitize-m32rx */
2370 /* start-sanitize-m32rx */
2371 /* pcmpbz $src2 */
2372 {
2373 { 1, 1, 1, 1 },
2374 "pcmpbz", "pcmpbz", SYN (20), FMT (22), 0x370,
2375 & fmt_22_cmpz_ops[0],
2376 { 4, 0, { (1<<MACH_M32RX), PIPE_OS, WRITE_LR_NO, WRITE_SRC_NO } }
2377 },
2378 /* end-sanitize-m32rx */
2379 /* start-sanitize-m32rx */
2380 /* sadd */
2381 {
2382 { 1, 1, 1, 1 },
2383 "sadd", "sadd", SYN (37), FMT (64), 0x50e4,
2384 & fmt_64_sadd_ops[0],
2385 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2386 },
2387 /* end-sanitize-m32rx */
2388 /* start-sanitize-m32rx */
2389 /* macwu1 $src1,$src2 */
2390 {
2391 { 1, 1, 1, 1 },
2392 "macwu1", "macwu1", SYN (15), FMT (65), 0x50b0,
2393 & fmt_65_macwu1_ops[0],
2394 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2395 },
2396 /* end-sanitize-m32rx */
2397 /* start-sanitize-m32rx */
2398 /* msblo $src1,$src2 */
2399 {
2400 { 1, 1, 1, 1 },
2401 "msblo", "msblo", SYN (15), FMT (38), 0x50d0,
2402 & fmt_38_machi_ops[0],
2403 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2404 },
2405 /* end-sanitize-m32rx */
2406 /* start-sanitize-m32rx */
2407 /* mulwu1 $src1,$src2 */
2408 {
2409 { 1, 1, 1, 1 },
2410 "mulwu1", "mulwu1", SYN (15), FMT (19), 0x50a0,
2411 & fmt_19_cmp_ops[0],
2412 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2413 },
2414 /* end-sanitize-m32rx */
2415 /* start-sanitize-m32rx */
2416 /* maclh1 $src1,$src2 */
2417 {
2418 { 1, 1, 1, 1 },
2419 "maclh1", "maclh1", SYN (15), FMT (65), 0x50c0,
2420 & fmt_65_macwu1_ops[0],
2421 { 4, 0, { (1<<MACH_M32RX), PIPE_S, WRITE_LR_NO, WRITE_SRC_NO } }
2422 },
2423 /* end-sanitize-m32rx */
2424 /* start-sanitize-m32rx */
2425 /* sc */
2426 {
2427 { 1, 1, 1, 1 },
2428 "sc", "sc", SYN (37), FMT (66), 0x7401,
2429 & fmt_66_sc_ops[0],
2430 { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2431 },
2432 /* end-sanitize-m32rx */
2433 /* start-sanitize-m32rx */
2434 /* snc */
2435 {
2436 { 1, 1, 1, 1 },
2437 "snc", "snc", SYN (37), FMT (66), 0x7501,
2438 & fmt_66_sc_ops[0],
2439 { 4, 0, { (1<<MACH_M32RX), PIPE_O, WRITE_LR_NO, WRITE_SRC_NO } }
2440 },
2441 /* end-sanitize-m32rx */
2442 };
2443
2444 #undef A
2445 #undef SYN
2446 #undef FMT
2447
2448 CGEN_INSN_TABLE m32r_cgen_insn_table =
2449 {
2450 & m32r_cgen_insn_table_entries[0],
2451 sizeof (CGEN_INSN),
2452 MAX_INSNS,
2453 NULL,
2454 m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2455 m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2456 };
2457
2458 /* The hash functions are recorded here to help keep assembler code out of
2459 the disassembler and vice versa. */
2460
2461 unsigned int
2462 m32r_cgen_asm_hash_insn (insn)
2463 const char * insn;
2464 {
2465 return CGEN_ASM_HASH (insn);
2466 }
2467
2468 unsigned int
2469 m32r_cgen_dis_hash_insn (buf, value)
2470 const char * buf;
2471 unsigned long value;
2472 {
2473 return CGEN_DIS_HASH (buf, value);
2474 }
2475
2476 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2477 {
2478 & m32r_cgen_hw_entries[0],
2479 & m32r_cgen_insn_table,
2480 };
2481
2482 void
2483 m32r_cgen_init_tables (mach)
2484 int mach;
2485 {
2486 }
2487
2488 /* Main entry point for stuffing values in cgen_fields. */
2489
2490 CGEN_INLINE void
2491 m32r_cgen_set_operand (opindex, valuep, fields)
2492 int opindex;
2493 const long * valuep;
2494 CGEN_FIELDS * fields;
2495 {
2496 switch (opindex)
2497 {
2498 case M32R_OPERAND_SR :
2499 fields->f_r2 = * valuep;
2500 break;
2501 case M32R_OPERAND_DR :
2502 fields->f_r1 = * valuep;
2503 break;
2504 case M32R_OPERAND_SRC1 :
2505 fields->f_r1 = * valuep;
2506 break;
2507 case M32R_OPERAND_SRC2 :
2508 fields->f_r2 = * valuep;
2509 break;
2510 case M32R_OPERAND_SCR :
2511 fields->f_r2 = * valuep;
2512 break;
2513 case M32R_OPERAND_DCR :
2514 fields->f_r1 = * valuep;
2515 break;
2516 case M32R_OPERAND_SIMM8 :
2517 fields->f_simm8 = * valuep;
2518 break;
2519 case M32R_OPERAND_SIMM16 :
2520 fields->f_simm16 = * valuep;
2521 break;
2522 case M32R_OPERAND_UIMM4 :
2523 fields->f_uimm4 = * valuep;
2524 break;
2525 case M32R_OPERAND_UIMM5 :
2526 fields->f_uimm5 = * valuep;
2527 break;
2528 case M32R_OPERAND_UIMM16 :
2529 fields->f_uimm16 = * valuep;
2530 break;
2531 /* start-sanitize-m32rx */
2532 case M32R_OPERAND_IMM1 :
2533 fields->f_imm1 = * valuep;
2534 break;
2535 /* end-sanitize-m32rx */
2536 /* start-sanitize-m32rx */
2537 case M32R_OPERAND_ACCD :
2538 fields->f_accd = * valuep;
2539 break;
2540 /* end-sanitize-m32rx */
2541 /* start-sanitize-m32rx */
2542 case M32R_OPERAND_ACCS :
2543 fields->f_accs = * valuep;
2544 break;
2545 /* end-sanitize-m32rx */
2546 /* start-sanitize-m32rx */
2547 case M32R_OPERAND_ACC :
2548 fields->f_acc = * valuep;
2549 break;
2550 /* end-sanitize-m32rx */
2551 case M32R_OPERAND_HI16 :
2552 fields->f_hi16 = * valuep;
2553 break;
2554 case M32R_OPERAND_SLO16 :
2555 fields->f_simm16 = * valuep;
2556 break;
2557 case M32R_OPERAND_ULO16 :
2558 fields->f_uimm16 = * valuep;
2559 break;
2560 case M32R_OPERAND_UIMM24 :
2561 fields->f_uimm24 = * valuep;
2562 break;
2563 case M32R_OPERAND_DISP8 :
2564 fields->f_disp8 = * valuep;
2565 break;
2566 case M32R_OPERAND_DISP16 :
2567 fields->f_disp16 = * valuep;
2568 break;
2569 case M32R_OPERAND_DISP24 :
2570 fields->f_disp24 = * valuep;
2571 break;
2572
2573 default :
2574 fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2575 opindex);
2576 abort ();
2577 }
2578 }
2579
2580 /* Main entry point for getting values from cgen_fields. */
2581
2582 CGEN_INLINE long
2583 m32r_cgen_get_operand (opindex, fields)
2584 int opindex;
2585 const CGEN_FIELDS * fields;
2586 {
2587 long value;
2588
2589 switch (opindex)
2590 {
2591 case M32R_OPERAND_SR :
2592 value = fields->f_r2;
2593 break;
2594 case M32R_OPERAND_DR :
2595 value = fields->f_r1;
2596 break;
2597 case M32R_OPERAND_SRC1 :
2598 value = fields->f_r1;
2599 break;
2600 case M32R_OPERAND_SRC2 :
2601 value = fields->f_r2;
2602 break;
2603 case M32R_OPERAND_SCR :
2604 value = fields->f_r2;
2605 break;
2606 case M32R_OPERAND_DCR :
2607 value = fields->f_r1;
2608 break;
2609 case M32R_OPERAND_SIMM8 :
2610 value = fields->f_simm8;
2611 break;
2612 case M32R_OPERAND_SIMM16 :
2613 value = fields->f_simm16;
2614 break;
2615 case M32R_OPERAND_UIMM4 :
2616 value = fields->f_uimm4;
2617 break;
2618 case M32R_OPERAND_UIMM5 :
2619 value = fields->f_uimm5;
2620 break;
2621 case M32R_OPERAND_UIMM16 :
2622 value = fields->f_uimm16;
2623 break;
2624 /* start-sanitize-m32rx */
2625 case M32R_OPERAND_IMM1 :
2626 value = fields->f_imm1;
2627 break;
2628 /* end-sanitize-m32rx */
2629 /* start-sanitize-m32rx */
2630 case M32R_OPERAND_ACCD :
2631 value = fields->f_accd;
2632 break;
2633 /* end-sanitize-m32rx */
2634 /* start-sanitize-m32rx */
2635 case M32R_OPERAND_ACCS :
2636 value = fields->f_accs;
2637 break;
2638 /* end-sanitize-m32rx */
2639 /* start-sanitize-m32rx */
2640 case M32R_OPERAND_ACC :
2641 value = fields->f_acc;
2642 break;
2643 /* end-sanitize-m32rx */
2644 case M32R_OPERAND_HI16 :
2645 value = fields->f_hi16;
2646 break;
2647 case M32R_OPERAND_SLO16 :
2648 value = fields->f_simm16;
2649 break;
2650 case M32R_OPERAND_ULO16 :
2651 value = fields->f_uimm16;
2652 break;
2653 case M32R_OPERAND_UIMM24 :
2654 value = fields->f_uimm24;
2655 break;
2656 case M32R_OPERAND_DISP8 :
2657 value = fields->f_disp8;
2658 break;
2659 case M32R_OPERAND_DISP16 :
2660 value = fields->f_disp16;
2661 break;
2662 case M32R_OPERAND_DISP24 :
2663 value = fields->f_disp24;
2664 break;
2665
2666 default :
2667 fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2668 opindex);
2669 abort ();
2670 }
2671
2672 return value;
2673 }
2674
GDB Binutils - Deliverables
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