opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31 #include "opintl.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
  40
  41 /* Cover function to read and properly byteswap an insn value.  */
  42
  43 CGEN_INSN_INT
  44 cgen_get_insn_value (od, buf, length)
  45      CGEN_OPCODE_DESC od;
  46      unsigned char *buf;
  47      int length;
  48 {
  49   CGEN_INSN_INT value;
  50
  51   switch (length)
  52     {
  53     case 8:
  54       value = *buf;
  55       break;
  56     case 16:
  57       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  58         value = bfd_getb16 (buf);
  59       else
  60         value = bfd_getl16 (buf);
  61       break;
  62     case 32:
  63       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  64         value = bfd_getb32 (buf);
  65       else
  66         value = bfd_getl32 (buf);
  67       break;
  68     default:
  69       abort ();
  70     }
  71
  72   return value;
  73 }
  74
  75 /* Cover function to store an insn value properly byteswapped.  */
  76
  77 void
  78 cgen_put_insn_value (od, buf, length, value)
  79      CGEN_OPCODE_DESC od;
  80      unsigned char *buf;
  81      int length;
  82      CGEN_INSN_INT value;
  83 {
  84   switch (length)
  85     {
  86     case 8:
  87       buf[0] = value;
  88       break;
  89     case 16:
  90       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  91         bfd_putb16 (value, buf);
  92       else
  93         bfd_putl16 (value, buf);
  94       break;
  95     case 32:
  96       if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
  97         bfd_putb32 (value, buf);
  98       else
  99         bfd_putl32 (value, buf);
 100       break;
 101     default:
 102       abort ();
 103     }
 104 }
 105
 106 /* Look up instruction INSN_VALUE and extract its fields.
 107    INSN, if non-null, is the insn table entry.
 108    Otherwise INSN_VALUE is examined to compute it.
 109    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
 110    0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
 111    If INSN != NULL, LENGTH must be valid.
 112    ALIAS_P is non-zero if alias insns are to be included in the search.
 113
 114    The result a pointer to the insn table entry, or NULL if the instruction
 115    wasn't recognized.  */
 116
 117 const CGEN_INSN *
 118 m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
 119      CGEN_OPCODE_DESC od;
 120      const CGEN_INSN *insn;
 121      CGEN_INSN_BYTES insn_value;
 122      int length;
 123      CGEN_FIELDS *fields;
 124      int alias_p;
 125 {
 126   unsigned char buf[16];
 127   unsigned char *bufp;
 128   unsigned int base_insn;
 129 #if CGEN_INT_INSN_P
 130   CGEN_EXTRACT_INFO *info = NULL;
 131 #else
 132   CGEN_EXTRACT_INFO ex_info;
 133   CGEN_EXTRACT_INFO *info = &ex_info;
 134 #endif
 135
 136 #if ! CGEN_INT_INSN_P
 137   ex_info.dis_info = NULL;
 138   ex_info.bytes = insn_value;
 139   ex_info.valid = -1;
 140 #endif
 141
 142   if (!insn)
 143     {
 144       const CGEN_INSN_LIST *insn_list;
 145
 146 #if CGEN_INT_INSN_P
 147       cgen_put_insn_value (od, buf, length, insn_value);
 148       bufp = buf;
 149       base_insn = insn_value; /*???*/
 150 #else
 151       base_insn = cgen_get_insn_value (od, buf, length);
 152       bufp = insn_value;
 153 #endif
 154
 155       /* The instructions are stored in hash lists.
 156          Pick the first one and keep trying until we find the right one.  */
 157
 158       insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
 159       while (insn_list != NULL)
 160         {
 161           insn = insn_list->insn;
 162
 163           if (alias_p
 164               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 165             {
 166               /* Basic bit mask must be correct.  */
 167               /* ??? May wish to allow target to defer this check until the
 168                  extract handler.  */
 169               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 170                 {
 171                   /* ??? 0 is passed for `pc' */
 172                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
 173                                                            insn_value, fields,
 174                                                            (bfd_vma) 0);
 175                   if (elength > 0)
 176                     {
 177                       /* sanity check */
 178                       if (length != 0 && length != elength)
 179                         abort ();
 180                       return insn;
 181                     }
 182                 }
 183             }
 184
 185           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 186         }
 187     }
 188   else
 189     {
 190       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 191       if (! alias_p
 192           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 193         abort ();
 194       /* Sanity check: length must be correct.  */
 195       if (length != CGEN_INSN_BITSIZE (insn))
 196         abort ();
 197
 198       /* ??? 0 is passed for `pc' */
 199       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
 200                                           (bfd_vma) 0);
 201       /* Sanity check: must succeed.
 202          Could relax this later if it ever proves useful.  */
 203       if (length == 0)
 204         abort ();
 205       return insn;
 206     }
 207
 208   return NULL;
 209 }
 210
 211 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 212    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 213    in.  */
 214
 215 void
 216 m32r_cgen_get_insn_operands (od, insn, fields, indices)
 217      CGEN_OPCODE_DESC od;
 218      const CGEN_INSN * insn;
 219      const CGEN_FIELDS * fields;
 220      int *indices;
 221 {
 222   const CGEN_OPERAND_INSTANCE *opinst;
 223   int i;
 224
 225   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 226        opinst != NULL
 227          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 228        ++i, ++opinst)
 229     {
 230       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 231       if (op == NULL)
 232         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 233       else
 234         indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 235                                                   fields);
 236     }
 237 }
 238
 239 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
 240    isn't known.
 241    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 242    m32r_cgen_lookup_insn unchanged.
 243
 244    The result is the insn table entry or NULL if the instruction wasn't
 245    recognized.  */
 246
 247 const CGEN_INSN *
 248 m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 249      CGEN_OPCODE_DESC od;
 250      const CGEN_INSN *insn;
 251      CGEN_INSN_BYTES insn_value;
 252      int length;
 253      int *indices;
 254 {
 255   CGEN_FIELDS fields;
 256
 257   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 258      If INSN == NULL, we want a real insn.  */
 259   insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 260                                   insn != NULL);
 261   if (! insn)
 262     return NULL;
 263
 264   m32r_cgen_get_insn_operands (od, insn, &fields, indices);
 265   return insn;
 266 }
 267 /* Attributes.  */
 268
 269 static const CGEN_ATTR_ENTRY MACH_attr[] =
 270 {
 271   { "base", MACH_BASE },
 272   { "m32r", MACH_M32R },
 273 /* start-sanitize-m32rx */
 274   { "m32rx", MACH_M32RX },
 275 /* end-sanitize-m32rx */
 276   { "max", MACH_MAX },
 277   { 0, 0 }
 278 };
 279
 280 /* start-sanitize-m32rx */
 281 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 282 {
 283   { "NONE", PIPE_NONE },
 284   { "O", PIPE_O },
 285   { "S", PIPE_S },
 286   { "OS", PIPE_OS },
 287   { 0, 0 }
 288 };
 289
 290 /* end-sanitize-m32rx */
 291 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
 292 {
 293   { "MACH", & MACH_attr[0] },
 294   { "CACHE-ADDR", NULL },
 295   { "FUN-ACCESS", NULL },
 296   { "PC", NULL },
 297   { "PROFILE", NULL },
 298   { "SIGN-OPT", NULL },
 299   { "UNSIGNED", NULL },
 300   { 0, 0 }
 301 };
 302
 303 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 304 {
 305   { "ABS-ADDR", NULL },
 306   { "HASH-PREFIX", NULL },
 307   { "NEGATIVE", NULL },
 308   { "PCREL-ADDR", NULL },
 309   { "RELAX", NULL },
 310   { "RELOC", NULL },
 311   { "SEM-ONLY", NULL },
 312   { "SIGN-OPT", NULL },
 313   { "UNSIGNED", NULL },
 314   { 0, 0 }
 315 };
 316
 317 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 318 {
 319   { "MACH", & MACH_attr[0] },
 320 /* start-sanitize-m32rx */
 321   { "PIPE", & PIPE_attr[0] },
 322 /* end-sanitize-m32rx */
 323   { "ALIAS", NULL },
 324   { "COND-CTI", NULL },
 325   { "FILL-SLOT", NULL },
 326   { "NO-DIS", NULL },
 327   { "RELAX", NULL },
 328   { "RELAXABLE", NULL },
 329   { "SKIP-CTI", NULL },
 330   { "SPECIAL", NULL },
 331   { "UNCOND-CTI", NULL },
 332   { "VIRTUAL", NULL },
 333   { 0, 0 }
 334 };
 335
 336 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 337 {
 338   { "fp", 13 },
 339   { "lr", 14 },
 340   { "sp", 15 },
 341   { "r0", 0 },
 342   { "r1", 1 },
 343   { "r2", 2 },
 344   { "r3", 3 },
 345   { "r4", 4 },
 346   { "r5", 5 },
 347   { "r6", 6 },
 348   { "r7", 7 },
 349   { "r8", 8 },
 350   { "r9", 9 },
 351   { "r10", 10 },
 352   { "r11", 11 },
 353   { "r12", 12 },
 354   { "r13", 13 },
 355   { "r14", 14 },
 356   { "r15", 15 }
 357 };
 358
 359 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 360 {
 361   & m32r_cgen_opval_h_gr_entries[0],
 362   19
 363 };
 364
 365 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 366 {
 367   { "psw", 0 },
 368   { "cbr", 1 },
 369   { "spi", 2 },
 370   { "spu", 3 },
 371   { "bpc", 6 },
 372   { "bbpsw", 8 },
 373   { "bbpc", 14 },
 374   { "cr0", 0 },
 375   { "cr1", 1 },
 376   { "cr2", 2 },
 377   { "cr3", 3 },
 378   { "cr4", 4 },
 379   { "cr5", 5 },
 380   { "cr6", 6 },
 381   { "cr7", 7 },
 382   { "cr8", 8 },
 383   { "cr9", 9 },
 384   { "cr10", 10 },
 385   { "cr11", 11 },
 386   { "cr12", 12 },
 387   { "cr13", 13 },
 388   { "cr14", 14 },
 389   { "cr15", 15 }
 390 };
 391
 392 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 393 {
 394   & m32r_cgen_opval_h_cr_entries[0],
 395   23
 396 };
 397
 398 /* start-sanitize-m32rx */
 399 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 400 {
 401   { "a0", 0 },
 402   { "a1", 1 }
 403 };
 404
 405 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 406 {
 407   & m32r_cgen_opval_h_accums_entries[0],
 408   2
 409 };
 410
 411 /* end-sanitize-m32rx */
 412
 413 /* The hardware table.  */
 414
 415 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 416 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 417 {
 418   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
 419   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 420   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 421   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 422   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 423   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 424   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_SIGN_OPT)|(1<<CGEN_HW_UNSIGNED), { (1<<MACH_BASE) } } },
 425   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 426   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 427   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
 428   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
 429   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
 430 /* start-sanitize-m32rx */
 431   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_M32RX) } } },
 432 /* end-sanitize-m32rx */
 433   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 434   { HW_H_PSW, & HW_ENT (HW_H_PSW + 1), "h-psw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
 435   { HW_H_BPSW, & HW_ENT (HW_H_BPSW + 1), "h-bpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 436   { HW_H_BBPSW, & HW_ENT (HW_H_BBPSW + 1), "h-bbpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 437   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 438   { 0 }
 439 };
 440
 441 /* The operand table.  */
 442
 443 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 444 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 445
 446 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 447 {
 448 /* pc: program counter */
 449   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 450     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 451 /* sr: source register */
 452   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 453     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 454 /* dr: destination register */
 455   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 456     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 457 /* src1: source register 1 */
 458   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 459     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 460 /* src2: source register 2 */
 461   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 462     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 463 /* scr: source control register */
 464   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 465     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 466 /* dcr: destination control register */
 467   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 468     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 469 /* simm8: 8 bit signed immediate */
 470   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 471     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 472 /* simm16: 16 bit signed immediate */
 473   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 474     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 475 /* uimm4: 4 bit trap number */
 476   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 477     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 478 /* uimm5: 5 bit shift count */
 479   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 480     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 481 /* uimm16: 16 bit unsigned immediate */
 482   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 483     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 484 /* start-sanitize-m32rx */
 485 /* imm1: 1 bit immediate */
 486   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 487     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 488 /* end-sanitize-m32rx */
 489 /* start-sanitize-m32rx */
 490 /* accd: accumulator destination register */
 491   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 492     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 493 /* end-sanitize-m32rx */
 494 /* start-sanitize-m32rx */
 495 /* accs: accumulator source register */
 496   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 497     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 498 /* end-sanitize-m32rx */
 499 /* start-sanitize-m32rx */
 500 /* acc: accumulator reg (d) */
 501   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 502     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 503 /* end-sanitize-m32rx */
 504 /* hash: # prefix */
 505   { "hash", & HW_ENT (HW_H_SINT), 0, 0,
 506     { 0, 0, { 0 } }  },
 507 /* hi16: high 16 bit immediate, sign optional */
 508   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 509     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 510 /* slo16: 16 bit signed immediate, for low() */
 511   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 512     { 0, 0, { 0 } }  },
 513 /* ulo16: 16 bit unsigned immediate, for low() */
 514   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 515     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 516 /* uimm24: 24 bit address */
 517   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 518     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 519 /* disp8: 8 bit displacement */
 520   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 521     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 522 /* disp16: 16 bit displacement */
 523   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 524     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 525 /* disp24: 24 bit displacement */
 526   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 527     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 528 /* condbit: condition bit */
 529   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 530     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 531 /* accum: accumulator */
 532   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 533     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 534 };
 535
 536 /* Operand references.  */
 537
 538 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 539 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 540
 541 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 542   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 543   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 544   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 545   { 0 }
 546 };
 547
 548 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
 549   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 550   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 551   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 552   { 0 }
 553 };
 554
 555 static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
 556   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 557   { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 558   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 559   { 0 }
 560 };
 561
 562 static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
 563   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 564   { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 565   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 566   { 0 }
 567 };
 568
 569 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 570   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 571   { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 572   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 573   { 0 }
 574 };
 575
 576 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
 577   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 578   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 579   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 580   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 581   { 0 }
 582 };
 583
 584 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
 585   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 586   { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 587   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 588   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 589   { 0 }
 590 };
 591
 592 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
 593   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 594   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 595   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 596   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 597   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 598   { 0 }
 599 };
 600
 601 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
 602   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 603   { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 604   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 605   { 0 }
 606 };
 607
 608 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
 609   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 610   { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 611   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 612   { 0 }
 613 };
 614
 615 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
 616   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 617   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 618   { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 619   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 620   { 0 }
 621 };
 622
 623 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
 624   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 625   { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 626   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 627   { 0 }
 628 };
 629
 630 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
 631   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 632   { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 633   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 634   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 635   { 0 }
 636 };
 637
 638 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
 639   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 640   { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 641   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 642   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 643   { 0 }
 644 };
 645
 646 /* start-sanitize-m32rx */
 647 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
 648   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 649   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 650   { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 651   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 652   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 653   { 0 }
 654 };
 655
 656 /* end-sanitize-m32rx */
 657 /* start-sanitize-m32rx */
 658 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
 659   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 660   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 661   { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 662   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 663   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 664   { 0 }
 665 };
 666
 667 /* end-sanitize-m32rx */
 668 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
 669   { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 670   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 671   { 0 }
 672 };
 673
 674 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
 675   { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 676   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 677   { 0 }
 678 };
 679
 680 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 681   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 682   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 683   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 684   { 0 }
 685 };
 686
 687 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 688   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 689   { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 690   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 691   { 0 }
 692 };
 693
 694 /* start-sanitize-m32rx */
 695 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
 696   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 697   { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 698   { 0 }
 699 };
 700
 701 /* end-sanitize-m32rx */
 702 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
 703   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 704   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 705   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 706   { 0 }
 707 };
 708
 709 /* start-sanitize-m32rx */
 710 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
 711   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
 712   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 713   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 714   { 0 }
 715 };
 716
 717 /* end-sanitize-m32rx */
 718 static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
 719   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 720   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 721   { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 722   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 723   { 0 }
 724 };
 725
 726 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
 727   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 728   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 729   { 0 }
 730 };
 731
 732 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
 733   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 734   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 735   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 736   { 0 }
 737 };
 738
 739 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
 740   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 741   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 742   { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 743   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 744   { 0 }
 745 };
 746
 747 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
 748   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 749   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 750   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 751   { 0 }
 752 };
 753
 754 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
 755   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 756   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 757   { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 758   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 759   { 0 }
 760 };
 761
 762 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
 763   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 764   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 765   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 766   { 0 }
 767 };
 768
 769 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
 770   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 771   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 772   { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 773   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 774   { 0 }
 775 };
 776
 777 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
 778   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 779   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 780   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 781   { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 782   { 0 }
 783 };
 784
 785 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
 786   { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
 787   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 788   { 0 }
 789 };
 790
 791 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
 792   { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 793   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 794   { 0 }
 795 };
 796
 797 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
 798   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 799   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 800   { 0 }
 801 };
 802
 803 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
 804   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 805   { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 806   { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
 807   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 808   { 0 }
 809 };
 810
 811 static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
 812   { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 813   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 814   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 815   { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 816   { 0 }
 817 };
 818
 819 /* start-sanitize-m32rx */
 820 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
 821   { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 822   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 823   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 824   { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 825   { 0 }
 826 };
 827
 828 /* end-sanitize-m32rx */
 829 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
 830   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 831   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 832   { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 833   { 0 }
 834 };
 835
 836 /* start-sanitize-m32rx */
 837 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
 838   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 839   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 840   { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 841   { 0 }
 842 };
 843
 844 /* end-sanitize-m32rx */
 845 static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
 846   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 847   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 848   { 0 }
 849 };
 850
 851 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
 852   { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 853   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 854   { 0 }
 855 };
 856
 857 /* start-sanitize-m32rx */
 858 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
 859   { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 860   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 861   { 0 }
 862 };
 863
 864 /* end-sanitize-m32rx */
 865 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
 866   { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 867   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 868   { 0 }
 869 };
 870
 871 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
 872   { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 873   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 874   { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 875   { 0 }
 876 };
 877
 878 /* start-sanitize-m32rx */
 879 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
 880   { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 881   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 882   { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 883   { 0 }
 884 };
 885
 886 /* end-sanitize-m32rx */
 887 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
 888   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 889   { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 890   { 0 }
 891 };
 892
 893 static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
 894   { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 895   { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 896   { 0 }
 897 };
 898
 899 /* start-sanitize-m32rx */
 900 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
 901   { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 902   { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 903   { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 904   { 0 }
 905 };
 906
 907 /* end-sanitize-m32rx */
 908 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
 909   { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
 910   { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
 911   { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
 912   { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
 913   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 914   { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
 915   { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
 916   { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
 917   { 0 }
 918 };
 919
 920 static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
 921   { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
 922   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 923   { 0 }
 924 };
 925
 926 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
 927   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 928   { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 929   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 930   { 0 }
 931 };
 932
 933 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
 934   { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 935   { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 936   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 937   { 0 }
 938 };
 939
 940 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
 941   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 942   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 943   { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 944   { 0 }
 945 };
 946
 947 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
 948   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 949   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 950   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 951   { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 952   { 0 }
 953 };
 954
 955 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
 956   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 957   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 958   { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 959   { 0 }
 960 };
 961
 962 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
 963   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 964   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 965   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 966   { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 967   { 0 }
 968 };
 969
 970 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
 971   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 972   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 973   { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 974   { 0 }
 975 };
 976
 977 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
 978   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 979   { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 980   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 981   { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 982   { 0 }
 983 };
 984
 985 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
 986   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 987   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 988   { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 989   { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 990   { 0 }
 991 };
 992
 993 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
 994   { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
 995   { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 996   { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
 997   { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
 998   { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
 999   { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
1000   { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
1001   { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
1002   { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
1003   { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
1004   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
1005   { 0 }
1006 };
1007
1008 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
1009   { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
1010   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
1011   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
1012   { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
1013   { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
1014   { 0 }
1015 };
1016
1017 /* start-sanitize-m32rx */
1018 static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
1019   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
1020   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
1021   { 0 }
1022 };
1023
1024 /* end-sanitize-m32rx */
1025 /* start-sanitize-m32rx */
1026 static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
1027   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
1028   { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
1029   { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
1030   { 0 }
1031 };
1032
1033 /* end-sanitize-m32rx */
1034 /* start-sanitize-m32rx */
1035 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
1036   { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
1037   { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
1038   { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
1039   { 0 }
1040 };
1041
1042 /* end-sanitize-m32rx */
1043 /* start-sanitize-m32rx */
1044 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
1045   { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
1046   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
1047   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
1048   { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
1049   { 0 }
1050 };
1051
1052 /* end-sanitize-m32rx */
1053 /* start-sanitize-m32rx */
1054 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
1055   { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
1056   { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
1057   { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
1058   { 0 }
1059 };
1060
1061 /* end-sanitize-m32rx */
1062 /* start-sanitize-m32rx */
1063 static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
1064   { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
1065   { 0 }
1066 };
1067
1068 /* end-sanitize-m32rx */
1069 #undef INPUT
1070 #undef OUTPUT
1071
1072 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1073 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1074 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1075
1076 /* The instruction table.
1077    This is currently non-static because the simulator accesses it
1078    directly.  */
1079
1080 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1081 {
1082   /* Special null first entry.
1083      A `num' value of zero is thus invalid.
1084      Also, the special `invalid' insn resides here.  */
1085   { { 0 }, 0 },
1086 /* add $dr,$sr */
1087   {
1088     { 1, 1, 1, 1 },
1089     M32R_INSN_ADD, "add", "add",
1090     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1091     { 16, 16, 0xf0f0 }, 0xa0,
1092     (PTR) & fmt_add_ops[0],
1093     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1094   },
1095 /* add3 $dr,$sr,$hash$slo16 */
1096   {
1097     { 1, 1, 1, 1 },
1098     M32R_INSN_ADD3, "add3", "add3",
1099     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
1100     { 32, 32, 0xf0f00000 }, 0x80a00000,
1101     (PTR) & fmt_add3_ops[0],
1102     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1103   },
1104 /* and $dr,$sr */
1105   {
1106     { 1, 1, 1, 1 },
1107     M32R_INSN_AND, "and", "and",
1108     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1109     { 16, 16, 0xf0f0 }, 0xc0,
1110     (PTR) & fmt_add_ops[0],
1111     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1112   },
1113 /* and3 $dr,$sr,$uimm16 */
1114   {
1115     { 1, 1, 1, 1 },
1116     M32R_INSN_AND3, "and3", "and3",
1117     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1118     { 32, 32, 0xf0f00000 }, 0x80c00000,
1119     (PTR) & fmt_and3_ops[0],
1120     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1121   },
1122 /* or $dr,$sr */
1123   {
1124     { 1, 1, 1, 1 },
1125     M32R_INSN_OR, "or", "or",
1126     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1127     { 16, 16, 0xf0f0 }, 0xe0,
1128     (PTR) & fmt_add_ops[0],
1129     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1130   },
1131 /* or3 $dr,$sr,$hash$ulo16 */
1132   {
1133     { 1, 1, 1, 1 },
1134     M32R_INSN_OR3, "or3", "or3",
1135     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
1136     { 32, 32, 0xf0f00000 }, 0x80e00000,
1137     (PTR) & fmt_or3_ops[0],
1138     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1139   },
1140 /* xor $dr,$sr */
1141   {
1142     { 1, 1, 1, 1 },
1143     M32R_INSN_XOR, "xor", "xor",
1144     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1145     { 16, 16, 0xf0f0 }, 0xd0,
1146     (PTR) & fmt_add_ops[0],
1147     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1148   },
1149 /* xor3 $dr,$sr,$uimm16 */
1150   {
1151     { 1, 1, 1, 1 },
1152     M32R_INSN_XOR3, "xor3", "xor3",
1153     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1154     { 32, 32, 0xf0f00000 }, 0x80d00000,
1155     (PTR) & fmt_and3_ops[0],
1156     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1157   },
1158 /* addi $dr,$simm8 */
1159   {
1160     { 1, 1, 1, 1 },
1161     M32R_INSN_ADDI, "addi", "addi",
1162     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1163     { 16, 16, 0xf000 }, 0x4000,
1164     (PTR) & fmt_addi_ops[0],
1165     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1166   },
1167 /* addv $dr,$sr */
1168   {
1169     { 1, 1, 1, 1 },
1170     M32R_INSN_ADDV, "addv", "addv",
1171     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1172     { 16, 16, 0xf0f0 }, 0x80,
1173     (PTR) & fmt_addv_ops[0],
1174     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1175   },
1176 /* addv3 $dr,$sr,$simm16 */
1177   {
1178     { 1, 1, 1, 1 },
1179     M32R_INSN_ADDV3, "addv3", "addv3",
1180     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
1181     { 32, 32, 0xf0f00000 }, 0x80800000,
1182     (PTR) & fmt_addv3_ops[0],
1183     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1184   },
1185 /* addx $dr,$sr */
1186   {
1187     { 1, 1, 1, 1 },
1188     M32R_INSN_ADDX, "addx", "addx",
1189     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1190     { 16, 16, 0xf0f0 }, 0x90,
1191     (PTR) & fmt_addx_ops[0],
1192     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1193   },
1194 /* bc.s $disp8 */
1195   {
1196     { 1, 1, 1, 1 },
1197     M32R_INSN_BC8, "bc8", "bc.s",
1198     { { MNEM, ' ', OP (DISP8), 0 } },
1199     { 16, 16, 0xff00 }, 0x7c00,
1200     (PTR) & fmt_bc8_ops[0],
1201     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
1202   },
1203 /* bc.l $disp24 */
1204   {
1205     { 1, 1, 1, 1 },
1206     M32R_INSN_BC24, "bc24", "bc.l",
1207     { { MNEM, ' ', OP (DISP24), 0 } },
1208     { 32, 32, 0xff000000 }, 0xfc000000,
1209     (PTR) & fmt_bc24_ops[0],
1210     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1211   },
1212 /* beq $src1,$src2,$disp16 */
1213   {
1214     { 1, 1, 1, 1 },
1215     M32R_INSN_BEQ, "beq", "beq",
1216     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1217     { 32, 32, 0xf0f00000 }, 0xb0000000,
1218     (PTR) & fmt_beq_ops[0],
1219     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1220   },
1221 /* beqz $src2,$disp16 */
1222   {
1223     { 1, 1, 1, 1 },
1224     M32R_INSN_BEQZ, "beqz", "beqz",
1225     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1226     { 32, 32, 0xfff00000 }, 0xb0800000,
1227     (PTR) & fmt_beqz_ops[0],
1228     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1229   },
1230 /* bgez $src2,$disp16 */
1231   {
1232     { 1, 1, 1, 1 },
1233     M32R_INSN_BGEZ, "bgez", "bgez",
1234     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1235     { 32, 32, 0xfff00000 }, 0xb0b00000,
1236     (PTR) & fmt_beqz_ops[0],
1237     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1238   },
1239 /* bgtz $src2,$disp16 */
1240   {
1241     { 1, 1, 1, 1 },
1242     M32R_INSN_BGTZ, "bgtz", "bgtz",
1243     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1244     { 32, 32, 0xfff00000 }, 0xb0d00000,
1245     (PTR) & fmt_beqz_ops[0],
1246     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1247   },
1248 /* blez $src2,$disp16 */
1249   {
1250     { 1, 1, 1, 1 },
1251     M32R_INSN_BLEZ, "blez", "blez",
1252     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1253     { 32, 32, 0xfff00000 }, 0xb0c00000,
1254     (PTR) & fmt_beqz_ops[0],
1255     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1256   },
1257 /* bltz $src2,$disp16 */
1258   {
1259     { 1, 1, 1, 1 },
1260     M32R_INSN_BLTZ, "bltz", "bltz",
1261     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1262     { 32, 32, 0xfff00000 }, 0xb0a00000,
1263     (PTR) & fmt_beqz_ops[0],
1264     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1265   },
1266 /* bnez $src2,$disp16 */
1267   {
1268     { 1, 1, 1, 1 },
1269     M32R_INSN_BNEZ, "bnez", "bnez",
1270     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1271     { 32, 32, 0xfff00000 }, 0xb0900000,
1272     (PTR) & fmt_beqz_ops[0],
1273     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1274   },
1275 /* bl.s $disp8 */
1276   {
1277     { 1, 1, 1, 1 },
1278     M32R_INSN_BL8, "bl8", "bl.s",
1279     { { MNEM, ' ', OP (DISP8), 0 } },
1280     { 16, 16, 0xff00 }, 0x7e00,
1281     (PTR) & fmt_bl8_ops[0],
1282     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1283   },
1284 /* bl.l $disp24 */
1285   {
1286     { 1, 1, 1, 1 },
1287     M32R_INSN_BL24, "bl24", "bl.l",
1288     { { MNEM, ' ', OP (DISP24), 0 } },
1289     { 32, 32, 0xff000000 }, 0xfe000000,
1290     (PTR) & fmt_bl24_ops[0],
1291     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1292   },
1293 /* start-sanitize-m32rx */
1294 /* bcl.s $disp8 */
1295   {
1296     { 1, 1, 1, 1 },
1297     M32R_INSN_BCL8, "bcl8", "bcl.s",
1298     { { MNEM, ' ', OP (DISP8), 0 } },
1299     { 16, 16, 0xff00 }, 0x7800,
1300     (PTR) & fmt_bcl8_ops[0],
1301     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1302   },
1303 /* end-sanitize-m32rx */
1304 /* start-sanitize-m32rx */
1305 /* bcl.l $disp24 */
1306   {
1307     { 1, 1, 1, 1 },
1308     M32R_INSN_BCL24, "bcl24", "bcl.l",
1309     { { MNEM, ' ', OP (DISP24), 0 } },
1310     { 32, 32, 0xff000000 }, 0xf8000000,
1311     (PTR) & fmt_bcl24_ops[0],
1312     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1313   },
1314 /* end-sanitize-m32rx */
1315 /* bnc.s $disp8 */
1316   {
1317     { 1, 1, 1, 1 },
1318     M32R_INSN_BNC8, "bnc8", "bnc.s",
1319     { { MNEM, ' ', OP (DISP8), 0 } },
1320     { 16, 16, 0xff00 }, 0x7d00,
1321     (PTR) & fmt_bc8_ops[0],
1322     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
1323   },
1324 /* bnc.l $disp24 */
1325   {
1326     { 1, 1, 1, 1 },
1327     M32R_INSN_BNC24, "bnc24", "bnc.l",
1328     { { MNEM, ' ', OP (DISP24), 0 } },
1329     { 32, 32, 0xff000000 }, 0xfd000000,
1330     (PTR) & fmt_bc24_ops[0],
1331     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1332   },
1333 /* bne $src1,$src2,$disp16 */
1334   {
1335     { 1, 1, 1, 1 },
1336     M32R_INSN_BNE, "bne", "bne",
1337     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1338     { 32, 32, 0xf0f00000 }, 0xb0100000,
1339     (PTR) & fmt_beq_ops[0],
1340     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1341   },
1342 /* bra.s $disp8 */
1343   {
1344     { 1, 1, 1, 1 },
1345     M32R_INSN_BRA8, "bra8", "bra.s",
1346     { { MNEM, ' ', OP (DISP8), 0 } },
1347     { 16, 16, 0xff00 }, 0x7f00,
1348     (PTR) & fmt_bra8_ops[0],
1349     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1350   },
1351 /* bra.l $disp24 */
1352   {
1353     { 1, 1, 1, 1 },
1354     M32R_INSN_BRA24, "bra24", "bra.l",
1355     { { MNEM, ' ', OP (DISP24), 0 } },
1356     { 32, 32, 0xff000000 }, 0xff000000,
1357     (PTR) & fmt_bra24_ops[0],
1358     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
1359   },
1360 /* start-sanitize-m32rx */
1361 /* bncl.s $disp8 */
1362   {
1363     { 1, 1, 1, 1 },
1364     M32R_INSN_BNCL8, "bncl8", "bncl.s",
1365     { { MNEM, ' ', OP (DISP8), 0 } },
1366     { 16, 16, 0xff00 }, 0x7900,
1367     (PTR) & fmt_bcl8_ops[0],
1368     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1369   },
1370 /* end-sanitize-m32rx */
1371 /* start-sanitize-m32rx */
1372 /* bncl.l $disp24 */
1373   {
1374     { 1, 1, 1, 1 },
1375     M32R_INSN_BNCL24, "bncl24", "bncl.l",
1376     { { MNEM, ' ', OP (DISP24), 0 } },
1377     { 32, 32, 0xff000000 }, 0xf9000000,
1378     (PTR) & fmt_bcl24_ops[0],
1379     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1380   },
1381 /* end-sanitize-m32rx */
1382 /* cmp $src1,$src2 */
1383   {
1384     { 1, 1, 1, 1 },
1385     M32R_INSN_CMP, "cmp", "cmp",
1386     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1387     { 16, 16, 0xf0f0 }, 0x40,
1388     (PTR) & fmt_cmp_ops[0],
1389     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1390   },
1391 /* cmpi $src2,$simm16 */
1392   {
1393     { 1, 1, 1, 1 },
1394     M32R_INSN_CMPI, "cmpi", "cmpi",
1395     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1396     { 32, 32, 0xfff00000 }, 0x80400000,
1397     (PTR) & fmt_cmpi_ops[0],
1398     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1399   },
1400 /* cmpu $src1,$src2 */
1401   {
1402     { 1, 1, 1, 1 },
1403     M32R_INSN_CMPU, "cmpu", "cmpu",
1404     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1405     { 16, 16, 0xf0f0 }, 0x50,
1406     (PTR) & fmt_cmp_ops[0],
1407     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1408   },
1409 /* cmpui $src2,$simm16 */
1410   {
1411     { 1, 1, 1, 1 },
1412     M32R_INSN_CMPUI, "cmpui", "cmpui",
1413     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1414     { 32, 32, 0xfff00000 }, 0x80500000,
1415     (PTR) & fmt_cmpi_ops[0],
1416     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1417   },
1418 /* start-sanitize-m32rx */
1419 /* cmpeq $src1,$src2 */
1420   {
1421     { 1, 1, 1, 1 },
1422     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
1423     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1424     { 16, 16, 0xf0f0 }, 0x60,
1425     (PTR) & fmt_cmp_ops[0],
1426     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1427   },
1428 /* end-sanitize-m32rx */
1429 /* start-sanitize-m32rx */
1430 /* cmpz $src2 */
1431   {
1432     { 1, 1, 1, 1 },
1433     M32R_INSN_CMPZ, "cmpz", "cmpz",
1434     { { MNEM, ' ', OP (SRC2), 0 } },
1435     { 16, 16, 0xfff0 }, 0x70,
1436     (PTR) & fmt_cmpz_ops[0],
1437     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1438   },
1439 /* end-sanitize-m32rx */
1440 /* div $dr,$sr */
1441   {
1442     { 1, 1, 1, 1 },
1443     M32R_INSN_DIV, "div", "div",
1444     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1445     { 32, 32, 0xf0f0ffff }, 0x90000000,
1446     (PTR) & fmt_div_ops[0],
1447     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1448   },
1449 /* divu $dr,$sr */
1450   {
1451     { 1, 1, 1, 1 },
1452     M32R_INSN_DIVU, "divu", "divu",
1453     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1454     { 32, 32, 0xf0f0ffff }, 0x90100000,
1455     (PTR) & fmt_div_ops[0],
1456     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1457   },
1458 /* rem $dr,$sr */
1459   {
1460     { 1, 1, 1, 1 },
1461     M32R_INSN_REM, "rem", "rem",
1462     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1463     { 32, 32, 0xf0f0ffff }, 0x90200000,
1464     (PTR) & fmt_div_ops[0],
1465     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1466   },
1467 /* remu $dr,$sr */
1468   {
1469     { 1, 1, 1, 1 },
1470     M32R_INSN_REMU, "remu", "remu",
1471     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1472     { 32, 32, 0xf0f0ffff }, 0x90300000,
1473     (PTR) & fmt_div_ops[0],
1474     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1475   },
1476 /* start-sanitize-m32rx */
1477 /* divh $dr,$sr */
1478   {
1479     { 1, 1, 1, 1 },
1480     M32R_INSN_DIVH, "divh", "divh",
1481     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1482     { 32, 32, 0xf0f0ffff }, 0x90000010,
1483     (PTR) & fmt_div_ops[0],
1484     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1485   },
1486 /* end-sanitize-m32rx */
1487 /* start-sanitize-m32rx */
1488 /* jc $sr */
1489   {
1490     { 1, 1, 1, 1 },
1491     M32R_INSN_JC, "jc", "jc",
1492     { { MNEM, ' ', OP (SR), 0 } },
1493     { 16, 16, 0xfff0 }, 0x1cc0,
1494     (PTR) & fmt_jc_ops[0],
1495     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1496   },
1497 /* end-sanitize-m32rx */
1498 /* start-sanitize-m32rx */
1499 /* jnc $sr */
1500   {
1501     { 1, 1, 1, 1 },
1502     M32R_INSN_JNC, "jnc", "jnc",
1503     { { MNEM, ' ', OP (SR), 0 } },
1504     { 16, 16, 0xfff0 }, 0x1dc0,
1505     (PTR) & fmt_jc_ops[0],
1506     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1507   },
1508 /* end-sanitize-m32rx */
1509 /* jl $sr */
1510   {
1511     { 1, 1, 1, 1 },
1512     M32R_INSN_JL, "jl", "jl",
1513     { { MNEM, ' ', OP (SR), 0 } },
1514     { 16, 16, 0xfff0 }, 0x1ec0,
1515     (PTR) & fmt_jl_ops[0],
1516     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1517   },
1518 /* jmp $sr */
1519   {
1520     { 1, 1, 1, 1 },
1521     M32R_INSN_JMP, "jmp", "jmp",
1522     { { MNEM, ' ', OP (SR), 0 } },
1523     { 16, 16, 0xfff0 }, 0x1fc0,
1524     (PTR) & fmt_jmp_ops[0],
1525     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1526   },
1527 /* ld $dr,@$sr */
1528   {
1529     { 1, 1, 1, 1 },
1530     M32R_INSN_LD, "ld", "ld",
1531     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1532     { 16, 16, 0xf0f0 }, 0x20c0,
1533     (PTR) & fmt_ld_ops[0],
1534     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1535   },
1536 /* ld $dr,@($slo16,$sr) */
1537   {
1538     { 1, 1, 1, 1 },
1539     M32R_INSN_LD_D, "ld-d", "ld",
1540     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1541     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1542     (PTR) & fmt_ld_d_ops[0],
1543     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1544   },
1545 /* ldb $dr,@$sr */
1546   {
1547     { 1, 1, 1, 1 },
1548     M32R_INSN_LDB, "ldb", "ldb",
1549     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1550     { 16, 16, 0xf0f0 }, 0x2080,
1551     (PTR) & fmt_ldb_ops[0],
1552     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1553   },
1554 /* ldb $dr,@($slo16,$sr) */
1555   {
1556     { 1, 1, 1, 1 },
1557     M32R_INSN_LDB_D, "ldb-d", "ldb",
1558     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1559     { 32, 32, 0xf0f00000 }, 0xa0800000,
1560     (PTR) & fmt_ldb_d_ops[0],
1561     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1562   },
1563 /* ldh $dr,@$sr */
1564   {
1565     { 1, 1, 1, 1 },
1566     M32R_INSN_LDH, "ldh", "ldh",
1567     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1568     { 16, 16, 0xf0f0 }, 0x20a0,
1569     (PTR) & fmt_ldh_ops[0],
1570     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1571   },
1572 /* ldh $dr,@($slo16,$sr) */
1573   {
1574     { 1, 1, 1, 1 },
1575     M32R_INSN_LDH_D, "ldh-d", "ldh",
1576     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1577     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1578     (PTR) & fmt_ldh_d_ops[0],
1579     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1580   },
1581 /* ldub $dr,@$sr */
1582   {
1583     { 1, 1, 1, 1 },
1584     M32R_INSN_LDUB, "ldub", "ldub",
1585     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1586     { 16, 16, 0xf0f0 }, 0x2090,
1587     (PTR) & fmt_ldb_ops[0],
1588     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1589   },
1590 /* ldub $dr,@($slo16,$sr) */
1591   {
1592     { 1, 1, 1, 1 },
1593     M32R_INSN_LDUB_D, "ldub-d", "ldub",
1594     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1595     { 32, 32, 0xf0f00000 }, 0xa0900000,
1596     (PTR) & fmt_ldb_d_ops[0],
1597     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1598   },
1599 /* lduh $dr,@$sr */
1600   {
1601     { 1, 1, 1, 1 },
1602     M32R_INSN_LDUH, "lduh", "lduh",
1603     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1604     { 16, 16, 0xf0f0 }, 0x20b0,
1605     (PTR) & fmt_ldh_ops[0],
1606     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1607   },
1608 /* lduh $dr,@($slo16,$sr) */
1609   {
1610     { 1, 1, 1, 1 },
1611     M32R_INSN_LDUH_D, "lduh-d", "lduh",
1612     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1613     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1614     (PTR) & fmt_ldh_d_ops[0],
1615     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1616   },
1617 /* ld $dr,@$sr+ */
1618   {
1619     { 1, 1, 1, 1 },
1620     M32R_INSN_LD_PLUS, "ld-plus", "ld",
1621     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
1622     { 16, 16, 0xf0f0 }, 0x20e0,
1623     (PTR) & fmt_ld_plus_ops[0],
1624     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1625   },
1626 /* ld24 $dr,$uimm24 */
1627   {
1628     { 1, 1, 1, 1 },
1629     M32R_INSN_LD24, "ld24", "ld24",
1630     { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
1631     { 32, 32, 0xf0000000 }, 0xe0000000,
1632     (PTR) & fmt_ld24_ops[0],
1633     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1634   },
1635 /* ldi8 $dr,$simm8 */
1636   {
1637     { 1, 1, 1, 1 },
1638     M32R_INSN_LDI8, "ldi8", "ldi8",
1639     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1640     { 16, 16, 0xf000 }, 0x6000,
1641     (PTR) & fmt_ldi8_ops[0],
1642     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1643   },
1644 /* ldi16 $dr,$hash$slo16 */
1645   {
1646     { 1, 1, 1, 1 },
1647     M32R_INSN_LDI16, "ldi16", "ldi16",
1648     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1649     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1650     (PTR) & fmt_ldi16_ops[0],
1651     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
1652   },
1653 /* lock $dr,@$sr */
1654   {
1655     { 1, 1, 1, 1 },
1656     M32R_INSN_LOCK, "lock", "lock",
1657     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1658     { 16, 16, 0xf0f0 }, 0x20d0,
1659     (PTR) & fmt_lock_ops[0],
1660     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1661   },
1662 /* machi $src1,$src2 */
1663   {
1664     { 1, 1, 1, 1 },
1665     M32R_INSN_MACHI, "machi", "machi",
1666     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1667     { 16, 16, 0xf0f0 }, 0x3040,
1668     (PTR) & fmt_machi_ops[0],
1669     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1670   },
1671 /* start-sanitize-m32rx */
1672 /* machi $src1,$src2,$acc */
1673   {
1674     { 1, 1, 1, 1 },
1675     M32R_INSN_MACHI_A, "machi-a", "machi",
1676     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1677     { 16, 16, 0xf070 }, 0x3040,
1678     (PTR) & fmt_machi_a_ops[0],
1679     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1680   },
1681 /* end-sanitize-m32rx */
1682 /* maclo $src1,$src2 */
1683   {
1684     { 1, 1, 1, 1 },
1685     M32R_INSN_MACLO, "maclo", "maclo",
1686     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1687     { 16, 16, 0xf0f0 }, 0x3050,
1688     (PTR) & fmt_machi_ops[0],
1689     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1690   },
1691 /* start-sanitize-m32rx */
1692 /* maclo $src1,$src2,$acc */
1693   {
1694     { 1, 1, 1, 1 },
1695     M32R_INSN_MACLO_A, "maclo-a", "maclo",
1696     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1697     { 16, 16, 0xf070 }, 0x3050,
1698     (PTR) & fmt_machi_a_ops[0],
1699     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1700   },
1701 /* end-sanitize-m32rx */
1702 /* macwhi $src1,$src2 */
1703   {
1704     { 1, 1, 1, 1 },
1705     M32R_INSN_MACWHI, "macwhi", "macwhi",
1706     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1707     { 16, 16, 0xf0f0 }, 0x3060,
1708     (PTR) & fmt_machi_ops[0],
1709     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1710   },
1711 /* start-sanitize-m32rx */
1712 /* macwhi $src1,$src2,$acc */
1713   {
1714     { 1, 1, 1, 1 },
1715     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
1716     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1717     { 16, 16, 0xf070 }, 0x3060,
1718     (PTR) & fmt_machi_a_ops[0],
1719     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1720   },
1721 /* end-sanitize-m32rx */
1722 /* macwlo $src1,$src2 */
1723   {
1724     { 1, 1, 1, 1 },
1725     M32R_INSN_MACWLO, "macwlo", "macwlo",
1726     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1727     { 16, 16, 0xf0f0 }, 0x3070,
1728     (PTR) & fmt_machi_ops[0],
1729     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1730   },
1731 /* start-sanitize-m32rx */
1732 /* macwlo $src1,$src2,$acc */
1733   {
1734     { 1, 1, 1, 1 },
1735     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
1736     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1737     { 16, 16, 0xf070 }, 0x3070,
1738     (PTR) & fmt_machi_a_ops[0],
1739     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1740   },
1741 /* end-sanitize-m32rx */
1742 /* mul $dr,$sr */
1743   {
1744     { 1, 1, 1, 1 },
1745     M32R_INSN_MUL, "mul", "mul",
1746     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1747     { 16, 16, 0xf0f0 }, 0x1060,
1748     (PTR) & fmt_add_ops[0],
1749     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } }
1750   },
1751 /* mulhi $src1,$src2 */
1752   {
1753     { 1, 1, 1, 1 },
1754     M32R_INSN_MULHI, "mulhi", "mulhi",
1755     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1756     { 16, 16, 0xf0f0 }, 0x3000,
1757     (PTR) & fmt_mulhi_ops[0],
1758     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1759   },
1760 /* start-sanitize-m32rx */
1761 /* mulhi $src1,$src2,$acc */
1762   {
1763     { 1, 1, 1, 1 },
1764     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
1765     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1766     { 16, 16, 0xf070 }, 0x3000,
1767     (PTR) & fmt_mulhi_a_ops[0],
1768     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1769   },
1770 /* end-sanitize-m32rx */
1771 /* mullo $src1,$src2 */
1772   {
1773     { 1, 1, 1, 1 },
1774     M32R_INSN_MULLO, "mullo", "mullo",
1775     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1776     { 16, 16, 0xf0f0 }, 0x3010,
1777     (PTR) & fmt_mulhi_ops[0],
1778     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1779   },
1780 /* start-sanitize-m32rx */
1781 /* mullo $src1,$src2,$acc */
1782   {
1783     { 1, 1, 1, 1 },
1784     M32R_INSN_MULLO_A, "mullo-a", "mullo",
1785     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1786     { 16, 16, 0xf070 }, 0x3010,
1787     (PTR) & fmt_mulhi_a_ops[0],
1788     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1789   },
1790 /* end-sanitize-m32rx */
1791 /* mulwhi $src1,$src2 */
1792   {
1793     { 1, 1, 1, 1 },
1794     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
1795     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1796     { 16, 16, 0xf0f0 }, 0x3020,
1797     (PTR) & fmt_mulhi_ops[0],
1798     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1799   },
1800 /* start-sanitize-m32rx */
1801 /* mulwhi $src1,$src2,$acc */
1802   {
1803     { 1, 1, 1, 1 },
1804     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
1805     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1806     { 16, 16, 0xf070 }, 0x3020,
1807     (PTR) & fmt_mulhi_a_ops[0],
1808     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1809   },
1810 /* end-sanitize-m32rx */
1811 /* mulwlo $src1,$src2 */
1812   {
1813     { 1, 1, 1, 1 },
1814     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
1815     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1816     { 16, 16, 0xf0f0 }, 0x3030,
1817     (PTR) & fmt_mulhi_ops[0],
1818     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1819   },
1820 /* start-sanitize-m32rx */
1821 /* mulwlo $src1,$src2,$acc */
1822   {
1823     { 1, 1, 1, 1 },
1824     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
1825     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1826     { 16, 16, 0xf070 }, 0x3030,
1827     (PTR) & fmt_mulhi_a_ops[0],
1828     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1829   },
1830 /* end-sanitize-m32rx */
1831 /* mv $dr,$sr */
1832   {
1833     { 1, 1, 1, 1 },
1834     M32R_INSN_MV, "mv", "mv",
1835     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1836     { 16, 16, 0xf0f0 }, 0x1080,
1837     (PTR) & fmt_mv_ops[0],
1838     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1839   },
1840 /* mvfachi $dr */
1841   {
1842     { 1, 1, 1, 1 },
1843     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
1844     { { MNEM, ' ', OP (DR), 0 } },
1845     { 16, 16, 0xf0ff }, 0x50f0,
1846     (PTR) & fmt_mvfachi_ops[0],
1847     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1848   },
1849 /* start-sanitize-m32rx */
1850 /* mvfachi $dr,$accs */
1851   {
1852     { 1, 1, 1, 1 },
1853     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
1854     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1855     { 16, 16, 0xf0f3 }, 0x50f0,
1856     (PTR) & fmt_mvfachi_a_ops[0],
1857     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1858   },
1859 /* end-sanitize-m32rx */
1860 /* mvfaclo $dr */
1861   {
1862     { 1, 1, 1, 1 },
1863     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
1864     { { MNEM, ' ', OP (DR), 0 } },
1865     { 16, 16, 0xf0ff }, 0x50f1,
1866     (PTR) & fmt_mvfachi_ops[0],
1867     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1868   },
1869 /* start-sanitize-m32rx */
1870 /* mvfaclo $dr,$accs */
1871   {
1872     { 1, 1, 1, 1 },
1873     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
1874     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1875     { 16, 16, 0xf0f3 }, 0x50f1,
1876     (PTR) & fmt_mvfachi_a_ops[0],
1877     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1878   },
1879 /* end-sanitize-m32rx */
1880 /* mvfacmi $dr */
1881   {
1882     { 1, 1, 1, 1 },
1883     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
1884     { { MNEM, ' ', OP (DR), 0 } },
1885     { 16, 16, 0xf0ff }, 0x50f2,
1886     (PTR) & fmt_mvfachi_ops[0],
1887     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1888   },
1889 /* start-sanitize-m32rx */
1890 /* mvfacmi $dr,$accs */
1891   {
1892     { 1, 1, 1, 1 },
1893     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
1894     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1895     { 16, 16, 0xf0f3 }, 0x50f2,
1896     (PTR) & fmt_mvfachi_a_ops[0],
1897     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1898   },
1899 /* end-sanitize-m32rx */
1900 /* mvfc $dr,$scr */
1901   {
1902     { 1, 1, 1, 1 },
1903     M32R_INSN_MVFC, "mvfc", "mvfc",
1904     { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
1905     { 16, 16, 0xf0f0 }, 0x1090,
1906     (PTR) & fmt_mvfc_ops[0],
1907     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1908   },
1909 /* mvtachi $src1 */
1910   {
1911     { 1, 1, 1, 1 },
1912     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
1913     { { MNEM, ' ', OP (SRC1), 0 } },
1914     { 16, 16, 0xf0ff }, 0x5070,
1915     (PTR) & fmt_mvtachi_ops[0],
1916     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1917   },
1918 /* start-sanitize-m32rx */
1919 /* mvtachi $src1,$accs */
1920   {
1921     { 1, 1, 1, 1 },
1922     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
1923     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
1924     { 16, 16, 0xf0f3 }, 0x5070,
1925     (PTR) & fmt_mvtachi_a_ops[0],
1926     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1927   },
1928 /* end-sanitize-m32rx */
1929 /* mvtaclo $src1 */
1930   {
1931     { 1, 1, 1, 1 },
1932     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
1933     { { MNEM, ' ', OP (SRC1), 0 } },
1934     { 16, 16, 0xf0ff }, 0x5071,
1935     (PTR) & fmt_mvtachi_ops[0],
1936     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1937   },
1938 /* start-sanitize-m32rx */
1939 /* mvtaclo $src1,$accs */
1940   {
1941     { 1, 1, 1, 1 },
1942     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
1943     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
1944     { 16, 16, 0xf0f3 }, 0x5071,
1945     (PTR) & fmt_mvtachi_a_ops[0],
1946     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1947   },
1948 /* end-sanitize-m32rx */
1949 /* mvtc $sr,$dcr */
1950   {
1951     { 1, 1, 1, 1 },
1952     M32R_INSN_MVTC, "mvtc", "mvtc",
1953     { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
1954     { 16, 16, 0xf0f0 }, 0x10a0,
1955     (PTR) & fmt_mvtc_ops[0],
1956     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
1957   },
1958 /* neg $dr,$sr */
1959   {
1960     { 1, 1, 1, 1 },
1961     M32R_INSN_NEG, "neg", "neg",
1962     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1963     { 16, 16, 0xf0f0 }, 0x30,
1964     (PTR) & fmt_mv_ops[0],
1965     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1966   },
1967 /* nop */
1968   {
1969     { 1, 1, 1, 1 },
1970     M32R_INSN_NOP, "nop", "nop",
1971     { { MNEM, 0 } },
1972     { 16, 16, 0xffff }, 0x7000,
1973     (PTR) 0,
1974     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1975   },
1976 /* not $dr,$sr */
1977   {
1978     { 1, 1, 1, 1 },
1979     M32R_INSN_NOT, "not", "not",
1980     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1981     { 16, 16, 0xf0f0 }, 0xb0,
1982     (PTR) & fmt_mv_ops[0],
1983     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
1984   },
1985 /* rac */
1986   {
1987     { 1, 1, 1, 1 },
1988     M32R_INSN_RAC, "rac", "rac",
1989     { { MNEM, 0 } },
1990     { 16, 16, 0xffff }, 0x5090,
1991     (PTR) & fmt_rac_ops[0],
1992     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1993   },
1994 /* start-sanitize-m32rx */
1995 /* rac $accd,$accs,$imm1 */
1996   {
1997     { 1, 1, 1, 1 },
1998     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
1999     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
2000     { 16, 16, 0xf3f2 }, 0x5090,
2001     (PTR) & fmt_rac_dsi_ops[0],
2002     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2003   },
2004 /* end-sanitize-m32rx */
2005 /* rach */
2006   {
2007     { 1, 1, 1, 1 },
2008     M32R_INSN_RACH, "rach", "rach",
2009     { { MNEM, 0 } },
2010     { 16, 16, 0xffff }, 0x5080,
2011     (PTR) & fmt_rac_ops[0],
2012     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2013   },
2014 /* start-sanitize-m32rx */
2015 /* rach $accd,$accs,$imm1 */
2016   {
2017     { 1, 1, 1, 1 },
2018     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
2019     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
2020     { 16, 16, 0xf3f2 }, 0x5080,
2021     (PTR) & fmt_rac_dsi_ops[0],
2022     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2023   },
2024 /* end-sanitize-m32rx */
2025 /* rte */
2026   {
2027     { 1, 1, 1, 1 },
2028     M32R_INSN_RTE, "rte", "rte",
2029     { { MNEM, 0 } },
2030     { 16, 16, 0xffff }, 0x10d6,
2031     (PTR) & fmt_rte_ops[0],
2032     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
2033   },
2034 /* seth $dr,$hash$hi16 */
2035   {
2036     { 1, 1, 1, 1 },
2037     M32R_INSN_SETH, "seth", "seth",
2038     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
2039     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2040     (PTR) & fmt_seth_ops[0],
2041     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2042   },
2043 /* sll $dr,$sr */
2044   {
2045     { 1, 1, 1, 1 },
2046     M32R_INSN_SLL, "sll", "sll",
2047     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2048     { 16, 16, 0xf0f0 }, 0x1040,
2049     (PTR) & fmt_add_ops[0],
2050     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2051   },
2052 /* sll3 $dr,$sr,$simm16 */
2053   {
2054     { 1, 1, 1, 1 },
2055     M32R_INSN_SLL3, "sll3", "sll3",
2056     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2057     { 32, 32, 0xf0f00000 }, 0x90c00000,
2058     (PTR) & fmt_sll3_ops[0],
2059     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2060   },
2061 /* slli $dr,$uimm5 */
2062   {
2063     { 1, 1, 1, 1 },
2064     M32R_INSN_SLLI, "slli", "slli",
2065     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2066     { 16, 16, 0xf0e0 }, 0x5040,
2067     (PTR) & fmt_slli_ops[0],
2068     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2069   },
2070 /* sra $dr,$sr */
2071   {
2072     { 1, 1, 1, 1 },
2073     M32R_INSN_SRA, "sra", "sra",
2074     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2075     { 16, 16, 0xf0f0 }, 0x1020,
2076     (PTR) & fmt_add_ops[0],
2077     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2078   },
2079 /* sra3 $dr,$sr,$simm16 */
2080   {
2081     { 1, 1, 1, 1 },
2082     M32R_INSN_SRA3, "sra3", "sra3",
2083     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2084     { 32, 32, 0xf0f00000 }, 0x90a00000,
2085     (PTR) & fmt_sll3_ops[0],
2086     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2087   },
2088 /* srai $dr,$uimm5 */
2089   {
2090     { 1, 1, 1, 1 },
2091     M32R_INSN_SRAI, "srai", "srai",
2092     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2093     { 16, 16, 0xf0e0 }, 0x5020,
2094     (PTR) & fmt_slli_ops[0],
2095     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2096   },
2097 /* srl $dr,$sr */
2098   {
2099     { 1, 1, 1, 1 },
2100     M32R_INSN_SRL, "srl", "srl",
2101     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2102     { 16, 16, 0xf0f0 }, 0x1000,
2103     (PTR) & fmt_add_ops[0],
2104     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2105   },
2106 /* srl3 $dr,$sr,$simm16 */
2107   {
2108     { 1, 1, 1, 1 },
2109     M32R_INSN_SRL3, "srl3", "srl3",
2110     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2111     { 32, 32, 0xf0f00000 }, 0x90800000,
2112     (PTR) & fmt_sll3_ops[0],
2113     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2114   },
2115 /* srli $dr,$uimm5 */
2116   {
2117     { 1, 1, 1, 1 },
2118     M32R_INSN_SRLI, "srli", "srli",
2119     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2120     { 16, 16, 0xf0e0 }, 0x5000,
2121     (PTR) & fmt_slli_ops[0],
2122     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2123   },
2124 /* st $src1,@$src2 */
2125   {
2126     { 1, 1, 1, 1 },
2127     M32R_INSN_ST, "st", "st",
2128     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2129     { 16, 16, 0xf0f0 }, 0x2040,
2130     (PTR) & fmt_st_ops[0],
2131     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2132   },
2133 /* st $src1,@($slo16,$src2) */
2134   {
2135     { 1, 1, 1, 1 },
2136     M32R_INSN_ST_D, "st-d", "st",
2137     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2138     { 32, 32, 0xf0f00000 }, 0xa0400000,
2139     (PTR) & fmt_st_d_ops[0],
2140     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2141   },
2142 /* stb $src1,@$src2 */
2143   {
2144     { 1, 1, 1, 1 },
2145     M32R_INSN_STB, "stb", "stb",
2146     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2147     { 16, 16, 0xf0f0 }, 0x2000,
2148     (PTR) & fmt_stb_ops[0],
2149     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2150   },
2151 /* stb $src1,@($slo16,$src2) */
2152   {
2153     { 1, 1, 1, 1 },
2154     M32R_INSN_STB_D, "stb-d", "stb",
2155     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2156     { 32, 32, 0xf0f00000 }, 0xa0000000,
2157     (PTR) & fmt_stb_d_ops[0],
2158     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2159   },
2160 /* sth $src1,@$src2 */
2161   {
2162     { 1, 1, 1, 1 },
2163     M32R_INSN_STH, "sth", "sth",
2164     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2165     { 16, 16, 0xf0f0 }, 0x2020,
2166     (PTR) & fmt_sth_ops[0],
2167     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2168   },
2169 /* sth $src1,@($slo16,$src2) */
2170   {
2171     { 1, 1, 1, 1 },
2172     M32R_INSN_STH_D, "sth-d", "sth",
2173     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2174     { 32, 32, 0xf0f00000 }, 0xa0200000,
2175     (PTR) & fmt_sth_d_ops[0],
2176     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
2177   },
2178 /* st $src1,@+$src2 */
2179   {
2180     { 1, 1, 1, 1 },
2181     M32R_INSN_ST_PLUS, "st-plus", "st",
2182     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
2183     { 16, 16, 0xf0f0 }, 0x2060,
2184     (PTR) & fmt_st_plus_ops[0],
2185     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2186   },
2187 /* st $src1,@-$src2 */
2188   {
2189     { 1, 1, 1, 1 },
2190     M32R_INSN_ST_MINUS, "st-minus", "st",
2191     { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
2192     { 16, 16, 0xf0f0 }, 0x2070,
2193     (PTR) & fmt_st_plus_ops[0],
2194     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2195   },
2196 /* sub $dr,$sr */
2197   {
2198     { 1, 1, 1, 1 },
2199     M32R_INSN_SUB, "sub", "sub",
2200     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2201     { 16, 16, 0xf0f0 }, 0x20,
2202     (PTR) & fmt_add_ops[0],
2203     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2204   },
2205 /* subv $dr,$sr */
2206   {
2207     { 1, 1, 1, 1 },
2208     M32R_INSN_SUBV, "subv", "subv",
2209     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2210     { 16, 16, 0xf0f0 }, 0x0,
2211     (PTR) & fmt_addv_ops[0],
2212     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2213   },
2214 /* subx $dr,$sr */
2215   {
2216     { 1, 1, 1, 1 },
2217     M32R_INSN_SUBX, "subx", "subx",
2218     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2219     { 16, 16, 0xf0f0 }, 0x10,
2220     (PTR) & fmt_addx_ops[0],
2221     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
2222   },
2223 /* trap $uimm4 */
2224   {
2225     { 1, 1, 1, 1 },
2226     M32R_INSN_TRAP, "trap", "trap",
2227     { { MNEM, ' ', OP (UIMM4), 0 } },
2228     { 16, 16, 0xfff0 }, 0x10f0,
2229     (PTR) & fmt_trap_ops[0],
2230     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
2231   },
2232 /* unlock $src1,@$src2 */
2233   {
2234     { 1, 1, 1, 1 },
2235     M32R_INSN_UNLOCK, "unlock", "unlock",
2236     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2237     { 16, 16, 0xf0f0 }, 0x2050,
2238     (PTR) & fmt_unlock_ops[0],
2239     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
2240   },
2241 /* start-sanitize-m32rx */
2242 /* satb $dr,$sr */
2243   {
2244     { 1, 1, 1, 1 },
2245     M32R_INSN_SATB, "satb", "satb",
2246     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2247     { 32, 32, 0xf0f0ffff }, 0x80600300,
2248     (PTR) & fmt_satb_ops[0],
2249     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2250   },
2251 /* end-sanitize-m32rx */
2252 /* start-sanitize-m32rx */
2253 /* sath $dr,$sr */
2254   {
2255     { 1, 1, 1, 1 },
2256     M32R_INSN_SATH, "sath", "sath",
2257     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2258     { 32, 32, 0xf0f0ffff }, 0x80600200,
2259     (PTR) & fmt_satb_ops[0],
2260     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2261   },
2262 /* end-sanitize-m32rx */
2263 /* start-sanitize-m32rx */
2264 /* sat $dr,$sr */
2265   {
2266     { 1, 1, 1, 1 },
2267     M32R_INSN_SAT, "sat", "sat",
2268     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2269     { 32, 32, 0xf0f0ffff }, 0x80600000,
2270     (PTR) & fmt_sat_ops[0],
2271     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
2272   },
2273 /* end-sanitize-m32rx */
2274 /* start-sanitize-m32rx */
2275 /* pcmpbz $src2 */
2276   {
2277     { 1, 1, 1, 1 },
2278     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2279     { { MNEM, ' ', OP (SRC2), 0 } },
2280     { 16, 16, 0xfff0 }, 0x370,
2281     (PTR) & fmt_cmpz_ops[0],
2282     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2283   },
2284 /* end-sanitize-m32rx */
2285 /* start-sanitize-m32rx */
2286 /* sadd */
2287   {
2288     { 1, 1, 1, 1 },
2289     M32R_INSN_SADD, "sadd", "sadd",
2290     { { MNEM, 0 } },
2291     { 16, 16, 0xffff }, 0x50e4,
2292     (PTR) & fmt_sadd_ops[0],
2293     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2294   },
2295 /* end-sanitize-m32rx */
2296 /* start-sanitize-m32rx */
2297 /* macwu1 $src1,$src2 */
2298   {
2299     { 1, 1, 1, 1 },
2300     M32R_INSN_MACWU1, "macwu1", "macwu1",
2301     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2302     { 16, 16, 0xf0f0 }, 0x50b0,
2303     (PTR) & fmt_macwu1_ops[0],
2304     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2305   },
2306 /* end-sanitize-m32rx */
2307 /* start-sanitize-m32rx */
2308 /* msblo $src1,$src2 */
2309   {
2310     { 1, 1, 1, 1 },
2311     M32R_INSN_MSBLO, "msblo", "msblo",
2312     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2313     { 16, 16, 0xf0f0 }, 0x50d0,
2314     (PTR) & fmt_machi_ops[0],
2315     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2316   },
2317 /* end-sanitize-m32rx */
2318 /* start-sanitize-m32rx */
2319 /* mulwu1 $src1,$src2 */
2320   {
2321     { 1, 1, 1, 1 },
2322     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2323     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2324     { 16, 16, 0xf0f0 }, 0x50a0,
2325     (PTR) & fmt_mulwu1_ops[0],
2326     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2327   },
2328 /* end-sanitize-m32rx */
2329 /* start-sanitize-m32rx */
2330 /* maclh1 $src1,$src2 */
2331   {
2332     { 1, 1, 1, 1 },
2333     M32R_INSN_MACLH1, "maclh1", "maclh1",
2334     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2335     { 16, 16, 0xf0f0 }, 0x50c0,
2336     (PTR) & fmt_macwu1_ops[0],
2337     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2338   },
2339 /* end-sanitize-m32rx */
2340 /* start-sanitize-m32rx */
2341 /* sc */
2342   {
2343     { 1, 1, 1, 1 },
2344     M32R_INSN_SC, "sc", "sc",
2345     { { MNEM, 0 } },
2346     { 16, 16, 0xffff }, 0x7401,
2347     (PTR) & fmt_sc_ops[0],
2348     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
2349   },
2350 /* end-sanitize-m32rx */
2351 /* start-sanitize-m32rx */
2352 /* snc */
2353   {
2354     { 1, 1, 1, 1 },
2355     M32R_INSN_SNC, "snc", "snc",
2356     { { MNEM, 0 } },
2357     { 16, 16, 0xffff }, 0x7501,
2358     (PTR) & fmt_sc_ops[0],
2359     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
2360   },
2361 /* end-sanitize-m32rx */
2362 };
2363
2364 #undef A
2365 #undef MNEM
2366 #undef OP
2367
2368 static const CGEN_INSN_TABLE insn_table =
2369 {
2370   & m32r_cgen_insn_table_entries[0],
2371   sizeof (CGEN_INSN),
2372   MAX_INSNS,
2373   NULL
2374 };
2375
2376 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2377
2378 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2379 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2380 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2381
2382 /* The macro instruction table.  */
2383
2384 static const CGEN_INSN macro_insn_table_entries[] =
2385 {
2386 /* bc $disp8 */
2387   {
2388     { 1, 1, 1, 1 },
2389     -1, "bc8r", "bc",
2390     { { MNEM, ' ', OP (DISP8), 0 } },
2391     { 16, 16, 0xff00 }, 0x7c00,
2392     (PTR) 0,
2393     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2394   },
2395 /* bc $disp24 */
2396   {
2397     { 1, 1, 1, 1 },
2398     -1, "bc24r", "bc",
2399     { { MNEM, ' ', OP (DISP24), 0 } },
2400     { 32, 32, 0xff000000 }, 0xfc000000,
2401     (PTR) 0,
2402     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2403   },
2404 /* bl $disp8 */
2405   {
2406     { 1, 1, 1, 1 },
2407     -1, "bl8r", "bl",
2408     { { MNEM, ' ', OP (DISP8), 0 } },
2409     { 16, 16, 0xff00 }, 0x7e00,
2410     (PTR) 0,
2411     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2412   },
2413 /* bl $disp24 */
2414   {
2415     { 1, 1, 1, 1 },
2416     -1, "bl24r", "bl",
2417     { { MNEM, ' ', OP (DISP24), 0 } },
2418     { 32, 32, 0xff000000 }, 0xfe000000,
2419     (PTR) 0,
2420     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2421   },
2422 /* bcl $disp8 */
2423   {
2424     { 1, 1, 1, 1 },
2425     -1, "bcl8r", "bcl",
2426     { { MNEM, ' ', OP (DISP8), 0 } },
2427     { 16, 16, 0xff00 }, 0x7800,
2428     (PTR) 0,
2429     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2430   },
2431 /* bcl $disp24 */
2432   {
2433     { 1, 1, 1, 1 },
2434     -1, "bcl24r", "bcl",
2435     { { MNEM, ' ', OP (DISP24), 0 } },
2436     { 32, 32, 0xff000000 }, 0xf8000000,
2437     (PTR) 0,
2438     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2439   },
2440 /* bnc $disp8 */
2441   {
2442     { 1, 1, 1, 1 },
2443     -1, "bnc8r", "bnc",
2444     { { MNEM, ' ', OP (DISP8), 0 } },
2445     { 16, 16, 0xff00 }, 0x7d00,
2446     (PTR) 0,
2447     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2448   },
2449 /* bnc $disp24 */
2450   {
2451     { 1, 1, 1, 1 },
2452     -1, "bnc24r", "bnc",
2453     { { MNEM, ' ', OP (DISP24), 0 } },
2454     { 32, 32, 0xff000000 }, 0xfd000000,
2455     (PTR) 0,
2456     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2457   },
2458 /* bra $disp8 */
2459   {
2460     { 1, 1, 1, 1 },
2461     -1, "bra8r", "bra",
2462     { { MNEM, ' ', OP (DISP8), 0 } },
2463     { 16, 16, 0xff00 }, 0x7f00,
2464     (PTR) 0,
2465     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2466   },
2467 /* bra $disp24 */
2468   {
2469     { 1, 1, 1, 1 },
2470     -1, "bra24r", "bra",
2471     { { MNEM, ' ', OP (DISP24), 0 } },
2472     { 32, 32, 0xff000000 }, 0xff000000,
2473     (PTR) 0,
2474     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2475   },
2476 /* bncl $disp8 */
2477   {
2478     { 1, 1, 1, 1 },
2479     -1, "bncl8r", "bncl",
2480     { { MNEM, ' ', OP (DISP8), 0 } },
2481     { 16, 16, 0xff00 }, 0x7900,
2482     (PTR) 0,
2483     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2484   },
2485 /* bncl $disp24 */
2486   {
2487     { 1, 1, 1, 1 },
2488     -1, "bncl24r", "bncl",
2489     { { MNEM, ' ', OP (DISP24), 0 } },
2490     { 32, 32, 0xff000000 }, 0xf9000000,
2491     (PTR) 0,
2492     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2493   },
2494 /* ld $dr,@($sr) */
2495   {
2496     { 1, 1, 1, 1 },
2497     -1, "ld-2", "ld",
2498     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2499     { 16, 16, 0xf0f0 }, 0x20c0,
2500     (PTR) 0,
2501     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2502   },
2503 /* ld $dr,@($sr,$slo16) */
2504   {
2505     { 1, 1, 1, 1 },
2506     -1, "ld-d2", "ld",
2507     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2508     { 32, 32, 0xf0f00000 }, 0xa0c00000,
2509     (PTR) 0,
2510     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2511   },
2512 /* ldb $dr,@($sr) */
2513   {
2514     { 1, 1, 1, 1 },
2515     -1, "ldb-2", "ldb",
2516     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2517     { 16, 16, 0xf0f0 }, 0x2080,
2518     (PTR) 0,
2519     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2520   },
2521 /* ldb $dr,@($sr,$slo16) */
2522   {
2523     { 1, 1, 1, 1 },
2524     -1, "ldb-d2", "ldb",
2525     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2526     { 32, 32, 0xf0f00000 }, 0xa0800000,
2527     (PTR) 0,
2528     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2529   },
2530 /* ldh $dr,@($sr) */
2531   {
2532     { 1, 1, 1, 1 },
2533     -1, "ldh-2", "ldh",
2534     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2535     { 16, 16, 0xf0f0 }, 0x20a0,
2536     (PTR) 0,
2537     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2538   },
2539 /* ldh $dr,@($sr,$slo16) */
2540   {
2541     { 1, 1, 1, 1 },
2542     -1, "ldh-d2", "ldh",
2543     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2544     { 32, 32, 0xf0f00000 }, 0xa0a00000,
2545     (PTR) 0,
2546     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2547   },
2548 /* ldub $dr,@($sr) */
2549   {
2550     { 1, 1, 1, 1 },
2551     -1, "ldub-2", "ldub",
2552     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2553     { 16, 16, 0xf0f0 }, 0x2090,
2554     (PTR) 0,
2555     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2556   },
2557 /* ldub $dr,@($sr,$slo16) */
2558   {
2559     { 1, 1, 1, 1 },
2560     -1, "ldub-d2", "ldub",
2561     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2562     { 32, 32, 0xf0f00000 }, 0xa0900000,
2563     (PTR) 0,
2564     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2565   },
2566 /* lduh $dr,@($sr) */
2567   {
2568     { 1, 1, 1, 1 },
2569     -1, "lduh-2", "lduh",
2570     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2571     { 16, 16, 0xf0f0 }, 0x20b0,
2572     (PTR) 0,
2573     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2574   },
2575 /* lduh $dr,@($sr,$slo16) */
2576   {
2577     { 1, 1, 1, 1 },
2578     -1, "lduh-d2", "lduh",
2579     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2580     { 32, 32, 0xf0f00000 }, 0xa0b00000,
2581     (PTR) 0,
2582     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2583   },
2584 /* pop $dr */
2585   {
2586     { 1, 1, 1, 1 },
2587     -1, "pop", "pop",
2588     { { MNEM, ' ', OP (DR), 0 } },
2589     { 16, 16, 0xf0ff }, 0x20ef,
2590     (PTR) 0,
2591     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2592   },
2593 /* ldi $dr,$simm8 */
2594   {
2595     { 1, 1, 1, 1 },
2596     -1, "ldi8a", "ldi",
2597     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
2598     { 16, 16, 0xf000 }, 0x6000,
2599     (PTR) 0,
2600     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
2601   },
2602 /* ldi $dr,$hash$slo16 */
2603   {
2604     { 1, 1, 1, 1 },
2605     -1, "ldi16a", "ldi",
2606     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
2607     { 32, 32, 0xf0ff0000 }, 0x90f00000,
2608     (PTR) 0,
2609     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2610   },
2611 /* rac $accd */
2612   {
2613     { 1, 1, 1, 1 },
2614     -1, "rac-d", "rac",
2615     { { MNEM, ' ', OP (ACCD), 0 } },
2616     { 16, 16, 0xf3ff }, 0x5090,
2617     (PTR) 0,
2618     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2619   },
2620 /* rac $accd,$accs */
2621   {
2622     { 1, 1, 1, 1 },
2623     -1, "rac-ds", "rac",
2624     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
2625     { 16, 16, 0xf3f3 }, 0x5090,
2626     (PTR) 0,
2627     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2628   },
2629 /* rach $accd */
2630   {
2631     { 1, 1, 1, 1 },
2632     -1, "rach-d", "rach",
2633     { { MNEM, ' ', OP (ACCD), 0 } },
2634     { 16, 16, 0xf3ff }, 0x5080,
2635     (PTR) 0,
2636     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2637   },
2638 /* rach $accd,$accs */
2639   {
2640     { 1, 1, 1, 1 },
2641     -1, "rach-ds", "rach",
2642     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
2643     { 16, 16, 0xf3f3 }, 0x5080,
2644     (PTR) 0,
2645     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2646   },
2647 /* st $src1,@($src2) */
2648   {
2649     { 1, 1, 1, 1 },
2650     -1, "st-2", "st",
2651     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2652     { 16, 16, 0xf0f0 }, 0x2040,
2653     (PTR) 0,
2654     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2655   },
2656 /* st $src1,@($src2,$slo16) */
2657   {
2658     { 1, 1, 1, 1 },
2659     -1, "st-d2", "st",
2660     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2661     { 32, 32, 0xf0f00000 }, 0xa0400000,
2662     (PTR) 0,
2663     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2664   },
2665 /* stb $src1,@($src2) */
2666   {
2667     { 1, 1, 1, 1 },
2668     -1, "stb-2", "stb",
2669     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2670     { 16, 16, 0xf0f0 }, 0x2000,
2671     (PTR) 0,
2672     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2673   },
2674 /* stb $src1,@($src2,$slo16) */
2675   {
2676     { 1, 1, 1, 1 },
2677     -1, "stb-d2", "stb",
2678     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2679     { 32, 32, 0xf0f00000 }, 0xa0000000,
2680     (PTR) 0,
2681     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2682   },
2683 /* sth $src1,@($src2) */
2684   {
2685     { 1, 1, 1, 1 },
2686     -1, "sth-2", "sth",
2687     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2688     { 16, 16, 0xf0f0 }, 0x2020,
2689     (PTR) 0,
2690     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
2691   },
2692 /* sth $src1,@($src2,$slo16) */
2693   {
2694     { 1, 1, 1, 1 },
2695     -1, "sth-d2", "sth",
2696     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2697     { 32, 32, 0xf0f00000 }, 0xa0200000,
2698     (PTR) 0,
2699     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2700   },
2701 /* push $src1 */
2702   {
2703     { 1, 1, 1, 1 },
2704     -1, "push", "push",
2705     { { MNEM, ' ', OP (SRC1), 0 } },
2706     { 16, 16, 0xf0ff }, 0x207f,
2707     (PTR) 0,
2708     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
2709   },
2710 };
2711
2712 #undef A
2713 #undef MNEM
2714 #undef OP
2715
2716 static const CGEN_INSN_TABLE macro_insn_table =
2717 {
2718   & macro_insn_table_entries[0],
2719   sizeof (CGEN_INSN),
2720   (sizeof (macro_insn_table_entries) /
2721    sizeof (macro_insn_table_entries[0])),
2722   NULL
2723 };
2724
2725 static void
2726 init_tables ()
2727 {
2728 }
2729
2730 /* Return non-zero if INSN is to be added to the hash table.
2731    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2732
2733 static int
2734 asm_hash_insn_p (insn)
2735      const CGEN_INSN * insn;
2736 {
2737   return CGEN_ASM_HASH_P (insn);
2738 }
2739
2740 static int
2741 dis_hash_insn_p (insn)
2742      const CGEN_INSN * insn;
2743 {
2744   /* If building the hash table and the NO-DIS attribute is present,
2745      ignore.  */
2746   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2747     return 0;
2748   return CGEN_DIS_HASH_P (insn);
2749 }
2750
2751 /* The result is the hash value of the insn.
2752    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2753
2754 static unsigned int
2755 asm_hash_insn (mnem)
2756      const char * mnem;
2757 {
2758   return CGEN_ASM_HASH (mnem);
2759 }
2760
2761 /* BUF is a pointer to the insn's bytes in target order.
2762    VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2763    host order.  */
2764
2765 static unsigned int
2766 dis_hash_insn (buf, value)
2767      const char * buf;
2768      unsigned long value;
2769 {
2770   return CGEN_DIS_HASH (buf, value);
2771 }
2772
2773 /* Initialize an opcode table and return a descriptor.
2774    It's much like opening a file, and must be the first function called.  */
2775
2776 CGEN_OPCODE_DESC
2777 m32r_cgen_opcode_open (mach, endian)
2778      int mach;
2779      enum cgen_endian endian;
2780 {
2781   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2782   static int init_p;
2783
2784   if (! init_p)
2785     {
2786       init_tables ();
2787       init_p = 1;
2788     }
2789
2790   memset (table, 0, sizeof (*table));
2791
2792   CGEN_OPCODE_MACH (table) = mach;
2793   CGEN_OPCODE_ENDIAN (table) = endian;
2794   /* FIXME: for the sparc case we can determine insn-endianness statically.
2795      The worry here is where both data and insn endian can be independently
2796      chosen, in which case this function will need another argument.
2797      Actually, will want to allow for more arguments in the future anyway.  */
2798   CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2799
2800   CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
2801
2802   CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
2803
2804   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2805
2806   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2807
2808   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2809   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2810   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2811
2812   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2813   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2814   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2815
2816   return (CGEN_OPCODE_DESC) table;
2817 }
2818
2819 /* Close an opcode table.  */
2820
2821 void
2822 m32r_cgen_opcode_close (desc)
2823      CGEN_OPCODE_DESC desc;
2824 {
2825   free (desc);
2826 }
2827
2828 /* Getting values from cgen_fields is handled by a collection of functions.
2829    They are distinguished by the type of the VALUE argument they return.
2830    TODO: floating point, inlining support, remove cases where result type
2831    not appropriate.  */
2832
2833 int
2834 m32r_cgen_get_int_operand (opindex, fields)
2835      int opindex;
2836      const CGEN_FIELDS * fields;
2837 {
2838   int value;
2839
2840   switch (opindex)
2841     {
2842     case M32R_OPERAND_SR :
2843       value = fields->f_r2;
2844       break;
2845     case M32R_OPERAND_DR :
2846       value = fields->f_r1;
2847       break;
2848     case M32R_OPERAND_SRC1 :
2849       value = fields->f_r1;
2850       break;
2851     case M32R_OPERAND_SRC2 :
2852       value = fields->f_r2;
2853       break;
2854     case M32R_OPERAND_SCR :
2855       value = fields->f_r2;
2856       break;
2857     case M32R_OPERAND_DCR :
2858       value = fields->f_r1;
2859       break;
2860     case M32R_OPERAND_SIMM8 :
2861       value = fields->f_simm8;
2862       break;
2863     case M32R_OPERAND_SIMM16 :
2864       value = fields->f_simm16;
2865       break;
2866     case M32R_OPERAND_UIMM4 :
2867       value = fields->f_uimm4;
2868       break;
2869     case M32R_OPERAND_UIMM5 :
2870       value = fields->f_uimm5;
2871       break;
2872     case M32R_OPERAND_UIMM16 :
2873       value = fields->f_uimm16;
2874       break;
2875 /* start-sanitize-m32rx */
2876     case M32R_OPERAND_IMM1 :
2877       value = fields->f_imm1;
2878       break;
2879 /* end-sanitize-m32rx */
2880 /* start-sanitize-m32rx */
2881     case M32R_OPERAND_ACCD :
2882       value = fields->f_accd;
2883       break;
2884 /* end-sanitize-m32rx */
2885 /* start-sanitize-m32rx */
2886     case M32R_OPERAND_ACCS :
2887       value = fields->f_accs;
2888       break;
2889 /* end-sanitize-m32rx */
2890 /* start-sanitize-m32rx */
2891     case M32R_OPERAND_ACC :
2892       value = fields->f_acc;
2893       break;
2894 /* end-sanitize-m32rx */
2895     case M32R_OPERAND_HASH :
2896       value = fields->f_nil;
2897       break;
2898     case M32R_OPERAND_HI16 :
2899       value = fields->f_hi16;
2900       break;
2901     case M32R_OPERAND_SLO16 :
2902       value = fields->f_simm16;
2903       break;
2904     case M32R_OPERAND_ULO16 :
2905       value = fields->f_uimm16;
2906       break;
2907     case M32R_OPERAND_UIMM24 :
2908       value = fields->f_uimm24;
2909       break;
2910     case M32R_OPERAND_DISP8 :
2911       value = fields->f_disp8;
2912       break;
2913     case M32R_OPERAND_DISP16 :
2914       value = fields->f_disp16;
2915       break;
2916     case M32R_OPERAND_DISP24 :
2917       value = fields->f_disp24;
2918       break;
2919
2920     default :
2921       /* xgettext:c-format */
2922       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2923                        opindex);
2924       abort ();
2925   }
2926
2927   return value;
2928 }
2929
2930 bfd_vma
2931 m32r_cgen_get_vma_operand (opindex, fields)
2932      int opindex;
2933      const CGEN_FIELDS * fields;
2934 {
2935   bfd_vma value;
2936
2937   switch (opindex)
2938     {
2939     case M32R_OPERAND_SR :
2940       value = fields->f_r2;
2941       break;
2942     case M32R_OPERAND_DR :
2943       value = fields->f_r1;
2944       break;
2945     case M32R_OPERAND_SRC1 :
2946       value = fields->f_r1;
2947       break;
2948     case M32R_OPERAND_SRC2 :
2949       value = fields->f_r2;
2950       break;
2951     case M32R_OPERAND_SCR :
2952       value = fields->f_r2;
2953       break;
2954     case M32R_OPERAND_DCR :
2955       value = fields->f_r1;
2956       break;
2957     case M32R_OPERAND_SIMM8 :
2958       value = fields->f_simm8;
2959       break;
2960     case M32R_OPERAND_SIMM16 :
2961       value = fields->f_simm16;
2962       break;
2963     case M32R_OPERAND_UIMM4 :
2964       value = fields->f_uimm4;
2965       break;
2966     case M32R_OPERAND_UIMM5 :
2967       value = fields->f_uimm5;
2968       break;
2969     case M32R_OPERAND_UIMM16 :
2970       value = fields->f_uimm16;
2971       break;
2972 /* start-sanitize-m32rx */
2973     case M32R_OPERAND_IMM1 :
2974       value = fields->f_imm1;
2975       break;
2976 /* end-sanitize-m32rx */
2977 /* start-sanitize-m32rx */
2978     case M32R_OPERAND_ACCD :
2979       value = fields->f_accd;
2980       break;
2981 /* end-sanitize-m32rx */
2982 /* start-sanitize-m32rx */
2983     case M32R_OPERAND_ACCS :
2984       value = fields->f_accs;
2985       break;
2986 /* end-sanitize-m32rx */
2987 /* start-sanitize-m32rx */
2988     case M32R_OPERAND_ACC :
2989       value = fields->f_acc;
2990       break;
2991 /* end-sanitize-m32rx */
2992     case M32R_OPERAND_HASH :
2993       value = fields->f_nil;
2994       break;
2995     case M32R_OPERAND_HI16 :
2996       value = fields->f_hi16;
2997       break;
2998     case M32R_OPERAND_SLO16 :
2999       value = fields->f_simm16;
3000       break;
3001     case M32R_OPERAND_ULO16 :
3002       value = fields->f_uimm16;
3003       break;
3004     case M32R_OPERAND_UIMM24 :
3005       value = fields->f_uimm24;
3006       break;
3007     case M32R_OPERAND_DISP8 :
3008       value = fields->f_disp8;
3009       break;
3010     case M32R_OPERAND_DISP16 :
3011       value = fields->f_disp16;
3012       break;
3013     case M32R_OPERAND_DISP24 :
3014       value = fields->f_disp24;
3015       break;
3016
3017     default :
3018       /* xgettext:c-format */
3019       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3020                        opindex);
3021       abort ();
3022   }
3023
3024   return value;
3025 }
3026
3027 /* Stuffing values in cgen_fields is handled by a collection of functions.
3028    They are distinguished by the type of the VALUE argument they accept.
3029    TODO: floating point, inlining support, remove cases where argument type
3030    not appropriate.  */
3031
3032 void
3033 m32r_cgen_set_int_operand (opindex, fields, value)
3034      int opindex;
3035      CGEN_FIELDS * fields;
3036      int value;
3037 {
3038   switch (opindex)
3039     {
3040     case M32R_OPERAND_SR :
3041       fields->f_r2 = value;
3042       break;
3043     case M32R_OPERAND_DR :
3044       fields->f_r1 = value;
3045       break;
3046     case M32R_OPERAND_SRC1 :
3047       fields->f_r1 = value;
3048       break;
3049     case M32R_OPERAND_SRC2 :
3050       fields->f_r2 = value;
3051       break;
3052     case M32R_OPERAND_SCR :
3053       fields->f_r2 = value;
3054       break;
3055     case M32R_OPERAND_DCR :
3056       fields->f_r1 = value;
3057       break;
3058     case M32R_OPERAND_SIMM8 :
3059       fields->f_simm8 = value;
3060       break;
3061     case M32R_OPERAND_SIMM16 :
3062       fields->f_simm16 = value;
3063       break;
3064     case M32R_OPERAND_UIMM4 :
3065       fields->f_uimm4 = value;
3066       break;
3067     case M32R_OPERAND_UIMM5 :
3068       fields->f_uimm5 = value;
3069       break;
3070     case M32R_OPERAND_UIMM16 :
3071       fields->f_uimm16 = value;
3072       break;
3073 /* start-sanitize-m32rx */
3074     case M32R_OPERAND_IMM1 :
3075       fields->f_imm1 = value;
3076       break;
3077 /* end-sanitize-m32rx */
3078 /* start-sanitize-m32rx */
3079     case M32R_OPERAND_ACCD :
3080       fields->f_accd = value;
3081       break;
3082 /* end-sanitize-m32rx */
3083 /* start-sanitize-m32rx */
3084     case M32R_OPERAND_ACCS :
3085       fields->f_accs = value;
3086       break;
3087 /* end-sanitize-m32rx */
3088 /* start-sanitize-m32rx */
3089     case M32R_OPERAND_ACC :
3090       fields->f_acc = value;
3091       break;
3092 /* end-sanitize-m32rx */
3093     case M32R_OPERAND_HASH :
3094       fields->f_nil = value;
3095       break;
3096     case M32R_OPERAND_HI16 :
3097       fields->f_hi16 = value;
3098       break;
3099     case M32R_OPERAND_SLO16 :
3100       fields->f_simm16 = value;
3101       break;
3102     case M32R_OPERAND_ULO16 :
3103       fields->f_uimm16 = value;
3104       break;
3105     case M32R_OPERAND_UIMM24 :
3106       fields->f_uimm24 = value;
3107       break;
3108     case M32R_OPERAND_DISP8 :
3109       fields->f_disp8 = value;
3110       break;
3111     case M32R_OPERAND_DISP16 :
3112       fields->f_disp16 = value;
3113       break;
3114     case M32R_OPERAND_DISP24 :
3115       fields->f_disp24 = value;
3116       break;
3117
3118     default :
3119       /* xgettext:c-format */
3120       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3121                        opindex);
3122       abort ();
3123   }
3124 }
3125
3126 void
3127 m32r_cgen_set_vma_operand (opindex, fields, value)
3128      int opindex;
3129      CGEN_FIELDS * fields;
3130      bfd_vma value;
3131 {
3132   switch (opindex)
3133     {
3134     case M32R_OPERAND_SR :
3135       fields->f_r2 = value;
3136       break;
3137     case M32R_OPERAND_DR :
3138       fields->f_r1 = value;
3139       break;
3140     case M32R_OPERAND_SRC1 :
3141       fields->f_r1 = value;
3142       break;
3143     case M32R_OPERAND_SRC2 :
3144       fields->f_r2 = value;
3145       break;
3146     case M32R_OPERAND_SCR :
3147       fields->f_r2 = value;
3148       break;
3149     case M32R_OPERAND_DCR :
3150       fields->f_r1 = value;
3151       break;
3152     case M32R_OPERAND_SIMM8 :
3153       fields->f_simm8 = value;
3154       break;
3155     case M32R_OPERAND_SIMM16 :
3156       fields->f_simm16 = value;
3157       break;
3158     case M32R_OPERAND_UIMM4 :
3159       fields->f_uimm4 = value;
3160       break;
3161     case M32R_OPERAND_UIMM5 :
3162       fields->f_uimm5 = value;
3163       break;
3164     case M32R_OPERAND_UIMM16 :
3165       fields->f_uimm16 = value;
3166       break;
3167 /* start-sanitize-m32rx */
3168     case M32R_OPERAND_IMM1 :
3169       fields->f_imm1 = value;
3170       break;
3171 /* end-sanitize-m32rx */
3172 /* start-sanitize-m32rx */
3173     case M32R_OPERAND_ACCD :
3174       fields->f_accd = value;
3175       break;
3176 /* end-sanitize-m32rx */
3177 /* start-sanitize-m32rx */
3178     case M32R_OPERAND_ACCS :
3179       fields->f_accs = value;
3180       break;
3181 /* end-sanitize-m32rx */
3182 /* start-sanitize-m32rx */
3183     case M32R_OPERAND_ACC :
3184       fields->f_acc = value;
3185       break;
3186 /* end-sanitize-m32rx */
3187     case M32R_OPERAND_HASH :
3188       fields->f_nil = value;
3189       break;
3190     case M32R_OPERAND_HI16 :
3191       fields->f_hi16 = value;
3192       break;
3193     case M32R_OPERAND_SLO16 :
3194       fields->f_simm16 = value;
3195       break;
3196     case M32R_OPERAND_ULO16 :
3197       fields->f_uimm16 = value;
3198       break;
3199     case M32R_OPERAND_UIMM24 :
3200       fields->f_uimm24 = value;
3201       break;
3202     case M32R_OPERAND_DISP8 :
3203       fields->f_disp8 = value;
3204       break;
3205     case M32R_OPERAND_DISP16 :
3206       fields->f_disp16 = value;
3207       break;
3208     case M32R_OPERAND_DISP24 :
3209       fields->f_disp24 = value;
3210       break;
3211
3212     default :
3213       /* xgettext:c-format */
3214       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3215                        opindex);
3216       abort ();
3217   }
3218 }
3219