opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31 #include "opintl.h"
  32
  33 /* Look up instruction INSN_VALUE and extract its fields.
  34    INSN, if non-null, is the insn table entry.
  35    Otherwise INSN_VALUE is examined to compute it.
  36    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  37    0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
  38    If INSN != NULL, LENGTH must be valid.
  39    ALIAS_P is non-zero if alias insns are to be included in the search.
  40
  41    The result a pointer to the insn table entry, or NULL if the instruction
  42    wasn't recognized.  */
  43
  44 const CGEN_INSN *
  45 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  46      const CGEN_INSN *insn;
  47      cgen_insn_t insn_value;
  48      int length;
  49      CGEN_FIELDS *fields;
  50      int alias_p;
  51 {
  52   char buf[16];
  53
  54   if (!insn)
  55     {
  56       const CGEN_INSN_LIST *insn_list;
  57
  58 #ifdef CGEN_INT_INSN
  59       switch (length)
  60         {
  61         case 8:
  62           buf[0] = insn_value;
  63           break;
  64         case 16:
  65           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  66             bfd_putb16 (insn_value, buf);
  67           else
  68             bfd_putl16 (insn_value, buf);
  69           break;
  70         case 32:
  71           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  72             bfd_putb32 (insn_value, buf);
  73           else
  74             bfd_putl32 (insn_value, buf);
  75           break;
  76         default:
  77           abort ();
  78         }
  79 #else
  80       abort (); /* FIXME: unfinished */
  81 #endif
  82
  83       /* The instructions are stored in hash lists.
  84          Pick the first one and keep trying until we find the right one.  */
  85
  86       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  87       while (insn_list != NULL)
  88         {
  89           insn = insn_list->insn;
  90
  91           if (alias_p
  92               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  93             {
  94               /* Basic bit mask must be correct.  */
  95               /* ??? May wish to allow target to defer this check until the
  96                  extract handler.  */
  97               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  98                 {
  99                   /* ??? 0 is passed for `pc' */
 100                   int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
 101                                                            insn_value, fields,
 102                                                            (bfd_vma) 0);
 103                   if (elength > 0)
 104                     {
 105                       /* sanity check */
 106                       if (length != 0 && length != elength)
 107                         abort ();
 108                       return insn;
 109                     }
 110                 }
 111             }
 112
 113           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 114         }
 115     }
 116   else
 117     {
 118       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 119       if (! alias_p
 120           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 121         abort ();
 122       /* Sanity check: length must be correct.  */
 123       if (length != CGEN_INSN_BITSIZE (insn))
 124         abort ();
 125
 126       /* ??? 0 is passed for `pc' */
 127       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields,
 128                                           (bfd_vma) 0);
 129       /* Sanity check: must succeed.
 130          Could relax this later if it ever proves useful.  */
 131       if (length == 0)
 132         abort ();
 133       return insn;
 134     }
 135
 136   return NULL;
 137 }
 138
 139 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 140    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 141    in.  */
 142
 143 void
 144 m32r_cgen_get_insn_operands (insn, fields, indices)
 145      const CGEN_INSN * insn;
 146      const CGEN_FIELDS * fields;
 147      int *indices;
 148 {
 149   const CGEN_OPERAND_INSTANCE *opinst;
 150   int i;
 151
 152   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 153        opinst != NULL
 154          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 155        ++i, ++opinst)
 156     {
 157       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 158       if (op == NULL)
 159         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 160       else
 161         indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), fields);
 162     }
 163 }
 164
 165 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
 166    isn't known.
 167    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 168    m32r_cgen_lookup_insn unchanged.
 169
 170    The result is the insn table entry or NULL if the instruction wasn't
 171    recognized.  */
 172
 173 const CGEN_INSN *
 174 m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
 175      const CGEN_INSN *insn;
 176      cgen_insn_t insn_value;
 177      int length;
 178      int *indices;
 179 {
 180   CGEN_FIELDS fields;
 181
 182   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 183      If INSN == NULL, we want a real insn.  */
 184   insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields,
 185                                   insn != NULL);
 186   if (! insn)
 187     return NULL;
 188
 189   m32r_cgen_get_insn_operands (insn, &fields, indices);
 190   return insn;
 191 }
 192 /* Attributes.  */
 193
 194 static const CGEN_ATTR_ENTRY MACH_attr[] =
 195 {
 196   { "m32r", MACH_M32R },
 197 /* start-sanitize-m32rx */
 198   { "m32rx", MACH_M32RX },
 199 /* end-sanitize-m32rx */
 200   { "max", MACH_MAX },
 201   { 0, 0 }
 202 };
 203
 204 /* start-sanitize-m32rx */
 205 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 206 {
 207   { "NONE", PIPE_NONE },
 208   { "O", PIPE_O },
 209   { "S", PIPE_S },
 210   { "OS", PIPE_OS },
 211   { 0, 0 }
 212 };
 213
 214 /* end-sanitize-m32rx */
 215 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 216 {
 217   { "ABS-ADDR", NULL },
 218   { "FAKE", NULL },
 219   { "HASH-PREFIX", NULL },
 220   { "NEGATIVE", NULL },
 221   { "PCREL-ADDR", NULL },
 222   { "RELAX", NULL },
 223   { "RELOC", NULL },
 224   { "SIGN-OPT", NULL },
 225   { "UNSIGNED", NULL },
 226   { 0, 0 }
 227 };
 228
 229 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 230 {
 231   { "MACH", & MACH_attr[0] },
 232 /* start-sanitize-m32rx */
 233   { "PIPE", & PIPE_attr[0] },
 234 /* end-sanitize-m32rx */
 235   { "ALIAS", NULL },
 236   { "COND-CTI", NULL },
 237   { "FILL-SLOT", NULL },
 238   { "NO-DIS", NULL },
 239   { "PARALLEL", NULL },
 240   { "RELAX", NULL },
 241   { "RELAXABLE", NULL },
 242   { "SPECIAL", NULL },
 243   { "UNCOND-CTI", NULL },
 244   { 0, 0 }
 245 };
 246
 247 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 248 {
 249   { "fp", 13 },
 250   { "lr", 14 },
 251   { "sp", 15 },
 252   { "r0", 0 },
 253   { "r1", 1 },
 254   { "r2", 2 },
 255   { "r3", 3 },
 256   { "r4", 4 },
 257   { "r5", 5 },
 258   { "r6", 6 },
 259   { "r7", 7 },
 260   { "r8", 8 },
 261   { "r9", 9 },
 262   { "r10", 10 },
 263   { "r11", 11 },
 264   { "r12", 12 },
 265   { "r13", 13 },
 266   { "r14", 14 },
 267   { "r15", 15 }
 268 };
 269
 270 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 271 {
 272   & m32r_cgen_opval_h_gr_entries[0],
 273   19
 274 };
 275
 276 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 277 {
 278   { "psw", 0 },
 279   { "cbr", 1 },
 280   { "spi", 2 },
 281   { "spu", 3 },
 282   { "bpc", 6 },
 283   { "cr0", 0 },
 284   { "cr1", 1 },
 285   { "cr2", 2 },
 286   { "cr3", 3 },
 287   { "cr4", 4 },
 288   { "cr5", 5 },
 289   { "cr6", 6 },
 290   { "cr7", 7 },
 291   { "cr8", 8 },
 292   { "cr9", 9 },
 293   { "cr10", 10 },
 294   { "cr11", 11 },
 295   { "cr12", 12 },
 296   { "cr13", 13 },
 297   { "cr14", 14 },
 298   { "cr15", 15 }
 299 };
 300
 301 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 302 {
 303   & m32r_cgen_opval_h_cr_entries[0],
 304   21
 305 };
 306
 307 /* start-sanitize-m32rx */
 308 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 309 {
 310   { "a0", 0 },
 311   { "a1", 1 }
 312 };
 313
 314 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 315 {
 316   & m32r_cgen_opval_h_accums_entries[0],
 317   2
 318 };
 319
 320 /* end-sanitize-m32rx */
 321
 322 /* The hardware table.  */
 323
 324 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 325 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 326 {
 327   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 328   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 329   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 330   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 331   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 332   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 333   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 334   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 335   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 336   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 337   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 338   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 339 /* start-sanitize-m32rx */
 340   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 341 /* end-sanitize-m32rx */
 342   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 343   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 344   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 345   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 346   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 347   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 348   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 349   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
 350   { 0 }
 351 };
 352
 353 /* The operand table.  */
 354
 355 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 356 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 357
 358 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 359 {
 360 /* pc: program counter */
 361   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 362     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 363 /* sr: source register */
 364   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 365     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 366 /* dr: destination register */
 367   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 368     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 369 /* src1: source register 1 */
 370   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 371     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 372 /* src2: source register 2 */
 373   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 374     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 375 /* scr: source control register */
 376   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 377     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 378 /* dcr: destination control register */
 379   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 380     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 381 /* simm8: 8 bit signed immediate */
 382   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 383     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 384 /* simm16: 16 bit signed immediate */
 385   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 386     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 387 /* uimm4: 4 bit trap number */
 388   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 389     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 390 /* uimm5: 5 bit shift count */
 391   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 392     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 393 /* uimm16: 16 bit unsigned immediate */
 394   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 395     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 396 /* start-sanitize-m32rx */
 397 /* imm1: 1 bit immediate */
 398   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 399     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 400 /* end-sanitize-m32rx */
 401 /* start-sanitize-m32rx */
 402 /* accd: accumulator destination register */
 403   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 404     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 405 /* end-sanitize-m32rx */
 406 /* start-sanitize-m32rx */
 407 /* accs: accumulator source register */
 408   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 409     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 410 /* end-sanitize-m32rx */
 411 /* start-sanitize-m32rx */
 412 /* acc: accumulator reg (d) */
 413   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 414     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 415 /* end-sanitize-m32rx */
 416 /* hash: # prefix */
 417   { "hash", & HW_ENT (HW_H_SINT), 0, 0,
 418     { 0, 0, { 0 } }  },
 419 /* hi16: high 16 bit immediate, sign optional */
 420   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 421     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 422 /* slo16: 16 bit signed immediate, for low() */
 423   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 424     { 0, 0, { 0 } }  },
 425 /* ulo16: 16 bit unsigned immediate, for low() */
 426   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 427     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 428 /* uimm24: 24 bit address */
 429   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 430     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 431 /* disp8: 8 bit displacement */
 432   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 433     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 434 /* disp16: 16 bit displacement */
 435   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 436     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 437 /* disp24: 24 bit displacement */
 438   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 439     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 440 /* condbit: condition bit */
 441   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 442     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 443 /* accum: accumulator */
 444   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 445     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 446 };
 447
 448 /* Operand references.  */
 449
 450 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 451 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 452
 453 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 454   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 455   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 456   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 457   { 0 }
 458 };
 459
 460 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
 461   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 462   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 463   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 464   { 0 }
 465 };
 466
 467 static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
 468   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 469   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 470   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 471   { 0 }
 472 };
 473
 474 static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
 475   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 476   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 477   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 478   { 0 }
 479 };
 480
 481 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 482   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 483   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 484   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 485   { 0 }
 486 };
 487
 488 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
 489   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 490   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 491   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 492   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 493   { 0 }
 494 };
 495
 496 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
 497   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 498   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 499   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 500   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 501   { 0 }
 502 };
 503
 504 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
 505   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 506   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 507   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 508   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 509   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 510   { 0 }
 511 };
 512
 513 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
 514   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 515   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 516   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 517   { 0 }
 518 };
 519
 520 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
 521   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 522   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 523   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 524   { 0 }
 525 };
 526
 527 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
 528   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 529   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 530   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 531   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 532   { 0 }
 533 };
 534
 535 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
 536   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 537   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 538   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 539   { 0 }
 540 };
 541
 542 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
 543   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 544   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 545   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 546   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 547   { 0 }
 548 };
 549
 550 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
 551   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 552   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 553   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 554   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 555   { 0 }
 556 };
 557
 558 /* start-sanitize-m32rx */
 559 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
 560   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 561   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 562   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 563   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 564   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 565   { 0 }
 566 };
 567
 568 /* end-sanitize-m32rx */
 569 /* start-sanitize-m32rx */
 570 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
 571   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 572   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 573   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 574   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 575   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 576   { 0 }
 577 };
 578
 579 /* end-sanitize-m32rx */
 580 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
 581   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 582   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 583   { 0 }
 584 };
 585
 586 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
 587   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 588   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 589   { 0 }
 590 };
 591
 592 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 593   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 594   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 595   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 596   { 0 }
 597 };
 598
 599 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 600   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 601   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 602   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 603   { 0 }
 604 };
 605
 606 /* start-sanitize-m32rx */
 607 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
 608   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 609   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 610   { 0 }
 611 };
 612
 613 /* end-sanitize-m32rx */
 614 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
 615   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 616   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 617   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 618   { 0 }
 619 };
 620
 621 /* start-sanitize-m32rx */
 622 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
 623   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 624   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 625   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 626   { 0 }
 627 };
 628
 629 /* end-sanitize-m32rx */
 630 static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
 631   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 632   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 633   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 634   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 635   { 0 }
 636 };
 637
 638 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
 639   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 640   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 641   { 0 }
 642 };
 643
 644 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
 645   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 646   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 647   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 648   { 0 }
 649 };
 650
 651 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
 652   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 653   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 654   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 655   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 656   { 0 }
 657 };
 658
 659 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
 660   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 661   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 662   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 663   { 0 }
 664 };
 665
 666 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
 667   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 668   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 669   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 670   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 671   { 0 }
 672 };
 673
 674 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
 675   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 676   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 677   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 678   { 0 }
 679 };
 680
 681 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
 682   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 683   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 684   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 685   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 686   { 0 }
 687 };
 688
 689 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
 690   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 691   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 692   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 693   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 694   { 0 }
 695 };
 696
 697 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
 698   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
 699   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 700   { 0 }
 701 };
 702
 703 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
 704   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 705   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 706   { 0 }
 707 };
 708
 709 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
 710   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 711   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 712   { 0 }
 713 };
 714
 715 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
 716   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 717   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 718   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 719   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 720   { 0 }
 721 };
 722
 723 static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
 724   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 725   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 726   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 727   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 728   { 0 }
 729 };
 730
 731 /* start-sanitize-m32rx */
 732 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
 733   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 734   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 735   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 736   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 737   { 0 }
 738 };
 739
 740 /* end-sanitize-m32rx */
 741 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
 742   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 743   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 744   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 745   { 0 }
 746 };
 747
 748 /* start-sanitize-m32rx */
 749 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
 750   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 751   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 752   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 753   { 0 }
 754 };
 755
 756 /* end-sanitize-m32rx */
 757 static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
 758   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 759   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 760   { 0 }
 761 };
 762
 763 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
 764   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 765   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 766   { 0 }
 767 };
 768
 769 /* start-sanitize-m32rx */
 770 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
 771   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 772   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 773   { 0 }
 774 };
 775
 776 /* end-sanitize-m32rx */
 777 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
 778   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 779   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 780   { 0 }
 781 };
 782
 783 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
 784   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 785   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 786   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 787   { 0 }
 788 };
 789
 790 /* start-sanitize-m32rx */
 791 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
 792   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 793   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 794   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 795   { 0 }
 796 };
 797
 798 /* end-sanitize-m32rx */
 799 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
 800   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 801   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 802   { 0 }
 803 };
 804
 805 static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
 806   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 807   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 808   { 0 }
 809 };
 810
 811 /* start-sanitize-m32rx */
 812 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
 813   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 814   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 815   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 816   { 0 }
 817 };
 818
 819 /* end-sanitize-m32rx */
 820 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
 821   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
 822   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
 823   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
 824   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
 825   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
 826   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
 827   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 828   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 829   { 0 }
 830 };
 831
 832 static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
 833   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
 834   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 835   { 0 }
 836 };
 837
 838 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
 839   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 840   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 841   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 842   { 0 }
 843 };
 844
 845 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
 846   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 847   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 848   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 849   { 0 }
 850 };
 851
 852 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
 853   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 854   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 855   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 856   { 0 }
 857 };
 858
 859 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
 860   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 861   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 862   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 863   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 864   { 0 }
 865 };
 866
 867 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
 868   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 869   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 870   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 871   { 0 }
 872 };
 873
 874 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
 875   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 876   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 877   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 878   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 879   { 0 }
 880 };
 881
 882 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
 883   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 884   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 885   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 886   { 0 }
 887 };
 888
 889 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
 890   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 891   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 892   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 893   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 894   { 0 }
 895 };
 896
 897 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
 898   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 899   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 900   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 901   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 902   { 0 }
 903 };
 904
 905 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
 906   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 907   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
 908   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
 909   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
 910   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
 911   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
 912   { 0 }
 913 };
 914
 915 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
 916   { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 917   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 918   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 919   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 920   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 921   { 0 }
 922 };
 923
 924 /* start-sanitize-m32rx */
 925 static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
 926   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 927   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 928   { 0 }
 929 };
 930
 931 /* end-sanitize-m32rx */
 932 /* start-sanitize-m32rx */
 933 static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
 934   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 935   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 936   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 937   { 0 }
 938 };
 939
 940 /* end-sanitize-m32rx */
 941 /* start-sanitize-m32rx */
 942 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
 943   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 944   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 945   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 946   { 0 }
 947 };
 948
 949 /* end-sanitize-m32rx */
 950 /* start-sanitize-m32rx */
 951 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
 952   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 953   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 954   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 955   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 956   { 0 }
 957 };
 958
 959 /* end-sanitize-m32rx */
 960 /* start-sanitize-m32rx */
 961 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
 962   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 963   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 964   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 965   { 0 }
 966 };
 967
 968 /* end-sanitize-m32rx */
 969 /* start-sanitize-m32rx */
 970 static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
 971   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 972   { 0 }
 973 };
 974
 975 /* end-sanitize-m32rx */
 976 #undef INPUT
 977 #undef OUTPUT
 978
 979 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 980 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 981 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 982
 983 /* The instruction table.
 984    This is currently non-static because the simulator accesses it
 985    directly.  */
 986
 987 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
 988 {
 989   /* Special null first entry.
 990      A `num' value of zero is thus illegal.
 991      Also, the special `illegal' insn resides here.  */
 992   { { 0 }, 0 },
 993 /* add $dr,$sr */
 994   {
 995     { 1, 1, 1, 1 },
 996     M32R_INSN_ADD, "add", "add",
 997     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 998     { 16, 16, 0xf0f0 }, 0xa0,
 999     (PTR) & fmt_add_ops[0],
1000     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1001   },
1002 /* add3 $dr,$sr,$hash$slo16 */
1003   {
1004     { 1, 1, 1, 1 },
1005     M32R_INSN_ADD3, "add3", "add3",
1006     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
1007     { 32, 32, 0xf0f00000 }, 0x80a00000,
1008     (PTR) & fmt_add3_ops[0],
1009     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1010   },
1011 /* and $dr,$sr */
1012   {
1013     { 1, 1, 1, 1 },
1014     M32R_INSN_AND, "and", "and",
1015     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1016     { 16, 16, 0xf0f0 }, 0xc0,
1017     (PTR) & fmt_add_ops[0],
1018     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1019   },
1020 /* and3 $dr,$sr,$uimm16 */
1021   {
1022     { 1, 1, 1, 1 },
1023     M32R_INSN_AND3, "and3", "and3",
1024     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1025     { 32, 32, 0xf0f00000 }, 0x80c00000,
1026     (PTR) & fmt_and3_ops[0],
1027     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1028   },
1029 /* or $dr,$sr */
1030   {
1031     { 1, 1, 1, 1 },
1032     M32R_INSN_OR, "or", "or",
1033     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1034     { 16, 16, 0xf0f0 }, 0xe0,
1035     (PTR) & fmt_add_ops[0],
1036     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1037   },
1038 /* or3 $dr,$sr,$hash$ulo16 */
1039   {
1040     { 1, 1, 1, 1 },
1041     M32R_INSN_OR3, "or3", "or3",
1042     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
1043     { 32, 32, 0xf0f00000 }, 0x80e00000,
1044     (PTR) & fmt_or3_ops[0],
1045     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1046   },
1047 /* xor $dr,$sr */
1048   {
1049     { 1, 1, 1, 1 },
1050     M32R_INSN_XOR, "xor", "xor",
1051     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1052     { 16, 16, 0xf0f0 }, 0xd0,
1053     (PTR) & fmt_add_ops[0],
1054     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1055   },
1056 /* xor3 $dr,$sr,$uimm16 */
1057   {
1058     { 1, 1, 1, 1 },
1059     M32R_INSN_XOR3, "xor3", "xor3",
1060     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1061     { 32, 32, 0xf0f00000 }, 0x80d00000,
1062     (PTR) & fmt_and3_ops[0],
1063     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1064   },
1065 /* addi $dr,$simm8 */
1066   {
1067     { 1, 1, 1, 1 },
1068     M32R_INSN_ADDI, "addi", "addi",
1069     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1070     { 16, 16, 0xf000 }, 0x4000,
1071     (PTR) & fmt_addi_ops[0],
1072     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1073   },
1074 /* addv $dr,$sr */
1075   {
1076     { 1, 1, 1, 1 },
1077     M32R_INSN_ADDV, "addv", "addv",
1078     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1079     { 16, 16, 0xf0f0 }, 0x80,
1080     (PTR) & fmt_addv_ops[0],
1081     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1082   },
1083 /* addv3 $dr,$sr,$simm16 */
1084   {
1085     { 1, 1, 1, 1 },
1086     M32R_INSN_ADDV3, "addv3", "addv3",
1087     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1088     { 32, 32, 0xf0f00000 }, 0x80800000,
1089     (PTR) & fmt_addv3_ops[0],
1090     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1091   },
1092 /* addx $dr,$sr */
1093   {
1094     { 1, 1, 1, 1 },
1095     M32R_INSN_ADDX, "addx", "addx",
1096     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1097     { 16, 16, 0xf0f0 }, 0x90,
1098     (PTR) & fmt_addx_ops[0],
1099     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1100   },
1101 /* bc.s $disp8 */
1102   {
1103     { 1, 1, 1, 1 },
1104     M32R_INSN_BC8, "bc8", "bc.s",
1105     { MNEM, ' ', OP (DISP8), 0 },
1106     { 16, 16, 0xff00 }, 0x7c00,
1107     (PTR) & fmt_bc8_ops[0],
1108     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1109   },
1110 /* bc.l $disp24 */
1111   {
1112     { 1, 1, 1, 1 },
1113     M32R_INSN_BC24, "bc24", "bc.l",
1114     { MNEM, ' ', OP (DISP24), 0 },
1115     { 32, 32, 0xff000000 }, 0xfc000000,
1116     (PTR) & fmt_bc24_ops[0],
1117     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1118   },
1119 /* beq $src1,$src2,$disp16 */
1120   {
1121     { 1, 1, 1, 1 },
1122     M32R_INSN_BEQ, "beq", "beq",
1123     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1124     { 32, 32, 0xf0f00000 }, 0xb0000000,
1125     (PTR) & fmt_beq_ops[0],
1126     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1127   },
1128 /* beqz $src2,$disp16 */
1129   {
1130     { 1, 1, 1, 1 },
1131     M32R_INSN_BEQZ, "beqz", "beqz",
1132     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1133     { 32, 32, 0xfff00000 }, 0xb0800000,
1134     (PTR) & fmt_beqz_ops[0],
1135     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1136   },
1137 /* bgez $src2,$disp16 */
1138   {
1139     { 1, 1, 1, 1 },
1140     M32R_INSN_BGEZ, "bgez", "bgez",
1141     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1142     { 32, 32, 0xfff00000 }, 0xb0b00000,
1143     (PTR) & fmt_beqz_ops[0],
1144     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1145   },
1146 /* bgtz $src2,$disp16 */
1147   {
1148     { 1, 1, 1, 1 },
1149     M32R_INSN_BGTZ, "bgtz", "bgtz",
1150     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1151     { 32, 32, 0xfff00000 }, 0xb0d00000,
1152     (PTR) & fmt_beqz_ops[0],
1153     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1154   },
1155 /* blez $src2,$disp16 */
1156   {
1157     { 1, 1, 1, 1 },
1158     M32R_INSN_BLEZ, "blez", "blez",
1159     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1160     { 32, 32, 0xfff00000 }, 0xb0c00000,
1161     (PTR) & fmt_beqz_ops[0],
1162     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1163   },
1164 /* bltz $src2,$disp16 */
1165   {
1166     { 1, 1, 1, 1 },
1167     M32R_INSN_BLTZ, "bltz", "bltz",
1168     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1169     { 32, 32, 0xfff00000 }, 0xb0a00000,
1170     (PTR) & fmt_beqz_ops[0],
1171     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1172   },
1173 /* bnez $src2,$disp16 */
1174   {
1175     { 1, 1, 1, 1 },
1176     M32R_INSN_BNEZ, "bnez", "bnez",
1177     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1178     { 32, 32, 0xfff00000 }, 0xb0900000,
1179     (PTR) & fmt_beqz_ops[0],
1180     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1181   },
1182 /* bl.s $disp8 */
1183   {
1184     { 1, 1, 1, 1 },
1185     M32R_INSN_BL8, "bl8", "bl.s",
1186     { MNEM, ' ', OP (DISP8), 0 },
1187     { 16, 16, 0xff00 }, 0x7e00,
1188     (PTR) & fmt_bl8_ops[0],
1189     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1190   },
1191 /* bl.l $disp24 */
1192   {
1193     { 1, 1, 1, 1 },
1194     M32R_INSN_BL24, "bl24", "bl.l",
1195     { MNEM, ' ', OP (DISP24), 0 },
1196     { 32, 32, 0xff000000 }, 0xfe000000,
1197     (PTR) & fmt_bl24_ops[0],
1198     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1199   },
1200 /* start-sanitize-m32rx */
1201 /* bcl.s $disp8 */
1202   {
1203     { 1, 1, 1, 1 },
1204     M32R_INSN_BCL8, "bcl8", "bcl.s",
1205     { MNEM, ' ', OP (DISP8), 0 },
1206     { 16, 16, 0xff00 }, 0x7800,
1207     (PTR) & fmt_bcl8_ops[0],
1208     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1209   },
1210 /* end-sanitize-m32rx */
1211 /* start-sanitize-m32rx */
1212 /* bcl.l $disp24 */
1213   {
1214     { 1, 1, 1, 1 },
1215     M32R_INSN_BCL24, "bcl24", "bcl.l",
1216     { MNEM, ' ', OP (DISP24), 0 },
1217     { 32, 32, 0xff000000 }, 0xf8000000,
1218     (PTR) & fmt_bcl24_ops[0],
1219     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1220   },
1221 /* end-sanitize-m32rx */
1222 /* bnc.s $disp8 */
1223   {
1224     { 1, 1, 1, 1 },
1225     M32R_INSN_BNC8, "bnc8", "bnc.s",
1226     { MNEM, ' ', OP (DISP8), 0 },
1227     { 16, 16, 0xff00 }, 0x7d00,
1228     (PTR) & fmt_bc8_ops[0],
1229     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1230   },
1231 /* bnc.l $disp24 */
1232   {
1233     { 1, 1, 1, 1 },
1234     M32R_INSN_BNC24, "bnc24", "bnc.l",
1235     { MNEM, ' ', OP (DISP24), 0 },
1236     { 32, 32, 0xff000000 }, 0xfd000000,
1237     (PTR) & fmt_bc24_ops[0],
1238     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1239   },
1240 /* bne $src1,$src2,$disp16 */
1241   {
1242     { 1, 1, 1, 1 },
1243     M32R_INSN_BNE, "bne", "bne",
1244     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1245     { 32, 32, 0xf0f00000 }, 0xb0100000,
1246     (PTR) & fmt_beq_ops[0],
1247     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1248   },
1249 /* bra.s $disp8 */
1250   {
1251     { 1, 1, 1, 1 },
1252     M32R_INSN_BRA8, "bra8", "bra.s",
1253     { MNEM, ' ', OP (DISP8), 0 },
1254     { 16, 16, 0xff00 }, 0x7f00,
1255     (PTR) & fmt_bra8_ops[0],
1256     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1257   },
1258 /* bra.l $disp24 */
1259   {
1260     { 1, 1, 1, 1 },
1261     M32R_INSN_BRA24, "bra24", "bra.l",
1262     { MNEM, ' ', OP (DISP24), 0 },
1263     { 32, 32, 0xff000000 }, 0xff000000,
1264     (PTR) & fmt_bra24_ops[0],
1265     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1266   },
1267 /* start-sanitize-m32rx */
1268 /* bncl.s $disp8 */
1269   {
1270     { 1, 1, 1, 1 },
1271     M32R_INSN_BNCL8, "bncl8", "bncl.s",
1272     { MNEM, ' ', OP (DISP8), 0 },
1273     { 16, 16, 0xff00 }, 0x7900,
1274     (PTR) & fmt_bcl8_ops[0],
1275     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1276   },
1277 /* end-sanitize-m32rx */
1278 /* start-sanitize-m32rx */
1279 /* bncl.l $disp24 */
1280   {
1281     { 1, 1, 1, 1 },
1282     M32R_INSN_BNCL24, "bncl24", "bncl.l",
1283     { MNEM, ' ', OP (DISP24), 0 },
1284     { 32, 32, 0xff000000 }, 0xf9000000,
1285     (PTR) & fmt_bcl24_ops[0],
1286     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1287   },
1288 /* end-sanitize-m32rx */
1289 /* cmp $src1,$src2 */
1290   {
1291     { 1, 1, 1, 1 },
1292     M32R_INSN_CMP, "cmp", "cmp",
1293     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1294     { 16, 16, 0xf0f0 }, 0x40,
1295     (PTR) & fmt_cmp_ops[0],
1296     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1297   },
1298 /* cmpi $src2,$simm16 */
1299   {
1300     { 1, 1, 1, 1 },
1301     M32R_INSN_CMPI, "cmpi", "cmpi",
1302     { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1303     { 32, 32, 0xfff00000 }, 0x80400000,
1304     (PTR) & fmt_cmpi_ops[0],
1305     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1306   },
1307 /* cmpu $src1,$src2 */
1308   {
1309     { 1, 1, 1, 1 },
1310     M32R_INSN_CMPU, "cmpu", "cmpu",
1311     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1312     { 16, 16, 0xf0f0 }, 0x50,
1313     (PTR) & fmt_cmp_ops[0],
1314     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1315   },
1316 /* cmpui $src2,$simm16 */
1317   {
1318     { 1, 1, 1, 1 },
1319     M32R_INSN_CMPUI, "cmpui", "cmpui",
1320     { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1321     { 32, 32, 0xfff00000 }, 0x80500000,
1322     (PTR) & fmt_cmpi_ops[0],
1323     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1324   },
1325 /* start-sanitize-m32rx */
1326 /* cmpeq $src1,$src2 */
1327   {
1328     { 1, 1, 1, 1 },
1329     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
1330     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1331     { 16, 16, 0xf0f0 }, 0x60,
1332     (PTR) & fmt_cmp_ops[0],
1333     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1334   },
1335 /* end-sanitize-m32rx */
1336 /* start-sanitize-m32rx */
1337 /* cmpz $src2 */
1338   {
1339     { 1, 1, 1, 1 },
1340     M32R_INSN_CMPZ, "cmpz", "cmpz",
1341     { MNEM, ' ', OP (SRC2), 0 },
1342     { 16, 16, 0xfff0 }, 0x70,
1343     (PTR) & fmt_cmpz_ops[0],
1344     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1345   },
1346 /* end-sanitize-m32rx */
1347 /* div $dr,$sr */
1348   {
1349     { 1, 1, 1, 1 },
1350     M32R_INSN_DIV, "div", "div",
1351     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1352     { 32, 32, 0xf0f0ffff }, 0x90000000,
1353     (PTR) & fmt_div_ops[0],
1354     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1355   },
1356 /* divu $dr,$sr */
1357   {
1358     { 1, 1, 1, 1 },
1359     M32R_INSN_DIVU, "divu", "divu",
1360     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1361     { 32, 32, 0xf0f0ffff }, 0x90100000,
1362     (PTR) & fmt_div_ops[0],
1363     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1364   },
1365 /* rem $dr,$sr */
1366   {
1367     { 1, 1, 1, 1 },
1368     M32R_INSN_REM, "rem", "rem",
1369     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1370     { 32, 32, 0xf0f0ffff }, 0x90200000,
1371     (PTR) & fmt_div_ops[0],
1372     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1373   },
1374 /* remu $dr,$sr */
1375   {
1376     { 1, 1, 1, 1 },
1377     M32R_INSN_REMU, "remu", "remu",
1378     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1379     { 32, 32, 0xf0f0ffff }, 0x90300000,
1380     (PTR) & fmt_div_ops[0],
1381     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1382   },
1383 /* start-sanitize-m32rx */
1384 /* divh $dr,$sr */
1385   {
1386     { 1, 1, 1, 1 },
1387     M32R_INSN_DIVH, "divh", "divh",
1388     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1389     { 32, 32, 0xf0f0ffff }, 0x90000010,
1390     (PTR) & fmt_div_ops[0],
1391     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1392   },
1393 /* end-sanitize-m32rx */
1394 /* start-sanitize-m32rx */
1395 /* jc $sr */
1396   {
1397     { 1, 1, 1, 1 },
1398     M32R_INSN_JC, "jc", "jc",
1399     { MNEM, ' ', OP (SR), 0 },
1400     { 16, 16, 0xfff0 }, 0x1cc0,
1401     (PTR) & fmt_jc_ops[0],
1402     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1403   },
1404 /* end-sanitize-m32rx */
1405 /* start-sanitize-m32rx */
1406 /* jnc $sr */
1407   {
1408     { 1, 1, 1, 1 },
1409     M32R_INSN_JNC, "jnc", "jnc",
1410     { MNEM, ' ', OP (SR), 0 },
1411     { 16, 16, 0xfff0 }, 0x1dc0,
1412     (PTR) & fmt_jc_ops[0],
1413     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1414   },
1415 /* end-sanitize-m32rx */
1416 /* jl $sr */
1417   {
1418     { 1, 1, 1, 1 },
1419     M32R_INSN_JL, "jl", "jl",
1420     { MNEM, ' ', OP (SR), 0 },
1421     { 16, 16, 0xfff0 }, 0x1ec0,
1422     (PTR) & fmt_jl_ops[0],
1423     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1424   },
1425 /* jmp $sr */
1426   {
1427     { 1, 1, 1, 1 },
1428     M32R_INSN_JMP, "jmp", "jmp",
1429     { MNEM, ' ', OP (SR), 0 },
1430     { 16, 16, 0xfff0 }, 0x1fc0,
1431     (PTR) & fmt_jmp_ops[0],
1432     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1433   },
1434 /* ld $dr,@$sr */
1435   {
1436     { 1, 1, 1, 1 },
1437     M32R_INSN_LD, "ld", "ld",
1438     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1439     { 16, 16, 0xf0f0 }, 0x20c0,
1440     (PTR) & fmt_ld_ops[0],
1441     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1442   },
1443 /* ld $dr,@($slo16,$sr) */
1444   {
1445     { 1, 1, 1, 1 },
1446     M32R_INSN_LD_D, "ld-d", "ld",
1447     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1448     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1449     (PTR) & fmt_ld_d_ops[0],
1450     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1451   },
1452 /* ldb $dr,@$sr */
1453   {
1454     { 1, 1, 1, 1 },
1455     M32R_INSN_LDB, "ldb", "ldb",
1456     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1457     { 16, 16, 0xf0f0 }, 0x2080,
1458     (PTR) & fmt_ldb_ops[0],
1459     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1460   },
1461 /* ldb $dr,@($slo16,$sr) */
1462   {
1463     { 1, 1, 1, 1 },
1464     M32R_INSN_LDB_D, "ldb-d", "ldb",
1465     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1466     { 32, 32, 0xf0f00000 }, 0xa0800000,
1467     (PTR) & fmt_ldb_d_ops[0],
1468     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1469   },
1470 /* ldh $dr,@$sr */
1471   {
1472     { 1, 1, 1, 1 },
1473     M32R_INSN_LDH, "ldh", "ldh",
1474     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1475     { 16, 16, 0xf0f0 }, 0x20a0,
1476     (PTR) & fmt_ldh_ops[0],
1477     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1478   },
1479 /* ldh $dr,@($slo16,$sr) */
1480   {
1481     { 1, 1, 1, 1 },
1482     M32R_INSN_LDH_D, "ldh-d", "ldh",
1483     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1484     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1485     (PTR) & fmt_ldh_d_ops[0],
1486     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1487   },
1488 /* ldub $dr,@$sr */
1489   {
1490     { 1, 1, 1, 1 },
1491     M32R_INSN_LDUB, "ldub", "ldub",
1492     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1493     { 16, 16, 0xf0f0 }, 0x2090,
1494     (PTR) & fmt_ldb_ops[0],
1495     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1496   },
1497 /* ldub $dr,@($slo16,$sr) */
1498   {
1499     { 1, 1, 1, 1 },
1500     M32R_INSN_LDUB_D, "ldub-d", "ldub",
1501     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1502     { 32, 32, 0xf0f00000 }, 0xa0900000,
1503     (PTR) & fmt_ldb_d_ops[0],
1504     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1505   },
1506 /* lduh $dr,@$sr */
1507   {
1508     { 1, 1, 1, 1 },
1509     M32R_INSN_LDUH, "lduh", "lduh",
1510     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1511     { 16, 16, 0xf0f0 }, 0x20b0,
1512     (PTR) & fmt_ldh_ops[0],
1513     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1514   },
1515 /* lduh $dr,@($slo16,$sr) */
1516   {
1517     { 1, 1, 1, 1 },
1518     M32R_INSN_LDUH_D, "lduh-d", "lduh",
1519     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1520     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1521     (PTR) & fmt_ldh_d_ops[0],
1522     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1523   },
1524 /* ld $dr,@$sr+ */
1525   {
1526     { 1, 1, 1, 1 },
1527     M32R_INSN_LD_PLUS, "ld-plus", "ld",
1528     { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1529     { 16, 16, 0xf0f0 }, 0x20e0,
1530     (PTR) & fmt_ld_plus_ops[0],
1531     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1532   },
1533 /* ld24 $dr,$uimm24 */
1534   {
1535     { 1, 1, 1, 1 },
1536     M32R_INSN_LD24, "ld24", "ld24",
1537     { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1538     { 32, 32, 0xf0000000 }, 0xe0000000,
1539     (PTR) & fmt_ld24_ops[0],
1540     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1541   },
1542 /* ldi8 $dr,$simm8 */
1543   {
1544     { 1, 1, 1, 1 },
1545     M32R_INSN_LDI8, "ldi8", "ldi8",
1546     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1547     { 16, 16, 0xf000 }, 0x6000,
1548     (PTR) & fmt_ldi8_ops[0],
1549     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1550   },
1551 /* ldi16 $dr,$hash$slo16 */
1552   {
1553     { 1, 1, 1, 1 },
1554     M32R_INSN_LDI16, "ldi16", "ldi16",
1555     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1556     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1557     (PTR) & fmt_ldi16_ops[0],
1558     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1559   },
1560 /* lock $dr,@$sr */
1561   {
1562     { 1, 1, 1, 1 },
1563     M32R_INSN_LOCK, "lock", "lock",
1564     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1565     { 16, 16, 0xf0f0 }, 0x20d0,
1566     (PTR) & fmt_lock_ops[0],
1567     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1568   },
1569 /* machi $src1,$src2 */
1570   {
1571     { 1, 1, 1, 1 },
1572     M32R_INSN_MACHI, "machi", "machi",
1573     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1574     { 16, 16, 0xf0f0 }, 0x3040,
1575     (PTR) & fmt_machi_ops[0],
1576     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1577   },
1578 /* start-sanitize-m32rx */
1579 /* machi $src1,$src2,$acc */
1580   {
1581     { 1, 1, 1, 1 },
1582     M32R_INSN_MACHI_A, "machi-a", "machi",
1583     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1584     { 16, 16, 0xf070 }, 0x3040,
1585     (PTR) & fmt_machi_a_ops[0],
1586     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1587   },
1588 /* end-sanitize-m32rx */
1589 /* maclo $src1,$src2 */
1590   {
1591     { 1, 1, 1, 1 },
1592     M32R_INSN_MACLO, "maclo", "maclo",
1593     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1594     { 16, 16, 0xf0f0 }, 0x3050,
1595     (PTR) & fmt_machi_ops[0],
1596     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1597   },
1598 /* start-sanitize-m32rx */
1599 /* maclo $src1,$src2,$acc */
1600   {
1601     { 1, 1, 1, 1 },
1602     M32R_INSN_MACLO_A, "maclo-a", "maclo",
1603     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1604     { 16, 16, 0xf070 }, 0x3050,
1605     (PTR) & fmt_machi_a_ops[0],
1606     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1607   },
1608 /* end-sanitize-m32rx */
1609 /* macwhi $src1,$src2 */
1610   {
1611     { 1, 1, 1, 1 },
1612     M32R_INSN_MACWHI, "macwhi", "macwhi",
1613     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1614     { 16, 16, 0xf0f0 }, 0x3060,
1615     (PTR) & fmt_machi_ops[0],
1616     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1617   },
1618 /* macwlo $src1,$src2 */
1619   {
1620     { 1, 1, 1, 1 },
1621     M32R_INSN_MACWLO, "macwlo", "macwlo",
1622     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1623     { 16, 16, 0xf0f0 }, 0x3070,
1624     (PTR) & fmt_machi_ops[0],
1625     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1626   },
1627 /* mul $dr,$sr */
1628   {
1629     { 1, 1, 1, 1 },
1630     M32R_INSN_MUL, "mul", "mul",
1631     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1632     { 16, 16, 0xf0f0 }, 0x1060,
1633     (PTR) & fmt_add_ops[0],
1634     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1635   },
1636 /* mulhi $src1,$src2 */
1637   {
1638     { 1, 1, 1, 1 },
1639     M32R_INSN_MULHI, "mulhi", "mulhi",
1640     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1641     { 16, 16, 0xf0f0 }, 0x3000,
1642     (PTR) & fmt_mulhi_ops[0],
1643     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1644   },
1645 /* start-sanitize-m32rx */
1646 /* mulhi $src1,$src2,$acc */
1647   {
1648     { 1, 1, 1, 1 },
1649     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
1650     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1651     { 16, 16, 0xf070 }, 0x3000,
1652     (PTR) & fmt_mulhi_a_ops[0],
1653     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1654   },
1655 /* end-sanitize-m32rx */
1656 /* mullo $src1,$src2 */
1657   {
1658     { 1, 1, 1, 1 },
1659     M32R_INSN_MULLO, "mullo", "mullo",
1660     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1661     { 16, 16, 0xf0f0 }, 0x3010,
1662     (PTR) & fmt_mulhi_ops[0],
1663     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1664   },
1665 /* start-sanitize-m32rx */
1666 /* mullo $src1,$src2,$acc */
1667   {
1668     { 1, 1, 1, 1 },
1669     M32R_INSN_MULLO_A, "mullo-a", "mullo",
1670     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1671     { 16, 16, 0xf070 }, 0x3010,
1672     (PTR) & fmt_mulhi_a_ops[0],
1673     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1674   },
1675 /* end-sanitize-m32rx */
1676 /* mulwhi $src1,$src2 */
1677   {
1678     { 1, 1, 1, 1 },
1679     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
1680     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1681     { 16, 16, 0xf0f0 }, 0x3020,
1682     (PTR) & fmt_mulhi_ops[0],
1683     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1684   },
1685 /* mulwlo $src1,$src2 */
1686   {
1687     { 1, 1, 1, 1 },
1688     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
1689     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1690     { 16, 16, 0xf0f0 }, 0x3030,
1691     (PTR) & fmt_mulhi_ops[0],
1692     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1693   },
1694 /* mv $dr,$sr */
1695   {
1696     { 1, 1, 1, 1 },
1697     M32R_INSN_MV, "mv", "mv",
1698     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1699     { 16, 16, 0xf0f0 }, 0x1080,
1700     (PTR) & fmt_mv_ops[0],
1701     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1702   },
1703 /* mvfachi $dr */
1704   {
1705     { 1, 1, 1, 1 },
1706     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
1707     { MNEM, ' ', OP (DR), 0 },
1708     { 16, 16, 0xf0ff }, 0x50f0,
1709     (PTR) & fmt_mvfachi_ops[0],
1710     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1711   },
1712 /* start-sanitize-m32rx */
1713 /* mvfachi $dr,$accs */
1714   {
1715     { 1, 1, 1, 1 },
1716     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
1717     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1718     { 16, 16, 0xf0f3 }, 0x50f0,
1719     (PTR) & fmt_mvfachi_a_ops[0],
1720     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1721   },
1722 /* end-sanitize-m32rx */
1723 /* mvfaclo $dr */
1724   {
1725     { 1, 1, 1, 1 },
1726     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
1727     { MNEM, ' ', OP (DR), 0 },
1728     { 16, 16, 0xf0ff }, 0x50f1,
1729     (PTR) & fmt_mvfachi_ops[0],
1730     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1731   },
1732 /* start-sanitize-m32rx */
1733 /* mvfaclo $dr,$accs */
1734   {
1735     { 1, 1, 1, 1 },
1736     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
1737     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1738     { 16, 16, 0xf0f3 }, 0x50f1,
1739     (PTR) & fmt_mvfachi_a_ops[0],
1740     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1741   },
1742 /* end-sanitize-m32rx */
1743 /* mvfacmi $dr */
1744   {
1745     { 1, 1, 1, 1 },
1746     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
1747     { MNEM, ' ', OP (DR), 0 },
1748     { 16, 16, 0xf0ff }, 0x50f2,
1749     (PTR) & fmt_mvfachi_ops[0],
1750     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1751   },
1752 /* start-sanitize-m32rx */
1753 /* mvfacmi $dr,$accs */
1754   {
1755     { 1, 1, 1, 1 },
1756     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
1757     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1758     { 16, 16, 0xf0f3 }, 0x50f2,
1759     (PTR) & fmt_mvfachi_a_ops[0],
1760     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1761   },
1762 /* end-sanitize-m32rx */
1763 /* mvfc $dr,$scr */
1764   {
1765     { 1, 1, 1, 1 },
1766     M32R_INSN_MVFC, "mvfc", "mvfc",
1767     { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
1768     { 16, 16, 0xf0f0 }, 0x1090,
1769     (PTR) & fmt_mvfc_ops[0],
1770     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1771   },
1772 /* mvtachi $src1 */
1773   {
1774     { 1, 1, 1, 1 },
1775     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
1776     { MNEM, ' ', OP (SRC1), 0 },
1777     { 16, 16, 0xf0ff }, 0x5070,
1778     (PTR) & fmt_mvtachi_ops[0],
1779     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1780   },
1781 /* start-sanitize-m32rx */
1782 /* mvtachi $src1,$accs */
1783   {
1784     { 1, 1, 1, 1 },
1785     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
1786     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1787     { 16, 16, 0xf0f3 }, 0x5070,
1788     (PTR) & fmt_mvtachi_a_ops[0],
1789     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1790   },
1791 /* end-sanitize-m32rx */
1792 /* mvtaclo $src1 */
1793   {
1794     { 1, 1, 1, 1 },
1795     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
1796     { MNEM, ' ', OP (SRC1), 0 },
1797     { 16, 16, 0xf0ff }, 0x5071,
1798     (PTR) & fmt_mvtachi_ops[0],
1799     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1800   },
1801 /* start-sanitize-m32rx */
1802 /* mvtaclo $src1,$accs */
1803   {
1804     { 1, 1, 1, 1 },
1805     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
1806     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1807     { 16, 16, 0xf0f3 }, 0x5071,
1808     (PTR) & fmt_mvtachi_a_ops[0],
1809     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1810   },
1811 /* end-sanitize-m32rx */
1812 /* mvtc $sr,$dcr */
1813   {
1814     { 1, 1, 1, 1 },
1815     M32R_INSN_MVTC, "mvtc", "mvtc",
1816     { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
1817     { 16, 16, 0xf0f0 }, 0x10a0,
1818     (PTR) & fmt_mvtc_ops[0],
1819     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1820   },
1821 /* neg $dr,$sr */
1822   {
1823     { 1, 1, 1, 1 },
1824     M32R_INSN_NEG, "neg", "neg",
1825     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1826     { 16, 16, 0xf0f0 }, 0x30,
1827     (PTR) & fmt_mv_ops[0],
1828     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1829   },
1830 /* nop */
1831   {
1832     { 1, 1, 1, 1 },
1833     M32R_INSN_NOP, "nop", "nop",
1834     { MNEM, 0 },
1835     { 16, 16, 0xffff }, 0x7000,
1836     (PTR) 0,
1837     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1838   },
1839 /* not $dr,$sr */
1840   {
1841     { 1, 1, 1, 1 },
1842     M32R_INSN_NOT, "not", "not",
1843     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1844     { 16, 16, 0xf0f0 }, 0xb0,
1845     (PTR) & fmt_mv_ops[0],
1846     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1847   },
1848 /* rac */
1849   {
1850     { 1, 1, 1, 1 },
1851     M32R_INSN_RAC, "rac", "rac",
1852     { MNEM, 0 },
1853     { 16, 16, 0xffff }, 0x5090,
1854     (PTR) & fmt_rac_ops[0],
1855     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1856   },
1857 /* start-sanitize-m32rx */
1858 /* rac $accd,$accs,$imm1 */
1859   {
1860     { 1, 1, 1, 1 },
1861     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
1862     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
1863     { 16, 16, 0xf3f2 }, 0x5090,
1864     (PTR) & fmt_rac_dsi_ops[0],
1865     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1866   },
1867 /* end-sanitize-m32rx */
1868 /* rach */
1869   {
1870     { 1, 1, 1, 1 },
1871     M32R_INSN_RACH, "rach", "rach",
1872     { MNEM, 0 },
1873     { 16, 16, 0xffff }, 0x5080,
1874     (PTR) & fmt_rac_ops[0],
1875     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1876   },
1877 /* start-sanitize-m32rx */
1878 /* rach $accd,$accs,$imm1 */
1879   {
1880     { 1, 1, 1, 1 },
1881     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
1882     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
1883     { 16, 16, 0xf3f2 }, 0x5080,
1884     (PTR) & fmt_rac_dsi_ops[0],
1885     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1886   },
1887 /* end-sanitize-m32rx */
1888 /* rte */
1889   {
1890     { 1, 1, 1, 1 },
1891     M32R_INSN_RTE, "rte", "rte",
1892     { MNEM, 0 },
1893     { 16, 16, 0xffff }, 0x10d6,
1894     (PTR) & fmt_rte_ops[0],
1895     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1896   },
1897 /* seth $dr,$hash$hi16 */
1898   {
1899     { 1, 1, 1, 1 },
1900     M32R_INSN_SETH, "seth", "seth",
1901     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
1902     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
1903     (PTR) & fmt_seth_ops[0],
1904     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1905   },
1906 /* sll $dr,$sr */
1907   {
1908     { 1, 1, 1, 1 },
1909     M32R_INSN_SLL, "sll", "sll",
1910     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1911     { 16, 16, 0xf0f0 }, 0x1040,
1912     (PTR) & fmt_add_ops[0],
1913     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1914   },
1915 /* sll3 $dr,$sr,$simm16 */
1916   {
1917     { 1, 1, 1, 1 },
1918     M32R_INSN_SLL3, "sll3", "sll3",
1919     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1920     { 32, 32, 0xf0f00000 }, 0x90c00000,
1921     (PTR) & fmt_sll3_ops[0],
1922     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1923   },
1924 /* slli $dr,$uimm5 */
1925   {
1926     { 1, 1, 1, 1 },
1927     M32R_INSN_SLLI, "slli", "slli",
1928     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1929     { 16, 16, 0xf0e0 }, 0x5040,
1930     (PTR) & fmt_slli_ops[0],
1931     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1932   },
1933 /* sra $dr,$sr */
1934   {
1935     { 1, 1, 1, 1 },
1936     M32R_INSN_SRA, "sra", "sra",
1937     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1938     { 16, 16, 0xf0f0 }, 0x1020,
1939     (PTR) & fmt_add_ops[0],
1940     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1941   },
1942 /* sra3 $dr,$sr,$simm16 */
1943   {
1944     { 1, 1, 1, 1 },
1945     M32R_INSN_SRA3, "sra3", "sra3",
1946     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1947     { 32, 32, 0xf0f00000 }, 0x90a00000,
1948     (PTR) & fmt_sll3_ops[0],
1949     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1950   },
1951 /* srai $dr,$uimm5 */
1952   {
1953     { 1, 1, 1, 1 },
1954     M32R_INSN_SRAI, "srai", "srai",
1955     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1956     { 16, 16, 0xf0e0 }, 0x5020,
1957     (PTR) & fmt_slli_ops[0],
1958     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1959   },
1960 /* srl $dr,$sr */
1961   {
1962     { 1, 1, 1, 1 },
1963     M32R_INSN_SRL, "srl", "srl",
1964     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1965     { 16, 16, 0xf0f0 }, 0x1000,
1966     (PTR) & fmt_add_ops[0],
1967     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1968   },
1969 /* srl3 $dr,$sr,$simm16 */
1970   {
1971     { 1, 1, 1, 1 },
1972     M32R_INSN_SRL3, "srl3", "srl3",
1973     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1974     { 32, 32, 0xf0f00000 }, 0x90800000,
1975     (PTR) & fmt_sll3_ops[0],
1976     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1977   },
1978 /* srli $dr,$uimm5 */
1979   {
1980     { 1, 1, 1, 1 },
1981     M32R_INSN_SRLI, "srli", "srli",
1982     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
1983     { 16, 16, 0xf0e0 }, 0x5000,
1984     (PTR) & fmt_slli_ops[0],
1985     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1986   },
1987 /* st $src1,@$src2 */
1988   {
1989     { 1, 1, 1, 1 },
1990     M32R_INSN_ST, "st", "st",
1991     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
1992     { 16, 16, 0xf0f0 }, 0x2040,
1993     (PTR) & fmt_st_ops[0],
1994     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1995   },
1996 /* st $src1,@($slo16,$src2) */
1997   {
1998     { 1, 1, 1, 1 },
1999     M32R_INSN_ST_D, "st-d", "st",
2000     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2001     { 32, 32, 0xf0f00000 }, 0xa0400000,
2002     (PTR) & fmt_st_d_ops[0],
2003     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2004   },
2005 /* stb $src1,@$src2 */
2006   {
2007     { 1, 1, 1, 1 },
2008     M32R_INSN_STB, "stb", "stb",
2009     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2010     { 16, 16, 0xf0f0 }, 0x2000,
2011     (PTR) & fmt_stb_ops[0],
2012     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2013   },
2014 /* stb $src1,@($slo16,$src2) */
2015   {
2016     { 1, 1, 1, 1 },
2017     M32R_INSN_STB_D, "stb-d", "stb",
2018     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2019     { 32, 32, 0xf0f00000 }, 0xa0000000,
2020     (PTR) & fmt_stb_d_ops[0],
2021     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2022   },
2023 /* sth $src1,@$src2 */
2024   {
2025     { 1, 1, 1, 1 },
2026     M32R_INSN_STH, "sth", "sth",
2027     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2028     { 16, 16, 0xf0f0 }, 0x2020,
2029     (PTR) & fmt_sth_ops[0],
2030     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2031   },
2032 /* sth $src1,@($slo16,$src2) */
2033   {
2034     { 1, 1, 1, 1 },
2035     M32R_INSN_STH_D, "sth-d", "sth",
2036     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2037     { 32, 32, 0xf0f00000 }, 0xa0200000,
2038     (PTR) & fmt_sth_d_ops[0],
2039     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2040   },
2041 /* st $src1,@+$src2 */
2042   {
2043     { 1, 1, 1, 1 },
2044     M32R_INSN_ST_PLUS, "st-plus", "st",
2045     { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2046     { 16, 16, 0xf0f0 }, 0x2060,
2047     (PTR) & fmt_st_plus_ops[0],
2048     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2049   },
2050 /* st $src1,@-$src2 */
2051   {
2052     { 1, 1, 1, 1 },
2053     M32R_INSN_ST_MINUS, "st-minus", "st",
2054     { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2055     { 16, 16, 0xf0f0 }, 0x2070,
2056     (PTR) & fmt_st_plus_ops[0],
2057     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2058   },
2059 /* sub $dr,$sr */
2060   {
2061     { 1, 1, 1, 1 },
2062     M32R_INSN_SUB, "sub", "sub",
2063     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2064     { 16, 16, 0xf0f0 }, 0x20,
2065     (PTR) & fmt_add_ops[0],
2066     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2067   },
2068 /* subv $dr,$sr */
2069   {
2070     { 1, 1, 1, 1 },
2071     M32R_INSN_SUBV, "subv", "subv",
2072     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2073     { 16, 16, 0xf0f0 }, 0x0,
2074     (PTR) & fmt_addv_ops[0],
2075     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2076   },
2077 /* subx $dr,$sr */
2078   {
2079     { 1, 1, 1, 1 },
2080     M32R_INSN_SUBX, "subx", "subx",
2081     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2082     { 16, 16, 0xf0f0 }, 0x10,
2083     (PTR) & fmt_addx_ops[0],
2084     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2085   },
2086 /* trap $uimm4 */
2087   {
2088     { 1, 1, 1, 1 },
2089     M32R_INSN_TRAP, "trap", "trap",
2090     { MNEM, ' ', OP (UIMM4), 0 },
2091     { 16, 16, 0xfff0 }, 0x10f0,
2092     (PTR) & fmt_trap_ops[0],
2093     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2094   },
2095 /* unlock $src1,@$src2 */
2096   {
2097     { 1, 1, 1, 1 },
2098     M32R_INSN_UNLOCK, "unlock", "unlock",
2099     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2100     { 16, 16, 0xf0f0 }, 0x2050,
2101     (PTR) & fmt_unlock_ops[0],
2102     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2103   },
2104 /* start-sanitize-m32rx */
2105 /* satb $dr,$sr */
2106   {
2107     { 1, 1, 1, 1 },
2108     M32R_INSN_SATB, "satb", "satb",
2109     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2110     { 32, 32, 0xf0f0ffff }, 0x80600300,
2111     (PTR) & fmt_satb_ops[0],
2112     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2113   },
2114 /* end-sanitize-m32rx */
2115 /* start-sanitize-m32rx */
2116 /* sath $dr,$sr */
2117   {
2118     { 1, 1, 1, 1 },
2119     M32R_INSN_SATH, "sath", "sath",
2120     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2121     { 32, 32, 0xf0f0ffff }, 0x80600200,
2122     (PTR) & fmt_satb_ops[0],
2123     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2124   },
2125 /* end-sanitize-m32rx */
2126 /* start-sanitize-m32rx */
2127 /* sat $dr,$sr */
2128   {
2129     { 1, 1, 1, 1 },
2130     M32R_INSN_SAT, "sat", "sat",
2131     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2132     { 32, 32, 0xf0f0ffff }, 0x80600000,
2133     (PTR) & fmt_sat_ops[0],
2134     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
2135   },
2136 /* end-sanitize-m32rx */
2137 /* start-sanitize-m32rx */
2138 /* pcmpbz $src2 */
2139   {
2140     { 1, 1, 1, 1 },
2141     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2142     { MNEM, ' ', OP (SRC2), 0 },
2143     { 16, 16, 0xfff0 }, 0x370,
2144     (PTR) & fmt_cmpz_ops[0],
2145     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
2146   },
2147 /* end-sanitize-m32rx */
2148 /* start-sanitize-m32rx */
2149 /* sadd */
2150   {
2151     { 1, 1, 1, 1 },
2152     M32R_INSN_SADD, "sadd", "sadd",
2153     { MNEM, 0 },
2154     { 16, 16, 0xffff }, 0x50e4,
2155     (PTR) & fmt_sadd_ops[0],
2156     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2157   },
2158 /* end-sanitize-m32rx */
2159 /* start-sanitize-m32rx */
2160 /* macwu1 $src1,$src2 */
2161   {
2162     { 1, 1, 1, 1 },
2163     M32R_INSN_MACWU1, "macwu1", "macwu1",
2164     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2165     { 16, 16, 0xf0f0 }, 0x50b0,
2166     (PTR) & fmt_macwu1_ops[0],
2167     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2168   },
2169 /* end-sanitize-m32rx */
2170 /* start-sanitize-m32rx */
2171 /* msblo $src1,$src2 */
2172   {
2173     { 1, 1, 1, 1 },
2174     M32R_INSN_MSBLO, "msblo", "msblo",
2175     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2176     { 16, 16, 0xf0f0 }, 0x50d0,
2177     (PTR) & fmt_machi_ops[0],
2178     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2179   },
2180 /* end-sanitize-m32rx */
2181 /* start-sanitize-m32rx */
2182 /* mulwu1 $src1,$src2 */
2183   {
2184     { 1, 1, 1, 1 },
2185     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2186     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2187     { 16, 16, 0xf0f0 }, 0x50a0,
2188     (PTR) & fmt_mulwu1_ops[0],
2189     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2190   },
2191 /* end-sanitize-m32rx */
2192 /* start-sanitize-m32rx */
2193 /* maclh1 $src1,$src2 */
2194   {
2195     { 1, 1, 1, 1 },
2196     M32R_INSN_MACLH1, "maclh1", "maclh1",
2197     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2198     { 16, 16, 0xf0f0 }, 0x50c0,
2199     (PTR) & fmt_macwu1_ops[0],
2200     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2201   },
2202 /* end-sanitize-m32rx */
2203 /* start-sanitize-m32rx */
2204 /* sc */
2205   {
2206     { 1, 1, 1, 1 },
2207     M32R_INSN_SC, "sc", "sc",
2208     { MNEM, 0 },
2209     { 16, 16, 0xffff }, 0x7401,
2210     (PTR) & fmt_sc_ops[0],
2211     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2212   },
2213 /* end-sanitize-m32rx */
2214 /* start-sanitize-m32rx */
2215 /* snc */
2216   {
2217     { 1, 1, 1, 1 },
2218     M32R_INSN_SNC, "snc", "snc",
2219     { MNEM, 0 },
2220     { 16, 16, 0xffff }, 0x7501,
2221     (PTR) & fmt_sc_ops[0],
2222     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2223   },
2224 /* end-sanitize-m32rx */
2225 };
2226
2227 #undef A
2228 #undef MNEM
2229 #undef OP
2230
2231 static CGEN_INSN_TABLE insn_table =
2232 {
2233   & m32r_cgen_insn_table_entries[0],
2234   sizeof (CGEN_INSN),
2235   MAX_INSNS,
2236   NULL
2237 };
2238
2239 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2240
2241 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2242 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2243 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2244
2245 /* The macro instruction table.  */
2246
2247 static const CGEN_INSN macro_insn_table_entries[] =
2248 {
2249 /* bc $disp8 */
2250   {
2251     { 1, 1, 1, 1 },
2252     -1, "bc8r", "bc",
2253     { MNEM, ' ', OP (DISP8), 0 },
2254     { 16, 16, 0xff00 }, 0x7c00,
2255     (PTR) 0,
2256     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2257   },
2258 /* bc $disp24 */
2259   {
2260     { 1, 1, 1, 1 },
2261     -1, "bc24r", "bc",
2262     { MNEM, ' ', OP (DISP24), 0 },
2263     { 32, 32, 0xff000000 }, 0xfc000000,
2264     (PTR) 0,
2265     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2266   },
2267 /* bl $disp8 */
2268   {
2269     { 1, 1, 1, 1 },
2270     -1, "bl8r", "bl",
2271     { MNEM, ' ', OP (DISP8), 0 },
2272     { 16, 16, 0xff00 }, 0x7e00,
2273     (PTR) 0,
2274     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2275   },
2276 /* bl $disp24 */
2277   {
2278     { 1, 1, 1, 1 },
2279     -1, "bl24r", "bl",
2280     { MNEM, ' ', OP (DISP24), 0 },
2281     { 32, 32, 0xff000000 }, 0xfe000000,
2282     (PTR) 0,
2283     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2284   },
2285 /* bcl $disp8 */
2286   {
2287     { 1, 1, 1, 1 },
2288     -1, "bcl8r", "bcl",
2289     { MNEM, ' ', OP (DISP8), 0 },
2290     { 16, 16, 0xff00 }, 0x7800,
2291     (PTR) 0,
2292     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2293   },
2294 /* bcl $disp24 */
2295   {
2296     { 1, 1, 1, 1 },
2297     -1, "bcl24r", "bcl",
2298     { MNEM, ' ', OP (DISP24), 0 },
2299     { 32, 32, 0xff000000 }, 0xf8000000,
2300     (PTR) 0,
2301     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2302   },
2303 /* bnc $disp8 */
2304   {
2305     { 1, 1, 1, 1 },
2306     -1, "bnc8r", "bnc",
2307     { MNEM, ' ', OP (DISP8), 0 },
2308     { 16, 16, 0xff00 }, 0x7d00,
2309     (PTR) 0,
2310     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2311   },
2312 /* bnc $disp24 */
2313   {
2314     { 1, 1, 1, 1 },
2315     -1, "bnc24r", "bnc",
2316     { MNEM, ' ', OP (DISP24), 0 },
2317     { 32, 32, 0xff000000 }, 0xfd000000,
2318     (PTR) 0,
2319     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2320   },
2321 /* bra $disp8 */
2322   {
2323     { 1, 1, 1, 1 },
2324     -1, "bra8r", "bra",
2325     { MNEM, ' ', OP (DISP8), 0 },
2326     { 16, 16, 0xff00 }, 0x7f00,
2327     (PTR) 0,
2328     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2329   },
2330 /* bra $disp24 */
2331   {
2332     { 1, 1, 1, 1 },
2333     -1, "bra24r", "bra",
2334     { MNEM, ' ', OP (DISP24), 0 },
2335     { 32, 32, 0xff000000 }, 0xff000000,
2336     (PTR) 0,
2337     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2338   },
2339 /* bncl $disp8 */
2340   {
2341     { 1, 1, 1, 1 },
2342     -1, "bncl8r", "bncl",
2343     { MNEM, ' ', OP (DISP8), 0 },
2344     { 16, 16, 0xff00 }, 0x7900,
2345     (PTR) 0,
2346     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2347   },
2348 /* bncl $disp24 */
2349   {
2350     { 1, 1, 1, 1 },
2351     -1, "bncl24r", "bncl",
2352     { MNEM, ' ', OP (DISP24), 0 },
2353     { 32, 32, 0xff000000 }, 0xf9000000,
2354     (PTR) 0,
2355     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2356   },
2357 /* ld $dr,@($sr) */
2358   {
2359     { 1, 1, 1, 1 },
2360     -1, "ld-2", "ld",
2361     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2362     { 16, 16, 0xf0f0 }, 0x20c0,
2363     (PTR) 0,
2364     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2365   },
2366 /* ld $dr,@($sr,$slo16) */
2367   {
2368     { 1, 1, 1, 1 },
2369     -1, "ld-d2", "ld",
2370     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2371     { 32, 32, 0xf0f00000 }, 0xa0c00000,
2372     (PTR) 0,
2373     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2374   },
2375 /* ldb $dr,@($sr) */
2376   {
2377     { 1, 1, 1, 1 },
2378     -1, "ldb-2", "ldb",
2379     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2380     { 16, 16, 0xf0f0 }, 0x2080,
2381     (PTR) 0,
2382     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2383   },
2384 /* ldb $dr,@($sr,$slo16) */
2385   {
2386     { 1, 1, 1, 1 },
2387     -1, "ldb-d2", "ldb",
2388     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2389     { 32, 32, 0xf0f00000 }, 0xa0800000,
2390     (PTR) 0,
2391     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2392   },
2393 /* ldh $dr,@($sr) */
2394   {
2395     { 1, 1, 1, 1 },
2396     -1, "ldh-2", "ldh",
2397     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2398     { 16, 16, 0xf0f0 }, 0x20a0,
2399     (PTR) 0,
2400     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2401   },
2402 /* ldh $dr,@($sr,$slo16) */
2403   {
2404     { 1, 1, 1, 1 },
2405     -1, "ldh-d2", "ldh",
2406     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2407     { 32, 32, 0xf0f00000 }, 0xa0a00000,
2408     (PTR) 0,
2409     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2410   },
2411 /* ldub $dr,@($sr) */
2412   {
2413     { 1, 1, 1, 1 },
2414     -1, "ldub-2", "ldub",
2415     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2416     { 16, 16, 0xf0f0 }, 0x2090,
2417     (PTR) 0,
2418     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2419   },
2420 /* ldub $dr,@($sr,$slo16) */
2421   {
2422     { 1, 1, 1, 1 },
2423     -1, "ldub-d2", "ldub",
2424     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2425     { 32, 32, 0xf0f00000 }, 0xa0900000,
2426     (PTR) 0,
2427     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2428   },
2429 /* lduh $dr,@($sr) */
2430   {
2431     { 1, 1, 1, 1 },
2432     -1, "lduh-2", "lduh",
2433     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
2434     { 16, 16, 0xf0f0 }, 0x20b0,
2435     (PTR) 0,
2436     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2437   },
2438 /* lduh $dr,@($sr,$slo16) */
2439   {
2440     { 1, 1, 1, 1 },
2441     -1, "lduh-d2", "lduh",
2442     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
2443     { 32, 32, 0xf0f00000 }, 0xa0b00000,
2444     (PTR) 0,
2445     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2446   },
2447 /* pop $dr */
2448   {
2449     { 1, 1, 1, 1 },
2450     -1, "pop", "pop",
2451     { MNEM, ' ', OP (DR), 0 },
2452     { 16, 16, 0xf0ff }, 0x20ef,
2453     (PTR) 0,
2454     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2455   },
2456 /* ldi $dr,$simm8 */
2457   {
2458     { 1, 1, 1, 1 },
2459     -1, "ldi8a", "ldi",
2460     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
2461     { 16, 16, 0xf000 }, 0x6000,
2462     (PTR) 0,
2463     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2464   },
2465 /* ldi $dr,$hash$slo16 */
2466   {
2467     { 1, 1, 1, 1 },
2468     -1, "ldi16a", "ldi",
2469     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
2470     { 32, 32, 0xf0ff0000 }, 0x90f00000,
2471     (PTR) 0,
2472     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2473   },
2474 /* rac $accd */
2475   {
2476     { 1, 1, 1, 1 },
2477     -1, "rac-d", "rac",
2478     { MNEM, ' ', OP (ACCD), 0 },
2479     { 16, 16, 0xf3ff }, 0x5090,
2480     (PTR) 0,
2481     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2482   },
2483 /* rac $accd,$accs */
2484   {
2485     { 1, 1, 1, 1 },
2486     -1, "rac-ds", "rac",
2487     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2488     { 16, 16, 0xf3f3 }, 0x5090,
2489     (PTR) 0,
2490     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2491   },
2492 /* rach $accd */
2493   {
2494     { 1, 1, 1, 1 },
2495     -1, "rach-d", "rach",
2496     { MNEM, ' ', OP (ACCD), 0 },
2497     { 16, 16, 0xf3ff }, 0x5080,
2498     (PTR) 0,
2499     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2500   },
2501 /* rach $accd,$accs */
2502   {
2503     { 1, 1, 1, 1 },
2504     -1, "rach-ds", "rach",
2505     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2506     { 16, 16, 0xf3f3 }, 0x5080,
2507     (PTR) 0,
2508     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2509   },
2510 /* st $src1,@($src2) */
2511   {
2512     { 1, 1, 1, 1 },
2513     -1, "st-2", "st",
2514     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2515     { 16, 16, 0xf0f0 }, 0x2040,
2516     (PTR) 0,
2517     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2518   },
2519 /* st $src1,@($src2,$slo16) */
2520   {
2521     { 1, 1, 1, 1 },
2522     -1, "st-d2", "st",
2523     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2524     { 32, 32, 0xf0f00000 }, 0xa0400000,
2525     (PTR) 0,
2526     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2527   },
2528 /* stb $src1,@($src2) */
2529   {
2530     { 1, 1, 1, 1 },
2531     -1, "stb-2", "stb",
2532     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2533     { 16, 16, 0xf0f0 }, 0x2000,
2534     (PTR) 0,
2535     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2536   },
2537 /* stb $src1,@($src2,$slo16) */
2538   {
2539     { 1, 1, 1, 1 },
2540     -1, "stb-d2", "stb",
2541     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2542     { 32, 32, 0xf0f00000 }, 0xa0000000,
2543     (PTR) 0,
2544     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2545   },
2546 /* sth $src1,@($src2) */
2547   {
2548     { 1, 1, 1, 1 },
2549     -1, "sth-2", "sth",
2550     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2551     { 16, 16, 0xf0f0 }, 0x2020,
2552     (PTR) 0,
2553     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2554   },
2555 /* sth $src1,@($src2,$slo16) */
2556   {
2557     { 1, 1, 1, 1 },
2558     -1, "sth-d2", "sth",
2559     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2560     { 32, 32, 0xf0f00000 }, 0xa0200000,
2561     (PTR) 0,
2562     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2563   },
2564 /* push $src1 */
2565   {
2566     { 1, 1, 1, 1 },
2567     -1, "push", "push",
2568     { MNEM, ' ', OP (SRC1), 0 },
2569     { 16, 16, 0xf0ff }, 0x207f,
2570     (PTR) 0,
2571     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2572   },
2573 };
2574
2575 #undef A
2576 #undef MNEM
2577 #undef OP
2578
2579 static CGEN_INSN_TABLE macro_insn_table =
2580 {
2581   & macro_insn_table_entries[0],
2582   sizeof (CGEN_INSN),
2583   (sizeof (macro_insn_table_entries) /
2584    sizeof (macro_insn_table_entries[0])),
2585   NULL
2586 };
2587
2588 /* The hash functions are recorded here to help keep assembler code out of
2589    the disassembler and vice versa.
2590
2591 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
2592 static unsigned int asm_hash_insn PARAMS ((const char *));
2593 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
2594 static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
2595
2596 /* Return non-zero if INSN is to be added to the hash table.
2597    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2598
2599 static int
2600 asm_hash_insn_p (insn)
2601      const CGEN_INSN * insn;
2602 {
2603   return CGEN_ASM_HASH_P (insn);
2604 }
2605
2606 static int
2607 dis_hash_insn_p (insn)
2608      const CGEN_INSN * insn;
2609 {
2610   /* If building the hash table and the NO-DIS attribute is present,
2611      ignore.  */
2612   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2613     return 0;
2614   return CGEN_DIS_HASH_P (insn);
2615 }
2616
2617 /* The result is the hash value of the insn.
2618    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2619
2620 static unsigned int
2621 asm_hash_insn (mnem)
2622      const char * mnem;
2623 {
2624   return CGEN_ASM_HASH (mnem);
2625 }
2626
2627 static unsigned int
2628 dis_hash_insn (buf, value)
2629      const char * buf;
2630      unsigned long value;
2631 {
2632   return CGEN_DIS_HASH (buf, value);
2633 }
2634
2635 const CGEN_OPCODE_TABLE m32r_cgen_opcode_table =
2636 {
2637   & m32r_cgen_hw_entries[0],
2638   /*& m32r_cgen_operand_table[0], - FIXME:wip */
2639   & insn_table,
2640   & macro_insn_table,
2641   asm_hash_insn_p, asm_hash_insn, CGEN_ASM_HASH_SIZE,
2642   dis_hash_insn_p, dis_hash_insn, CGEN_DIS_HASH_SIZE
2643 };
2644
2645 void
2646 m32r_cgen_init_tables (mach)
2647     int mach;
2648 {
2649 }
2650
2651 /* Getting values from cgen_fields is handled by a collection of functions.
2652    They are distinguished by the type of the VALUE argument they return.
2653    TODO: floating point, inlining support, remove cases where result type
2654    not appropriate.  */
2655
2656 int
2657 m32r_cgen_get_int_operand (opindex, fields)
2658      int opindex;
2659      const CGEN_FIELDS * fields;
2660 {
2661   int value;
2662
2663   switch (opindex)
2664     {
2665     case M32R_OPERAND_SR :
2666       value = fields->f_r2;
2667       break;
2668     case M32R_OPERAND_DR :
2669       value = fields->f_r1;
2670       break;
2671     case M32R_OPERAND_SRC1 :
2672       value = fields->f_r1;
2673       break;
2674     case M32R_OPERAND_SRC2 :
2675       value = fields->f_r2;
2676       break;
2677     case M32R_OPERAND_SCR :
2678       value = fields->f_r2;
2679       break;
2680     case M32R_OPERAND_DCR :
2681       value = fields->f_r1;
2682       break;
2683     case M32R_OPERAND_SIMM8 :
2684       value = fields->f_simm8;
2685       break;
2686     case M32R_OPERAND_SIMM16 :
2687       value = fields->f_simm16;
2688       break;
2689     case M32R_OPERAND_UIMM4 :
2690       value = fields->f_uimm4;
2691       break;
2692     case M32R_OPERAND_UIMM5 :
2693       value = fields->f_uimm5;
2694       break;
2695     case M32R_OPERAND_UIMM16 :
2696       value = fields->f_uimm16;
2697       break;
2698 /* start-sanitize-m32rx */
2699     case M32R_OPERAND_IMM1 :
2700       value = fields->f_imm1;
2701       break;
2702 /* end-sanitize-m32rx */
2703 /* start-sanitize-m32rx */
2704     case M32R_OPERAND_ACCD :
2705       value = fields->f_accd;
2706       break;
2707 /* end-sanitize-m32rx */
2708 /* start-sanitize-m32rx */
2709     case M32R_OPERAND_ACCS :
2710       value = fields->f_accs;
2711       break;
2712 /* end-sanitize-m32rx */
2713 /* start-sanitize-m32rx */
2714     case M32R_OPERAND_ACC :
2715       value = fields->f_acc;
2716       break;
2717 /* end-sanitize-m32rx */
2718     case M32R_OPERAND_HASH :
2719       value = fields->f_nil;
2720       break;
2721     case M32R_OPERAND_HI16 :
2722       value = fields->f_hi16;
2723       break;
2724     case M32R_OPERAND_SLO16 :
2725       value = fields->f_simm16;
2726       break;
2727     case M32R_OPERAND_ULO16 :
2728       value = fields->f_uimm16;
2729       break;
2730     case M32R_OPERAND_UIMM24 :
2731       value = fields->f_uimm24;
2732       break;
2733     case M32R_OPERAND_DISP8 :
2734       value = fields->f_disp8;
2735       break;
2736     case M32R_OPERAND_DISP16 :
2737       value = fields->f_disp16;
2738       break;
2739     case M32R_OPERAND_DISP24 :
2740       value = fields->f_disp24;
2741       break;
2742
2743     default :
2744       /* xgettext:c-format */
2745       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2746                        opindex);
2747       abort ();
2748   }
2749
2750   return value;
2751 }
2752
2753 bfd_vma
2754 m32r_cgen_get_vma_operand (opindex, fields)
2755      int opindex;
2756      const CGEN_FIELDS * fields;
2757 {
2758   bfd_vma value;
2759
2760   switch (opindex)
2761     {
2762     case M32R_OPERAND_SR :
2763       value = fields->f_r2;
2764       break;
2765     case M32R_OPERAND_DR :
2766       value = fields->f_r1;
2767       break;
2768     case M32R_OPERAND_SRC1 :
2769       value = fields->f_r1;
2770       break;
2771     case M32R_OPERAND_SRC2 :
2772       value = fields->f_r2;
2773       break;
2774     case M32R_OPERAND_SCR :
2775       value = fields->f_r2;
2776       break;
2777     case M32R_OPERAND_DCR :
2778       value = fields->f_r1;
2779       break;
2780     case M32R_OPERAND_SIMM8 :
2781       value = fields->f_simm8;
2782       break;
2783     case M32R_OPERAND_SIMM16 :
2784       value = fields->f_simm16;
2785       break;
2786     case M32R_OPERAND_UIMM4 :
2787       value = fields->f_uimm4;
2788       break;
2789     case M32R_OPERAND_UIMM5 :
2790       value = fields->f_uimm5;
2791       break;
2792     case M32R_OPERAND_UIMM16 :
2793       value = fields->f_uimm16;
2794       break;
2795 /* start-sanitize-m32rx */
2796     case M32R_OPERAND_IMM1 :
2797       value = fields->f_imm1;
2798       break;
2799 /* end-sanitize-m32rx */
2800 /* start-sanitize-m32rx */
2801     case M32R_OPERAND_ACCD :
2802       value = fields->f_accd;
2803       break;
2804 /* end-sanitize-m32rx */
2805 /* start-sanitize-m32rx */
2806     case M32R_OPERAND_ACCS :
2807       value = fields->f_accs;
2808       break;
2809 /* end-sanitize-m32rx */
2810 /* start-sanitize-m32rx */
2811     case M32R_OPERAND_ACC :
2812       value = fields->f_acc;
2813       break;
2814 /* end-sanitize-m32rx */
2815     case M32R_OPERAND_HASH :
2816       value = fields->f_nil;
2817       break;
2818     case M32R_OPERAND_HI16 :
2819       value = fields->f_hi16;
2820       break;
2821     case M32R_OPERAND_SLO16 :
2822       value = fields->f_simm16;
2823       break;
2824     case M32R_OPERAND_ULO16 :
2825       value = fields->f_uimm16;
2826       break;
2827     case M32R_OPERAND_UIMM24 :
2828       value = fields->f_uimm24;
2829       break;
2830     case M32R_OPERAND_DISP8 :
2831       value = fields->f_disp8;
2832       break;
2833     case M32R_OPERAND_DISP16 :
2834       value = fields->f_disp16;
2835       break;
2836     case M32R_OPERAND_DISP24 :
2837       value = fields->f_disp24;
2838       break;
2839
2840     default :
2841       /* xgettext:c-format */
2842       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2843                        opindex);
2844       abort ();
2845   }
2846
2847   return value;
2848 }
2849
2850 /* Stuffing values in cgen_fields is handled by a collection of functions.
2851    They are distinguished by the type of the VALUE argument they accept.
2852    TODO: floating point, inlining support, remove cases where argument type
2853    not appropriate.  */
2854
2855 void
2856 m32r_cgen_set_int_operand (opindex, fields, value)
2857      int opindex;
2858      CGEN_FIELDS * fields;
2859      int value;
2860 {
2861   switch (opindex)
2862     {
2863     case M32R_OPERAND_SR :
2864       fields->f_r2 = value;
2865       break;
2866     case M32R_OPERAND_DR :
2867       fields->f_r1 = value;
2868       break;
2869     case M32R_OPERAND_SRC1 :
2870       fields->f_r1 = value;
2871       break;
2872     case M32R_OPERAND_SRC2 :
2873       fields->f_r2 = value;
2874       break;
2875     case M32R_OPERAND_SCR :
2876       fields->f_r2 = value;
2877       break;
2878     case M32R_OPERAND_DCR :
2879       fields->f_r1 = value;
2880       break;
2881     case M32R_OPERAND_SIMM8 :
2882       fields->f_simm8 = value;
2883       break;
2884     case M32R_OPERAND_SIMM16 :
2885       fields->f_simm16 = value;
2886       break;
2887     case M32R_OPERAND_UIMM4 :
2888       fields->f_uimm4 = value;
2889       break;
2890     case M32R_OPERAND_UIMM5 :
2891       fields->f_uimm5 = value;
2892       break;
2893     case M32R_OPERAND_UIMM16 :
2894       fields->f_uimm16 = value;
2895       break;
2896 /* start-sanitize-m32rx */
2897     case M32R_OPERAND_IMM1 :
2898       fields->f_imm1 = value;
2899       break;
2900 /* end-sanitize-m32rx */
2901 /* start-sanitize-m32rx */
2902     case M32R_OPERAND_ACCD :
2903       fields->f_accd = value;
2904       break;
2905 /* end-sanitize-m32rx */
2906 /* start-sanitize-m32rx */
2907     case M32R_OPERAND_ACCS :
2908       fields->f_accs = value;
2909       break;
2910 /* end-sanitize-m32rx */
2911 /* start-sanitize-m32rx */
2912     case M32R_OPERAND_ACC :
2913       fields->f_acc = value;
2914       break;
2915 /* end-sanitize-m32rx */
2916     case M32R_OPERAND_HASH :
2917       fields->f_nil = value;
2918       break;
2919     case M32R_OPERAND_HI16 :
2920       fields->f_hi16 = value;
2921       break;
2922     case M32R_OPERAND_SLO16 :
2923       fields->f_simm16 = value;
2924       break;
2925     case M32R_OPERAND_ULO16 :
2926       fields->f_uimm16 = value;
2927       break;
2928     case M32R_OPERAND_UIMM24 :
2929       fields->f_uimm24 = value;
2930       break;
2931     case M32R_OPERAND_DISP8 :
2932       fields->f_disp8 = value;
2933       break;
2934     case M32R_OPERAND_DISP16 :
2935       fields->f_disp16 = value;
2936       break;
2937     case M32R_OPERAND_DISP24 :
2938       fields->f_disp24 = value;
2939       break;
2940
2941     default :
2942       /* xgettext:c-format */
2943       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2944                        opindex);
2945       abort ();
2946   }
2947 }
2948
2949 void
2950 m32r_cgen_set_vma_operand (opindex, fields, value)
2951      int opindex;
2952      CGEN_FIELDS * fields;
2953      bfd_vma value;
2954 {
2955   switch (opindex)
2956     {
2957     case M32R_OPERAND_SR :
2958       fields->f_r2 = value;
2959       break;
2960     case M32R_OPERAND_DR :
2961       fields->f_r1 = value;
2962       break;
2963     case M32R_OPERAND_SRC1 :
2964       fields->f_r1 = value;
2965       break;
2966     case M32R_OPERAND_SRC2 :
2967       fields->f_r2 = value;
2968       break;
2969     case M32R_OPERAND_SCR :
2970       fields->f_r2 = value;
2971       break;
2972     case M32R_OPERAND_DCR :
2973       fields->f_r1 = value;
2974       break;
2975     case M32R_OPERAND_SIMM8 :
2976       fields->f_simm8 = value;
2977       break;
2978     case M32R_OPERAND_SIMM16 :
2979       fields->f_simm16 = value;
2980       break;
2981     case M32R_OPERAND_UIMM4 :
2982       fields->f_uimm4 = value;
2983       break;
2984     case M32R_OPERAND_UIMM5 :
2985       fields->f_uimm5 = value;
2986       break;
2987     case M32R_OPERAND_UIMM16 :
2988       fields->f_uimm16 = value;
2989       break;
2990 /* start-sanitize-m32rx */
2991     case M32R_OPERAND_IMM1 :
2992       fields->f_imm1 = value;
2993       break;
2994 /* end-sanitize-m32rx */
2995 /* start-sanitize-m32rx */
2996     case M32R_OPERAND_ACCD :
2997       fields->f_accd = value;
2998       break;
2999 /* end-sanitize-m32rx */
3000 /* start-sanitize-m32rx */
3001     case M32R_OPERAND_ACCS :
3002       fields->f_accs = value;
3003       break;
3004 /* end-sanitize-m32rx */
3005 /* start-sanitize-m32rx */
3006     case M32R_OPERAND_ACC :
3007       fields->f_acc = value;
3008       break;
3009 /* end-sanitize-m32rx */
3010     case M32R_OPERAND_HASH :
3011       fields->f_nil = value;
3012       break;
3013     case M32R_OPERAND_HI16 :
3014       fields->f_hi16 = value;
3015       break;
3016     case M32R_OPERAND_SLO16 :
3017       fields->f_simm16 = value;
3018       break;
3019     case M32R_OPERAND_ULO16 :
3020       fields->f_uimm16 = value;
3021       break;
3022     case M32R_OPERAND_UIMM24 :
3023       fields->f_uimm24 = value;
3024       break;
3025     case M32R_OPERAND_DISP8 :
3026       fields->f_disp8 = value;
3027       break;
3028     case M32R_OPERAND_DISP16 :
3029       fields->f_disp16 = value;
3030       break;
3031     case M32R_OPERAND_DISP24 :
3032       fields->f_disp24 = value;
3033       break;
3034
3035     default :
3036       /* xgettext:c-format */
3037       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3038                        opindex);
3039       abort ();
3040   }
3041 }
3042