opcodes/m32r-opc.h

   1 /* Instruction description for m32r.
   2
   3 This file is machine generated.
   4
   5 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef m32r_OPC_H
  26 #define m32r_OPC_H
  27
  28 #define CGEN_ARCH m32r
  29 /* Given symbol S, return m32r_cgen_<s>.  */
  30 #define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
  31
  32 #define CGEN_WORD_BITSIZE 32
  33 #define CGEN_DEFAULT_INSN_BITSIZE 32
  34 #define CGEN_BASE_INSN_BITSIZE 32
  35 #define CGEN_MAX_INSN_BITSIZE 32
  36 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  37 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  38 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  39 #define CGEN_INT_INSN
  40
  41 /* +1 because the first entry is reserved (null) */
  42 #define CGEN_NUM_INSNS (127 + 1)
  43 #define CGEN_NUM_OPERANDS (21)
  44
  45 /* Number of non-boolean attributes. */
  46 #define CGEN_MAX_INSN_ATTRS 0
  47 #define CGEN_MAX_OPERAND_ATTRS 0
  48
  49 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  50
  51 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  52    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  53    we can't hash on everything up to the space.  */
  54 #define CGEN_MNEMONIC_OPERANDS
  55
  56 /* Number of architecture variants.  */
  57 #define MAX_MACHS 1
  58
  59 /* Enums.  */
  60
  61 /* Enum declaration for insn format enums.  */
  62 typedef enum insn_op1 {
  63   OP1_0 = 0, OP1_1 = 1, OP1_2 = 2, OP1_3 = 3,
  64   OP1_4 = 4, OP1_5 = 5, OP1_6 = 6, OP1_7 = 7,
  65   OP1_8 = 8, OP1_9 = 9, OP1_10 = 10, OP1_11 = 11,
  66   OP1_12 = 12, OP1_13 = 13, OP1_14 = 14, OP1_15 = 15
  67 } INSN_OP1;
  68
  69 /* Enum declaration for op2 enums.  */
  70 typedef enum insn_op2 {
  71   OP2_0 = 0, OP2_1 = 1, OP2_2 = 2, OP2_3 = 3,
  72   OP2_4 = 4, OP2_5 = 5, OP2_6 = 6, OP2_7 = 7,
  73   OP2_8 = 8, OP2_9 = 9, OP2_10 = 10, OP2_11 = 11,
  74   OP2_12 = 12, OP2_13 = 13, OP2_14 = 14, OP2_15 = 15
  75 } INSN_OP2;
  76
  77 /* Enum declaration for m32r operand types.  */
  78 typedef enum cgen_operand_type {
  79   M32R_OPERAND_PC = 0, M32R_OPERAND_SR = 1, M32R_OPERAND_DR = 2, M32R_OPERAND_SRC1 = 3,
  80   M32R_OPERAND_SRC2 = 4, M32R_OPERAND_SCR = 5, M32R_OPERAND_DCR = 6, M32R_OPERAND_SIMM8 = 7,
  81   M32R_OPERAND_SIMM16 = 8, M32R_OPERAND_UIMM4 = 9, M32R_OPERAND_UIMM5 = 10, M32R_OPERAND_UIMM16 = 11,
  82   M32R_OPERAND_HI16 = 12, M32R_OPERAND_SLO16 = 13, M32R_OPERAND_ULO16 = 14, M32R_OPERAND_UIMM24 = 15,
  83   M32R_OPERAND_DISP8 = 16, M32R_OPERAND_DISP16 = 17, M32R_OPERAND_DISP24 = 18, M32R_OPERAND_CONDBIT = 19,
  84   M32R_OPERAND_ACCUM = 20
  85 } CGEN_OPERAND_TYPE;
  86
  87 /* Non-boolean attributes.  */
  88
  89 /* Enum declaration for machine type selection.  */
  90 typedef enum mach_attr {
  91   MACH_M32R = 0
  92 } MACH_ATTR;
  93
  94 /* Operand and instruction attribute indices.  */
  95
  96 /* Enum declaration for cgen_operand attrs.  */
  97 typedef enum cgen_operand_attr {
  98   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC,
  99   CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT,
 100   CGEN_OPERAND_UNSIGNED
 101 } CGEN_OPERAND_ATTR;
 102
 103 /* Enum declaration for cgen_insn attrs.  */
 104 typedef enum cgen_insn_attr {
 105   CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_RELAX,
 106   CGEN_INSN_RELAX_BC, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BRA,
 107   CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
 108 } CGEN_INSN_ATTR;
 109
 110 /* Insn types are used by the simulator.  */
 111 /* Enum declaration for m32r instruction types.  */
 112 typedef enum cgen_insn_type {
 113   M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND,
 114   M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR,
 115   M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3,
 116   M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC8_S, M32R_INSN_BC24,
 117   M32R_INSN_BC24_L, M32R_INSN_BEQ, M32R_INSN_BEQZ, M32R_INSN_BGEZ,
 118   M32R_INSN_BGTZ, M32R_INSN_BLEZ, M32R_INSN_BLTZ, M32R_INSN_BNEZ,
 119   M32R_INSN_BL8, M32R_INSN_BL8_S, M32R_INSN_BL24, M32R_INSN_BL24_L,
 120   M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L,
 121   M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24,
 122   M32R_INSN_BRA24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU,
 123   M32R_INSN_CMPUI, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM,
 124   M32R_INSN_REMU, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD,
 125   M32R_INSN_LD_2, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB,
 126   M32R_INSN_LDB_2, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH,
 127   M32R_INSN_LDH_2, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB,
 128   M32R_INSN_LDUB_2, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH,
 129   M32R_INSN_LDUH_2, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS,
 130   M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI8A, M32R_INSN_LDI16,
 131   M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACLO,
 132   M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI,
 133   M32R_INSN_MULLO, M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV,
 134   M32R_INSN_MVFACHI, M32R_INSN_MVFACLO, M32R_INSN_MVFACMI, M32R_INSN_MVFC,
 135   M32R_INSN_MVTACHI, M32R_INSN_MVTACLO, M32R_INSN_MVTC, M32R_INSN_NEG,
 136   M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC, M32R_INSN_RACH,
 137   M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3,
 138   M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI,
 139   M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST,
 140   M32R_INSN_ST_2, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB,
 141   M32R_INSN_STB_2, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH,
 142   M32R_INSN_STH_2, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS,
 143   M32R_INSN_ST_MINUS, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX,
 144   M32R_INSN_TRAP, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP,
 145   M32R_INSN_MAX
 146 } CGEN_INSN_TYPE;
 147
 148 /* Index of `illegal' insn place holder.  */
 149 #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
 150 /* Total number of insns in table.  */
 151 #define CGEN_MAX_INSNS ((int) M32R_INSN_MAX)
 152
 153 /* cgen.h uses things we just defined.  */
 154 #include "opcode/cgen.h"
 155
 156 /* This struct records data prior to insertion or after extraction.  */
 157 typedef struct cgen_fields
 158 {  long f_nil;
 159   long f_op1;
 160   long f_op2;
 161   long f_cond;
 162   long f_r1;
 163   long f_r2;
 164   long f_simm8;
 165   long f_simm16;
 166   long f_shift_op2;
 167   long f_uimm4;
 168   long f_uimm5;
 169   long f_uimm16;
 170   long f_uimm24;
 171   long f_hi16;
 172   long f_disp8;
 173   long f_disp16;
 174   long f_disp24;
 175   int length;
 176 } CGEN_FIELDS;
 177
 178 /* Attributes.  */
 179 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 180 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 181
 182 extern CGEN_KEYWORD m32r_cgen_opval_mach;
 183 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 184 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 185
 186 #define CGEN_INIT_PARSE() \
 187 {\
 188 }
 189 #define CGEN_INIT_INSERT() \
 190 {\
 191 }
 192 #define CGEN_INIT_EXTRACT() \
 193 {\
 194 }
 195 #define CGEN_INIT_PRINT() \
 196 {\
 197 }
 198
 199 /* -- opc.h */
 200
 201 #undef CGEN_DIS_HASH_SIZE
 202 #define CGEN_DIS_HASH_SIZE 256
 203 #undef CGEN_DIS_HASH
 204 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 205 #define CGEN_DIS_HASH(buffer, insn) \
 206 (X (buffer) | \
 207  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
 208   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
 209   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 210
 211 /* -- */
 212
 213
 214 #endif /* m32r_OPC_H */