opcodes/m32r-opc.h

   1 /* Instruction description for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef M32R_OPC_H
  26 #define M32R_OPC_H
  27
  28 #define CGEN_ARCH m32r
  29
  30 /* Given symbol S, return m32r_cgen_<s>.  */
  31 #define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_M32R
  35 /* start-sanitize-m32rx */
  36 #define HAVE_CPU_M32RX
  37 /* end-sanitize-m32rx */
  38
  39 #define CGEN_WORD_BITSIZE 32
  40 #define CGEN_DEFAULT_INSN_BITSIZE 32
  41 #define CGEN_BASE_INSN_BITSIZE 32
  42 #define CGEN_MIN_INSN_BITSIZE 16
  43 #define CGEN_MAX_INSN_BITSIZE 32
  44 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  45 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  46 #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
  47 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  48 #define CGEN_INT_INSN
  49
  50 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  51
  52 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  53    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  54    we can't hash on everything up to the space.  */
  55 #define CGEN_MNEMONIC_OPERANDS
  56 /* Maximum number of operands any insn or macro-insn has.  */
  57 #define CGEN_MAX_INSN_OPERANDS 16
  58
  59 /* Enums.  */
  60
  61 /* Enum declaration for insn format enums.  */
  62 typedef enum insn_op1 {
  63   OP1_0, OP1_1, OP1_2, OP1_3
  64  , OP1_4, OP1_5, OP1_6, OP1_7
  65  , OP1_8, OP1_9, OP1_10, OP1_11
  66  , OP1_12, OP1_13, OP1_14, OP1_15
  67 } INSN_OP1;
  68
  69 /* Enum declaration for op2 enums.  */
  70 typedef enum insn_op2 {
  71   OP2_0, OP2_1, OP2_2, OP2_3
  72  , OP2_4, OP2_5, OP2_6, OP2_7
  73  , OP2_8, OP2_9, OP2_10, OP2_11
  74  , OP2_12, OP2_13, OP2_14, OP2_15
  75 } INSN_OP2;
  76
  77 /* Enum declaration for general registers.  */
  78 typedef enum h_gr {
  79   H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
  80  , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
  81  , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
  82  , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
  83  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
  84 } H_GR;
  85
  86 /* Enum declaration for control registers.  */
  87 typedef enum h_cr {
  88   H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
  89  , H_CR_BPC = 6, H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2
  90  , H_CR_CR3 = 3, H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6
  91  , H_CR_CR7 = 7, H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10
  92  , H_CR_CR11 = 11, H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14
  93  , H_CR_CR15 = 15
  94 } H_CR;
  95
  96 /* start-sanitize-m32rx */
  97 /* Enum declaration for accumulators.  */
  98 typedef enum h_accums {
  99   H_ACCUMS_A0, H_ACCUMS_A1
 100 } H_ACCUMS;
 101
 102 /* end-sanitize-m32rx */
 103 /* Enum declaration for m32r operand types.  */
 104 typedef enum cgen_operand_type {
 105   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
 106  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
 107  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
 108 /* start-sanitize-m32rx */
 109  , M32R_OPERAND_IMM1
 110 /* end-sanitize-m32rx */
 111 /* start-sanitize-m32rx */
 112  , M32R_OPERAND_ACCD
 113 /* end-sanitize-m32rx */
 114 /* start-sanitize-m32rx */
 115  , M32R_OPERAND_ACCS
 116 /* end-sanitize-m32rx */
 117 /* start-sanitize-m32rx */
 118  , M32R_OPERAND_ACC
 119 /* end-sanitize-m32rx */
 120  , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
 121  , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
 122  , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
 123 } CGEN_OPERAND_TYPE;
 124
 125 /* Non-boolean attributes.  */
 126
 127 /* Enum declaration for machine type selection.  */
 128 typedef enum mach_attr {
 129   MACH_M32R
 130 /* start-sanitize-m32rx */
 131  , MACH_M32RX
 132 /* end-sanitize-m32rx */
 133  , MACH_MAX
 134 } MACH_ATTR;
 135
 136 /* start-sanitize-m32rx */
 137 /* Enum declaration for parallel execution pipeline selection.  */
 138 typedef enum pipe_attr {
 139   PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
 140 } PIPE_ATTR;
 141
 142 /* end-sanitize-m32rx */
 143 /* Number of architecture variants.  */
 144 #define MAX_MACHS ((int) MACH_MAX)
 145
 146 /* Number of operands types.  */
 147 #define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
 148
 149 /* Maximum number of operands referenced by any insn.  */
 150 #define MAX_OPERAND_INSTANCES 8
 151
 152 /* Operand and instruction attribute indices.  */
 153
 154 /* Enum declaration for cgen_operand attrs.  */
 155 typedef enum cgen_operand_attr {
 156   CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE
 157  , CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
 158  , CGEN_OPERAND_UNSIGNED
 159 } CGEN_OPERAND_ATTR;
 160
 161 /* Number of non-boolean elements in cgen_operand.  */
 162 #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
 163
 164 /* Enum declaration for cgen_insn attrs.  */
 165 typedef enum cgen_insn_attr {
 166   CGEN_INSN_MACH
 167 /* start-sanitize-m32rx */
 168  , CGEN_INSN_PIPE
 169 /* end-sanitize-m32rx */
 170  , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_NO_DIS
 171  , CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SPECIAL
 172  , CGEN_INSN_UNCOND_CTI
 173 } CGEN_INSN_ATTR;
 174
 175 /* Number of non-boolean elements in cgen_insn.  */
 176 #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
 177
 178 /* Enum declaration for m32r instruction types.  */
 179 typedef enum cgen_insn_type {
 180   M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
 181  , M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR
 182  , M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3
 183  , M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
 184  , M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
 185  , M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL24
 186 /* start-sanitize-m32rx */
 187  , M32R_INSN_BCL8
 188 /* end-sanitize-m32rx */
 189 /* start-sanitize-m32rx */
 190  , M32R_INSN_BCL24
 191 /* end-sanitize-m32rx */
 192  , M32R_INSN_BNC8, M32R_INSN_BNC24, M32R_INSN_BNE, M32R_INSN_BRA8
 193  , M32R_INSN_BRA24
 194 /* start-sanitize-m32rx */
 195  , M32R_INSN_BNCL8
 196 /* end-sanitize-m32rx */
 197 /* start-sanitize-m32rx */
 198  , M32R_INSN_BNCL24
 199 /* end-sanitize-m32rx */
 200  , M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU, M32R_INSN_CMPUI
 201 /* start-sanitize-m32rx */
 202  , M32R_INSN_CMPEQ
 203 /* end-sanitize-m32rx */
 204 /* start-sanitize-m32rx */
 205  , M32R_INSN_CMPZ
 206 /* end-sanitize-m32rx */
 207  , M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
 208 /* start-sanitize-m32rx */
 209  , M32R_INSN_DIVH
 210 /* end-sanitize-m32rx */
 211 /* start-sanitize-m32rx */
 212  , M32R_INSN_JC
 213 /* end-sanitize-m32rx */
 214 /* start-sanitize-m32rx */
 215  , M32R_INSN_JNC
 216 /* end-sanitize-m32rx */
 217  , M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_D
 218  , M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH, M32R_INSN_LDH_D
 219  , M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH, M32R_INSN_LDUH_D
 220  , M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI16
 221  , M32R_INSN_LOCK, M32R_INSN_MACHI
 222 /* start-sanitize-m32rx */
 223  , M32R_INSN_MACHI_A
 224 /* end-sanitize-m32rx */
 225  , M32R_INSN_MACLO
 226 /* start-sanitize-m32rx */
 227  , M32R_INSN_MACLO_A
 228 /* end-sanitize-m32rx */
 229  , M32R_INSN_MACWHI
 230 /* start-sanitize-m32rx */
 231  , M32R_INSN_MACWHI_A
 232 /* end-sanitize-m32rx */
 233  , M32R_INSN_MACWLO
 234 /* start-sanitize-m32rx */
 235  , M32R_INSN_MACWLO_A
 236 /* end-sanitize-m32rx */
 237  , M32R_INSN_MUL, M32R_INSN_MULHI
 238 /* start-sanitize-m32rx */
 239  , M32R_INSN_MULHI_A
 240 /* end-sanitize-m32rx */
 241  , M32R_INSN_MULLO
 242 /* start-sanitize-m32rx */
 243  , M32R_INSN_MULLO_A
 244 /* end-sanitize-m32rx */
 245  , M32R_INSN_MULWHI
 246 /* start-sanitize-m32rx */
 247  , M32R_INSN_MULWHI_A
 248 /* end-sanitize-m32rx */
 249  , M32R_INSN_MULWLO
 250 /* start-sanitize-m32rx */
 251  , M32R_INSN_MULWLO_A
 252 /* end-sanitize-m32rx */
 253  , M32R_INSN_MV, M32R_INSN_MVFACHI
 254 /* start-sanitize-m32rx */
 255  , M32R_INSN_MVFACHI_A
 256 /* end-sanitize-m32rx */
 257  , M32R_INSN_MVFACLO
 258 /* start-sanitize-m32rx */
 259  , M32R_INSN_MVFACLO_A
 260 /* end-sanitize-m32rx */
 261  , M32R_INSN_MVFACMI
 262 /* start-sanitize-m32rx */
 263  , M32R_INSN_MVFACMI_A
 264 /* end-sanitize-m32rx */
 265  , M32R_INSN_MVFC, M32R_INSN_MVTACHI
 266 /* start-sanitize-m32rx */
 267  , M32R_INSN_MVTACHI_A
 268 /* end-sanitize-m32rx */
 269  , M32R_INSN_MVTACLO
 270 /* start-sanitize-m32rx */
 271  , M32R_INSN_MVTACLO_A
 272 /* end-sanitize-m32rx */
 273  , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
 274  , M32R_INSN_RAC
 275 /* start-sanitize-m32rx */
 276  , M32R_INSN_RAC_DSI
 277 /* end-sanitize-m32rx */
 278  , M32R_INSN_RACH
 279 /* start-sanitize-m32rx */
 280  , M32R_INSN_RACH_DSI
 281 /* end-sanitize-m32rx */
 282  , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
 283  , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
 284  , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
 285  , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
 286  , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
 287  , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
 288 /* start-sanitize-m32rx */
 289  , M32R_INSN_SATB
 290 /* end-sanitize-m32rx */
 291 /* start-sanitize-m32rx */
 292  , M32R_INSN_SATH
 293 /* end-sanitize-m32rx */
 294 /* start-sanitize-m32rx */
 295  , M32R_INSN_SAT
 296 /* end-sanitize-m32rx */
 297 /* start-sanitize-m32rx */
 298  , M32R_INSN_PCMPBZ
 299 /* end-sanitize-m32rx */
 300 /* start-sanitize-m32rx */
 301  , M32R_INSN_SADD
 302 /* end-sanitize-m32rx */
 303 /* start-sanitize-m32rx */
 304  , M32R_INSN_MACWU1
 305 /* end-sanitize-m32rx */
 306 /* start-sanitize-m32rx */
 307  , M32R_INSN_MSBLO
 308 /* end-sanitize-m32rx */
 309 /* start-sanitize-m32rx */
 310  , M32R_INSN_MULWU1
 311 /* end-sanitize-m32rx */
 312 /* start-sanitize-m32rx */
 313  , M32R_INSN_MACLH1
 314 /* end-sanitize-m32rx */
 315 /* start-sanitize-m32rx */
 316  , M32R_INSN_SC
 317 /* end-sanitize-m32rx */
 318 /* start-sanitize-m32rx */
 319  , M32R_INSN_SNC
 320 /* end-sanitize-m32rx */
 321  , M32R_INSN_MAX
 322 } CGEN_INSN_TYPE;
 323
 324 /* Index of `illegal' insn place holder.  */
 325 #define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
 326 /* Total number of insns in table.  */
 327 #define MAX_INSNS ((int) M32R_INSN_MAX)
 328
 329 /* cgen.h uses things we just defined.  */
 330 #include "opcode/cgen.h"
 331
 332 /* This struct records data prior to insertion or after extraction.  */
 333 struct cgen_fields
 334 {
 335   long f_nil;
 336   long f_op1;
 337   long f_op2;
 338   long f_cond;
 339   long f_r1;
 340   long f_r2;
 341   long f_simm8;
 342   long f_simm16;
 343   long f_shift_op2;
 344   long f_uimm4;
 345   long f_uimm5;
 346   long f_uimm16;
 347   long f_uimm24;
 348   long f_hi16;
 349   long f_disp8;
 350   long f_disp16;
 351   long f_disp24;
 352 /* start-sanitize-m32rx */
 353   long f_op23;
 354 /* end-sanitize-m32rx */
 355 /* start-sanitize-m32rx */
 356   long f_op3;
 357 /* end-sanitize-m32rx */
 358 /* start-sanitize-m32rx */
 359   long f_acc;
 360 /* end-sanitize-m32rx */
 361 /* start-sanitize-m32rx */
 362   long f_accs;
 363 /* end-sanitize-m32rx */
 364 /* start-sanitize-m32rx */
 365   long f_accd;
 366 /* end-sanitize-m32rx */
 367 /* start-sanitize-m32rx */
 368   long f_bits67;
 369 /* end-sanitize-m32rx */
 370 /* start-sanitize-m32rx */
 371   long f_bit14;
 372 /* end-sanitize-m32rx */
 373 /* start-sanitize-m32rx */
 374   long f_imm1;
 375 /* end-sanitize-m32rx */
 376   int length;
 377 };
 378
 379 /* Attributes.  */
 380 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 381 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 382
 383 /* Enum declaration for m32r hardware types.  */
 384 typedef enum hw_type {
 385   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 386  , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
 387  , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
 388 /* start-sanitize-m32rx */
 389  , HW_H_ACCUMS
 390 /* end-sanitize-m32rx */
 391  , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
 392  , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
 393  , HW_MAX
 394 } HW_TYPE;
 395
 396 #define MAX_HW ((int) HW_MAX)
 397
 398 /* Hardware decls.  */
 399
 400 extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
 401 extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
 402 /* start-sanitize-m32rx */
 403 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 404 /* end-sanitize-m32rx */
 405
 406 #define CGEN_INIT_PARSE(od) \
 407 {\
 408 }
 409 #define CGEN_INIT_INSERT(od) \
 410 {\
 411 }
 412 #define CGEN_INIT_EXTRACT(od) \
 413 {\
 414 }
 415 #define CGEN_INIT_PRINT(od) \
 416 {\
 417 }
 418
 419 /* -- opc.h */
 420
 421 #undef CGEN_DIS_HASH_SIZE
 422 #define CGEN_DIS_HASH_SIZE 256
 423 #undef CGEN_DIS_HASH
 424 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 425 #define CGEN_DIS_HASH(buffer, value) \
 426 (X (buffer) | \
 427  (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
 428   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
 429   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
 430   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
 431
 432 /* -- */
 433
 434
 435 #endif /* M32R_OPC_H */