Reorganise m68k instruction decoding and improve handling of MAC/EMAC
[deliverable/binutils-gdb.git] / opcodes / m68k-dis.c
1 /* Print Motorola 68k instructions.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
5
6 This file is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20 #include "sysdep.h"
21 #include "dis-asm.h"
22 #include "floatformat.h"
23 #include "libiberty.h"
24 #include "opintl.h"
25
26 #include "opcode/m68k.h"
27
28 /* Local function prototypes */
29
30 static int
31 fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
32
33 static void
34 dummy_print_address PARAMS ((bfd_vma, struct disassemble_info *));
35
36 static int
37 fetch_arg PARAMS ((unsigned char *, int, int, disassemble_info *));
38
39 static void
40 print_base PARAMS ((int, bfd_vma, disassemble_info *));
41
42 static unsigned char *
43 print_indexed PARAMS ((int, unsigned char *, bfd_vma, disassemble_info *));
44
45 static int
46 print_insn_arg PARAMS ((const char *, unsigned char *, unsigned char *,
47 bfd_vma, disassemble_info *));
48
49 static bfd_boolean m68k_valid_ea (char code, int val);
50
51 const char * const fpcr_names[] =
52 {
53 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
54 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
55 };
56
57 static char *const reg_names[] =
58 {
59 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
60 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
61 "%ps", "%pc"
62 };
63
64 /* Name of register halves for MAC/EMAC.
65 Seperate from reg_names since 'spu', 'fpl' look weird. */
66 static char *const reg_half_names[] =
67 {
68 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
69 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
70 "%ps", "%pc"
71 };
72
73 /* Sign-extend an (unsigned char). */
74 #if __STDC__ == 1
75 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
76 #else
77 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
78 #endif
79
80 /* Get a 1 byte signed integer. */
81 #define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1]))
82
83 /* Get a 2 byte signed integer. */
84 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
85 #define NEXTWORD(p) \
86 (p += 2, FETCH_DATA (info, p), \
87 COERCE16 ((p[-2] << 8) + p[-1]))
88
89 /* Get a 4 byte signed integer. */
90 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
91 #define NEXTLONG(p) \
92 (p += 4, FETCH_DATA (info, p), \
93 (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])))
94
95 /* Get a 4 byte unsigned integer. */
96 #define NEXTULONG(p) \
97 (p += 4, FETCH_DATA (info, p), \
98 (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))
99
100 /* Get a single precision float. */
101 #define NEXTSINGLE(val, p) \
102 (p += 4, FETCH_DATA (info, p), \
103 floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val))
104
105 /* Get a double precision float. */
106 #define NEXTDOUBLE(val, p) \
107 (p += 8, FETCH_DATA (info, p), \
108 floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val))
109
110 /* Get an extended precision float. */
111 #define NEXTEXTEND(val, p) \
112 (p += 12, FETCH_DATA (info, p), \
113 floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val))
114
115 /* Need a function to convert from packed to double
116 precision. Actually, it's easier to print a
117 packed number than a double anyway, so maybe
118 there should be a special case to handle this... */
119 #define NEXTPACKED(p) \
120 (p += 12, FETCH_DATA (info, p), 0.0)
121 \f
122 /* Maximum length of an instruction. */
123 #define MAXLEN 22
124
125 #include <setjmp.h>
126
127 struct private {
128 /* Points to first byte not fetched. */
129 bfd_byte *max_fetched;
130 bfd_byte the_buffer[MAXLEN];
131 bfd_vma insn_start;
132 jmp_buf bailout;
133 };
134
135 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
136 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
137 on error. */
138 #define FETCH_DATA(info, addr) \
139 ((addr) <= ((struct private *) (info->private_data))->max_fetched \
140 ? 1 : fetch_data ((info), (addr)))
141
142 static int
143 fetch_data (info, addr)
144 struct disassemble_info *info;
145 bfd_byte *addr;
146 {
147 int status;
148 struct private *priv = (struct private *)info->private_data;
149 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
150
151 status = (*info->read_memory_func) (start,
152 priv->max_fetched,
153 addr - priv->max_fetched,
154 info);
155 if (status != 0)
156 {
157 (*info->memory_error_func) (status, start, info);
158 longjmp (priv->bailout, 1);
159 }
160 else
161 priv->max_fetched = addr;
162 return 1;
163 }
164 \f
165 /* This function is used to print to the bit-bucket. */
166 static int
167 #ifdef __STDC__
168 dummy_printer (FILE *file ATTRIBUTE_UNUSED,
169 const char *format ATTRIBUTE_UNUSED, ...)
170 #else
171 dummy_printer (file)
172 FILE *file ATTRIBUTE_UNUSED;
173 #endif
174 {
175 return 0;
176 }
177
178 static void
179 dummy_print_address (vma, info)
180 bfd_vma vma ATTRIBUTE_UNUSED;
181 struct disassemble_info *info ATTRIBUTE_UNUSED;
182 {
183 }
184
185 /* Try to match the current instruction to best and if so, return the
186 number of bytes consumed from the instruction stream, else zero. */
187
188 static int
189 match_insn_m68k (bfd_vma memaddr, disassemble_info * info,
190 const struct m68k_opcode * best, struct private * priv)
191 {
192 unsigned char *save_p;
193 unsigned char *p;
194 const char *d;
195
196 bfd_byte *buffer = priv->the_buffer;
197 fprintf_ftype save_printer = info->fprintf_func;
198 void (* save_print_address) (bfd_vma, struct disassemble_info *)
199 = info->print_address_func;
200
201 /* Point at first word of argument data,
202 and at descriptor for first argument. */
203 p = buffer + 2;
204
205 /* Figure out how long the fixed-size portion of the instruction is.
206 The only place this is stored in the opcode table is
207 in the arguments--look for arguments which specify fields in the 2nd
208 or 3rd words of the instruction. */
209 for (d = best->args; *d; d += 2)
210 {
211 /* I don't think it is necessary to be checking d[0] here;
212 I suspect all this could be moved to the case statement below. */
213 if (d[0] == '#')
214 {
215 if (d[1] == 'l' && p - buffer < 6)
216 p = buffer + 6;
217 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
218 p = buffer + 4;
219 }
220
221 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
222 p = buffer + 4;
223
224 switch (d[1])
225 {
226 case '1':
227 case '2':
228 case '3':
229 case '7':
230 case '8':
231 case '9':
232 case 'i':
233 if (p - buffer < 4)
234 p = buffer + 4;
235 break;
236 case '4':
237 case '5':
238 case '6':
239 if (p - buffer < 6)
240 p = buffer + 6;
241 break;
242 default:
243 break;
244 }
245 }
246
247 /* pflusha is an exceptions. It takes no arguments but is two words
248 long. Recognize it by looking at the lower 16 bits of the mask. */
249 if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
250 p = buffer + 4;
251
252 /* lpstop is another exception. It takes a one word argument but is
253 three words long. */
254 if (p - buffer < 6
255 && (best->match & 0xffff) == 0xffff
256 && best->args[0] == '#'
257 && best->args[1] == 'w')
258 {
259 /* Copy the one word argument into the usual location for a one
260 word argument, to simplify printing it. We can get away with
261 this because we know exactly what the second word is, and we
262 aren't going to print anything based on it. */
263 p = buffer + 6;
264 FETCH_DATA (info, p);
265 buffer[2] = buffer[4];
266 buffer[3] = buffer[5];
267 }
268
269 FETCH_DATA (info, p);
270
271 d = best->args;
272
273 save_p = p;
274 info->print_address_func = dummy_print_address;
275 info->fprintf_func = (fprintf_ftype) dummy_printer;
276
277 /* We scan the operands twice. The first time we don't print anything,
278 but look for errors. */
279 for (; *d; d += 2)
280 {
281 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
282
283 if (eaten >= 0)
284 p += eaten;
285 else if (eaten == -1)
286 {
287 info->fprintf_func = save_printer;
288 info->print_address_func = save_print_address;
289 return 0;
290 }
291 else
292 {
293 info->fprintf_func (info->stream,
294 /* xgettext:c-format */
295 _("<internal error in opcode table: %s %s>\n"),
296 best->name, best->args);
297 info->fprintf_func = save_printer;
298 info->print_address_func = save_print_address;
299 return 2;
300 }
301 }
302
303 p = save_p;
304 info->fprintf_func = save_printer;
305 info->print_address_func = save_print_address;
306
307 d = best->args;
308
309 info->fprintf_func (info->stream, "%s", best->name);
310
311 if (*d)
312 info->fprintf_func (info->stream, " ");
313
314 while (*d)
315 {
316 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
317 d += 2;
318
319 if (*d && *(d - 2) != 'I' && *d != 'k')
320 info->fprintf_func (info->stream, ",");
321 }
322
323 return p - buffer;
324 }
325
326 /* Print the m68k instruction at address MEMADDR in debugged memory,
327 on INFO->STREAM. Returns length of the instruction, in bytes. */
328
329 int
330 print_insn_m68k (memaddr, info)
331 bfd_vma memaddr;
332 disassemble_info *info;
333 {
334 int i;
335 const char *d;
336 unsigned int arch_mask;
337 struct private priv;
338 bfd_byte *buffer = priv.the_buffer;
339 int major_opcode;
340 static int numopcodes[16];
341 static const struct m68k_opcode **opcodes[16];
342 int val;
343
344 if (!opcodes[0])
345 {
346 /* Speed up the matching by sorting the opcode
347 table on the upper four bits of the opcode. */
348 const struct m68k_opcode **opc_pointer[16];
349
350 /* First count how many opcodes are in each of the sixteen buckets. */
351 for (i = 0; i < m68k_numopcodes; i++)
352 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
353
354 /* Then create a sorted table of pointers
355 that point into the unsorted table. */
356 opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *)
357 * m68k_numopcodes);
358 opcodes[0] = opc_pointer[0];
359
360 for (i = 1; i < 16; i++)
361 {
362 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
363 opcodes[i] = opc_pointer[i];
364 }
365
366 for (i = 0; i < m68k_numopcodes; i++)
367 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
368 }
369
370 info->private_data = (PTR) &priv;
371 /* Tell objdump to use two bytes per chunk
372 and six bytes per line for displaying raw data. */
373 info->bytes_per_chunk = 2;
374 info->bytes_per_line = 6;
375 info->display_endian = BFD_ENDIAN_BIG;
376 priv.max_fetched = priv.the_buffer;
377 priv.insn_start = memaddr;
378
379 if (setjmp (priv.bailout) != 0)
380 /* Error return. */
381 return -1;
382
383 switch (info->mach)
384 {
385 default:
386 case 0:
387 arch_mask = (unsigned int) -1;
388 break;
389 case bfd_mach_m68000:
390 arch_mask = m68000|m68881|m68851;
391 break;
392 case bfd_mach_m68008:
393 arch_mask = m68008|m68881|m68851;
394 break;
395 case bfd_mach_m68010:
396 arch_mask = m68010|m68881|m68851;
397 break;
398 case bfd_mach_m68020:
399 arch_mask = m68020|m68881|m68851;
400 break;
401 case bfd_mach_m68030:
402 arch_mask = m68030|m68881|m68851;
403 break;
404 case bfd_mach_m68040:
405 arch_mask = m68040|m68881|m68851;
406 break;
407 case bfd_mach_m68060:
408 arch_mask = m68060|m68881|m68851;
409 break;
410 case bfd_mach_mcf5200:
411 arch_mask = mcfisa_a;
412 break;
413 case bfd_mach_mcf521x:
414 case bfd_mach_mcf528x:
415 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
416 break;
417 case bfd_mach_mcf5206e:
418 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
419 break;
420 case bfd_mach_mcf5249:
421 arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
422 break;
423 case bfd_mach_mcf5307:
424 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
425 break;
426 case bfd_mach_mcf5407:
427 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
428 break;
429 case bfd_mach_mcf547x:
430 case bfd_mach_mcf548x:
431 case bfd_mach_mcfv4e:
432 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
433 break;
434 }
435
436 FETCH_DATA (info, buffer + 2);
437 major_opcode = (buffer[0] >> 4) & 15;
438
439 for (i = 0; i < numopcodes[major_opcode]; i++)
440 {
441 const struct m68k_opcode *opc = opcodes[major_opcode][i];
442 unsigned long opcode = opc->opcode;
443 unsigned long match = opc->match;
444
445 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
446 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
447 /* Only fetch the next two bytes if we need to. */
448 && (((0xffff & match) == 0)
449 ||
450 (FETCH_DATA (info, buffer + 4)
451 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
452 && ((0xff & buffer[3] & match) == (0xff & opcode)))
453 )
454 && (opc->arch & arch_mask) != 0)
455 {
456 /* Don't use for printout the variants of divul and divsl
457 that have the same register number in two places.
458 The more general variants will match instead. */
459 for (d = opc->args; *d; d += 2)
460 if (d[1] == 'D')
461 break;
462
463 /* Don't use for printout the variants of most floating
464 point coprocessor instructions which use the same
465 register number in two places, as above. */
466 if (*d == '\0')
467 for (d = opc->args; *d; d += 2)
468 if (d[1] == 't')
469 break;
470
471 /* Don't match fmovel with more than one register;
472 wait for fmoveml. */
473 if (*d == '\0')
474 {
475 for (d = opc->args; *d; d += 2)
476 {
477 if (d[0] == 's' && d[1] == '8')
478 {
479 val = fetch_arg (buffer, d[1], 3, info);
480 if ((val & (val - 1)) != 0)
481 break;
482 }
483 }
484 }
485
486 if (*d == '\0')
487 if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
488 return val;
489 }
490 }
491
492 /* Handle undefined instructions. */
493 info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
494 return 2;
495 }
496
497 /* Returns number of bytes "eaten" by the operand, or
498 return -1 if an invalid operand was found, or -2 if
499 an opcode tabe error was found. */
500
501 static int
502 print_insn_arg (d, buffer, p0, addr, info)
503 const char *d;
504 unsigned char *buffer;
505 unsigned char *p0;
506 bfd_vma addr; /* PC for this arg to be relative to. */
507 disassemble_info *info;
508 {
509 int val = 0;
510 int place = d[1];
511 unsigned char *p = p0;
512 int regno;
513 const char *regname;
514 unsigned char *p1;
515 double flval;
516 int flt_p;
517 bfd_signed_vma disp;
518 unsigned int uval;
519
520 switch (*d)
521 {
522 case 'c': /* Cache identifier. */
523 {
524 static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
525 val = fetch_arg (buffer, place, 2, info);
526 (*info->fprintf_func) (info->stream, cacheFieldName[val]);
527 break;
528 }
529
530 case 'a': /* Address register indirect only. Cf. case '+'. */
531 {
532 (*info->fprintf_func)
533 (info->stream,
534 "%s@",
535 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
536 break;
537 }
538
539 case '_': /* 32-bit absolute address for move16. */
540 {
541 uval = NEXTULONG (p);
542 (*info->print_address_func) (uval, info);
543 break;
544 }
545
546 case 'C':
547 (*info->fprintf_func) (info->stream, "%%ccr");
548 break;
549
550 case 'S':
551 (*info->fprintf_func) (info->stream, "%%sr");
552 break;
553
554 case 'U':
555 (*info->fprintf_func) (info->stream, "%%usp");
556 break;
557
558 case 'E':
559 (*info->fprintf_func) (info->stream, "%%acc");
560 break;
561
562 case 'G':
563 (*info->fprintf_func) (info->stream, "%%macsr");
564 break;
565
566 case 'H':
567 (*info->fprintf_func) (info->stream, "%%mask");
568 break;
569
570 case 'J':
571 {
572 /* FIXME: There's a problem here, different m68k processors call the
573 same address different names. This table can't get it right
574 because it doesn't know which processor it's disassembling for. */
575 static const struct { char *name; int value; } names[]
576 = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
577 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
578 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
579 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
580 {"%msp", 0x803}, {"%isp", 0x804},
581 {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
582
583 /* Should we be calling this psr like we do in case 'Y'? */
584 {"%mmusr",0x805},
585
586 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
587
588 val = fetch_arg (buffer, place, 12, info);
589 for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
590 if (names[regno].value == val)
591 {
592 (*info->fprintf_func) (info->stream, "%s", names[regno].name);
593 break;
594 }
595 if (regno < 0)
596 (*info->fprintf_func) (info->stream, "%d", val);
597 }
598 break;
599
600 case 'Q':
601 val = fetch_arg (buffer, place, 3, info);
602 /* 0 means 8, except for the bkpt instruction... */
603 if (val == 0 && d[1] != 's')
604 val = 8;
605 (*info->fprintf_func) (info->stream, "#%d", val);
606 break;
607
608 case 'x':
609 val = fetch_arg (buffer, place, 3, info);
610 /* 0 means -1. */
611 if (val == 0)
612 val = -1;
613 (*info->fprintf_func) (info->stream, "#%d", val);
614 break;
615
616 case 'M':
617 if (place == 'h')
618 {
619 static char *const scalefactor_name[] = { "<<", ">>" };
620 val = fetch_arg (buffer, place, 1, info);
621 (*info->fprintf_func) (info->stream, scalefactor_name[val]);
622 }
623 else
624 {
625 val = fetch_arg (buffer, place, 8, info);
626 if (val & 0x80)
627 val = val - 0x100;
628 (*info->fprintf_func) (info->stream, "#%d", val);
629 }
630 break;
631
632 case 'T':
633 val = fetch_arg (buffer, place, 4, info);
634 (*info->fprintf_func) (info->stream, "#%d", val);
635 break;
636
637 case 'D':
638 (*info->fprintf_func) (info->stream, "%s",
639 reg_names[fetch_arg (buffer, place, 3, info)]);
640 break;
641
642 case 'A':
643 (*info->fprintf_func)
644 (info->stream, "%s",
645 reg_names[fetch_arg (buffer, place, 3, info) + 010]);
646 break;
647
648 case 'R':
649 (*info->fprintf_func)
650 (info->stream, "%s",
651 reg_names[fetch_arg (buffer, place, 4, info)]);
652 break;
653
654 case 'r':
655 regno = fetch_arg (buffer, place, 4, info);
656 if (regno > 7)
657 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
658 else
659 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
660 break;
661
662 case 'F':
663 (*info->fprintf_func)
664 (info->stream, "%%fp%d",
665 fetch_arg (buffer, place, 3, info));
666 break;
667
668 case 'O':
669 val = fetch_arg (buffer, place, 6, info);
670 if (val & 0x20)
671 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
672 else
673 (*info->fprintf_func) (info->stream, "%d", val);
674 break;
675
676 case '+':
677 (*info->fprintf_func)
678 (info->stream, "%s@+",
679 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
680 break;
681
682 case '-':
683 (*info->fprintf_func)
684 (info->stream, "%s@-",
685 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
686 break;
687
688 case 'k':
689 if (place == 'k')
690 (*info->fprintf_func)
691 (info->stream, "{%s}",
692 reg_names[fetch_arg (buffer, place, 3, info)]);
693 else if (place == 'C')
694 {
695 val = fetch_arg (buffer, place, 7, info);
696 if (val > 63) /* This is a signed constant. */
697 val -= 128;
698 (*info->fprintf_func) (info->stream, "{#%d}", val);
699 }
700 else
701 return -2;
702 break;
703
704 case '#':
705 case '^':
706 p1 = buffer + (*d == '#' ? 2 : 4);
707 if (place == 's')
708 val = fetch_arg (buffer, place, 4, info);
709 else if (place == 'C')
710 val = fetch_arg (buffer, place, 7, info);
711 else if (place == '8')
712 val = fetch_arg (buffer, place, 3, info);
713 else if (place == '3')
714 val = fetch_arg (buffer, place, 8, info);
715 else if (place == 'b')
716 val = NEXTBYTE (p1);
717 else if (place == 'w' || place == 'W')
718 val = NEXTWORD (p1);
719 else if (place == 'l')
720 val = NEXTLONG (p1);
721 else
722 return -2;
723 (*info->fprintf_func) (info->stream, "#%d", val);
724 break;
725
726 case 'B':
727 if (place == 'b')
728 disp = NEXTBYTE (p);
729 else if (place == 'B')
730 disp = COERCE_SIGNED_CHAR (buffer[1]);
731 else if (place == 'w' || place == 'W')
732 disp = NEXTWORD (p);
733 else if (place == 'l' || place == 'L' || place == 'C')
734 disp = NEXTLONG (p);
735 else if (place == 'g')
736 {
737 disp = NEXTBYTE (buffer);
738 if (disp == 0)
739 disp = NEXTWORD (p);
740 else if (disp == -1)
741 disp = NEXTLONG (p);
742 }
743 else if (place == 'c')
744 {
745 if (buffer[1] & 0x40) /* If bit six is one, long offset */
746 disp = NEXTLONG (p);
747 else
748 disp = NEXTWORD (p);
749 }
750 else
751 return -2;
752
753 (*info->print_address_func) (addr + disp, info);
754 break;
755
756 case 'd':
757 val = NEXTWORD (p);
758 (*info->fprintf_func)
759 (info->stream, "%s@(%d)",
760 reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
761 break;
762
763 case 's':
764 (*info->fprintf_func) (info->stream, "%s",
765 fpcr_names[fetch_arg (buffer, place, 3, info)]);
766 break;
767
768 case 'e':
769 val = fetch_arg(buffer, place, 2, info);
770 (*info->fprintf_func) (info->stream, "%%acc%d", val);
771 break;
772
773 case 'g':
774 val = fetch_arg(buffer, place, 1, info);
775 (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
776 break;
777
778 case 'i':
779 val = fetch_arg(buffer, place, 2, info);
780 if (val == 1)
781 (*info->fprintf_func) (info->stream, "<<");
782 else if (val == 3)
783 (*info->fprintf_func) (info->stream, ">>");
784 else
785 return -1;
786 break;
787
788 case 'I':
789 /* Get coprocessor ID... */
790 val = fetch_arg (buffer, 'd', 3, info);
791
792 if (val != 1) /* Unusual coprocessor ID? */
793 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
794 break;
795
796 case '4':
797 case '*':
798 case '~':
799 case '%':
800 case ';':
801 case '@':
802 case '!':
803 case '$':
804 case '?':
805 case '/':
806 case '&':
807 case '|':
808 case '<':
809 case '>':
810 case 'm':
811 case 'n':
812 case 'o':
813 case 'p':
814 case 'q':
815 case 'v':
816 case 'b':
817 case 'w':
818 case 'y':
819 case 'z':
820 if (place == 'd')
821 {
822 val = fetch_arg (buffer, 'x', 6, info);
823 val = ((val & 7) << 3) + ((val >> 3) & 7);
824 }
825 else
826 val = fetch_arg (buffer, 's', 6, info);
827
828 /* If the <ea> is invalid for *d, then reject this match. */
829 if (m68k_valid_ea (*d, val) == FALSE)
830 return -1;
831
832 /* Get register number assuming address register. */
833 regno = (val & 7) + 8;
834 regname = reg_names[regno];
835 switch (val >> 3)
836 {
837 case 0:
838 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
839 break;
840
841 case 1:
842 (*info->fprintf_func) (info->stream, "%s", regname);
843 break;
844
845 case 2:
846 (*info->fprintf_func) (info->stream, "%s@", regname);
847 break;
848
849 case 3:
850 (*info->fprintf_func) (info->stream, "%s@+", regname);
851 break;
852
853 case 4:
854 (*info->fprintf_func) (info->stream, "%s@-", regname);
855 break;
856
857 case 5:
858 val = NEXTWORD (p);
859 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
860 break;
861
862 case 6:
863 p = print_indexed (regno, p, addr, info);
864 break;
865
866 case 7:
867 switch (val & 7)
868 {
869 case 0:
870 val = NEXTWORD (p);
871 (*info->print_address_func) (val, info);
872 break;
873
874 case 1:
875 uval = NEXTULONG (p);
876 (*info->print_address_func) (uval, info);
877 break;
878
879 case 2:
880 val = NEXTWORD (p);
881 (*info->fprintf_func) (info->stream, "%%pc@(");
882 (*info->print_address_func) (addr + val, info);
883 (*info->fprintf_func) (info->stream, ")");
884 break;
885
886 case 3:
887 p = print_indexed (-1, p, addr, info);
888 break;
889
890 case 4:
891 flt_p = 1; /* Assume it's a float... */
892 switch (place)
893 {
894 case 'b':
895 val = NEXTBYTE (p);
896 flt_p = 0;
897 break;
898
899 case 'w':
900 val = NEXTWORD (p);
901 flt_p = 0;
902 break;
903
904 case 'l':
905 val = NEXTLONG (p);
906 flt_p = 0;
907 break;
908
909 case 'f':
910 NEXTSINGLE (flval, p);
911 break;
912
913 case 'F':
914 NEXTDOUBLE (flval, p);
915 break;
916
917 case 'x':
918 NEXTEXTEND (flval, p);
919 break;
920
921 case 'p':
922 flval = NEXTPACKED (p);
923 break;
924
925 default:
926 return -1;
927 }
928 if (flt_p) /* Print a float? */
929 (*info->fprintf_func) (info->stream, "#%g", flval);
930 else
931 (*info->fprintf_func) (info->stream, "#%d", val);
932 break;
933
934 default:
935 return -1;
936 }
937 }
938
939 /* If place is '/', then this is the case of the mask bit for
940 mac/emac loads. Now that the arg has been printed, grab the
941 mask bit and if set, add a '&' to the arg. */
942 if (place == '/')
943 {
944 val = fetch_arg (buffer, place, 1, info);
945 if (val)
946 info->fprintf_func (info->stream, "&");
947 }
948 break;
949
950 case 'L':
951 case 'l':
952 if (place == 'w')
953 {
954 char doneany;
955 p1 = buffer + 2;
956 val = NEXTWORD (p1);
957 /* Move the pointer ahead if this point is farther ahead
958 than the last. */
959 p = p1 > p ? p1 : p;
960 if (val == 0)
961 {
962 (*info->fprintf_func) (info->stream, "#0");
963 break;
964 }
965 if (*d == 'l')
966 {
967 register int newval = 0;
968 for (regno = 0; regno < 16; ++regno)
969 if (val & (0x8000 >> regno))
970 newval |= 1 << regno;
971 val = newval;
972 }
973 val &= 0xffff;
974 doneany = 0;
975 for (regno = 0; regno < 16; ++regno)
976 if (val & (1 << regno))
977 {
978 int first_regno;
979 if (doneany)
980 (*info->fprintf_func) (info->stream, "/");
981 doneany = 1;
982 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
983 first_regno = regno;
984 while (val & (1 << (regno + 1)))
985 ++regno;
986 if (regno > first_regno)
987 (*info->fprintf_func) (info->stream, "-%s",
988 reg_names[regno]);
989 }
990 }
991 else if (place == '3')
992 {
993 /* `fmovem' insn. */
994 char doneany;
995 val = fetch_arg (buffer, place, 8, info);
996 if (val == 0)
997 {
998 (*info->fprintf_func) (info->stream, "#0");
999 break;
1000 }
1001 if (*d == 'l')
1002 {
1003 register int newval = 0;
1004 for (regno = 0; regno < 8; ++regno)
1005 if (val & (0x80 >> regno))
1006 newval |= 1 << regno;
1007 val = newval;
1008 }
1009 val &= 0xff;
1010 doneany = 0;
1011 for (regno = 0; regno < 8; ++regno)
1012 if (val & (1 << regno))
1013 {
1014 int first_regno;
1015 if (doneany)
1016 (*info->fprintf_func) (info->stream, "/");
1017 doneany = 1;
1018 (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1019 first_regno = regno;
1020 while (val & (1 << (regno + 1)))
1021 ++regno;
1022 if (regno > first_regno)
1023 (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1024 }
1025 }
1026 else if (place == '8')
1027 {
1028 /* fmoveml for FP status registers */
1029 (*info->fprintf_func) (info->stream, "%s",
1030 fpcr_names[fetch_arg (buffer, place, 3,
1031 info)]);
1032 }
1033 else
1034 return -2;
1035 break;
1036
1037 case 'X':
1038 place = '8';
1039 case 'Y':
1040 case 'Z':
1041 case 'W':
1042 case '0':
1043 case '1':
1044 case '2':
1045 case '3':
1046 {
1047 int val = fetch_arg (buffer, place, 5, info);
1048 char *name = 0;
1049 switch (val)
1050 {
1051 case 2: name = "%tt0"; break;
1052 case 3: name = "%tt1"; break;
1053 case 0x10: name = "%tc"; break;
1054 case 0x11: name = "%drp"; break;
1055 case 0x12: name = "%srp"; break;
1056 case 0x13: name = "%crp"; break;
1057 case 0x14: name = "%cal"; break;
1058 case 0x15: name = "%val"; break;
1059 case 0x16: name = "%scc"; break;
1060 case 0x17: name = "%ac"; break;
1061 case 0x18: name = "%psr"; break;
1062 case 0x19: name = "%pcsr"; break;
1063 case 0x1c:
1064 case 0x1d:
1065 {
1066 int break_reg = ((buffer[3] >> 2) & 7);
1067 (*info->fprintf_func)
1068 (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1069 break_reg);
1070 }
1071 break;
1072 default:
1073 (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1074 }
1075 if (name)
1076 (*info->fprintf_func) (info->stream, "%s", name);
1077 }
1078 break;
1079
1080 case 'f':
1081 {
1082 int fc = fetch_arg (buffer, place, 5, info);
1083 if (fc == 1)
1084 (*info->fprintf_func) (info->stream, "%%dfc");
1085 else if (fc == 0)
1086 (*info->fprintf_func) (info->stream, "%%sfc");
1087 else
1088 /* xgettext:c-format */
1089 (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
1090 }
1091 break;
1092
1093 case 'V':
1094 (*info->fprintf_func) (info->stream, "%%val");
1095 break;
1096
1097 case 't':
1098 {
1099 int level = fetch_arg (buffer, place, 3, info);
1100 (*info->fprintf_func) (info->stream, "%d", level);
1101 }
1102 break;
1103
1104 case 'u':
1105 {
1106 short is_upper = 0;
1107 int reg = fetch_arg (buffer, place, 5, info);
1108
1109 if (reg & 0x10)
1110 {
1111 is_upper = 1;
1112 reg &= 0xf;
1113 }
1114 (*info->fprintf_func) (info->stream, "%s%s",
1115 reg_half_names[reg],
1116 is_upper ? "u" : "l");
1117 }
1118 break;
1119
1120 default:
1121 return -2;
1122 }
1123
1124 return p - p0;
1125 }
1126
1127 /* Check if an EA is valid for a particular code. This is required
1128 for the EMAC instructions since the type of source address determines
1129 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
1130 is a non-load EMAC instruction and the bits mean register Ry. */
1131
1132 static bfd_boolean
1133 m68k_valid_ea (char code, int val)
1134 {
1135 int mode;
1136
1137 mode = (val >> 3) & 7;
1138 if (code == '4')
1139 if (!(mode >= 2 && mode <= 5))
1140 return FALSE;
1141
1142 return TRUE;
1143 }
1144
1145 /* Fetch BITS bits from a position in the instruction specified by CODE.
1146 CODE is a "place to put an argument", or 'x' for a destination
1147 that is a general address (mode and register).
1148 BUFFER contains the instruction. */
1149
1150 static int
1151 fetch_arg (buffer, code, bits, info)
1152 unsigned char *buffer;
1153 int code;
1154 int bits;
1155 disassemble_info *info;
1156 {
1157 int val = 0;
1158
1159 switch (code)
1160 {
1161 case '/': /* MAC/EMAC mask bit. */
1162 val = buffer[3] >> 5;
1163 break;
1164
1165 case 'G': /* EMAC ACC load. */
1166 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
1167 break;
1168
1169 case 'H': /* EMAC ACC !load. */
1170 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
1171 break;
1172
1173 case ']': /* EMAC ACCEXT bit. */
1174 val = buffer[0] >> 2;
1175 break;
1176
1177 case 'I': /* MAC/EMAC scale factor. */
1178 val = buffer[2] >> 1;
1179 break;
1180
1181 case 'F': /* EMAC ACCx. */
1182 val = buffer[0] >> 1;
1183 break;
1184
1185 case 'f':
1186 val = buffer[1];
1187 break;
1188
1189 case 's':
1190 val = buffer[1];
1191 break;
1192
1193 case 'd': /* Destination, for register or quick. */
1194 val = (buffer[0] << 8) + buffer[1];
1195 val >>= 9;
1196 break;
1197
1198 case 'x': /* Destination, for general arg */
1199 val = (buffer[0] << 8) + buffer[1];
1200 val >>= 6;
1201 break;
1202
1203 case 'k':
1204 FETCH_DATA (info, buffer + 3);
1205 val = (buffer[3] >> 4);
1206 break;
1207
1208 case 'C':
1209 FETCH_DATA (info, buffer + 3);
1210 val = buffer[3];
1211 break;
1212
1213 case '1':
1214 FETCH_DATA (info, buffer + 3);
1215 val = (buffer[2] << 8) + buffer[3];
1216 val >>= 12;
1217 break;
1218
1219 case '2':
1220 FETCH_DATA (info, buffer + 3);
1221 val = (buffer[2] << 8) + buffer[3];
1222 val >>= 6;
1223 break;
1224
1225 case '3':
1226 case 'j':
1227 FETCH_DATA (info, buffer + 3);
1228 val = (buffer[2] << 8) + buffer[3];
1229 break;
1230
1231 case '4':
1232 FETCH_DATA (info, buffer + 5);
1233 val = (buffer[4] << 8) + buffer[5];
1234 val >>= 12;
1235 break;
1236
1237 case '5':
1238 FETCH_DATA (info, buffer + 5);
1239 val = (buffer[4] << 8) + buffer[5];
1240 val >>= 6;
1241 break;
1242
1243 case '6':
1244 FETCH_DATA (info, buffer + 5);
1245 val = (buffer[4] << 8) + buffer[5];
1246 break;
1247
1248 case '7':
1249 FETCH_DATA (info, buffer + 3);
1250 val = (buffer[2] << 8) + buffer[3];
1251 val >>= 7;
1252 break;
1253
1254 case '8':
1255 FETCH_DATA (info, buffer + 3);
1256 val = (buffer[2] << 8) + buffer[3];
1257 val >>= 10;
1258 break;
1259
1260 case '9':
1261 FETCH_DATA (info, buffer + 3);
1262 val = (buffer[2] << 8) + buffer[3];
1263 val >>= 5;
1264 break;
1265
1266 case 'e':
1267 val = (buffer[1] >> 6);
1268 break;
1269
1270 case 'm':
1271 val = (buffer[1] & 0x40 ? 0x8 : 0)
1272 | ((buffer[0] >> 1) & 0x7)
1273 | (buffer[3] & 0x80 ? 0x10 : 0);
1274 break;
1275
1276 case 'n':
1277 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
1278 break;
1279
1280 case 'o':
1281 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
1282 break;
1283
1284 case 'M':
1285 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
1286 break;
1287
1288 case 'N':
1289 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
1290 break;
1291
1292 case 'h':
1293 val = buffer[2] >> 2;
1294 break;
1295
1296 default:
1297 abort ();
1298 }
1299
1300 switch (bits)
1301 {
1302 case 1:
1303 return val & 1;
1304 case 2:
1305 return val & 3;
1306 case 3:
1307 return val & 7;
1308 case 4:
1309 return val & 017;
1310 case 5:
1311 return val & 037;
1312 case 6:
1313 return val & 077;
1314 case 7:
1315 return val & 0177;
1316 case 8:
1317 return val & 0377;
1318 case 12:
1319 return val & 07777;
1320 default:
1321 abort ();
1322 }
1323 }
1324
1325 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
1326 P points to extension word, in buffer.
1327 ADDR is the nominal core address of that extension word. */
1328
1329 static unsigned char *
1330 print_indexed (basereg, p, addr, info)
1331 int basereg;
1332 unsigned char *p;
1333 bfd_vma addr;
1334 disassemble_info *info;
1335 {
1336 int word;
1337 static char *const scales[] = { "", ":2", ":4", ":8" };
1338 bfd_vma base_disp;
1339 bfd_vma outer_disp;
1340 char buf[40];
1341 char vmabuf[50];
1342
1343 word = NEXTWORD (p);
1344
1345 /* Generate the text for the index register.
1346 Where this will be output is not yet determined. */
1347 sprintf (buf, "%s:%c%s",
1348 reg_names[(word >> 12) & 0xf],
1349 (word & 0x800) ? 'l' : 'w',
1350 scales[(word >> 9) & 3]);
1351
1352 /* Handle the 68000 style of indexing. */
1353
1354 if ((word & 0x100) == 0)
1355 {
1356 base_disp = word & 0xff;
1357 if ((base_disp & 0x80) != 0)
1358 base_disp -= 0x100;
1359 if (basereg == -1)
1360 base_disp += addr;
1361 print_base (basereg, base_disp, info);
1362 (*info->fprintf_func) (info->stream, ",%s)", buf);
1363 return p;
1364 }
1365
1366 /* Handle the generalized kind. */
1367 /* First, compute the displacement to add to the base register. */
1368
1369 if (word & 0200)
1370 {
1371 if (basereg == -1)
1372 basereg = -3;
1373 else
1374 basereg = -2;
1375 }
1376 if (word & 0100)
1377 buf[0] = '\0';
1378 base_disp = 0;
1379 switch ((word >> 4) & 3)
1380 {
1381 case 2:
1382 base_disp = NEXTWORD (p);
1383 break;
1384 case 3:
1385 base_disp = NEXTLONG (p);
1386 }
1387 if (basereg == -1)
1388 base_disp += addr;
1389
1390 /* Handle single-level case (not indirect) */
1391
1392 if ((word & 7) == 0)
1393 {
1394 print_base (basereg, base_disp, info);
1395 if (buf[0] != '\0')
1396 (*info->fprintf_func) (info->stream, ",%s", buf);
1397 (*info->fprintf_func) (info->stream, ")");
1398 return p;
1399 }
1400
1401 /* Two level. Compute displacement to add after indirection. */
1402
1403 outer_disp = 0;
1404 switch (word & 3)
1405 {
1406 case 2:
1407 outer_disp = NEXTWORD (p);
1408 break;
1409 case 3:
1410 outer_disp = NEXTLONG (p);
1411 }
1412
1413 print_base (basereg, base_disp, info);
1414 if ((word & 4) == 0 && buf[0] != '\0')
1415 {
1416 (*info->fprintf_func) (info->stream, ",%s", buf);
1417 buf[0] = '\0';
1418 }
1419 sprintf_vma (vmabuf, outer_disp);
1420 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
1421 if (buf[0] != '\0')
1422 (*info->fprintf_func) (info->stream, ",%s", buf);
1423 (*info->fprintf_func) (info->stream, ")");
1424
1425 return p;
1426 }
1427
1428 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
1429 REGNO = -1 for pc, -2 for none (suppressed). */
1430
1431 static void
1432 print_base (regno, disp, info)
1433 int regno;
1434 bfd_vma disp;
1435 disassemble_info *info;
1436 {
1437 if (regno == -1)
1438 {
1439 (*info->fprintf_func) (info->stream, "%%pc@(");
1440 (*info->print_address_func) (disp, info);
1441 }
1442 else
1443 {
1444 char buf[50];
1445
1446 if (regno == -2)
1447 (*info->fprintf_func) (info->stream, "@(");
1448 else if (regno == -3)
1449 (*info->fprintf_func) (info->stream, "%%zpc@(");
1450 else
1451 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
1452
1453 sprintf_vma (buf, disp);
1454 (*info->fprintf_func) (info->stream, "%s", buf);
1455 }
1456 }
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