opcodes/mep-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4    THIS FILE IS MACHINE GENERATED WITH CGEN.
   5    - the resultant file is machine generated, cgen-dis.in isn't
   6
   7    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
   8    2008, 2010  Free Software Foundation, Inc.
   9
  10    This file is part of libopcodes.
  11
  12    This library is free software; you can redistribute it and/or modify
  13    it under the terms of the GNU General Public License as published by
  14    the Free Software Foundation; either version 3, or (at your option)
  15    any later version.
  16
  17    It is distributed in the hope that it will be useful, but WITHOUT
  18    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  19    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20    License for more details.
  21
  22    You should have received a copy of the GNU General Public License
  23    along with this program; if not, write to the Free Software Foundation, Inc.,
  24    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "mep-desc.h"
  37 #include "mep-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
  45 static void print_address
  46   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
  47 static void print_keyword
  48   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
  49 static void print_insn_normal
  50   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
  51 static int print_insn
  52   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
  53 static int default_print_insn
  54   (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
  55 static int read_insn
  56   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
  57    unsigned long *);
  58 \f
  59 /* -- disassembler routines inserted here.  */
  60
  61 /* -- dis.c */
  62
  63 #include "elf/mep.h"
  64 #include "elf-bfd.h"
  65
  66 #define CGEN_VALIDATE_INSN_SUPPORTED
  67
  68 static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
  69 static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int);
  70
  71 static void
  72 print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
  73              CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
  74              unsigned int flags ATTRIBUTE_UNUSED)
  75 {
  76   disassemble_info *info = (disassemble_info *) dis_info;
  77
  78   (*info->fprintf_func) (info->stream, "$tp");
  79 }
  80
  81 static void
  82 print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
  83              CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
  84              unsigned int flags ATTRIBUTE_UNUSED)
  85 {
  86   disassemble_info *info = (disassemble_info *) dis_info;
  87
  88   (*info->fprintf_func) (info->stream, "$sp");
  89 }
  90
  91 /* begin-cop-ip-print-handlers */
  92 static void
  93 print_ivc2_cr (CGEN_CPU_DESC,
  94         void *,
  95         CGEN_KEYWORD *,
  96         long,
  97         unsigned int) ATTRIBUTE_UNUSED;
  98 static void
  99 print_ivc2_cr (CGEN_CPU_DESC cd,
 100         void *dis_info,
 101         CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
 102         long value,
 103         unsigned int attrs)
 104 {
 105   print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs);
 106 }
 107 static void
 108 print_ivc2_ccr (CGEN_CPU_DESC,
 109         void *,
 110         CGEN_KEYWORD *,
 111         long,
 112         unsigned int) ATTRIBUTE_UNUSED;
 113 static void
 114 print_ivc2_ccr (CGEN_CPU_DESC cd,
 115         void *dis_info,
 116         CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
 117         long value,
 118         unsigned int attrs)
 119 {
 120   print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs);
 121 }
 122 /* end-cop-ip-print-handlers */
 123
 124 /************************************************************\
 125 *********************** Experimental *************************
 126 \************************************************************/
 127
 128 #undef  CGEN_PRINT_INSN
 129 #define CGEN_PRINT_INSN mep_print_insn
 130
 131 static int
 132 mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
 133                       bfd_byte *buf, int corelength, int copro1length,
 134                       int copro2length ATTRIBUTE_UNUSED)
 135 {
 136   int i;
 137   int status = 0;
 138   /* char insnbuf[CGEN_MAX_INSN_SIZE]; */
 139   bfd_byte insnbuf[64];
 140
 141   /* If corelength > 0 then there is a core insn present. It
 142      will be at the beginning of the buffer.  After printing
 143      the core insn, we need to print the + on the next line.  */
 144   if (corelength > 0)
 145     {
 146       int my_status = 0;
 147
 148       for (i = 0; i < corelength; i++ )
 149         insnbuf[i] = buf[i];
 150       cd->isas = & MEP_CORE_ISA;
 151
 152       my_status = print_insn (cd, pc, info, insnbuf, corelength);
 153       if (my_status != corelength)
 154         {
 155           (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 156           my_status = corelength;
 157         }
 158       status += my_status;
 159
 160       /* Print the + to indicate that the following copro insn is   */
 161       /* part of a vliw group.                                      */
 162       if (copro1length > 0)
 163         (*info->fprintf_func) (info->stream, " + ");
 164     }
 165
 166   /* Now all that is left to be processed is the coprocessor insns
 167      In vliw mode, there will always be one.  Its positioning will
 168      be from byte corelength to byte corelength+copro1length -1.
 169      No need to check for existence.   Also, the first vliw insn,
 170      will, as spec'd, always be at least as long as the core insn
 171      so we don't need to flush the buffer.  */
 172   if (copro1length > 0)
 173     {
 174       int my_status = 0;
 175
 176       for (i = corelength; i < corelength + copro1length; i++ )
 177         insnbuf[i - corelength] = buf[i];
 178
 179       switch (copro1length)
 180         {
 181         case 0:
 182           break;
 183         case 2:
 184           cd->isas = & MEP_COP16_ISA;
 185           break;
 186         case 4:
 187           cd->isas = & MEP_COP32_ISA;
 188           break;
 189         case 6:
 190           cd->isas = & MEP_COP48_ISA;
 191           break;
 192         case 8:
 193           cd->isas = & MEP_COP64_ISA;
 194           break;
 195         default:
 196           /* Shouldn't be anything but 16,32,48,64.  */
 197           break;
 198         }
 199
 200       my_status = print_insn (cd, pc, info, insnbuf, copro1length);
 201
 202       if (my_status != copro1length)
 203         {
 204           (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 205           my_status = copro1length;
 206         }
 207       status += my_status;
 208     }
 209
 210 #if 0
 211   /* Now we need to process the second copro insn if it exists. We
 212      have no guarantee that the second copro insn will be longer
 213      than the first, so we have to flush the buffer if we are have
 214      a second copro insn to process.  If present, this insn will
 215      be in the position from byte corelength+copro1length to byte
 216      corelength+copro1length+copro2length-1 (which better equal 8
 217      or else we're in big trouble.  */
 218   if (copro2length > 0)
 219     {
 220       int my_status = 0;
 221
 222       for (i = 0; i < 64 ; i++)
 223         insnbuf[i] = 0;
 224
 225       for (i = corelength + copro1length; i < 64; i++)
 226         insnbuf[i - (corelength + copro1length)] = buf[i];
 227
 228       switch (copro2length)
 229         {
 230         case 2:
 231           cd->isas = 1 << ISA_EXT_COP1_16;
 232           break;
 233         case 4:
 234           cd->isas = 1 << ISA_EXT_COP1_32;
 235           break;
 236         case 6:
 237           cd->isas = 1 << ISA_EXT_COP1_48;
 238           break;
 239         case 8:
 240           cd->isas = 1 << ISA_EXT_COP1_64;
 241           break;
 242         default:
 243           /* Shouldn't be anything but 16,32,48,64.  */
 244           break;
 245         }
 246
 247       my_status = print_insn (cd, pc, info, insnbuf, copro2length);
 248
 249       if (my_status != copro2length)
 250         {
 251           (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 252           my_status = copro2length;
 253         }
 254
 255       status += my_status;
 256     }
 257 #endif
 258
 259   /* Status should now be the number of bytes that were printed
 260      which should be 4 for VLIW32 mode and 64 for VLIW64 mode.  */
 261
 262   if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8)))
 263     return -1;
 264   else
 265     return status;
 266 }
 267
 268 /* The two functions mep_examine_vliw[32,64]_insns are used find out
 269    which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
 270    with 32 bit copro, etc.) is present.  Later on, when internally
 271    parallel coprocessors are handled, only these functions should
 272    need to be changed.
 273
 274    At this time only the following combinations are supported:
 275
 276    VLIW32 Mode:
 277    16 bit core insn (core) and 16 bit coprocessor insn (cop1)
 278    32 bit core insn (core)
 279    32 bit coprocessor insn (cop1)
 280    Note: As of this time, I do not believe we have enough information
 281          to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
 282          no 16 bit coprocessor insns have been specified.
 283
 284    VLIW64 Mode:
 285    16 bit core insn (core) and 48 bit coprocessor insn (cop1)
 286    32 bit core insn (core) and 32 bit coprocessor insn (cop1)
 287    64 bit coprocessor insn (cop1)
 288
 289    The framework for an internally parallel coprocessor is also
 290    present (2nd coprocessor insn is cop2), but at this time it
 291    is not used.  This only appears to be valid in VLIW64 mode.  */
 292
 293 static int
 294 mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 295 {
 296   int status;
 297   int buflength;
 298   int corebuflength;
 299   int cop1buflength;
 300   int cop2buflength;
 301   bfd_byte buf[CGEN_MAX_INSN_SIZE];
 302   char indicator16[1];
 303   char indicatorcop32[2];
 304
 305   /* At this time we're not supporting internally parallel coprocessors,
 306      so cop2buflength will always be 0.  */
 307   cop2buflength = 0;
 308
 309   /* Read in 32 bits.  */
 310   buflength = 4; /* VLIW insn spans 4 bytes.  */
 311   status = (*info->read_memory_func) (pc, buf, buflength, info);
 312
 313   if (status != 0)
 314     {
 315       (*info->memory_error_func) (status, pc, info);
 316       return -1;
 317     }
 318
 319   /* Put the big endian representation of the bytes to be examined
 320      in the temporary buffers for examination.  */
 321
 322   if (info->endian == BFD_ENDIAN_BIG)
 323     {
 324       indicator16[0] = buf[0];
 325       indicatorcop32[0] = buf[0];
 326       indicatorcop32[1] = buf[1];
 327     }
 328   else
 329     {
 330       indicator16[0] = buf[1];
 331       indicatorcop32[0] = buf[1];
 332       indicatorcop32[1] = buf[0];
 333     }
 334
 335   /* If the two high order bits are 00, 01 or 10, we have a 16 bit
 336      core insn and a 48 bit copro insn.  */
 337
 338   if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
 339     {
 340       if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07)
 341         {
 342           /* We have a 32 bit copro insn.  */
 343           corebuflength = 0;
 344           /* All 4 4ytes are one copro insn. */
 345           cop1buflength = 4;
 346         }
 347       else
 348         {
 349           /* We have a 32 bit core.  */
 350           corebuflength = 4;
 351           cop1buflength = 0;
 352         }
 353     }
 354   else
 355     {
 356       /* We have a 16 bit core insn and a 16 bit copro insn.  */
 357       corebuflength = 2;
 358       cop1buflength = 2;
 359     }
 360
 361   /* Now we have the distrubution set.  Print them out.  */
 362   status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
 363                                  cop1buflength, cop2buflength);
 364
 365   return status;
 366 }
 367
 368 static int
 369 mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 370 {
 371   int status;
 372   int buflength;
 373   int corebuflength;
 374   int cop1buflength;
 375   int cop2buflength;
 376   bfd_byte buf[CGEN_MAX_INSN_SIZE];
 377   char indicator16[1];
 378   char indicator64[4];
 379
 380   /* At this time we're not supporting internally parallel
 381      coprocessors, so cop2buflength will always be 0.  */
 382   cop2buflength = 0;
 383
 384   /* Read in 64 bits.  */
 385   buflength = 8; /* VLIW insn spans 8 bytes.  */
 386   status = (*info->read_memory_func) (pc, buf, buflength, info);
 387
 388   if (status != 0)
 389     {
 390       (*info->memory_error_func) (status, pc, info);
 391       return -1;
 392     }
 393
 394   /* We have all 64 bits in the buffer now.  We have to figure out
 395      what combination of instruction sizes are present.  The two
 396      high order bits will indicate whether or not we have a 16 bit
 397      core insn or not.  If not, then we have to look at the 7,8th
 398      bytes to tell whether we have 64 bit copro insn or a 32 bit
 399      core insn with a 32 bit copro insn.  Endianness will make a
 400      difference here.  */
 401
 402   /* Put the big endian representation of the bytes to be examined
 403      in the temporary buffers for examination.  */
 404
 405   /* indicator16[0] = buf[0];  */
 406   if (info->endian == BFD_ENDIAN_BIG)
 407     {
 408       indicator16[0] = buf[0];
 409       indicator64[0] = buf[0];
 410       indicator64[1] = buf[1];
 411       indicator64[2] = buf[2];
 412       indicator64[3] = buf[3];
 413     }
 414   else
 415     {
 416       indicator16[0] = buf[1];
 417       indicator64[0] = buf[1];
 418       indicator64[1] = buf[0];
 419       indicator64[2] = buf[3];
 420       indicator64[3] = buf[2];
 421     }
 422
 423   /* If the two high order bits are 00, 01 or 10, we have a 16 bit
 424      core insn and a 48 bit copro insn.  */
 425
 426   if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40))
 427     {
 428       if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07
 429           && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0))
 430         {
 431           /* We have a 64 bit copro insn.  */
 432           corebuflength = 0;
 433           /* All 8 bytes are one copro insn.  */
 434           cop1buflength = 8;
 435         }
 436       else
 437         {
 438           /* We have a 32 bit core insn and a 32 bit copro insn.  */
 439           corebuflength = 4;
 440           cop1buflength = 4;
 441         }
 442     }
 443   else
 444     {
 445       /* We have a 16 bit core insn and a 48 bit copro insn.  */
 446       corebuflength = 2;
 447       cop1buflength = 6;
 448     }
 449
 450   /* Now we have the distrubution set.  Print them out. */
 451   status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength,
 452                                  cop1buflength, cop2buflength);
 453
 454   return status;
 455 }
 456
 457 #ifdef MEP_IVC2_SUPPORTED
 458
 459 static int
 460 print_slot_insn (CGEN_CPU_DESC cd,
 461                  bfd_vma pc,
 462                  disassemble_info *info,
 463                  SLOTS_ATTR slot,
 464                  bfd_byte *buf)
 465 {
 466   const CGEN_INSN_LIST *insn_list;
 467   CGEN_INSN_INT insn_value;
 468   CGEN_EXTRACT_INFO ex_info;
 469
 470   insn_value = cgen_get_insn_value (cd, buf, 32);
 471
 472   /* Fill in ex_info fields like read_insn would.  Don't actually call
 473      read_insn, since the incoming buffer is already read (and possibly
 474      modified a la m32r).  */
 475   ex_info.valid = (1 << 8) - 1;
 476   ex_info.dis_info = info;
 477   ex_info.insn_bytes = buf;
 478
 479   /* The instructions are stored in hash lists.
 480      Pick the first one and keep trying until we find the right one.  */
 481
 482   insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
 483   while (insn_list != NULL)
 484     {
 485       const CGEN_INSN *insn = insn_list->insn;
 486       CGEN_FIELDS fields;
 487       int length;
 488
 489       if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
 490            && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
 491           || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
 492         {
 493           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 494           continue;
 495         }
 496
 497       if ((insn_value & CGEN_INSN_BASE_MASK (insn))
 498           == CGEN_INSN_BASE_VALUE (insn))
 499         {
 500           /* Printing is handled in two passes.  The first pass parses the
 501              machine insn and extracts the fields.  The second pass prints
 502              them.  */
 503
 504           length = CGEN_EXTRACT_FN (cd, insn)
 505             (cd, insn, &ex_info, insn_value, &fields, pc);
 506
 507           /* Length < 0 -> error.  */
 508           if (length < 0)
 509             return length;
 510           if (length > 0)
 511             {
 512               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 513               /* Length is in bits, result is in bytes.  */
 514               return length / 8;
 515             }
 516         }
 517
 518       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 519     }
 520
 521   if (slot == SLOTS_P0S)
 522     (*info->fprintf_func) (info->stream, "*unknown-p0s*");
 523   else if (slot == SLOTS_P0)
 524     (*info->fprintf_func) (info->stream, "*unknown-p0*");
 525   else if (slot == SLOTS_P1)
 526     (*info->fprintf_func) (info->stream, "*unknown-p1*");
 527   else if (slot == SLOTS_C3)
 528     (*info->fprintf_func) (info->stream, "*unknown-c3*");
 529   return 0;
 530 }
 531
 532 static int
 533 mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED)
 534 {
 535   int status;
 536   int buflength;
 537   bfd_byte buf[8];
 538   bfd_byte insn[8];
 539   int e;
 540
 541   /* At this time we're not supporting internally parallel
 542      coprocessors, so cop2buflength will always be 0.  */
 543
 544   /* Read in 64 bits.  */
 545   buflength = 8; /* VLIW insn spans 8 bytes.  */
 546   status = (*info->read_memory_func) (pc, buf, buflength, info);
 547
 548   if (status != 0)
 549     {
 550       (*info->memory_error_func) (status, pc, info);
 551       return -1;
 552     }
 553
 554   if (info->endian == BFD_ENDIAN_LITTLE)
 555     e = 1;
 556   else
 557     e = 0;
 558
 559   if (((unsigned char)buf[0^e] & 0xf0) < 0xc0)
 560     {
 561       /*      <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
 562       /* V1   [-----core-----][--------p0s-------][------------p1------------] */
 563
 564       print_insn (cd, pc, info, buf, 2);
 565
 566       insn[0^e] = 0;
 567       insn[1^e] = buf[2^e];
 568       insn[2^e] = buf[3^e];
 569       insn[3^e] = buf[4^e] & 0xf0;
 570       (*info->fprintf_func) (info->stream, " + ");
 571       print_slot_insn (cd, pc, info, SLOTS_P0S, insn);
 572
 573       insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
 574       insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
 575       insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
 576       insn[3^e] = buf[7^e] << 4;
 577       (*info->fprintf_func) (info->stream, " + ");
 578       print_slot_insn (cd, pc, info, SLOTS_P1, insn);
 579     }
 580   else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07)
 581     {
 582       /*      <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
 583       /* V3   1111[--p0--]0111[--------p0--------][------------p1------------] */
 584       /*                                          00000000111111112222222233333333 */
 585
 586       insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4;
 587       insn[1^e] = buf[2^e];
 588       insn[2^e] = buf[3^e];
 589       insn[3^e] = buf[4^e] & 0xf0;
 590       print_slot_insn (cd, pc, info, SLOTS_P0, insn);
 591
 592       insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
 593       insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
 594       insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
 595       insn[3^e] = buf[7^e] << 4;
 596       (*info->fprintf_func) (info->stream, " + ");
 597       print_slot_insn (cd, pc, info, SLOTS_P1, insn);
 598     }
 599   else
 600     {
 601       /*      <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
 602       /* V2   [-------------core-------------]xxxx[------------p1------------] */
 603       print_insn (cd, pc, info, buf, 4);
 604
 605       insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
 606       insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
 607       insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
 608       insn[3^e] = buf[7^e] << 4;
 609       (*info->fprintf_func) (info->stream, " + ");
 610       print_slot_insn (cd, pc, info, SLOTS_P1, insn);
 611     }
 612
 613   return 8;
 614 }
 615
 616 #endif /* MEP_IVC2_SUPPORTED */
 617
 618 /* This is a hack.  SID calls this to update the disassembler as the
 619    CPU changes modes.  */
 620 static int mep_ivc2_disassemble_p = 0;
 621 static int mep_ivc2_vliw_disassemble_p = 0;
 622
 623 void
 624 mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx);
 625 void
 626 mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx)
 627 {
 628   mep_ivc2_disassemble_p = ivc2_p;
 629   mep_ivc2_vliw_disassemble_p = vliw_p;
 630   mep_config_index = cfg_idx;
 631 }
 632
 633 static int
 634 mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 635 {
 636   int status;
 637   int cop_type;
 638   int ivc2 = 0;
 639   static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL;
 640
 641   if (ivc2_core_isa == NULL)
 642     {
 643       /* IVC2 has some core-only coprocessor instructions.  We
 644          use COP32 to flag those, and COP64 for the VLIW ones,
 645          since they have the same names.  */
 646       ivc2_core_isa = cgen_bitset_create (MAX_ISAS);
 647     }
 648
 649   /* Extract and adapt to configuration number, if available. */
 650   if (info->section && info->section->owner)
 651     {
 652       bfd *abfd = info->section->owner;
 653       mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
 654       /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
 655
 656       cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
 657       if (cop_type == EF_MEP_COP_IVC2)
 658         ivc2 = 1;
 659     }
 660
 661   /* Picking the right ISA bitmask for the current context is tricky.  */
 662   if (info->section)
 663     {
 664       if (info->section->flags & SEC_MEP_VLIW)
 665         {
 666 #ifdef MEP_IVC2_SUPPORTED
 667           if (ivc2)
 668             {
 669               /* ivc2 has its own way of selecting its functions.  */
 670               cd->isas = & MEP_CORE_ISA;
 671               status = mep_examine_ivc2_insns (cd, pc, info);
 672             }
 673           else
 674 #endif
 675             /* Are we in 32 or 64 bit vliw mode?  */
 676             if (MEP_VLIW64)
 677               status = mep_examine_vliw64_insns (cd, pc, info);
 678             else
 679               status = mep_examine_vliw32_insns (cd, pc, info);
 680           /* Both the above branches set their own isa bitmasks.  */
 681         }
 682       else
 683         {
 684           if (ivc2)
 685             {
 686               cgen_bitset_clear (ivc2_core_isa);
 687               cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa);
 688               cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa);
 689               cd->isas = ivc2_core_isa;
 690             }
 691           else
 692             cd->isas = & MEP_CORE_ISA;
 693           status = default_print_insn (cd, pc, info);
 694         }
 695     }
 696   else /* sid or gdb */
 697     {
 698 #ifdef MEP_IVC2_SUPPORTED
 699       if (mep_ivc2_disassemble_p)
 700         {
 701           if (mep_ivc2_vliw_disassemble_p)
 702             {
 703               cd->isas = & MEP_CORE_ISA;
 704               status = mep_examine_ivc2_insns (cd, pc, info);
 705               return status;
 706             }
 707           else
 708             {
 709               if (ivc2)
 710                 cd->isas = ivc2_core_isa;
 711             }
 712         }
 713 #endif
 714
 715       status = default_print_insn (cd, pc, info);
 716     }
 717
 718   return status;
 719 }
 720
 721
 722 /* -- opc.c */
 723
 724 void mep_cgen_print_operand
 725   (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 726
 727 /* Main entry point for printing operands.
 728    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 729    of dis-asm.h on cgen.h.
 730
 731    This function is basically just a big switch statement.  Earlier versions
 732    used tables to look up the function to use, but
 733    - if the table contains both assembler and disassembler functions then
 734      the disassembler contains much of the assembler and vice-versa,
 735    - there's a lot of inlining possibilities as things grow,
 736    - using a switch statement avoids the function call overhead.
 737
 738    This function could be moved into `print_insn_normal', but keeping it
 739    separate makes clear the interface between `print_insn_normal' and each of
 740    the handlers.  */
 741
 742 void
 743 mep_cgen_print_operand (CGEN_CPU_DESC cd,
 744                            int opindex,
 745                            void * xinfo,
 746                            CGEN_FIELDS *fields,
 747                            void const *attrs ATTRIBUTE_UNUSED,
 748                            bfd_vma pc,
 749                            int length)
 750 {
 751   disassemble_info *info = (disassemble_info *) xinfo;
 752
 753   switch (opindex)
 754     {
 755     case MEP_OPERAND_ADDR24A4 :
 756       print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 757       break;
 758     case MEP_OPERAND_C5RMUIMM20 :
 759       print_normal (cd, info, fields->f_c5_rmuimm20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 760       break;
 761     case MEP_OPERAND_C5RNMUIMM24 :
 762       print_normal (cd, info, fields->f_c5_rnmuimm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 763       break;
 764     case MEP_OPERAND_CALLNUM :
 765       print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 766       break;
 767     case MEP_OPERAND_CCCC :
 768       print_normal (cd, info, fields->f_rm, 0, pc, length);
 769       break;
 770     case MEP_OPERAND_CCRN :
 771       print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
 772       break;
 773     case MEP_OPERAND_CDISP10 :
 774       print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 775       break;
 776     case MEP_OPERAND_CDISP10A2 :
 777       print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 778       break;
 779     case MEP_OPERAND_CDISP10A4 :
 780       print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 781       break;
 782     case MEP_OPERAND_CDISP10A8 :
 783       print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 784       break;
 785     case MEP_OPERAND_CDISP12 :
 786       print_normal (cd, info, fields->f_12s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 787       break;
 788     case MEP_OPERAND_CIMM4 :
 789       print_normal (cd, info, fields->f_rn, 0, pc, length);
 790       break;
 791     case MEP_OPERAND_CIMM5 :
 792       print_normal (cd, info, fields->f_5u24, 0, pc, length);
 793       break;
 794     case MEP_OPERAND_CODE16 :
 795       print_normal (cd, info, fields->f_16u16, 0, pc, length);
 796       break;
 797     case MEP_OPERAND_CODE24 :
 798       print_normal (cd, info, fields->f_24u4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 799       break;
 800     case MEP_OPERAND_CP_FLAG :
 801       print_keyword (cd, info, & mep_cgen_opval_h_ccr, 0, 0);
 802       break;
 803     case MEP_OPERAND_CRN :
 804       print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crn, 0);
 805       break;
 806     case MEP_OPERAND_CRN64 :
 807       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crn, 0);
 808       break;
 809     case MEP_OPERAND_CRNX :
 810       print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
 811       break;
 812     case MEP_OPERAND_CRNX64 :
 813       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
 814       break;
 815     case MEP_OPERAND_CROC :
 816       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u7, 0);
 817       break;
 818     case MEP_OPERAND_CROP :
 819       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u23, 0);
 820       break;
 821     case MEP_OPERAND_CRPC :
 822       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u26, 0);
 823       break;
 824     case MEP_OPERAND_CRPP :
 825       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u18, 0);
 826       break;
 827     case MEP_OPERAND_CRQC :
 828       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u21, 0);
 829       break;
 830     case MEP_OPERAND_CRQP :
 831       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u13, 0);
 832       break;
 833     case MEP_OPERAND_CSRN :
 834       print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
 835       break;
 836     case MEP_OPERAND_CSRN_IDX :
 837       print_normal (cd, info, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 838       break;
 839     case MEP_OPERAND_DBG :
 840       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
 841       break;
 842     case MEP_OPERAND_DEPC :
 843       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
 844       break;
 845     case MEP_OPERAND_EPC :
 846       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
 847       break;
 848     case MEP_OPERAND_EXC :
 849       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
 850       break;
 851     case MEP_OPERAND_HI :
 852       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
 853       break;
 854     case MEP_OPERAND_IMM16P0 :
 855       print_normal (cd, info, fields->f_ivc2_imm16p0, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
 856       break;
 857     case MEP_OPERAND_IMM3P12 :
 858       print_normal (cd, info, fields->f_ivc2_3u12, 0, pc, length);
 859       break;
 860     case MEP_OPERAND_IMM3P25 :
 861       print_normal (cd, info, fields->f_ivc2_3u25, 0, pc, length);
 862       break;
 863     case MEP_OPERAND_IMM3P4 :
 864       print_normal (cd, info, fields->f_ivc2_3u4, 0, pc, length);
 865       break;
 866     case MEP_OPERAND_IMM3P5 :
 867       print_normal (cd, info, fields->f_ivc2_3u5, 0, pc, length);
 868       break;
 869     case MEP_OPERAND_IMM3P9 :
 870       print_normal (cd, info, fields->f_ivc2_3u9, 0, pc, length);
 871       break;
 872     case MEP_OPERAND_IMM4P10 :
 873       print_normal (cd, info, fields->f_ivc2_4u10, 0, pc, length);
 874       break;
 875     case MEP_OPERAND_IMM4P4 :
 876       print_normal (cd, info, fields->f_ivc2_4u4, 0, pc, length);
 877       break;
 878     case MEP_OPERAND_IMM4P8 :
 879       print_normal (cd, info, fields->f_ivc2_4u8, 0, pc, length);
 880       break;
 881     case MEP_OPERAND_IMM5P23 :
 882       print_normal (cd, info, fields->f_ivc2_5u23, 0, pc, length);
 883       break;
 884     case MEP_OPERAND_IMM5P3 :
 885       print_normal (cd, info, fields->f_ivc2_5u3, 0, pc, length);
 886       break;
 887     case MEP_OPERAND_IMM5P7 :
 888       print_normal (cd, info, fields->f_ivc2_5u7, 0, pc, length);
 889       break;
 890     case MEP_OPERAND_IMM5P8 :
 891       print_normal (cd, info, fields->f_ivc2_5u8, 0, pc, length);
 892       break;
 893     case MEP_OPERAND_IMM6P2 :
 894       print_normal (cd, info, fields->f_ivc2_6u2, 0, pc, length);
 895       break;
 896     case MEP_OPERAND_IMM6P6 :
 897       print_normal (cd, info, fields->f_ivc2_6u6, 0, pc, length);
 898       break;
 899     case MEP_OPERAND_IMM8P0 :
 900       print_normal (cd, info, fields->f_ivc2_8u0, 0, pc, length);
 901       break;
 902     case MEP_OPERAND_IMM8P20 :
 903       print_normal (cd, info, fields->f_ivc2_8u20, 0, pc, length);
 904       break;
 905     case MEP_OPERAND_IMM8P4 :
 906       print_normal (cd, info, fields->f_ivc2_8u4, 0, pc, length);
 907       break;
 908     case MEP_OPERAND_IVC_X_0_2 :
 909       print_normal (cd, info, fields->f_ivc2_2u0, 0, pc, length);
 910       break;
 911     case MEP_OPERAND_IVC_X_0_3 :
 912       print_normal (cd, info, fields->f_ivc2_3u0, 0, pc, length);
 913       break;
 914     case MEP_OPERAND_IVC_X_0_4 :
 915       print_normal (cd, info, fields->f_ivc2_4u0, 0, pc, length);
 916       break;
 917     case MEP_OPERAND_IVC_X_0_5 :
 918       print_normal (cd, info, fields->f_ivc2_5u0, 0, pc, length);
 919       break;
 920     case MEP_OPERAND_IVC_X_6_1 :
 921       print_normal (cd, info, fields->f_ivc2_1u6, 0, pc, length);
 922       break;
 923     case MEP_OPERAND_IVC_X_6_2 :
 924       print_normal (cd, info, fields->f_ivc2_2u6, 0, pc, length);
 925       break;
 926     case MEP_OPERAND_IVC_X_6_3 :
 927       print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
 928       break;
 929     case MEP_OPERAND_IVC2_ACC0_0 :
 930       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 931       break;
 932     case MEP_OPERAND_IVC2_ACC0_1 :
 933       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 934       break;
 935     case MEP_OPERAND_IVC2_ACC0_2 :
 936       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 937       break;
 938     case MEP_OPERAND_IVC2_ACC0_3 :
 939       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 940       break;
 941     case MEP_OPERAND_IVC2_ACC0_4 :
 942       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 943       break;
 944     case MEP_OPERAND_IVC2_ACC0_5 :
 945       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 946       break;
 947     case MEP_OPERAND_IVC2_ACC0_6 :
 948       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 949       break;
 950     case MEP_OPERAND_IVC2_ACC0_7 :
 951       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 952       break;
 953     case MEP_OPERAND_IVC2_ACC1_0 :
 954       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 955       break;
 956     case MEP_OPERAND_IVC2_ACC1_1 :
 957       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 958       break;
 959     case MEP_OPERAND_IVC2_ACC1_2 :
 960       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 961       break;
 962     case MEP_OPERAND_IVC2_ACC1_3 :
 963       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 964       break;
 965     case MEP_OPERAND_IVC2_ACC1_4 :
 966       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 967       break;
 968     case MEP_OPERAND_IVC2_ACC1_5 :
 969       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 970       break;
 971     case MEP_OPERAND_IVC2_ACC1_6 :
 972       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 973       break;
 974     case MEP_OPERAND_IVC2_ACC1_7 :
 975       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 976       break;
 977     case MEP_OPERAND_IVC2_CC :
 978       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 979       break;
 980     case MEP_OPERAND_IVC2_COFA0 :
 981       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 982       break;
 983     case MEP_OPERAND_IVC2_COFA1 :
 984       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 985       break;
 986     case MEP_OPERAND_IVC2_COFR0 :
 987       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 988       break;
 989     case MEP_OPERAND_IVC2_COFR1 :
 990       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 991       break;
 992     case MEP_OPERAND_IVC2_CSAR0 :
 993       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 994       break;
 995     case MEP_OPERAND_IVC2_CSAR1 :
 996       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
 997       break;
 998     case MEP_OPERAND_IVC2C3CCRN :
 999       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
1000       break;
1001     case MEP_OPERAND_IVC2CCRN :
1002       print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
1003       break;
1004     case MEP_OPERAND_IVC2CRN :
1005       print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
1006       break;
1007     case MEP_OPERAND_IVC2RM :
1008       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_ivc2_crm, 0);
1009       break;
1010     case MEP_OPERAND_LO :
1011       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1012       break;
1013     case MEP_OPERAND_LP :
1014       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1015       break;
1016     case MEP_OPERAND_MB0 :
1017       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1018       break;
1019     case MEP_OPERAND_MB1 :
1020       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1021       break;
1022     case MEP_OPERAND_ME0 :
1023       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1024       break;
1025     case MEP_OPERAND_ME1 :
1026       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1027       break;
1028     case MEP_OPERAND_NPC :
1029       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1030       break;
1031     case MEP_OPERAND_OPT :
1032       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1033       break;
1034     case MEP_OPERAND_PCABS24A2 :
1035       print_address (cd, info, fields->f_24u5a2n, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1036       break;
1037     case MEP_OPERAND_PCREL12A2 :
1038       print_address (cd, info, fields->f_12s4a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1039       break;
1040     case MEP_OPERAND_PCREL17A2 :
1041       print_address (cd, info, fields->f_17s16a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1042       break;
1043     case MEP_OPERAND_PCREL24A2 :
1044       print_address (cd, info, fields->f_24s5a2n, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1045       break;
1046     case MEP_OPERAND_PCREL8A2 :
1047       print_address (cd, info, fields->f_8s8a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
1048       break;
1049     case MEP_OPERAND_PSW :
1050       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1051       break;
1052     case MEP_OPERAND_R0 :
1053       print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1054       break;
1055     case MEP_OPERAND_R1 :
1056       print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1057       break;
1058     case MEP_OPERAND_RL :
1059       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0);
1060       break;
1061     case MEP_OPERAND_RL5 :
1062       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0);
1063       break;
1064     case MEP_OPERAND_RM :
1065       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
1066       break;
1067     case MEP_OPERAND_RMA :
1068       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
1069       break;
1070     case MEP_OPERAND_RN :
1071       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1072       break;
1073     case MEP_OPERAND_RN3 :
1074       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1075       break;
1076     case MEP_OPERAND_RN3C :
1077       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1078       break;
1079     case MEP_OPERAND_RN3L :
1080       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1081       break;
1082     case MEP_OPERAND_RN3S :
1083       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1084       break;
1085     case MEP_OPERAND_RN3UC :
1086       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1087       break;
1088     case MEP_OPERAND_RN3UL :
1089       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1090       break;
1091     case MEP_OPERAND_RN3US :
1092       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0);
1093       break;
1094     case MEP_OPERAND_RNC :
1095       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1096       break;
1097     case MEP_OPERAND_RNL :
1098       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1099       break;
1100     case MEP_OPERAND_RNS :
1101       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1102       break;
1103     case MEP_OPERAND_RNUC :
1104       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1105       break;
1106     case MEP_OPERAND_RNUL :
1107       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1108       break;
1109     case MEP_OPERAND_RNUS :
1110       print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0);
1111       break;
1112     case MEP_OPERAND_SAR :
1113       print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
1114       break;
1115     case MEP_OPERAND_SDISP16 :
1116       print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1117       break;
1118     case MEP_OPERAND_SIMM16 :
1119       print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1120       break;
1121     case MEP_OPERAND_SIMM16P0 :
1122       print_normal (cd, info, fields->f_ivc2_simm16p0, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1123       break;
1124     case MEP_OPERAND_SIMM6 :
1125       print_normal (cd, info, fields->f_6s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1126       break;
1127     case MEP_OPERAND_SIMM8 :
1128       print_normal (cd, info, fields->f_8s8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW), pc, length);
1129       break;
1130     case MEP_OPERAND_SIMM8P0 :
1131       print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1132       break;
1133     case MEP_OPERAND_SIMM8P20 :
1134       print_normal (cd, info, fields->f_ivc2_8s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1135       break;
1136     case MEP_OPERAND_SIMM8P4 :
1137       print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1138       break;
1139     case MEP_OPERAND_SP :
1140       print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1141       break;
1142     case MEP_OPERAND_SPR :
1143       print_spreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1144       break;
1145     case MEP_OPERAND_TP :
1146       print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1147       break;
1148     case MEP_OPERAND_TPR :
1149       print_tpreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
1150       break;
1151     case MEP_OPERAND_UDISP2 :
1152       print_normal (cd, info, fields->f_2u6, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1153       break;
1154     case MEP_OPERAND_UDISP7 :
1155       print_normal (cd, info, fields->f_7u9, 0, pc, length);
1156       break;
1157     case MEP_OPERAND_UDISP7A2 :
1158       print_normal (cd, info, fields->f_7u9a2, 0, pc, length);
1159       break;
1160     case MEP_OPERAND_UDISP7A4 :
1161       print_normal (cd, info, fields->f_7u9a4, 0, pc, length);
1162       break;
1163     case MEP_OPERAND_UIMM16 :
1164       print_normal (cd, info, fields->f_16u16, 0, pc, length);
1165       break;
1166     case MEP_OPERAND_UIMM2 :
1167       print_normal (cd, info, fields->f_2u10, 0, pc, length);
1168       break;
1169     case MEP_OPERAND_UIMM24 :
1170       print_normal (cd, info, fields->f_24u8n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
1171       break;
1172     case MEP_OPERAND_UIMM3 :
1173       print_normal (cd, info, fields->f_3u5, 0, pc, length);
1174       break;
1175     case MEP_OPERAND_UIMM4 :
1176       print_normal (cd, info, fields->f_4u8, 0, pc, length);
1177       break;
1178     case MEP_OPERAND_UIMM5 :
1179       print_normal (cd, info, fields->f_5u8, 0, pc, length);
1180       break;
1181     case MEP_OPERAND_UIMM7A4 :
1182       print_normal (cd, info, fields->f_7u9a4, 0, pc, length);
1183       break;
1184     case MEP_OPERAND_ZERO :
1185       print_normal (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
1186       break;
1187
1188     default :
1189       /* xgettext:c-format */
1190       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
1191                opindex);
1192     abort ();
1193   }
1194 }
1195
1196 cgen_print_fn * const mep_cgen_print_handlers[] =
1197 {
1198   print_insn_normal,
1199 };
1200
1201
1202 void
1203 mep_cgen_init_dis (CGEN_CPU_DESC cd)
1204 {
1205   mep_cgen_init_opcode_table (cd);
1206   mep_cgen_init_ibld_table (cd);
1207   cd->print_handlers = & mep_cgen_print_handlers[0];
1208   cd->print_operand = mep_cgen_print_operand;
1209 }
1210
1211 \f
1212 /* Default print handler.  */
1213
1214 static void
1215 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1216               void *dis_info,
1217               long value,
1218               unsigned int attrs,
1219               bfd_vma pc ATTRIBUTE_UNUSED,
1220               int length ATTRIBUTE_UNUSED)
1221 {
1222   disassemble_info *info = (disassemble_info *) dis_info;
1223
1224   /* Print the operand as directed by the attributes.  */
1225   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
1226     ; /* nothing to do */
1227   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
1228     (*info->fprintf_func) (info->stream, "%ld", value);
1229   else
1230     (*info->fprintf_func) (info->stream, "0x%lx", value);
1231 }
1232
1233 /* Default address handler.  */
1234
1235 static void
1236 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1237                void *dis_info,
1238                bfd_vma value,
1239                unsigned int attrs,
1240                bfd_vma pc ATTRIBUTE_UNUSED,
1241                int length ATTRIBUTE_UNUSED)
1242 {
1243   disassemble_info *info = (disassemble_info *) dis_info;
1244
1245   /* Print the operand as directed by the attributes.  */
1246   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
1247     ; /* Nothing to do.  */
1248   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
1249     (*info->print_address_func) (value, info);
1250   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
1251     (*info->print_address_func) (value, info);
1252   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
1253     (*info->fprintf_func) (info->stream, "%ld", (long) value);
1254   else
1255     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
1256 }
1257
1258 /* Keyword print handler.  */
1259
1260 static void
1261 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1262                void *dis_info,
1263                CGEN_KEYWORD *keyword_table,
1264                long value,
1265                unsigned int attrs ATTRIBUTE_UNUSED)
1266 {
1267   disassemble_info *info = (disassemble_info *) dis_info;
1268   const CGEN_KEYWORD_ENTRY *ke;
1269
1270   ke = cgen_keyword_lookup_value (keyword_table, value);
1271   if (ke != NULL)
1272     (*info->fprintf_func) (info->stream, "%s", ke->name);
1273   else
1274     (*info->fprintf_func) (info->stream, "???");
1275 }
1276 \f
1277 /* Default insn printer.
1278
1279    DIS_INFO is defined as `void *' so the disassembler needn't know anything
1280    about disassemble_info.  */
1281
1282 static void
1283 print_insn_normal (CGEN_CPU_DESC cd,
1284                    void *dis_info,
1285                    const CGEN_INSN *insn,
1286                    CGEN_FIELDS *fields,
1287                    bfd_vma pc,
1288                    int length)
1289 {
1290   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
1291   disassemble_info *info = (disassemble_info *) dis_info;
1292   const CGEN_SYNTAX_CHAR_TYPE *syn;
1293
1294   CGEN_INIT_PRINT (cd);
1295
1296   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
1297     {
1298       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
1299         {
1300           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
1301           continue;
1302         }
1303       if (CGEN_SYNTAX_CHAR_P (*syn))
1304         {
1305           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
1306           continue;
1307         }
1308
1309       /* We have an operand.  */
1310       mep_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
1311                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
1312     }
1313 }
1314 \f
1315 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
1316    the extract info.
1317    Returns 0 if all is well, non-zero otherwise.  */
1318
1319 static int
1320 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1321            bfd_vma pc,
1322            disassemble_info *info,
1323            bfd_byte *buf,
1324            int buflen,
1325            CGEN_EXTRACT_INFO *ex_info,
1326            unsigned long *insn_value)
1327 {
1328   int status = (*info->read_memory_func) (pc, buf, buflen, info);
1329
1330   if (status != 0)
1331     {
1332       (*info->memory_error_func) (status, pc, info);
1333       return -1;
1334     }
1335
1336   ex_info->dis_info = info;
1337   ex_info->valid = (1 << buflen) - 1;
1338   ex_info->insn_bytes = buf;
1339
1340   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
1341   return 0;
1342 }
1343
1344 /* Utility to print an insn.
1345    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
1346    The result is the size of the insn in bytes or zero for an unknown insn
1347    or -1 if an error occurs fetching data (memory_error_func will have
1348    been called).  */
1349
1350 static int
1351 print_insn (CGEN_CPU_DESC cd,
1352             bfd_vma pc,
1353             disassemble_info *info,
1354             bfd_byte *buf,
1355             unsigned int buflen)
1356 {
1357   CGEN_INSN_INT insn_value;
1358   const CGEN_INSN_LIST *insn_list;
1359   CGEN_EXTRACT_INFO ex_info;
1360   int basesize;
1361
1362   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
1363   basesize = cd->base_insn_bitsize < buflen * 8 ?
1364                                      cd->base_insn_bitsize : buflen * 8;
1365   insn_value = cgen_get_insn_value (cd, buf, basesize);
1366
1367
1368   /* Fill in ex_info fields like read_insn would.  Don't actually call
1369      read_insn, since the incoming buffer is already read (and possibly
1370      modified a la m32r).  */
1371   ex_info.valid = (1 << buflen) - 1;
1372   ex_info.dis_info = info;
1373   ex_info.insn_bytes = buf;
1374
1375   /* The instructions are stored in hash lists.
1376      Pick the first one and keep trying until we find the right one.  */
1377
1378   insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
1379   while (insn_list != NULL)
1380     {
1381       const CGEN_INSN *insn = insn_list->insn;
1382       CGEN_FIELDS fields;
1383       int length;
1384       unsigned long insn_value_cropped;
1385
1386 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
1387       /* Not needed as insn shouldn't be in hash lists if not supported.  */
1388       /* Supported by this cpu?  */
1389       if (! mep_cgen_insn_supported (cd, insn))
1390         {
1391           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1392           continue;
1393         }
1394 #endif
1395
1396       /* Basic bit mask must be correct.  */
1397       /* ??? May wish to allow target to defer this check until the extract
1398          handler.  */
1399
1400       /* Base size may exceed this instruction's size.  Extract the
1401          relevant part from the buffer. */
1402       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
1403           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1404         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
1405                                            info->endian == BFD_ENDIAN_BIG);
1406       else
1407         insn_value_cropped = insn_value;
1408
1409       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
1410           == CGEN_INSN_BASE_VALUE (insn))
1411         {
1412           /* Printing is handled in two passes.  The first pass parses the
1413              machine insn and extracts the fields.  The second pass prints
1414              them.  */
1415
1416           /* Make sure the entire insn is loaded into insn_value, if it
1417              can fit.  */
1418           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
1419               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
1420             {
1421               unsigned long full_insn_value;
1422               int rc = read_insn (cd, pc, info, buf,
1423                                   CGEN_INSN_BITSIZE (insn) / 8,
1424                                   & ex_info, & full_insn_value);
1425               if (rc != 0)
1426                 return rc;
1427               length = CGEN_EXTRACT_FN (cd, insn)
1428                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
1429             }
1430           else
1431             length = CGEN_EXTRACT_FN (cd, insn)
1432               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
1433
1434           /* Length < 0 -> error.  */
1435           if (length < 0)
1436             return length;
1437           if (length > 0)
1438             {
1439               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
1440               /* Length is in bits, result is in bytes.  */
1441               return length / 8;
1442             }
1443         }
1444
1445       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
1446     }
1447
1448   return 0;
1449 }
1450
1451 /* Default value for CGEN_PRINT_INSN.
1452    The result is the size of the insn in bytes or zero for an unknown insn
1453    or -1 if an error occured fetching bytes.  */
1454
1455 #ifndef CGEN_PRINT_INSN
1456 #define CGEN_PRINT_INSN default_print_insn
1457 #endif
1458
1459 static int
1460 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
1461 {
1462   bfd_byte buf[CGEN_MAX_INSN_SIZE];
1463   int buflen;
1464   int status;
1465
1466   /* Attempt to read the base part of the insn.  */
1467   buflen = cd->base_insn_bitsize / 8;
1468   status = (*info->read_memory_func) (pc, buf, buflen, info);
1469
1470   /* Try again with the minimum part, if min < base.  */
1471   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
1472     {
1473       buflen = cd->min_insn_bitsize / 8;
1474       status = (*info->read_memory_func) (pc, buf, buflen, info);
1475     }
1476
1477   if (status != 0)
1478     {
1479       (*info->memory_error_func) (status, pc, info);
1480       return -1;
1481     }
1482
1483   return print_insn (cd, pc, info, buf, buflen);
1484 }
1485
1486 /* Main entry point.
1487    Print one instruction from PC on INFO->STREAM.
1488    Return the size of the instruction (in bytes).  */
1489
1490 typedef struct cpu_desc_list
1491 {
1492   struct cpu_desc_list *next;
1493   CGEN_BITSET *isa;
1494   int mach;
1495   int endian;
1496   CGEN_CPU_DESC cd;
1497 } cpu_desc_list;
1498
1499 int
1500 print_insn_mep (bfd_vma pc, disassemble_info *info)
1501 {
1502   static cpu_desc_list *cd_list = 0;
1503   cpu_desc_list *cl = 0;
1504   static CGEN_CPU_DESC cd = 0;
1505   static CGEN_BITSET *prev_isa;
1506   static int prev_mach;
1507   static int prev_endian;
1508   int length;
1509   CGEN_BITSET *isa;
1510   int mach;
1511   int endian = (info->endian == BFD_ENDIAN_BIG
1512                 ? CGEN_ENDIAN_BIG
1513                 : CGEN_ENDIAN_LITTLE);
1514   enum bfd_architecture arch;
1515
1516   /* ??? gdb will set mach but leave the architecture as "unknown" */
1517 #ifndef CGEN_BFD_ARCH
1518 #define CGEN_BFD_ARCH bfd_arch_mep
1519 #endif
1520   arch = info->arch;
1521   if (arch == bfd_arch_unknown)
1522     arch = CGEN_BFD_ARCH;
1523
1524   /* There's no standard way to compute the machine or isa number
1525      so we leave it to the target.  */
1526 #ifdef CGEN_COMPUTE_MACH
1527   mach = CGEN_COMPUTE_MACH (info);
1528 #else
1529   mach = info->mach;
1530 #endif
1531
1532 #ifdef CGEN_COMPUTE_ISA
1533   {
1534     static CGEN_BITSET *permanent_isa;
1535
1536     if (!permanent_isa)
1537       permanent_isa = cgen_bitset_create (MAX_ISAS);
1538     isa = permanent_isa;
1539     cgen_bitset_clear (isa);
1540     cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
1541   }
1542 #else
1543   isa = info->insn_sets;
1544 #endif
1545
1546   /* If we've switched cpu's, try to find a handle we've used before */
1547   if (cd
1548       && (cgen_bitset_compare (isa, prev_isa) != 0
1549           || mach != prev_mach
1550           || endian != prev_endian))
1551     {
1552       cd = 0;
1553       for (cl = cd_list; cl; cl = cl->next)
1554         {
1555           if (cgen_bitset_compare (cl->isa, isa) == 0 &&
1556               cl->mach == mach &&
1557               cl->endian == endian)
1558             {
1559               cd = cl->cd;
1560               prev_isa = cd->isas;
1561               break;
1562             }
1563         }
1564     }
1565
1566   /* If we haven't initialized yet, initialize the opcode table.  */
1567   if (! cd)
1568     {
1569       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
1570       const char *mach_name;
1571
1572       if (!arch_type)
1573         abort ();
1574       mach_name = arch_type->printable_name;
1575
1576       prev_isa = cgen_bitset_copy (isa);
1577       prev_mach = mach;
1578       prev_endian = endian;
1579       cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
1580                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
1581                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
1582                                  CGEN_CPU_OPEN_END);
1583       if (!cd)
1584         abort ();
1585
1586       /* Save this away for future reference.  */
1587       cl = xmalloc (sizeof (struct cpu_desc_list));
1588       cl->cd = cd;
1589       cl->isa = prev_isa;
1590       cl->mach = mach;
1591       cl->endian = endian;
1592       cl->next = cd_list;
1593       cd_list = cl;
1594
1595       mep_cgen_init_dis (cd);
1596     }
1597
1598   /* We try to have as much common code as possible.
1599      But at this point some targets need to take over.  */
1600   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
1601      but if not possible try to move this hook elsewhere rather than
1602      have two hooks.  */
1603   length = CGEN_PRINT_INSN (cd, pc, info);
1604   if (length > 0)
1605     return length;
1606   if (length < 0)
1607     return -1;
1608
1609   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
1610   return cd->default_insn_bitsize / 8;
1611 }