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include/opcode/
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 /* The microMIPS registers with type b. */
61 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
62
63 /* The microMIPS registers with type c. */
64 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
65
66 /* The microMIPS registers with type d. */
67 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
68
69 /* The microMIPS registers with type e. */
70 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
71
72 /* The microMIPS registers with type f. */
73 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
74
75 /* The microMIPS registers with type g. */
76 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
77
78 /* The microMIPS registers with type h. */
79 static const unsigned int micromips_to_32_reg_h_map1[] =
80 {
81 5, 5, 6, 4, 4, 4, 4, 4
82 };
83 static const unsigned int micromips_to_32_reg_h_map2[] =
84 {
85 6, 7, 7, 21, 22, 5, 6, 7
86 };
87
88 /* The microMIPS registers with type j: 32 registers. */
89
90 /* The microMIPS registers with type l. */
91 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
92
93 /* The microMIPS registers with type m. */
94 static const unsigned int micromips_to_32_reg_m_map[] =
95 {
96 0, 17, 2, 3, 16, 18, 19, 20
97 };
98
99 /* The microMIPS registers with type n. */
100 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
101
102 /* The microMIPS registers with type p: 32 registers. */
103
104 /* The microMIPS registers with type q. */
105 static const unsigned int micromips_to_32_reg_q_map[] =
106 {
107 0, 17, 2, 3, 4, 5, 6, 7
108 };
109
110 /* reg type s is $29. */
111
112 /* reg type t is the same as the last register. */
113
114 /* reg type y is $31. */
115
116 /* reg type z is $0. */
117
118 /* micromips imm B type. */
119 static const int micromips_imm_b_map[8] =
120 {
121 1, 4, 8, 12, 16, 20, 24, -1
122 };
123
124 /* micromips imm C type. */
125 static const int micromips_imm_c_map[16] =
126 {
127 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
128 };
129
130 /* micromips imm D type: (-512..511)<<1. */
131 /* micromips imm E type: (-64..63)<<1. */
132 /* micromips imm F type: (0..63). */
133 /* micromips imm G type: (-1..14). */
134 /* micromips imm H type: (0..15)<<1. */
135 /* micromips imm I type: (-1..126). */
136 /* micromips imm J type: (0..15)<<2. */
137 /* micromips imm L type: (0..15). */
138 /* micromips imm M type: (1..8). */
139 /* micromips imm W type: (0..63)<<2. */
140 /* micromips imm X type: (-8..7). */
141 /* micromips imm Y type: (-258..-3, 2..257)<<2. */
142
143 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
144
145
146 static const char * const mips_gpr_names_numeric[32] =
147 {
148 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
149 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
150 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
151 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
152 };
153
154 static const char * const mips_gpr_names_oldabi[32] =
155 {
156 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
157 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
158 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
159 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
160 };
161
162 static const char * const mips_gpr_names_newabi[32] =
163 {
164 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
165 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
166 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
167 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
168 };
169
170 static const char * const mips_fpr_names_numeric[32] =
171 {
172 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
173 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
174 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
175 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
176 };
177
178 static const char * const mips_fpr_names_32[32] =
179 {
180 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
181 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
182 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
183 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
184 };
185
186 static const char * const mips_fpr_names_n32[32] =
187 {
188 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
189 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
190 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
191 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
192 };
193
194 static const char * const mips_fpr_names_64[32] =
195 {
196 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
197 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
198 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
199 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
200 };
201
202 static const char * const mips_cp0_names_numeric[32] =
203 {
204 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
205 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
206 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
207 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
208 };
209
210 static const char * const mips_cp0_names_r3000[32] =
211 {
212 "c0_index", "c0_random", "c0_entrylo", "$3",
213 "c0_context", "$5", "$6", "$7",
214 "c0_badvaddr", "$9", "c0_entryhi", "$11",
215 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
216 "$16", "$17", "$18", "$19",
217 "$20", "$21", "$22", "$23",
218 "$24", "$25", "$26", "$27",
219 "$28", "$29", "$30", "$31",
220 };
221
222 static const char * const mips_cp0_names_r4000[32] =
223 {
224 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
225 "c0_context", "c0_pagemask", "c0_wired", "$7",
226 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
227 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
228 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
229 "c0_xcontext", "$21", "$22", "$23",
230 "$24", "$25", "c0_ecc", "c0_cacheerr",
231 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
232 };
233
234 static const char * const mips_cp0_names_r5900[32] =
235 {
236 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
237 "c0_context", "c0_pagemask", "c0_wired", "$7",
238 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
239 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
240 "c0_config", "$17", "$18", "$19",
241 "$20", "$21", "$22", "c0_badpaddr",
242 "c0_depc", "c0_perfcnt", "$26", "$27",
243 "c0_taglo", "c0_taghi", "c0_errorepc", "$31"
244 };
245
246 static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] =
247 {
248 { 24, 2, "c0_iab" },
249 { 24, 3, "c0_iabm" },
250 { 24, 4, "c0_dab" },
251 { 24, 5, "c0_dabm" },
252 { 24, 6, "c0_dvb" },
253 { 24, 7, "c0_dvbm" },
254 { 25, 1, "c0_perfcnt,1" },
255 { 25, 2, "c0_perfcnt,2" }
256 };
257
258 static const char * const mips_cp0_names_mips3264[32] =
259 {
260 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
261 "c0_context", "c0_pagemask", "c0_wired", "$7",
262 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
263 "c0_status", "c0_cause", "c0_epc", "c0_prid",
264 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
265 "c0_xcontext", "$21", "$22", "c0_debug",
266 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
267 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
268 };
269
270 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
271 {
272 { 16, 1, "c0_config1" },
273 { 16, 2, "c0_config2" },
274 { 16, 3, "c0_config3" },
275 { 18, 1, "c0_watchlo,1" },
276 { 18, 2, "c0_watchlo,2" },
277 { 18, 3, "c0_watchlo,3" },
278 { 18, 4, "c0_watchlo,4" },
279 { 18, 5, "c0_watchlo,5" },
280 { 18, 6, "c0_watchlo,6" },
281 { 18, 7, "c0_watchlo,7" },
282 { 19, 1, "c0_watchhi,1" },
283 { 19, 2, "c0_watchhi,2" },
284 { 19, 3, "c0_watchhi,3" },
285 { 19, 4, "c0_watchhi,4" },
286 { 19, 5, "c0_watchhi,5" },
287 { 19, 6, "c0_watchhi,6" },
288 { 19, 7, "c0_watchhi,7" },
289 { 25, 1, "c0_perfcnt,1" },
290 { 25, 2, "c0_perfcnt,2" },
291 { 25, 3, "c0_perfcnt,3" },
292 { 25, 4, "c0_perfcnt,4" },
293 { 25, 5, "c0_perfcnt,5" },
294 { 25, 6, "c0_perfcnt,6" },
295 { 25, 7, "c0_perfcnt,7" },
296 { 27, 1, "c0_cacheerr,1" },
297 { 27, 2, "c0_cacheerr,2" },
298 { 27, 3, "c0_cacheerr,3" },
299 { 28, 1, "c0_datalo" },
300 { 29, 1, "c0_datahi" }
301 };
302
303 static const char * const mips_cp0_names_mips3264r2[32] =
304 {
305 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
306 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
307 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
308 "c0_status", "c0_cause", "c0_epc", "c0_prid",
309 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
310 "c0_xcontext", "$21", "$22", "c0_debug",
311 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
312 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
313 };
314
315 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
316 {
317 { 4, 1, "c0_contextconfig" },
318 { 0, 1, "c0_mvpcontrol" },
319 { 0, 2, "c0_mvpconf0" },
320 { 0, 3, "c0_mvpconf1" },
321 { 1, 1, "c0_vpecontrol" },
322 { 1, 2, "c0_vpeconf0" },
323 { 1, 3, "c0_vpeconf1" },
324 { 1, 4, "c0_yqmask" },
325 { 1, 5, "c0_vpeschedule" },
326 { 1, 6, "c0_vpeschefback" },
327 { 2, 1, "c0_tcstatus" },
328 { 2, 2, "c0_tcbind" },
329 { 2, 3, "c0_tcrestart" },
330 { 2, 4, "c0_tchalt" },
331 { 2, 5, "c0_tccontext" },
332 { 2, 6, "c0_tcschedule" },
333 { 2, 7, "c0_tcschefback" },
334 { 5, 1, "c0_pagegrain" },
335 { 6, 1, "c0_srsconf0" },
336 { 6, 2, "c0_srsconf1" },
337 { 6, 3, "c0_srsconf2" },
338 { 6, 4, "c0_srsconf3" },
339 { 6, 5, "c0_srsconf4" },
340 { 12, 1, "c0_intctl" },
341 { 12, 2, "c0_srsctl" },
342 { 12, 3, "c0_srsmap" },
343 { 15, 1, "c0_ebase" },
344 { 16, 1, "c0_config1" },
345 { 16, 2, "c0_config2" },
346 { 16, 3, "c0_config3" },
347 { 18, 1, "c0_watchlo,1" },
348 { 18, 2, "c0_watchlo,2" },
349 { 18, 3, "c0_watchlo,3" },
350 { 18, 4, "c0_watchlo,4" },
351 { 18, 5, "c0_watchlo,5" },
352 { 18, 6, "c0_watchlo,6" },
353 { 18, 7, "c0_watchlo,7" },
354 { 19, 1, "c0_watchhi,1" },
355 { 19, 2, "c0_watchhi,2" },
356 { 19, 3, "c0_watchhi,3" },
357 { 19, 4, "c0_watchhi,4" },
358 { 19, 5, "c0_watchhi,5" },
359 { 19, 6, "c0_watchhi,6" },
360 { 19, 7, "c0_watchhi,7" },
361 { 23, 1, "c0_tracecontrol" },
362 { 23, 2, "c0_tracecontrol2" },
363 { 23, 3, "c0_usertracedata" },
364 { 23, 4, "c0_tracebpc" },
365 { 25, 1, "c0_perfcnt,1" },
366 { 25, 2, "c0_perfcnt,2" },
367 { 25, 3, "c0_perfcnt,3" },
368 { 25, 4, "c0_perfcnt,4" },
369 { 25, 5, "c0_perfcnt,5" },
370 { 25, 6, "c0_perfcnt,6" },
371 { 25, 7, "c0_perfcnt,7" },
372 { 27, 1, "c0_cacheerr,1" },
373 { 27, 2, "c0_cacheerr,2" },
374 { 27, 3, "c0_cacheerr,3" },
375 { 28, 1, "c0_datalo" },
376 { 28, 2, "c0_taglo1" },
377 { 28, 3, "c0_datalo1" },
378 { 28, 4, "c0_taglo2" },
379 { 28, 5, "c0_datalo2" },
380 { 28, 6, "c0_taglo3" },
381 { 28, 7, "c0_datalo3" },
382 { 29, 1, "c0_datahi" },
383 { 29, 2, "c0_taghi1" },
384 { 29, 3, "c0_datahi1" },
385 { 29, 4, "c0_taghi2" },
386 { 29, 5, "c0_datahi2" },
387 { 29, 6, "c0_taghi3" },
388 { 29, 7, "c0_datahi3" },
389 };
390
391 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
392 static const char * const mips_cp0_names_sb1[32] =
393 {
394 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
395 "c0_context", "c0_pagemask", "c0_wired", "$7",
396 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
397 "c0_status", "c0_cause", "c0_epc", "c0_prid",
398 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
399 "c0_xcontext", "$21", "$22", "c0_debug",
400 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
401 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
402 };
403
404 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
405 {
406 { 16, 1, "c0_config1" },
407 { 18, 1, "c0_watchlo,1" },
408 { 19, 1, "c0_watchhi,1" },
409 { 22, 0, "c0_perftrace" },
410 { 23, 3, "c0_edebug" },
411 { 25, 1, "c0_perfcnt,1" },
412 { 25, 2, "c0_perfcnt,2" },
413 { 25, 3, "c0_perfcnt,3" },
414 { 25, 4, "c0_perfcnt,4" },
415 { 25, 5, "c0_perfcnt,5" },
416 { 25, 6, "c0_perfcnt,6" },
417 { 25, 7, "c0_perfcnt,7" },
418 { 26, 1, "c0_buserr_pa" },
419 { 27, 1, "c0_cacheerr_d" },
420 { 27, 3, "c0_cacheerr_d_pa" },
421 { 28, 1, "c0_datalo_i" },
422 { 28, 2, "c0_taglo_d" },
423 { 28, 3, "c0_datalo_d" },
424 { 29, 1, "c0_datahi_i" },
425 { 29, 2, "c0_taghi_d" },
426 { 29, 3, "c0_datahi_d" },
427 };
428
429 /* Xlr cop0 register names. */
430 static const char * const mips_cp0_names_xlr[32] = {
431 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
432 "c0_context", "c0_pagemask", "c0_wired", "$7",
433 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
434 "c0_status", "c0_cause", "c0_epc", "c0_prid",
435 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
436 "c0_xcontext", "$21", "$22", "c0_debug",
437 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
438 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
439 };
440
441 /* XLR's CP0 Select Registers. */
442
443 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
444 { 9, 6, "c0_extintreq" },
445 { 9, 7, "c0_extintmask" },
446 { 15, 1, "c0_ebase" },
447 { 16, 1, "c0_config1" },
448 { 16, 2, "c0_config2" },
449 { 16, 3, "c0_config3" },
450 { 16, 7, "c0_procid2" },
451 { 18, 1, "c0_watchlo,1" },
452 { 18, 2, "c0_watchlo,2" },
453 { 18, 3, "c0_watchlo,3" },
454 { 18, 4, "c0_watchlo,4" },
455 { 18, 5, "c0_watchlo,5" },
456 { 18, 6, "c0_watchlo,6" },
457 { 18, 7, "c0_watchlo,7" },
458 { 19, 1, "c0_watchhi,1" },
459 { 19, 2, "c0_watchhi,2" },
460 { 19, 3, "c0_watchhi,3" },
461 { 19, 4, "c0_watchhi,4" },
462 { 19, 5, "c0_watchhi,5" },
463 { 19, 6, "c0_watchhi,6" },
464 { 19, 7, "c0_watchhi,7" },
465 { 25, 1, "c0_perfcnt,1" },
466 { 25, 2, "c0_perfcnt,2" },
467 { 25, 3, "c0_perfcnt,3" },
468 { 25, 4, "c0_perfcnt,4" },
469 { 25, 5, "c0_perfcnt,5" },
470 { 25, 6, "c0_perfcnt,6" },
471 { 25, 7, "c0_perfcnt,7" },
472 { 27, 1, "c0_cacheerr,1" },
473 { 27, 2, "c0_cacheerr,2" },
474 { 27, 3, "c0_cacheerr,3" },
475 { 28, 1, "c0_datalo" },
476 { 29, 1, "c0_datahi" }
477 };
478
479 static const char * const mips_hwr_names_numeric[32] =
480 {
481 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
482 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
483 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
484 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
485 };
486
487 static const char * const mips_hwr_names_mips3264r2[32] =
488 {
489 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
490 "$4", "$5", "$6", "$7",
491 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
492 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
493 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
494 };
495
496 struct mips_abi_choice
497 {
498 const char * name;
499 const char * const *gpr_names;
500 const char * const *fpr_names;
501 };
502
503 struct mips_abi_choice mips_abi_choices[] =
504 {
505 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
506 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
507 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
508 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
509 };
510
511 struct mips_arch_choice
512 {
513 const char *name;
514 int bfd_mach_valid;
515 unsigned long bfd_mach;
516 int processor;
517 int isa;
518 int ase;
519 const char * const *cp0_names;
520 const struct mips_cp0sel_name *cp0sel_names;
521 unsigned int cp0sel_names_len;
522 const char * const *hwr_names;
523 };
524
525 const struct mips_arch_choice mips_arch_choices[] =
526 {
527 { "numeric", 0, 0, 0, 0, 0,
528 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
529
530 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
531 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
532 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
533 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
534 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
535 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
536 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
537 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
538 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
539 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
540 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
541 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
542 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
543 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
544 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
545 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
546 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
547 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
548 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
549 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
550 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
551 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
552 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
553 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
554 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
555 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
556 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
557 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
558 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
559 mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
560 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
561 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
562 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
563 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
564 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
565 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
566 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
567 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
568 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
569 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
570 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
571 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
572 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
573 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
574 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
575 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
576 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
577 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
578
579 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
580 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
581 _MIPS32 Architecture For Programmers Volume I: Introduction to the
582 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
583 page 1. */
584 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
585 ISA_MIPS32, ASE_SMARTMIPS,
586 mips_cp0_names_mips3264,
587 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
588 mips_hwr_names_numeric },
589
590 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
591 ISA_MIPS32R2,
592 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
593 | ASE_MT | ASE_MCU | ASE_VIRT),
594 mips_cp0_names_mips3264r2,
595 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
596 mips_hwr_names_mips3264r2 },
597
598 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
599 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
600 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
601 mips_cp0_names_mips3264,
602 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
603 mips_hwr_names_numeric },
604
605 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
606 ISA_MIPS64R2,
607 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
608 | ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64),
609 mips_cp0_names_mips3264r2,
610 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
611 mips_hwr_names_mips3264r2 },
612
613 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
614 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
615 mips_cp0_names_sb1,
616 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
617 mips_hwr_names_numeric },
618
619 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
620 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
621 NULL, 0, mips_hwr_names_numeric },
622
623 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
624 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
625 NULL, 0, mips_hwr_names_numeric },
626
627 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
628 ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
629 NULL, 0, mips_hwr_names_numeric },
630
631 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
632 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
633 mips_hwr_names_numeric },
634
635 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
636 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
637 NULL, 0, mips_hwr_names_numeric },
638
639 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
640 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
641 NULL, 0, mips_hwr_names_numeric },
642
643 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
644 ISA_MIPS64 | INSN_XLR, 0,
645 mips_cp0_names_xlr,
646 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
647 mips_hwr_names_numeric },
648
649 /* XLP is mostly like XLR, with the prominent exception it is being
650 MIPS64R2. */
651 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
652 ISA_MIPS64R2 | INSN_XLR, 0,
653 mips_cp0_names_xlr,
654 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
655 mips_hwr_names_numeric },
656
657 /* This entry, mips16, is here only for ISA/processor selection; do
658 not print its name. */
659 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
660 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
661 };
662
663 /* ISA and processor type to disassemble for, and register names to use.
664 set_default_mips_dis_options and parse_mips_dis_options fill in these
665 values. */
666 static int mips_processor;
667 static int mips_isa;
668 static int mips_ase;
669 static int micromips_ase;
670 static const char * const *mips_gpr_names;
671 static const char * const *mips_fpr_names;
672 static const char * const *mips_cp0_names;
673 static const struct mips_cp0sel_name *mips_cp0sel_names;
674 static int mips_cp0sel_names_len;
675 static const char * const *mips_hwr_names;
676
677 /* Other options */
678 static int no_aliases; /* If set disassemble as most general inst. */
679 \f
680 static const struct mips_abi_choice *
681 choose_abi_by_name (const char *name, unsigned int namelen)
682 {
683 const struct mips_abi_choice *c;
684 unsigned int i;
685
686 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
687 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
688 && strlen (mips_abi_choices[i].name) == namelen)
689 c = &mips_abi_choices[i];
690
691 return c;
692 }
693
694 static const struct mips_arch_choice *
695 choose_arch_by_name (const char *name, unsigned int namelen)
696 {
697 const struct mips_arch_choice *c = NULL;
698 unsigned int i;
699
700 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
701 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
702 && strlen (mips_arch_choices[i].name) == namelen)
703 c = &mips_arch_choices[i];
704
705 return c;
706 }
707
708 static const struct mips_arch_choice *
709 choose_arch_by_number (unsigned long mach)
710 {
711 static unsigned long hint_bfd_mach;
712 static const struct mips_arch_choice *hint_arch_choice;
713 const struct mips_arch_choice *c;
714 unsigned int i;
715
716 /* We optimize this because even if the user specifies no
717 flags, this will be done for every instruction! */
718 if (hint_bfd_mach == mach
719 && hint_arch_choice != NULL
720 && hint_arch_choice->bfd_mach == hint_bfd_mach)
721 return hint_arch_choice;
722
723 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
724 {
725 if (mips_arch_choices[i].bfd_mach_valid
726 && mips_arch_choices[i].bfd_mach == mach)
727 {
728 c = &mips_arch_choices[i];
729 hint_bfd_mach = mach;
730 hint_arch_choice = c;
731 }
732 }
733 return c;
734 }
735
736 /* Check if the object uses NewABI conventions. */
737
738 static int
739 is_newabi (Elf_Internal_Ehdr *header)
740 {
741 /* There are no old-style ABIs which use 64-bit ELF. */
742 if (header->e_ident[EI_CLASS] == ELFCLASS64)
743 return 1;
744
745 /* If a 32-bit ELF file, n32 is a new-style ABI. */
746 if ((header->e_flags & EF_MIPS_ABI2) != 0)
747 return 1;
748
749 return 0;
750 }
751
752 /* Check if the object has microMIPS ASE code. */
753
754 static int
755 is_micromips (Elf_Internal_Ehdr *header)
756 {
757 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
758 return 1;
759
760 return 0;
761 }
762
763 static void
764 set_default_mips_dis_options (struct disassemble_info *info)
765 {
766 const struct mips_arch_choice *chosen_arch;
767
768 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
769 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
770 CP0 register, and HWR names. */
771 mips_isa = ISA_MIPS3;
772 mips_processor = CPU_R3000;
773 micromips_ase = 0;
774 mips_ase = 0;
775 mips_gpr_names = mips_gpr_names_oldabi;
776 mips_fpr_names = mips_fpr_names_numeric;
777 mips_cp0_names = mips_cp0_names_numeric;
778 mips_cp0sel_names = NULL;
779 mips_cp0sel_names_len = 0;
780 mips_hwr_names = mips_hwr_names_numeric;
781 no_aliases = 0;
782
783 /* Update settings according to the ELF file header flags. */
784 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
785 {
786 Elf_Internal_Ehdr *header;
787
788 header = elf_elfheader (info->section->owner);
789 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
790 if (is_newabi (header))
791 mips_gpr_names = mips_gpr_names_newabi;
792 /* If a microMIPS binary, then don't use MIPS16 bindings. */
793 micromips_ase = is_micromips (header);
794 }
795
796 /* Set ISA, architecture, and cp0 register names as best we can. */
797 #if ! SYMTAB_AVAILABLE
798 /* This is running out on a target machine, not in a host tool.
799 FIXME: Where does mips_target_info come from? */
800 target_processor = mips_target_info.processor;
801 mips_isa = mips_target_info.isa;
802 mips_ase = mips_target_info.ase;
803 #else
804 chosen_arch = choose_arch_by_number (info->mach);
805 if (chosen_arch != NULL)
806 {
807 mips_processor = chosen_arch->processor;
808 mips_isa = chosen_arch->isa;
809 mips_ase = chosen_arch->ase;
810 mips_cp0_names = chosen_arch->cp0_names;
811 mips_cp0sel_names = chosen_arch->cp0sel_names;
812 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
813 mips_hwr_names = chosen_arch->hwr_names;
814 }
815 #endif
816 }
817
818 static void
819 parse_mips_dis_option (const char *option, unsigned int len)
820 {
821 unsigned int i, optionlen, vallen;
822 const char *val;
823 const struct mips_abi_choice *chosen_abi;
824 const struct mips_arch_choice *chosen_arch;
825
826 /* Try to match options that are simple flags */
827 if (CONST_STRNEQ (option, "no-aliases"))
828 {
829 no_aliases = 1;
830 return;
831 }
832
833 if (CONST_STRNEQ (option, "virt"))
834 {
835 mips_ase |= ASE_VIRT;
836 if (mips_isa & ISA_MIPS64R2)
837 mips_ase |= ASE_VIRT64;
838 return;
839 }
840
841 /* Look for the = that delimits the end of the option name. */
842 for (i = 0; i < len; i++)
843 if (option[i] == '=')
844 break;
845
846 if (i == 0) /* Invalid option: no name before '='. */
847 return;
848 if (i == len) /* Invalid option: no '='. */
849 return;
850 if (i == (len - 1)) /* Invalid option: no value after '='. */
851 return;
852
853 optionlen = i;
854 val = option + (optionlen + 1);
855 vallen = len - (optionlen + 1);
856
857 if (strncmp ("gpr-names", option, optionlen) == 0
858 && strlen ("gpr-names") == optionlen)
859 {
860 chosen_abi = choose_abi_by_name (val, vallen);
861 if (chosen_abi != NULL)
862 mips_gpr_names = chosen_abi->gpr_names;
863 return;
864 }
865
866 if (strncmp ("fpr-names", option, optionlen) == 0
867 && strlen ("fpr-names") == optionlen)
868 {
869 chosen_abi = choose_abi_by_name (val, vallen);
870 if (chosen_abi != NULL)
871 mips_fpr_names = chosen_abi->fpr_names;
872 return;
873 }
874
875 if (strncmp ("cp0-names", option, optionlen) == 0
876 && strlen ("cp0-names") == optionlen)
877 {
878 chosen_arch = choose_arch_by_name (val, vallen);
879 if (chosen_arch != NULL)
880 {
881 mips_cp0_names = chosen_arch->cp0_names;
882 mips_cp0sel_names = chosen_arch->cp0sel_names;
883 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
884 }
885 return;
886 }
887
888 if (strncmp ("hwr-names", option, optionlen) == 0
889 && strlen ("hwr-names") == optionlen)
890 {
891 chosen_arch = choose_arch_by_name (val, vallen);
892 if (chosen_arch != NULL)
893 mips_hwr_names = chosen_arch->hwr_names;
894 return;
895 }
896
897 if (strncmp ("reg-names", option, optionlen) == 0
898 && strlen ("reg-names") == optionlen)
899 {
900 /* We check both ABI and ARCH here unconditionally, so
901 that "numeric" will do the desirable thing: select
902 numeric register names for all registers. Other than
903 that, a given name probably won't match both. */
904 chosen_abi = choose_abi_by_name (val, vallen);
905 if (chosen_abi != NULL)
906 {
907 mips_gpr_names = chosen_abi->gpr_names;
908 mips_fpr_names = chosen_abi->fpr_names;
909 }
910 chosen_arch = choose_arch_by_name (val, vallen);
911 if (chosen_arch != NULL)
912 {
913 mips_cp0_names = chosen_arch->cp0_names;
914 mips_cp0sel_names = chosen_arch->cp0sel_names;
915 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
916 mips_hwr_names = chosen_arch->hwr_names;
917 }
918 return;
919 }
920
921 /* Invalid option. */
922 }
923
924 static void
925 parse_mips_dis_options (const char *options)
926 {
927 const char *option_end;
928
929 if (options == NULL)
930 return;
931
932 while (*options != '\0')
933 {
934 /* Skip empty options. */
935 if (*options == ',')
936 {
937 options++;
938 continue;
939 }
940
941 /* We know that *options is neither NUL or a comma. */
942 option_end = options + 1;
943 while (*option_end != ',' && *option_end != '\0')
944 option_end++;
945
946 parse_mips_dis_option (options, option_end - options);
947
948 /* Go on to the next one. If option_end points to a comma, it
949 will be skipped above. */
950 options = option_end;
951 }
952 }
953
954 static const struct mips_cp0sel_name *
955 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
956 unsigned int len,
957 unsigned int cp0reg,
958 unsigned int sel)
959 {
960 unsigned int i;
961
962 for (i = 0; i < len; i++)
963 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
964 return &names[i];
965 return NULL;
966 }
967 \f
968 /* Print insn arguments for 32/64-bit code. */
969
970 static void
971 print_insn_args (const char *d,
972 int l,
973 bfd_vma pc,
974 struct disassemble_info *info,
975 const struct mips_opcode *opp)
976 {
977 const fprintf_ftype infprintf = info->fprintf_func;
978 unsigned int lsb, msb, msbd, cpreg;
979 void *is = info->stream;
980
981 lsb = 0;
982
983 #define GET_OP(insn, field) \
984 (((insn) >> OP_SH_##field) & OP_MASK_##field)
985 #define GET_OP_S(insn, field) \
986 ((GET_OP (insn, field) ^ ((OP_MASK_##field >> 1) + 1)) \
987 - ((OP_MASK_##field >> 1) + 1))
988 for (; *d != '\0'; d++)
989 {
990 switch (*d)
991 {
992 case ',':
993 case '(':
994 case ')':
995 case '[':
996 case ']':
997 infprintf (is, "%c", *d);
998 break;
999
1000 case '+':
1001 /* Extension character; switch for second char. */
1002 d++;
1003 switch (*d)
1004 {
1005 case '\0':
1006 /* xgettext:c-format */
1007 infprintf (is,
1008 _("# internal error, "
1009 "incomplete extension sequence (+)"));
1010 return;
1011
1012 case 'A':
1013 lsb = GET_OP (l, SHAMT);
1014 infprintf (is, "0x%x", lsb);
1015 break;
1016
1017 case 'B':
1018 msb = GET_OP (l, INSMSB);
1019 infprintf (is, "0x%x", msb - lsb + 1);
1020 break;
1021
1022 case '1':
1023 infprintf (is, "0x%x", GET_OP (l, UDI1));
1024 break;
1025
1026 case '2':
1027 infprintf (is, "0x%x", GET_OP (l, UDI2));
1028 break;
1029
1030 case '3':
1031 infprintf (is, "0x%x", GET_OP (l, UDI3));
1032 break;
1033
1034 case '4':
1035 infprintf (is, "0x%x", GET_OP (l, UDI4));
1036 break;
1037
1038 case 'C':
1039 case 'H':
1040 msbd = GET_OP (l, EXTMSBD);
1041 infprintf (is, "0x%x", msbd + 1);
1042 break;
1043
1044 case 'E':
1045 lsb = GET_OP (l, SHAMT) + 32;
1046 infprintf (is, "0x%x", lsb);
1047 break;
1048
1049 case 'F':
1050 msb = GET_OP (l, INSMSB) + 32;
1051 infprintf (is, "0x%x", msb - lsb + 1);
1052 break;
1053
1054 case 'G':
1055 msbd = GET_OP (l, EXTMSBD) + 32;
1056 infprintf (is, "0x%x", msbd + 1);
1057 break;
1058
1059 case 'J': /* hypcall operand */
1060 infprintf (is, "0x%x", GET_OP (l, CODE10));
1061 break;
1062
1063 case 't': /* Coprocessor 0 reg name */
1064 infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]);
1065 break;
1066
1067 case 'x': /* bbit bit index */
1068 infprintf (is, "0x%x", GET_OP (l, BBITIND));
1069 break;
1070
1071 case 'p': /* cins, cins32, exts and exts32 position */
1072 infprintf (is, "0x%x", GET_OP (l, CINSPOS));
1073 break;
1074
1075 case 's': /* cins and exts length-minus-one */
1076 infprintf (is, "0x%x", GET_OP (l, CINSLM1));
1077 break;
1078
1079 case 'S': /* cins32 and exts32 length-minus-one field */
1080 infprintf (is, "0x%x", GET_OP (l, CINSLM1));
1081 break;
1082
1083 case 'Q': /* seqi/snei immediate field */
1084 infprintf (is, "%d", GET_OP_S (l, SEQI));
1085 break;
1086
1087 case 'a': /* 8-bit signed offset in bit 6 */
1088 infprintf (is, "%d", GET_OP_S (l, OFFSET_A));
1089 break;
1090
1091 case 'b': /* 8-bit signed offset in bit 3 */
1092 infprintf (is, "%d", GET_OP_S (l, OFFSET_B));
1093 break;
1094
1095 case 'c': /* 9-bit signed offset in bit 6 */
1096 /* Left shift 4 bits to print the real offset. */
1097 infprintf (is, "%d", GET_OP_S (l, OFFSET_C) << 4);
1098 break;
1099
1100 case 'z':
1101 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RZ)]);
1102 break;
1103
1104 case 'Z':
1105 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
1106 break;
1107
1108 case 'i': /* JALX destination */
1109 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1110 | (GET_OP (l, TARGET) << 2));
1111 /* For gdb disassembler, force odd address on jalx. */
1112 if (info->flavour == bfd_target_unknown_flavour)
1113 info->target |= 1;
1114 (*info->print_address_func) (info->target, info);
1115 break;
1116
1117 case 'j': /* 9-bit signed offset in bit 7. */
1118 infprintf (is, "%d", GET_OP_S (l, EVAOFFSET));
1119 break;
1120
1121 default:
1122 /* xgettext:c-format */
1123 infprintf (is,
1124 _("# internal error, "
1125 "undefined extension sequence (+%c)"),
1126 *d);
1127 return;
1128 }
1129 break;
1130
1131 case '2':
1132 infprintf (is, "0x%x", GET_OP (l, BP));
1133 break;
1134
1135 case '3':
1136 infprintf (is, "0x%x", GET_OP (l, SA3));
1137 break;
1138
1139 case '4':
1140 infprintf (is, "0x%x", GET_OP (l, SA4));
1141 break;
1142
1143 case '5':
1144 infprintf (is, "0x%x", GET_OP (l, IMM8));
1145 break;
1146
1147 case '6':
1148 infprintf (is, "0x%x", GET_OP (l, RS));
1149 break;
1150
1151 case '7':
1152 infprintf (is, "$ac%d", GET_OP (l, DSPACC));
1153 break;
1154
1155 case '8':
1156 infprintf (is, "0x%x", GET_OP (l, WRDSP));
1157 break;
1158
1159 case '9':
1160 infprintf (is, "$ac%d", GET_OP (l, DSPACC_S));
1161 break;
1162
1163 case '0': /* dsp 6-bit signed immediate in bit 20 */
1164 infprintf (is, "%d", GET_OP_S (l, DSPSFT));
1165 break;
1166
1167 case ':': /* dsp 7-bit signed immediate in bit 19 */
1168 infprintf (is, "%d", GET_OP_S (l, DSPSFT_7));
1169 break;
1170
1171 case '~':
1172 infprintf (is, "%d", GET_OP_S (l, OFFSET12));
1173 break;
1174
1175 case '\\':
1176 infprintf (is, "0x%x", GET_OP (l, 3BITPOS));
1177 break;
1178
1179 case '\'':
1180 infprintf (is, "0x%x", GET_OP (l, RDDSP));
1181 break;
1182
1183 case '@': /* dsp 10-bit signed immediate in bit 16 */
1184 infprintf (is, "%d", GET_OP_S (l, IMM10));
1185 break;
1186
1187 case '!':
1188 infprintf (is, "%d", GET_OP (l, MT_U));
1189 break;
1190
1191 case '$':
1192 infprintf (is, "%d", GET_OP (l, MT_H));
1193 break;
1194
1195 case '*':
1196 infprintf (is, "$ac%d", GET_OP (l, MTACC_T));
1197 break;
1198
1199 case '&':
1200 infprintf (is, "$ac%d", GET_OP (l, MTACC_D));
1201 break;
1202
1203 case 'g':
1204 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1205 infprintf (is, "$%d", GET_OP (l, RD));
1206 break;
1207
1208 case 's':
1209 case 'b':
1210 case 'r':
1211 case 'v':
1212 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RS)]);
1213 break;
1214
1215 case 't':
1216 case 'w':
1217 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
1218 break;
1219
1220 case 'i':
1221 case 'u':
1222 infprintf (is, "0x%x", GET_OP (l, IMMEDIATE));
1223 break;
1224
1225 case 'j': /* Same as i, but sign-extended. */
1226 case 'o':
1227 infprintf (is, "%d", GET_OP_S (l, DELTA));
1228 break;
1229
1230 case 'h':
1231 infprintf (is, "0x%x", GET_OP (l, PREFX));
1232 break;
1233
1234 case 'k':
1235 infprintf (is, "0x%x", GET_OP (l, CACHE));
1236 break;
1237
1238 case 'a':
1239 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1240 | (GET_OP (l, TARGET) << 2));
1241 (*info->print_address_func) (info->target, info);
1242 break;
1243
1244 case 'p':
1245 /* Sign extend the displacement. */
1246 info->target = (GET_OP_S (l, DELTA) << 2) + pc + INSNLEN;
1247 (*info->print_address_func) (info->target, info);
1248 break;
1249
1250 case 'd':
1251 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RD)]);
1252 break;
1253
1254 case 'U':
1255 {
1256 /* First check for both rd and rt being equal. */
1257 unsigned int reg;
1258
1259 reg = GET_OP (l, RD);
1260 if (reg == GET_OP (l, RT))
1261 infprintf (is, "%s", mips_gpr_names[reg]);
1262 else
1263 {
1264 /* If one is zero use the other. */
1265 if (reg == 0)
1266 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
1267 else if (GET_OP (l, RT) == 0)
1268 infprintf (is, "%s", mips_gpr_names[reg]);
1269 else /* Bogus, result depends on processor. */
1270 infprintf (is, "%s or %s",
1271 mips_gpr_names[reg],
1272 mips_gpr_names[GET_OP (l, RT)]);
1273 }
1274 }
1275 break;
1276
1277 case 'z':
1278 infprintf (is, "%s", mips_gpr_names[0]);
1279 break;
1280
1281 case '<':
1282 case '1':
1283 infprintf (is, "0x%x", GET_OP (l, SHAMT));
1284 break;
1285
1286 case 'c':
1287 infprintf (is, "0x%x", GET_OP (l, CODE));
1288 break;
1289
1290 case 'q':
1291 infprintf (is, "0x%x", GET_OP (l, CODE2));
1292 break;
1293
1294 case 'C':
1295 infprintf (is, "0x%x", GET_OP (l, COPZ));
1296 break;
1297
1298 case 'B':
1299 infprintf (is, "0x%x", GET_OP (l, CODE20));
1300 break;
1301
1302 case 'J':
1303 infprintf (is, "0x%x", GET_OP (l, CODE19));
1304 break;
1305
1306 case 'S':
1307 case 'V':
1308 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FS)]);
1309 break;
1310
1311 case 'T':
1312 case 'W':
1313 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FT)]);
1314 break;
1315
1316 case 'D':
1317 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FD)]);
1318 break;
1319
1320 case 'R':
1321 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FR)]);
1322 break;
1323
1324 case 'E':
1325 cpreg = GET_OP (l, RT);
1326 goto copro;
1327
1328 case 'G':
1329 cpreg = GET_OP (l, RD);
1330 copro:
1331 /* Coprocessor register for mtcN instructions, et al. Note
1332 that FPU (cp1) instructions disassemble this field using
1333 'S' format. Therefore, we only need to worry about cp0,
1334 cp2, and cp3. */
1335 if (opp->name[strlen (opp->name) - 1] == '0')
1336 {
1337 if (d[1] == ',' && d[2] == 'H')
1338 {
1339 const struct mips_cp0sel_name *n;
1340 unsigned int sel;
1341
1342 sel = GET_OP (l, SEL);
1343
1344 /* CP0 register including 'sel' code for mtcN (et al.), to be
1345 printed textually if known. If not known, print both
1346 CP0 register name and sel numerically since CP0 register
1347 with sel 0 may have a name unrelated to register being
1348 printed. */
1349 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
1350 mips_cp0sel_names_len,
1351 cpreg, sel);
1352 if (n != NULL)
1353 infprintf (is, "%s", n->name);
1354 else
1355 infprintf (is, "$%d,%d", cpreg, sel);
1356 d += 2;
1357 }
1358 else
1359 infprintf (is, "%s", mips_cp0_names[cpreg]);
1360 }
1361 else
1362 infprintf (is, "$%d", cpreg);
1363 break;
1364
1365 case 'K':
1366 infprintf (is, "%s", mips_hwr_names[GET_OP (l, RD)]);
1367 break;
1368
1369 case 'N':
1370 infprintf (is,
1371 (opp->pinfo & (FP_D | FP_S)) != 0 ? "$fcc%d" : "$cc%d",
1372 GET_OP (l, BCC));
1373 break;
1374
1375 case 'M':
1376 infprintf (is, "$fcc%d", GET_OP (l, CCC));
1377 break;
1378
1379 case 'P':
1380 infprintf (is, "%d", GET_OP (l, PERFREG));
1381 break;
1382
1383 case 'e':
1384 infprintf (is, "%d", GET_OP (l, VECBYTE));
1385 break;
1386
1387 case '%':
1388 infprintf (is, "%d", GET_OP (l, VECALIGN));
1389 break;
1390
1391 case 'H':
1392 infprintf (is, "%d", GET_OP (l, SEL));
1393 break;
1394
1395 case 'O':
1396 infprintf (is, "%d", GET_OP (l, ALN));
1397 break;
1398
1399 case 'Q':
1400 {
1401 unsigned int vsel = GET_OP (l, VSEL);
1402
1403 if ((vsel & 0x10) == 0)
1404 {
1405 int fmt;
1406
1407 vsel &= 0x0f;
1408 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1409 if ((vsel & 1) == 0)
1410 break;
1411 infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1);
1412 }
1413 else if ((vsel & 0x08) == 0)
1414 {
1415 infprintf (is, "$v%d", GET_OP (l, FT));
1416 }
1417 else
1418 {
1419 infprintf (is, "0x%x", GET_OP (l, FT));
1420 }
1421 }
1422 break;
1423
1424 case 'X':
1425 infprintf (is, "$v%d", GET_OP (l, FD));
1426 break;
1427
1428 case 'Y':
1429 infprintf (is, "$v%d", GET_OP (l, FS));
1430 break;
1431
1432 case 'Z':
1433 infprintf (is, "$v%d", GET_OP (l, FT));
1434 break;
1435
1436 default:
1437 /* xgettext:c-format */
1438 infprintf (is, _("# internal error, undefined modifier (%c)"), *d);
1439 return;
1440 }
1441 }
1442 }
1443 \f
1444 /* Print the mips instruction at address MEMADDR in debugged memory,
1445 on using INFO. Returns length of the instruction, in bytes, which is
1446 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1447 this is little-endian code. */
1448
1449 static int
1450 print_insn_mips (bfd_vma memaddr,
1451 int word,
1452 struct disassemble_info *info)
1453 {
1454 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1455 const fprintf_ftype infprintf = info->fprintf_func;
1456 const struct mips_opcode *op;
1457 static bfd_boolean init = 0;
1458 void *is = info->stream;
1459
1460 /* Build a hash table to shorten the search time. */
1461 if (! init)
1462 {
1463 unsigned int i;
1464
1465 for (i = 0; i <= OP_MASK_OP; i++)
1466 {
1467 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1468 {
1469 if (op->pinfo == INSN_MACRO
1470 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1471 continue;
1472 if (i == GET_OP (op->match, OP))
1473 {
1474 mips_hash[i] = op;
1475 break;
1476 }
1477 }
1478 }
1479
1480 init = 1;
1481 }
1482
1483 info->bytes_per_chunk = INSNLEN;
1484 info->display_endian = info->endian;
1485 info->insn_info_valid = 1;
1486 info->branch_delay_insns = 0;
1487 info->data_size = 0;
1488 info->insn_type = dis_nonbranch;
1489 info->target = 0;
1490 info->target2 = 0;
1491
1492 op = mips_hash[GET_OP (word, OP)];
1493 if (op != NULL)
1494 {
1495 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1496 {
1497 if (op->pinfo != INSN_MACRO
1498 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1499 && (word & op->mask) == op->match)
1500 {
1501 const char *d;
1502
1503 /* We always allow to disassemble the jalx instruction. */
1504 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
1505 && strcmp (op->name, "jalx"))
1506 continue;
1507
1508 /* Figure out instruction type and branch delay information. */
1509 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1510 {
1511 if ((op->pinfo & (INSN_WRITE_GPR_31
1512 | INSN_WRITE_GPR_D)) != 0)
1513 info->insn_type = dis_jsr;
1514 else
1515 info->insn_type = dis_branch;
1516 info->branch_delay_insns = 1;
1517 }
1518 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1519 | INSN_COND_BRANCH_LIKELY)) != 0)
1520 {
1521 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1522 info->insn_type = dis_condjsr;
1523 else
1524 info->insn_type = dis_condbranch;
1525 info->branch_delay_insns = 1;
1526 }
1527 else if ((op->pinfo & (INSN_STORE_MEMORY
1528 | INSN_LOAD_MEMORY_DELAY)) != 0)
1529 info->insn_type = dis_dref;
1530
1531 infprintf (is, "%s", op->name);
1532
1533 d = op->args;
1534 if (d != NULL && *d != '\0')
1535 {
1536 infprintf (is, "\t");
1537 print_insn_args (d, word, memaddr, info, op);
1538 }
1539
1540 return INSNLEN;
1541 }
1542 }
1543 }
1544 #undef GET_OP_S
1545 #undef GET_OP
1546
1547 /* Handle undefined instructions. */
1548 info->insn_type = dis_noninsn;
1549 infprintf (is, "0x%x", word);
1550 return INSNLEN;
1551 }
1552 \f
1553 /* Disassemble an operand for a mips16 instruction. */
1554
1555 static void
1556 print_mips16_insn_arg (char type,
1557 const struct mips_opcode *op,
1558 int l,
1559 bfd_boolean use_extend,
1560 int extend,
1561 bfd_vma memaddr,
1562 struct disassemble_info *info)
1563 {
1564 const fprintf_ftype infprintf = info->fprintf_func;
1565 void *is = info->stream;
1566
1567 #define GET_OP(insn, field) \
1568 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
1569 #define GET_OP_S(insn, field) \
1570 ((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \
1571 - ((MIPS16OP_MASK_##field >> 1) + 1))
1572 switch (type)
1573 {
1574 case ',':
1575 case '(':
1576 case ')':
1577 infprintf (is, "%c", type);
1578 break;
1579
1580 case 'y':
1581 case 'w':
1582 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY)));
1583 break;
1584
1585 case 'x':
1586 case 'v':
1587 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX)));
1588 break;
1589
1590 case 'z':
1591 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ)));
1592 break;
1593
1594 case 'Z':
1595 infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z)));
1596 break;
1597
1598 case '0':
1599 infprintf (is, "%s", mips_gpr_names[0]);
1600 break;
1601
1602 case 'S':
1603 infprintf (is, "%s", mips_gpr_names[29]);
1604 break;
1605
1606 case 'P':
1607 infprintf (is, "$pc");
1608 break;
1609
1610 case 'R':
1611 infprintf (is, "%s", mips_gpr_names[31]);
1612 break;
1613
1614 case 'X':
1615 infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]);
1616 break;
1617
1618 case 'Y':
1619 infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1620 break;
1621
1622 case '<':
1623 case '>':
1624 case '[':
1625 case ']':
1626 case '4':
1627 case '5':
1628 case 'H':
1629 case 'W':
1630 case 'D':
1631 case 'j':
1632 case '6':
1633 case '8':
1634 case 'V':
1635 case 'C':
1636 case 'U':
1637 case 'k':
1638 case 'K':
1639 case 'p':
1640 case 'q':
1641 case 'A':
1642 case 'B':
1643 case 'E':
1644 {
1645 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1646
1647 shift = 0;
1648 signedp = 0;
1649 extbits = 16;
1650 pcrel = 0;
1651 extu = 0;
1652 branch = 0;
1653 switch (type)
1654 {
1655 case '<':
1656 nbits = 3;
1657 immed = GET_OP (l, RZ);
1658 extbits = 5;
1659 extu = 1;
1660 break;
1661 case '>':
1662 nbits = 3;
1663 immed = GET_OP (l, RX);
1664 extbits = 5;
1665 extu = 1;
1666 break;
1667 case '[':
1668 nbits = 3;
1669 immed = GET_OP (l, RZ);
1670 extbits = 6;
1671 extu = 1;
1672 break;
1673 case ']':
1674 nbits = 3;
1675 immed = GET_OP (l, RX);
1676 extbits = 6;
1677 extu = 1;
1678 break;
1679 case '4':
1680 nbits = 4;
1681 immed = GET_OP (l, IMM4);
1682 signedp = 1;
1683 extbits = 15;
1684 break;
1685 case '5':
1686 nbits = 5;
1687 immed = GET_OP (l, IMM5);
1688 info->insn_type = dis_dref;
1689 info->data_size = 1;
1690 break;
1691 case 'H':
1692 nbits = 5;
1693 shift = 1;
1694 immed = GET_OP (l, IMM5);
1695 info->insn_type = dis_dref;
1696 info->data_size = 2;
1697 break;
1698 case 'W':
1699 nbits = 5;
1700 shift = 2;
1701 immed = GET_OP (l, IMM5);
1702 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1703 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1704 {
1705 info->insn_type = dis_dref;
1706 info->data_size = 4;
1707 }
1708 break;
1709 case 'D':
1710 nbits = 5;
1711 shift = 3;
1712 immed = GET_OP (l, IMM5);
1713 info->insn_type = dis_dref;
1714 info->data_size = 8;
1715 break;
1716 case 'j':
1717 nbits = 5;
1718 immed = GET_OP (l, IMM5);
1719 signedp = 1;
1720 break;
1721 case '6':
1722 nbits = 6;
1723 immed = GET_OP (l, IMM6);
1724 break;
1725 case '8':
1726 nbits = 8;
1727 immed = GET_OP (l, IMM8);
1728 break;
1729 case 'V':
1730 nbits = 8;
1731 shift = 2;
1732 immed = GET_OP (l, IMM8);
1733 /* FIXME: This might be lw, or it might be addiu to $sp or
1734 $pc. We assume it's load. */
1735 info->insn_type = dis_dref;
1736 info->data_size = 4;
1737 break;
1738 case 'C':
1739 nbits = 8;
1740 shift = 3;
1741 immed = GET_OP (l, IMM8);
1742 info->insn_type = dis_dref;
1743 info->data_size = 8;
1744 break;
1745 case 'U':
1746 nbits = 8;
1747 immed = GET_OP (l, IMM8);
1748 extu = 1;
1749 break;
1750 case 'k':
1751 nbits = 8;
1752 immed = GET_OP (l, IMM8);
1753 signedp = 1;
1754 break;
1755 case 'K':
1756 nbits = 8;
1757 shift = 3;
1758 immed = GET_OP (l, IMM8);
1759 signedp = 1;
1760 break;
1761 case 'p':
1762 nbits = 8;
1763 immed = GET_OP (l, IMM8);
1764 signedp = 1;
1765 pcrel = 1;
1766 branch = 1;
1767 break;
1768 case 'q':
1769 nbits = 11;
1770 immed = GET_OP (l, IMM11);
1771 signedp = 1;
1772 pcrel = 1;
1773 branch = 1;
1774 break;
1775 case 'A':
1776 nbits = 8;
1777 shift = 2;
1778 immed = GET_OP (l, IMM8);
1779 pcrel = 1;
1780 /* FIXME: This can be lw or la. We assume it is lw. */
1781 info->insn_type = dis_dref;
1782 info->data_size = 4;
1783 break;
1784 case 'B':
1785 nbits = 5;
1786 shift = 3;
1787 immed = GET_OP (l, IMM5);
1788 pcrel = 1;
1789 info->insn_type = dis_dref;
1790 info->data_size = 8;
1791 break;
1792 case 'E':
1793 nbits = 5;
1794 shift = 2;
1795 immed = GET_OP (l, IMM5);
1796 pcrel = 1;
1797 break;
1798 default:
1799 abort ();
1800 }
1801
1802 if (! use_extend)
1803 {
1804 if (signedp && immed >= (1 << (nbits - 1)))
1805 immed -= 1 << nbits;
1806 immed <<= shift;
1807 if ((type == '<' || type == '>' || type == '[' || type == ']')
1808 && immed == 0)
1809 immed = 8;
1810 }
1811 else
1812 {
1813 if (extbits == 16)
1814 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1815 else if (extbits == 15)
1816 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1817 else
1818 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1819 immed &= (1 << extbits) - 1;
1820 if (! extu && immed >= (1 << (extbits - 1)))
1821 immed -= 1 << extbits;
1822 }
1823
1824 if (! pcrel)
1825 infprintf (is, "%d", immed);
1826 else
1827 {
1828 bfd_vma baseaddr;
1829
1830 if (branch)
1831 {
1832 immed *= 2;
1833 baseaddr = memaddr + 2;
1834 }
1835 else if (use_extend)
1836 baseaddr = memaddr - 2;
1837 else
1838 {
1839 int status;
1840 bfd_byte buffer[2];
1841
1842 baseaddr = memaddr;
1843
1844 /* If this instruction is in the delay slot of a jr
1845 instruction, the base address is the address of the
1846 jr instruction. If it is in the delay slot of jalr
1847 instruction, the base address is the address of the
1848 jalr instruction. This test is unreliable: we have
1849 no way of knowing whether the previous word is
1850 instruction or data. */
1851 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1852 info);
1853 if (status == 0
1854 && (((info->endian == BFD_ENDIAN_BIG
1855 ? bfd_getb16 (buffer)
1856 : bfd_getl16 (buffer))
1857 & 0xf800) == 0x1800))
1858 baseaddr = memaddr - 4;
1859 else
1860 {
1861 status = (*info->read_memory_func) (memaddr - 2, buffer,
1862 2, info);
1863 if (status == 0
1864 && (((info->endian == BFD_ENDIAN_BIG
1865 ? bfd_getb16 (buffer)
1866 : bfd_getl16 (buffer))
1867 & 0xf81f) == 0xe800))
1868 baseaddr = memaddr - 2;
1869 }
1870 }
1871 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1872 if (pcrel && branch
1873 && info->flavour == bfd_target_unknown_flavour)
1874 /* For gdb disassembler, maintain odd address. */
1875 info->target |= 1;
1876 (*info->print_address_func) (info->target, info);
1877 }
1878 }
1879 break;
1880
1881 case 'a':
1882 case 'i':
1883 {
1884 if (! use_extend)
1885 extend = 0;
1886 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1887 if (type == 'a' && info->flavour == bfd_target_unknown_flavour)
1888 /* For gdb disassembler, maintain odd address. */
1889 l |= 1;
1890 }
1891 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1892 (*info->print_address_func) (info->target, info);
1893 break;
1894
1895 case 'l':
1896 case 'L':
1897 {
1898 int need_comma, amask, smask;
1899
1900 need_comma = 0;
1901
1902 l = GET_OP (l, IMM6);
1903
1904 amask = (l >> 3) & 7;
1905
1906 if (amask > 0 && amask < 5)
1907 {
1908 infprintf (is, "%s", mips_gpr_names[4]);
1909 if (amask > 1)
1910 infprintf (is, "-%s", mips_gpr_names[amask + 3]);
1911 need_comma = 1;
1912 }
1913
1914 smask = (l >> 1) & 3;
1915 if (smask == 3)
1916 {
1917 infprintf (is, "%s??", need_comma ? "," : "");
1918 need_comma = 1;
1919 }
1920 else if (smask > 0)
1921 {
1922 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]);
1923 if (smask > 1)
1924 infprintf (is, "-%s", mips_gpr_names[smask + 15]);
1925 need_comma = 1;
1926 }
1927
1928 if (l & 1)
1929 {
1930 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]);
1931 need_comma = 1;
1932 }
1933
1934 if (amask == 5 || amask == 6)
1935 {
1936 infprintf (is, "%s$f0", need_comma ? "," : "");
1937 if (amask == 6)
1938 infprintf (is, "-$f1");
1939 }
1940 }
1941 break;
1942
1943 case 'm':
1944 case 'M':
1945 /* MIPS16e save/restore. */
1946 {
1947 int need_comma = 0;
1948 int amask, args, statics;
1949 int nsreg, smask;
1950 int framesz;
1951 int i, j;
1952
1953 l = l & 0x7f;
1954 if (use_extend)
1955 l |= extend << 16;
1956
1957 amask = (l >> 16) & 0xf;
1958 if (amask == MIPS16_ALL_ARGS)
1959 {
1960 args = 4;
1961 statics = 0;
1962 }
1963 else if (amask == MIPS16_ALL_STATICS)
1964 {
1965 args = 0;
1966 statics = 4;
1967 }
1968 else
1969 {
1970 args = amask >> 2;
1971 statics = amask & 3;
1972 }
1973
1974 if (args > 0) {
1975 infprintf (is, "%s", mips_gpr_names[4]);
1976 if (args > 1)
1977 infprintf (is, "-%s", mips_gpr_names[4 + args - 1]);
1978 need_comma = 1;
1979 }
1980
1981 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1982 if (framesz == 0 && !use_extend)
1983 framesz = 128;
1984
1985 infprintf (is, "%s%d", need_comma ? "," : "", framesz);
1986
1987 if (l & 0x40) /* $ra */
1988 infprintf (is, ",%s", mips_gpr_names[31]);
1989
1990 nsreg = (l >> 24) & 0x7;
1991 smask = 0;
1992 if (l & 0x20) /* $s0 */
1993 smask |= 1 << 0;
1994 if (l & 0x10) /* $s1 */
1995 smask |= 1 << 1;
1996 if (nsreg > 0) /* $s2-$s8 */
1997 smask |= ((1 << nsreg) - 1) << 2;
1998
1999 /* Find first set static reg bit. */
2000 for (i = 0; i < 9; i++)
2001 {
2002 if (smask & (1 << i))
2003 {
2004 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
2005 /* Skip over string of set bits. */
2006 for (j = i; smask & (2 << j); j++)
2007 continue;
2008 if (j > i)
2009 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
2010 i = j + 1;
2011 }
2012 }
2013
2014 /* Statics $ax - $a3. */
2015 if (statics == 1)
2016 infprintf (is, ",%s", mips_gpr_names[7]);
2017 else if (statics > 0)
2018 infprintf (is, ",%s-%s",
2019 mips_gpr_names[7 - statics + 1],
2020 mips_gpr_names[7]);
2021 }
2022 break;
2023
2024 default:
2025 /* xgettext:c-format */
2026 infprintf (is,
2027 _("# internal disassembler error, "
2028 "unrecognised modifier (%c)"),
2029 type);
2030 abort ();
2031 }
2032 }
2033
2034
2035 /* Check if the given address is the last word of a MIPS16 PLT entry.
2036 This word is data and depending on the value it may interfere with
2037 disassembly of further PLT entries. We make use of the fact PLT
2038 symbols are marked BSF_SYNTHETIC. */
2039 static bfd_boolean
2040 is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr)
2041 {
2042 if (info->symbols
2043 && info->symbols[0]
2044 && (info->symbols[0]->flags & BSF_SYNTHETIC)
2045 && addr == bfd_asymbol_value (info->symbols[0]) + 12)
2046 return TRUE;
2047
2048 return FALSE;
2049 }
2050
2051 /* Disassemble mips16 instructions. */
2052
2053 static int
2054 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
2055 {
2056 const fprintf_ftype infprintf = info->fprintf_func;
2057 int status;
2058 bfd_byte buffer[4];
2059 int length;
2060 int insn;
2061 bfd_boolean use_extend;
2062 int extend = 0;
2063 const struct mips_opcode *op, *opend;
2064 void *is = info->stream;
2065
2066 info->bytes_per_chunk = 2;
2067 info->display_endian = info->endian;
2068 info->insn_info_valid = 1;
2069 info->branch_delay_insns = 0;
2070 info->data_size = 0;
2071 info->target = 0;
2072 info->target2 = 0;
2073
2074 /* Decode PLT entry's GOT slot address word. */
2075 if (is_mips16_plt_tail (info, memaddr))
2076 {
2077 info->insn_type = dis_noninsn;
2078 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
2079 if (status == 0)
2080 {
2081 unsigned int gotslot;
2082
2083 if (info->endian == BFD_ENDIAN_BIG)
2084 gotslot = bfd_getb32 (buffer);
2085 else
2086 gotslot = bfd_getl32 (buffer);
2087 infprintf (is, ".word\t0x%x", gotslot);
2088
2089 return 4;
2090 }
2091 }
2092 else
2093 {
2094 info->insn_type = dis_nonbranch;
2095 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2096 }
2097 if (status != 0)
2098 {
2099 (*info->memory_error_func) (status, memaddr, info);
2100 return -1;
2101 }
2102
2103 length = 2;
2104
2105 if (info->endian == BFD_ENDIAN_BIG)
2106 insn = bfd_getb16 (buffer);
2107 else
2108 insn = bfd_getl16 (buffer);
2109
2110 /* Handle the extend opcode specially. */
2111 use_extend = FALSE;
2112 if ((insn & 0xf800) == 0xf000)
2113 {
2114 use_extend = TRUE;
2115 extend = insn & 0x7ff;
2116
2117 memaddr += 2;
2118
2119 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2120 if (status != 0)
2121 {
2122 infprintf (is, "extend 0x%x", (unsigned int) extend);
2123 (*info->memory_error_func) (status, memaddr, info);
2124 return -1;
2125 }
2126
2127 if (info->endian == BFD_ENDIAN_BIG)
2128 insn = bfd_getb16 (buffer);
2129 else
2130 insn = bfd_getl16 (buffer);
2131
2132 /* Check for an extend opcode followed by an extend opcode. */
2133 if ((insn & 0xf800) == 0xf000)
2134 {
2135 infprintf (is, "extend 0x%x", (unsigned int) extend);
2136 info->insn_type = dis_noninsn;
2137 return length;
2138 }
2139
2140 length += 2;
2141 }
2142
2143 /* FIXME: Should probably use a hash table on the major opcode here. */
2144
2145 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2146 for (op = mips16_opcodes; op < opend; op++)
2147 {
2148 if (op->pinfo != INSN_MACRO
2149 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2150 && (insn & op->mask) == op->match)
2151 {
2152 const char *s;
2153
2154 if (op->args[0] == 'a' || op->args[0] == 'i')
2155 {
2156 if (use_extend)
2157 {
2158 infprintf (is, "extend 0x%x", (unsigned int) extend);
2159 info->insn_type = dis_noninsn;
2160 return length - 2;
2161 }
2162
2163 use_extend = FALSE;
2164
2165 memaddr += 2;
2166
2167 status = (*info->read_memory_func) (memaddr, buffer, 2,
2168 info);
2169 if (status == 0)
2170 {
2171 use_extend = TRUE;
2172 if (info->endian == BFD_ENDIAN_BIG)
2173 extend = bfd_getb16 (buffer);
2174 else
2175 extend = bfd_getl16 (buffer);
2176 length += 2;
2177 }
2178 }
2179
2180 infprintf (is, "%s", op->name);
2181 if (op->args[0] != '\0')
2182 infprintf (is, "\t");
2183
2184 for (s = op->args; *s != '\0'; s++)
2185 {
2186 if (*s == ','
2187 && s[1] == 'w'
2188 && GET_OP (insn, RX) == GET_OP (insn, RY))
2189 {
2190 /* Skip the register and the comma. */
2191 ++s;
2192 continue;
2193 }
2194 if (*s == ','
2195 && s[1] == 'v'
2196 && GET_OP (insn, RZ) == GET_OP (insn, RX))
2197 {
2198 /* Skip the register and the comma. */
2199 ++s;
2200 continue;
2201 }
2202 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2203 info);
2204 }
2205
2206 /* Figure out branch instruction type and delay slot information. */
2207 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2208 info->branch_delay_insns = 1;
2209 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
2210 | MIPS16_INSN_UNCOND_BRANCH)) != 0)
2211 {
2212 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2213 info->insn_type = dis_jsr;
2214 else
2215 info->insn_type = dis_branch;
2216 }
2217 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
2218 info->insn_type = dis_condbranch;
2219
2220 return length;
2221 }
2222 }
2223 #undef GET_OP_S
2224 #undef GET_OP
2225
2226 if (use_extend)
2227 infprintf (is, "0x%x", extend | 0xf000);
2228 infprintf (is, "0x%x", insn);
2229 info->insn_type = dis_noninsn;
2230
2231 return length;
2232 }
2233
2234 /* Disassemble microMIPS instructions. */
2235
2236 static int
2237 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
2238 {
2239 const fprintf_ftype infprintf = info->fprintf_func;
2240 const struct mips_opcode *op, *opend;
2241 unsigned int lsb, msbd, msb;
2242 void *is = info->stream;
2243 unsigned int regno;
2244 bfd_byte buffer[2];
2245 int lastregno = 0;
2246 int higher;
2247 int length;
2248 int status;
2249 int delta;
2250 int immed;
2251 int insn;
2252
2253 lsb = 0;
2254
2255 info->bytes_per_chunk = 2;
2256 info->display_endian = info->endian;
2257 info->insn_info_valid = 1;
2258 info->branch_delay_insns = 0;
2259 info->data_size = 0;
2260 info->insn_type = dis_nonbranch;
2261 info->target = 0;
2262 info->target2 = 0;
2263
2264 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2265 if (status != 0)
2266 {
2267 (*info->memory_error_func) (status, memaddr, info);
2268 return -1;
2269 }
2270
2271 length = 2;
2272
2273 if (info->endian == BFD_ENDIAN_BIG)
2274 insn = bfd_getb16 (buffer);
2275 else
2276 insn = bfd_getl16 (buffer);
2277
2278 if ((insn & 0xfc00) == 0x7c00)
2279 {
2280 /* This is a 48-bit microMIPS instruction. */
2281 higher = insn;
2282
2283 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2284 if (status != 0)
2285 {
2286 infprintf (is, "micromips 0x%x", higher);
2287 (*info->memory_error_func) (status, memaddr + 2, info);
2288 return -1;
2289 }
2290 if (info->endian == BFD_ENDIAN_BIG)
2291 insn = bfd_getb16 (buffer);
2292 else
2293 insn = bfd_getl16 (buffer);
2294 higher = (higher << 16) | insn;
2295
2296 status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
2297 if (status != 0)
2298 {
2299 infprintf (is, "micromips 0x%x", higher);
2300 (*info->memory_error_func) (status, memaddr + 4, info);
2301 return -1;
2302 }
2303 if (info->endian == BFD_ENDIAN_BIG)
2304 insn = bfd_getb16 (buffer);
2305 else
2306 insn = bfd_getl16 (buffer);
2307 infprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
2308
2309 info->insn_type = dis_noninsn;
2310 return 6;
2311 }
2312 else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
2313 {
2314 /* This is a 32-bit microMIPS instruction. */
2315 higher = insn;
2316
2317 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2318 if (status != 0)
2319 {
2320 infprintf (is, "micromips 0x%x", higher);
2321 (*info->memory_error_func) (status, memaddr + 2, info);
2322 return -1;
2323 }
2324
2325 if (info->endian == BFD_ENDIAN_BIG)
2326 insn = bfd_getb16 (buffer);
2327 else
2328 insn = bfd_getl16 (buffer);
2329
2330 insn = insn | (higher << 16);
2331
2332 length += 2;
2333 }
2334
2335 /* FIXME: Should probably use a hash table on the major opcode here. */
2336
2337 #define GET_OP(insn, field) \
2338 (((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
2339 #define GET_OP_S(insn, field) \
2340 ((GET_OP (insn, field) ^ ((MICROMIPSOP_MASK_##field >> 1) + 1)) \
2341 - ((MICROMIPSOP_MASK_##field >> 1) + 1))
2342 opend = micromips_opcodes + bfd_micromips_num_opcodes;
2343 for (op = micromips_opcodes; op < opend; op++)
2344 {
2345 if (op->pinfo != INSN_MACRO
2346 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2347 && (insn & op->mask) == op->match
2348 && ((length == 2 && (op->mask & 0xffff0000) == 0)
2349 || (length == 4 && (op->mask & 0xffff0000) != 0)))
2350 {
2351 const char *s;
2352
2353 infprintf (is, "%s", op->name);
2354 if (op->args[0] != '\0')
2355 infprintf (is, "\t");
2356
2357 for (s = op->args; *s != '\0'; s++)
2358 {
2359 switch (*s)
2360 {
2361 case ',':
2362 case '(':
2363 case ')':
2364 infprintf (is, "%c", *s);
2365 break;
2366
2367 case '.':
2368 infprintf (is, "%d", GET_OP_S (insn, OFFSET10));
2369 break;
2370
2371 case '1':
2372 infprintf (is, "0x%x", GET_OP (insn, STYPE));
2373 break;
2374
2375 case '2':
2376 infprintf (is, "0x%x", GET_OP (insn, BP));
2377 break;
2378
2379 case '3':
2380 infprintf (is, "0x%x", GET_OP (insn, SA3));
2381 break;
2382
2383 case '4':
2384 infprintf (is, "0x%x", GET_OP (insn, SA4));
2385 break;
2386
2387 case '5':
2388 infprintf (is, "0x%x", GET_OP (insn, IMM8));
2389 break;
2390
2391 case '6':
2392 infprintf (is, "0x%x", GET_OP (insn, RS));
2393 break;
2394
2395 case '7':
2396 infprintf (is, "$ac%d", GET_OP (insn, DSPACC));
2397 break;
2398
2399 case '8':
2400 infprintf (is, "0x%x", GET_OP (insn, WRDSP));
2401 break;
2402
2403 case '0': /* DSP 6-bit signed immediate in bit 16. */
2404 delta = (GET_OP (insn, DSPSFT) ^ 0x20) - 0x20;
2405 infprintf (is, "%d", delta);
2406 break;
2407
2408 case '<':
2409 infprintf (is, "0x%x", GET_OP (insn, SHAMT));
2410 break;
2411
2412 case '\\':
2413 infprintf (is, "0x%x", GET_OP (insn, 3BITPOS));
2414 break;
2415
2416 case '^':
2417 infprintf (is, "0x%x", GET_OP (insn, RD));
2418 break;
2419
2420 case '|':
2421 infprintf (is, "0x%x", GET_OP (insn, TRAP));
2422 break;
2423
2424 case '~':
2425 infprintf (is, "%d", GET_OP_S (insn, OFFSET12));
2426 break;
2427
2428 case 'a':
2429 info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
2430 | (GET_OP (insn, TARGET) << 1));
2431 /* For gdb disassembler, maintain odd address. */
2432 if (info->flavour == bfd_target_unknown_flavour)
2433 info->target |= 1;
2434 (*info->print_address_func) (info->target, info);
2435 break;
2436
2437 case 'b':
2438 case 'r':
2439 case 's':
2440 case 'v':
2441 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]);
2442 break;
2443
2444 case 'c':
2445 infprintf (is, "0x%x", GET_OP (insn, CODE));
2446 break;
2447
2448 case 'd':
2449 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]);
2450 break;
2451
2452 case 'h':
2453 infprintf (is, "0x%x", GET_OP (insn, PREFX));
2454 break;
2455
2456 case 'i':
2457 case 'u':
2458 infprintf (is, "0x%x", GET_OP (insn, IMMEDIATE));
2459 break;
2460
2461 case 'j': /* Same as i, but sign-extended. */
2462 case 'o':
2463 infprintf (is, "%d", GET_OP_S (insn, DELTA));
2464 break;
2465
2466 case 'k':
2467 infprintf (is, "0x%x", GET_OP (insn, CACHE));
2468 break;
2469
2470 case 'n':
2471 {
2472 int s_reg_encode;
2473
2474 immed = GET_OP (insn, RT);
2475 s_reg_encode = immed & 0xf;
2476 if (s_reg_encode != 0)
2477 {
2478 if (s_reg_encode == 1)
2479 infprintf (is, "%s", mips_gpr_names[16]);
2480 else if (s_reg_encode < 9)
2481 infprintf (is, "%s-%s",
2482 mips_gpr_names[16],
2483 mips_gpr_names[15 + s_reg_encode]);
2484 else if (s_reg_encode == 9)
2485 infprintf (is, "%s-%s,%s",
2486 mips_gpr_names[16],
2487 mips_gpr_names[23],
2488 mips_gpr_names[30]);
2489 else
2490 infprintf (is, "UNKNOWN");
2491 }
2492
2493 if (immed & 0x10) /* For ra. */
2494 {
2495 if (s_reg_encode == 0)
2496 infprintf (is, "%s", mips_gpr_names[31]);
2497 else
2498 infprintf (is, ",%s", mips_gpr_names[31]);
2499 }
2500 break;
2501 }
2502
2503 case 'p':
2504 /* Sign-extend the displacement. */
2505 delta = GET_OP_S (insn, DELTA);
2506 info->target = (delta << 1) + memaddr + length;
2507 (*info->print_address_func) (info->target, info);
2508 break;
2509
2510 case 'q':
2511 infprintf (is, "0x%x", GET_OP (insn, CODE2));
2512 break;
2513
2514 case 't':
2515 case 'w':
2516 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]);
2517 break;
2518
2519 case 'y':
2520 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]);
2521 break;
2522
2523 case 'z':
2524 infprintf (is, "%s", mips_gpr_names[0]);
2525 break;
2526
2527 case '@': /* DSP 10-bit signed immediate in bit 16. */
2528 delta = (GET_OP (insn, IMM10) ^ 0x200) - 0x200;
2529 infprintf (is, "%d", delta);
2530 break;
2531
2532 case 'B':
2533 infprintf (is, "0x%x", GET_OP (insn, CODE10));
2534 break;
2535
2536 case 'C':
2537 infprintf (is, "0x%x", GET_OP (insn, COPZ));
2538 break;
2539
2540 case 'D':
2541 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]);
2542 break;
2543
2544 case 'E':
2545 /* Coprocessor register for lwcN instructions, et al.
2546
2547 Note that there is no load/store cp0 instructions, and
2548 that FPU (cp1) instructions disassemble this field using
2549 'T' format. Therefore, until we gain understanding of
2550 cp2 register names, we can simply print the register
2551 numbers. */
2552 infprintf (is, "$%d", GET_OP (insn, RT));
2553 break;
2554
2555 case 'G':
2556 /* Coprocessor register for mtcN instructions, et al. Note
2557 that FPU (cp1) instructions disassemble this field using
2558 'S' format. Therefore, we only need to worry about cp0,
2559 cp2, and cp3. */
2560 if (op->name[strlen (op->name) - 1] == '0')
2561 {
2562 if (s[1] == ',' && s[2] == 'H')
2563 {
2564 const struct mips_cp0sel_name *n;
2565 unsigned int cp0reg, sel;
2566
2567 cp0reg = GET_OP (insn, RS);
2568 sel = GET_OP (insn, SEL);
2569
2570 /* CP0 register including 'sel' code for mtcN
2571 (et al.), to be printed textually if known.
2572 If not known, print both CP0 register name and
2573 sel numerically since CP0 register with sel 0 may
2574 have a name unrelated to register being
2575 printed. */
2576 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
2577 mips_cp0sel_names_len,
2578 cp0reg, sel);
2579 if (n != NULL)
2580 infprintf (is, "%s", n->name);
2581 else
2582 infprintf (is, "$%d,%d", cp0reg, sel);
2583 s += 2;
2584 }
2585 else
2586 infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
2587 }
2588 else
2589 infprintf (is, "$%d", GET_OP (insn, RS));
2590 break;
2591
2592 case 'H':
2593 infprintf (is, "%d", GET_OP (insn, SEL));
2594 break;
2595
2596 case 'K':
2597 infprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]);
2598 break;
2599
2600 case 'M':
2601 infprintf (is, "$fcc%d", GET_OP (insn, CCC));
2602 break;
2603
2604 case 'N':
2605 infprintf (is,
2606 (op->pinfo & (FP_D | FP_S)) != 0
2607 ? "$fcc%d" : "$cc%d",
2608 GET_OP (insn, BCC));
2609 break;
2610
2611 case 'R':
2612 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]);
2613 break;
2614
2615 case 'S':
2616 case 'V':
2617 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]);
2618 break;
2619
2620 case 'T':
2621 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]);
2622 break;
2623
2624 case '+':
2625 /* Extension character; switch for second char. */
2626 s++;
2627 switch (*s)
2628 {
2629 case 'A':
2630 lsb = GET_OP (insn, EXTLSB);
2631 infprintf (is, "0x%x", lsb);
2632 break;
2633
2634 case 'B':
2635 msb = GET_OP (insn, INSMSB);
2636 infprintf (is, "0x%x", msb - lsb + 1);
2637 break;
2638
2639 case 'C':
2640 case 'H':
2641 msbd = GET_OP (insn, EXTMSBD);
2642 infprintf (is, "0x%x", msbd + 1);
2643 break;
2644
2645 case 'E':
2646 lsb = GET_OP (insn, EXTLSB) + 32;
2647 infprintf (is, "0x%x", lsb);
2648 break;
2649
2650 case 'F':
2651 msb = GET_OP (insn, INSMSB) + 32;
2652 infprintf (is, "0x%x", msb - lsb + 1);
2653 break;
2654
2655 case 'G':
2656 msbd = GET_OP (insn, EXTMSBD) + 32;
2657 infprintf (is, "0x%x", msbd + 1);
2658 break;
2659
2660 case 'i':
2661 info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff)
2662 | (GET_OP (insn, TARGET) << 2));
2663 (*info->print_address_func) (info->target, info);
2664 break;
2665
2666 case 'j': /* 9-bit signed offset in bit 0. */
2667 delta = GET_OP_S (insn, EVAOFFSET);
2668 infprintf (is, "%d", delta);
2669 break;
2670
2671 default:
2672 /* xgettext:c-format */
2673 infprintf (is,
2674 _("# internal disassembler error, "
2675 "unrecognized modifier (+%c)"),
2676 *s);
2677 abort ();
2678 }
2679 break;
2680
2681 case 'm':
2682 /* Extension character; switch for second char. */
2683 s++;
2684 switch (*s)
2685 {
2686 case 'a': /* global pointer. */
2687 infprintf (is, "%s", mips_gpr_names[28]);
2688 break;
2689
2690 case 'b':
2691 regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)];
2692 infprintf (is, "%s", mips_gpr_names[regno]);
2693 break;
2694
2695 case 'c':
2696 regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)];
2697 infprintf (is, "%s", mips_gpr_names[regno]);
2698 break;
2699
2700 case 'd':
2701 regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)];
2702 infprintf (is, "%s", mips_gpr_names[regno]);
2703 break;
2704
2705 case 'e':
2706 regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)];
2707 infprintf (is, "%s", mips_gpr_names[regno]);
2708 break;
2709
2710 case 'f':
2711 /* Save lastregno for "mt" to print out later. */
2712 lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)];
2713 infprintf (is, "%s", mips_gpr_names[lastregno]);
2714 break;
2715
2716 case 'g':
2717 regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)];
2718 infprintf (is, "%s", mips_gpr_names[regno]);
2719 break;
2720
2721 case 'h':
2722 regno = micromips_to_32_reg_h_map1[GET_OP (insn, MH)];
2723 infprintf (is, "%s", mips_gpr_names[regno]);
2724 regno = micromips_to_32_reg_h_map2[GET_OP (insn, MH)];
2725 infprintf (is, ",%s", mips_gpr_names[regno]);
2726 break;
2727
2728 case 'j':
2729 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]);
2730 break;
2731
2732 case 'l':
2733 regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)];
2734 infprintf (is, "%s", mips_gpr_names[regno]);
2735 break;
2736
2737 case 'm':
2738 regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)];
2739 infprintf (is, "%s", mips_gpr_names[regno]);
2740 break;
2741
2742 case 'n':
2743 regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)];
2744 infprintf (is, "%s", mips_gpr_names[regno]);
2745 break;
2746
2747 case 'p':
2748 /* Save lastregno for "mt" to print out later. */
2749 lastregno = GET_OP (insn, MP);
2750 infprintf (is, "%s", mips_gpr_names[lastregno]);
2751 break;
2752
2753 case 'q':
2754 regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)];
2755 infprintf (is, "%s", mips_gpr_names[regno]);
2756 break;
2757
2758 case 'r': /* program counter. */
2759 infprintf (is, "$pc");
2760 break;
2761
2762 case 's': /* stack pointer. */
2763 lastregno = 29;
2764 infprintf (is, "%s", mips_gpr_names[29]);
2765 break;
2766
2767 case 't':
2768 infprintf (is, "%s", mips_gpr_names[lastregno]);
2769 break;
2770
2771 case 'z': /* $0. */
2772 infprintf (is, "%s", mips_gpr_names[0]);
2773 break;
2774
2775 case 'A':
2776 /* Sign-extend the immediate. */
2777 immed = GET_OP_S (insn, IMMA) << 2;
2778 infprintf (is, "%d", immed);
2779 break;
2780
2781 case 'B':
2782 immed = micromips_imm_b_map[GET_OP (insn, IMMB)];
2783 infprintf (is, "%d", immed);
2784 break;
2785
2786 case 'C':
2787 immed = micromips_imm_c_map[GET_OP (insn, IMMC)];
2788 infprintf (is, "0x%x", immed);
2789 break;
2790
2791 case 'D':
2792 /* Sign-extend the displacement. */
2793 delta = GET_OP_S (insn, IMMD);
2794 info->target = (delta << 1) + memaddr + length;
2795 (*info->print_address_func) (info->target, info);
2796 break;
2797
2798 case 'E':
2799 /* Sign-extend the displacement. */
2800 delta = GET_OP_S (insn, IMME);
2801 info->target = (delta << 1) + memaddr + length;
2802 (*info->print_address_func) (info->target, info);
2803 break;
2804
2805 case 'F':
2806 immed = GET_OP (insn, IMMF);
2807 infprintf (is, "0x%x", immed);
2808 break;
2809
2810 case 'G':
2811 immed = (insn >> MICROMIPSOP_SH_IMMG) + 1;
2812 immed = (immed & MICROMIPSOP_MASK_IMMG) - 1;
2813 infprintf (is, "%d", immed);
2814 break;
2815
2816 case 'H':
2817 immed = GET_OP (insn, IMMH) << 1;
2818 infprintf (is, "%d", immed);
2819 break;
2820
2821 case 'I':
2822 immed = (insn >> MICROMIPSOP_SH_IMMI) + 1;
2823 immed = (immed & MICROMIPSOP_MASK_IMMI) - 1;
2824 infprintf (is, "%d", immed);
2825 break;
2826
2827 case 'J':
2828 immed = GET_OP (insn, IMMJ) << 2;
2829 infprintf (is, "%d", immed);
2830 break;
2831
2832 case 'L':
2833 immed = GET_OP (insn, IMML);
2834 infprintf (is, "%d", immed);
2835 break;
2836
2837 case 'M':
2838 immed = (insn >> MICROMIPSOP_SH_IMMM) - 1;
2839 immed = (immed & MICROMIPSOP_MASK_IMMM) + 1;
2840 infprintf (is, "%d", immed);
2841 break;
2842
2843 case 'N':
2844 immed = GET_OP (insn, IMMN);
2845 if (immed == 0)
2846 infprintf (is, "%s,%s",
2847 mips_gpr_names[16],
2848 mips_gpr_names[31]);
2849 else
2850 infprintf (is, "%s-%s,%s",
2851 mips_gpr_names[16],
2852 mips_gpr_names[16 + immed],
2853 mips_gpr_names[31]);
2854 break;
2855
2856 case 'O':
2857 immed = GET_OP (insn, IMMO);
2858 infprintf (is, "0x%x", immed);
2859 break;
2860
2861 case 'P':
2862 immed = GET_OP (insn, IMMP) << 2;
2863 infprintf (is, "%d", immed);
2864 break;
2865
2866 case 'Q':
2867 /* Sign-extend the immediate. */
2868 immed = GET_OP_S (insn, IMMQ) << 2;
2869 infprintf (is, "%d", immed);
2870 break;
2871
2872 case 'U':
2873 immed = GET_OP (insn, IMMU) << 2;
2874 infprintf (is, "%d", immed);
2875 break;
2876
2877 case 'W':
2878 immed = GET_OP (insn, IMMW) << 2;
2879 infprintf (is, "%d", immed);
2880 break;
2881
2882 case 'X':
2883 /* Sign-extend the immediate. */
2884 immed = GET_OP_S (insn, IMMX);
2885 infprintf (is, "%d", immed);
2886 break;
2887
2888 case 'Y':
2889 /* Sign-extend the immediate. */
2890 immed = GET_OP_S (insn, IMMY) << 2;
2891 if ((unsigned int) (immed + 8) < 16)
2892 immed ^= 0x400;
2893 infprintf (is, "%d", immed);
2894 break;
2895
2896 default:
2897 /* xgettext:c-format */
2898 infprintf (is,
2899 _("# internal disassembler error, "
2900 "unrecognized modifier (m%c)"),
2901 *s);
2902 abort ();
2903 }
2904 break;
2905
2906 default:
2907 /* xgettext:c-format */
2908 infprintf (is,
2909 _("# internal disassembler error, "
2910 "unrecognized modifier (%c)"),
2911 *s);
2912 abort ();
2913 }
2914 }
2915
2916 /* Figure out instruction type and branch delay information. */
2917 if ((op->pinfo
2918 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
2919 info->branch_delay_insns = 1;
2920 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
2921 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
2922 {
2923 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
2924 info->insn_type = dis_jsr;
2925 else
2926 info->insn_type = dis_branch;
2927 }
2928 else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
2929 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
2930 {
2931 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2932 info->insn_type = dis_condjsr;
2933 else
2934 info->insn_type = dis_condbranch;
2935 }
2936 else if ((op->pinfo
2937 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
2938 info->insn_type = dis_dref;
2939
2940 return length;
2941 }
2942 }
2943 #undef GET_OP_S
2944 #undef GET_OP
2945
2946 infprintf (is, "0x%x", insn);
2947 info->insn_type = dis_noninsn;
2948
2949 return length;
2950 }
2951
2952 /* Return 1 if a symbol associated with the location being disassembled
2953 indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
2954 all the symbols at the address being considered assuming if at least
2955 one of them indicates code compression, then such code has been
2956 genuinely produced here (other symbols could have been derived from
2957 function symbols defined elsewhere or could define data). Otherwise,
2958 return 0. */
2959
2960 static bfd_boolean
2961 is_compressed_mode_p (struct disassemble_info *info)
2962 {
2963 int i;
2964 int l;
2965
2966 for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++)
2967 if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0
2968 && ((!micromips_ase
2969 && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i))
2970 || (micromips_ase
2971 && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i))))
2972 return 1;
2973 else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour
2974 && info->symtab[i]->section == info->section)
2975 {
2976 elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i];
2977 if ((!micromips_ase
2978 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
2979 || (micromips_ase
2980 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
2981 return 1;
2982 }
2983
2984 return 0;
2985 }
2986
2987 /* In an environment where we do not know the symbol type of the
2988 instruction we are forced to assume that the low order bit of the
2989 instructions' address may mark it as a mips16 instruction. If we
2990 are single stepping, or the pc is within the disassembled function,
2991 this works. Otherwise, we need a clue. Sometimes. */
2992
2993 static int
2994 _print_insn_mips (bfd_vma memaddr,
2995 struct disassemble_info *info,
2996 enum bfd_endian endianness)
2997 {
2998 int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
2999 bfd_byte buffer[INSNLEN];
3000 int status;
3001
3002 set_default_mips_dis_options (info);
3003 parse_mips_dis_options (info->disassembler_options);
3004
3005 if (info->mach == bfd_mach_mips16)
3006 return print_insn_mips16 (memaddr, info);
3007 if (info->mach == bfd_mach_mips_micromips)
3008 return print_insn_micromips (memaddr, info);
3009
3010 print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
3011
3012 #if 1
3013 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
3014 /* Only a few tools will work this way. */
3015 if (memaddr & 0x01)
3016 return print_insn_compr (memaddr, info);
3017 #endif
3018
3019 #if SYMTAB_AVAILABLE
3020 if (is_compressed_mode_p (info))
3021 return print_insn_compr (memaddr, info);
3022 #endif
3023
3024 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
3025 if (status == 0)
3026 {
3027 int insn;
3028
3029 if (endianness == BFD_ENDIAN_BIG)
3030 insn = bfd_getb32 (buffer);
3031 else
3032 insn = bfd_getl32 (buffer);
3033
3034 return print_insn_mips (memaddr, insn, info);
3035 }
3036 else
3037 {
3038 (*info->memory_error_func) (status, memaddr, info);
3039 return -1;
3040 }
3041 }
3042
3043 int
3044 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
3045 {
3046 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
3047 }
3048
3049 int
3050 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
3051 {
3052 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
3053 }
3054 \f
3055 void
3056 print_mips_disassembler_options (FILE *stream)
3057 {
3058 unsigned int i;
3059
3060 fprintf (stream, _("\n\
3061 The following MIPS specific disassembler options are supported for use\n\
3062 with the -M switch (multiple options should be separated by commas):\n"));
3063
3064 fprintf (stream, _("\n\
3065 virt Recognize the virtualization ASE instructions.\n"));
3066
3067 fprintf (stream, _("\n\
3068 gpr-names=ABI Print GPR names according to specified ABI.\n\
3069 Default: based on binary being disassembled.\n"));
3070
3071 fprintf (stream, _("\n\
3072 fpr-names=ABI Print FPR names according to specified ABI.\n\
3073 Default: numeric.\n"));
3074
3075 fprintf (stream, _("\n\
3076 cp0-names=ARCH Print CP0 register names according to\n\
3077 specified architecture.\n\
3078 Default: based on binary being disassembled.\n"));
3079
3080 fprintf (stream, _("\n\
3081 hwr-names=ARCH Print HWR names according to specified \n\
3082 architecture.\n\
3083 Default: based on binary being disassembled.\n"));
3084
3085 fprintf (stream, _("\n\
3086 reg-names=ABI Print GPR and FPR names according to\n\
3087 specified ABI.\n"));
3088
3089 fprintf (stream, _("\n\
3090 reg-names=ARCH Print CP0 register and HWR names according to\n\
3091 specified architecture.\n"));
3092
3093 fprintf (stream, _("\n\
3094 For the options above, the following values are supported for \"ABI\":\n\
3095 "));
3096 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
3097 fprintf (stream, " %s", mips_abi_choices[i].name);
3098 fprintf (stream, _("\n"));
3099
3100 fprintf (stream, _("\n\
3101 For the options above, The following values are supported for \"ARCH\":\n\
3102 "));
3103 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
3104 if (*mips_arch_choices[i].name != '\0')
3105 fprintf (stream, " %s", mips_arch_choices[i].name);
3106 fprintf (stream, _("\n"));
3107
3108 fprintf (stream, _("\n"));
3109 }
GDB Binutils - Deliverables
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