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* aoutx.h (NAME): Add case statements for bfd_mach_mips14000,
[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
61
62
63 static const char * const mips_gpr_names_numeric[32] =
64 {
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
69 };
70
71 static const char * const mips_gpr_names_oldabi[32] =
72 {
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
77 };
78
79 static const char * const mips_gpr_names_newabi[32] =
80 {
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
85 };
86
87 static const char * const mips_fpr_names_numeric[32] =
88 {
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
93 };
94
95 static const char * const mips_fpr_names_32[32] =
96 {
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
101 };
102
103 static const char * const mips_fpr_names_n32[32] =
104 {
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
109 };
110
111 static const char * const mips_fpr_names_64[32] =
112 {
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
117 };
118
119 static const char * const mips_cp0_names_numeric[32] =
120 {
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
125 };
126
127 static const char * const mips_cp0_names_r3000[32] =
128 {
129 "c0_index", "c0_random", "c0_entrylo", "$3",
130 "c0_context", "$5", "$6", "$7",
131 "c0_badvaddr", "$9", "c0_entryhi", "$11",
132 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
133 "$16", "$17", "$18", "$19",
134 "$20", "$21", "$22", "$23",
135 "$24", "$25", "$26", "$27",
136 "$28", "$29", "$30", "$31",
137 };
138
139 static const char * const mips_cp0_names_r4000[32] =
140 {
141 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
142 "c0_context", "c0_pagemask", "c0_wired", "$7",
143 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
144 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
145 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
146 "c0_xcontext", "$21", "$22", "$23",
147 "$24", "$25", "c0_ecc", "c0_cacheerr",
148 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
149 };
150
151 static const char * const mips_cp0_names_mips3264[32] =
152 {
153 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
154 "c0_context", "c0_pagemask", "c0_wired", "$7",
155 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
156 "c0_status", "c0_cause", "c0_epc", "c0_prid",
157 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
158 "c0_xcontext", "$21", "$22", "c0_debug",
159 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
160 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
161 };
162
163 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
164 {
165 { 16, 1, "c0_config1" },
166 { 16, 2, "c0_config2" },
167 { 16, 3, "c0_config3" },
168 { 18, 1, "c0_watchlo,1" },
169 { 18, 2, "c0_watchlo,2" },
170 { 18, 3, "c0_watchlo,3" },
171 { 18, 4, "c0_watchlo,4" },
172 { 18, 5, "c0_watchlo,5" },
173 { 18, 6, "c0_watchlo,6" },
174 { 18, 7, "c0_watchlo,7" },
175 { 19, 1, "c0_watchhi,1" },
176 { 19, 2, "c0_watchhi,2" },
177 { 19, 3, "c0_watchhi,3" },
178 { 19, 4, "c0_watchhi,4" },
179 { 19, 5, "c0_watchhi,5" },
180 { 19, 6, "c0_watchhi,6" },
181 { 19, 7, "c0_watchhi,7" },
182 { 25, 1, "c0_perfcnt,1" },
183 { 25, 2, "c0_perfcnt,2" },
184 { 25, 3, "c0_perfcnt,3" },
185 { 25, 4, "c0_perfcnt,4" },
186 { 25, 5, "c0_perfcnt,5" },
187 { 25, 6, "c0_perfcnt,6" },
188 { 25, 7, "c0_perfcnt,7" },
189 { 27, 1, "c0_cacheerr,1" },
190 { 27, 2, "c0_cacheerr,2" },
191 { 27, 3, "c0_cacheerr,3" },
192 { 28, 1, "c0_datalo" },
193 { 29, 1, "c0_datahi" }
194 };
195
196 static const char * const mips_cp0_names_mips3264r2[32] =
197 {
198 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
199 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
200 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
201 "c0_status", "c0_cause", "c0_epc", "c0_prid",
202 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
203 "c0_xcontext", "$21", "$22", "c0_debug",
204 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
205 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
206 };
207
208 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
209 {
210 { 4, 1, "c0_contextconfig" },
211 { 0, 1, "c0_mvpcontrol" },
212 { 0, 2, "c0_mvpconf0" },
213 { 0, 3, "c0_mvpconf1" },
214 { 1, 1, "c0_vpecontrol" },
215 { 1, 2, "c0_vpeconf0" },
216 { 1, 3, "c0_vpeconf1" },
217 { 1, 4, "c0_yqmask" },
218 { 1, 5, "c0_vpeschedule" },
219 { 1, 6, "c0_vpeschefback" },
220 { 2, 1, "c0_tcstatus" },
221 { 2, 2, "c0_tcbind" },
222 { 2, 3, "c0_tcrestart" },
223 { 2, 4, "c0_tchalt" },
224 { 2, 5, "c0_tccontext" },
225 { 2, 6, "c0_tcschedule" },
226 { 2, 7, "c0_tcschefback" },
227 { 5, 1, "c0_pagegrain" },
228 { 6, 1, "c0_srsconf0" },
229 { 6, 2, "c0_srsconf1" },
230 { 6, 3, "c0_srsconf2" },
231 { 6, 4, "c0_srsconf3" },
232 { 6, 5, "c0_srsconf4" },
233 { 12, 1, "c0_intctl" },
234 { 12, 2, "c0_srsctl" },
235 { 12, 3, "c0_srsmap" },
236 { 15, 1, "c0_ebase" },
237 { 16, 1, "c0_config1" },
238 { 16, 2, "c0_config2" },
239 { 16, 3, "c0_config3" },
240 { 18, 1, "c0_watchlo,1" },
241 { 18, 2, "c0_watchlo,2" },
242 { 18, 3, "c0_watchlo,3" },
243 { 18, 4, "c0_watchlo,4" },
244 { 18, 5, "c0_watchlo,5" },
245 { 18, 6, "c0_watchlo,6" },
246 { 18, 7, "c0_watchlo,7" },
247 { 19, 1, "c0_watchhi,1" },
248 { 19, 2, "c0_watchhi,2" },
249 { 19, 3, "c0_watchhi,3" },
250 { 19, 4, "c0_watchhi,4" },
251 { 19, 5, "c0_watchhi,5" },
252 { 19, 6, "c0_watchhi,6" },
253 { 19, 7, "c0_watchhi,7" },
254 { 23, 1, "c0_tracecontrol" },
255 { 23, 2, "c0_tracecontrol2" },
256 { 23, 3, "c0_usertracedata" },
257 { 23, 4, "c0_tracebpc" },
258 { 25, 1, "c0_perfcnt,1" },
259 { 25, 2, "c0_perfcnt,2" },
260 { 25, 3, "c0_perfcnt,3" },
261 { 25, 4, "c0_perfcnt,4" },
262 { 25, 5, "c0_perfcnt,5" },
263 { 25, 6, "c0_perfcnt,6" },
264 { 25, 7, "c0_perfcnt,7" },
265 { 27, 1, "c0_cacheerr,1" },
266 { 27, 2, "c0_cacheerr,2" },
267 { 27, 3, "c0_cacheerr,3" },
268 { 28, 1, "c0_datalo" },
269 { 28, 2, "c0_taglo1" },
270 { 28, 3, "c0_datalo1" },
271 { 28, 4, "c0_taglo2" },
272 { 28, 5, "c0_datalo2" },
273 { 28, 6, "c0_taglo3" },
274 { 28, 7, "c0_datalo3" },
275 { 29, 1, "c0_datahi" },
276 { 29, 2, "c0_taghi1" },
277 { 29, 3, "c0_datahi1" },
278 { 29, 4, "c0_taghi2" },
279 { 29, 5, "c0_datahi2" },
280 { 29, 6, "c0_taghi3" },
281 { 29, 7, "c0_datahi3" },
282 };
283
284 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
285 static const char * const mips_cp0_names_sb1[32] =
286 {
287 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
288 "c0_context", "c0_pagemask", "c0_wired", "$7",
289 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
290 "c0_status", "c0_cause", "c0_epc", "c0_prid",
291 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
292 "c0_xcontext", "$21", "$22", "c0_debug",
293 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
294 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
295 };
296
297 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
298 {
299 { 16, 1, "c0_config1" },
300 { 18, 1, "c0_watchlo,1" },
301 { 19, 1, "c0_watchhi,1" },
302 { 22, 0, "c0_perftrace" },
303 { 23, 3, "c0_edebug" },
304 { 25, 1, "c0_perfcnt,1" },
305 { 25, 2, "c0_perfcnt,2" },
306 { 25, 3, "c0_perfcnt,3" },
307 { 25, 4, "c0_perfcnt,4" },
308 { 25, 5, "c0_perfcnt,5" },
309 { 25, 6, "c0_perfcnt,6" },
310 { 25, 7, "c0_perfcnt,7" },
311 { 26, 1, "c0_buserr_pa" },
312 { 27, 1, "c0_cacheerr_d" },
313 { 27, 3, "c0_cacheerr_d_pa" },
314 { 28, 1, "c0_datalo_i" },
315 { 28, 2, "c0_taglo_d" },
316 { 28, 3, "c0_datalo_d" },
317 { 29, 1, "c0_datahi_i" },
318 { 29, 2, "c0_taghi_d" },
319 { 29, 3, "c0_datahi_d" },
320 };
321
322 static const char * const mips_hwr_names_numeric[32] =
323 {
324 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
325 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
326 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
327 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
328 };
329
330 static const char * const mips_hwr_names_mips3264r2[32] =
331 {
332 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
333 "$4", "$5", "$6", "$7",
334 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
335 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
336 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
337 };
338
339 struct mips_abi_choice
340 {
341 const char * name;
342 const char * const *gpr_names;
343 const char * const *fpr_names;
344 };
345
346 struct mips_abi_choice mips_abi_choices[] =
347 {
348 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
349 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
350 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
351 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
352 };
353
354 struct mips_arch_choice
355 {
356 const char *name;
357 int bfd_mach_valid;
358 unsigned long bfd_mach;
359 int processor;
360 int isa;
361 const char * const *cp0_names;
362 const struct mips_cp0sel_name *cp0sel_names;
363 unsigned int cp0sel_names_len;
364 const char * const *hwr_names;
365 };
366
367 const struct mips_arch_choice mips_arch_choices[] =
368 {
369 { "numeric", 0, 0, 0, 0,
370 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
371
372 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
373 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
374 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
377 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
378 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
389 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
390 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
391 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
392 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
393 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
394 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
395 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
396 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
397 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
398 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
399 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
400 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
401 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
402 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
403 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
404 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
405 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
406 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
407 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
408 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
410 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
411 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
412 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
413 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
414 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
415 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
416 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
417 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
418
419 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
420 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
421 _MIPS32 Architecture For Programmers Volume I: Introduction to the
422 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
423 page 1. */
424 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
425 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
426 mips_cp0_names_mips3264,
427 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
428 mips_hwr_names_numeric },
429
430 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
431 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
432 | INSN_MIPS3D | INSN_MT),
433 mips_cp0_names_mips3264r2,
434 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
435 mips_hwr_names_mips3264r2 },
436
437 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
438 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
439 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
440 mips_cp0_names_mips3264,
441 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
442 mips_hwr_names_numeric },
443
444 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
445 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
446 | INSN_DSP64 | INSN_MT | INSN_MDMX),
447 mips_cp0_names_mips3264r2,
448 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
449 mips_hwr_names_mips3264r2 },
450
451 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
452 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
453 mips_cp0_names_sb1,
454 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
455 mips_hwr_names_numeric },
456
457 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
458 ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric,
459 NULL, 0, mips_hwr_names_numeric },
460
461 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
462 ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
463 NULL, 0, mips_hwr_names_numeric },
464
465 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
466 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
467 mips_hwr_names_numeric },
468
469 /* This entry, mips16, is here only for ISA/processor selection; do
470 not print its name. */
471 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
472 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
473 };
474
475 /* ISA and processor type to disassemble for, and register names to use.
476 set_default_mips_dis_options and parse_mips_dis_options fill in these
477 values. */
478 static int mips_processor;
479 static int mips_isa;
480 static const char * const *mips_gpr_names;
481 static const char * const *mips_fpr_names;
482 static const char * const *mips_cp0_names;
483 static const struct mips_cp0sel_name *mips_cp0sel_names;
484 static int mips_cp0sel_names_len;
485 static const char * const *mips_hwr_names;
486
487 /* Other options */
488 static int no_aliases; /* If set disassemble as most general inst. */
489 \f
490 static const struct mips_abi_choice *
491 choose_abi_by_name (const char *name, unsigned int namelen)
492 {
493 const struct mips_abi_choice *c;
494 unsigned int i;
495
496 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
497 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
498 && strlen (mips_abi_choices[i].name) == namelen)
499 c = &mips_abi_choices[i];
500
501 return c;
502 }
503
504 static const struct mips_arch_choice *
505 choose_arch_by_name (const char *name, unsigned int namelen)
506 {
507 const struct mips_arch_choice *c = NULL;
508 unsigned int i;
509
510 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
511 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
512 && strlen (mips_arch_choices[i].name) == namelen)
513 c = &mips_arch_choices[i];
514
515 return c;
516 }
517
518 static const struct mips_arch_choice *
519 choose_arch_by_number (unsigned long mach)
520 {
521 static unsigned long hint_bfd_mach;
522 static const struct mips_arch_choice *hint_arch_choice;
523 const struct mips_arch_choice *c;
524 unsigned int i;
525
526 /* We optimize this because even if the user specifies no
527 flags, this will be done for every instruction! */
528 if (hint_bfd_mach == mach
529 && hint_arch_choice != NULL
530 && hint_arch_choice->bfd_mach == hint_bfd_mach)
531 return hint_arch_choice;
532
533 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
534 {
535 if (mips_arch_choices[i].bfd_mach_valid
536 && mips_arch_choices[i].bfd_mach == mach)
537 {
538 c = &mips_arch_choices[i];
539 hint_bfd_mach = mach;
540 hint_arch_choice = c;
541 }
542 }
543 return c;
544 }
545
546 /* Check if the object uses NewABI conventions. */
547
548 static int
549 is_newabi (Elf_Internal_Ehdr *header)
550 {
551 /* There are no old-style ABIs which use 64-bit ELF. */
552 if (header->e_ident[EI_CLASS] == ELFCLASS64)
553 return 1;
554
555 /* If a 32-bit ELF file, n32 is a new-style ABI. */
556 if ((header->e_flags & EF_MIPS_ABI2) != 0)
557 return 1;
558
559 return 0;
560 }
561
562 static void
563 set_default_mips_dis_options (struct disassemble_info *info)
564 {
565 const struct mips_arch_choice *chosen_arch;
566
567 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
568 and numeric FPR, CP0 register, and HWR names. */
569 mips_isa = ISA_MIPS3;
570 mips_processor = CPU_R3000;
571 mips_gpr_names = mips_gpr_names_oldabi;
572 mips_fpr_names = mips_fpr_names_numeric;
573 mips_cp0_names = mips_cp0_names_numeric;
574 mips_cp0sel_names = NULL;
575 mips_cp0sel_names_len = 0;
576 mips_hwr_names = mips_hwr_names_numeric;
577 no_aliases = 0;
578
579 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
580 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
581 {
582 Elf_Internal_Ehdr *header;
583
584 header = elf_elfheader (info->section->owner);
585 if (is_newabi (header))
586 mips_gpr_names = mips_gpr_names_newabi;
587 }
588
589 /* Set ISA, architecture, and cp0 register names as best we can. */
590 #if ! SYMTAB_AVAILABLE
591 /* This is running out on a target machine, not in a host tool.
592 FIXME: Where does mips_target_info come from? */
593 target_processor = mips_target_info.processor;
594 mips_isa = mips_target_info.isa;
595 #else
596 chosen_arch = choose_arch_by_number (info->mach);
597 if (chosen_arch != NULL)
598 {
599 mips_processor = chosen_arch->processor;
600 mips_isa = chosen_arch->isa;
601 mips_cp0_names = chosen_arch->cp0_names;
602 mips_cp0sel_names = chosen_arch->cp0sel_names;
603 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
604 mips_hwr_names = chosen_arch->hwr_names;
605 }
606 #endif
607 }
608
609 static void
610 parse_mips_dis_option (const char *option, unsigned int len)
611 {
612 unsigned int i, optionlen, vallen;
613 const char *val;
614 const struct mips_abi_choice *chosen_abi;
615 const struct mips_arch_choice *chosen_arch;
616
617 /* Try to match options that are simple flags */
618 if (CONST_STRNEQ (option, "no-aliases"))
619 {
620 no_aliases = 1;
621 return;
622 }
623
624 /* Look for the = that delimits the end of the option name. */
625 for (i = 0; i < len; i++)
626 if (option[i] == '=')
627 break;
628
629 if (i == 0) /* Invalid option: no name before '='. */
630 return;
631 if (i == len) /* Invalid option: no '='. */
632 return;
633 if (i == (len - 1)) /* Invalid option: no value after '='. */
634 return;
635
636 optionlen = i;
637 val = option + (optionlen + 1);
638 vallen = len - (optionlen + 1);
639
640 if (strncmp ("gpr-names", option, optionlen) == 0
641 && strlen ("gpr-names") == optionlen)
642 {
643 chosen_abi = choose_abi_by_name (val, vallen);
644 if (chosen_abi != NULL)
645 mips_gpr_names = chosen_abi->gpr_names;
646 return;
647 }
648
649 if (strncmp ("fpr-names", option, optionlen) == 0
650 && strlen ("fpr-names") == optionlen)
651 {
652 chosen_abi = choose_abi_by_name (val, vallen);
653 if (chosen_abi != NULL)
654 mips_fpr_names = chosen_abi->fpr_names;
655 return;
656 }
657
658 if (strncmp ("cp0-names", option, optionlen) == 0
659 && strlen ("cp0-names") == optionlen)
660 {
661 chosen_arch = choose_arch_by_name (val, vallen);
662 if (chosen_arch != NULL)
663 {
664 mips_cp0_names = chosen_arch->cp0_names;
665 mips_cp0sel_names = chosen_arch->cp0sel_names;
666 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
667 }
668 return;
669 }
670
671 if (strncmp ("hwr-names", option, optionlen) == 0
672 && strlen ("hwr-names") == optionlen)
673 {
674 chosen_arch = choose_arch_by_name (val, vallen);
675 if (chosen_arch != NULL)
676 mips_hwr_names = chosen_arch->hwr_names;
677 return;
678 }
679
680 if (strncmp ("reg-names", option, optionlen) == 0
681 && strlen ("reg-names") == optionlen)
682 {
683 /* We check both ABI and ARCH here unconditionally, so
684 that "numeric" will do the desirable thing: select
685 numeric register names for all registers. Other than
686 that, a given name probably won't match both. */
687 chosen_abi = choose_abi_by_name (val, vallen);
688 if (chosen_abi != NULL)
689 {
690 mips_gpr_names = chosen_abi->gpr_names;
691 mips_fpr_names = chosen_abi->fpr_names;
692 }
693 chosen_arch = choose_arch_by_name (val, vallen);
694 if (chosen_arch != NULL)
695 {
696 mips_cp0_names = chosen_arch->cp0_names;
697 mips_cp0sel_names = chosen_arch->cp0sel_names;
698 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
699 mips_hwr_names = chosen_arch->hwr_names;
700 }
701 return;
702 }
703
704 /* Invalid option. */
705 }
706
707 static void
708 parse_mips_dis_options (const char *options)
709 {
710 const char *option_end;
711
712 if (options == NULL)
713 return;
714
715 while (*options != '\0')
716 {
717 /* Skip empty options. */
718 if (*options == ',')
719 {
720 options++;
721 continue;
722 }
723
724 /* We know that *options is neither NUL or a comma. */
725 option_end = options + 1;
726 while (*option_end != ',' && *option_end != '\0')
727 option_end++;
728
729 parse_mips_dis_option (options, option_end - options);
730
731 /* Go on to the next one. If option_end points to a comma, it
732 will be skipped above. */
733 options = option_end;
734 }
735 }
736
737 static const struct mips_cp0sel_name *
738 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
739 unsigned int len,
740 unsigned int cp0reg,
741 unsigned int sel)
742 {
743 unsigned int i;
744
745 for (i = 0; i < len; i++)
746 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
747 return &names[i];
748 return NULL;
749 }
750 \f
751 /* Print insn arguments for 32/64-bit code. */
752
753 static void
754 print_insn_args (const char *d,
755 register unsigned long int l,
756 bfd_vma pc,
757 struct disassemble_info *info,
758 const struct mips_opcode *opp)
759 {
760 int op, delta;
761 unsigned int lsb, msb, msbd;
762
763 lsb = 0;
764
765 for (; *d != '\0'; d++)
766 {
767 switch (*d)
768 {
769 case ',':
770 case '(':
771 case ')':
772 case '[':
773 case ']':
774 (*info->fprintf_func) (info->stream, "%c", *d);
775 break;
776
777 case '+':
778 /* Extension character; switch for second char. */
779 d++;
780 switch (*d)
781 {
782 case '\0':
783 /* xgettext:c-format */
784 (*info->fprintf_func) (info->stream,
785 _("# internal error, incomplete extension sequence (+)"));
786 return;
787
788 case 'A':
789 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
790 (*info->fprintf_func) (info->stream, "0x%x", lsb);
791 break;
792
793 case 'B':
794 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
795 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
796 break;
797
798 case '1':
799 (*info->fprintf_func) (info->stream, "0x%lx",
800 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
801 break;
802
803 case '2':
804 (*info->fprintf_func) (info->stream, "0x%lx",
805 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
806 break;
807
808 case '3':
809 (*info->fprintf_func) (info->stream, "0x%lx",
810 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
811 break;
812
813 case '4':
814 (*info->fprintf_func) (info->stream, "0x%lx",
815 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
816 break;
817
818 case 'C':
819 case 'H':
820 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
821 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
822 break;
823
824 case 'D':
825 {
826 const struct mips_cp0sel_name *n;
827 unsigned int cp0reg, sel;
828
829 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
830 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
831
832 /* CP0 register including 'sel' code for mtcN (et al.), to be
833 printed textually if known. If not known, print both
834 CP0 register name and sel numerically since CP0 register
835 with sel 0 may have a name unrelated to register being
836 printed. */
837 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
838 mips_cp0sel_names_len, cp0reg, sel);
839 if (n != NULL)
840 (*info->fprintf_func) (info->stream, "%s", n->name);
841 else
842 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
843 break;
844 }
845
846 case 'E':
847 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
848 (*info->fprintf_func) (info->stream, "0x%x", lsb);
849 break;
850
851 case 'F':
852 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
853 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
854 break;
855
856 case 'G':
857 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
858 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
859 break;
860
861 case 't': /* Coprocessor 0 reg name */
862 (*info->fprintf_func) (info->stream, "%s",
863 mips_cp0_names[(l >> OP_SH_RT) &
864 OP_MASK_RT]);
865 break;
866
867 case 'T': /* Coprocessor 0 reg name */
868 {
869 const struct mips_cp0sel_name *n;
870 unsigned int cp0reg, sel;
871
872 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
873 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
874
875 /* CP0 register including 'sel' code for mftc0, to be
876 printed textually if known. If not known, print both
877 CP0 register name and sel numerically since CP0 register
878 with sel 0 may have a name unrelated to register being
879 printed. */
880 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
881 mips_cp0sel_names_len, cp0reg, sel);
882 if (n != NULL)
883 (*info->fprintf_func) (info->stream, "%s", n->name);
884 else
885 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
886 break;
887 }
888
889 case 'x': /* bbit bit index */
890 (*info->fprintf_func) (info->stream, "0x%lx",
891 (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);
892 break;
893
894 case 'p': /* cins, cins32, exts and exts32 position */
895 (*info->fprintf_func) (info->stream, "0x%lx",
896 (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);
897 break;
898
899 case 's': /* cins and exts length-minus-one */
900 (*info->fprintf_func) (info->stream, "0x%lx",
901 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
902 break;
903
904 case 'S': /* cins32 and exts32 length-minus-one field */
905 (*info->fprintf_func) (info->stream, "0x%lx",
906 (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);
907 break;
908
909 case 'Q': /* seqi/snei immediate field */
910 op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;
911 /* Sign-extend it. */
912 op = (op ^ 512) - 512;
913 (*info->fprintf_func) (info->stream, "%d", op);
914 break;
915
916 default:
917 /* xgettext:c-format */
918 (*info->fprintf_func) (info->stream,
919 _("# internal error, undefined extension sequence (+%c)"),
920 *d);
921 return;
922 }
923 break;
924
925 case '2':
926 (*info->fprintf_func) (info->stream, "0x%lx",
927 (l >> OP_SH_BP) & OP_MASK_BP);
928 break;
929
930 case '3':
931 (*info->fprintf_func) (info->stream, "0x%lx",
932 (l >> OP_SH_SA3) & OP_MASK_SA3);
933 break;
934
935 case '4':
936 (*info->fprintf_func) (info->stream, "0x%lx",
937 (l >> OP_SH_SA4) & OP_MASK_SA4);
938 break;
939
940 case '5':
941 (*info->fprintf_func) (info->stream, "0x%lx",
942 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
943 break;
944
945 case '6':
946 (*info->fprintf_func) (info->stream, "0x%lx",
947 (l >> OP_SH_RS) & OP_MASK_RS);
948 break;
949
950 case '7':
951 (*info->fprintf_func) (info->stream, "$ac%ld",
952 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
953 break;
954
955 case '8':
956 (*info->fprintf_func) (info->stream, "0x%lx",
957 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
958 break;
959
960 case '9':
961 (*info->fprintf_func) (info->stream, "$ac%ld",
962 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
963 break;
964
965 case '0': /* dsp 6-bit signed immediate in bit 20 */
966 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
967 if (delta & 0x20) /* test sign bit */
968 delta |= ~OP_MASK_DSPSFT;
969 (*info->fprintf_func) (info->stream, "%d", delta);
970 break;
971
972 case ':': /* dsp 7-bit signed immediate in bit 19 */
973 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
974 if (delta & 0x40) /* test sign bit */
975 delta |= ~OP_MASK_DSPSFT_7;
976 (*info->fprintf_func) (info->stream, "%d", delta);
977 break;
978
979 case '\'':
980 (*info->fprintf_func) (info->stream, "0x%lx",
981 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
982 break;
983
984 case '@': /* dsp 10-bit signed immediate in bit 16 */
985 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
986 if (delta & 0x200) /* test sign bit */
987 delta |= ~OP_MASK_IMM10;
988 (*info->fprintf_func) (info->stream, "%d", delta);
989 break;
990
991 case '!':
992 (*info->fprintf_func) (info->stream, "%ld",
993 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
994 break;
995
996 case '$':
997 (*info->fprintf_func) (info->stream, "%ld",
998 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
999 break;
1000
1001 case '*':
1002 (*info->fprintf_func) (info->stream, "$ac%ld",
1003 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
1004 break;
1005
1006 case '&':
1007 (*info->fprintf_func) (info->stream, "$ac%ld",
1008 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
1009 break;
1010
1011 case 'g':
1012 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1013 (*info->fprintf_func) (info->stream, "$%ld",
1014 (l >> OP_SH_RD) & OP_MASK_RD);
1015 break;
1016
1017 case 's':
1018 case 'b':
1019 case 'r':
1020 case 'v':
1021 (*info->fprintf_func) (info->stream, "%s",
1022 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1023 break;
1024
1025 case 't':
1026 case 'w':
1027 (*info->fprintf_func) (info->stream, "%s",
1028 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1029 break;
1030
1031 case 'i':
1032 case 'u':
1033 (*info->fprintf_func) (info->stream, "0x%lx",
1034 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1035 break;
1036
1037 case 'j': /* Same as i, but sign-extended. */
1038 case 'o':
1039 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1040 if (delta & 0x8000)
1041 delta |= ~0xffff;
1042 (*info->fprintf_func) (info->stream, "%d",
1043 delta);
1044 break;
1045
1046 case 'h':
1047 (*info->fprintf_func) (info->stream, "0x%x",
1048 (unsigned int) ((l >> OP_SH_PREFX)
1049 & OP_MASK_PREFX));
1050 break;
1051
1052 case 'k':
1053 (*info->fprintf_func) (info->stream, "0x%x",
1054 (unsigned int) ((l >> OP_SH_CACHE)
1055 & OP_MASK_CACHE));
1056 break;
1057
1058 case 'a':
1059 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1060 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1061 /* For gdb disassembler, force odd address on jalx. */
1062 if (info->flavour == bfd_target_unknown_flavour
1063 && strcmp (opp->name, "jalx") == 0)
1064 info->target |= 1;
1065 (*info->print_address_func) (info->target, info);
1066 break;
1067
1068 case 'p':
1069 /* Sign extend the displacement. */
1070 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1071 if (delta & 0x8000)
1072 delta |= ~0xffff;
1073 info->target = (delta << 2) + pc + INSNLEN;
1074 (*info->print_address_func) (info->target, info);
1075 break;
1076
1077 case 'd':
1078 (*info->fprintf_func) (info->stream, "%s",
1079 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1080 break;
1081
1082 case 'U':
1083 {
1084 /* First check for both rd and rt being equal. */
1085 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1086 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
1087 (*info->fprintf_func) (info->stream, "%s",
1088 mips_gpr_names[reg]);
1089 else
1090 {
1091 /* If one is zero use the other. */
1092 if (reg == 0)
1093 (*info->fprintf_func) (info->stream, "%s",
1094 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1095 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
1096 (*info->fprintf_func) (info->stream, "%s",
1097 mips_gpr_names[reg]);
1098 else /* Bogus, result depends on processor. */
1099 (*info->fprintf_func) (info->stream, "%s or %s",
1100 mips_gpr_names[reg],
1101 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1102 }
1103 }
1104 break;
1105
1106 case 'z':
1107 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1108 break;
1109
1110 case '<':
1111 case '1':
1112 (*info->fprintf_func) (info->stream, "0x%lx",
1113 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1114 break;
1115
1116 case 'c':
1117 (*info->fprintf_func) (info->stream, "0x%lx",
1118 (l >> OP_SH_CODE) & OP_MASK_CODE);
1119 break;
1120
1121 case 'q':
1122 (*info->fprintf_func) (info->stream, "0x%lx",
1123 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1124 break;
1125
1126 case 'C':
1127 (*info->fprintf_func) (info->stream, "0x%lx",
1128 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1129 break;
1130
1131 case 'B':
1132 (*info->fprintf_func) (info->stream, "0x%lx",
1133
1134 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1135 break;
1136
1137 case 'J':
1138 (*info->fprintf_func) (info->stream, "0x%lx",
1139 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1140 break;
1141
1142 case 'S':
1143 case 'V':
1144 (*info->fprintf_func) (info->stream, "%s",
1145 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1146 break;
1147
1148 case 'T':
1149 case 'W':
1150 (*info->fprintf_func) (info->stream, "%s",
1151 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1152 break;
1153
1154 case 'D':
1155 (*info->fprintf_func) (info->stream, "%s",
1156 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1157 break;
1158
1159 case 'R':
1160 (*info->fprintf_func) (info->stream, "%s",
1161 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1162 break;
1163
1164 case 'E':
1165 /* Coprocessor register for lwcN instructions, et al.
1166
1167 Note that there is no load/store cp0 instructions, and
1168 that FPU (cp1) instructions disassemble this field using
1169 'T' format. Therefore, until we gain understanding of
1170 cp2 register names, we can simply print the register
1171 numbers. */
1172 (*info->fprintf_func) (info->stream, "$%ld",
1173 (l >> OP_SH_RT) & OP_MASK_RT);
1174 break;
1175
1176 case 'G':
1177 /* Coprocessor register for mtcN instructions, et al. Note
1178 that FPU (cp1) instructions disassemble this field using
1179 'S' format. Therefore, we only need to worry about cp0,
1180 cp2, and cp3. */
1181 op = (l >> OP_SH_OP) & OP_MASK_OP;
1182 if (op == OP_OP_COP0)
1183 (*info->fprintf_func) (info->stream, "%s",
1184 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1185 else
1186 (*info->fprintf_func) (info->stream, "$%ld",
1187 (l >> OP_SH_RD) & OP_MASK_RD);
1188 break;
1189
1190 case 'K':
1191 (*info->fprintf_func) (info->stream, "%s",
1192 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1193 break;
1194
1195 case 'N':
1196 (*info->fprintf_func) (info->stream,
1197 ((opp->pinfo & (FP_D | FP_S)) != 0
1198 ? "$fcc%ld" : "$cc%ld"),
1199 (l >> OP_SH_BCC) & OP_MASK_BCC);
1200 break;
1201
1202 case 'M':
1203 (*info->fprintf_func) (info->stream, "$fcc%ld",
1204 (l >> OP_SH_CCC) & OP_MASK_CCC);
1205 break;
1206
1207 case 'P':
1208 (*info->fprintf_func) (info->stream, "%ld",
1209 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1210 break;
1211
1212 case 'e':
1213 (*info->fprintf_func) (info->stream, "%ld",
1214 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1215 break;
1216
1217 case '%':
1218 (*info->fprintf_func) (info->stream, "%ld",
1219 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1220 break;
1221
1222 case 'H':
1223 (*info->fprintf_func) (info->stream, "%ld",
1224 (l >> OP_SH_SEL) & OP_MASK_SEL);
1225 break;
1226
1227 case 'O':
1228 (*info->fprintf_func) (info->stream, "%ld",
1229 (l >> OP_SH_ALN) & OP_MASK_ALN);
1230 break;
1231
1232 case 'Q':
1233 {
1234 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1235
1236 if ((vsel & 0x10) == 0)
1237 {
1238 int fmt;
1239
1240 vsel &= 0x0f;
1241 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1242 if ((vsel & 1) == 0)
1243 break;
1244 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1245 (l >> OP_SH_FT) & OP_MASK_FT,
1246 vsel >> 1);
1247 }
1248 else if ((vsel & 0x08) == 0)
1249 {
1250 (*info->fprintf_func) (info->stream, "$v%ld",
1251 (l >> OP_SH_FT) & OP_MASK_FT);
1252 }
1253 else
1254 {
1255 (*info->fprintf_func) (info->stream, "0x%lx",
1256 (l >> OP_SH_FT) & OP_MASK_FT);
1257 }
1258 }
1259 break;
1260
1261 case 'X':
1262 (*info->fprintf_func) (info->stream, "$v%ld",
1263 (l >> OP_SH_FD) & OP_MASK_FD);
1264 break;
1265
1266 case 'Y':
1267 (*info->fprintf_func) (info->stream, "$v%ld",
1268 (l >> OP_SH_FS) & OP_MASK_FS);
1269 break;
1270
1271 case 'Z':
1272 (*info->fprintf_func) (info->stream, "$v%ld",
1273 (l >> OP_SH_FT) & OP_MASK_FT);
1274 break;
1275
1276 default:
1277 /* xgettext:c-format */
1278 (*info->fprintf_func) (info->stream,
1279 _("# internal error, undefined modifier (%c)"),
1280 *d);
1281 return;
1282 }
1283 }
1284 }
1285 \f
1286 /* Print the mips instruction at address MEMADDR in debugged memory,
1287 on using INFO. Returns length of the instruction, in bytes, which is
1288 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1289 this is little-endian code. */
1290
1291 static int
1292 print_insn_mips (bfd_vma memaddr,
1293 unsigned long int word,
1294 struct disassemble_info *info)
1295 {
1296 const struct mips_opcode *op;
1297 static bfd_boolean init = 0;
1298 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1299
1300 /* Build a hash table to shorten the search time. */
1301 if (! init)
1302 {
1303 unsigned int i;
1304
1305 for (i = 0; i <= OP_MASK_OP; i++)
1306 {
1307 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1308 {
1309 if (op->pinfo == INSN_MACRO
1310 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1311 continue;
1312 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1313 {
1314 mips_hash[i] = op;
1315 break;
1316 }
1317 }
1318 }
1319
1320 init = 1;
1321 }
1322
1323 info->bytes_per_chunk = INSNLEN;
1324 info->display_endian = info->endian;
1325 info->insn_info_valid = 1;
1326 info->branch_delay_insns = 0;
1327 info->data_size = 0;
1328 info->insn_type = dis_nonbranch;
1329 info->target = 0;
1330 info->target2 = 0;
1331
1332 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1333 if (op != NULL)
1334 {
1335 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1336 {
1337 if (op->pinfo != INSN_MACRO
1338 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1339 && (word & op->mask) == op->match)
1340 {
1341 const char *d;
1342
1343 /* We always allow to disassemble the jalx instruction. */
1344 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1345 && strcmp (op->name, "jalx"))
1346 continue;
1347
1348 /* Figure out instruction type and branch delay information. */
1349 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1350 {
1351 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1352 info->insn_type = dis_jsr;
1353 else
1354 info->insn_type = dis_branch;
1355 info->branch_delay_insns = 1;
1356 }
1357 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1358 | INSN_COND_BRANCH_LIKELY)) != 0)
1359 {
1360 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1361 info->insn_type = dis_condjsr;
1362 else
1363 info->insn_type = dis_condbranch;
1364 info->branch_delay_insns = 1;
1365 }
1366 else if ((op->pinfo & (INSN_STORE_MEMORY
1367 | INSN_LOAD_MEMORY_DELAY)) != 0)
1368 info->insn_type = dis_dref;
1369
1370 (*info->fprintf_func) (info->stream, "%s", op->name);
1371
1372 d = op->args;
1373 if (d != NULL && *d != '\0')
1374 {
1375 (*info->fprintf_func) (info->stream, "\t");
1376 print_insn_args (d, word, memaddr, info, op);
1377 }
1378
1379 return INSNLEN;
1380 }
1381 }
1382 }
1383
1384 /* Handle undefined instructions. */
1385 info->insn_type = dis_noninsn;
1386 (*info->fprintf_func) (info->stream, "0x%lx", word);
1387 return INSNLEN;
1388 }
1389 \f
1390 /* Disassemble an operand for a mips16 instruction. */
1391
1392 static void
1393 print_mips16_insn_arg (char type,
1394 const struct mips_opcode *op,
1395 int l,
1396 bfd_boolean use_extend,
1397 int extend,
1398 bfd_vma memaddr,
1399 struct disassemble_info *info)
1400 {
1401 switch (type)
1402 {
1403 case ',':
1404 case '(':
1405 case ')':
1406 (*info->fprintf_func) (info->stream, "%c", type);
1407 break;
1408
1409 case 'y':
1410 case 'w':
1411 (*info->fprintf_func) (info->stream, "%s",
1412 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1413 & MIPS16OP_MASK_RY)));
1414 break;
1415
1416 case 'x':
1417 case 'v':
1418 (*info->fprintf_func) (info->stream, "%s",
1419 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1420 & MIPS16OP_MASK_RX)));
1421 break;
1422
1423 case 'z':
1424 (*info->fprintf_func) (info->stream, "%s",
1425 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1426 & MIPS16OP_MASK_RZ)));
1427 break;
1428
1429 case 'Z':
1430 (*info->fprintf_func) (info->stream, "%s",
1431 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1432 & MIPS16OP_MASK_MOVE32Z)));
1433 break;
1434
1435 case '0':
1436 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1437 break;
1438
1439 case 'S':
1440 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1441 break;
1442
1443 case 'P':
1444 (*info->fprintf_func) (info->stream, "$pc");
1445 break;
1446
1447 case 'R':
1448 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1449 break;
1450
1451 case 'X':
1452 (*info->fprintf_func) (info->stream, "%s",
1453 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1454 & MIPS16OP_MASK_REGR32)]);
1455 break;
1456
1457 case 'Y':
1458 (*info->fprintf_func) (info->stream, "%s",
1459 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1460 break;
1461
1462 case '<':
1463 case '>':
1464 case '[':
1465 case ']':
1466 case '4':
1467 case '5':
1468 case 'H':
1469 case 'W':
1470 case 'D':
1471 case 'j':
1472 case '6':
1473 case '8':
1474 case 'V':
1475 case 'C':
1476 case 'U':
1477 case 'k':
1478 case 'K':
1479 case 'p':
1480 case 'q':
1481 case 'A':
1482 case 'B':
1483 case 'E':
1484 {
1485 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1486
1487 shift = 0;
1488 signedp = 0;
1489 extbits = 16;
1490 pcrel = 0;
1491 extu = 0;
1492 branch = 0;
1493 switch (type)
1494 {
1495 case '<':
1496 nbits = 3;
1497 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1498 extbits = 5;
1499 extu = 1;
1500 break;
1501 case '>':
1502 nbits = 3;
1503 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1504 extbits = 5;
1505 extu = 1;
1506 break;
1507 case '[':
1508 nbits = 3;
1509 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1510 extbits = 6;
1511 extu = 1;
1512 break;
1513 case ']':
1514 nbits = 3;
1515 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1516 extbits = 6;
1517 extu = 1;
1518 break;
1519 case '4':
1520 nbits = 4;
1521 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1522 signedp = 1;
1523 extbits = 15;
1524 break;
1525 case '5':
1526 nbits = 5;
1527 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1528 info->insn_type = dis_dref;
1529 info->data_size = 1;
1530 break;
1531 case 'H':
1532 nbits = 5;
1533 shift = 1;
1534 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1535 info->insn_type = dis_dref;
1536 info->data_size = 2;
1537 break;
1538 case 'W':
1539 nbits = 5;
1540 shift = 2;
1541 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1542 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1543 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1544 {
1545 info->insn_type = dis_dref;
1546 info->data_size = 4;
1547 }
1548 break;
1549 case 'D':
1550 nbits = 5;
1551 shift = 3;
1552 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1553 info->insn_type = dis_dref;
1554 info->data_size = 8;
1555 break;
1556 case 'j':
1557 nbits = 5;
1558 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1559 signedp = 1;
1560 break;
1561 case '6':
1562 nbits = 6;
1563 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1564 break;
1565 case '8':
1566 nbits = 8;
1567 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1568 break;
1569 case 'V':
1570 nbits = 8;
1571 shift = 2;
1572 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1573 /* FIXME: This might be lw, or it might be addiu to $sp or
1574 $pc. We assume it's load. */
1575 info->insn_type = dis_dref;
1576 info->data_size = 4;
1577 break;
1578 case 'C':
1579 nbits = 8;
1580 shift = 3;
1581 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1582 info->insn_type = dis_dref;
1583 info->data_size = 8;
1584 break;
1585 case 'U':
1586 nbits = 8;
1587 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1588 extu = 1;
1589 break;
1590 case 'k':
1591 nbits = 8;
1592 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1593 signedp = 1;
1594 break;
1595 case 'K':
1596 nbits = 8;
1597 shift = 3;
1598 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1599 signedp = 1;
1600 break;
1601 case 'p':
1602 nbits = 8;
1603 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1604 signedp = 1;
1605 pcrel = 1;
1606 branch = 1;
1607 info->insn_type = dis_condbranch;
1608 break;
1609 case 'q':
1610 nbits = 11;
1611 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1612 signedp = 1;
1613 pcrel = 1;
1614 branch = 1;
1615 info->insn_type = dis_branch;
1616 break;
1617 case 'A':
1618 nbits = 8;
1619 shift = 2;
1620 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1621 pcrel = 1;
1622 /* FIXME: This can be lw or la. We assume it is lw. */
1623 info->insn_type = dis_dref;
1624 info->data_size = 4;
1625 break;
1626 case 'B':
1627 nbits = 5;
1628 shift = 3;
1629 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1630 pcrel = 1;
1631 info->insn_type = dis_dref;
1632 info->data_size = 8;
1633 break;
1634 case 'E':
1635 nbits = 5;
1636 shift = 2;
1637 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1638 pcrel = 1;
1639 break;
1640 default:
1641 abort ();
1642 }
1643
1644 if (! use_extend)
1645 {
1646 if (signedp && immed >= (1 << (nbits - 1)))
1647 immed -= 1 << nbits;
1648 immed <<= shift;
1649 if ((type == '<' || type == '>' || type == '[' || type == ']')
1650 && immed == 0)
1651 immed = 8;
1652 }
1653 else
1654 {
1655 if (extbits == 16)
1656 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1657 else if (extbits == 15)
1658 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1659 else
1660 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1661 immed &= (1 << extbits) - 1;
1662 if (! extu && immed >= (1 << (extbits - 1)))
1663 immed -= 1 << extbits;
1664 }
1665
1666 if (! pcrel)
1667 (*info->fprintf_func) (info->stream, "%d", immed);
1668 else
1669 {
1670 bfd_vma baseaddr;
1671
1672 if (branch)
1673 {
1674 immed *= 2;
1675 baseaddr = memaddr + 2;
1676 }
1677 else if (use_extend)
1678 baseaddr = memaddr - 2;
1679 else
1680 {
1681 int status;
1682 bfd_byte buffer[2];
1683
1684 baseaddr = memaddr;
1685
1686 /* If this instruction is in the delay slot of a jr
1687 instruction, the base address is the address of the
1688 jr instruction. If it is in the delay slot of jalr
1689 instruction, the base address is the address of the
1690 jalr instruction. This test is unreliable: we have
1691 no way of knowing whether the previous word is
1692 instruction or data. */
1693 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1694 info);
1695 if (status == 0
1696 && (((info->endian == BFD_ENDIAN_BIG
1697 ? bfd_getb16 (buffer)
1698 : bfd_getl16 (buffer))
1699 & 0xf800) == 0x1800))
1700 baseaddr = memaddr - 4;
1701 else
1702 {
1703 status = (*info->read_memory_func) (memaddr - 2, buffer,
1704 2, info);
1705 if (status == 0
1706 && (((info->endian == BFD_ENDIAN_BIG
1707 ? bfd_getb16 (buffer)
1708 : bfd_getl16 (buffer))
1709 & 0xf81f) == 0xe800))
1710 baseaddr = memaddr - 2;
1711 }
1712 }
1713 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1714 if (pcrel && branch
1715 && info->flavour == bfd_target_unknown_flavour)
1716 /* For gdb disassembler, maintain odd address. */
1717 info->target |= 1;
1718 (*info->print_address_func) (info->target, info);
1719 }
1720 }
1721 break;
1722
1723 case 'a':
1724 {
1725 int jalx = l & 0x400;
1726
1727 if (! use_extend)
1728 extend = 0;
1729 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1730 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1731 /* For gdb disassembler, maintain odd address. */
1732 l |= 1;
1733 }
1734 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1735 (*info->print_address_func) (info->target, info);
1736 info->insn_type = dis_jsr;
1737 info->branch_delay_insns = 1;
1738 break;
1739
1740 case 'l':
1741 case 'L':
1742 {
1743 int need_comma, amask, smask;
1744
1745 need_comma = 0;
1746
1747 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1748
1749 amask = (l >> 3) & 7;
1750
1751 if (amask > 0 && amask < 5)
1752 {
1753 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1754 if (amask > 1)
1755 (*info->fprintf_func) (info->stream, "-%s",
1756 mips_gpr_names[amask + 3]);
1757 need_comma = 1;
1758 }
1759
1760 smask = (l >> 1) & 3;
1761 if (smask == 3)
1762 {
1763 (*info->fprintf_func) (info->stream, "%s??",
1764 need_comma ? "," : "");
1765 need_comma = 1;
1766 }
1767 else if (smask > 0)
1768 {
1769 (*info->fprintf_func) (info->stream, "%s%s",
1770 need_comma ? "," : "",
1771 mips_gpr_names[16]);
1772 if (smask > 1)
1773 (*info->fprintf_func) (info->stream, "-%s",
1774 mips_gpr_names[smask + 15]);
1775 need_comma = 1;
1776 }
1777
1778 if (l & 1)
1779 {
1780 (*info->fprintf_func) (info->stream, "%s%s",
1781 need_comma ? "," : "",
1782 mips_gpr_names[31]);
1783 need_comma = 1;
1784 }
1785
1786 if (amask == 5 || amask == 6)
1787 {
1788 (*info->fprintf_func) (info->stream, "%s$f0",
1789 need_comma ? "," : "");
1790 if (amask == 6)
1791 (*info->fprintf_func) (info->stream, "-$f1");
1792 }
1793 }
1794 break;
1795
1796 case 'm':
1797 case 'M':
1798 /* MIPS16e save/restore. */
1799 {
1800 int need_comma = 0;
1801 int amask, args, statics;
1802 int nsreg, smask;
1803 int framesz;
1804 int i, j;
1805
1806 l = l & 0x7f;
1807 if (use_extend)
1808 l |= extend << 16;
1809
1810 amask = (l >> 16) & 0xf;
1811 if (amask == MIPS16_ALL_ARGS)
1812 {
1813 args = 4;
1814 statics = 0;
1815 }
1816 else if (amask == MIPS16_ALL_STATICS)
1817 {
1818 args = 0;
1819 statics = 4;
1820 }
1821 else
1822 {
1823 args = amask >> 2;
1824 statics = amask & 3;
1825 }
1826
1827 if (args > 0) {
1828 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1829 if (args > 1)
1830 (*info->fprintf_func) (info->stream, "-%s",
1831 mips_gpr_names[4 + args - 1]);
1832 need_comma = 1;
1833 }
1834
1835 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1836 if (framesz == 0 && !use_extend)
1837 framesz = 128;
1838
1839 (*info->fprintf_func) (info->stream, "%s%d",
1840 need_comma ? "," : "",
1841 framesz);
1842
1843 if (l & 0x40) /* $ra */
1844 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1845
1846 nsreg = (l >> 24) & 0x7;
1847 smask = 0;
1848 if (l & 0x20) /* $s0 */
1849 smask |= 1 << 0;
1850 if (l & 0x10) /* $s1 */
1851 smask |= 1 << 1;
1852 if (nsreg > 0) /* $s2-$s8 */
1853 smask |= ((1 << nsreg) - 1) << 2;
1854
1855 /* Find first set static reg bit. */
1856 for (i = 0; i < 9; i++)
1857 {
1858 if (smask & (1 << i))
1859 {
1860 (*info->fprintf_func) (info->stream, ",%s",
1861 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1862 /* Skip over string of set bits. */
1863 for (j = i; smask & (2 << j); j++)
1864 continue;
1865 if (j > i)
1866 (*info->fprintf_func) (info->stream, "-%s",
1867 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1868 i = j + 1;
1869 }
1870 }
1871
1872 /* Statics $ax - $a3. */
1873 if (statics == 1)
1874 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1875 else if (statics > 0)
1876 (*info->fprintf_func) (info->stream, ",%s-%s",
1877 mips_gpr_names[7 - statics + 1],
1878 mips_gpr_names[7]);
1879 }
1880 break;
1881
1882 default:
1883 /* xgettext:c-format */
1884 (*info->fprintf_func)
1885 (info->stream,
1886 _("# internal disassembler error, unrecognised modifier (%c)"),
1887 type);
1888 abort ();
1889 }
1890 }
1891
1892 /* Disassemble mips16 instructions. */
1893
1894 static int
1895 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1896 {
1897 int status;
1898 bfd_byte buffer[2];
1899 int length;
1900 int insn;
1901 bfd_boolean use_extend;
1902 int extend = 0;
1903 const struct mips_opcode *op, *opend;
1904
1905 info->bytes_per_chunk = 2;
1906 info->display_endian = info->endian;
1907 info->insn_info_valid = 1;
1908 info->branch_delay_insns = 0;
1909 info->data_size = 0;
1910 info->insn_type = dis_nonbranch;
1911 info->target = 0;
1912 info->target2 = 0;
1913
1914 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1915 if (status != 0)
1916 {
1917 (*info->memory_error_func) (status, memaddr, info);
1918 return -1;
1919 }
1920
1921 length = 2;
1922
1923 if (info->endian == BFD_ENDIAN_BIG)
1924 insn = bfd_getb16 (buffer);
1925 else
1926 insn = bfd_getl16 (buffer);
1927
1928 /* Handle the extend opcode specially. */
1929 use_extend = FALSE;
1930 if ((insn & 0xf800) == 0xf000)
1931 {
1932 use_extend = TRUE;
1933 extend = insn & 0x7ff;
1934
1935 memaddr += 2;
1936
1937 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1938 if (status != 0)
1939 {
1940 (*info->fprintf_func) (info->stream, "extend 0x%x",
1941 (unsigned int) extend);
1942 (*info->memory_error_func) (status, memaddr, info);
1943 return -1;
1944 }
1945
1946 if (info->endian == BFD_ENDIAN_BIG)
1947 insn = bfd_getb16 (buffer);
1948 else
1949 insn = bfd_getl16 (buffer);
1950
1951 /* Check for an extend opcode followed by an extend opcode. */
1952 if ((insn & 0xf800) == 0xf000)
1953 {
1954 (*info->fprintf_func) (info->stream, "extend 0x%x",
1955 (unsigned int) extend);
1956 info->insn_type = dis_noninsn;
1957 return length;
1958 }
1959
1960 length += 2;
1961 }
1962
1963 /* FIXME: Should probably use a hash table on the major opcode here. */
1964
1965 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1966 for (op = mips16_opcodes; op < opend; op++)
1967 {
1968 if (op->pinfo != INSN_MACRO
1969 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1970 && (insn & op->mask) == op->match)
1971 {
1972 const char *s;
1973
1974 if (strchr (op->args, 'a') != NULL)
1975 {
1976 if (use_extend)
1977 {
1978 (*info->fprintf_func) (info->stream, "extend 0x%x",
1979 (unsigned int) extend);
1980 info->insn_type = dis_noninsn;
1981 return length - 2;
1982 }
1983
1984 use_extend = FALSE;
1985
1986 memaddr += 2;
1987
1988 status = (*info->read_memory_func) (memaddr, buffer, 2,
1989 info);
1990 if (status == 0)
1991 {
1992 use_extend = TRUE;
1993 if (info->endian == BFD_ENDIAN_BIG)
1994 extend = bfd_getb16 (buffer);
1995 else
1996 extend = bfd_getl16 (buffer);
1997 length += 2;
1998 }
1999 }
2000
2001 (*info->fprintf_func) (info->stream, "%s", op->name);
2002 if (op->args[0] != '\0')
2003 (*info->fprintf_func) (info->stream, "\t");
2004
2005 for (s = op->args; *s != '\0'; s++)
2006 {
2007 if (*s == ','
2008 && s[1] == 'w'
2009 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2010 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2011 {
2012 /* Skip the register and the comma. */
2013 ++s;
2014 continue;
2015 }
2016 if (*s == ','
2017 && s[1] == 'v'
2018 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2019 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2020 {
2021 /* Skip the register and the comma. */
2022 ++s;
2023 continue;
2024 }
2025 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2026 info);
2027 }
2028
2029 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2030 {
2031 info->branch_delay_insns = 1;
2032 if (info->insn_type != dis_jsr)
2033 info->insn_type = dis_branch;
2034 }
2035
2036 return length;
2037 }
2038 }
2039
2040 if (use_extend)
2041 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2042 (*info->fprintf_func) (info->stream, "0x%x", insn);
2043 info->insn_type = dis_noninsn;
2044
2045 return length;
2046 }
2047
2048 /* In an environment where we do not know the symbol type of the
2049 instruction we are forced to assume that the low order bit of the
2050 instructions' address may mark it as a mips16 instruction. If we
2051 are single stepping, or the pc is within the disassembled function,
2052 this works. Otherwise, we need a clue. Sometimes. */
2053
2054 static int
2055 _print_insn_mips (bfd_vma memaddr,
2056 struct disassemble_info *info,
2057 enum bfd_endian endianness)
2058 {
2059 bfd_byte buffer[INSNLEN];
2060 int status;
2061
2062 set_default_mips_dis_options (info);
2063 parse_mips_dis_options (info->disassembler_options);
2064
2065 #if 1
2066 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2067 /* Only a few tools will work this way. */
2068 if (memaddr & 0x01)
2069 return print_insn_mips16 (memaddr, info);
2070 #endif
2071
2072 #if SYMTAB_AVAILABLE
2073 if (info->mach == bfd_mach_mips16
2074 || (info->symbols != NULL
2075 && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
2076 && ELF_ST_IS_MIPS16 ((*(elf_symbol_type **) info->symbols)
2077 ->internal_elf_sym.st_other)))
2078 return print_insn_mips16 (memaddr, info);
2079 #endif
2080
2081 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2082 if (status == 0)
2083 {
2084 unsigned long insn;
2085
2086 if (endianness == BFD_ENDIAN_BIG)
2087 insn = (unsigned long) bfd_getb32 (buffer);
2088 else
2089 insn = (unsigned long) bfd_getl32 (buffer);
2090
2091 return print_insn_mips (memaddr, insn, info);
2092 }
2093 else
2094 {
2095 (*info->memory_error_func) (status, memaddr, info);
2096 return -1;
2097 }
2098 }
2099
2100 int
2101 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2102 {
2103 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2104 }
2105
2106 int
2107 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2108 {
2109 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2110 }
2111 \f
2112 void
2113 print_mips_disassembler_options (FILE *stream)
2114 {
2115 unsigned int i;
2116
2117 fprintf (stream, _("\n\
2118 The following MIPS specific disassembler options are supported for use\n\
2119 with the -M switch (multiple options should be separated by commas):\n"));
2120
2121 fprintf (stream, _("\n\
2122 gpr-names=ABI Print GPR names according to specified ABI.\n\
2123 Default: based on binary being disassembled.\n"));
2124
2125 fprintf (stream, _("\n\
2126 fpr-names=ABI Print FPR names according to specified ABI.\n\
2127 Default: numeric.\n"));
2128
2129 fprintf (stream, _("\n\
2130 cp0-names=ARCH Print CP0 register names according to\n\
2131 specified architecture.\n\
2132 Default: based on binary being disassembled.\n"));
2133
2134 fprintf (stream, _("\n\
2135 hwr-names=ARCH Print HWR names according to specified \n\
2136 architecture.\n\
2137 Default: based on binary being disassembled.\n"));
2138
2139 fprintf (stream, _("\n\
2140 reg-names=ABI Print GPR and FPR names according to\n\
2141 specified ABI.\n"));
2142
2143 fprintf (stream, _("\n\
2144 reg-names=ARCH Print CP0 register and HWR names according to\n\
2145 specified architecture.\n"));
2146
2147 fprintf (stream, _("\n\
2148 For the options above, the following values are supported for \"ABI\":\n\
2149 "));
2150 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2151 fprintf (stream, " %s", mips_abi_choices[i].name);
2152 fprintf (stream, _("\n"));
2153
2154 fprintf (stream, _("\n\
2155 For the options above, The following values are supported for \"ARCH\":\n\
2156 "));
2157 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2158 if (*mips_arch_choices[i].name != '\0')
2159 fprintf (stream, " %s", mips_arch_choices[i].name);
2160 fprintf (stream, _("\n"));
2161
2162 fprintf (stream, _("\n"));
2163 }
GDB Binutils - Deliverables
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