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[deliverable/binutils-gdb.git] / opcodes / mips-dis.c
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44 \f
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
56 {
57 16, 17, 2, 3, 4, 5, 6, 7
58 };
59
60 /* The microMIPS registers with type b. */
61 #define micromips_to_32_reg_b_map mips16_to_32_reg_map
62
63 /* The microMIPS registers with type c. */
64 #define micromips_to_32_reg_c_map mips16_to_32_reg_map
65
66 /* The microMIPS registers with type d. */
67 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
68
69 /* The microMIPS registers with type e. */
70 #define micromips_to_32_reg_e_map mips16_to_32_reg_map
71
72 /* The microMIPS registers with type f. */
73 #define micromips_to_32_reg_f_map mips16_to_32_reg_map
74
75 /* The microMIPS registers with type g. */
76 #define micromips_to_32_reg_g_map mips16_to_32_reg_map
77
78 /* The microMIPS registers with type h. */
79 static const unsigned int micromips_to_32_reg_h_map[] =
80 {
81 5, 5, 6, 4, 4, 4, 4, 4
82 };
83
84 /* The microMIPS registers with type i. */
85 static const unsigned int micromips_to_32_reg_i_map[] =
86 {
87 6, 7, 7, 21, 22, 5, 6, 7
88 };
89
90 /* The microMIPS registers with type j: 32 registers. */
91
92 /* The microMIPS registers with type l. */
93 #define micromips_to_32_reg_l_map mips16_to_32_reg_map
94
95 /* The microMIPS registers with type m. */
96 static const unsigned int micromips_to_32_reg_m_map[] =
97 {
98 0, 17, 2, 3, 16, 18, 19, 20
99 };
100
101 /* The microMIPS registers with type n. */
102 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
103
104 /* The microMIPS registers with type p: 32 registers. */
105
106 /* The microMIPS registers with type q. */
107 static const unsigned int micromips_to_32_reg_q_map[] =
108 {
109 0, 17, 2, 3, 4, 5, 6, 7
110 };
111
112 /* reg type s is $29. */
113
114 /* reg type t is the same as the last register. */
115
116 /* reg type y is $31. */
117
118 /* reg type z is $0. */
119
120 /* micromips imm B type. */
121 static const int micromips_imm_b_map[8] =
122 {
123 1, 4, 8, 12, 16, 20, 24, -1
124 };
125
126 /* micromips imm C type. */
127 static const int micromips_imm_c_map[16] =
128 {
129 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535
130 };
131
132 /* micromips imm D type: (-512..511)<<1. */
133 /* micromips imm E type: (-64..63)<<1. */
134 /* micromips imm F type: (0..63). */
135 /* micromips imm G type: (-1..14). */
136 /* micromips imm H type: (0..15)<<1. */
137 /* micromips imm I type: (-1..126). */
138 /* micromips imm J type: (0..15)<<2. */
139 /* micromips imm L type: (0..15). */
140 /* micromips imm M type: (1..8). */
141 /* micromips imm W type: (0..63)<<2. */
142 /* micromips imm X type: (-8..7). */
143 /* micromips imm Y type: (-258..-3, 2..257)<<2. */
144
145 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
146
147
148 static const char * const mips_gpr_names_numeric[32] =
149 {
150 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
151 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
152 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
153 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
154 };
155
156 static const char * const mips_gpr_names_oldabi[32] =
157 {
158 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
159 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
160 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
161 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
162 };
163
164 static const char * const mips_gpr_names_newabi[32] =
165 {
166 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
167 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
168 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
169 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
170 };
171
172 static const char * const mips_fpr_names_numeric[32] =
173 {
174 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
175 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
176 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
177 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
178 };
179
180 static const char * const mips_fpr_names_32[32] =
181 {
182 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
183 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
184 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
185 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
186 };
187
188 static const char * const mips_fpr_names_n32[32] =
189 {
190 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
191 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
192 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
193 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
194 };
195
196 static const char * const mips_fpr_names_64[32] =
197 {
198 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
199 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
200 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
201 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
202 };
203
204 static const char * const mips_cp0_names_numeric[32] =
205 {
206 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
207 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
208 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
209 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
210 };
211
212 static const char * const mips_cp0_names_r3000[32] =
213 {
214 "c0_index", "c0_random", "c0_entrylo", "$3",
215 "c0_context", "$5", "$6", "$7",
216 "c0_badvaddr", "$9", "c0_entryhi", "$11",
217 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
218 "$16", "$17", "$18", "$19",
219 "$20", "$21", "$22", "$23",
220 "$24", "$25", "$26", "$27",
221 "$28", "$29", "$30", "$31",
222 };
223
224 static const char * const mips_cp0_names_r4000[32] =
225 {
226 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
227 "c0_context", "c0_pagemask", "c0_wired", "$7",
228 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
229 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
230 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
231 "c0_xcontext", "$21", "$22", "$23",
232 "$24", "$25", "c0_ecc", "c0_cacheerr",
233 "c0_taglo", "c0_taghi", "c0_errorepc", "$31",
234 };
235
236 static const char * const mips_cp0_names_r5900[32] =
237 {
238 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
239 "c0_context", "c0_pagemask", "c0_wired", "$7",
240 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
241 "c0_sr", "c0_cause", "c0_epc", "c0_prid",
242 "c0_config", "$17", "$18", "$19",
243 "$20", "$21", "$22", "c0_badpaddr",
244 "c0_depc", "c0_perfcnt", "$26", "$27",
245 "c0_taglo", "c0_taghi", "c0_errorepc", "$31"
246 };
247
248 static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] =
249 {
250 { 24, 2, "c0_iab" },
251 { 24, 3, "c0_iabm" },
252 { 24, 4, "c0_dab" },
253 { 24, 5, "c0_dabm" },
254 { 24, 6, "c0_dvb" },
255 { 24, 7, "c0_dvbm" },
256 { 25, 1, "c0_perfcnt,1" },
257 { 25, 2, "c0_perfcnt,2" }
258 };
259
260 static const char * const mips_cp0_names_mips3264[32] =
261 {
262 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
263 "c0_context", "c0_pagemask", "c0_wired", "$7",
264 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
265 "c0_status", "c0_cause", "c0_epc", "c0_prid",
266 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
267 "c0_xcontext", "$21", "$22", "c0_debug",
268 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
269 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
270 };
271
272 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
273 {
274 { 16, 1, "c0_config1" },
275 { 16, 2, "c0_config2" },
276 { 16, 3, "c0_config3" },
277 { 18, 1, "c0_watchlo,1" },
278 { 18, 2, "c0_watchlo,2" },
279 { 18, 3, "c0_watchlo,3" },
280 { 18, 4, "c0_watchlo,4" },
281 { 18, 5, "c0_watchlo,5" },
282 { 18, 6, "c0_watchlo,6" },
283 { 18, 7, "c0_watchlo,7" },
284 { 19, 1, "c0_watchhi,1" },
285 { 19, 2, "c0_watchhi,2" },
286 { 19, 3, "c0_watchhi,3" },
287 { 19, 4, "c0_watchhi,4" },
288 { 19, 5, "c0_watchhi,5" },
289 { 19, 6, "c0_watchhi,6" },
290 { 19, 7, "c0_watchhi,7" },
291 { 25, 1, "c0_perfcnt,1" },
292 { 25, 2, "c0_perfcnt,2" },
293 { 25, 3, "c0_perfcnt,3" },
294 { 25, 4, "c0_perfcnt,4" },
295 { 25, 5, "c0_perfcnt,5" },
296 { 25, 6, "c0_perfcnt,6" },
297 { 25, 7, "c0_perfcnt,7" },
298 { 27, 1, "c0_cacheerr,1" },
299 { 27, 2, "c0_cacheerr,2" },
300 { 27, 3, "c0_cacheerr,3" },
301 { 28, 1, "c0_datalo" },
302 { 29, 1, "c0_datahi" }
303 };
304
305 static const char * const mips_cp0_names_mips3264r2[32] =
306 {
307 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
308 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
309 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
310 "c0_status", "c0_cause", "c0_epc", "c0_prid",
311 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
312 "c0_xcontext", "$21", "$22", "c0_debug",
313 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
314 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
315 };
316
317 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
318 {
319 { 4, 1, "c0_contextconfig" },
320 { 0, 1, "c0_mvpcontrol" },
321 { 0, 2, "c0_mvpconf0" },
322 { 0, 3, "c0_mvpconf1" },
323 { 1, 1, "c0_vpecontrol" },
324 { 1, 2, "c0_vpeconf0" },
325 { 1, 3, "c0_vpeconf1" },
326 { 1, 4, "c0_yqmask" },
327 { 1, 5, "c0_vpeschedule" },
328 { 1, 6, "c0_vpeschefback" },
329 { 2, 1, "c0_tcstatus" },
330 { 2, 2, "c0_tcbind" },
331 { 2, 3, "c0_tcrestart" },
332 { 2, 4, "c0_tchalt" },
333 { 2, 5, "c0_tccontext" },
334 { 2, 6, "c0_tcschedule" },
335 { 2, 7, "c0_tcschefback" },
336 { 5, 1, "c0_pagegrain" },
337 { 6, 1, "c0_srsconf0" },
338 { 6, 2, "c0_srsconf1" },
339 { 6, 3, "c0_srsconf2" },
340 { 6, 4, "c0_srsconf3" },
341 { 6, 5, "c0_srsconf4" },
342 { 12, 1, "c0_intctl" },
343 { 12, 2, "c0_srsctl" },
344 { 12, 3, "c0_srsmap" },
345 { 15, 1, "c0_ebase" },
346 { 16, 1, "c0_config1" },
347 { 16, 2, "c0_config2" },
348 { 16, 3, "c0_config3" },
349 { 18, 1, "c0_watchlo,1" },
350 { 18, 2, "c0_watchlo,2" },
351 { 18, 3, "c0_watchlo,3" },
352 { 18, 4, "c0_watchlo,4" },
353 { 18, 5, "c0_watchlo,5" },
354 { 18, 6, "c0_watchlo,6" },
355 { 18, 7, "c0_watchlo,7" },
356 { 19, 1, "c0_watchhi,1" },
357 { 19, 2, "c0_watchhi,2" },
358 { 19, 3, "c0_watchhi,3" },
359 { 19, 4, "c0_watchhi,4" },
360 { 19, 5, "c0_watchhi,5" },
361 { 19, 6, "c0_watchhi,6" },
362 { 19, 7, "c0_watchhi,7" },
363 { 23, 1, "c0_tracecontrol" },
364 { 23, 2, "c0_tracecontrol2" },
365 { 23, 3, "c0_usertracedata" },
366 { 23, 4, "c0_tracebpc" },
367 { 25, 1, "c0_perfcnt,1" },
368 { 25, 2, "c0_perfcnt,2" },
369 { 25, 3, "c0_perfcnt,3" },
370 { 25, 4, "c0_perfcnt,4" },
371 { 25, 5, "c0_perfcnt,5" },
372 { 25, 6, "c0_perfcnt,6" },
373 { 25, 7, "c0_perfcnt,7" },
374 { 27, 1, "c0_cacheerr,1" },
375 { 27, 2, "c0_cacheerr,2" },
376 { 27, 3, "c0_cacheerr,3" },
377 { 28, 1, "c0_datalo" },
378 { 28, 2, "c0_taglo1" },
379 { 28, 3, "c0_datalo1" },
380 { 28, 4, "c0_taglo2" },
381 { 28, 5, "c0_datalo2" },
382 { 28, 6, "c0_taglo3" },
383 { 28, 7, "c0_datalo3" },
384 { 29, 1, "c0_datahi" },
385 { 29, 2, "c0_taghi1" },
386 { 29, 3, "c0_datahi1" },
387 { 29, 4, "c0_taghi2" },
388 { 29, 5, "c0_datahi2" },
389 { 29, 6, "c0_taghi3" },
390 { 29, 7, "c0_datahi3" },
391 };
392
393 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
394 static const char * const mips_cp0_names_sb1[32] =
395 {
396 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
397 "c0_context", "c0_pagemask", "c0_wired", "$7",
398 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
399 "c0_status", "c0_cause", "c0_epc", "c0_prid",
400 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
401 "c0_xcontext", "$21", "$22", "c0_debug",
402 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
403 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
404 };
405
406 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
407 {
408 { 16, 1, "c0_config1" },
409 { 18, 1, "c0_watchlo,1" },
410 { 19, 1, "c0_watchhi,1" },
411 { 22, 0, "c0_perftrace" },
412 { 23, 3, "c0_edebug" },
413 { 25, 1, "c0_perfcnt,1" },
414 { 25, 2, "c0_perfcnt,2" },
415 { 25, 3, "c0_perfcnt,3" },
416 { 25, 4, "c0_perfcnt,4" },
417 { 25, 5, "c0_perfcnt,5" },
418 { 25, 6, "c0_perfcnt,6" },
419 { 25, 7, "c0_perfcnt,7" },
420 { 26, 1, "c0_buserr_pa" },
421 { 27, 1, "c0_cacheerr_d" },
422 { 27, 3, "c0_cacheerr_d_pa" },
423 { 28, 1, "c0_datalo_i" },
424 { 28, 2, "c0_taglo_d" },
425 { 28, 3, "c0_datalo_d" },
426 { 29, 1, "c0_datahi_i" },
427 { 29, 2, "c0_taghi_d" },
428 { 29, 3, "c0_datahi_d" },
429 };
430
431 /* Xlr cop0 register names. */
432 static const char * const mips_cp0_names_xlr[32] = {
433 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
434 "c0_context", "c0_pagemask", "c0_wired", "$7",
435 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
436 "c0_status", "c0_cause", "c0_epc", "c0_prid",
437 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
438 "c0_xcontext", "$21", "$22", "c0_debug",
439 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
440 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
441 };
442
443 /* XLR's CP0 Select Registers. */
444
445 static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
446 { 9, 6, "c0_extintreq" },
447 { 9, 7, "c0_extintmask" },
448 { 15, 1, "c0_ebase" },
449 { 16, 1, "c0_config1" },
450 { 16, 2, "c0_config2" },
451 { 16, 3, "c0_config3" },
452 { 16, 7, "c0_procid2" },
453 { 18, 1, "c0_watchlo,1" },
454 { 18, 2, "c0_watchlo,2" },
455 { 18, 3, "c0_watchlo,3" },
456 { 18, 4, "c0_watchlo,4" },
457 { 18, 5, "c0_watchlo,5" },
458 { 18, 6, "c0_watchlo,6" },
459 { 18, 7, "c0_watchlo,7" },
460 { 19, 1, "c0_watchhi,1" },
461 { 19, 2, "c0_watchhi,2" },
462 { 19, 3, "c0_watchhi,3" },
463 { 19, 4, "c0_watchhi,4" },
464 { 19, 5, "c0_watchhi,5" },
465 { 19, 6, "c0_watchhi,6" },
466 { 19, 7, "c0_watchhi,7" },
467 { 25, 1, "c0_perfcnt,1" },
468 { 25, 2, "c0_perfcnt,2" },
469 { 25, 3, "c0_perfcnt,3" },
470 { 25, 4, "c0_perfcnt,4" },
471 { 25, 5, "c0_perfcnt,5" },
472 { 25, 6, "c0_perfcnt,6" },
473 { 25, 7, "c0_perfcnt,7" },
474 { 27, 1, "c0_cacheerr,1" },
475 { 27, 2, "c0_cacheerr,2" },
476 { 27, 3, "c0_cacheerr,3" },
477 { 28, 1, "c0_datalo" },
478 { 29, 1, "c0_datahi" }
479 };
480
481 static const char * const mips_hwr_names_numeric[32] =
482 {
483 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
484 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
485 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
486 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
487 };
488
489 static const char * const mips_hwr_names_mips3264r2[32] =
490 {
491 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
492 "$4", "$5", "$6", "$7",
493 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
494 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
495 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
496 };
497
498 struct mips_abi_choice
499 {
500 const char * name;
501 const char * const *gpr_names;
502 const char * const *fpr_names;
503 };
504
505 struct mips_abi_choice mips_abi_choices[] =
506 {
507 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
508 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
509 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
510 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
511 };
512
513 struct mips_arch_choice
514 {
515 const char *name;
516 int bfd_mach_valid;
517 unsigned long bfd_mach;
518 int processor;
519 int isa;
520 int ase;
521 const char * const *cp0_names;
522 const struct mips_cp0sel_name *cp0sel_names;
523 unsigned int cp0sel_names_len;
524 const char * const *hwr_names;
525 };
526
527 const struct mips_arch_choice mips_arch_choices[] =
528 {
529 { "numeric", 0, 0, 0, 0, 0,
530 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
531
532 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
533 mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
534 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
535 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
536 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
537 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
538 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
539 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
540 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
541 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
542 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
543 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
544 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
545 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
546 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
547 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
548 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
549 mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
550 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
551 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
552 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
553 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
554 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
555 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
556 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
557 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
558 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
559 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
560 { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
561 mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
562 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
563 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
564 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
565 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
566 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
567 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
568 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
569 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
570 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
571 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
572 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
573 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
574 { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
575 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
576 { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
577 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
578 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
579 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
580
581 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
582 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
583 _MIPS32 Architecture For Programmers Volume I: Introduction to the
584 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
585 page 1. */
586 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
587 ISA_MIPS32, ASE_SMARTMIPS,
588 mips_cp0_names_mips3264,
589 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
590 mips_hwr_names_numeric },
591
592 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
593 ISA_MIPS32R2,
594 (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_MIPS3D | ASE_MT
595 | ASE_MCU | ASE_VIRT),
596 mips_cp0_names_mips3264r2,
597 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
598 mips_hwr_names_mips3264r2 },
599
600 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
601 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
602 ISA_MIPS64, ASE_MIPS3D | ASE_MDMX,
603 mips_cp0_names_mips3264,
604 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
605 mips_hwr_names_numeric },
606
607 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
608 ISA_MIPS64R2,
609 (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_MT | ASE_MDMX
610 | ASE_MCU | ASE_VIRT | ASE_VIRT64),
611 mips_cp0_names_mips3264r2,
612 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
613 mips_hwr_names_mips3264r2 },
614
615 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
616 ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
617 mips_cp0_names_sb1,
618 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
619 mips_hwr_names_numeric },
620
621 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
622 ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
623 NULL, 0, mips_hwr_names_numeric },
624
625 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
626 ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
627 NULL, 0, mips_hwr_names_numeric },
628
629 { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
630 ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
631 NULL, 0, mips_hwr_names_numeric },
632
633 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
634 ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
635 mips_hwr_names_numeric },
636
637 { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
638 ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
639 NULL, 0, mips_hwr_names_numeric },
640
641 { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2,
642 ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
643 NULL, 0, mips_hwr_names_numeric },
644
645 { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
646 ISA_MIPS64 | INSN_XLR, 0,
647 mips_cp0_names_xlr,
648 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
649 mips_hwr_names_numeric },
650
651 /* XLP is mostly like XLR, with the prominent exception it is being
652 MIPS64R2. */
653 { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
654 ISA_MIPS64R2 | INSN_XLR, 0,
655 mips_cp0_names_xlr,
656 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
657 mips_hwr_names_numeric },
658
659 /* This entry, mips16, is here only for ISA/processor selection; do
660 not print its name. */
661 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
662 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
663 };
664
665 /* ISA and processor type to disassemble for, and register names to use.
666 set_default_mips_dis_options and parse_mips_dis_options fill in these
667 values. */
668 static int mips_processor;
669 static int mips_isa;
670 static int mips_ase;
671 static int micromips_ase;
672 static const char * const *mips_gpr_names;
673 static const char * const *mips_fpr_names;
674 static const char * const *mips_cp0_names;
675 static const struct mips_cp0sel_name *mips_cp0sel_names;
676 static int mips_cp0sel_names_len;
677 static const char * const *mips_hwr_names;
678
679 /* Other options */
680 static int no_aliases; /* If set disassemble as most general inst. */
681 \f
682 static const struct mips_abi_choice *
683 choose_abi_by_name (const char *name, unsigned int namelen)
684 {
685 const struct mips_abi_choice *c;
686 unsigned int i;
687
688 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
689 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
690 && strlen (mips_abi_choices[i].name) == namelen)
691 c = &mips_abi_choices[i];
692
693 return c;
694 }
695
696 static const struct mips_arch_choice *
697 choose_arch_by_name (const char *name, unsigned int namelen)
698 {
699 const struct mips_arch_choice *c = NULL;
700 unsigned int i;
701
702 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
703 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
704 && strlen (mips_arch_choices[i].name) == namelen)
705 c = &mips_arch_choices[i];
706
707 return c;
708 }
709
710 static const struct mips_arch_choice *
711 choose_arch_by_number (unsigned long mach)
712 {
713 static unsigned long hint_bfd_mach;
714 static const struct mips_arch_choice *hint_arch_choice;
715 const struct mips_arch_choice *c;
716 unsigned int i;
717
718 /* We optimize this because even if the user specifies no
719 flags, this will be done for every instruction! */
720 if (hint_bfd_mach == mach
721 && hint_arch_choice != NULL
722 && hint_arch_choice->bfd_mach == hint_bfd_mach)
723 return hint_arch_choice;
724
725 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
726 {
727 if (mips_arch_choices[i].bfd_mach_valid
728 && mips_arch_choices[i].bfd_mach == mach)
729 {
730 c = &mips_arch_choices[i];
731 hint_bfd_mach = mach;
732 hint_arch_choice = c;
733 }
734 }
735 return c;
736 }
737
738 /* Check if the object uses NewABI conventions. */
739
740 static int
741 is_newabi (Elf_Internal_Ehdr *header)
742 {
743 /* There are no old-style ABIs which use 64-bit ELF. */
744 if (header->e_ident[EI_CLASS] == ELFCLASS64)
745 return 1;
746
747 /* If a 32-bit ELF file, n32 is a new-style ABI. */
748 if ((header->e_flags & EF_MIPS_ABI2) != 0)
749 return 1;
750
751 return 0;
752 }
753
754 /* Check if the object has microMIPS ASE code. */
755
756 static int
757 is_micromips (Elf_Internal_Ehdr *header)
758 {
759 if ((header->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0)
760 return 1;
761
762 return 0;
763 }
764
765 static void
766 set_default_mips_dis_options (struct disassemble_info *info)
767 {
768 const struct mips_arch_choice *chosen_arch;
769
770 /* Defaults: mipsIII/r3000 (?!), no microMIPS ASE (any compressed code
771 is MIPS16 ASE) (o)32-style ("oldabi") GPR names, and numeric FPR,
772 CP0 register, and HWR names. */
773 mips_isa = ISA_MIPS3;
774 mips_processor = CPU_R3000;
775 micromips_ase = 0;
776 mips_ase = 0;
777 mips_gpr_names = mips_gpr_names_oldabi;
778 mips_fpr_names = mips_fpr_names_numeric;
779 mips_cp0_names = mips_cp0_names_numeric;
780 mips_cp0sel_names = NULL;
781 mips_cp0sel_names_len = 0;
782 mips_hwr_names = mips_hwr_names_numeric;
783 no_aliases = 0;
784
785 /* Update settings according to the ELF file header flags. */
786 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
787 {
788 Elf_Internal_Ehdr *header;
789
790 header = elf_elfheader (info->section->owner);
791 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
792 if (is_newabi (header))
793 mips_gpr_names = mips_gpr_names_newabi;
794 /* If a microMIPS binary, then don't use MIPS16 bindings. */
795 micromips_ase = is_micromips (header);
796 }
797
798 /* Set ISA, architecture, and cp0 register names as best we can. */
799 #if ! SYMTAB_AVAILABLE
800 /* This is running out on a target machine, not in a host tool.
801 FIXME: Where does mips_target_info come from? */
802 target_processor = mips_target_info.processor;
803 mips_isa = mips_target_info.isa;
804 mips_ase = mips_target_info.ase;
805 #else
806 chosen_arch = choose_arch_by_number (info->mach);
807 if (chosen_arch != NULL)
808 {
809 mips_processor = chosen_arch->processor;
810 mips_isa = chosen_arch->isa;
811 mips_ase = chosen_arch->ase;
812 mips_cp0_names = chosen_arch->cp0_names;
813 mips_cp0sel_names = chosen_arch->cp0sel_names;
814 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
815 mips_hwr_names = chosen_arch->hwr_names;
816 }
817 #endif
818 }
819
820 static void
821 parse_mips_dis_option (const char *option, unsigned int len)
822 {
823 unsigned int i, optionlen, vallen;
824 const char *val;
825 const struct mips_abi_choice *chosen_abi;
826 const struct mips_arch_choice *chosen_arch;
827
828 /* Try to match options that are simple flags */
829 if (CONST_STRNEQ (option, "no-aliases"))
830 {
831 no_aliases = 1;
832 return;
833 }
834
835 if (CONST_STRNEQ (option, "virt"))
836 {
837 mips_ase |= ASE_VIRT;
838 if (mips_isa & ISA_MIPS64R2)
839 mips_ase |= ASE_VIRT64;
840 return;
841 }
842
843 /* Look for the = that delimits the end of the option name. */
844 for (i = 0; i < len; i++)
845 if (option[i] == '=')
846 break;
847
848 if (i == 0) /* Invalid option: no name before '='. */
849 return;
850 if (i == len) /* Invalid option: no '='. */
851 return;
852 if (i == (len - 1)) /* Invalid option: no value after '='. */
853 return;
854
855 optionlen = i;
856 val = option + (optionlen + 1);
857 vallen = len - (optionlen + 1);
858
859 if (strncmp ("gpr-names", option, optionlen) == 0
860 && strlen ("gpr-names") == optionlen)
861 {
862 chosen_abi = choose_abi_by_name (val, vallen);
863 if (chosen_abi != NULL)
864 mips_gpr_names = chosen_abi->gpr_names;
865 return;
866 }
867
868 if (strncmp ("fpr-names", option, optionlen) == 0
869 && strlen ("fpr-names") == optionlen)
870 {
871 chosen_abi = choose_abi_by_name (val, vallen);
872 if (chosen_abi != NULL)
873 mips_fpr_names = chosen_abi->fpr_names;
874 return;
875 }
876
877 if (strncmp ("cp0-names", option, optionlen) == 0
878 && strlen ("cp0-names") == optionlen)
879 {
880 chosen_arch = choose_arch_by_name (val, vallen);
881 if (chosen_arch != NULL)
882 {
883 mips_cp0_names = chosen_arch->cp0_names;
884 mips_cp0sel_names = chosen_arch->cp0sel_names;
885 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
886 }
887 return;
888 }
889
890 if (strncmp ("hwr-names", option, optionlen) == 0
891 && strlen ("hwr-names") == optionlen)
892 {
893 chosen_arch = choose_arch_by_name (val, vallen);
894 if (chosen_arch != NULL)
895 mips_hwr_names = chosen_arch->hwr_names;
896 return;
897 }
898
899 if (strncmp ("reg-names", option, optionlen) == 0
900 && strlen ("reg-names") == optionlen)
901 {
902 /* We check both ABI and ARCH here unconditionally, so
903 that "numeric" will do the desirable thing: select
904 numeric register names for all registers. Other than
905 that, a given name probably won't match both. */
906 chosen_abi = choose_abi_by_name (val, vallen);
907 if (chosen_abi != NULL)
908 {
909 mips_gpr_names = chosen_abi->gpr_names;
910 mips_fpr_names = chosen_abi->fpr_names;
911 }
912 chosen_arch = choose_arch_by_name (val, vallen);
913 if (chosen_arch != NULL)
914 {
915 mips_cp0_names = chosen_arch->cp0_names;
916 mips_cp0sel_names = chosen_arch->cp0sel_names;
917 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
918 mips_hwr_names = chosen_arch->hwr_names;
919 }
920 return;
921 }
922
923 /* Invalid option. */
924 }
925
926 static void
927 parse_mips_dis_options (const char *options)
928 {
929 const char *option_end;
930
931 if (options == NULL)
932 return;
933
934 while (*options != '\0')
935 {
936 /* Skip empty options. */
937 if (*options == ',')
938 {
939 options++;
940 continue;
941 }
942
943 /* We know that *options is neither NUL or a comma. */
944 option_end = options + 1;
945 while (*option_end != ',' && *option_end != '\0')
946 option_end++;
947
948 parse_mips_dis_option (options, option_end - options);
949
950 /* Go on to the next one. If option_end points to a comma, it
951 will be skipped above. */
952 options = option_end;
953 }
954 }
955
956 static const struct mips_cp0sel_name *
957 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
958 unsigned int len,
959 unsigned int cp0reg,
960 unsigned int sel)
961 {
962 unsigned int i;
963
964 for (i = 0; i < len; i++)
965 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
966 return &names[i];
967 return NULL;
968 }
969 \f
970 /* Print insn arguments for 32/64-bit code. */
971
972 static void
973 print_insn_args (const char *d,
974 int l,
975 bfd_vma pc,
976 struct disassemble_info *info,
977 const struct mips_opcode *opp)
978 {
979 const fprintf_ftype infprintf = info->fprintf_func;
980 unsigned int lsb, msb, msbd;
981 void *is = info->stream;
982 int op;
983
984 lsb = 0;
985
986 #define GET_OP(insn, field) \
987 (((insn) >> OP_SH_##field) & OP_MASK_##field)
988 #define GET_OP_S(insn, field) \
989 ((GET_OP (insn, field) ^ ((OP_MASK_##field >> 1) + 1)) \
990 - ((OP_MASK_##field >> 1) + 1))
991 for (; *d != '\0'; d++)
992 {
993 switch (*d)
994 {
995 case ',':
996 case '(':
997 case ')':
998 case '[':
999 case ']':
1000 infprintf (is, "%c", *d);
1001 break;
1002
1003 case '+':
1004 /* Extension character; switch for second char. */
1005 d++;
1006 switch (*d)
1007 {
1008 case '\0':
1009 /* xgettext:c-format */
1010 infprintf (is,
1011 _("# internal error, "
1012 "incomplete extension sequence (+)"));
1013 return;
1014
1015 case 'A':
1016 lsb = GET_OP (l, SHAMT);
1017 infprintf (is, "0x%x", lsb);
1018 break;
1019
1020 case 'B':
1021 msb = GET_OP (l, INSMSB);
1022 infprintf (is, "0x%x", msb - lsb + 1);
1023 break;
1024
1025 case '1':
1026 infprintf (is, "0x%x", GET_OP (l, UDI1));
1027 break;
1028
1029 case '2':
1030 infprintf (is, "0x%x", GET_OP (l, UDI2));
1031 break;
1032
1033 case '3':
1034 infprintf (is, "0x%x", GET_OP (l, UDI3));
1035 break;
1036
1037 case '4':
1038 infprintf (is, "0x%x", GET_OP (l, UDI4));
1039 break;
1040
1041 case 'C':
1042 case 'H':
1043 msbd = GET_OP (l, EXTMSBD);
1044 infprintf (is, "0x%x", msbd + 1);
1045 break;
1046
1047 case 'D':
1048 {
1049 const struct mips_cp0sel_name *n;
1050 unsigned int cp0reg, sel;
1051
1052 cp0reg = GET_OP (l, RD);
1053 sel = GET_OP (l, SEL);
1054
1055 /* CP0 register including 'sel' code for mtcN (et al.), to be
1056 printed textually if known. If not known, print both
1057 CP0 register name and sel numerically since CP0 register
1058 with sel 0 may have a name unrelated to register being
1059 printed. */
1060 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
1061 mips_cp0sel_names_len, cp0reg, sel);
1062 if (n != NULL)
1063 infprintf (is, "%s", n->name);
1064 else
1065 infprintf (is, "$%d,%d", cp0reg, sel);
1066 break;
1067 }
1068
1069 case 'E':
1070 lsb = GET_OP (l, SHAMT) + 32;
1071 infprintf (is, "0x%x", lsb);
1072 break;
1073
1074 case 'F':
1075 msb = GET_OP (l, INSMSB) + 32;
1076 infprintf (is, "0x%x", msb - lsb + 1);
1077 break;
1078
1079 case 'G':
1080 msbd = GET_OP (l, EXTMSBD) + 32;
1081 infprintf (is, "0x%x", msbd + 1);
1082 break;
1083
1084 case 'J': /* hypcall operand */
1085 infprintf (is, "0x%x", GET_OP (l, CODE10));
1086 break;
1087
1088 case 't': /* Coprocessor 0 reg name */
1089 infprintf (is, "%s", mips_cp0_names[GET_OP (l, RT)]);
1090 break;
1091
1092 case 'T': /* Coprocessor 0 reg name */
1093 {
1094 const struct mips_cp0sel_name *n;
1095 unsigned int cp0reg, sel;
1096
1097 cp0reg = GET_OP (l, RT);
1098 sel = GET_OP (l, SEL);
1099
1100 /* CP0 register including 'sel' code for mftc0, to be
1101 printed textually if known. If not known, print both
1102 CP0 register name and sel numerically since CP0 register
1103 with sel 0 may have a name unrelated to register being
1104 printed. */
1105 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
1106 mips_cp0sel_names_len, cp0reg, sel);
1107 if (n != NULL)
1108 infprintf (is, "%s", n->name);
1109 else
1110 infprintf (is, "$%d,%d", cp0reg, sel);
1111 break;
1112 }
1113
1114 case 'x': /* bbit bit index */
1115 infprintf (is, "0x%x", GET_OP (l, BBITIND));
1116 break;
1117
1118 case 'p': /* cins, cins32, exts and exts32 position */
1119 infprintf (is, "0x%x", GET_OP (l, CINSPOS));
1120 break;
1121
1122 case 's': /* cins and exts length-minus-one */
1123 infprintf (is, "0x%x", GET_OP (l, CINSLM1));
1124 break;
1125
1126 case 'S': /* cins32 and exts32 length-minus-one field */
1127 infprintf (is, "0x%x", GET_OP (l, CINSLM1));
1128 break;
1129
1130 case 'Q': /* seqi/snei immediate field */
1131 infprintf (is, "%d", GET_OP_S (l, SEQI));
1132 break;
1133
1134 case 'a': /* 8-bit signed offset in bit 6 */
1135 infprintf (is, "%d", GET_OP_S (l, OFFSET_A));
1136 break;
1137
1138 case 'b': /* 8-bit signed offset in bit 3 */
1139 infprintf (is, "%d", GET_OP_S (l, OFFSET_B));
1140 break;
1141
1142 case 'c': /* 9-bit signed offset in bit 6 */
1143 /* Left shift 4 bits to print the real offset. */
1144 infprintf (is, "%d", GET_OP_S (l, OFFSET_C) << 4);
1145 break;
1146
1147 case 'z':
1148 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RZ)]);
1149 break;
1150
1151 case 'Z':
1152 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]);
1153 break;
1154
1155 default:
1156 /* xgettext:c-format */
1157 infprintf (is,
1158 _("# internal error, "
1159 "undefined extension sequence (+%c)"),
1160 *d);
1161 return;
1162 }
1163 break;
1164
1165 case '2':
1166 infprintf (is, "0x%x", GET_OP (l, BP));
1167 break;
1168
1169 case '3':
1170 infprintf (is, "0x%x", GET_OP (l, SA3));
1171 break;
1172
1173 case '4':
1174 infprintf (is, "0x%x", GET_OP (l, SA4));
1175 break;
1176
1177 case '5':
1178 infprintf (is, "0x%x", GET_OP (l, IMM8));
1179 break;
1180
1181 case '6':
1182 infprintf (is, "0x%x", GET_OP (l, RS));
1183 break;
1184
1185 case '7':
1186 infprintf (is, "$ac%d", GET_OP (l, DSPACC));
1187 break;
1188
1189 case '8':
1190 infprintf (is, "0x%x", GET_OP (l, WRDSP));
1191 break;
1192
1193 case '9':
1194 infprintf (is, "$ac%d", GET_OP (l, DSPACC_S));
1195 break;
1196
1197 case '0': /* dsp 6-bit signed immediate in bit 20 */
1198 infprintf (is, "%d", GET_OP_S (l, DSPSFT));
1199 break;
1200
1201 case ':': /* dsp 7-bit signed immediate in bit 19 */
1202 infprintf (is, "%d", GET_OP_S (l, DSPSFT_7));
1203 break;
1204
1205 case '~':
1206 infprintf (is, "%d", GET_OP_S (l, OFFSET12));
1207 break;
1208
1209 case '\\':
1210 infprintf (is, "0x%x", GET_OP (l, 3BITPOS));
1211 break;
1212
1213 case '\'':
1214 infprintf (is, "0x%x", GET_OP (l, RDDSP));
1215 break;
1216
1217 case '@': /* dsp 10-bit signed immediate in bit 16 */
1218 infprintf (is, "%d", GET_OP_S (l, IMM10));
1219 break;
1220
1221 case '!':
1222 infprintf (is, "%d", GET_OP (l, MT_U));
1223 break;
1224
1225 case '$':
1226 infprintf (is, "%d", GET_OP (l, MT_H));
1227 break;
1228
1229 case '*':
1230 infprintf (is, "$ac%d", GET_OP (l, MTACC_T));
1231 break;
1232
1233 case '&':
1234 infprintf (is, "$ac%d", GET_OP (l, MTACC_D));
1235 break;
1236
1237 case 'g':
1238 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
1239 infprintf (is, "$%d", GET_OP (l, RD));
1240 break;
1241
1242 case 's':
1243 case 'b':
1244 case 'r':
1245 case 'v':
1246 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RS)]);
1247 break;
1248
1249 case 't':
1250 case 'w':
1251 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
1252 break;
1253
1254 case 'i':
1255 case 'u':
1256 infprintf (is, "0x%x", GET_OP (l, IMMEDIATE));
1257 break;
1258
1259 case 'j': /* Same as i, but sign-extended. */
1260 case 'o':
1261 infprintf (is, "%d", GET_OP_S (l, DELTA));
1262 break;
1263
1264 case 'h':
1265 infprintf (is, "0x%x", GET_OP (l, PREFX));
1266 break;
1267
1268 case 'k':
1269 infprintf (is, "0x%x", GET_OP (l, CACHE));
1270 break;
1271
1272 case 'a':
1273 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1274 | (GET_OP (l, TARGET) << 2));
1275 /* For gdb disassembler, force odd address on jalx. */
1276 if (info->flavour == bfd_target_unknown_flavour
1277 && strcmp (opp->name, "jalx") == 0)
1278 info->target |= 1;
1279 (*info->print_address_func) (info->target, info);
1280 break;
1281
1282 case 'p':
1283 /* Sign extend the displacement. */
1284 info->target = (GET_OP_S (l, DELTA) << 2) + pc + INSNLEN;
1285 (*info->print_address_func) (info->target, info);
1286 break;
1287
1288 case 'd':
1289 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RD)]);
1290 break;
1291
1292 case 'U':
1293 {
1294 /* First check for both rd and rt being equal. */
1295 unsigned int reg;
1296
1297 reg = GET_OP (l, RD);
1298 if (reg == GET_OP (l, RT))
1299 infprintf (is, "%s", mips_gpr_names[reg]);
1300 else
1301 {
1302 /* If one is zero use the other. */
1303 if (reg == 0)
1304 infprintf (is, "%s", mips_gpr_names[GET_OP (l, RT)]);
1305 else if (GET_OP (l, RT) == 0)
1306 infprintf (is, "%s", mips_gpr_names[reg]);
1307 else /* Bogus, result depends on processor. */
1308 infprintf (is, "%s or %s",
1309 mips_gpr_names[reg],
1310 mips_gpr_names[GET_OP (l, RT)]);
1311 }
1312 }
1313 break;
1314
1315 case 'z':
1316 infprintf (is, "%s", mips_gpr_names[0]);
1317 break;
1318
1319 case '<':
1320 case '1':
1321 infprintf (is, "0x%x", GET_OP (l, SHAMT));
1322 break;
1323
1324 case 'c':
1325 infprintf (is, "0x%x", GET_OP (l, CODE));
1326 break;
1327
1328 case 'q':
1329 infprintf (is, "0x%x", GET_OP (l, CODE2));
1330 break;
1331
1332 case 'C':
1333 infprintf (is, "0x%x", GET_OP (l, COPZ));
1334 break;
1335
1336 case 'B':
1337 infprintf (is, "0x%x", GET_OP (l, CODE20));
1338 break;
1339
1340 case 'J':
1341 infprintf (is, "0x%x", GET_OP (l, CODE19));
1342 break;
1343
1344 case 'S':
1345 case 'V':
1346 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FS)]);
1347 break;
1348
1349 case 'T':
1350 case 'W':
1351 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FT)]);
1352 break;
1353
1354 case 'D':
1355 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FD)]);
1356 break;
1357
1358 case 'R':
1359 infprintf (is, "%s", mips_fpr_names[GET_OP (l, FR)]);
1360 break;
1361
1362 case 'E':
1363 /* Coprocessor register for lwcN instructions, et al.
1364
1365 Note that there is no load/store cp0 instructions, and
1366 that FPU (cp1) instructions disassemble this field using
1367 'T' format. Therefore, until we gain understanding of
1368 cp2 register names, we can simply print the register
1369 numbers. */
1370 infprintf (is, "$%d", GET_OP (l, RT));
1371 break;
1372
1373 case 'G':
1374 /* Coprocessor register for mtcN instructions, et al. Note
1375 that FPU (cp1) instructions disassemble this field using
1376 'S' format. Therefore, we only need to worry about cp0,
1377 cp2, and cp3. */
1378 op = GET_OP (l, OP);
1379 if (op == OP_OP_COP0)
1380 infprintf (is, "%s", mips_cp0_names[GET_OP (l, RD)]);
1381 else
1382 infprintf (is, "$%d", GET_OP (l, RD));
1383 break;
1384
1385 case 'K':
1386 infprintf (is, "%s", mips_hwr_names[GET_OP (l, RD)]);
1387 break;
1388
1389 case 'N':
1390 infprintf (is,
1391 (opp->pinfo & (FP_D | FP_S)) != 0 ? "$fcc%d" : "$cc%d",
1392 GET_OP (l, BCC));
1393 break;
1394
1395 case 'M':
1396 infprintf (is, "$fcc%d", GET_OP (l, CCC));
1397 break;
1398
1399 case 'P':
1400 infprintf (is, "%d", GET_OP (l, PERFREG));
1401 break;
1402
1403 case 'e':
1404 infprintf (is, "%d", GET_OP (l, VECBYTE));
1405 break;
1406
1407 case '%':
1408 infprintf (is, "%d", GET_OP (l, VECALIGN));
1409 break;
1410
1411 case 'H':
1412 infprintf (is, "%d", GET_OP (l, SEL));
1413 break;
1414
1415 case 'O':
1416 infprintf (is, "%d", GET_OP (l, ALN));
1417 break;
1418
1419 case 'Q':
1420 {
1421 unsigned int vsel = GET_OP (l, VSEL);
1422
1423 if ((vsel & 0x10) == 0)
1424 {
1425 int fmt;
1426
1427 vsel &= 0x0f;
1428 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1429 if ((vsel & 1) == 0)
1430 break;
1431 infprintf (is, "$v%d[%d]", GET_OP (l, FT), vsel >> 1);
1432 }
1433 else if ((vsel & 0x08) == 0)
1434 {
1435 infprintf (is, "$v%d", GET_OP (l, FT));
1436 }
1437 else
1438 {
1439 infprintf (is, "0x%x", GET_OP (l, FT));
1440 }
1441 }
1442 break;
1443
1444 case 'X':
1445 infprintf (is, "$v%d", GET_OP (l, FD));
1446 break;
1447
1448 case 'Y':
1449 infprintf (is, "$v%d", GET_OP (l, FS));
1450 break;
1451
1452 case 'Z':
1453 infprintf (is, "$v%d", GET_OP (l, FT));
1454 break;
1455
1456 default:
1457 /* xgettext:c-format */
1458 infprintf (is, _("# internal error, undefined modifier (%c)"), *d);
1459 return;
1460 }
1461 }
1462 }
1463 \f
1464 /* Print the mips instruction at address MEMADDR in debugged memory,
1465 on using INFO. Returns length of the instruction, in bytes, which is
1466 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1467 this is little-endian code. */
1468
1469 static int
1470 print_insn_mips (bfd_vma memaddr,
1471 int word,
1472 struct disassemble_info *info)
1473 {
1474 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1475 const fprintf_ftype infprintf = info->fprintf_func;
1476 const struct mips_opcode *op;
1477 static bfd_boolean init = 0;
1478 void *is = info->stream;
1479
1480 /* Build a hash table to shorten the search time. */
1481 if (! init)
1482 {
1483 unsigned int i;
1484
1485 for (i = 0; i <= OP_MASK_OP; i++)
1486 {
1487 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1488 {
1489 if (op->pinfo == INSN_MACRO
1490 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1491 continue;
1492 if (i == GET_OP (op->match, OP))
1493 {
1494 mips_hash[i] = op;
1495 break;
1496 }
1497 }
1498 }
1499
1500 init = 1;
1501 }
1502
1503 info->bytes_per_chunk = INSNLEN;
1504 info->display_endian = info->endian;
1505 info->insn_info_valid = 1;
1506 info->branch_delay_insns = 0;
1507 info->data_size = 0;
1508 info->insn_type = dis_nonbranch;
1509 info->target = 0;
1510 info->target2 = 0;
1511
1512 op = mips_hash[GET_OP (word, OP)];
1513 if (op != NULL)
1514 {
1515 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1516 {
1517 if (op->pinfo != INSN_MACRO
1518 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1519 && (word & op->mask) == op->match)
1520 {
1521 const char *d;
1522
1523 /* We always allow to disassemble the jalx instruction. */
1524 if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
1525 && strcmp (op->name, "jalx"))
1526 continue;
1527
1528 /* Figure out instruction type and branch delay information. */
1529 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1530 {
1531 if ((op->pinfo & (INSN_WRITE_GPR_31
1532 | INSN_WRITE_GPR_D)) != 0)
1533 info->insn_type = dis_jsr;
1534 else
1535 info->insn_type = dis_branch;
1536 info->branch_delay_insns = 1;
1537 }
1538 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1539 | INSN_COND_BRANCH_LIKELY)) != 0)
1540 {
1541 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
1542 info->insn_type = dis_condjsr;
1543 else
1544 info->insn_type = dis_condbranch;
1545 info->branch_delay_insns = 1;
1546 }
1547 else if ((op->pinfo & (INSN_STORE_MEMORY
1548 | INSN_LOAD_MEMORY_DELAY)) != 0)
1549 info->insn_type = dis_dref;
1550
1551 infprintf (is, "%s", op->name);
1552
1553 d = op->args;
1554 if (d != NULL && *d != '\0')
1555 {
1556 infprintf (is, "\t");
1557 print_insn_args (d, word, memaddr, info, op);
1558 }
1559
1560 return INSNLEN;
1561 }
1562 }
1563 }
1564 #undef GET_OP_S
1565 #undef GET_OP
1566
1567 /* Handle undefined instructions. */
1568 info->insn_type = dis_noninsn;
1569 infprintf (is, "0x%x", word);
1570 return INSNLEN;
1571 }
1572 \f
1573 /* Disassemble an operand for a mips16 instruction. */
1574
1575 static void
1576 print_mips16_insn_arg (char type,
1577 const struct mips_opcode *op,
1578 int l,
1579 bfd_boolean use_extend,
1580 int extend,
1581 bfd_vma memaddr,
1582 struct disassemble_info *info)
1583 {
1584 const fprintf_ftype infprintf = info->fprintf_func;
1585 void *is = info->stream;
1586
1587 #define GET_OP(insn, field) \
1588 (((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
1589 #define GET_OP_S(insn, field) \
1590 ((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \
1591 - ((MIPS16OP_MASK_##field >> 1) + 1))
1592 switch (type)
1593 {
1594 case ',':
1595 case '(':
1596 case ')':
1597 infprintf (is, "%c", type);
1598 break;
1599
1600 case 'y':
1601 case 'w':
1602 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY)));
1603 break;
1604
1605 case 'x':
1606 case 'v':
1607 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX)));
1608 break;
1609
1610 case 'z':
1611 infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ)));
1612 break;
1613
1614 case 'Z':
1615 infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z)));
1616 break;
1617
1618 case '0':
1619 infprintf (is, "%s", mips_gpr_names[0]);
1620 break;
1621
1622 case 'S':
1623 infprintf (is, "%s", mips_gpr_names[29]);
1624 break;
1625
1626 case 'P':
1627 infprintf (is, "$pc");
1628 break;
1629
1630 case 'R':
1631 infprintf (is, "%s", mips_gpr_names[31]);
1632 break;
1633
1634 case 'X':
1635 infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]);
1636 break;
1637
1638 case 'Y':
1639 infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1640 break;
1641
1642 case '<':
1643 case '>':
1644 case '[':
1645 case ']':
1646 case '4':
1647 case '5':
1648 case 'H':
1649 case 'W':
1650 case 'D':
1651 case 'j':
1652 case '6':
1653 case '8':
1654 case 'V':
1655 case 'C':
1656 case 'U':
1657 case 'k':
1658 case 'K':
1659 case 'p':
1660 case 'q':
1661 case 'A':
1662 case 'B':
1663 case 'E':
1664 {
1665 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1666
1667 shift = 0;
1668 signedp = 0;
1669 extbits = 16;
1670 pcrel = 0;
1671 extu = 0;
1672 branch = 0;
1673 switch (type)
1674 {
1675 case '<':
1676 nbits = 3;
1677 immed = GET_OP (l, RZ);
1678 extbits = 5;
1679 extu = 1;
1680 break;
1681 case '>':
1682 nbits = 3;
1683 immed = GET_OP (l, RX);
1684 extbits = 5;
1685 extu = 1;
1686 break;
1687 case '[':
1688 nbits = 3;
1689 immed = GET_OP (l, RZ);
1690 extbits = 6;
1691 extu = 1;
1692 break;
1693 case ']':
1694 nbits = 3;
1695 immed = GET_OP (l, RX);
1696 extbits = 6;
1697 extu = 1;
1698 break;
1699 case '4':
1700 nbits = 4;
1701 immed = GET_OP (l, IMM4);
1702 signedp = 1;
1703 extbits = 15;
1704 break;
1705 case '5':
1706 nbits = 5;
1707 immed = GET_OP (l, IMM5);
1708 info->insn_type = dis_dref;
1709 info->data_size = 1;
1710 break;
1711 case 'H':
1712 nbits = 5;
1713 shift = 1;
1714 immed = GET_OP (l, IMM5);
1715 info->insn_type = dis_dref;
1716 info->data_size = 2;
1717 break;
1718 case 'W':
1719 nbits = 5;
1720 shift = 2;
1721 immed = GET_OP (l, IMM5);
1722 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1723 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1724 {
1725 info->insn_type = dis_dref;
1726 info->data_size = 4;
1727 }
1728 break;
1729 case 'D':
1730 nbits = 5;
1731 shift = 3;
1732 immed = GET_OP (l, IMM5);
1733 info->insn_type = dis_dref;
1734 info->data_size = 8;
1735 break;
1736 case 'j':
1737 nbits = 5;
1738 immed = GET_OP (l, IMM5);
1739 signedp = 1;
1740 break;
1741 case '6':
1742 nbits = 6;
1743 immed = GET_OP (l, IMM6);
1744 break;
1745 case '8':
1746 nbits = 8;
1747 immed = GET_OP (l, IMM8);
1748 break;
1749 case 'V':
1750 nbits = 8;
1751 shift = 2;
1752 immed = GET_OP (l, IMM8);
1753 /* FIXME: This might be lw, or it might be addiu to $sp or
1754 $pc. We assume it's load. */
1755 info->insn_type = dis_dref;
1756 info->data_size = 4;
1757 break;
1758 case 'C':
1759 nbits = 8;
1760 shift = 3;
1761 immed = GET_OP (l, IMM8);
1762 info->insn_type = dis_dref;
1763 info->data_size = 8;
1764 break;
1765 case 'U':
1766 nbits = 8;
1767 immed = GET_OP (l, IMM8);
1768 extu = 1;
1769 break;
1770 case 'k':
1771 nbits = 8;
1772 immed = GET_OP (l, IMM8);
1773 signedp = 1;
1774 break;
1775 case 'K':
1776 nbits = 8;
1777 shift = 3;
1778 immed = GET_OP (l, IMM8);
1779 signedp = 1;
1780 break;
1781 case 'p':
1782 nbits = 8;
1783 immed = GET_OP (l, IMM8);
1784 signedp = 1;
1785 pcrel = 1;
1786 branch = 1;
1787 break;
1788 case 'q':
1789 nbits = 11;
1790 immed = GET_OP (l, IMM11);
1791 signedp = 1;
1792 pcrel = 1;
1793 branch = 1;
1794 break;
1795 case 'A':
1796 nbits = 8;
1797 shift = 2;
1798 immed = GET_OP (l, IMM8);
1799 pcrel = 1;
1800 /* FIXME: This can be lw or la. We assume it is lw. */
1801 info->insn_type = dis_dref;
1802 info->data_size = 4;
1803 break;
1804 case 'B':
1805 nbits = 5;
1806 shift = 3;
1807 immed = GET_OP (l, IMM5);
1808 pcrel = 1;
1809 info->insn_type = dis_dref;
1810 info->data_size = 8;
1811 break;
1812 case 'E':
1813 nbits = 5;
1814 shift = 2;
1815 immed = GET_OP (l, IMM5);
1816 pcrel = 1;
1817 break;
1818 default:
1819 abort ();
1820 }
1821
1822 if (! use_extend)
1823 {
1824 if (signedp && immed >= (1 << (nbits - 1)))
1825 immed -= 1 << nbits;
1826 immed <<= shift;
1827 if ((type == '<' || type == '>' || type == '[' || type == ']')
1828 && immed == 0)
1829 immed = 8;
1830 }
1831 else
1832 {
1833 if (extbits == 16)
1834 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1835 else if (extbits == 15)
1836 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1837 else
1838 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1839 immed &= (1 << extbits) - 1;
1840 if (! extu && immed >= (1 << (extbits - 1)))
1841 immed -= 1 << extbits;
1842 }
1843
1844 if (! pcrel)
1845 infprintf (is, "%d", immed);
1846 else
1847 {
1848 bfd_vma baseaddr;
1849
1850 if (branch)
1851 {
1852 immed *= 2;
1853 baseaddr = memaddr + 2;
1854 }
1855 else if (use_extend)
1856 baseaddr = memaddr - 2;
1857 else
1858 {
1859 int status;
1860 bfd_byte buffer[2];
1861
1862 baseaddr = memaddr;
1863
1864 /* If this instruction is in the delay slot of a jr
1865 instruction, the base address is the address of the
1866 jr instruction. If it is in the delay slot of jalr
1867 instruction, the base address is the address of the
1868 jalr instruction. This test is unreliable: we have
1869 no way of knowing whether the previous word is
1870 instruction or data. */
1871 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1872 info);
1873 if (status == 0
1874 && (((info->endian == BFD_ENDIAN_BIG
1875 ? bfd_getb16 (buffer)
1876 : bfd_getl16 (buffer))
1877 & 0xf800) == 0x1800))
1878 baseaddr = memaddr - 4;
1879 else
1880 {
1881 status = (*info->read_memory_func) (memaddr - 2, buffer,
1882 2, info);
1883 if (status == 0
1884 && (((info->endian == BFD_ENDIAN_BIG
1885 ? bfd_getb16 (buffer)
1886 : bfd_getl16 (buffer))
1887 & 0xf81f) == 0xe800))
1888 baseaddr = memaddr - 2;
1889 }
1890 }
1891 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1892 if (pcrel && branch
1893 && info->flavour == bfd_target_unknown_flavour)
1894 /* For gdb disassembler, maintain odd address. */
1895 info->target |= 1;
1896 (*info->print_address_func) (info->target, info);
1897 }
1898 }
1899 break;
1900
1901 case 'a':
1902 {
1903 int jalx = l & 0x400;
1904
1905 if (! use_extend)
1906 extend = 0;
1907 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1908 if (!jalx && info->flavour == bfd_target_unknown_flavour)
1909 /* For gdb disassembler, maintain odd address. */
1910 l |= 1;
1911 }
1912 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1913 (*info->print_address_func) (info->target, info);
1914 break;
1915
1916 case 'l':
1917 case 'L':
1918 {
1919 int need_comma, amask, smask;
1920
1921 need_comma = 0;
1922
1923 l = GET_OP (l, IMM6);
1924
1925 amask = (l >> 3) & 7;
1926
1927 if (amask > 0 && amask < 5)
1928 {
1929 infprintf (is, "%s", mips_gpr_names[4]);
1930 if (amask > 1)
1931 infprintf (is, "-%s", mips_gpr_names[amask + 3]);
1932 need_comma = 1;
1933 }
1934
1935 smask = (l >> 1) & 3;
1936 if (smask == 3)
1937 {
1938 infprintf (is, "%s??", need_comma ? "," : "");
1939 need_comma = 1;
1940 }
1941 else if (smask > 0)
1942 {
1943 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]);
1944 if (smask > 1)
1945 infprintf (is, "-%s", mips_gpr_names[smask + 15]);
1946 need_comma = 1;
1947 }
1948
1949 if (l & 1)
1950 {
1951 infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]);
1952 need_comma = 1;
1953 }
1954
1955 if (amask == 5 || amask == 6)
1956 {
1957 infprintf (is, "%s$f0", need_comma ? "," : "");
1958 if (amask == 6)
1959 infprintf (is, "-$f1");
1960 }
1961 }
1962 break;
1963
1964 case 'm':
1965 case 'M':
1966 /* MIPS16e save/restore. */
1967 {
1968 int need_comma = 0;
1969 int amask, args, statics;
1970 int nsreg, smask;
1971 int framesz;
1972 int i, j;
1973
1974 l = l & 0x7f;
1975 if (use_extend)
1976 l |= extend << 16;
1977
1978 amask = (l >> 16) & 0xf;
1979 if (amask == MIPS16_ALL_ARGS)
1980 {
1981 args = 4;
1982 statics = 0;
1983 }
1984 else if (amask == MIPS16_ALL_STATICS)
1985 {
1986 args = 0;
1987 statics = 4;
1988 }
1989 else
1990 {
1991 args = amask >> 2;
1992 statics = amask & 3;
1993 }
1994
1995 if (args > 0) {
1996 infprintf (is, "%s", mips_gpr_names[4]);
1997 if (args > 1)
1998 infprintf (is, "-%s", mips_gpr_names[4 + args - 1]);
1999 need_comma = 1;
2000 }
2001
2002 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
2003 if (framesz == 0 && !use_extend)
2004 framesz = 128;
2005
2006 infprintf (is, "%s%d", need_comma ? "," : "", framesz);
2007
2008 if (l & 0x40) /* $ra */
2009 infprintf (is, ",%s", mips_gpr_names[31]);
2010
2011 nsreg = (l >> 24) & 0x7;
2012 smask = 0;
2013 if (l & 0x20) /* $s0 */
2014 smask |= 1 << 0;
2015 if (l & 0x10) /* $s1 */
2016 smask |= 1 << 1;
2017 if (nsreg > 0) /* $s2-$s8 */
2018 smask |= ((1 << nsreg) - 1) << 2;
2019
2020 /* Find first set static reg bit. */
2021 for (i = 0; i < 9; i++)
2022 {
2023 if (smask & (1 << i))
2024 {
2025 infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
2026 /* Skip over string of set bits. */
2027 for (j = i; smask & (2 << j); j++)
2028 continue;
2029 if (j > i)
2030 infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
2031 i = j + 1;
2032 }
2033 }
2034
2035 /* Statics $ax - $a3. */
2036 if (statics == 1)
2037 infprintf (is, ",%s", mips_gpr_names[7]);
2038 else if (statics > 0)
2039 infprintf (is, ",%s-%s",
2040 mips_gpr_names[7 - statics + 1],
2041 mips_gpr_names[7]);
2042 }
2043 break;
2044
2045 default:
2046 /* xgettext:c-format */
2047 infprintf (is,
2048 _("# internal disassembler error, "
2049 "unrecognised modifier (%c)"),
2050 type);
2051 abort ();
2052 }
2053 }
2054
2055 /* Disassemble mips16 instructions. */
2056
2057 static int
2058 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
2059 {
2060 const fprintf_ftype infprintf = info->fprintf_func;
2061 int status;
2062 bfd_byte buffer[2];
2063 int length;
2064 int insn;
2065 bfd_boolean use_extend;
2066 int extend = 0;
2067 const struct mips_opcode *op, *opend;
2068 void *is = info->stream;
2069
2070 info->bytes_per_chunk = 2;
2071 info->display_endian = info->endian;
2072 info->insn_info_valid = 1;
2073 info->branch_delay_insns = 0;
2074 info->data_size = 0;
2075 info->insn_type = dis_nonbranch;
2076 info->target = 0;
2077 info->target2 = 0;
2078
2079 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2080 if (status != 0)
2081 {
2082 (*info->memory_error_func) (status, memaddr, info);
2083 return -1;
2084 }
2085
2086 length = 2;
2087
2088 if (info->endian == BFD_ENDIAN_BIG)
2089 insn = bfd_getb16 (buffer);
2090 else
2091 insn = bfd_getl16 (buffer);
2092
2093 /* Handle the extend opcode specially. */
2094 use_extend = FALSE;
2095 if ((insn & 0xf800) == 0xf000)
2096 {
2097 use_extend = TRUE;
2098 extend = insn & 0x7ff;
2099
2100 memaddr += 2;
2101
2102 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2103 if (status != 0)
2104 {
2105 infprintf (is, "extend 0x%x", (unsigned int) extend);
2106 (*info->memory_error_func) (status, memaddr, info);
2107 return -1;
2108 }
2109
2110 if (info->endian == BFD_ENDIAN_BIG)
2111 insn = bfd_getb16 (buffer);
2112 else
2113 insn = bfd_getl16 (buffer);
2114
2115 /* Check for an extend opcode followed by an extend opcode. */
2116 if ((insn & 0xf800) == 0xf000)
2117 {
2118 infprintf (is, "extend 0x%x", (unsigned int) extend);
2119 info->insn_type = dis_noninsn;
2120 return length;
2121 }
2122
2123 length += 2;
2124 }
2125
2126 /* FIXME: Should probably use a hash table on the major opcode here. */
2127
2128 opend = mips16_opcodes + bfd_mips16_num_opcodes;
2129 for (op = mips16_opcodes; op < opend; op++)
2130 {
2131 if (op->pinfo != INSN_MACRO
2132 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2133 && (insn & op->mask) == op->match)
2134 {
2135 const char *s;
2136
2137 if (strchr (op->args, 'a') != NULL)
2138 {
2139 if (use_extend)
2140 {
2141 infprintf (is, "extend 0x%x", (unsigned int) extend);
2142 info->insn_type = dis_noninsn;
2143 return length - 2;
2144 }
2145
2146 use_extend = FALSE;
2147
2148 memaddr += 2;
2149
2150 status = (*info->read_memory_func) (memaddr, buffer, 2,
2151 info);
2152 if (status == 0)
2153 {
2154 use_extend = TRUE;
2155 if (info->endian == BFD_ENDIAN_BIG)
2156 extend = bfd_getb16 (buffer);
2157 else
2158 extend = bfd_getl16 (buffer);
2159 length += 2;
2160 }
2161 }
2162
2163 infprintf (is, "%s", op->name);
2164 if (op->args[0] != '\0')
2165 infprintf (is, "\t");
2166
2167 for (s = op->args; *s != '\0'; s++)
2168 {
2169 if (*s == ','
2170 && s[1] == 'w'
2171 && GET_OP (insn, RX) == GET_OP (insn, RY))
2172 {
2173 /* Skip the register and the comma. */
2174 ++s;
2175 continue;
2176 }
2177 if (*s == ','
2178 && s[1] == 'v'
2179 && GET_OP (insn, RZ) == GET_OP (insn, RX))
2180 {
2181 /* Skip the register and the comma. */
2182 ++s;
2183 continue;
2184 }
2185 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2186 info);
2187 }
2188
2189 /* Figure out branch instruction type and delay slot information. */
2190 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2191 info->branch_delay_insns = 1;
2192 if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
2193 | MIPS16_INSN_UNCOND_BRANCH)) != 0)
2194 {
2195 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2196 info->insn_type = dis_jsr;
2197 else
2198 info->insn_type = dis_branch;
2199 }
2200 else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
2201 info->insn_type = dis_condbranch;
2202
2203 return length;
2204 }
2205 }
2206 #undef GET_OP_S
2207 #undef GET_OP
2208
2209 if (use_extend)
2210 infprintf (is, "0x%x", extend | 0xf000);
2211 infprintf (is, "0x%x", insn);
2212 info->insn_type = dis_noninsn;
2213
2214 return length;
2215 }
2216
2217 /* Disassemble microMIPS instructions. */
2218
2219 static int
2220 print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
2221 {
2222 const fprintf_ftype infprintf = info->fprintf_func;
2223 const struct mips_opcode *op, *opend;
2224 unsigned int lsb, msbd, msb;
2225 void *is = info->stream;
2226 unsigned int regno;
2227 bfd_byte buffer[2];
2228 int lastregno = 0;
2229 int higher;
2230 int length;
2231 int status;
2232 int delta;
2233 int immed;
2234 int insn;
2235
2236 lsb = 0;
2237
2238 info->bytes_per_chunk = 2;
2239 info->display_endian = info->endian;
2240 info->insn_info_valid = 1;
2241 info->branch_delay_insns = 0;
2242 info->data_size = 0;
2243 info->insn_type = dis_nonbranch;
2244 info->target = 0;
2245 info->target2 = 0;
2246
2247 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
2248 if (status != 0)
2249 {
2250 (*info->memory_error_func) (status, memaddr, info);
2251 return -1;
2252 }
2253
2254 length = 2;
2255
2256 if (info->endian == BFD_ENDIAN_BIG)
2257 insn = bfd_getb16 (buffer);
2258 else
2259 insn = bfd_getl16 (buffer);
2260
2261 if ((insn & 0xfc00) == 0x7c00)
2262 {
2263 /* This is a 48-bit microMIPS instruction. */
2264 higher = insn;
2265
2266 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2267 if (status != 0)
2268 {
2269 infprintf (is, "micromips 0x%x", higher);
2270 (*info->memory_error_func) (status, memaddr + 2, info);
2271 return -1;
2272 }
2273 if (info->endian == BFD_ENDIAN_BIG)
2274 insn = bfd_getb16 (buffer);
2275 else
2276 insn = bfd_getl16 (buffer);
2277 higher = (higher << 16) | insn;
2278
2279 status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
2280 if (status != 0)
2281 {
2282 infprintf (is, "micromips 0x%x", higher);
2283 (*info->memory_error_func) (status, memaddr + 4, info);
2284 return -1;
2285 }
2286 if (info->endian == BFD_ENDIAN_BIG)
2287 insn = bfd_getb16 (buffer);
2288 else
2289 insn = bfd_getl16 (buffer);
2290 infprintf (is, "0x%x%04x (48-bit insn)", higher, insn);
2291
2292 info->insn_type = dis_noninsn;
2293 return 6;
2294 }
2295 else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000)
2296 {
2297 /* This is a 32-bit microMIPS instruction. */
2298 higher = insn;
2299
2300 status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
2301 if (status != 0)
2302 {
2303 infprintf (is, "micromips 0x%x", higher);
2304 (*info->memory_error_func) (status, memaddr + 2, info);
2305 return -1;
2306 }
2307
2308 if (info->endian == BFD_ENDIAN_BIG)
2309 insn = bfd_getb16 (buffer);
2310 else
2311 insn = bfd_getl16 (buffer);
2312
2313 insn = insn | (higher << 16);
2314
2315 length += 2;
2316 }
2317
2318 /* FIXME: Should probably use a hash table on the major opcode here. */
2319
2320 #define GET_OP(insn, field) \
2321 (((insn) >> MICROMIPSOP_SH_##field) & MICROMIPSOP_MASK_##field)
2322 #define GET_OP_S(insn, field) \
2323 ((GET_OP (insn, field) ^ ((MICROMIPSOP_MASK_##field >> 1) + 1)) \
2324 - ((MICROMIPSOP_MASK_##field >> 1) + 1))
2325 opend = micromips_opcodes + bfd_micromips_num_opcodes;
2326 for (op = micromips_opcodes; op < opend; op++)
2327 {
2328 if (op->pinfo != INSN_MACRO
2329 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
2330 && (insn & op->mask) == op->match
2331 && ((length == 2 && (op->mask & 0xffff0000) == 0)
2332 || (length == 4 && (op->mask & 0xffff0000) != 0)))
2333 {
2334 const char *s;
2335
2336 infprintf (is, "%s", op->name);
2337 if (op->args[0] != '\0')
2338 infprintf (is, "\t");
2339
2340 for (s = op->args; *s != '\0'; s++)
2341 {
2342 switch (*s)
2343 {
2344 case ',':
2345 case '(':
2346 case ')':
2347 infprintf (is, "%c", *s);
2348 break;
2349
2350 case '.':
2351 infprintf (is, "%d", GET_OP_S (insn, OFFSET10));
2352 break;
2353
2354 case '1':
2355 infprintf (is, "0x%x", GET_OP (insn, STYPE));
2356 break;
2357
2358 case '2':
2359 infprintf (is, "0x%x", GET_OP (insn, BP));
2360 break;
2361
2362 case '3':
2363 infprintf (is, "0x%x", GET_OP (insn, SA3));
2364 break;
2365
2366 case '4':
2367 infprintf (is, "0x%x", GET_OP (insn, SA4));
2368 break;
2369
2370 case '5':
2371 infprintf (is, "0x%x", GET_OP (insn, IMM8));
2372 break;
2373
2374 case '6':
2375 infprintf (is, "0x%x", GET_OP (insn, RS));
2376 break;
2377
2378 case '7':
2379 infprintf (is, "$ac%d", GET_OP (insn, DSPACC));
2380 break;
2381
2382 case '8':
2383 infprintf (is, "0x%x", GET_OP (insn, WRDSP));
2384 break;
2385
2386 case '0': /* DSP 6-bit signed immediate in bit 16. */
2387 delta = (GET_OP (insn, DSPSFT) ^ 0x20) - 0x20;
2388 infprintf (is, "%d", delta);
2389 break;
2390
2391 case '<':
2392 infprintf (is, "0x%x", GET_OP (insn, SHAMT));
2393 break;
2394
2395 case '\\':
2396 infprintf (is, "0x%x", GET_OP (insn, 3BITPOS));
2397 break;
2398
2399 case '^':
2400 infprintf (is, "0x%x", GET_OP (insn, RD));
2401 break;
2402
2403 case '|':
2404 infprintf (is, "0x%x", GET_OP (insn, TRAP));
2405 break;
2406
2407 case '~':
2408 infprintf (is, "%d", GET_OP_S (insn, OFFSET12));
2409 break;
2410
2411 case 'a':
2412 if (strcmp (op->name, "jalx") == 0)
2413 info->target = (((memaddr + 4) & ~(bfd_vma) 0x0fffffff)
2414 | (GET_OP (insn, TARGET) << 2));
2415 else
2416 info->target = (((memaddr + 4) & ~(bfd_vma) 0x07ffffff)
2417 | (GET_OP (insn, TARGET) << 1));
2418 /* For gdb disassembler, force odd address on jalx. */
2419 if (info->flavour == bfd_target_unknown_flavour
2420 && strcmp (op->name, "jalx") == 0)
2421 info->target |= 1;
2422 (*info->print_address_func) (info->target, info);
2423 break;
2424
2425 case 'b':
2426 case 'r':
2427 case 's':
2428 case 'v':
2429 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS)]);
2430 break;
2431
2432 case 'c':
2433 infprintf (is, "0x%x", GET_OP (insn, CODE));
2434 break;
2435
2436 case 'd':
2437 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RD)]);
2438 break;
2439
2440 case 'h':
2441 infprintf (is, "0x%x", GET_OP (insn, PREFX));
2442 break;
2443
2444 case 'i':
2445 case 'u':
2446 infprintf (is, "0x%x", GET_OP (insn, IMMEDIATE));
2447 break;
2448
2449 case 'j': /* Same as i, but sign-extended. */
2450 case 'o':
2451 infprintf (is, "%d", GET_OP_S (insn, DELTA));
2452 break;
2453
2454 case 'k':
2455 infprintf (is, "0x%x", GET_OP (insn, CACHE));
2456 break;
2457
2458 case 'n':
2459 {
2460 int s_reg_encode;
2461
2462 immed = GET_OP (insn, RT);
2463 s_reg_encode = immed & 0xf;
2464 if (s_reg_encode != 0)
2465 {
2466 if (s_reg_encode == 1)
2467 infprintf (is, "%s", mips_gpr_names[16]);
2468 else if (s_reg_encode < 9)
2469 infprintf (is, "%s-%s",
2470 mips_gpr_names[16],
2471 mips_gpr_names[15 + s_reg_encode]);
2472 else if (s_reg_encode == 9)
2473 infprintf (is, "%s-%s,%s",
2474 mips_gpr_names[16],
2475 mips_gpr_names[23],
2476 mips_gpr_names[30]);
2477 else
2478 infprintf (is, "UNKNOWN");
2479 }
2480
2481 if (immed & 0x10) /* For ra. */
2482 {
2483 if (s_reg_encode == 0)
2484 infprintf (is, "%s", mips_gpr_names[31]);
2485 else
2486 infprintf (is, ",%s", mips_gpr_names[31]);
2487 }
2488 break;
2489 }
2490
2491 case 'p':
2492 /* Sign-extend the displacement. */
2493 delta = GET_OP_S (insn, DELTA);
2494 info->target = (delta << 1) + memaddr + length;
2495 (*info->print_address_func) (info->target, info);
2496 break;
2497
2498 case 'q':
2499 infprintf (is, "0x%x", GET_OP (insn, CODE2));
2500 break;
2501
2502 case 't':
2503 case 'w':
2504 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RT)]);
2505 break;
2506
2507 case 'y':
2508 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, RS3)]);
2509 break;
2510
2511 case 'z':
2512 infprintf (is, "%s", mips_gpr_names[0]);
2513 break;
2514
2515 case '@': /* DSP 10-bit signed immediate in bit 16. */
2516 delta = (GET_OP (insn, IMM10) ^ 0x200) - 0x200;
2517 infprintf (is, "%d", delta);
2518 break;
2519
2520 case 'B':
2521 infprintf (is, "0x%x", GET_OP (insn, CODE10));
2522 break;
2523
2524 case 'C':
2525 infprintf (is, "0x%x", GET_OP (insn, COPZ));
2526 break;
2527
2528 case 'D':
2529 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FD)]);
2530 break;
2531
2532 case 'E':
2533 /* Coprocessor register for lwcN instructions, et al.
2534
2535 Note that there is no load/store cp0 instructions, and
2536 that FPU (cp1) instructions disassemble this field using
2537 'T' format. Therefore, until we gain understanding of
2538 cp2 register names, we can simply print the register
2539 numbers. */
2540 infprintf (is, "$%d", GET_OP (insn, RT));
2541 break;
2542
2543 case 'G':
2544 /* Coprocessor register for mtcN instructions, et al. Note
2545 that FPU (cp1) instructions disassemble this field using
2546 'S' format. Therefore, we only need to worry about cp0,
2547 cp2, and cp3.
2548 The microMIPS encoding does not have a coprocessor
2549 identifier field as such, so we must work out the
2550 coprocessor number by looking at the opcode. */
2551 switch (insn
2552 & ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT)
2553 | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)))
2554 {
2555 case 0x000000fc: /* mfc0 */
2556 case 0x000002fc: /* mtc0 */
2557 case 0x580000fc: /* dmfc0 */
2558 case 0x580002fc: /* dmtc0 */
2559 infprintf (is, "%s", mips_cp0_names[GET_OP (insn, RS)]);
2560 break;
2561 default:
2562 infprintf (is, "$%d", GET_OP (insn, RS));
2563 break;
2564 }
2565 break;
2566
2567 case 'H':
2568 infprintf (is, "%d", GET_OP (insn, SEL));
2569 break;
2570
2571 case 'K':
2572 infprintf (is, "%s", mips_hwr_names[GET_OP (insn, RS)]);
2573 break;
2574
2575 case 'M':
2576 infprintf (is, "$fcc%d", GET_OP (insn, CCC));
2577 break;
2578
2579 case 'N':
2580 infprintf (is,
2581 (op->pinfo & (FP_D | FP_S)) != 0
2582 ? "$fcc%d" : "$cc%d",
2583 GET_OP (insn, BCC));
2584 break;
2585
2586 case 'R':
2587 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FR)]);
2588 break;
2589
2590 case 'S':
2591 case 'V':
2592 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FS)]);
2593 break;
2594
2595 case 'T':
2596 infprintf (is, "%s", mips_fpr_names[GET_OP (insn, FT)]);
2597 break;
2598
2599 case '+':
2600 /* Extension character; switch for second char. */
2601 s++;
2602 switch (*s)
2603 {
2604 case 'A':
2605 lsb = GET_OP (insn, EXTLSB);
2606 infprintf (is, "0x%x", lsb);
2607 break;
2608
2609 case 'B':
2610 msb = GET_OP (insn, INSMSB);
2611 infprintf (is, "0x%x", msb - lsb + 1);
2612 break;
2613
2614 case 'C':
2615 case 'H':
2616 msbd = GET_OP (insn, EXTMSBD);
2617 infprintf (is, "0x%x", msbd + 1);
2618 break;
2619
2620 case 'D':
2621 {
2622 const struct mips_cp0sel_name *n;
2623 unsigned int cp0reg, sel;
2624
2625 cp0reg = GET_OP (insn, RS);
2626 sel = GET_OP (insn, SEL);
2627
2628 /* CP0 register including 'sel' code for mtcN
2629 (et al.), to be printed textually if known.
2630 If not known, print both CP0 register name and
2631 sel numerically since CP0 register with sel 0 may
2632 have a name unrelated to register being printed. */
2633 n = lookup_mips_cp0sel_name (mips_cp0sel_names,
2634 mips_cp0sel_names_len,
2635 cp0reg, sel);
2636 if (n != NULL)
2637 infprintf (is, "%s", n->name);
2638 else
2639 infprintf (is, "$%d,%d", cp0reg, sel);
2640 break;
2641 }
2642
2643 case 'E':
2644 lsb = GET_OP (insn, EXTLSB) + 32;
2645 infprintf (is, "0x%x", lsb);
2646 break;
2647
2648 case 'F':
2649 msb = GET_OP (insn, INSMSB) + 32;
2650 infprintf (is, "0x%x", msb - lsb + 1);
2651 break;
2652
2653 case 'G':
2654 msbd = GET_OP (insn, EXTMSBD) + 32;
2655 infprintf (is, "0x%x", msbd + 1);
2656 break;
2657
2658 default:
2659 /* xgettext:c-format */
2660 infprintf (is,
2661 _("# internal disassembler error, "
2662 "unrecognized modifier (+%c)"),
2663 *s);
2664 abort ();
2665 }
2666 break;
2667
2668 case 'm':
2669 /* Extension character; switch for second char. */
2670 s++;
2671 switch (*s)
2672 {
2673 case 'a': /* global pointer. */
2674 infprintf (is, "%s", mips_gpr_names[28]);
2675 break;
2676
2677 case 'b':
2678 regno = micromips_to_32_reg_b_map[GET_OP (insn, MB)];
2679 infprintf (is, "%s", mips_gpr_names[regno]);
2680 break;
2681
2682 case 'c':
2683 regno = micromips_to_32_reg_c_map[GET_OP (insn, MC)];
2684 infprintf (is, "%s", mips_gpr_names[regno]);
2685 break;
2686
2687 case 'd':
2688 regno = micromips_to_32_reg_d_map[GET_OP (insn, MD)];
2689 infprintf (is, "%s", mips_gpr_names[regno]);
2690 break;
2691
2692 case 'e':
2693 regno = micromips_to_32_reg_e_map[GET_OP (insn, ME)];
2694 infprintf (is, "%s", mips_gpr_names[regno]);
2695 break;
2696
2697 case 'f':
2698 /* Save lastregno for "mt" to print out later. */
2699 lastregno = micromips_to_32_reg_f_map[GET_OP (insn, MF)];
2700 infprintf (is, "%s", mips_gpr_names[lastregno]);
2701 break;
2702
2703 case 'g':
2704 regno = micromips_to_32_reg_g_map[GET_OP (insn, MG)];
2705 infprintf (is, "%s", mips_gpr_names[regno]);
2706 break;
2707
2708 case 'h':
2709 regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)];
2710 infprintf (is, "%s", mips_gpr_names[regno]);
2711 break;
2712
2713 case 'i':
2714 regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)];
2715 infprintf (is, "%s", mips_gpr_names[regno]);
2716 break;
2717
2718 case 'j':
2719 infprintf (is, "%s", mips_gpr_names[GET_OP (insn, MJ)]);
2720 break;
2721
2722 case 'l':
2723 regno = micromips_to_32_reg_l_map[GET_OP (insn, ML)];
2724 infprintf (is, "%s", mips_gpr_names[regno]);
2725 break;
2726
2727 case 'm':
2728 regno = micromips_to_32_reg_m_map[GET_OP (insn, MM)];
2729 infprintf (is, "%s", mips_gpr_names[regno]);
2730 break;
2731
2732 case 'n':
2733 regno = micromips_to_32_reg_n_map[GET_OP (insn, MN)];
2734 infprintf (is, "%s", mips_gpr_names[regno]);
2735 break;
2736
2737 case 'p':
2738 /* Save lastregno for "mt" to print out later. */
2739 lastregno = GET_OP (insn, MP);
2740 infprintf (is, "%s", mips_gpr_names[lastregno]);
2741 break;
2742
2743 case 'q':
2744 regno = micromips_to_32_reg_q_map[GET_OP (insn, MQ)];
2745 infprintf (is, "%s", mips_gpr_names[regno]);
2746 break;
2747
2748 case 'r': /* program counter. */
2749 infprintf (is, "$pc");
2750 break;
2751
2752 case 's': /* stack pointer. */
2753 lastregno = 29;
2754 infprintf (is, "%s", mips_gpr_names[29]);
2755 break;
2756
2757 case 't':
2758 infprintf (is, "%s", mips_gpr_names[lastregno]);
2759 break;
2760
2761 case 'z': /* $0. */
2762 infprintf (is, "%s", mips_gpr_names[0]);
2763 break;
2764
2765 case 'A':
2766 /* Sign-extend the immediate. */
2767 immed = GET_OP_S (insn, IMMA) << 2;
2768 infprintf (is, "%d", immed);
2769 break;
2770
2771 case 'B':
2772 immed = micromips_imm_b_map[GET_OP (insn, IMMB)];
2773 infprintf (is, "%d", immed);
2774 break;
2775
2776 case 'C':
2777 immed = micromips_imm_c_map[GET_OP (insn, IMMC)];
2778 infprintf (is, "0x%x", immed);
2779 break;
2780
2781 case 'D':
2782 /* Sign-extend the displacement. */
2783 delta = GET_OP_S (insn, IMMD);
2784 info->target = (delta << 1) + memaddr + length;
2785 (*info->print_address_func) (info->target, info);
2786 break;
2787
2788 case 'E':
2789 /* Sign-extend the displacement. */
2790 delta = GET_OP_S (insn, IMME);
2791 info->target = (delta << 1) + memaddr + length;
2792 (*info->print_address_func) (info->target, info);
2793 break;
2794
2795 case 'F':
2796 immed = GET_OP (insn, IMMF);
2797 infprintf (is, "0x%x", immed);
2798 break;
2799
2800 case 'G':
2801 immed = (insn >> MICROMIPSOP_SH_IMMG) + 1;
2802 immed = (immed & MICROMIPSOP_MASK_IMMG) - 1;
2803 infprintf (is, "%d", immed);
2804 break;
2805
2806 case 'H':
2807 immed = GET_OP (insn, IMMH) << 1;
2808 infprintf (is, "%d", immed);
2809 break;
2810
2811 case 'I':
2812 immed = (insn >> MICROMIPSOP_SH_IMMI) + 1;
2813 immed = (immed & MICROMIPSOP_MASK_IMMI) - 1;
2814 infprintf (is, "%d", immed);
2815 break;
2816
2817 case 'J':
2818 immed = GET_OP (insn, IMMJ) << 2;
2819 infprintf (is, "%d", immed);
2820 break;
2821
2822 case 'L':
2823 immed = GET_OP (insn, IMML);
2824 infprintf (is, "%d", immed);
2825 break;
2826
2827 case 'M':
2828 immed = (insn >> MICROMIPSOP_SH_IMMM) - 1;
2829 immed = (immed & MICROMIPSOP_MASK_IMMM) + 1;
2830 infprintf (is, "%d", immed);
2831 break;
2832
2833 case 'N':
2834 immed = GET_OP (insn, IMMN);
2835 if (immed == 0)
2836 infprintf (is, "%s,%s",
2837 mips_gpr_names[16],
2838 mips_gpr_names[31]);
2839 else
2840 infprintf (is, "%s-%s,%s",
2841 mips_gpr_names[16],
2842 mips_gpr_names[16 + immed],
2843 mips_gpr_names[31]);
2844 break;
2845
2846 case 'O':
2847 immed = GET_OP (insn, IMMO);
2848 infprintf (is, "0x%x", immed);
2849 break;
2850
2851 case 'P':
2852 immed = GET_OP (insn, IMMP) << 2;
2853 infprintf (is, "%d", immed);
2854 break;
2855
2856 case 'Q':
2857 /* Sign-extend the immediate. */
2858 immed = GET_OP_S (insn, IMMQ) << 2;
2859 infprintf (is, "%d", immed);
2860 break;
2861
2862 case 'U':
2863 immed = GET_OP (insn, IMMU) << 2;
2864 infprintf (is, "%d", immed);
2865 break;
2866
2867 case 'W':
2868 immed = GET_OP (insn, IMMW) << 2;
2869 infprintf (is, "%d", immed);
2870 break;
2871
2872 case 'X':
2873 /* Sign-extend the immediate. */
2874 immed = GET_OP_S (insn, IMMX);
2875 infprintf (is, "%d", immed);
2876 break;
2877
2878 case 'Y':
2879 /* Sign-extend the immediate. */
2880 immed = GET_OP_S (insn, IMMY) << 2;
2881 if ((unsigned int) (immed + 8) < 16)
2882 immed ^= 0x400;
2883 infprintf (is, "%d", immed);
2884 break;
2885
2886 default:
2887 /* xgettext:c-format */
2888 infprintf (is,
2889 _("# internal disassembler error, "
2890 "unrecognized modifier (m%c)"),
2891 *s);
2892 abort ();
2893 }
2894 break;
2895
2896 default:
2897 /* xgettext:c-format */
2898 infprintf (is,
2899 _("# internal disassembler error, "
2900 "unrecognized modifier (%c)"),
2901 *s);
2902 abort ();
2903 }
2904 }
2905
2906 /* Figure out instruction type and branch delay information. */
2907 if ((op->pinfo
2908 & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY)) != 0)
2909 info->branch_delay_insns = 1;
2910 if (((op->pinfo & INSN_UNCOND_BRANCH_DELAY)
2911 | (op->pinfo2 & INSN2_UNCOND_BRANCH)) != 0)
2912 {
2913 if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_GPR_T)) != 0)
2914 info->insn_type = dis_jsr;
2915 else
2916 info->insn_type = dis_branch;
2917 }
2918 else if (((op->pinfo & INSN_COND_BRANCH_DELAY)
2919 | (op->pinfo2 & INSN2_COND_BRANCH)) != 0)
2920 {
2921 if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
2922 info->insn_type = dis_condjsr;
2923 else
2924 info->insn_type = dis_condbranch;
2925 }
2926 else if ((op->pinfo
2927 & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
2928 info->insn_type = dis_dref;
2929
2930 return length;
2931 }
2932 }
2933 #undef GET_OP_S
2934 #undef GET_OP
2935
2936 infprintf (is, "0x%x", insn);
2937 info->insn_type = dis_noninsn;
2938
2939 return length;
2940 }
2941
2942 /* Return 1 if a symbol associated with the location being disassembled
2943 indicates a compressed (MIPS16 or microMIPS) mode. We iterate over
2944 all the symbols at the address being considered assuming if at least
2945 one of them indicates code compression, then such code has been
2946 genuinely produced here (other symbols could have been derived from
2947 function symbols defined elsewhere or could define data). Otherwise,
2948 return 0. */
2949
2950 static bfd_boolean
2951 is_compressed_mode_p (struct disassemble_info *info)
2952 {
2953 elf_symbol_type *symbol;
2954 int pos;
2955 int i;
2956
2957 for (i = 0; i < info->num_symbols; i++)
2958 {
2959 pos = info->symtab_pos + i;
2960
2961 if (bfd_asymbol_flavour (info->symtab[pos]) != bfd_target_elf_flavour)
2962 continue;
2963
2964 if (info->symtab[pos]->section != info->section)
2965 continue;
2966
2967 symbol = (elf_symbol_type *) info->symtab[pos];
2968 if ((!micromips_ase
2969 && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other))
2970 || (micromips_ase
2971 && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other)))
2972 return 1;
2973 }
2974
2975 return 0;
2976 }
2977
2978 /* In an environment where we do not know the symbol type of the
2979 instruction we are forced to assume that the low order bit of the
2980 instructions' address may mark it as a mips16 instruction. If we
2981 are single stepping, or the pc is within the disassembled function,
2982 this works. Otherwise, we need a clue. Sometimes. */
2983
2984 static int
2985 _print_insn_mips (bfd_vma memaddr,
2986 struct disassemble_info *info,
2987 enum bfd_endian endianness)
2988 {
2989 int (*print_insn_compr) (bfd_vma, struct disassemble_info *);
2990 bfd_byte buffer[INSNLEN];
2991 int status;
2992
2993 set_default_mips_dis_options (info);
2994 parse_mips_dis_options (info->disassembler_options);
2995
2996 if (info->mach == bfd_mach_mips16)
2997 return print_insn_mips16 (memaddr, info);
2998 if (info->mach == bfd_mach_mips_micromips)
2999 return print_insn_micromips (memaddr, info);
3000
3001 print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips;
3002
3003 #if 1
3004 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */
3005 /* Only a few tools will work this way. */
3006 if (memaddr & 0x01)
3007 return print_insn_compr (memaddr, info);
3008 #endif
3009
3010 #if SYMTAB_AVAILABLE
3011 if (is_compressed_mode_p (info))
3012 return print_insn_compr (memaddr, info);
3013 #endif
3014
3015 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
3016 if (status == 0)
3017 {
3018 int insn;
3019
3020 if (endianness == BFD_ENDIAN_BIG)
3021 insn = bfd_getb32 (buffer);
3022 else
3023 insn = bfd_getl32 (buffer);
3024
3025 return print_insn_mips (memaddr, insn, info);
3026 }
3027 else
3028 {
3029 (*info->memory_error_func) (status, memaddr, info);
3030 return -1;
3031 }
3032 }
3033
3034 int
3035 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
3036 {
3037 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
3038 }
3039
3040 int
3041 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
3042 {
3043 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
3044 }
3045 \f
3046 void
3047 print_mips_disassembler_options (FILE *stream)
3048 {
3049 unsigned int i;
3050
3051 fprintf (stream, _("\n\
3052 The following MIPS specific disassembler options are supported for use\n\
3053 with the -M switch (multiple options should be separated by commas):\n"));
3054
3055 fprintf (stream, _("\n\
3056 virt Recognize the virtualization ASE instructions.\n"));
3057
3058 fprintf (stream, _("\n\
3059 gpr-names=ABI Print GPR names according to specified ABI.\n\
3060 Default: based on binary being disassembled.\n"));
3061
3062 fprintf (stream, _("\n\
3063 fpr-names=ABI Print FPR names according to specified ABI.\n\
3064 Default: numeric.\n"));
3065
3066 fprintf (stream, _("\n\
3067 cp0-names=ARCH Print CP0 register names according to\n\
3068 specified architecture.\n\
3069 Default: based on binary being disassembled.\n"));
3070
3071 fprintf (stream, _("\n\
3072 hwr-names=ARCH Print HWR names according to specified \n\
3073 architecture.\n\
3074 Default: based on binary being disassembled.\n"));
3075
3076 fprintf (stream, _("\n\
3077 reg-names=ABI Print GPR and FPR names according to\n\
3078 specified ABI.\n"));
3079
3080 fprintf (stream, _("\n\
3081 reg-names=ARCH Print CP0 register and HWR names according to\n\
3082 specified architecture.\n"));
3083
3084 fprintf (stream, _("\n\
3085 For the options above, the following values are supported for \"ABI\":\n\
3086 "));
3087 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
3088 fprintf (stream, " %s", mips_abi_choices[i].name);
3089 fprintf (stream, _("\n"));
3090
3091 fprintf (stream, _("\n\
3092 For the options above, The following values are supported for \"ARCH\":\n\
3093 "));
3094 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
3095 if (*mips_arch_choices[i].name != '\0')
3096 fprintf (stream, " %s", mips_arch_choices[i].name);
3097 fprintf (stream, _("\n"));
3098
3099 fprintf (stream, _("\n"));
3100 }
GDB Binutils - Deliverables
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