opcodes/nios2-opc.c

   1 /* Altera Nios II opcode list.
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    Contributed by Nigel Gray (ngray@altera.com).
   4    Contributed by Mentor Graphics, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <stdio.h>
  25 #include "opcode/nios2.h"
  26
  27 /* Register string table */
  28
  29 const struct nios2_reg nios2_builtin_regs[] = {
  30   /* Standard register names.  */
  31   {"zero", 0, REG_NORMAL},
  32   {"at", 1, REG_NORMAL},                        /* assembler temporary */
  33   {"r2", 2, REG_NORMAL},
  34   {"r3", 3, REG_NORMAL},
  35   {"r4", 4, REG_NORMAL},
  36   {"r5", 5, REG_NORMAL},
  37   {"r6", 6, REG_NORMAL},
  38   {"r7", 7, REG_NORMAL},
  39   {"r8", 8, REG_NORMAL},
  40   {"r9", 9, REG_NORMAL},
  41   {"r10", 10, REG_NORMAL},
  42   {"r11", 11, REG_NORMAL},
  43   {"r12", 12, REG_NORMAL},
  44   {"r13", 13, REG_NORMAL},
  45   {"r14", 14, REG_NORMAL},
  46   {"r15", 15, REG_NORMAL},
  47   {"r16", 16, REG_NORMAL},
  48   {"r17", 17, REG_NORMAL},
  49   {"r18", 18, REG_NORMAL},
  50   {"r19", 19, REG_NORMAL},
  51   {"r20", 20, REG_NORMAL},
  52   {"r21", 21, REG_NORMAL},
  53   {"r22", 22, REG_NORMAL},
  54   {"r23", 23, REG_NORMAL},
  55   {"et", 24, REG_NORMAL},
  56   {"bt", 25, REG_NORMAL},
  57   {"gp", 26, REG_NORMAL},                       /* global pointer */
  58   {"sp", 27, REG_NORMAL},                       /* stack pointer */
  59   {"fp", 28, REG_NORMAL},                       /* frame pointer */
  60   {"ea", 29, REG_NORMAL},                       /* exception return address */
  61   {"sstatus", 30, REG_NORMAL},                  /* saved processor status */
  62   {"ra", 31, REG_NORMAL},                       /* return address */
  63
  64   /* Alternative names for special registers.  */
  65   {"r0", 0, REG_NORMAL},
  66   {"r1", 1, REG_NORMAL},
  67   {"r24", 24, REG_NORMAL},
  68   {"r25", 25, REG_NORMAL},
  69   {"r26", 26, REG_NORMAL},
  70   {"r27", 27, REG_NORMAL},
  71   {"r28", 28, REG_NORMAL},
  72   {"r29", 29, REG_NORMAL},
  73   {"r30", 30, REG_NORMAL},
  74   {"ba", 30, REG_NORMAL},                       /* breakpoint return address */
  75   {"r31", 31, REG_NORMAL},
  76
  77   /* Control register names.  */
  78   {"status", 0, REG_CONTROL},
  79   {"estatus", 1, REG_CONTROL},
  80   {"bstatus", 2, REG_CONTROL},
  81   {"ienable", 3, REG_CONTROL},
  82   {"ipending", 4, REG_CONTROL},
  83   {"cpuid", 5, REG_CONTROL},
  84   {"ctl6", 6, REG_CONTROL},
  85   {"exception", 7, REG_CONTROL},
  86   {"pteaddr", 8, REG_CONTROL},
  87   {"tlbacc", 9, REG_CONTROL},
  88   {"tlbmisc", 10, REG_CONTROL},
  89   {"eccinj", 11, REG_CONTROL},
  90   {"badaddr", 12, REG_CONTROL},
  91   {"config", 13, REG_CONTROL},
  92   {"mpubase", 14, REG_CONTROL},
  93   {"mpuacc", 15, REG_CONTROL},
  94   {"ctl16", 16, REG_CONTROL},
  95   {"ctl17", 17, REG_CONTROL},
  96   {"ctl18", 18, REG_CONTROL},
  97   {"ctl19", 19, REG_CONTROL},
  98   {"ctl20", 20, REG_CONTROL},
  99   {"ctl21", 21, REG_CONTROL},
 100   {"ctl22", 22, REG_CONTROL},
 101   {"ctl23", 23, REG_CONTROL},
 102   {"ctl24", 24, REG_CONTROL},
 103   {"ctl25", 25, REG_CONTROL},
 104   {"ctl26", 26, REG_CONTROL},
 105   {"ctl27", 27, REG_CONTROL},
 106   {"ctl28", 28, REG_CONTROL},
 107   {"ctl29", 29, REG_CONTROL},
 108   {"ctl30", 30, REG_CONTROL},
 109   {"ctl31", 31, REG_CONTROL},
 110
 111   /* Alternative names for special control registers.  */
 112   {"ctl0", 0, REG_CONTROL},
 113   {"ctl1", 1, REG_CONTROL},
 114   {"ctl2", 2, REG_CONTROL},
 115   {"ctl3", 3, REG_CONTROL},
 116   {"ctl4", 4, REG_CONTROL},
 117   {"ctl5", 5, REG_CONTROL},
 118   {"ctl7", 7, REG_CONTROL},
 119   {"ctl8", 8, REG_CONTROL},
 120   {"ctl9", 9, REG_CONTROL},
 121   {"ctl10", 10, REG_CONTROL},
 122   {"ctl11", 11, REG_CONTROL},
 123   {"ctl12", 12, REG_CONTROL},
 124   {"ctl13", 13, REG_CONTROL},
 125   {"ctl14", 14, REG_CONTROL},
 126   {"ctl15", 15, REG_CONTROL},
 127
 128   /* Coprocessor register names.  */
 129   {"c0", 0, REG_COPROCESSOR},
 130   {"c1", 1, REG_COPROCESSOR},
 131   {"c2", 2, REG_COPROCESSOR},
 132   {"c3", 3, REG_COPROCESSOR},
 133   {"c4", 4, REG_COPROCESSOR},
 134   {"c5", 5, REG_COPROCESSOR},
 135   {"c6", 6, REG_COPROCESSOR},
 136   {"c7", 7, REG_COPROCESSOR},
 137   {"c8", 8, REG_COPROCESSOR},
 138   {"c9", 9, REG_COPROCESSOR},
 139   {"c10", 10, REG_COPROCESSOR},
 140   {"c11", 11, REG_COPROCESSOR},
 141   {"c12", 12, REG_COPROCESSOR},
 142   {"c13", 13, REG_COPROCESSOR},
 143   {"c14", 14, REG_COPROCESSOR},
 144   {"c15", 15, REG_COPROCESSOR},
 145   {"c16", 16, REG_COPROCESSOR},
 146   {"c17", 17, REG_COPROCESSOR},
 147   {"c18", 18, REG_COPROCESSOR},
 148   {"c19", 19, REG_COPROCESSOR},
 149   {"c20", 20, REG_COPROCESSOR},
 150   {"c21", 21, REG_COPROCESSOR},
 151   {"c22", 22, REG_COPROCESSOR},
 152   {"c23", 23, REG_COPROCESSOR},
 153   {"c24", 24, REG_COPROCESSOR},
 154   {"c25", 25, REG_COPROCESSOR},
 155   {"c26", 26, REG_COPROCESSOR},
 156   {"c27", 27, REG_COPROCESSOR},
 157   {"c28", 28, REG_COPROCESSOR},
 158   {"c29", 29, REG_COPROCESSOR},
 159   {"c30", 30, REG_COPROCESSOR},
 160   {"c31", 31, REG_COPROCESSOR},
 161 };
 162
 163 #define NIOS2_NUM_REGS \
 164        ((sizeof nios2_builtin_regs) / (sizeof (nios2_builtin_regs[0])))
 165 const int nios2_num_builtin_regs = NIOS2_NUM_REGS;
 166
 167 /* This is not const in order to allow for dynamic extensions to the
 168    built-in instruction set.  */
 169 struct nios2_reg *nios2_regs = (struct nios2_reg *) nios2_builtin_regs;
 170 int nios2_num_regs = NIOS2_NUM_REGS;
 171 #undef NIOS2_NUM_REGS
 172
 173 /* This is the opcode table used by the Nios II GNU as, disassembler
 174    and GDB.  */
 175 const struct nios2_opcode nios2_r1_opcodes[] =
 176 {
 177   /* { name, args, args_test, num_args, size, format,
 178        match, mask, pinfo, overflow } */
 179   {"add", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 180    MATCH_R1_ADD, MASK_R1_ADD, 0, no_overflow},
 181   {"addi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 182    MATCH_R1_ADDI, MASK_R1_ADDI, 0, signed_immed16_overflow},
 183   {"and", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 184    MATCH_R1_AND, MASK_R1_AND, 0, no_overflow},
 185   {"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 186    MATCH_R1_ANDHI, MASK_R1_ANDHI, 0, unsigned_immed16_overflow},
 187   {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 188    MATCH_R1_ANDI, MASK_R1_ANDI, 0, unsigned_immed16_overflow},
 189   {"beq", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 190    MATCH_R1_BEQ, MASK_R1_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow},
 191   {"bge", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 192    MATCH_R1_BGE, MASK_R1_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow},
 193   {"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 194    MATCH_R1_BGEU, MASK_R1_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow},
 195   {"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 196    MATCH_R1_BGT, MASK_R1_BGT,
 197    NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
 198   {"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 199    MATCH_R1_BGTU, MASK_R1_BGTU,
 200    NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
 201   {"ble", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 202    MATCH_R1_BLE, MASK_R1_BLE,
 203    NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
 204   {"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 205    MATCH_R1_BLEU, MASK_R1_BLEU,
 206    NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
 207   {"blt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 208    MATCH_R1_BLT, MASK_R1_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow},
 209   {"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 210    MATCH_R1_BLTU, MASK_R1_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow},
 211   {"bne", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
 212    MATCH_R1_BNE, MASK_R1_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow},
 213   {"br", "o", "o,E", 1, 4, iw_i_type,
 214    MATCH_R1_BR, MASK_R1_BR, NIOS2_INSN_UBRANCH, branch_target_overflow},
 215   {"break", "j", "j,E", 1, 4, iw_r_type,
 216    MATCH_R1_BREAK, MASK_R1_BREAK, NIOS2_INSN_OPTARG, no_overflow},
 217   {"bret", "", "E", 0, 4, iw_r_type,
 218    MATCH_R1_BRET, MASK_R1_BRET, 0, no_overflow},
 219   {"call", "m", "m,E", 1, 4, iw_j_type,
 220    MATCH_R1_CALL, MASK_R1_CALL, NIOS2_INSN_CALL, call_target_overflow},
 221   {"callr", "s", "s,E", 1, 4, iw_r_type,
 222    MATCH_R1_CALLR, MASK_R1_CALLR, 0, no_overflow},
 223   {"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 224    MATCH_R1_CMPEQ, MASK_R1_CMPEQ, 0, no_overflow},
 225   {"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 226    MATCH_R1_CMPEQI, MASK_R1_CMPEQI, 0, signed_immed16_overflow},
 227   {"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 228    MATCH_R1_CMPGE, MASK_R1_CMPGE, 0, no_overflow},
 229   {"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 230    MATCH_R1_CMPGEI, MASK_R1_CMPGEI, 0, signed_immed16_overflow},
 231   {"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 232    MATCH_R1_CMPGEU, MASK_R1_CMPGEU, 0, no_overflow},
 233   {"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 234    MATCH_R1_CMPGEUI, MASK_R1_CMPGEUI, 0, unsigned_immed16_overflow},
 235   {"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 236    MATCH_R1_CMPGT, MASK_R1_CMPGT, NIOS2_INSN_MACRO, no_overflow},
 237   {"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 238    MATCH_R1_CMPGTI, MASK_R1_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow},
 239   {"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 240    MATCH_R1_CMPGTU, MASK_R1_CMPGTU, NIOS2_INSN_MACRO, no_overflow},
 241   {"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 242    MATCH_R1_CMPGTUI, MASK_R1_CMPGTUI,
 243    NIOS2_INSN_MACRO, unsigned_immed16_overflow},
 244   {"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 245    MATCH_R1_CMPLE, MASK_R1_CMPLE, NIOS2_INSN_MACRO, no_overflow},
 246   {"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 247    MATCH_R1_CMPLEI, MASK_R1_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow},
 248   {"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 249    MATCH_R1_CMPLEU, MASK_R1_CMPLEU, NIOS2_INSN_MACRO, no_overflow},
 250   {"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 251    MATCH_R1_CMPLEUI, MASK_R1_CMPLEUI,
 252    NIOS2_INSN_MACRO, unsigned_immed16_overflow},
 253   {"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 254    MATCH_R1_CMPLT, MASK_R1_CMPLT, 0, no_overflow},
 255   {"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 256    MATCH_R1_CMPLTI, MASK_R1_CMPLTI, 0, signed_immed16_overflow},
 257   {"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 258    MATCH_R1_CMPLTU, MASK_R1_CMPLTU, 0, no_overflow},
 259   {"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 260    MATCH_R1_CMPLTUI, MASK_R1_CMPLTUI, 0, unsigned_immed16_overflow},
 261   {"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 262    MATCH_R1_CMPNE, MASK_R1_CMPNE, 0, no_overflow},
 263   {"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 264    MATCH_R1_CMPNEI, MASK_R1_CMPNEI, 0, signed_immed16_overflow},
 265   {"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_custom_type,
 266    MATCH_R1_CUSTOM, MASK_R1_CUSTOM, 0, custom_opcode_overflow},
 267   {"div", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 268    MATCH_R1_DIV, MASK_R1_DIV, 0, no_overflow},
 269   {"divu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 270    MATCH_R1_DIVU, MASK_R1_DIVU, 0, no_overflow},
 271   {"eret", "", "E", 0, 4, iw_r_type,
 272    MATCH_R1_ERET, MASK_R1_ERET, 0, no_overflow},
 273   {"flushd", "i(s)", "i(s),E", 2, 4, iw_i_type,
 274    MATCH_R1_FLUSHD, MASK_R1_FLUSHD, 0, address_offset_overflow},
 275   {"flushda", "i(s)", "i(s),E", 2, 4, iw_i_type,
 276    MATCH_R1_FLUSHDA, MASK_R1_FLUSHDA, 0, address_offset_overflow},
 277   {"flushi", "s", "s,E", 1, 4, iw_r_type,
 278    MATCH_R1_FLUSHI, MASK_R1_FLUSHI, 0, no_overflow},
 279   {"flushp", "", "E", 0, 4, iw_r_type,
 280    MATCH_R1_FLUSHP, MASK_R1_FLUSHP, 0, no_overflow},
 281   {"initd", "i(s)", "i(s),E", 2, 4, iw_i_type,
 282    MATCH_R1_INITD, MASK_R1_INITD, 0, address_offset_overflow},
 283   {"initda", "i(s)", "i(s),E", 2, 4, iw_i_type,
 284    MATCH_R1_INITDA, MASK_R1_INITDA, 0, address_offset_overflow},
 285   {"initi", "s", "s,E", 1, 4, iw_r_type,
 286    MATCH_R1_INITI, MASK_R1_INITI, 0, no_overflow},
 287   {"jmp", "s", "s,E", 1, 4, iw_r_type,
 288    MATCH_R1_JMP, MASK_R1_JMP, 0, no_overflow},
 289   {"jmpi", "m", "m,E", 1, 4, iw_j_type,
 290    MATCH_R1_JMPI, MASK_R1_JMPI, 0, call_target_overflow},
 291   {"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 292    MATCH_R1_LDB, MASK_R1_LDB, 0, address_offset_overflow},
 293   {"ldbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 294    MATCH_R1_LDBIO, MASK_R1_LDBIO, 0, address_offset_overflow},
 295   {"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 296    MATCH_R1_LDBU, MASK_R1_LDBU, 0, address_offset_overflow},
 297   {"ldbuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 298    MATCH_R1_LDBUIO, MASK_R1_LDBUIO, 0, address_offset_overflow},
 299   {"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 300    MATCH_R1_LDH, MASK_R1_LDH, 0, address_offset_overflow},
 301   {"ldhio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 302    MATCH_R1_LDHIO, MASK_R1_LDHIO, 0, address_offset_overflow},
 303   {"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 304    MATCH_R1_LDHU, MASK_R1_LDHU, 0, address_offset_overflow},
 305   {"ldhuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 306    MATCH_R1_LDHUIO, MASK_R1_LDHUIO, 0, address_offset_overflow},
 307   {"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 308    MATCH_R1_LDW, MASK_R1_LDW, 0, address_offset_overflow},
 309   {"ldwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 310    MATCH_R1_LDWIO, MASK_R1_LDWIO, 0, address_offset_overflow},
 311   {"mov", "d,s", "d,s,E", 2, 4, iw_r_type,
 312    MATCH_R1_MOV, MASK_R1_MOV, NIOS2_INSN_MACRO_MOV, no_overflow},
 313   {"movhi", "t,u", "t,u,E", 2, 4, iw_i_type,
 314    MATCH_R1_MOVHI, MASK_R1_MOVHI,
 315    NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
 316   {"movi", "t,i", "t,i,E", 2, 4, iw_i_type,
 317    MATCH_R1_MOVI, MASK_R1_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow},
 318   {"movia", "t,o", "t,o,E", 2, 4, iw_i_type,
 319    MATCH_R1_ORHI, MASK_R1_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow},
 320   {"movui", "t,u", "t,u,E", 2, 4, iw_i_type,
 321    MATCH_R1_MOVUI, MASK_R1_MOVUI,
 322    NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
 323   {"mul", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 324    MATCH_R1_MUL, MASK_R1_MUL, 0, no_overflow},
 325   {"muli", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 326    MATCH_R1_MULI, MASK_R1_MULI, 0, signed_immed16_overflow},
 327   {"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 328    MATCH_R1_MULXSS, MASK_R1_MULXSS, 0, no_overflow},
 329   {"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 330    MATCH_R1_MULXSU, MASK_R1_MULXSU, 0, no_overflow},
 331   {"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 332    MATCH_R1_MULXUU, MASK_R1_MULXUU, 0, no_overflow},
 333   {"nextpc", "d", "d,E", 1, 4, iw_r_type,
 334    MATCH_R1_NEXTPC, MASK_R1_NEXTPC, 0, no_overflow},
 335   {"nop", "", "E", 0, 4, iw_r_type,
 336    MATCH_R1_NOP, MASK_R1_NOP, NIOS2_INSN_MACRO_MOV, no_overflow},
 337   {"nor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 338    MATCH_R1_NOR, MASK_R1_NOR, 0, no_overflow},
 339   {"or", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 340    MATCH_R1_OR, MASK_R1_OR, 0, no_overflow},
 341   {"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 342    MATCH_R1_ORHI, MASK_R1_ORHI, 0, unsigned_immed16_overflow},
 343   {"ori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 344    MATCH_R1_ORI, MASK_R1_ORI, 0, unsigned_immed16_overflow},
 345   {"rdctl", "d,c", "d,c,E", 2, 4, iw_r_type,
 346    MATCH_R1_RDCTL, MASK_R1_RDCTL, 0, no_overflow},
 347   {"rdprs", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 348    MATCH_R1_RDPRS, MASK_R1_RDPRS, 0, signed_immed16_overflow},
 349   {"ret", "", "E", 0, 4, iw_r_type,
 350    MATCH_R1_RET, MASK_R1_RET, 0, no_overflow},
 351   {"rol", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 352    MATCH_R1_ROL, MASK_R1_ROL, 0, no_overflow},
 353   {"roli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
 354    MATCH_R1_ROLI, MASK_R1_ROLI, 0, unsigned_immed5_overflow},
 355   {"ror", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 356    MATCH_R1_ROR, MASK_R1_ROR, 0, no_overflow},
 357   {"sll", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 358    MATCH_R1_SLL, MASK_R1_SLL, 0, no_overflow},
 359   {"slli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
 360    MATCH_R1_SLLI, MASK_R1_SLLI, 0, unsigned_immed5_overflow},
 361   {"sra", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 362    MATCH_R1_SRA, MASK_R1_SRA, 0, no_overflow},
 363   {"srai", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
 364    MATCH_R1_SRAI, MASK_R1_SRAI, 0, unsigned_immed5_overflow},
 365   {"srl", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 366    MATCH_R1_SRL, MASK_R1_SRL, 0, no_overflow},
 367   {"srli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
 368    MATCH_R1_SRLI, MASK_R1_SRLI, 0, unsigned_immed5_overflow},
 369   {"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 370    MATCH_R1_STB, MASK_R1_STB, 0, address_offset_overflow},
 371   {"stbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 372    MATCH_R1_STBIO, MASK_R1_STBIO, 0, address_offset_overflow},
 373   {"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 374    MATCH_R1_STH, MASK_R1_STH, 0, address_offset_overflow},
 375   {"sthio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 376    MATCH_R1_STHIO, MASK_R1_STHIO, 0, address_offset_overflow},
 377   {"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 378    MATCH_R1_STW, MASK_R1_STW, 0, address_offset_overflow},
 379   {"stwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
 380    MATCH_R1_STWIO, MASK_R1_STWIO, 0, address_offset_overflow},
 381   {"sub", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 382    MATCH_R1_SUB, MASK_R1_SUB, 0, no_overflow},
 383   {"subi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
 384    MATCH_R1_SUBI, MASK_R1_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow},
 385   {"sync", "", "E", 0, 4, iw_r_type,
 386    MATCH_R1_SYNC, MASK_R1_SYNC, 0, no_overflow},
 387   {"trap", "j", "j,E", 1, 4, iw_r_type,
 388    MATCH_R1_TRAP, MASK_R1_TRAP, NIOS2_INSN_OPTARG, no_overflow},
 389   {"wrctl", "c,s", "c,s,E", 2, 4, iw_r_type,
 390    MATCH_R1_WRCTL, MASK_R1_WRCTL, 0, no_overflow},
 391   {"wrprs", "d,s", "d,s,E", 2, 4, iw_r_type,
 392    MATCH_R1_WRPRS, MASK_R1_WRPRS, 0, no_overflow},
 393   {"xor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
 394    MATCH_R1_XOR, MASK_R1_XOR, 0, no_overflow},
 395   {"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 396    MATCH_R1_XORHI, MASK_R1_XORHI, 0, unsigned_immed16_overflow},
 397   {"xori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
 398    MATCH_R1_XORI, MASK_R1_XORI, 0, unsigned_immed16_overflow}
 399 };
 400
 401 #define NIOS2_NUM_OPCODES \
 402        ((sizeof nios2_r1_opcodes) / (sizeof (nios2_r1_opcodes[0])))
 403 const int nios2_num_r1_opcodes = NIOS2_NUM_OPCODES;
 404
 405 struct nios2_opcode *nios2_opcodes = (struct nios2_opcode *) nios2_r1_opcodes;
 406 int nios2_num_opcodes = NIOS2_NUM_OPCODES;
 407 #undef NIOS2_NUM_OPCODES