Remove support for the (deprecated) openrisc and or32 configurations and replace
[deliverable/binutils-gdb.git] / opcodes / or1k-dis.c
1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 - the resultant file is machine generated, cgen-dis.in isn't
6
7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
8 2008, 2010 Free Software Foundation, Inc.
9
10 This file is part of libopcodes.
11
12 This library is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 It is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software Foundation, Inc.,
24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25
26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
27 Keep that in mind. */
28
29 #include "sysdep.h"
30 #include <stdio.h>
31 #include "ansidecl.h"
32 #include "dis-asm.h"
33 #include "bfd.h"
34 #include "symcat.h"
35 #include "libiberty.h"
36 #include "or1k-desc.h"
37 #include "or1k-opc.h"
38 #include "opintl.h"
39
40 /* Default text to print if an instruction isn't recognized. */
41 #define UNKNOWN_INSN_MSG _("*unknown*")
42
43 static void print_normal
44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
45 static void print_address
46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
47 static void print_keyword
48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
49 static void print_insn_normal
50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
51 static int print_insn
52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
53 static int default_print_insn
54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
55 static int read_insn
56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
57 unsigned long *);
58 \f
59 /* -- disassembler routines inserted here. */
60
61
62 void or1k_cgen_print_operand
63 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
64
65 /* Main entry point for printing operands.
66 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
67 of dis-asm.h on cgen.h.
68
69 This function is basically just a big switch statement. Earlier versions
70 used tables to look up the function to use, but
71 - if the table contains both assembler and disassembler functions then
72 the disassembler contains much of the assembler and vice-versa,
73 - there's a lot of inlining possibilities as things grow,
74 - using a switch statement avoids the function call overhead.
75
76 This function could be moved into `print_insn_normal', but keeping it
77 separate makes clear the interface between `print_insn_normal' and each of
78 the handlers. */
79
80 void
81 or1k_cgen_print_operand (CGEN_CPU_DESC cd,
82 int opindex,
83 void * xinfo,
84 CGEN_FIELDS *fields,
85 void const *attrs ATTRIBUTE_UNUSED,
86 bfd_vma pc,
87 int length)
88 {
89 disassemble_info *info = (disassemble_info *) xinfo;
90
91 switch (opindex)
92 {
93 case OR1K_OPERAND_DISP26 :
94 print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
95 break;
96 case OR1K_OPERAND_RA :
97 print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r2, 0);
98 break;
99 case OR1K_OPERAND_RADF :
100 print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
101 break;
102 case OR1K_OPERAND_RASF :
103 print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r2, 0);
104 break;
105 case OR1K_OPERAND_RB :
106 print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r3, 0);
107 break;
108 case OR1K_OPERAND_RBDF :
109 print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
110 break;
111 case OR1K_OPERAND_RBSF :
112 print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r3, 0);
113 break;
114 case OR1K_OPERAND_RD :
115 print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r1, 0);
116 break;
117 case OR1K_OPERAND_RDDF :
118 print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
119 break;
120 case OR1K_OPERAND_RDSF :
121 print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r1, 0);
122 break;
123 case OR1K_OPERAND_SIMM16 :
124 print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
125 break;
126 case OR1K_OPERAND_SIMM16_SPLIT :
127 print_normal (cd, info, fields->f_simm16_split, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
128 break;
129 case OR1K_OPERAND_UIMM16 :
130 print_normal (cd, info, fields->f_uimm16, 0, pc, length);
131 break;
132 case OR1K_OPERAND_UIMM16_SPLIT :
133 print_normal (cd, info, fields->f_uimm16_split, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
134 break;
135 case OR1K_OPERAND_UIMM6 :
136 print_normal (cd, info, fields->f_uimm6, 0, pc, length);
137 break;
138
139 default :
140 /* xgettext:c-format */
141 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
142 opindex);
143 abort ();
144 }
145 }
146
147 cgen_print_fn * const or1k_cgen_print_handlers[] =
148 {
149 print_insn_normal,
150 };
151
152
153 void
154 or1k_cgen_init_dis (CGEN_CPU_DESC cd)
155 {
156 or1k_cgen_init_opcode_table (cd);
157 or1k_cgen_init_ibld_table (cd);
158 cd->print_handlers = & or1k_cgen_print_handlers[0];
159 cd->print_operand = or1k_cgen_print_operand;
160 }
161
162 \f
163 /* Default print handler. */
164
165 static void
166 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
167 void *dis_info,
168 long value,
169 unsigned int attrs,
170 bfd_vma pc ATTRIBUTE_UNUSED,
171 int length ATTRIBUTE_UNUSED)
172 {
173 disassemble_info *info = (disassemble_info *) dis_info;
174
175 /* Print the operand as directed by the attributes. */
176 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
177 ; /* nothing to do */
178 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
179 (*info->fprintf_func) (info->stream, "%ld", value);
180 else
181 (*info->fprintf_func) (info->stream, "0x%lx", value);
182 }
183
184 /* Default address handler. */
185
186 static void
187 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
188 void *dis_info,
189 bfd_vma value,
190 unsigned int attrs,
191 bfd_vma pc ATTRIBUTE_UNUSED,
192 int length ATTRIBUTE_UNUSED)
193 {
194 disassemble_info *info = (disassemble_info *) dis_info;
195
196 /* Print the operand as directed by the attributes. */
197 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
198 ; /* Nothing to do. */
199 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
200 (*info->print_address_func) (value, info);
201 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
202 (*info->print_address_func) (value, info);
203 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
204 (*info->fprintf_func) (info->stream, "%ld", (long) value);
205 else
206 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
207 }
208
209 /* Keyword print handler. */
210
211 static void
212 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
213 void *dis_info,
214 CGEN_KEYWORD *keyword_table,
215 long value,
216 unsigned int attrs ATTRIBUTE_UNUSED)
217 {
218 disassemble_info *info = (disassemble_info *) dis_info;
219 const CGEN_KEYWORD_ENTRY *ke;
220
221 ke = cgen_keyword_lookup_value (keyword_table, value);
222 if (ke != NULL)
223 (*info->fprintf_func) (info->stream, "%s", ke->name);
224 else
225 (*info->fprintf_func) (info->stream, "???");
226 }
227 \f
228 /* Default insn printer.
229
230 DIS_INFO is defined as `void *' so the disassembler needn't know anything
231 about disassemble_info. */
232
233 static void
234 print_insn_normal (CGEN_CPU_DESC cd,
235 void *dis_info,
236 const CGEN_INSN *insn,
237 CGEN_FIELDS *fields,
238 bfd_vma pc,
239 int length)
240 {
241 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
242 disassemble_info *info = (disassemble_info *) dis_info;
243 const CGEN_SYNTAX_CHAR_TYPE *syn;
244
245 CGEN_INIT_PRINT (cd);
246
247 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
248 {
249 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
250 {
251 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
252 continue;
253 }
254 if (CGEN_SYNTAX_CHAR_P (*syn))
255 {
256 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
257 continue;
258 }
259
260 /* We have an operand. */
261 or1k_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
262 fields, CGEN_INSN_ATTRS (insn), pc, length);
263 }
264 }
265 \f
266 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
267 the extract info.
268 Returns 0 if all is well, non-zero otherwise. */
269
270 static int
271 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
272 bfd_vma pc,
273 disassemble_info *info,
274 bfd_byte *buf,
275 int buflen,
276 CGEN_EXTRACT_INFO *ex_info,
277 unsigned long *insn_value)
278 {
279 int status = (*info->read_memory_func) (pc, buf, buflen, info);
280
281 if (status != 0)
282 {
283 (*info->memory_error_func) (status, pc, info);
284 return -1;
285 }
286
287 ex_info->dis_info = info;
288 ex_info->valid = (1 << buflen) - 1;
289 ex_info->insn_bytes = buf;
290
291 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
292 return 0;
293 }
294
295 /* Utility to print an insn.
296 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
297 The result is the size of the insn in bytes or zero for an unknown insn
298 or -1 if an error occurs fetching data (memory_error_func will have
299 been called). */
300
301 static int
302 print_insn (CGEN_CPU_DESC cd,
303 bfd_vma pc,
304 disassemble_info *info,
305 bfd_byte *buf,
306 unsigned int buflen)
307 {
308 CGEN_INSN_INT insn_value;
309 const CGEN_INSN_LIST *insn_list;
310 CGEN_EXTRACT_INFO ex_info;
311 int basesize;
312
313 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
314 basesize = cd->base_insn_bitsize < buflen * 8 ?
315 cd->base_insn_bitsize : buflen * 8;
316 insn_value = cgen_get_insn_value (cd, buf, basesize);
317
318
319 /* Fill in ex_info fields like read_insn would. Don't actually call
320 read_insn, since the incoming buffer is already read (and possibly
321 modified a la m32r). */
322 ex_info.valid = (1 << buflen) - 1;
323 ex_info.dis_info = info;
324 ex_info.insn_bytes = buf;
325
326 /* The instructions are stored in hash lists.
327 Pick the first one and keep trying until we find the right one. */
328
329 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
330 while (insn_list != NULL)
331 {
332 const CGEN_INSN *insn = insn_list->insn;
333 CGEN_FIELDS fields;
334 int length;
335 unsigned long insn_value_cropped;
336
337 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
338 /* Not needed as insn shouldn't be in hash lists if not supported. */
339 /* Supported by this cpu? */
340 if (! or1k_cgen_insn_supported (cd, insn))
341 {
342 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
343 continue;
344 }
345 #endif
346
347 /* Basic bit mask must be correct. */
348 /* ??? May wish to allow target to defer this check until the extract
349 handler. */
350
351 /* Base size may exceed this instruction's size. Extract the
352 relevant part from the buffer. */
353 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
354 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
355 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
356 info->endian == BFD_ENDIAN_BIG);
357 else
358 insn_value_cropped = insn_value;
359
360 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
361 == CGEN_INSN_BASE_VALUE (insn))
362 {
363 /* Printing is handled in two passes. The first pass parses the
364 machine insn and extracts the fields. The second pass prints
365 them. */
366
367 /* Make sure the entire insn is loaded into insn_value, if it
368 can fit. */
369 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
370 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
371 {
372 unsigned long full_insn_value;
373 int rc = read_insn (cd, pc, info, buf,
374 CGEN_INSN_BITSIZE (insn) / 8,
375 & ex_info, & full_insn_value);
376 if (rc != 0)
377 return rc;
378 length = CGEN_EXTRACT_FN (cd, insn)
379 (cd, insn, &ex_info, full_insn_value, &fields, pc);
380 }
381 else
382 length = CGEN_EXTRACT_FN (cd, insn)
383 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
384
385 /* Length < 0 -> error. */
386 if (length < 0)
387 return length;
388 if (length > 0)
389 {
390 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
391 /* Length is in bits, result is in bytes. */
392 return length / 8;
393 }
394 }
395
396 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
397 }
398
399 return 0;
400 }
401
402 /* Default value for CGEN_PRINT_INSN.
403 The result is the size of the insn in bytes or zero for an unknown insn
404 or -1 if an error occured fetching bytes. */
405
406 #ifndef CGEN_PRINT_INSN
407 #define CGEN_PRINT_INSN default_print_insn
408 #endif
409
410 static int
411 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
412 {
413 bfd_byte buf[CGEN_MAX_INSN_SIZE];
414 int buflen;
415 int status;
416
417 /* Attempt to read the base part of the insn. */
418 buflen = cd->base_insn_bitsize / 8;
419 status = (*info->read_memory_func) (pc, buf, buflen, info);
420
421 /* Try again with the minimum part, if min < base. */
422 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
423 {
424 buflen = cd->min_insn_bitsize / 8;
425 status = (*info->read_memory_func) (pc, buf, buflen, info);
426 }
427
428 if (status != 0)
429 {
430 (*info->memory_error_func) (status, pc, info);
431 return -1;
432 }
433
434 return print_insn (cd, pc, info, buf, buflen);
435 }
436
437 /* Main entry point.
438 Print one instruction from PC on INFO->STREAM.
439 Return the size of the instruction (in bytes). */
440
441 typedef struct cpu_desc_list
442 {
443 struct cpu_desc_list *next;
444 CGEN_BITSET *isa;
445 int mach;
446 int endian;
447 CGEN_CPU_DESC cd;
448 } cpu_desc_list;
449
450 int
451 print_insn_or1k (bfd_vma pc, disassemble_info *info)
452 {
453 static cpu_desc_list *cd_list = 0;
454 cpu_desc_list *cl = 0;
455 static CGEN_CPU_DESC cd = 0;
456 static CGEN_BITSET *prev_isa;
457 static int prev_mach;
458 static int prev_endian;
459 int length;
460 CGEN_BITSET *isa;
461 int mach;
462 int endian = (info->endian == BFD_ENDIAN_BIG
463 ? CGEN_ENDIAN_BIG
464 : CGEN_ENDIAN_LITTLE);
465 enum bfd_architecture arch;
466
467 /* ??? gdb will set mach but leave the architecture as "unknown" */
468 #ifndef CGEN_BFD_ARCH
469 #define CGEN_BFD_ARCH bfd_arch_or1k
470 #endif
471 arch = info->arch;
472 if (arch == bfd_arch_unknown)
473 arch = CGEN_BFD_ARCH;
474
475 /* There's no standard way to compute the machine or isa number
476 so we leave it to the target. */
477 #ifdef CGEN_COMPUTE_MACH
478 mach = CGEN_COMPUTE_MACH (info);
479 #else
480 mach = info->mach;
481 #endif
482
483 #ifdef CGEN_COMPUTE_ISA
484 {
485 static CGEN_BITSET *permanent_isa;
486
487 if (!permanent_isa)
488 permanent_isa = cgen_bitset_create (MAX_ISAS);
489 isa = permanent_isa;
490 cgen_bitset_clear (isa);
491 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
492 }
493 #else
494 isa = info->insn_sets;
495 #endif
496
497 /* If we've switched cpu's, try to find a handle we've used before */
498 if (cd
499 && (cgen_bitset_compare (isa, prev_isa) != 0
500 || mach != prev_mach
501 || endian != prev_endian))
502 {
503 cd = 0;
504 for (cl = cd_list; cl; cl = cl->next)
505 {
506 if (cgen_bitset_compare (cl->isa, isa) == 0 &&
507 cl->mach == mach &&
508 cl->endian == endian)
509 {
510 cd = cl->cd;
511 prev_isa = cd->isas;
512 break;
513 }
514 }
515 }
516
517 /* If we haven't initialized yet, initialize the opcode table. */
518 if (! cd)
519 {
520 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
521 const char *mach_name;
522
523 if (!arch_type)
524 abort ();
525 mach_name = arch_type->printable_name;
526
527 prev_isa = cgen_bitset_copy (isa);
528 prev_mach = mach;
529 prev_endian = endian;
530 cd = or1k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
531 CGEN_CPU_OPEN_BFDMACH, mach_name,
532 CGEN_CPU_OPEN_ENDIAN, prev_endian,
533 CGEN_CPU_OPEN_END);
534 if (!cd)
535 abort ();
536
537 /* Save this away for future reference. */
538 cl = xmalloc (sizeof (struct cpu_desc_list));
539 cl->cd = cd;
540 cl->isa = prev_isa;
541 cl->mach = mach;
542 cl->endian = endian;
543 cl->next = cd_list;
544 cd_list = cl;
545
546 or1k_cgen_init_dis (cd);
547 }
548
549 /* We try to have as much common code as possible.
550 But at this point some targets need to take over. */
551 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
552 but if not possible try to move this hook elsewhere rather than
553 have two hooks. */
554 length = CGEN_PRINT_INSN (cd, pc, info);
555 if (length > 0)
556 return length;
557 if (length < 0)
558 return -1;
559
560 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
561 return cd->default_insn_bitsize / 8;
562 }
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