opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
   3    2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "dis-asm.h"
  26 #include "elf-bfd.h"
  27 #include "elf32-ppc.h"
  28 #include "elf/ppc.h"
  29 #include "opintl.h"
  30 #include "opcode/ppc.h"
  31
  32 /* This file provides several disassembler functions, all of which use
  33    the disassembler interface defined in dis-asm.h.  Several functions
  34    are provided because this file handles disassembly for the PowerPC
  35    in both big and little endian mode and also for the POWER (RS/6000)
  36    chip.  */
  37 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  38                                ppc_cpu_t);
  39
  40 struct dis_private
  41 {
  42   /* Stash the result of parsing disassembler_options here.  */
  43   ppc_cpu_t dialect;
  44 } private;
  45
  46 #define POWERPC_DIALECT(INFO) \
  47   (((struct dis_private *) ((INFO)->private_data))->dialect)
  48
  49 struct ppc_mopt {
  50   const char *opt;
  51   ppc_cpu_t cpu;
  52   ppc_cpu_t sticky;
  53 };
  54
  55 struct ppc_mopt ppc_opts[] = {
  56   { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_403),
  57     0 },
  58   { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
  59     0 },
  60   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  61                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  62     0 },
  63   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  64                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  65     0 },
  66   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
  67                 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  68     0 },
  69   { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_601),
  70     0 },
  71   { "603",     (PPC_OPCODE_PPC),
  72     0 },
  73   { "604",     (PPC_OPCODE_PPC),
  74     0 },
  75   { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_64),
  76     0 },
  77   { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  78     0 },
  79   { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  80     0 },
  81   { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  82     0 },
  83   { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  84     0 },
  85   { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
  86     , 0 },
  87   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
  88                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
  89                 | PPC_OPCODE_A2),
  90     0 },
  91   { "altivec", (PPC_OPCODE_PPC),
  92     PPC_OPCODE_ALTIVEC },
  93   { "any",     0,
  94     PPC_OPCODE_ANY },
  95   { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
  96     0 },
  97   { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
  98     0 },
  99   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 100                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 101     0 },
 102   { "com",     (PPC_OPCODE_COMMON),
 103     0 },
 104   { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_E300),
 105     0 },
 106   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 107                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 108                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 109                 | PPC_OPCODE_E500),
 110     0 },
 111   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 112                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 113                 | PPC_OPCODE_E500MC),
 114     0 },
 115   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 116                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 117                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 118                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 119     0 },
 120   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 121                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 122                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 123                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 124                 | PPC_OPCODE_POWER7),
 125     0 },
 126   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 127                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 128                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 129                 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
 130                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 131     0 },
 132   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 133                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 134                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 135                 | PPC_OPCODE_E500),
 136     0 },
 137   { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 138     0 },
 139   { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 140     0 },
 141   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 142                 | PPC_OPCODE_POWER5),
 143     0 },
 144   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 145                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 146     0 },
 147   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 148                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 149                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 150     0 },
 151   { "ppc",     (PPC_OPCODE_PPC),
 152     0 },
 153   { "ppc32",   (PPC_OPCODE_PPC),
 154     0 },
 155   { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_64),
 156     0 },
 157   { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
 158     0 },
 159   { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
 160     0 },
 161   { "pwr",     (PPC_OPCODE_POWER),
 162     0 },
 163   { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 164     0 },
 165   { "pwr4",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 166     0 },
 167   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 168                 | PPC_OPCODE_POWER5),
 169     0 },
 170   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 171                 | PPC_OPCODE_POWER5),
 172     0 },
 173   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 174                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 175     0 },
 176   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 177                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 178                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 179     0 },
 180   { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 181     0 },
 182   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 183     PPC_OPCODE_SPE },
 184   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 185                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 186     0 },
 187   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
 188     PPC_OPCODE_VLE },
 189   { "vsx",     (PPC_OPCODE_PPC),
 190     PPC_OPCODE_VSX },
 191 };
 192
 193 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 194 static ppc_cpu_t
 195 get_powerpc_dialect (struct disassemble_info *info)
 196 {
 197   ppc_cpu_t dialect = 0;
 198
 199   dialect = POWERPC_DIALECT (info);
 200
 201   /* Disassemble according to the section headers flags for VLE-mode.  */
 202   if (dialect & PPC_OPCODE_VLE
 203       && is_ppc_vle (info->section))
 204     return dialect;
 205   else
 206     return dialect & ~ PPC_OPCODE_VLE;
 207 }
 208
 209 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 210
 211 ppc_cpu_t
 212 ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg)
 213 {
 214   const ppc_cpu_t retain_mask = (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
 215                                  | PPC_OPCODE_SPE | PPC_OPCODE_ANY
 216                                  | PPC_OPCODE_VLE | PPC_OPCODE_PMR);
 217   /* Sticky bits.  */
 218   ppc_cpu_t retain_flags = ppc_cpu & retain_mask;
 219   unsigned int i;
 220
 221   for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 222     if (strcmp (ppc_opts[i].opt, arg) == 0)
 223       {
 224         if (ppc_opts[i].sticky)
 225           {
 226             retain_flags |= ppc_opts[i].sticky;
 227             if ((ppc_cpu & ~retain_mask) != 0)
 228               break;
 229           }
 230         ppc_cpu = ppc_opts[i].cpu;
 231         break;
 232       }
 233   if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
 234     return 0;
 235
 236   ppc_cpu |= retain_flags;
 237   return ppc_cpu;
 238 }
 239
 240 /* Determine which set of machines to disassemble for.  */
 241
 242 static void
 243 powerpc_init_dialect (struct disassemble_info *info)
 244 {
 245   ppc_cpu_t dialect = 0;
 246   char *arg;
 247   struct dis_private *priv = calloc (sizeof (*priv), 1);
 248
 249   if (priv == NULL)
 250     priv = &private;
 251
 252   arg = info->disassembler_options;
 253   while (arg != NULL)
 254     {
 255       ppc_cpu_t new_cpu = 0;
 256       char *end = strchr (arg, ',');
 257
 258       if (end != NULL)
 259         *end = 0;
 260
 261       if ((new_cpu = ppc_parse_cpu (dialect, arg)) != 0)
 262         dialect = new_cpu;
 263       else if (strcmp (arg, "32") == 0)
 264         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 265       else if (strcmp (arg, "64") == 0)
 266         dialect |= PPC_OPCODE_64;
 267       else
 268         fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
 269
 270       if (end != NULL)
 271         *end++ = ',';
 272       arg = end;
 273     }
 274
 275   if ((dialect & ~(ppc_cpu_t) PPC_OPCODE_64) == 0)
 276     {
 277       if (info->mach == bfd_mach_ppc64)
 278         dialect |= PPC_OPCODE_64;
 279       else
 280         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 281       if (info->mach == bfd_mach_ppc_vle)
 282         dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE;
 283       else
 284         /* Choose a reasonable default.  */
 285         dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
 286                     | PPC_OPCODE_ALTIVEC);
 287     }
 288
 289   info->private_data = priv;
 290   POWERPC_DIALECT(info) = dialect;
 291 }
 292
 293 #define PPC_OPCD_SEGS 64
 294 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 295 #define VLE_OPCD_SEGS 32
 296 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 297
 298 /* Calculate opcode table indices to speed up disassembly,
 299    and init dialect.  */
 300
 301 void
 302 disassemble_init_powerpc (struct disassemble_info *info)
 303 {
 304   int i;
 305   unsigned short last;
 306
 307   i = powerpc_num_opcodes;
 308   while (--i >= 0)
 309     {
 310       unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 311
 312       powerpc_opcd_indices[op] = i;
 313     }
 314
 315   last = powerpc_num_opcodes;
 316   for (i = PPC_OPCD_SEGS; i > 0; --i)
 317     {
 318       if (powerpc_opcd_indices[i] == 0)
 319         powerpc_opcd_indices[i] = last;
 320       last = powerpc_opcd_indices[i];
 321     }
 322
 323   i = vle_num_opcodes;
 324   while (--i >= 0)
 325     {
 326       unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 327       unsigned seg = VLE_OP_TO_SEG (op);
 328
 329       vle_opcd_indices[seg] = i;
 330     }
 331
 332   last = vle_num_opcodes;
 333   for (i = VLE_OPCD_SEGS; i > 0; --i)
 334     {
 335       if (vle_opcd_indices[i] == 0)
 336         vle_opcd_indices[i] = last;
 337       last = vle_opcd_indices[i];
 338     }
 339
 340   if (info->arch == bfd_arch_powerpc)
 341     powerpc_init_dialect (info);
 342 }
 343
 344 /* Print a big endian PowerPC instruction.  */
 345
 346 int
 347 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 348 {
 349   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 350 }
 351
 352 /* Print a little endian PowerPC instruction.  */
 353
 354 int
 355 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 356 {
 357   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 358 }
 359
 360 /* Print a POWER (RS/6000) instruction.  */
 361
 362 int
 363 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 364 {
 365   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 366 }
 367
 368 /* Extract the operand value from the PowerPC or POWER instruction.  */
 369
 370 static long
 371 operand_value_powerpc (const struct powerpc_operand *operand,
 372                        unsigned long insn, ppc_cpu_t dialect)
 373 {
 374   long value;
 375   int invalid;
 376   /* Extract the value from the instruction.  */
 377   if (operand->extract)
 378     value = (*operand->extract) (insn, dialect, &invalid);
 379   else
 380     {
 381       if (operand->shift >= 0)
 382         value = (insn >> operand->shift) & operand->bitm;
 383       else
 384         value = (insn << -operand->shift) & operand->bitm;
 385       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 386         {
 387           /* BITM is always some number of zeros followed by some
 388              number of ones, followed by some number of zeros.  */
 389           unsigned long top = operand->bitm;
 390           /* top & -top gives the rightmost 1 bit, so this
 391              fills in any trailing zeros.  */
 392           top |= (top & -top) - 1;
 393           top &= ~(top >> 1);
 394           value = (value ^ top) - top;
 395         }
 396     }
 397
 398   return value;
 399 }
 400
 401 /* Determine whether the optional operand(s) should be printed.  */
 402
 403 static int
 404 skip_optional_operands (const unsigned char *opindex,
 405                         unsigned long insn, ppc_cpu_t dialect)
 406 {
 407   const struct powerpc_operand *operand;
 408
 409   for (; *opindex != 0; opindex++)
 410     {
 411       operand = &powerpc_operands[*opindex];
 412       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 413           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 414               && operand_value_powerpc (operand, insn, dialect) != 0))
 415         return 0;
 416     }
 417
 418   return 1;
 419 }
 420
 421 /* Find a match for INSN in the opcode table, given machine DIALECT.
 422    A DIALECT of -1 is special, matching all machine opcode variations.  */
 423
 424 static const struct powerpc_opcode *
 425 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
 426 {
 427   const struct powerpc_opcode *opcode;
 428   const struct powerpc_opcode *opcode_end;
 429   unsigned long op;
 430
 431   /* Get the major opcode of the instruction.  */
 432   op = PPC_OP (insn);
 433
 434   /* Find the first match in the opcode table for this major opcode.  */
 435   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 436   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 437        opcode < opcode_end;
 438        ++opcode)
 439     {
 440       const unsigned char *opindex;
 441       const struct powerpc_operand *operand;
 442       int invalid;
 443
 444       if ((insn & opcode->mask) != opcode->opcode
 445           || (dialect != (ppc_cpu_t) -1
 446               && ((opcode->flags & dialect) == 0
 447                   || (opcode->deprecated & dialect) != 0)))
 448         continue;
 449
 450       /* Check validity of operands.  */
 451       invalid = 0;
 452       for (opindex = opcode->operands; *opindex != 0; opindex++)
 453         {
 454           operand = powerpc_operands + *opindex;
 455           if (operand->extract)
 456             (*operand->extract) (insn, dialect, &invalid);
 457         }
 458       if (invalid)
 459         continue;
 460
 461       return opcode;
 462     }
 463
 464   return NULL;
 465 }
 466
 467 /* Find a match for INSN in the VLE opcode table.  */
 468
 469 static const struct powerpc_opcode *
 470 lookup_vle (unsigned long insn)
 471 {
 472   const struct powerpc_opcode *opcode;
 473   const struct powerpc_opcode *opcode_end;
 474   unsigned op, seg;
 475
 476   op = PPC_OP (insn);
 477   if (op >= 0x20 && op <= 0x37)
 478     {
 479       /* This insn has a 4-bit opcode.  */
 480       op &= 0x3c;
 481     }
 482   seg = VLE_OP_TO_SEG (op);
 483
 484   /* Find the first match in the opcode table for this major opcode.  */
 485   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 486   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 487        opcode < opcode_end;
 488        ++opcode)
 489     {
 490       unsigned long table_opcd = opcode->opcode;
 491       unsigned long table_mask = opcode->mask;
 492       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 493       unsigned long insn2;
 494       const unsigned char *opindex;
 495       const struct powerpc_operand *operand;
 496       int invalid;
 497
 498       insn2 = insn;
 499       if (table_op_is_short)
 500         insn2 >>= 16;
 501       if ((insn2 & table_mask) != table_opcd)
 502         continue;
 503
 504       /* Check validity of operands.  */
 505       invalid = 0;
 506       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 507         {
 508           operand = powerpc_operands + *opindex;
 509           if (operand->extract)
 510             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 511         }
 512       if (invalid)
 513         continue;
 514
 515       return opcode;
 516     }
 517
 518   return NULL;
 519 }
 520
 521 /* Print a PowerPC or POWER instruction.  */
 522
 523 static int
 524 print_insn_powerpc (bfd_vma memaddr,
 525                     struct disassemble_info *info,
 526                     int bigendian,
 527                     ppc_cpu_t dialect)
 528 {
 529   bfd_byte buffer[4];
 530   int status;
 531   unsigned long insn;
 532   const struct powerpc_opcode *opcode;
 533   bfd_boolean insn_is_short;
 534
 535   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 536   if (status != 0)
 537     {
 538       /* The final instruction may be a 2-byte VLE insn.  */
 539       if ((dialect & PPC_OPCODE_VLE) != 0)
 540         {
 541           /* Clear buffer so unused bytes will not have garbage in them.  */
 542           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 543           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 544           if (status != 0)
 545             {
 546               (*info->memory_error_func) (status, memaddr, info);
 547               return -1;
 548             }
 549         }
 550       else
 551         {
 552           (*info->memory_error_func) (status, memaddr, info);
 553           return -1;
 554         }
 555     }
 556
 557   if (bigendian)
 558     insn = bfd_getb32 (buffer);
 559   else
 560     insn = bfd_getl32 (buffer);
 561
 562   /* Get the major opcode of the insn.  */
 563   opcode = NULL;
 564   insn_is_short = FALSE;
 565   if ((dialect & PPC_OPCODE_VLE) != 0)
 566     {
 567       opcode = lookup_vle (insn);
 568       if (opcode != NULL)
 569         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 570     }
 571   if (opcode == NULL)
 572     opcode = lookup_powerpc (insn, dialect);
 573   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 574     opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
 575
 576   if (opcode != NULL)
 577     {
 578       const unsigned char *opindex;
 579       const struct powerpc_operand *operand;
 580       int need_comma;
 581       int need_paren;
 582       int skip_optional;
 583
 584       if (opcode->operands[0] != 0)
 585         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 586       else
 587         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 588
 589       if (insn_is_short)
 590         /* The operands will be fetched out of the 16-bit instruction.  */
 591         insn >>= 16;
 592
 593       /* Now extract and print the operands.  */
 594       need_comma = 0;
 595       need_paren = 0;
 596       skip_optional = -1;
 597       for (opindex = opcode->operands; *opindex != 0; opindex++)
 598         {
 599           long value;
 600
 601           operand = powerpc_operands + *opindex;
 602
 603           /* Operands that are marked FAKE are simply ignored.  We
 604              already made sure that the extract function considered
 605              the instruction to be valid.  */
 606           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 607             continue;
 608
 609           /* If all of the optional operands have the value zero,
 610              then don't print any of them.  */
 611           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 612             {
 613               if (skip_optional < 0)
 614                 skip_optional = skip_optional_operands (opindex, insn,
 615                                                         dialect);
 616               if (skip_optional)
 617                 continue;
 618             }
 619
 620           value = operand_value_powerpc (operand, insn, dialect);
 621
 622           if (need_comma)
 623             {
 624               (*info->fprintf_func) (info->stream, ",");
 625               need_comma = 0;
 626             }
 627
 628           /* Print the operand as directed by the flags.  */
 629           if ((operand->flags & PPC_OPERAND_GPR) != 0
 630               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 631             (*info->fprintf_func) (info->stream, "r%ld", value);
 632           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 633             (*info->fprintf_func) (info->stream, "f%ld", value);
 634           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 635             (*info->fprintf_func) (info->stream, "v%ld", value);
 636           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 637             (*info->fprintf_func) (info->stream, "vs%ld", value);
 638           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 639             (*info->print_address_func) (memaddr + value, info);
 640           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 641             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 642           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 643             (*info->fprintf_func) (info->stream, "fsl%ld", value);
 644           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 645             (*info->fprintf_func) (info->stream, "fcr%ld", value);
 646           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 647             (*info->fprintf_func) (info->stream, "%ld", value);
 648           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 649                    && (((dialect & PPC_OPCODE_PPC) != 0)
 650                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 651             (*info->fprintf_func) (info->stream, "cr%ld", value);
 652           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 653                    && (((dialect & PPC_OPCODE_PPC) != 0)
 654                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 655             {
 656               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 657               int cr;
 658               int cc;
 659
 660               cr = value >> 2;
 661               if (cr != 0)
 662                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 663               cc = value & 3;
 664               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 665             }
 666           else
 667             (*info->fprintf_func) (info->stream, "%d", value);
 668
 669           if (need_paren)
 670             {
 671               (*info->fprintf_func) (info->stream, ")");
 672               need_paren = 0;
 673             }
 674
 675           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 676             need_comma = 1;
 677           else
 678             {
 679               (*info->fprintf_func) (info->stream, "(");
 680               need_paren = 1;
 681             }
 682         }
 683
 684       /* We have found and printed an instruction.
 685          If it was a short VLE instruction we have more to do.  */
 686       if (insn_is_short)
 687         {
 688           memaddr += 2;
 689           return 2;
 690         }
 691       else
 692         /* Otherwise, return.  */
 693         return 4;
 694     }
 695
 696   /* We could not find a match.  */
 697   (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
 698
 699   return 4;
 700 }
 701
 702 void
 703 print_ppc_disassembler_options (FILE *stream)
 704 {
 705   unsigned int i, col;
 706
 707   fprintf (stream, _("\n\
 708 The following PPC specific disassembler options are supported for use with\n\
 709 the -M switch:\n"));
 710
 711   for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 712     {
 713       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 714       if (col > 66)
 715         {
 716           fprintf (stream, "\n");
 717           col = 0;
 718         }
 719     }
 720   fprintf (stream, " 32, 64\n");
 721 }