opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2015 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "dis-asm.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29
  30 /* This file provides several disassembler functions, all of which use
  31    the disassembler interface defined in dis-asm.h.  Several functions
  32    are provided because this file handles disassembly for the PowerPC
  33    in both big and little endian mode and also for the POWER (RS/6000)
  34    chip.  */
  35 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  36                                ppc_cpu_t);
  37
  38 struct dis_private
  39 {
  40   /* Stash the result of parsing disassembler_options here.  */
  41   ppc_cpu_t dialect;
  42 } private;
  43
  44 #define POWERPC_DIALECT(INFO) \
  45   (((struct dis_private *) ((INFO)->private_data))->dialect)
  46
  47 struct ppc_mopt {
  48   const char *opt;
  49   ppc_cpu_t cpu;
  50   ppc_cpu_t sticky;
  51 };
  52
  53 struct ppc_mopt ppc_opts[] = {
  54   { "403",     (PPC_OPCODE_PPC | PPC_OPCODE_403),
  55     0 },
  56   { "405",     (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
  57     0 },
  58   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  59                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  60     0 },
  61   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  62                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  63     0 },
  64   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
  65                 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  66     0 },
  67   { "601",     (PPC_OPCODE_PPC | PPC_OPCODE_601),
  68     0 },
  69   { "603",     (PPC_OPCODE_PPC),
  70     0 },
  71   { "604",     (PPC_OPCODE_PPC),
  72     0 },
  73   { "620",     (PPC_OPCODE_PPC | PPC_OPCODE_64),
  74     0 },
  75   { "7400",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  76     0 },
  77   { "7410",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  78     0 },
  79   { "7450",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  80     0 },
  81   { "7455",    (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
  82     0 },
  83   { "750cl",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
  84     , 0 },
  85   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
  86                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
  87                 | PPC_OPCODE_A2),
  88     0 },
  89   { "altivec", (PPC_OPCODE_PPC),
  90     PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
  91   { "any",     0,
  92     PPC_OPCODE_ANY },
  93   { "booke",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
  94     0 },
  95   { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
  96     0 },
  97   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
  98                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
  99     0 },
 100   { "com",     (PPC_OPCODE_COMMON),
 101     0 },
 102   { "e300",    (PPC_OPCODE_PPC | PPC_OPCODE_E300),
 103     0 },
 104   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 105                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 106                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 107                 | PPC_OPCODE_E500),
 108     0 },
 109   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 110                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 111                 | PPC_OPCODE_E500MC),
 112     0 },
 113   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 114                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 115                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 116                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 117     0 },
 118   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 119                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 120                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 121                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 122                 | PPC_OPCODE_POWER7),
 123     0 },
 124   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 125                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 126                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 127                 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
 128                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 129     0 },
 130   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 131                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 132                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 133                 | PPC_OPCODE_E500),
 134     0 },
 135   { "efs",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 136     0 },
 137   { "power4",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 138     0 },
 139   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 140                 | PPC_OPCODE_POWER5),
 141     0 },
 142   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 143                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 144     0 },
 145   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 146                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 147                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 148     0 },
 149   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 150                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 151                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 152                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 153     0 },
 154   { "ppc",     (PPC_OPCODE_PPC),
 155     0 },
 156   { "ppc32",   (PPC_OPCODE_PPC),
 157     0 },
 158   { "ppc64",   (PPC_OPCODE_PPC | PPC_OPCODE_64),
 159     0 },
 160   { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
 161     0 },
 162   { "ppcps",   (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
 163     0 },
 164   { "pwr",     (PPC_OPCODE_POWER),
 165     0 },
 166   { "pwr2",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 167     0 },
 168   { "pwr4",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
 169     0 },
 170   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 171                 | PPC_OPCODE_POWER5),
 172     0 },
 173   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 174                 | PPC_OPCODE_POWER5),
 175     0 },
 176   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 177                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 178     0 },
 179   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 180                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 181                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 182     0 },
 183   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 184                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 185                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 186                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 187     0 },
 188   { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
 189     0 },
 190   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
 191     PPC_OPCODE_SPE },
 192   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 193                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 194     0 },
 195   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
 196     PPC_OPCODE_VLE },
 197   { "vsx",     (PPC_OPCODE_PPC),
 198     PPC_OPCODE_VSX },
 199   { "htm",     (PPC_OPCODE_PPC),
 200     PPC_OPCODE_HTM },
 201 };
 202
 203 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 204 static ppc_cpu_t
 205 get_powerpc_dialect (struct disassemble_info *info)
 206 {
 207   ppc_cpu_t dialect = 0;
 208
 209   dialect = POWERPC_DIALECT (info);
 210
 211   /* Disassemble according to the section headers flags for VLE-mode.  */
 212   if (dialect & PPC_OPCODE_VLE
 213       && info->section->owner != NULL
 214       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 215       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 216       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 217     return dialect;
 218   else
 219     return dialect & ~ PPC_OPCODE_VLE;
 220 }
 221
 222 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 223
 224 ppc_cpu_t
 225 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 226 {
 227   unsigned int i;
 228
 229   for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 230     if (strcmp (ppc_opts[i].opt, arg) == 0)
 231       {
 232         if (ppc_opts[i].sticky)
 233           {
 234             *sticky |= ppc_opts[i].sticky;
 235             if ((ppc_cpu & ~*sticky) != 0)
 236               break;
 237           }
 238         ppc_cpu = ppc_opts[i].cpu;
 239         break;
 240       }
 241   if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
 242     return 0;
 243
 244   ppc_cpu |= *sticky;
 245   return ppc_cpu;
 246 }
 247
 248 /* Determine which set of machines to disassemble for.  */
 249
 250 static void
 251 powerpc_init_dialect (struct disassemble_info *info)
 252 {
 253   ppc_cpu_t dialect = 0;
 254   ppc_cpu_t sticky = 0;
 255   char *arg;
 256   struct dis_private *priv = calloc (sizeof (*priv), 1);
 257
 258   if (priv == NULL)
 259     priv = &private;
 260
 261   switch (info->mach)
 262     {
 263     case bfd_mach_ppc_403:
 264     case bfd_mach_ppc_403gc:
 265       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 266       break;
 267     case bfd_mach_ppc_405:
 268       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 269       break;
 270     case bfd_mach_ppc_601:
 271       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 272       break;
 273     case bfd_mach_ppc_a35:
 274     case bfd_mach_ppc_rs64ii:
 275     case bfd_mach_ppc_rs64iii:
 276       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 277       break;
 278     case bfd_mach_ppc_e500:
 279       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 280       break;
 281     case bfd_mach_ppc_e500mc:
 282       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 283       break;
 284     case bfd_mach_ppc_e500mc64:
 285       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 286       break;
 287     case bfd_mach_ppc_e5500:
 288       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 289       break;
 290     case bfd_mach_ppc_e6500:
 291       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 292       break;
 293     case bfd_mach_ppc_titan:
 294       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 295       break;
 296     case bfd_mach_ppc_vle:
 297       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 298       break;
 299     default:
 300       dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY;
 301     }
 302
 303   arg = info->disassembler_options;
 304   while (arg != NULL)
 305     {
 306       ppc_cpu_t new_cpu = 0;
 307       char *end = strchr (arg, ',');
 308
 309       if (end != NULL)
 310         *end = 0;
 311
 312       if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
 313         dialect = new_cpu;
 314       else if (strcmp (arg, "32") == 0)
 315         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 316       else if (strcmp (arg, "64") == 0)
 317         dialect |= PPC_OPCODE_64;
 318       else
 319         fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
 320
 321       if (end != NULL)
 322         *end++ = ',';
 323       arg = end;
 324     }
 325
 326   info->private_data = priv;
 327   POWERPC_DIALECT(info) = dialect;
 328 }
 329
 330 #define PPC_OPCD_SEGS 64
 331 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 332 #define VLE_OPCD_SEGS 32
 333 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 334
 335 /* Calculate opcode table indices to speed up disassembly,
 336    and init dialect.  */
 337
 338 void
 339 disassemble_init_powerpc (struct disassemble_info *info)
 340 {
 341   int i;
 342   unsigned short last;
 343
 344   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 345     {
 346
 347       i = powerpc_num_opcodes;
 348       while (--i >= 0)
 349         {
 350           unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 351
 352           powerpc_opcd_indices[op] = i;
 353         }
 354
 355       last = powerpc_num_opcodes;
 356       for (i = PPC_OPCD_SEGS; i > 0; --i)
 357         {
 358           if (powerpc_opcd_indices[i] == 0)
 359             powerpc_opcd_indices[i] = last;
 360           last = powerpc_opcd_indices[i];
 361         }
 362
 363       i = vle_num_opcodes;
 364       while (--i >= 0)
 365         {
 366           unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 367           unsigned seg = VLE_OP_TO_SEG (op);
 368
 369           vle_opcd_indices[seg] = i;
 370         }
 371
 372       last = vle_num_opcodes;
 373       for (i = VLE_OPCD_SEGS; i > 0; --i)
 374         {
 375           if (vle_opcd_indices[i] == 0)
 376             vle_opcd_indices[i] = last;
 377           last = vle_opcd_indices[i];
 378         }
 379     }
 380
 381   if (info->arch == bfd_arch_powerpc)
 382     powerpc_init_dialect (info);
 383 }
 384
 385 /* Print a big endian PowerPC instruction.  */
 386
 387 int
 388 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 389 {
 390   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 391 }
 392
 393 /* Print a little endian PowerPC instruction.  */
 394
 395 int
 396 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 397 {
 398   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 399 }
 400
 401 /* Print a POWER (RS/6000) instruction.  */
 402
 403 int
 404 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 405 {
 406   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 407 }
 408
 409 /* Extract the operand value from the PowerPC or POWER instruction.  */
 410
 411 static long
 412 operand_value_powerpc (const struct powerpc_operand *operand,
 413                        unsigned long insn, ppc_cpu_t dialect)
 414 {
 415   long value;
 416   int invalid;
 417   /* Extract the value from the instruction.  */
 418   if (operand->extract)
 419     value = (*operand->extract) (insn, dialect, &invalid);
 420   else
 421     {
 422       if (operand->shift >= 0)
 423         value = (insn >> operand->shift) & operand->bitm;
 424       else
 425         value = (insn << -operand->shift) & operand->bitm;
 426       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 427         {
 428           /* BITM is always some number of zeros followed by some
 429              number of ones, followed by some number of zeros.  */
 430           unsigned long top = operand->bitm;
 431           /* top & -top gives the rightmost 1 bit, so this
 432              fills in any trailing zeros.  */
 433           top |= (top & -top) - 1;
 434           top &= ~(top >> 1);
 435           value = (value ^ top) - top;
 436         }
 437     }
 438
 439   return value;
 440 }
 441
 442 /* Determine whether the optional operand(s) should be printed.  */
 443
 444 static int
 445 skip_optional_operands (const unsigned char *opindex,
 446                         unsigned long insn, ppc_cpu_t dialect)
 447 {
 448   const struct powerpc_operand *operand;
 449
 450   for (; *opindex != 0; opindex++)
 451     {
 452       operand = &powerpc_operands[*opindex];
 453       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 454           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 455               && operand_value_powerpc (operand, insn, dialect) != 0))
 456         return 0;
 457     }
 458
 459   return 1;
 460 }
 461
 462 /* Find a match for INSN in the opcode table, given machine DIALECT.
 463    A DIALECT of -1 is special, matching all machine opcode variations.  */
 464
 465 static const struct powerpc_opcode *
 466 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
 467 {
 468   const struct powerpc_opcode *opcode;
 469   const struct powerpc_opcode *opcode_end;
 470   unsigned long op;
 471
 472   /* Get the major opcode of the instruction.  */
 473   op = PPC_OP (insn);
 474
 475   /* Find the first match in the opcode table for this major opcode.  */
 476   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 477   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 478        opcode < opcode_end;
 479        ++opcode)
 480     {
 481       const unsigned char *opindex;
 482       const struct powerpc_operand *operand;
 483       int invalid;
 484
 485       if ((insn & opcode->mask) != opcode->opcode
 486           || (dialect != (ppc_cpu_t) -1
 487               && ((opcode->flags & dialect) == 0
 488                   || (opcode->deprecated & dialect) != 0)))
 489         continue;
 490
 491       /* Check validity of operands.  */
 492       invalid = 0;
 493       for (opindex = opcode->operands; *opindex != 0; opindex++)
 494         {
 495           operand = powerpc_operands + *opindex;
 496           if (operand->extract)
 497             (*operand->extract) (insn, dialect, &invalid);
 498         }
 499       if (invalid)
 500         continue;
 501
 502       return opcode;
 503     }
 504
 505   return NULL;
 506 }
 507
 508 /* Find a match for INSN in the VLE opcode table.  */
 509
 510 static const struct powerpc_opcode *
 511 lookup_vle (unsigned long insn)
 512 {
 513   const struct powerpc_opcode *opcode;
 514   const struct powerpc_opcode *opcode_end;
 515   unsigned op, seg;
 516
 517   op = PPC_OP (insn);
 518   if (op >= 0x20 && op <= 0x37)
 519     {
 520       /* This insn has a 4-bit opcode.  */
 521       op &= 0x3c;
 522     }
 523   seg = VLE_OP_TO_SEG (op);
 524
 525   /* Find the first match in the opcode table for this major opcode.  */
 526   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 527   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 528        opcode < opcode_end;
 529        ++opcode)
 530     {
 531       unsigned long table_opcd = opcode->opcode;
 532       unsigned long table_mask = opcode->mask;
 533       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 534       unsigned long insn2;
 535       const unsigned char *opindex;
 536       const struct powerpc_operand *operand;
 537       int invalid;
 538
 539       insn2 = insn;
 540       if (table_op_is_short)
 541         insn2 >>= 16;
 542       if ((insn2 & table_mask) != table_opcd)
 543         continue;
 544
 545       /* Check validity of operands.  */
 546       invalid = 0;
 547       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 548         {
 549           operand = powerpc_operands + *opindex;
 550           if (operand->extract)
 551             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 552         }
 553       if (invalid)
 554         continue;
 555
 556       return opcode;
 557     }
 558
 559   return NULL;
 560 }
 561
 562 /* Print a PowerPC or POWER instruction.  */
 563
 564 static int
 565 print_insn_powerpc (bfd_vma memaddr,
 566                     struct disassemble_info *info,
 567                     int bigendian,
 568                     ppc_cpu_t dialect)
 569 {
 570   bfd_byte buffer[4];
 571   int status;
 572   unsigned long insn;
 573   const struct powerpc_opcode *opcode;
 574   bfd_boolean insn_is_short;
 575
 576   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 577   if (status != 0)
 578     {
 579       /* The final instruction may be a 2-byte VLE insn.  */
 580       if ((dialect & PPC_OPCODE_VLE) != 0)
 581         {
 582           /* Clear buffer so unused bytes will not have garbage in them.  */
 583           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 584           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 585           if (status != 0)
 586             {
 587               (*info->memory_error_func) (status, memaddr, info);
 588               return -1;
 589             }
 590         }
 591       else
 592         {
 593           (*info->memory_error_func) (status, memaddr, info);
 594           return -1;
 595         }
 596     }
 597
 598   if (bigendian)
 599     insn = bfd_getb32 (buffer);
 600   else
 601     insn = bfd_getl32 (buffer);
 602
 603   /* Get the major opcode of the insn.  */
 604   opcode = NULL;
 605   insn_is_short = FALSE;
 606   if ((dialect & PPC_OPCODE_VLE) != 0)
 607     {
 608       opcode = lookup_vle (insn);
 609       if (opcode != NULL)
 610         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 611     }
 612   if (opcode == NULL)
 613     opcode = lookup_powerpc (insn, dialect);
 614   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 615     opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
 616
 617   if (opcode != NULL)
 618     {
 619       const unsigned char *opindex;
 620       const struct powerpc_operand *operand;
 621       int need_comma;
 622       int need_paren;
 623       int skip_optional;
 624
 625       if (opcode->operands[0] != 0)
 626         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 627       else
 628         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 629
 630       if (insn_is_short)
 631         /* The operands will be fetched out of the 16-bit instruction.  */
 632         insn >>= 16;
 633
 634       /* Now extract and print the operands.  */
 635       need_comma = 0;
 636       need_paren = 0;
 637       skip_optional = -1;
 638       for (opindex = opcode->operands; *opindex != 0; opindex++)
 639         {
 640           long value;
 641
 642           operand = powerpc_operands + *opindex;
 643
 644           /* Operands that are marked FAKE are simply ignored.  We
 645              already made sure that the extract function considered
 646              the instruction to be valid.  */
 647           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 648             continue;
 649
 650           /* If all of the optional operands have the value zero,
 651              then don't print any of them.  */
 652           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 653             {
 654               if (skip_optional < 0)
 655                 skip_optional = skip_optional_operands (opindex, insn,
 656                                                         dialect);
 657               if (skip_optional)
 658                 continue;
 659             }
 660
 661           value = operand_value_powerpc (operand, insn, dialect);
 662
 663           if (need_comma)
 664             {
 665               (*info->fprintf_func) (info->stream, ",");
 666               need_comma = 0;
 667             }
 668
 669           /* Print the operand as directed by the flags.  */
 670           if ((operand->flags & PPC_OPERAND_GPR) != 0
 671               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 672             (*info->fprintf_func) (info->stream, "r%ld", value);
 673           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 674             (*info->fprintf_func) (info->stream, "f%ld", value);
 675           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 676             (*info->fprintf_func) (info->stream, "v%ld", value);
 677           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 678             (*info->fprintf_func) (info->stream, "vs%ld", value);
 679           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 680             (*info->print_address_func) (memaddr + value, info);
 681           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 682             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 683           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 684             (*info->fprintf_func) (info->stream, "fsl%ld", value);
 685           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 686             (*info->fprintf_func) (info->stream, "fcr%ld", value);
 687           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 688             (*info->fprintf_func) (info->stream, "%ld", value);
 689           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 690                    && (((dialect & PPC_OPCODE_PPC) != 0)
 691                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 692             (*info->fprintf_func) (info->stream, "cr%ld", value);
 693           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 694                    && (((dialect & PPC_OPCODE_PPC) != 0)
 695                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 696             {
 697               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 698               int cr;
 699               int cc;
 700
 701               cr = value >> 2;
 702               if (cr != 0)
 703                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 704               cc = value & 3;
 705               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 706             }
 707           else
 708             (*info->fprintf_func) (info->stream, "%d", (int) value);
 709
 710           if (need_paren)
 711             {
 712               (*info->fprintf_func) (info->stream, ")");
 713               need_paren = 0;
 714             }
 715
 716           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 717             need_comma = 1;
 718           else
 719             {
 720               (*info->fprintf_func) (info->stream, "(");
 721               need_paren = 1;
 722             }
 723         }
 724
 725       /* We have found and printed an instruction.
 726          If it was a short VLE instruction we have more to do.  */
 727       if (insn_is_short)
 728         {
 729           memaddr += 2;
 730           return 2;
 731         }
 732       else
 733         /* Otherwise, return.  */
 734         return 4;
 735     }
 736
 737   /* We could not find a match.  */
 738   (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
 739
 740   return 4;
 741 }
 742
 743 void
 744 print_ppc_disassembler_options (FILE *stream)
 745 {
 746   unsigned int i, col;
 747
 748   fprintf (stream, _("\n\
 749 The following PPC specific disassembler options are supported for use with\n\
 750 the -M switch:\n"));
 751
 752   for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 753     {
 754       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 755       if (col > 66)
 756         {
 757           fprintf (stream, "\n");
 758           col = 0;
 759         }
 760     }
 761   fprintf (stream, " 32, 64\n");
 762 }