opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version
  11    2, or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  21    02110-1301, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, int, const char **);
  42 static long extract_bat (unsigned long, int, int *);
  43 static unsigned long insert_bba (unsigned long, long, int, const char **);
  44 static long extract_bba (unsigned long, int, int *);
  45 static unsigned long insert_bdm (unsigned long, long, int, const char **);
  46 static long extract_bdm (unsigned long, int, int *);
  47 static unsigned long insert_bdp (unsigned long, long, int, const char **);
  48 static long extract_bdp (unsigned long, int, int *);
  49 static unsigned long insert_bo (unsigned long, long, int, const char **);
  50 static long extract_bo (unsigned long, int, int *);
  51 static unsigned long insert_boe (unsigned long, long, int, const char **);
  52 static long extract_boe (unsigned long, int, int *);
  53 static unsigned long insert_fxm (unsigned long, long, int, const char **);
  54 static long extract_fxm (unsigned long, int, int *);
  55 static unsigned long insert_mbe (unsigned long, long, int, const char **);
  56 static long extract_mbe (unsigned long, int, int *);
  57 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
  58 static long extract_mb6 (unsigned long, int, int *);
  59 static long extract_nb (unsigned long, int, int *);
  60 static unsigned long insert_nsi (unsigned long, long, int, const char **);
  61 static long extract_nsi (unsigned long, int, int *);
  62 static unsigned long insert_ral (unsigned long, long, int, const char **);
  63 static unsigned long insert_ram (unsigned long, long, int, const char **);
  64 static unsigned long insert_raq (unsigned long, long, int, const char **);
  65 static unsigned long insert_ras (unsigned long, long, int, const char **);
  66 static unsigned long insert_rbs (unsigned long, long, int, const char **);
  67 static long extract_rbs (unsigned long, int, int *);
  68 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
  69 static long extract_sh6 (unsigned long, int, int *);
  70 static unsigned long insert_spr (unsigned long, long, int, const char **);
  71 static long extract_spr (unsigned long, int, int *);
  72 static unsigned long insert_sprg (unsigned long, long, int, const char **);
  73 static long extract_sprg (unsigned long, int, int *);
  74 static unsigned long insert_tbr (unsigned long, long, int, const char **);
  75 static long extract_tbr (unsigned long, int, int *);
  76 \f
  77 /* The operands table.
  78
  79    The fields are bits, shift, insert, extract, flags.
  80
  81    We used to put parens around the various additions, like the one
  82    for BA just below.  However, that caused trouble with feeble
  83    compilers with a limit on depth of a parenthesized expression, like
  84    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  85    omit the parens, since the macros are never used in a context where
  86    the addition will be ambiguous.  */
  87
  88 const struct powerpc_operand powerpc_operands[] =
  89 {
  90   /* The zero index is used to indicate the end of the list of
  91      operands.  */
  92 #define UNUSED 0
  93   { 0, 0, NULL, NULL, 0 },
  94
  95   /* The BA field in an XL form instruction.  */
  96 #define BA UNUSED + 1
  97 #define BA_MASK (0x1f << 16)
  98   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
  99
 100   /* The BA field in an XL form instruction when it must be the same
 101      as the BT field in the same instruction.  */
 102 #define BAT BA + 1
 103   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 104
 105   /* The BB field in an XL form instruction.  */
 106 #define BB BAT + 1
 107 #define BB_MASK (0x1f << 11)
 108   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
 109
 110   /* The BB field in an XL form instruction when it must be the same
 111      as the BA field in the same instruction.  */
 112 #define BBA BB + 1
 113   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 114
 115   /* The BD field in a B form instruction.  The lower two bits are
 116      forced to zero.  */
 117 #define BD BBA + 1
 118   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 119
 120   /* The BD field in a B form instruction when absolute addressing is
 121      used.  */
 122 #define BDA BD + 1
 123   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 124
 125   /* The BD field in a B form instruction when the - modifier is used.
 126      This sets the y bit of the BO field appropriately.  */
 127 #define BDM BDA + 1
 128   { 0xfffc, 0, insert_bdm, extract_bdm,
 129       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 130
 131   /* The BD field in a B form instruction when the - modifier is used
 132      and absolute address is used.  */
 133 #define BDMA BDM + 1
 134   { 0xfffc, 0, insert_bdm, extract_bdm,
 135       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 136
 137   /* The BD field in a B form instruction when the + modifier is used.
 138      This sets the y bit of the BO field appropriately.  */
 139 #define BDP BDMA + 1
 140   { 0xfffc, 0, insert_bdp, extract_bdp,
 141       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 142
 143   /* The BD field in a B form instruction when the + modifier is used
 144      and absolute addressing is used.  */
 145 #define BDPA BDP + 1
 146   { 0xfffc, 0, insert_bdp, extract_bdp,
 147       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 148
 149   /* The BF field in an X or XL form instruction.  */
 150 #define BF BDPA + 1
 151   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
 152
 153   /* An optional BF field.  This is used for comparison instructions,
 154      in which an omitted BF field is taken as zero.  */
 155 #define OBF BF + 1
 156   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 157
 158   /* The BFA field in an X or XL form instruction.  */
 159 #define BFA OBF + 1
 160   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
 161
 162   /* The BI field in a B form or XL form instruction.  */
 163 #define BI BFA + 1
 164 #define BI_MASK (0x1f << 16)
 165   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
 166
 167   /* The BO field in a B form instruction.  Certain values are
 168      illegal.  */
 169 #define BO BI + 1
 170 #define BO_MASK (0x1f << 21)
 171   { 0x1f, 21, insert_bo, extract_bo, 0 },
 172
 173   /* The BO field in a B form instruction when the + or - modifier is
 174      used.  This is like the BO field, but it must be even.  */
 175 #define BOE BO + 1
 176   { 0x1e, 21, insert_boe, extract_boe, 0 },
 177
 178 #define BH BOE + 1
 179   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 180
 181   /* The BT field in an X or XL form instruction.  */
 182 #define BT BH + 1
 183   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
 184
 185   /* The condition register number portion of the BI field in a B form
 186      or XL form instruction.  This is used for the extended
 187      conditional branch mnemonics, which set the lower two bits of the
 188      BI field.  This field is optional.  */
 189 #define CR BT + 1
 190   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 191
 192   /* The CRB field in an X form instruction.  */
 193 #define CRB CR + 1
 194   { 0x1f, 6, NULL, NULL, 0 },
 195
 196   /* The CRFD field in an X form instruction.  */
 197 #define CRFD CRB + 1
 198   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
 199
 200   /* The CRFS field in an X form instruction.  */
 201 #define CRFS CRFD + 1
 202   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
 203
 204   /* The CT field in an X form instruction.  */
 205 #define CT CRFS + 1
 206   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 207
 208   /* The D field in a D form instruction.  This is a displacement off
 209      a register, and implies that the next operand is a register in
 210      parentheses.  */
 211 #define D CT + 1
 212   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 213
 214   /* The DE field in a DE form instruction.  This is like D, but is 12
 215      bits only.  */
 216 #define DE D + 1
 217   { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 218
 219   /* The DES field in a DES form instruction.  This is like DS, but is 14
 220      bits only (12 stored.)  */
 221 #define DES DE + 1
 222   { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 223
 224   /* The DQ field in a DQ form instruction.  This is like D, but the
 225      lower four bits are forced to zero. */
 226 #define DQ DES + 1
 227   { 0xfff0, 0, NULL, NULL,
 228     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 229
 230   /* The DS field in a DS form instruction.  This is like D, but the
 231      lower two bits are forced to zero.  */
 232 #define DS DQ + 1
 233   { 0xfffc, 0, NULL, NULL,
 234     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 235
 236   /* The E field in a wrteei instruction.  */
 237 #define E DS + 1
 238   { 0x1, 15, NULL, NULL, 0 },
 239
 240   /* The FL1 field in a POWER SC form instruction.  */
 241 #define FL1 E + 1
 242   { 0xf, 12, NULL, NULL, 0 },
 243
 244   /* The FL2 field in a POWER SC form instruction.  */
 245 #define FL2 FL1 + 1
 246   { 0x7, 2, NULL, NULL, 0 },
 247
 248   /* The FLM field in an XFL form instruction.  */
 249 #define FLM FL2 + 1
 250   { 0xff, 17, NULL, NULL, 0 },
 251
 252   /* The FRA field in an X or A form instruction.  */
 253 #define FRA FLM + 1
 254 #define FRA_MASK (0x1f << 16)
 255   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 256
 257   /* The FRB field in an X or A form instruction.  */
 258 #define FRB FRA + 1
 259 #define FRB_MASK (0x1f << 11)
 260   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 261
 262   /* The FRC field in an A form instruction.  */
 263 #define FRC FRB + 1
 264 #define FRC_MASK (0x1f << 6)
 265   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 266
 267   /* The FRS field in an X form instruction or the FRT field in a D, X
 268      or A form instruction.  */
 269 #define FRS FRC + 1
 270 #define FRT FRS
 271   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 272
 273   /* The FXM field in an XFX instruction.  */
 274 #define FXM FRS + 1
 275 #define FXM_MASK (0xff << 12)
 276   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 277
 278   /* Power4 version for mfcr.  */
 279 #define FXM4 FXM + 1
 280   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 281
 282   /* The L field in a D or X form instruction.  */
 283 #define L FXM4 + 1
 284   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 285
 286   /* The LEV field in a POWER SVC form instruction.  */
 287 #define SVC_LEV L + 1
 288   { 0x7f, 5, NULL, NULL, 0 },
 289
 290   /* The LEV field in an SC form instruction.  */
 291 #define LEV SVC_LEV + 1
 292   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 293
 294   /* The LI field in an I form instruction.  The lower two bits are
 295      forced to zero.  */
 296 #define LI LEV + 1
 297   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 298
 299   /* The LI field in an I form instruction when used as an absolute
 300      address.  */
 301 #define LIA LI + 1
 302   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 303
 304   /* The LS field in an X (sync) form instruction.  */
 305 #define LS LIA + 1
 306   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 307
 308   /* The MB field in an M form instruction.  */
 309 #define MB LS + 1
 310 #define MB_MASK (0x1f << 6)
 311   { 0x1f, 6, NULL, NULL, 0 },
 312
 313   /* The ME field in an M form instruction.  */
 314 #define ME MB + 1
 315 #define ME_MASK (0x1f << 1)
 316   { 0x1f, 1, NULL, NULL, 0 },
 317
 318   /* The MB and ME fields in an M form instruction expressed a single
 319      operand which is a bitmask indicating which bits to select.  This
 320      is a two operand form using PPC_OPERAND_NEXT.  See the
 321      description in opcode/ppc.h for what this means.  */
 322 #define MBE ME + 1
 323   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 324   { 0xff, 0, insert_mbe, extract_mbe, 0 },
 325
 326   /* The MB or ME field in an MD or MDS form instruction.  The high
 327      bit is wrapped to the low end.  */
 328 #define MB6 MBE + 2
 329 #define ME6 MB6
 330 #define MB6_MASK (0x3f << 5)
 331   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 332
 333   /* The MO field in an mbar instruction.  */
 334 #define MO MB6 + 1
 335   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 336
 337   /* The NB field in an X form instruction.  The value 32 is stored as
 338      0.  */
 339 #define NB MO + 1
 340   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 341
 342   /* The NSI field in a D form instruction.  This is the same as the
 343      SI field, only negated.  */
 344 #define NSI NB + 1
 345   { 0xffff, 0, insert_nsi, extract_nsi,
 346       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 347
 348   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 349 #define RA NSI + 1
 350 #define RA_MASK (0x1f << 16)
 351   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 352
 353   /* As above, but 0 in the RA field means zero, not r0.  */
 354 #define RA0 RA + 1
 355   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 356
 357   /* The RA field in the DQ form lq instruction, which has special
 358      value restrictions.  */
 359 #define RAQ RA0 + 1
 360   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 361
 362   /* The RA field in a D or X form instruction which is an updating
 363      load, which means that the RA field may not be zero and may not
 364      equal the RT field.  */
 365 #define RAL RAQ + 1
 366   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 367
 368   /* The RA field in an lmw instruction, which has special value
 369      restrictions.  */
 370 #define RAM RAL + 1
 371   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 372
 373   /* The RA field in a D or X form instruction which is an updating
 374      store or an updating floating point load, which means that the RA
 375      field may not be zero.  */
 376 #define RAS RAM + 1
 377   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 378
 379   /* The RA field of the tlbwe instruction, which is optional.  */
 380 #define RAOPT RAS + 1
 381   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 382
 383   /* The RB field in an X, XO, M, or MDS form instruction.  */
 384 #define RB RAOPT + 1
 385 #define RB_MASK (0x1f << 11)
 386   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 387
 388   /* The RB field in an X form instruction when it must be the same as
 389      the RS field in the instruction.  This is used for extended
 390      mnemonics like mr.  */
 391 #define RBS RB + 1
 392   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 393
 394   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 395      instruction or the RT field in a D, DS, X, XFX or XO form
 396      instruction.  */
 397 #define RS RBS + 1
 398 #define RT RS
 399 #define RT_MASK (0x1f << 21)
 400   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 401
 402   /* The RS field of the DS form stq instruction, which has special
 403      value restrictions.  */
 404 #define RSQ RS + 1
 405   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 406
 407   /* The RT field of the DQ form lq instruction, which has special
 408      value restrictions.  */
 409 #define RTQ RSQ + 1
 410   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 411
 412   /* The RS field of the tlbwe instruction, which is optional.  */
 413 #define RSO RTQ + 1
 414 #define RTO RSO
 415   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 416
 417   /* The SH field in an X or M form instruction.  */
 418 #define SH RSO + 1
 419 #define SH_MASK (0x1f << 11)
 420   { 0x1f, 11, NULL, NULL, 0 },
 421
 422   /* The SH field in an MD form instruction.  This is split.  */
 423 #define SH6 SH + 1
 424 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 425   { 0x3f, -1, insert_sh6, extract_sh6, 0 },
 426
 427   /* The SH field of the tlbwe instruction, which is optional.  */
 428 #define SHO SH6 + 1
 429   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 430
 431   /* The SI field in a D form instruction.  */
 432 #define SI SHO + 1
 433   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 434
 435   /* The SI field in a D form instruction when we accept a wide range
 436      of positive values.  */
 437 #define SISIGNOPT SI + 1
 438   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 439
 440   /* The SPR field in an XFX form instruction.  This is flipped--the
 441      lower 5 bits are stored in the upper 5 and vice- versa.  */
 442 #define SPR SISIGNOPT + 1
 443 #define PMR SPR
 444 #define SPR_MASK (0x3ff << 11)
 445   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 446
 447   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 448 #define SPRBAT SPR + 1
 449 #define SPRBAT_MASK (0x3 << 17)
 450   { 0x3, 17, NULL, NULL, 0 },
 451
 452   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 453 #define SPRG SPRBAT + 1
 454   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 455
 456   /* The SR field in an X form instruction.  */
 457 #define SR SPRG + 1
 458   { 0xf, 16, NULL, NULL, 0 },
 459
 460   /* The STRM field in an X AltiVec form instruction.  */
 461 #define STRM SR + 1
 462 #define STRM_MASK (0x3 << 21)
 463   { 0x3, 21, NULL, NULL, 0 },
 464
 465   /* The SV field in a POWER SC form instruction.  */
 466 #define SV STRM + 1
 467   { 0x3fff, 2, NULL, NULL, 0 },
 468
 469   /* The TBR field in an XFX form instruction.  This is like the SPR
 470      field, but it is optional.  */
 471 #define TBR SV + 1
 472   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 473
 474   /* The TO field in a D or X form instruction.  */
 475 #define TO TBR + 1
 476 #define TO_MASK (0x1f << 21)
 477   { 0x1f, 21, NULL, NULL, 0 },
 478
 479   /* The U field in an X form instruction.  */
 480 #define U TO + 1
 481   { 0xf, 12, NULL, NULL, 0 },
 482
 483   /* The UI field in a D form instruction.  */
 484 #define UI U + 1
 485   { 0xffff, 0, NULL, NULL, 0 },
 486
 487   /* The VA field in a VA, VX or VXR form instruction.  */
 488 #define VA UI + 1
 489 #define VA_MASK (0x1f << 16)
 490   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 491
 492   /* The VB field in a VA, VX or VXR form instruction.  */
 493 #define VB VA + 1
 494 #define VB_MASK (0x1f << 11)
 495   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 496
 497   /* The VC field in a VA form instruction.  */
 498 #define VC VB + 1
 499 #define VC_MASK (0x1f << 6)
 500   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 501
 502   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 503 #define VD VC + 1
 504 #define VS VD
 505 #define VD_MASK (0x1f << 21)
 506   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 507
 508   /* The SIMM field in a VX form instruction.  */
 509 #define SIMM VD + 1
 510   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 511
 512   /* The UIMM field in a VX form instruction, and TE in Z form.  */
 513 #define UIMM SIMM + 1
 514 #define TE UIMM
 515   { 0x1f, 16, NULL, NULL, 0 },
 516
 517   /* The SHB field in a VA form instruction.  */
 518 #define SHB UIMM + 1
 519   { 0xf, 6, NULL, NULL, 0 },
 520
 521   /* The other UIMM field in a EVX form instruction.  */
 522 #define EVUIMM SHB + 1
 523   { 0x1f, 11, NULL, NULL, 0 },
 524
 525   /* The other UIMM field in a half word EVX form instruction.  */
 526 #define EVUIMM_2 EVUIMM + 1
 527   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 528
 529   /* The other UIMM field in a word EVX form instruction.  */
 530 #define EVUIMM_4 EVUIMM_2 + 1
 531   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 532
 533   /* The other UIMM field in a double EVX form instruction.  */
 534 #define EVUIMM_8 EVUIMM_4 + 1
 535   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 536
 537   /* The WS field.  */
 538 #define WS EVUIMM_8 + 1
 539 #define WS_MASK (0x7 << 11)
 540   { 0x7, 11, NULL, NULL, 0 },
 541
 542   /* The L field in an mtmsrd or A form instruction.  */
 543 #define MTMSRD_L WS + 1
 544 #define A_L MTMSRD_L
 545   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 546
 547 #define RMC A_L + 1
 548   { 0x3, 9, NULL, NULL, 0 },
 549
 550 #define R RMC + 1
 551   { 0x1, 16, NULL, NULL, 0 },
 552
 553 #define SP R + 1
 554   { 0x3, 19, NULL, NULL, 0 },
 555
 556 #define S SP + 1
 557   { 0x1, 20, NULL, NULL, 0 },
 558
 559   /* SH field starting at bit position 16.  */
 560 #define SH16 S + 1
 561   /* The DCM and DGM fields in a Z form instruction.  */
 562 #define DCM SH16
 563 #define DGM DCM
 564   { 0x3f, 10, NULL, NULL, 0 },
 565
 566   /* The L field in an X form with the RT field fixed instruction.  */
 567 #define XRT_L SH16 + 1
 568   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 569
 570   /* The EH field in larx instruction.  */
 571 #define EH XRT_L + 1
 572   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 573 };
 574
 575 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 576                                            / sizeof (powerpc_operands[0]));
 577
 578 /* The functions used to insert and extract complicated operands.  */
 579
 580 /* The BA field in an XL form instruction when it must be the same as
 581    the BT field in the same instruction.  This operand is marked FAKE.
 582    The insertion function just copies the BT field into the BA field,
 583    and the extraction function just checks that the fields are the
 584    same.  */
 585
 586 static unsigned long
 587 insert_bat (unsigned long insn,
 588             long value ATTRIBUTE_UNUSED,
 589             int dialect ATTRIBUTE_UNUSED,
 590             const char **errmsg ATTRIBUTE_UNUSED)
 591 {
 592   return insn | (((insn >> 21) & 0x1f) << 16);
 593 }
 594
 595 static long
 596 extract_bat (unsigned long insn,
 597              int dialect ATTRIBUTE_UNUSED,
 598              int *invalid)
 599 {
 600   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 601     *invalid = 1;
 602   return 0;
 603 }
 604
 605 /* The BB field in an XL form instruction when it must be the same as
 606    the BA field in the same instruction.  This operand is marked FAKE.
 607    The insertion function just copies the BA field into the BB field,
 608    and the extraction function just checks that the fields are the
 609    same.  */
 610
 611 static unsigned long
 612 insert_bba (unsigned long insn,
 613             long value ATTRIBUTE_UNUSED,
 614             int dialect ATTRIBUTE_UNUSED,
 615             const char **errmsg ATTRIBUTE_UNUSED)
 616 {
 617   return insn | (((insn >> 16) & 0x1f) << 11);
 618 }
 619
 620 static long
 621 extract_bba (unsigned long insn,
 622              int dialect ATTRIBUTE_UNUSED,
 623              int *invalid)
 624 {
 625   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 626     *invalid = 1;
 627   return 0;
 628 }
 629
 630 /* The BD field in a B form instruction when the - modifier is used.
 631    This modifier means that the branch is not expected to be taken.
 632    For chips built to versions of the architecture prior to version 2
 633    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 634    if the offset is negative.  When extracting, we require that the y
 635    bit be 1 and that the offset be positive, since if the y bit is 0
 636    we just want to print the normal form of the instruction.
 637    Power4 compatible targets use two bits, "a", and "t", instead of
 638    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 639    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 640    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 641    for branch on CTR.  We only handle the taken/not-taken hint here.
 642    Note that we don't relax the conditions tested here when
 643    disassembling with -Many because insns using extract_bdm and
 644    extract_bdp always occur in pairs.  One or the other will always
 645    be valid.  */
 646
 647 static unsigned long
 648 insert_bdm (unsigned long insn,
 649             long value,
 650             int dialect,
 651             const char **errmsg ATTRIBUTE_UNUSED)
 652 {
 653   if ((dialect & PPC_OPCODE_POWER4) == 0)
 654     {
 655       if ((value & 0x8000) != 0)
 656         insn |= 1 << 21;
 657     }
 658   else
 659     {
 660       if ((insn & (0x14 << 21)) == (0x04 << 21))
 661         insn |= 0x02 << 21;
 662       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 663         insn |= 0x08 << 21;
 664     }
 665   return insn | (value & 0xfffc);
 666 }
 667
 668 static long
 669 extract_bdm (unsigned long insn,
 670              int dialect,
 671              int *invalid)
 672 {
 673   if ((dialect & PPC_OPCODE_POWER4) == 0)
 674     {
 675       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 676         *invalid = 1;
 677     }
 678   else
 679     {
 680       if ((insn & (0x17 << 21)) != (0x06 << 21)
 681           && (insn & (0x1d << 21)) != (0x18 << 21))
 682         *invalid = 1;
 683     }
 684
 685   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 686 }
 687
 688 /* The BD field in a B form instruction when the + modifier is used.
 689    This is like BDM, above, except that the branch is expected to be
 690    taken.  */
 691
 692 static unsigned long
 693 insert_bdp (unsigned long insn,
 694             long value,
 695             int dialect,
 696             const char **errmsg ATTRIBUTE_UNUSED)
 697 {
 698   if ((dialect & PPC_OPCODE_POWER4) == 0)
 699     {
 700       if ((value & 0x8000) == 0)
 701         insn |= 1 << 21;
 702     }
 703   else
 704     {
 705       if ((insn & (0x14 << 21)) == (0x04 << 21))
 706         insn |= 0x03 << 21;
 707       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 708         insn |= 0x09 << 21;
 709     }
 710   return insn | (value & 0xfffc);
 711 }
 712
 713 static long
 714 extract_bdp (unsigned long insn,
 715              int dialect,
 716              int *invalid)
 717 {
 718   if ((dialect & PPC_OPCODE_POWER4) == 0)
 719     {
 720       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 721         *invalid = 1;
 722     }
 723   else
 724     {
 725       if ((insn & (0x17 << 21)) != (0x07 << 21)
 726           && (insn & (0x1d << 21)) != (0x19 << 21))
 727         *invalid = 1;
 728     }
 729
 730   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 731 }
 732
 733 /* Check for legal values of a BO field.  */
 734
 735 static int
 736 valid_bo (long value, int dialect, int extract)
 737 {
 738   if ((dialect & PPC_OPCODE_POWER4) == 0)
 739     {
 740       int valid;
 741       /* Certain encodings have bits that are required to be zero.
 742          These are (z must be zero, y may be anything):
 743              001zy
 744              011zy
 745              1z00y
 746              1z01y
 747              1z1zz
 748       */
 749       switch (value & 0x14)
 750         {
 751         default:
 752         case 0:
 753           valid = 1;
 754           break;
 755         case 0x4:
 756           valid = (value & 0x2) == 0;
 757           break;
 758         case 0x10:
 759           valid = (value & 0x8) == 0;
 760           break;
 761         case 0x14:
 762           valid = value == 0x14;
 763           break;
 764         }
 765       /* When disassembling with -Many, accept power4 encodings too.  */
 766       if (valid
 767           || (dialect & PPC_OPCODE_ANY) == 0
 768           || !extract)
 769         return valid;
 770     }
 771
 772   /* Certain encodings have bits that are required to be zero.
 773      These are (z must be zero, a & t may be anything):
 774          0000z
 775          0001z
 776          0100z
 777          0101z
 778          001at
 779          011at
 780          1a00t
 781          1a01t
 782          1z1zz
 783   */
 784   if ((value & 0x14) == 0)
 785     return (value & 0x1) == 0;
 786   else if ((value & 0x14) == 0x14)
 787     return value == 0x14;
 788   else
 789     return 1;
 790 }
 791
 792 /* The BO field in a B form instruction.  Warn about attempts to set
 793    the field to an illegal value.  */
 794
 795 static unsigned long
 796 insert_bo (unsigned long insn,
 797            long value,
 798            int dialect,
 799            const char **errmsg)
 800 {
 801   if (!valid_bo (value, dialect, 0))
 802     *errmsg = _("invalid conditional option");
 803   return insn | ((value & 0x1f) << 21);
 804 }
 805
 806 static long
 807 extract_bo (unsigned long insn,
 808             int dialect,
 809             int *invalid)
 810 {
 811   long value;
 812
 813   value = (insn >> 21) & 0x1f;
 814   if (!valid_bo (value, dialect, 1))
 815     *invalid = 1;
 816   return value;
 817 }
 818
 819 /* The BO field in a B form instruction when the + or - modifier is
 820    used.  This is like the BO field, but it must be even.  When
 821    extracting it, we force it to be even.  */
 822
 823 static unsigned long
 824 insert_boe (unsigned long insn,
 825             long value,
 826             int dialect,
 827             const char **errmsg)
 828 {
 829   if (!valid_bo (value, dialect, 0))
 830     *errmsg = _("invalid conditional option");
 831   else if ((value & 1) != 0)
 832     *errmsg = _("attempt to set y bit when using + or - modifier");
 833
 834   return insn | ((value & 0x1f) << 21);
 835 }
 836
 837 static long
 838 extract_boe (unsigned long insn,
 839              int dialect,
 840              int *invalid)
 841 {
 842   long value;
 843
 844   value = (insn >> 21) & 0x1f;
 845   if (!valid_bo (value, dialect, 1))
 846     *invalid = 1;
 847   return value & 0x1e;
 848 }
 849
 850 /* FXM mask in mfcr and mtcrf instructions.  */
 851
 852 static unsigned long
 853 insert_fxm (unsigned long insn,
 854             long value,
 855             int dialect,
 856             const char **errmsg)
 857 {
 858   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
 859      one bit of the mask field is set.  */
 860   if ((insn & (1 << 20)) != 0)
 861     {
 862       if (value == 0 || (value & -value) != value)
 863         {
 864           *errmsg = _("invalid mask field");
 865           value = 0;
 866         }
 867     }
 868
 869   /* If the optional field on mfcr is missing that means we want to use
 870      the old form of the instruction that moves the whole cr.  In that
 871      case we'll have VALUE zero.  There doesn't seem to be a way to
 872      distinguish this from the case where someone writes mfcr %r3,0.  */
 873   else if (value == 0)
 874     ;
 875
 876   /* If only one bit of the FXM field is set, we can use the new form
 877      of the instruction, which is faster.  Unlike the Power4 branch hint
 878      encoding, this is not backward compatible.  Do not generate the
 879      new form unless -mpower4 has been given, or -many and the two
 880      operand form of mfcr was used.  */
 881   else if ((value & -value) == value
 882            && ((dialect & PPC_OPCODE_POWER4) != 0
 883                || ((dialect & PPC_OPCODE_ANY) != 0
 884                    && (insn & (0x3ff << 1)) == 19 << 1)))
 885     insn |= 1 << 20;
 886
 887   /* Any other value on mfcr is an error.  */
 888   else if ((insn & (0x3ff << 1)) == 19 << 1)
 889     {
 890       *errmsg = _("ignoring invalid mfcr mask");
 891       value = 0;
 892     }
 893
 894   return insn | ((value & 0xff) << 12);
 895 }
 896
 897 static long
 898 extract_fxm (unsigned long insn,
 899              int dialect ATTRIBUTE_UNUSED,
 900              int *invalid)
 901 {
 902   long mask = (insn >> 12) & 0xff;
 903
 904   /* Is this a Power4 insn?  */
 905   if ((insn & (1 << 20)) != 0)
 906     {
 907       /* Exactly one bit of MASK should be set.  */
 908       if (mask == 0 || (mask & -mask) != mask)
 909         *invalid = 1;
 910     }
 911
 912   /* Check that non-power4 form of mfcr has a zero MASK.  */
 913   else if ((insn & (0x3ff << 1)) == 19 << 1)
 914     {
 915       if (mask != 0)
 916         *invalid = 1;
 917     }
 918
 919   return mask;
 920 }
 921
 922 /* The MB and ME fields in an M form instruction expressed as a single
 923    operand which is itself a bitmask.  The extraction function always
 924    marks it as invalid, since we never want to recognize an
 925    instruction which uses a field of this type.  */
 926
 927 static unsigned long
 928 insert_mbe (unsigned long insn,
 929             long value,
 930             int dialect ATTRIBUTE_UNUSED,
 931             const char **errmsg)
 932 {
 933   unsigned long uval, mask;
 934   int mb, me, mx, count, last;
 935
 936   uval = value;
 937
 938   if (uval == 0)
 939     {
 940       *errmsg = _("illegal bitmask");
 941       return insn;
 942     }
 943
 944   mb = 0;
 945   me = 32;
 946   if ((uval & 1) != 0)
 947     last = 1;
 948   else
 949     last = 0;
 950   count = 0;
 951
 952   /* mb: location of last 0->1 transition */
 953   /* me: location of last 1->0 transition */
 954   /* count: # transitions */
 955
 956   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
 957     {
 958       if ((uval & mask) && !last)
 959         {
 960           ++count;
 961           mb = mx;
 962           last = 1;
 963         }
 964       else if (!(uval & mask) && last)
 965         {
 966           ++count;
 967           me = mx;
 968           last = 0;
 969         }
 970     }
 971   if (me == 0)
 972     me = 32;
 973
 974   if (count != 2 && (count != 0 || ! last))
 975     *errmsg = _("illegal bitmask");
 976
 977   return insn | (mb << 6) | ((me - 1) << 1);
 978 }
 979
 980 static long
 981 extract_mbe (unsigned long insn,
 982              int dialect ATTRIBUTE_UNUSED,
 983              int *invalid)
 984 {
 985   long ret;
 986   int mb, me;
 987   int i;
 988
 989   *invalid = 1;
 990
 991   mb = (insn >> 6) & 0x1f;
 992   me = (insn >> 1) & 0x1f;
 993   if (mb < me + 1)
 994     {
 995       ret = 0;
 996       for (i = mb; i <= me; i++)
 997         ret |= 1L << (31 - i);
 998     }
 999   else if (mb == me + 1)
1000     ret = ~0;
1001   else /* (mb > me + 1) */
1002     {
1003       ret = ~0;
1004       for (i = me + 1; i < mb; i++)
1005         ret &= ~(1L << (31 - i));
1006     }
1007   return ret;
1008 }
1009
1010 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1011    is wrapped to the low end.  */
1012
1013 static unsigned long
1014 insert_mb6 (unsigned long insn,
1015             long value,
1016             int dialect ATTRIBUTE_UNUSED,
1017             const char **errmsg ATTRIBUTE_UNUSED)
1018 {
1019   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1020 }
1021
1022 static long
1023 extract_mb6 (unsigned long insn,
1024              int dialect ATTRIBUTE_UNUSED,
1025              int *invalid ATTRIBUTE_UNUSED)
1026 {
1027   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1028 }
1029
1030 /* The NB field in an X form instruction.  The value 32 is stored as
1031    0.  */
1032
1033 static long
1034 extract_nb (unsigned long insn,
1035             int dialect ATTRIBUTE_UNUSED,
1036             int *invalid ATTRIBUTE_UNUSED)
1037 {
1038   long ret;
1039
1040   ret = (insn >> 11) & 0x1f;
1041   if (ret == 0)
1042     ret = 32;
1043   return ret;
1044 }
1045
1046 /* The NSI field in a D form instruction.  This is the same as the SI
1047    field, only negated.  The extraction function always marks it as
1048    invalid, since we never want to recognize an instruction which uses
1049    a field of this type.  */
1050
1051 static unsigned long
1052 insert_nsi (unsigned long insn,
1053             long value,
1054             int dialect ATTRIBUTE_UNUSED,
1055             const char **errmsg ATTRIBUTE_UNUSED)
1056 {
1057   return insn | (-value & 0xffff);
1058 }
1059
1060 static long
1061 extract_nsi (unsigned long insn,
1062              int dialect ATTRIBUTE_UNUSED,
1063              int *invalid)
1064 {
1065   *invalid = 1;
1066   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1067 }
1068
1069 /* The RA field in a D or X form instruction which is an updating
1070    load, which means that the RA field may not be zero and may not
1071    equal the RT field.  */
1072
1073 static unsigned long
1074 insert_ral (unsigned long insn,
1075             long value,
1076             int dialect ATTRIBUTE_UNUSED,
1077             const char **errmsg)
1078 {
1079   if (value == 0
1080       || (unsigned long) value == ((insn >> 21) & 0x1f))
1081     *errmsg = "invalid register operand when updating";
1082   return insn | ((value & 0x1f) << 16);
1083 }
1084
1085 /* The RA field in an lmw instruction, which has special value
1086    restrictions.  */
1087
1088 static unsigned long
1089 insert_ram (unsigned long insn,
1090             long value,
1091             int dialect ATTRIBUTE_UNUSED,
1092             const char **errmsg)
1093 {
1094   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1095     *errmsg = _("index register in load range");
1096   return insn | ((value & 0x1f) << 16);
1097 }
1098
1099 /* The RA field in the DQ form lq instruction, which has special
1100    value restrictions.  */
1101
1102 static unsigned long
1103 insert_raq (unsigned long insn,
1104             long value,
1105             int dialect ATTRIBUTE_UNUSED,
1106             const char **errmsg)
1107 {
1108   long rtvalue = (insn & RT_MASK) >> 21;
1109
1110   if (value == rtvalue)
1111     *errmsg = _("source and target register operands must be different");
1112   return insn | ((value & 0x1f) << 16);
1113 }
1114
1115 /* The RA field in a D or X form instruction which is an updating
1116    store or an updating floating point load, which means that the RA
1117    field may not be zero.  */
1118
1119 static unsigned long
1120 insert_ras (unsigned long insn,
1121             long value,
1122             int dialect ATTRIBUTE_UNUSED,
1123             const char **errmsg)
1124 {
1125   if (value == 0)
1126     *errmsg = _("invalid register operand when updating");
1127   return insn | ((value & 0x1f) << 16);
1128 }
1129
1130 /* The RB field in an X form instruction when it must be the same as
1131    the RS field in the instruction.  This is used for extended
1132    mnemonics like mr.  This operand is marked FAKE.  The insertion
1133    function just copies the BT field into the BA field, and the
1134    extraction function just checks that the fields are the same.  */
1135
1136 static unsigned long
1137 insert_rbs (unsigned long insn,
1138             long value ATTRIBUTE_UNUSED,
1139             int dialect ATTRIBUTE_UNUSED,
1140             const char **errmsg ATTRIBUTE_UNUSED)
1141 {
1142   return insn | (((insn >> 21) & 0x1f) << 11);
1143 }
1144
1145 static long
1146 extract_rbs (unsigned long insn,
1147              int dialect ATTRIBUTE_UNUSED,
1148              int *invalid)
1149 {
1150   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1151     *invalid = 1;
1152   return 0;
1153 }
1154
1155 /* The SH field in an MD form instruction.  This is split.  */
1156
1157 static unsigned long
1158 insert_sh6 (unsigned long insn,
1159             long value,
1160             int dialect ATTRIBUTE_UNUSED,
1161             const char **errmsg ATTRIBUTE_UNUSED)
1162 {
1163   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1164 }
1165
1166 static long
1167 extract_sh6 (unsigned long insn,
1168              int dialect ATTRIBUTE_UNUSED,
1169              int *invalid ATTRIBUTE_UNUSED)
1170 {
1171   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1172 }
1173
1174 /* The SPR field in an XFX form instruction.  This is flipped--the
1175    lower 5 bits are stored in the upper 5 and vice- versa.  */
1176
1177 static unsigned long
1178 insert_spr (unsigned long insn,
1179             long value,
1180             int dialect ATTRIBUTE_UNUSED,
1181             const char **errmsg ATTRIBUTE_UNUSED)
1182 {
1183   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1184 }
1185
1186 static long
1187 extract_spr (unsigned long insn,
1188              int dialect ATTRIBUTE_UNUSED,
1189              int *invalid ATTRIBUTE_UNUSED)
1190 {
1191   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1192 }
1193
1194 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1195
1196 static unsigned long
1197 insert_sprg (unsigned long insn,
1198              long value,
1199              int dialect,
1200              const char **errmsg)
1201 {
1202   /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1203      as a synonym.  If ever a 405 specific dialect is added this
1204      check should use that instead.  */
1205   if (value > 7
1206       || (value > 3
1207           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1208     *errmsg = _("invalid sprg number");
1209
1210   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1211      user mode.  Anything else must use spr 272..279.  */
1212   if (value <= 3 || (insn & 0x100) != 0)
1213     value |= 0x10;
1214
1215   return insn | ((value & 0x17) << 16);
1216 }
1217
1218 static long
1219 extract_sprg (unsigned long insn,
1220               int dialect,
1221               int *invalid)
1222 {
1223   unsigned long val = (insn >> 16) & 0x1f;
1224
1225   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1226      If not BOOKE or 405, then both use only 272..275.  */
1227   if (val <= 3
1228       || (val < 0x10 && (insn & 0x100) != 0)
1229       || (val - 0x10 > 3
1230           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1231     *invalid = 1;
1232   return val & 7;
1233 }
1234
1235 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1236    is optional.  When TBR is omitted, it must be inserted as 268 (the
1237    magic number of the TB register).  These functions treat 0
1238    (indicating an omitted optional operand) as 268.  This means that
1239    ``mftb 4,0'' is not handled correctly.  This does not matter very
1240    much, since the architecture manual does not define mftb as
1241    accepting any values other than 268 or 269.  */
1242
1243 #define TB (268)
1244
1245 static unsigned long
1246 insert_tbr (unsigned long insn,
1247             long value,
1248             int dialect ATTRIBUTE_UNUSED,
1249             const char **errmsg ATTRIBUTE_UNUSED)
1250 {
1251   if (value == 0)
1252     value = TB;
1253   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1254 }
1255
1256 static long
1257 extract_tbr (unsigned long insn,
1258              int dialect ATTRIBUTE_UNUSED,
1259              int *invalid ATTRIBUTE_UNUSED)
1260 {
1261   long ret;
1262
1263   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1264   if (ret == TB)
1265     ret = 0;
1266   return ret;
1267 }
1268 \f
1269 /* Macros used to form opcodes.  */
1270
1271 /* The main opcode.  */
1272 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1273 #define OP_MASK OP (0x3f)
1274
1275 /* The main opcode combined with a trap code in the TO field of a D
1276    form instruction.  Used for extended mnemonics for the trap
1277    instructions.  */
1278 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1279 #define OPTO_MASK (OP_MASK | TO_MASK)
1280
1281 /* The main opcode combined with a comparison size bit in the L field
1282    of a D form or X form instruction.  Used for extended mnemonics for
1283    the comparison instructions.  */
1284 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1285 #define OPL_MASK OPL (0x3f,1)
1286
1287 /* An A form instruction.  */
1288 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1289 #define A_MASK A (0x3f, 0x1f, 1)
1290
1291 /* An A_MASK with the FRB field fixed.  */
1292 #define AFRB_MASK (A_MASK | FRB_MASK)
1293
1294 /* An A_MASK with the FRC field fixed.  */
1295 #define AFRC_MASK (A_MASK | FRC_MASK)
1296
1297 /* An A_MASK with the FRA and FRC fields fixed.  */
1298 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1299
1300 /* An AFRAFRC_MASK, but with L bit clear.  */
1301 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1302
1303 /* A B form instruction.  */
1304 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1305 #define B_MASK B (0x3f, 1, 1)
1306
1307 /* A B form instruction setting the BO field.  */
1308 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1309 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1310
1311 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1312    matching a conditional branch regardless of the setting of the y
1313    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1314 #define Y_MASK   (((unsigned long) 1) << 21)
1315 #define AT1_MASK (((unsigned long) 3) << 21)
1316 #define AT2_MASK (((unsigned long) 9) << 21)
1317 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1318 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1319
1320 /* A B form instruction setting the BO field and the condition bits of
1321    the BI field.  */
1322 #define BBOCB(op, bo, cb, aa, lk) \
1323   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1324 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1325
1326 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1327 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1328 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1329 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1330
1331 /* A BBOYCB_MASK in which the BI field is fixed.  */
1332 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1333 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1334
1335 /* An Context form instruction.  */
1336 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1337 #define CTX_MASK CTX(0x3f, 0x7)
1338
1339 /* An User Context form instruction.  */
1340 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1341 #define UCTX_MASK UCTX(0x3f, 0x1f)
1342
1343 /* The main opcode mask with the RA field clear.  */
1344 #define DRA_MASK (OP_MASK | RA_MASK)
1345
1346 /* A DS form instruction.  */
1347 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1348 #define DS_MASK DSO (0x3f, 3)
1349
1350 /* A DE form instruction.  */
1351 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1352 #define DE_MASK DEO (0x3e, 0xf)
1353
1354 /* An EVSEL form instruction.  */
1355 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1356 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1357
1358 /* An M form instruction.  */
1359 #define M(op, rc) (OP (op) | ((rc) & 1))
1360 #define M_MASK M (0x3f, 1)
1361
1362 /* An M form instruction with the ME field specified.  */
1363 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1364
1365 /* An M_MASK with the MB and ME fields fixed.  */
1366 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1367
1368 /* An M_MASK with the SH and ME fields fixed.  */
1369 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1370
1371 /* An MD form instruction.  */
1372 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1373 #define MD_MASK MD (0x3f, 0x7, 1)
1374
1375 /* An MD_MASK with the MB field fixed.  */
1376 #define MDMB_MASK (MD_MASK | MB6_MASK)
1377
1378 /* An MD_MASK with the SH field fixed.  */
1379 #define MDSH_MASK (MD_MASK | SH6_MASK)
1380
1381 /* An MDS form instruction.  */
1382 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1383 #define MDS_MASK MDS (0x3f, 0xf, 1)
1384
1385 /* An MDS_MASK with the MB field fixed.  */
1386 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1387
1388 /* An SC form instruction.  */
1389 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1390 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1391
1392 /* An VX form instruction.  */
1393 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1394
1395 /* The mask for an VX form instruction.  */
1396 #define VX_MASK VX(0x3f, 0x7ff)
1397
1398 /* An VA form instruction.  */
1399 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1400
1401 /* The mask for an VA form instruction.  */
1402 #define VXA_MASK VXA(0x3f, 0x3f)
1403
1404 /* An VXR form instruction.  */
1405 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1406
1407 /* The mask for a VXR form instruction.  */
1408 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1409
1410 /* An X form instruction.  */
1411 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1412
1413 /* A Z form instruction.  */
1414 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1415
1416 /* An X form instruction with the RC bit specified.  */
1417 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1418
1419 /* A Z form instruction with the RC bit specified.  */
1420 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1421
1422 /* The mask for an X form instruction.  */
1423 #define X_MASK XRC (0x3f, 0x3ff, 1)
1424
1425 /* The mask for a Z form instruction.  */
1426 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1427 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1428
1429 /* An X_MASK with the RA field fixed.  */
1430 #define XRA_MASK (X_MASK | RA_MASK)
1431
1432 /* An X_MASK with the RB field fixed.  */
1433 #define XRB_MASK (X_MASK | RB_MASK)
1434
1435 /* An X_MASK with the RT field fixed.  */
1436 #define XRT_MASK (X_MASK | RT_MASK)
1437
1438 /* An XRT_MASK mask with the L bits clear.  */
1439 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1440
1441 /* An X_MASK with the RA and RB fields fixed.  */
1442 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1443
1444 /* An XRARB_MASK, but with the L bit clear.  */
1445 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1446
1447 /* An X_MASK with the RT and RA fields fixed.  */
1448 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1449
1450 /* An XRTRA_MASK, but with L bit clear.  */
1451 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1452
1453 /* An X form instruction with the L bit specified.  */
1454 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1455
1456 /* The mask for an X form comparison instruction.  */
1457 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1458
1459 /* The mask for an X form comparison instruction with the L field
1460    fixed.  */
1461 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1462
1463 /* An X form trap instruction with the TO field specified.  */
1464 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1465 #define XTO_MASK (X_MASK | TO_MASK)
1466
1467 /* An X form tlb instruction with the SH field specified.  */
1468 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1469 #define XTLB_MASK (X_MASK | SH_MASK)
1470
1471 /* An X form sync instruction.  */
1472 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1473
1474 /* An X form sync instruction with everything filled in except the LS field.  */
1475 #define XSYNC_MASK (0xff9fffff)
1476
1477 /* An X_MASK, but with the EH bit clear.  */
1478 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1479
1480 /* An X form AltiVec dss instruction.  */
1481 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1482 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1483
1484 /* An XFL form instruction.  */
1485 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1486 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1487
1488 /* An X form isel instruction.  */
1489 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1490 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1491
1492 /* An XL form instruction with the LK field set to 0.  */
1493 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1494
1495 /* An XL form instruction which uses the LK field.  */
1496 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1497
1498 /* The mask for an XL form instruction.  */
1499 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1500
1501 /* An XL form instruction which explicitly sets the BO field.  */
1502 #define XLO(op, bo, xop, lk) \
1503   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1504 #define XLO_MASK (XL_MASK | BO_MASK)
1505
1506 /* An XL form instruction which explicitly sets the y bit of the BO
1507    field.  */
1508 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1509 #define XLYLK_MASK (XL_MASK | Y_MASK)
1510
1511 /* An XL form instruction which sets the BO field and the condition
1512    bits of the BI field.  */
1513 #define XLOCB(op, bo, cb, xop, lk) \
1514   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1515 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1516
1517 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1518 #define XLBB_MASK (XL_MASK | BB_MASK)
1519 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1520 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1521
1522 /* A mask for branch instructions using the BH field.  */
1523 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1524
1525 /* An XL_MASK with the BO and BB fields fixed.  */
1526 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1527
1528 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1529 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1530
1531 /* An XO form instruction.  */
1532 #define XO(op, xop, oe, rc) \
1533   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1534 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1535
1536 /* An XO_MASK with the RB field fixed.  */
1537 #define XORB_MASK (XO_MASK | RB_MASK)
1538
1539 /* An XS form instruction.  */
1540 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1541 #define XS_MASK XS (0x3f, 0x1ff, 1)
1542
1543 /* A mask for the FXM version of an XFX form instruction.  */
1544 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1545
1546 /* An XFX form instruction with the FXM field filled in.  */
1547 #define XFXM(op, xop, fxm, p4) \
1548   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1549    | ((unsigned long)(p4) << 20))
1550
1551 /* An XFX form instruction with the SPR field filled in.  */
1552 #define XSPR(op, xop, spr) \
1553   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1554 #define XSPR_MASK (X_MASK | SPR_MASK)
1555
1556 /* An XFX form instruction with the SPR field filled in except for the
1557    SPRBAT field.  */
1558 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1559
1560 /* An XFX form instruction with the SPR field filled in except for the
1561    SPRG field.  */
1562 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1563
1564 /* An X form instruction with everything filled in except the E field.  */
1565 #define XE_MASK (0xffff7fff)
1566
1567 /* An X form user context instruction.  */
1568 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1569 #define XUC_MASK      XUC(0x3f, 0x1f)
1570
1571 /* The BO encodings used in extended conditional branch mnemonics.  */
1572 #define BODNZF  (0x0)
1573 #define BODNZFP (0x1)
1574 #define BODZF   (0x2)
1575 #define BODZFP  (0x3)
1576 #define BODNZT  (0x8)
1577 #define BODNZTP (0x9)
1578 #define BODZT   (0xa)
1579 #define BODZTP  (0xb)
1580
1581 #define BOF     (0x4)
1582 #define BOFP    (0x5)
1583 #define BOFM4   (0x6)
1584 #define BOFP4   (0x7)
1585 #define BOT     (0xc)
1586 #define BOTP    (0xd)
1587 #define BOTM4   (0xe)
1588 #define BOTP4   (0xf)
1589
1590 #define BODNZ   (0x10)
1591 #define BODNZP  (0x11)
1592 #define BODZ    (0x12)
1593 #define BODZP   (0x13)
1594 #define BODNZM4 (0x18)
1595 #define BODNZP4 (0x19)
1596 #define BODZM4  (0x1a)
1597 #define BODZP4  (0x1b)
1598
1599 #define BOU     (0x14)
1600
1601 /* The BI condition bit encodings used in extended conditional branch
1602    mnemonics.  */
1603 #define CBLT    (0)
1604 #define CBGT    (1)
1605 #define CBEQ    (2)
1606 #define CBSO    (3)
1607
1608 /* The TO encodings used in extended trap mnemonics.  */
1609 #define TOLGT   (0x1)
1610 #define TOLLT   (0x2)
1611 #define TOEQ    (0x4)
1612 #define TOLGE   (0x5)
1613 #define TOLNL   (0x5)
1614 #define TOLLE   (0x6)
1615 #define TOLNG   (0x6)
1616 #define TOGT    (0x8)
1617 #define TOGE    (0xc)
1618 #define TONL    (0xc)
1619 #define TOLT    (0x10)
1620 #define TOLE    (0x14)
1621 #define TONG    (0x14)
1622 #define TONE    (0x18)
1623 #define TOU     (0x1f)
1624 \f
1625 /* Smaller names for the flags so each entry in the opcodes table will
1626    fit on a single line.  */
1627 #undef  PPC
1628 #define PPC     PPC_OPCODE_PPC
1629 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1630 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1631 #define POWER4  PPC_OPCODE_POWER4
1632 #define POWER5  PPC_OPCODE_POWER5
1633 #define POWER6  PPC_OPCODE_POWER6
1634 #define CELL    PPC_OPCODE_CELL
1635 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1636 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1637 #define PPC403  PPC_OPCODE_403
1638 #define PPC405  PPC403
1639 #define PPC440  PPC_OPCODE_440
1640 #define PPC750  PPC
1641 #define PPC860  PPC
1642 #define PPCVEC  PPC_OPCODE_ALTIVEC
1643 #define POWER   PPC_OPCODE_POWER
1644 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1645 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1646 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1647 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1648 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1649 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1650 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1651 #define MFDEC1  PPC_OPCODE_POWER
1652 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1653 #define BOOKE   PPC_OPCODE_BOOKE
1654 #define BOOKE64 PPC_OPCODE_BOOKE64
1655 #define CLASSIC PPC_OPCODE_CLASSIC
1656 #define PPCE300 PPC_OPCODE_E300
1657 #define PPCSPE  PPC_OPCODE_SPE
1658 #define PPCISEL PPC_OPCODE_ISEL
1659 #define PPCEFS  PPC_OPCODE_EFS
1660 #define PPCBRLK PPC_OPCODE_BRLOCK
1661 #define PPCPMR  PPC_OPCODE_PMR
1662 #define PPCCHLK PPC_OPCODE_CACHELCK
1663 #define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1664 #define PPCRFMCI        PPC_OPCODE_RFMCI
1665 \f
1666 /* The opcode table.
1667
1668    The format of the opcode table is:
1669
1670    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1671
1672    NAME is the name of the instruction.
1673    OPCODE is the instruction opcode.
1674    MASK is the opcode mask; this is used to tell the disassembler
1675      which bits in the actual opcode must match OPCODE.
1676    FLAGS are flags indicated what processors support the instruction.
1677    OPERANDS is the list of operands.
1678
1679    The disassembler reads the table in order and prints the first
1680    instruction which matches, so this table is sorted to put more
1681    specific instructions before more general instructions.  It is also
1682    sorted by major opcode.  */
1683
1684 const struct powerpc_opcode powerpc_opcodes[] = {
1685 { "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
1686 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1687 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1688 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1689 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1690 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1691 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1692 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1693 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1694 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1695 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1696 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1697 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1698 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1699 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1700 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1701
1702 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1703 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1704 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1705 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1706 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1707 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1708 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1709 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1710 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1711 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1712 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1713 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1714 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1715 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1716 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1717 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1718 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1719 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1720 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1721 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1722 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1723 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1724 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1725 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1726 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1727 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1728 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1729 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1730 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1731 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1732
1733 { "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1734 { "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1735 { "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1736 { "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1737 { "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1738 { "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1739 { "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1740 { "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1741 { "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1742 { "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1743 { "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1744 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1745 { "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1746 { "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1747 { "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1748 { "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1749 { "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1750 { "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1751 { "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1752 { "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1753 { "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1754 { "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1755 { "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1756 { "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1757 { "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1758 { "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1759 { "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1760 { "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1761 { "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1762 { "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1763 { "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1764 { "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1765 { "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1766 { "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1767 { "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1768 { "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1769 { "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1770 { "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1771 { "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1772 { "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1773 { "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1774 { "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1775 { "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1776 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1777 { "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1778 { "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1779 { "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1780 { "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1781 { "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1782 { "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1783 { "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1784 { "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1785 { "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1786 { "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1787 { "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1788 { "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1789 { "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1790 { "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1791 { "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1792 { "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
1793 { "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1794 { "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1795 { "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1796 { "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1797 { "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1798 { "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1799 { "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1800 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1801 { "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1802 { "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1803 { "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1804 { "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1805 { "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1806 { "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1807 { "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1808 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1809 { "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1810 { "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1811 { "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1812 { "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1813 { "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1814 { "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1815 { "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1816 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
1817 { "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
1818 { "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
1819
1820   /* Double-precision opcodes.  */
1821   /* Some of these conflict with AltiVec, so move them before, since
1822      PPCVEC includes the PPC_OPCODE_PPC set.  */
1823 { "efscfd",   VX(4, 719), VX_MASK,      PPCEFS,         { RS, RB } },
1824 { "efdabs",   VX(4, 740), VX_MASK,      PPCEFS,         { RS, RA } },
1825 { "efdnabs",  VX(4, 741), VX_MASK,      PPCEFS,         { RS, RA } },
1826 { "efdneg",   VX(4, 742), VX_MASK,      PPCEFS,         { RS, RA } },
1827 { "efdadd",   VX(4, 736), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1828 { "efdsub",   VX(4, 737), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1829 { "efdmul",   VX(4, 744), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1830 { "efddiv",   VX(4, 745), VX_MASK,      PPCEFS,         { RS, RA, RB } },
1831 { "efdcmpgt", VX(4, 748), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1832 { "efdcmplt", VX(4, 749), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1833 { "efdcmpeq", VX(4, 750), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1834 { "efdtstgt", VX(4, 764), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1835 { "efdtstlt", VX(4, 765), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1836 { "efdtsteq", VX(4, 766), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
1837 { "efdcfsi",  VX(4, 753), VX_MASK,      PPCEFS,         { RS, RB } },
1838 { "efdcfsid", VX(4, 739), VX_MASK,      PPCEFS,         { RS, RB } },
1839 { "efdcfui",  VX(4, 752), VX_MASK,      PPCEFS,         { RS, RB } },
1840 { "efdcfuid", VX(4, 738), VX_MASK,      PPCEFS,         { RS, RB } },
1841 { "efdcfsf",  VX(4, 755), VX_MASK,      PPCEFS,         { RS, RB } },
1842 { "efdcfuf",  VX(4, 754), VX_MASK,      PPCEFS,         { RS, RB } },
1843 { "efdctsi",  VX(4, 757), VX_MASK,      PPCEFS,         { RS, RB } },
1844 { "efdctsidz",VX(4, 747), VX_MASK,      PPCEFS,         { RS, RB } },
1845 { "efdctsiz", VX(4, 762), VX_MASK,      PPCEFS,         { RS, RB } },
1846 { "efdctui",  VX(4, 756), VX_MASK,      PPCEFS,         { RS, RB } },
1847 { "efdctuidz",VX(4, 746), VX_MASK,      PPCEFS,         { RS, RB } },
1848 { "efdctuiz", VX(4, 760), VX_MASK,      PPCEFS,         { RS, RB } },
1849 { "efdctsf",  VX(4, 759), VX_MASK,      PPCEFS,         { RS, RB } },
1850 { "efdctuf",  VX(4, 758), VX_MASK,      PPCEFS,         { RS, RB } },
1851 { "efdcfs",   VX(4, 751), VX_MASK,      PPCEFS,         { RS, RB } },
1852   /* End of double-precision opcodes.  */
1853
1854 { "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1855 { "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1856 { "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1857 { "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1858 { "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1859 { "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1860 { "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1861 { "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1862 { "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1863 { "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1864 { "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1865 { "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1866 { "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1867 { "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1868 { "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1869 { "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1870 { "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1871 { "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1872 { "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
1873 { "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1874 { "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
1875 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1876 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1877 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1878 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1879 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1880 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1881 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1882 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1883 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1884 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1885 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1886 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1887 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1888 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1889 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1890 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1891 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1892 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1893 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1894 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1895 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1896 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1897 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1898 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1899 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1900 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
1901 { "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1902 { "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1903 { "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
1904 { "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
1905 { "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1906 { "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1907 { "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1908 { "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1909 { "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1910 { "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1911 { "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1912 { "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1913 { "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1914 { "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1915 { "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1916 { "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1917 { "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1918 { "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1919 { "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1920 { "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1921 { "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1922 { "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1923 { "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1924 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1925 { "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1926 { "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1927 { "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1928 { "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1929 { "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1930 { "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1931 { "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1932 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1933 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1934 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1935 { "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1936 { "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1937 { "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1938 { "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1939 { "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1940 { "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1941 { "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1942 { "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1943 { "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
1944 { "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1945 { "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1946 { "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1947 { "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1948 { "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1949 { "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1950 { "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1951 { "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1952 { "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1953 { "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1954 { "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1955 { "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1956 { "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
1957 { "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
1958 { "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
1959 { "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
1960 { "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
1961 { "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1962 { "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1963 { "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1964 { "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
1965 { "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
1966 { "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1967 { "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1968 { "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
1969 { "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1970 { "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1971 { "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1972 { "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1973 { "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1974 { "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
1975 { "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
1976 { "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
1977 { "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
1978 { "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1979 { "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1980 { "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1981 { "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1982 { "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1983 { "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1984 { "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1985 { "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1986 { "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1987 { "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1988 { "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1989 { "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1990 { "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1991 { "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1992 { "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1993 { "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1994 { "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1995 { "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1996 { "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1997 { "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1998 { "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
1999 { "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2000 { "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2001 { "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2002 { "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
2003 { "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
2004 { "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
2005 { "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
2006 { "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
2007 { "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
2008 { "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
2009
2010 { "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2011 { "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2012 { "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2013 { "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
2014 { "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
2015 { "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
2016 { "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
2017 { "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
2018 { "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
2019 { "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
2020 { "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
2021 { "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
2022 { "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
2023
2024 { "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2025
2026 { "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2027 { "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2028 { "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2029 { "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2030 { "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2031 { "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2032 { "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2033 { "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2034 { "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
2035 { "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2036
2037 { "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2038 { "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2039 { "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2040 { "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2041 { "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2042 { "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2043 { "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2044 { "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
2045 { "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
2046 { "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
2047 { "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2048 { "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2049 { "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2050 { "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2051
2052 { "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2053 { "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2054 { "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2055 { "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2056 { "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2057 { "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
2058
2059 { "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2060 { "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2061 { "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2062 { "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2063 { "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2064 { "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2065 { "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2066 { "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2067 { "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2068 { "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2069 { "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2070 { "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2071 { "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2072 { "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2073 { "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2074 { "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2075 { "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
2076 { "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2077 { "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2078 { "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2079 { "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
2080 { "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
2081
2082 { "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2083 { "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2084 { "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2085 { "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2086 { "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
2087 { "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2088 { "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2089 { "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2090 { "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2091 { "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2092 { "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2093 { "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2094 { "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
2095 { "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2096
2097 { "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
2098 { "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
2099 { "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
2100 { "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2101 { "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2102 { "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2103 { "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2104 { "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2105 { "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2106 { "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2107 { "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2108 { "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2109 { "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
2110 { "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
2111 { "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
2112 { "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
2113 { "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
2114 { "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
2115 { "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
2116 { "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
2117 { "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
2118 { "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
2119 { "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
2120
2121 { "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
2122 { "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
2123 { "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
2124 { "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2125 { "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2126 { "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2127 { "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
2128 { "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2129 { "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2130 { "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2131 { "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2132 { "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2133 { "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
2134 { "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
2135 { "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
2136 { "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
2137 { "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
2138 { "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
2139 { "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
2140 { "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
2141 { "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
2142 { "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
2143 { "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
2144
2145 { "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2146 { "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2147 { "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2148 { "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2149 { "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2150 { "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2151 { "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2152 { "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2153 { "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2154 { "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2155 { "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2156 { "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2157 { "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2158 { "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2159 { "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2160 { "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2161
2162 { "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2163 { "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2164 { "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2165 { "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2166 { "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2167 { "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2168 { "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2169 { "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2170 { "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2171 { "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2172 { "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2173 { "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2174
2175 { "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2176 { "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2177 { "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2178 { "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2179 { "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2180 { "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2181 { "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2182 { "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2183 { "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2184 { "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2185 { "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2186 { "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2187
2188 { "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2189 { "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2190 { "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2191 { "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2192 { "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2193 { "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2194
2195 { "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2196 { "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2197 { "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2198 { "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2199 { "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2200 { "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2201
2202 { "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2203 { "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2204 { "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2205 { "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2206 { "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2207 { "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2208 { "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2209 { "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2210
2211 { "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2212 { "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2213
2214 { "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2215 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2216 { "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2217 { "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2218
2219 { "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2220 { "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2221 { "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2222 { "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
2223
2224 { "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2225 { "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2226 { "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2227 { "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2228 { "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2229 { "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2230 { "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2231 { "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2232
2233 { "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2234 { "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2235 { "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2236 { "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2237
2238 { "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2239 { "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2240 { "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2241 { "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
2242
2243 { "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
2244 { "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
2245 { "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
2246 { "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
2247
2248 { "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
2249 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
2250 { "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
2251 { "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
2252
2253 { "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
2254
2255 { "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2256 { "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
2257
2258 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2259 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2260
2261 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
2262 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
2263
2264 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
2265
2266 { "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2267 { "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
2268 { "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2269 { "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
2270
2271 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
2272 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
2273 { "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
2274 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
2275
2276 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
2277 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
2278 { "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
2279 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
2280
2281 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2282 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2283 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2284
2285 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
2286 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
2287 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
2288
2289 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
2290 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
2291 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, SI } },
2292 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
2293 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2294 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
2295
2296 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
2297 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
2298 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA0,SISIGNOPT } },
2299 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA0,SISIGNOPT } },
2300 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
2301
2302 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
2303 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
2304 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
2305 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
2306 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
2307 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
2308 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
2309 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
2310 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2311 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2312 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
2313 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
2314 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
2315 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
2316 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
2317 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
2318 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
2319 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
2320 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
2321 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
2322 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
2323 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
2324 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2325 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2326 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
2327 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
2328 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
2329 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
2330 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2331 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2332 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2333 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2334 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2335 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2336 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2337 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2338 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2339 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2340 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2341 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2342 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2343 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2344 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2345 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2346 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2347 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2348 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2349 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2350 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2351 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2352 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2353 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2354 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2355 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2356 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2357 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2358 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2359 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2360 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2361 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2362 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2363 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2364 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2365 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2366 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2367 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2368 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2369 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2370 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2371 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2372 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2373 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2374 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2375 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2376 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2377 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2378 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2379 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2380 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2381 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2382 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2383 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2384 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2385 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2386 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2387 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2388 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2389 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2390 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2391 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2392 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2393 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2394 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2395 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2396 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2397 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2398 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2399 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2400 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2401 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2402 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2403 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2404 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2405 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2406 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2407 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2408 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2409 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2410 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2411 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2412 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2413 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2414 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2415 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2416 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2417 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2418 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2419 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2420 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2421 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2422 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2423 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2424 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2425 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2426 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2427 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2428 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2429 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2430 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2431 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2432 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2433 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2434 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2435 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2436 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2437 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2438 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2439 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2440 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2441 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2442 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2443 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2444 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2445 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2446 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2447 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2448 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2449 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2450 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2451 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2452 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
2453 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2454 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2455 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
2456 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2457 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2458 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
2459 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2460 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2461 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
2462 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2463 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2464 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2465 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
2466 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
2467 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
2468 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2469 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2470 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2471 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
2472 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
2473 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
2474 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2475 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2476 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2477 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2478 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2479 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2480 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2481 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2482 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2483 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2484 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2485 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2486 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2487 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2488 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
2489 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
2490 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
2491 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
2492 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2493 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2494 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
2495 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
2496 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
2497 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
2498 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2499 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2500 { "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2501 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2502 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2503 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2504 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2505 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2506 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2507 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2508 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2509 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2510 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2511 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2512 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2513 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2514 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2515 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2516 { "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
2517 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
2518 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
2519 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
2520 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
2521 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
2522 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2523 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2524 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2525 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2526 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
2527 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
2528 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
2529 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
2530 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2531 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2532 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2533 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2534 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2535 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2536 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2537 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2538 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2539 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2540 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2541 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2542 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2543 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2544 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
2545 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
2546 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
2547 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
2548 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2549 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2550 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
2551 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
2552 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
2553 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
2554 { "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2555 { "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2556 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
2557 { "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
2558 { "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
2559 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
2560 { "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2561 { "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2562 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
2563 { "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
2564 { "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
2565 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
2566
2567 { "sc",      SC(17,1,0), SC_MASK,       PPC,            { LEV } },
2568 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { SVC_LEV, FL1, FL2 } },
2569 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { SVC_LEV, FL1, FL2 } },
2570 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
2571 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
2572
2573 { "b",       B(18,0,0), B_MASK,         COM,            { LI } },
2574 { "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
2575 { "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
2576 { "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
2577
2578 { "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
2579
2580 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2581 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2582 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
2583 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
2584 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2585 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2586 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2587 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2588 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
2589 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2590 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2591 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2592 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
2593 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
2594 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2595 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2596 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2597 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2598 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
2599 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
2600 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
2601 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2602 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
2603 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
2604 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2605 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2606 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2607 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2608 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2609 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2610 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2611 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2612 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2613 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2614 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2615 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2616 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2617 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2618 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2619 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2620 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2621 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2622 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2623 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2624 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2625 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2626 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2627 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2628 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2629 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2630 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2631 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2632 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2633 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2634 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2635 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2636 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2637 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2638 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2639 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2640 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2641 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2642 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2643 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2644 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2645 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2646 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2647 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2648 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2649 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2650 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2651 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2652 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2653 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2654 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2655 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2656 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2657 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2658 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2659 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2660 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2661 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2662 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2663 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2664 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2665 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2666 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2667 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2668 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2669 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2670 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2671 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2672 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2673 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2674 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2675 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2676 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2677 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2678 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2679 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2680 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2681 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2682 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2683 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2684 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2685 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2686 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2687 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2688 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2689 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2690 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2691 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2692 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2693 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2694 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2695 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2696 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2697 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2698 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2699 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2700 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2701 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2702 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2703 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2704 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2705 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2706 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2707 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2708 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2709 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2710 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2711 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2712 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2713 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2715 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2716 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2717 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2718 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2719 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2720 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2721 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2722 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2723 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2724 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2725 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2727 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2728 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2729 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2730 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2731 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2733 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2734 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2735 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2736 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2737 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2739 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2740 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2741 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2742 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2744 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2745 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2746 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2747 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2748 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2749 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2750 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2751 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2752 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2753 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2754 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2755 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2756 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
2757 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
2758 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2759 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
2760 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
2761 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
2762 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
2763 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
2764 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2765 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
2766 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
2767 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
2768 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2769 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2770 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2771 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2772 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2773 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2774 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
2775 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2776 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2777 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
2778 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2779 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2780 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2781 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2782 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2783 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2784 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2785 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2786 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
2787 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2788 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2789 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
2790 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2791 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2792 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2793 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2794 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2795 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
2796 { "bclr",    XLLK(19,16,0), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2797 { "bclrl",   XLLK(19,16,1), XLBH_MASK,  PPCCOM,         { BO, BI, BH } },
2798 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
2799 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
2800 { "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
2801 { "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
2802
2803 { "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
2804
2805 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
2806 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
2807 { "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
2808
2809 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
2810 { "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
2811
2812 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
2813
2814 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
2815
2816 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
2817 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
2818
2819 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2820 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
2821
2822 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
2823
2824 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
2825
2826 { "hrfid",   XL(19,274), 0xffffffff,    POWER5 | CELL,  { 0 } },
2827
2828 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
2829 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
2830
2831 { "doze",    XL(19,402), 0xffffffff,    POWER6,         { 0 } },
2832
2833 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
2834
2835 { "nap",     XL(19,434), 0xffffffff,    POWER6,         { 0 } },
2836
2837 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
2838 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
2839
2840 { "sleep",   XL(19,466), 0xffffffff,    POWER6,         { 0 } },
2841 { "rvwinkle", XL(19,498), 0xffffffff,   POWER6,         { 0 } },
2842
2843 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
2844 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
2845 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2846 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2847 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2848 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2849 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2850 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2851 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2852 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2853 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2854 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2855 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2856 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2857 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2858 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2859 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2860 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2861 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2862 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2863 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2864 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2865 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2866 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2867 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2868 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2869 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2870 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2871 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2872 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2873 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2874 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2875 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2876 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2877 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2878 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2879 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2880 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2881 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2882 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2883 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2884 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2885 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2886 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2887 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2888 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2889 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2890 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2891 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2892 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2893 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2894 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2895 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2896 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2897 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2898 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2899 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2900 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2901 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2902 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2903 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2904 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2905 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2906 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2907 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2908 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2909 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2910 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2911 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2912 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2913 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2914 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2915 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2916 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2917 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2918 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2919 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2920 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2921 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2922 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2923 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2924 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2925 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2926 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2927 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2928 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2929 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2930 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2931 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2932 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2933 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2934 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2935 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2936 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2937 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2938 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2940 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2941 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2942 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2943 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2945 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2946 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2947 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2948 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2950 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2951 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2952 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2953 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2955 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2956 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2957 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2958 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2960 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
2961 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
2962 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2963 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2965 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2966 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
2967 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2968 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2969 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2970 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2971 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
2972 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2973 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2974 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2975 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
2976 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
2977 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2978 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2979 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2980 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
2981 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
2982 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2983 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2984 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2985 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2986 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2987 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2988 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
2989 { "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
2990 { "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
2991 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2992 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
2993 { "bcctre",  XLLK(19,529,0),     XLBB_MASK,   BOOKE64,  { BO, BI } },
2994 { "bcctrel", XLLK(19,529,1),     XLBB_MASK,   BOOKE64,  { BO, BI } },
2995
2996 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
2997 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
2998
2999 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3000 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3001
3002 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
3003 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3004 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3005 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3006 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
3007 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
3008 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
3009 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
3010
3011 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3012 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
3013
3014 { "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
3015 { "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
3016 { "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
3017 { "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
3018
3019 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3020 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3021 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3022 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
3023 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
3024 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
3025
3026 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
3027 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3028 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3029
3030 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3031 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3032
3033 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3034 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3035
3036 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3037 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3038
3039 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3040 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3041
3042 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
3043 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
3044
3045 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3046 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3047 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3048 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
3049 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
3050 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3051
3052 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3053 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
3054
3055 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3056 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3057
3058 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3059 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
3060
3061 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3062 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3063 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
3064 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
3065
3066 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3067 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
3068
3069 { "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,          { OBF, RA, RB } },
3070 { "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,           { OBF, RA, RB } },
3071 { "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
3072 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
3073
3074 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
3075 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
3076 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
3077 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
3078 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
3079 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
3080 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
3081 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
3082 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
3083 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
3084 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
3085 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
3086 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
3087 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
3088 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
3089 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
3090 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
3091 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
3092 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
3093 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
3094 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
3095 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
3096 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
3097 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
3098 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
3099 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
3100 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
3101 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
3102 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
3103 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
3104 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
3105
3106 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3107 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3108 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
3109 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3110 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3111 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
3112 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3113 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3114 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
3115 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
3116 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
3117 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
3118
3119 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
3120 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
3121
3122 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3123 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3124 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3125 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3126 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3127 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3128 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
3129 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
3130
3131 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3132 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3133
3134 { "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3135 { "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3136 { "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
3137 { "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
3138
3139 { "mfocrf",  XFXM(31,19,0,1), XFXFXM_MASK, COM,         { RT, FXM } },
3140 { "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4 | COM, { RT } },
3141 { "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
3142
3143 { "lwarx",   X(31,20),  XEH_MASK,       PPC,            { RT, RA0, RB, EH } },
3144
3145 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA0, RB } },
3146
3147 { "icbt",    X(31,22),  X_MASK,         BOOKE|PPCE300,  { CT, RA, RB } },
3148 { "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
3149
3150 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA0, RB } },
3151 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3152
3153 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
3154 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
3155 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
3156 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
3157
3158 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
3159 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
3160 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
3161 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
3162
3163 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
3164 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
3165
3166 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
3167 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
3168
3169 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
3170 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
3171
3172 { "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
3173
3174 { "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3175
3176 { "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3177 { "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
3178 { "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
3179 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
3180
3181 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3182 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
3183 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3184 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
3185 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
3186 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
3187 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
3188 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
3189
3190 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
3191
3192 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
3193
3194 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
3195 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
3196
3197 { "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
3198
3199 { "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
3200
3201 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
3202 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
3203
3204 { "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
3205 { "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
3206
3207 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
3208 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
3209 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
3210 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
3211 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
3212 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
3213 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
3214 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
3215 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
3216 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
3217 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
3218 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
3219 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
3220 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
3221 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
3222
3223 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
3224 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
3225
3226 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
3227 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
3228
3229 { "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3230 { "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
3231
3232 { "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
3233
3234 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
3235
3236 { "ldarx",   X(31,84),  XEH_MASK,       PPC64,          { RT, RA0, RB, EH } },
3237
3238 { "dcbfl",   XOPL(31,86,1), XRT_MASK,   POWER5,         { RA, RB } },
3239 { "dcbf",    X(31,86),  XLRT_MASK,      PPC,            { RA, RB, XRT_L } },
3240
3241 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA0, RB } },
3242
3243 { "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
3244
3245 { "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA0, RB } },
3246
3247 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
3248 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
3249 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
3250 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
3251
3252 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3253 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3254 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3255 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3256
3257 { "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
3258
3259 { "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
3260
3261 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
3262
3263 { "popcntb", X(31,122), XRB_MASK,       POWER5,         { RA, RS } },
3264
3265 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
3266 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
3267 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
3268 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
3269
3270 { "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3271
3272 { "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3273
3274 { "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
3275
3276 { "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3277
3278 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3279 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3280 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3281 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3282 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3283 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3284 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3285 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3286
3287 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3288 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3289 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3290 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3291 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3292 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3293 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3294 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3295
3296 { "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3297
3298 { "mtocrf",  XFXM(31,144,0,1), XFXFXM_MASK, COM,        { FXM, RS } },
3299 { "mtcr",    XFXM(31,144,0xff,0), XRARB_MASK, COM,      { RS }},
3300 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
3301
3302 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
3303
3304 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA0, RB } },
3305
3306 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA0, RB } },
3307
3308 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA0, RB } },
3309 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
3310
3311 { "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA0, RB } },
3312
3313 { "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3314
3315 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
3316 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
3317
3318 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
3319 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
3320
3321 { "prtyw",   X(31,154), XRB_MASK,       POWER6,         { RA, RS } },
3322
3323 { "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
3324
3325 { "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3326 { "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3327
3328 { "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
3329
3330 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
3331
3332 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
3333 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA0, RB } },
3334
3335 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
3336 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
3337
3338 { "prtyd",   X(31,186), XRB_MASK,       POWER6,         { RA, RS } },
3339
3340 { "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3341
3342 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3343 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3344 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3345 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3346 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3347 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3348 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3349 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3350
3351 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3352 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3353 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3354 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3355 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3356 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3357 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3358 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3359
3360 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
3361
3362 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA0, RB } },
3363
3364 { "stbx",    X(31,215), X_MASK,         COM,            { RS, RA0, RB } },
3365
3366 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
3367 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
3368
3369 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
3370 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
3371
3372 { "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3373
3374 { "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3375
3376 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3377 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3378 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3379 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3380 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3381 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3382 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3383 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3384
3385 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3386 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3387 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3388 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3389
3390 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
3391 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
3392 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
3393 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
3394 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
3395 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
3396 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
3397 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
3398
3399 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3400 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3401 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3402 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3403 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3404 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3405 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3406 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3407
3408 { "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3409 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
3410 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
3411
3412 { "dcbtst",  X(31,246), X_MASK, PPC,                    { CT, RA, RB } },
3413
3414 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
3415
3416 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
3417 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
3418
3419 { "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
3420
3421 { "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3422
3423 { "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
3424
3425 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3426 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3427 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3428 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3429
3430 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3431 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3432 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3433 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3434 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3435 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3436 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
3437 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
3438
3439 { "tlbiel",  X(31,274), XRTLRA_MASK,    POWER4,         { RB, L } },
3440
3441 { "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
3442
3443 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
3444 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
3445
3446 { "dcbt",    X(31,278), X_MASK,         PPC,            { CT, RA, RB } },
3447
3448 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA0, RB } },
3449
3450 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
3451 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
3452
3453 { "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
3454
3455 { "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3456
3457 { "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
3458 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA0, RB } },
3459
3460 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
3461
3462 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
3463
3464 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
3465 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
3466
3467 { "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3468
3469 { "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
3470 { "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
3471 { "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
3472 { "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
3473 { "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
3474 { "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
3475 { "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
3476 { "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
3477 { "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
3478 { "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
3479 { "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
3480 { "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
3481 { "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
3482 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
3483 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
3484 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
3485 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
3486 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
3487 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
3488 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
3489 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
3490 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
3491 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
3492 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
3493 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
3494 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
3495 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
3496 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
3497 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
3498 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
3499 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
3500 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
3501 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
3502 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
3503 { "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
3504
3505 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3506 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3507 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3508 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3509
3510 { "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
3511
3512 { "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
3513 { "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
3514 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
3515 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
3516 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
3517 { "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
3518 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
3519 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
3520 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
3521 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
3522 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
3523 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
3524 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
3525 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
3526 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
3527 { "mfcfar",     XSPR(31,339,28),   XSPR_MASK, POWER6,   { RT } },
3528 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3529 { "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
3530 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3531 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3532 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3533 { "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
3534 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3535 { "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
3536 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3537 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
3538 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
3539 { "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
3540 { "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
3541 { "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
3542 { "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
3543 { "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
3544 { "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
3545 { "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
3546 { "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
3547 { "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
3548 { "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
3549 { "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
3550 { "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
3551 { "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
3552 { "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
3553 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
3554 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3555 { "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
3556 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3557 { "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
3558 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3559 { "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
3560 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3561 { "mfsprg",     XSPR(31,339,256),  XSPRG_MASK, PPC,     { RT, SPRG } },
3562 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
3563 { "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
3564 { "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
3565 { "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
3566 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3567 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3568 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3569 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405 | BOOKE,   { RT } },
3570 { "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
3571 { "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
3572 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3573 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
3574 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3575 { "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
3576 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3577 { "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
3578 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3579 { "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
3580 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3581 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3582 { "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
3583 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3584 { "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
3585 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3586 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
3587 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3588 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
3589 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3590 { "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
3591 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3592 { "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
3593 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3594 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
3595 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3596 { "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
3597 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3598 { "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
3599 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3600 { "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
3601 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3602 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3603 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3604 { "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3605 { "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3606 { "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3607 { "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3608 { "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3609 { "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3610 { "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3611 { "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3612 { "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3613 { "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3614 { "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3615 { "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3616 { "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3617 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
3618 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3619 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3620 { "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,   { RT } },
3621 { "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,   { RT } },
3622 { "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,   { RT } },
3623 { "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,   { RT } },
3624 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3625 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3626 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3627 { "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
3628 { "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
3629 { "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
3630 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
3631 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
3632 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
3633 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3634 { "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
3635 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3636 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3637 { "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3638 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
3639 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
3640 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
3641 { "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
3642 { "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
3643 { "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
3644 { "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
3645 { "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
3646 { "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
3647 { "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
3648 { "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
3649 { "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
3650 { "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
3651 { "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
3652 { "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
3653 { "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
3654 { "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
3655 { "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
3656 { "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
3657 { "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
3658 { "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
3659 { "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
3660 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3661 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3662 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3663 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3664 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3665 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3666 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3667 { "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
3668 { "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
3669 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
3670 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
3671 { "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
3672 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
3673 { "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
3674 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
3675 { "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
3676 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
3677 { "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
3678 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
3679 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
3680 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
3681 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
3682 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
3683 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
3684 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
3685 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
3686 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
3687 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
3688 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
3689 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
3690 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
3691 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
3692 { "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
3693 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
3694 { "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
3695 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
3696 { "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
3697 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
3698 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
3699 { "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
3700
3701 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA0, RB } },
3702
3703 { "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3704 { "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3705
3706 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA0, RB } },
3707
3708 { "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA0, RB } },
3709
3710 { "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3711 { "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
3712
3713 { "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
3714
3715 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
3716 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
3717 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
3718 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
3719
3720 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
3721 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
3722 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
3723 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
3724
3725 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
3726
3727 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
3728
3729 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
3730
3731 { "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
3732
3733 { "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
3734
3735 { "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
3736
3737 { "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3738 { "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3739
3740 { "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3741 { "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
3742
3743 { "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
3744
3745 { "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
3746
3747 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA0, RB } },
3748
3749 { "cmpb",    X(31,508), X_MASK,         POWER6,         { RA, RS, RB } },
3750
3751 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
3752
3753 { "lfdpx",   X(31,791), X_MASK,         POWER6,         { FRT, RA, RB } },
3754
3755 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
3756
3757 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
3758
3759 { "stfdpx",  X(31,919), X_MASK,         POWER6,         { FRS, RA, RB } },
3760
3761 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
3762
3763 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
3764 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
3765
3766 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3767 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
3768
3769 { "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA0, RB } },
3770
3771 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
3772
3773 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
3774
3775 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
3776
3777 { "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
3778
3779 { "cctpl",   0x7c210b78,    0xffffffff, CELL,           { 0 }},
3780 { "cctpm",   0x7c421378,    0xffffffff, CELL,           { 0 }},
3781 { "cctph",   0x7c631b78,    0xffffffff, CELL,           { 0 }},
3782 { "db8cyc",  0x7f9ce378,    0xffffffff, CELL,           { 0 }},
3783 { "db10cyc", 0x7fbdeb78,    0xffffffff, CELL,           { 0 }},
3784 { "db12cyc", 0x7fdef378,    0xffffffff, CELL,           { 0 }},
3785 { "db16cyc", 0x7ffffb78,    0xffffffff, CELL,           { 0 }},
3786 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
3787 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
3788 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
3789 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
3790
3791 { "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
3792 { "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
3793 { "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
3794 { "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
3795 { "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
3796 { "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
3797 { "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
3798 { "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
3799 { "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
3800 { "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
3801 { "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
3802 { "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
3803 { "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
3804 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
3805 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
3806 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
3807 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
3808 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
3809 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
3810 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
3811 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
3812 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
3813 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
3814 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
3815 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
3816 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
3817 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
3818 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
3819 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
3820 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
3821 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
3822 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
3823 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
3824 { "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
3825 { "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
3826
3827 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3828 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
3829
3830 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3831 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3832 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
3833 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
3834
3835 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
3836 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
3837
3838 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
3839 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
3840 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
3841 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
3842
3843 { "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
3844 { "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
3845 { "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
3846 { "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
3847 { "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
3848 { "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
3849 { "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
3850 { "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
3851 { "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
3852 { "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
3853 { "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
3854 { "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
3855 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
3856 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
3857 { "mtcfar",    XSPR(31,467,28),   XSPR_MASK, POWER6,    { RS } },
3858 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
3859 { "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
3860 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
3861 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
3862 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
3863 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
3864 { "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
3865 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
3866 { "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
3867 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
3868 { "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
3869 { "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
3870 { "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
3871 { "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
3872 { "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
3873 { "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
3874 { "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
3875 { "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
3876 { "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
3877 { "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
3878 { "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
3879 { "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
3880 { "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
3881 { "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
3882 { "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
3883 { "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
3884 { "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
3885 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
3886 { "mtsprg",    XSPR(31,467,256),  XSPRG_MASK,PPC,       { SPRG, RS } },
3887 { "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
3888 { "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
3889 { "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
3890 { "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
3891 { "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3892 { "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3893 { "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3894 { "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
3895 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
3896 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
3897 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
3898 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
3899 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
3900 { "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
3901 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
3902 { "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
3903 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
3904 { "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
3905 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
3906 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
3907 { "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
3908 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
3909 { "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
3910 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
3911 { "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
3912 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
3913 { "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
3914 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
3915 { "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
3916 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
3917 { "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
3918 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
3919 { "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
3920 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
3921 { "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
3922 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
3923 { "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
3924 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
3925 { "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
3926 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
3927 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
3928 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
3929 { "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
3930 { "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
3931 { "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
3932 { "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
3933 { "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
3934 { "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
3935 { "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
3936 { "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
3937 { "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
3938 { "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
3939 { "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
3940 { "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
3941 { "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
3942 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
3943 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
3944 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
3945 { "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,    { RS } },
3946 { "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,    { RS } },
3947 { "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,    { RS } },
3948 { "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,    { RS } },
3949 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3950 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3951 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3952 { "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
3953 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
3954 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
3955 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
3956 { "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
3957 { "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
3958 { "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
3959 { "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
3960 { "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
3961 { "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
3962 { "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
3963 { "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
3964 { "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
3965 { "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
3966 { "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
3967 { "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
3968 { "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
3969 { "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
3970 { "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
3971 { "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
3972 { "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
3973 { "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
3974 { "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
3975 { "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
3976 { "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
3977 { "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
3978 { "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
3979 { "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
3980 { "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
3981 { "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
3982 { "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
3983 { "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
3984 { "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
3985 { "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
3986 { "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
3987 { "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
3988 { "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
3989 { "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
3990 { "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
3991 { "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
3992 { "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
3993 { "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
3994 { "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
3995 { "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
3996
3997 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
3998
3999 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
4000 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
4001
4002 { "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
4003
4004 { "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
4005
4006 { "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
4007
4008 { "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
4009
4010 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
4011 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4012 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
4013 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
4014 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
4015 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
4016
4017 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4018 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4019 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
4020 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
4021
4022 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
4023 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
4024
4025 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
4026 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
4027 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
4028 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
4029
4030 { "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
4031
4032 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
4033
4034 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
4035
4036 { "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
4037
4038 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
4039
4040 { "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
4041 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
4042
4043 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
4044
4045 { "ldbrx",   X(31,532), X_MASK,         CELL,           { RT, RA0, RB } },
4046
4047 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4048 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
4049
4050 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA0, RB } },
4051 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
4052
4053 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA0, RB } },
4054
4055 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4056 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4057 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4058 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4059
4060 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
4061 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
4062
4063 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
4064 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
4065
4066 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
4067 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
4068
4069 { "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4070
4071 { "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4072
4073 { "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
4074
4075 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
4076
4077 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
4078
4079 { "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4080
4081 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
4082
4083 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA0, NB } },
4084 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA0, NB } },
4085
4086 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
4087 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
4088 { "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
4089 { "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
4090 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
4091
4092 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA0, RB } },
4093
4094 { "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA0, RB } },
4095
4096 { "mffgpr",  XRC(31,607,0), XRA_MASK,   POWER6,         { FRT, RB } },
4097
4098 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
4099
4100 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
4101
4102 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
4103
4104 { "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
4105
4106 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
4107
4108 { "stdbrx",  X(31,660), X_MASK,         CELL,           { RS, RA0, RB } },
4109
4110 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4111 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4112
4113 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA0, RB } },
4114 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA0, RB } },
4115
4116 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA0, RB } },
4117
4118 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
4119 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
4120
4121 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
4122 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
4123
4124 { "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4125
4126 { "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4127
4128 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
4129
4130 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
4131 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
4132
4133 { "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4134
4135 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA0, NB } },
4136 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA0, NB } },
4137
4138 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA0, RB } },
4139
4140 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
4141 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
4142
4143 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
4144 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
4145
4146 { "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4147
4148 { "mftgpr",  XRC(31,735,0), XRA_MASK,   POWER6,         { RT, FRB } },
4149
4150 { "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
4151
4152 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
4153
4154 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
4155 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
4156
4157 { "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
4158
4159 { "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
4160
4161 { "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
4162 { "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
4163
4164 { "lwzcix",  X(31,789), X_MASK,         POWER6,         { RT, RA0, RB } },
4165
4166 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA0, RB } },
4167
4168 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
4169 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
4170 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
4171 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
4172
4173 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
4174 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
4175
4176 { "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4177
4178 { "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4179 { "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA0, RB } },
4180
4181 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
4182
4183 { "lhzcix",  X(31,821), X_MASK,         POWER6,         { RT, RA0, RB } },
4184
4185 { "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
4186 { "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
4187
4188 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
4189 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
4190 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
4191 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
4192
4193 { "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
4194
4195 { "lbzcix",  X(31,853), X_MASK,         POWER6,         { RT, RA0, RB } },
4196
4197 { "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
4198 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
4199
4200 { "lfiwax",  X(31,855), X_MASK,         POWER6,         { FRT, RA0, RB } },
4201
4202 { "ldcix",   X(31,885), X_MASK,         POWER6,         { RT, RA0, RB } },
4203
4204 { "tlbsx",   XRC(31,914,0), X_MASK,     PPC403|BOOKE,   { RTO, RA, RB } },
4205 { "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403|BOOKE,   { RTO, RA, RB } },
4206 { "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RTO, RA, RB } },
4207 { "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RTO, RA, RB } },
4208
4209 { "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
4210
4211 { "stwcix",  X(31,917), X_MASK,         POWER6,         { RS, RA0, RB } },
4212
4213 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA0, RB } },
4214
4215 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
4216 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
4217
4218 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
4219 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
4220
4221 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
4222 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
4223 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
4224 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
4225
4226 { "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4227
4228 { "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA0, RB } },
4229
4230 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
4231 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
4232 { "tlbre",   X(31,946), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4233
4234 { "sthcix",  X(31,949), X_MASK,         POWER6,         { RS, RA0, RB } },
4235
4236 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
4237 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
4238
4239 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
4240 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
4241
4242 { "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
4243
4244 { "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4245
4246 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
4247 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
4248 { "tlbwe",   X(31,978), X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
4249 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
4250
4251 { "stbcix",  X(31,981), X_MASK,         POWER6,         { RS, RA0, RB } },
4252
4253 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
4254
4255 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA0, RB } },
4256
4257 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
4258 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
4259
4260 { "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
4261
4262 { "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
4263 { "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA0, RB } },
4264
4265 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
4266
4267 { "stdcix",  X(31,1013), X_MASK,        POWER6,         { RS, RA0, RB } },
4268
4269 { "dcbzl",   XOPL(31,1014,1), XRT_MASK,POWER4,            { RA, RB } },
4270 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4271 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
4272
4273 { "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
4274
4275 { "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
4276 { "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
4277 { "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
4278 { "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
4279 { "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
4280 { "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
4281 { "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
4282 { "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
4283 { "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
4284 { "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
4285 { "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
4286 { "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
4287
4288 /* New load/store left/right index vector instructions that are in the Cell only.  */
4289 { "lvlx",    X(31, 519), X_MASK,        CELL,           { VD, RA0, RB } },
4290 { "lvlxl",   X(31, 775), X_MASK,        CELL,           { VD, RA0, RB } },
4291 { "lvrx",    X(31, 551), X_MASK,        CELL,           { VD, RA0, RB } },
4292 { "lvrxl",   X(31, 807), X_MASK,        CELL,           { VD, RA0, RB } },
4293 { "stvlx",   X(31, 647), X_MASK,        CELL,           { VS, RA0, RB } },
4294 { "stvlxl",  X(31, 903), X_MASK,        CELL,           { VS, RA0, RB } },
4295 { "stvrx",   X(31, 679), X_MASK,        CELL,           { VS, RA0, RB } },
4296 { "stvrxl",  X(31, 935), X_MASK,        CELL,           { VS, RA0, RB } },
4297
4298 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },
4299 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4300
4301 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
4302 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4303
4304 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA0 } },
4305
4306 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
4307
4308 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4309 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4310
4311 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
4312 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4313
4314 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA0 } },
4315
4316 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
4317
4318 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA0 } },
4319
4320 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
4321
4322 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA0 } },
4323
4324 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
4325
4326 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA0 } },
4327
4328 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
4329
4330 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
4331 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
4332
4333 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA0 } },
4334 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA0 } },
4335
4336 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA0 } },
4337
4338 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
4339
4340 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA0 } },
4341
4342 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
4343
4344 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA0 } },
4345
4346 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
4347
4348 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA0 } },
4349
4350 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
4351
4352 { "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
4353
4354 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4355
4356 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA0 } },
4357
4358 { "lfdp",    OP(57),    OP_MASK,        POWER6,         { FRT, D, RA0 } },
4359
4360 { "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4361 { "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4362 { "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4363 { "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4364 { "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4365 { "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4366 { "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA0 } },
4367 { "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
4368 { "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA0 } },
4369 { "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
4370 { "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4371 { "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4372 { "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },
4373 { "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
4374
4375 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4376
4377 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
4378
4379 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA0 } },
4380
4381 { "dadd",    XRC(59,2,0), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4382 { "dadd.",   XRC(59,2,1), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4383
4384 { "dqua",    ZRC(59,3,0), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4385 { "dqua.",   ZRC(59,3,1), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4386
4387 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4388 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4389
4390 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4391 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4392
4393 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4394 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
4395
4396 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4397 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
4398
4399 { "fres",    A(59,24,0), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4400 { "fres.",   A(59,24,1), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4401
4402 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4403 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
4404
4405 { "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5,         { FRT, FRB, A_L } },
4406 { "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5,         { FRT, FRB, A_L } },
4407
4408 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4409 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4410
4411 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4412 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4413
4414 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4415 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4416
4417 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4418 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4419
4420 { "dmul",    XRC(59,34,0), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4421 { "dmul.",   XRC(59,34,1), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4422
4423 { "drrnd",   ZRC(59,35,0), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4424 { "drrnd.",  ZRC(59,35,1), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4425
4426 { "dscli",   ZRC(59,66,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4427 { "dscli.",  ZRC(59,66,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4428
4429 { "dquai",   ZRC(59,67,0), Z2_MASK,     POWER6,         { TE,  FRT, FRB, RMC } },
4430 { "dquai.",  ZRC(59,67,1), Z2_MASK,     POWER6,         { TE,  FRT, FRB, RMC } },
4431
4432 { "dscri",   ZRC(59,98,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4433 { "dscri.",  ZRC(59,98,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4434
4435 { "drintx",  ZRC(59,99,0), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4436 { "drintx.", ZRC(59,99,1), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4437
4438 { "dcmpo",   X(59,130),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4439
4440 { "dtstex",  X(59,162),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4441 { "dtstdc",  Z(59,194),    Z_MASK,      POWER6,         { BF,  FRA, DCM } },
4442 { "dtstdg",  Z(59,226),    Z_MASK,      POWER6,         { BF,  FRA, DGM } },
4443
4444 { "drintn",  ZRC(59,227,0), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4445 { "drintn.", ZRC(59,227,1), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4446
4447 { "dctdp",   XRC(59,258,0), X_MASK,     POWER6,         { FRT, FRB } },
4448 { "dctdp.",  XRC(59,258,1), X_MASK,     POWER6,         { FRT, FRB } },
4449
4450 { "dctfix",  XRC(59,290,0), X_MASK,     POWER6,         { FRT, FRB } },
4451 { "dctfix.", XRC(59,290,1), X_MASK,     POWER6,         { FRT, FRB } },
4452
4453 { "ddedpd",  XRC(59,322,0), X_MASK,     POWER6,         { SP, FRT, FRB } },
4454 { "ddedpd.", XRC(59,322,1), X_MASK,     POWER6,         { SP, FRT, FRB } },
4455
4456 { "dxex",    XRC(59,354,0), X_MASK,     POWER6,         { FRT, FRB } },
4457 { "dxex.",   XRC(59,354,1), X_MASK,     POWER6,         { FRT, FRB } },
4458
4459 { "dsub",    XRC(59,514,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4460 { "dsub.",   XRC(59,514,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4461
4462 { "ddiv",    XRC(59,546,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4463 { "ddiv.",   XRC(59,546,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4464
4465 { "dcmpu",   X(59,642),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4466
4467 { "dtstsf",  X(59,674),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4468
4469 { "drsp",    XRC(59,770,0), X_MASK,     POWER6,         { FRT, FRB } },
4470 { "drsp.",   XRC(59,770,1), X_MASK,     POWER6,         { FRT, FRB } },
4471
4472 { "dcffix",  XRC(59,802,0), X_MASK,     POWER6,         { FRT, FRB } },
4473 { "dcffix.", XRC(59,802,1), X_MASK,     POWER6,         { FRT, FRB } },
4474
4475 { "denbcd",  XRC(59,834,0), X_MASK,     POWER6,         { S, FRT, FRB } },
4476 { "denbcd.", XRC(59,834,1), X_MASK,     POWER6,         { S, FRT, FRB } },
4477
4478 { "diex",    XRC(59,866,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4479 { "diex.",   XRC(59,866,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4480
4481 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
4482
4483 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
4484
4485 { "stfdp",   OP(61),    OP_MASK,        POWER6,         { FRT, D, RA0 } },
4486
4487 { "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4488 { "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA0 } },
4489 { "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4490 { "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4491 { "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA0 } },
4492 { "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
4493 { "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA0 } },
4494 { "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
4495 { "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4496 { "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4497 { "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA0 } },
4498 { "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
4499
4500 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA0 } },
4501
4502 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
4503
4504 { "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA0 } },
4505
4506 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4507
4508 { "daddq",   XRC(63,2,0), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4509 { "daddq.",  XRC(63,2,1), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4510
4511 { "dquaq",   ZRC(63,3,0), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4512 { "dquaq.",  ZRC(63,3,1), Z2_MASK,      POWER6,         { FRT, FRA, FRB, RMC } },
4513
4514 { "fcpsgn",  XRC(63,8,0), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4515 { "fcpsgn.", XRC(63,8,1), X_MASK,       POWER6,         { FRT, FRA, FRB } },
4516
4517 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
4518 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
4519
4520 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4521 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4522 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4523 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4524
4525 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4526 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
4527 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
4528 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
4529
4530 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4531 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4532 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4533 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4534
4535 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4536 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4537 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4538 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4539
4540 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4541 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4542 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
4543 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
4544
4545 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4546 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
4547
4548 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4549 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
4550
4551 { "fre",     A(63,24,0), AFRALFRC_MASK, POWER5,         { FRT, FRB, A_L } },
4552 { "fre.",    A(63,24,1), AFRALFRC_MASK, POWER5,         { FRT, FRB, A_L } },
4553
4554 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4555 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4556 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
4557 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
4558
4559 { "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4560 { "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC,            { FRT, FRB, A_L } },
4561
4562 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4563 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4564 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4565 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4566
4567 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4568 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4569 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4570 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4571
4572 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4573 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4574 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4575 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4576
4577 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4578 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4579 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
4580 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
4581
4582 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
4583
4584 { "dmulq",   XRC(63,34,0), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4585 { "dmulq.",  XRC(63,34,1), X_MASK,      POWER6,         { FRT, FRA, FRB } },
4586
4587 { "drrndq",  ZRC(63,35,0), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4588 { "drrndq.", ZRC(63,35,1), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4589
4590 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
4591 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
4592
4593 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
4594 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
4595
4596 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
4597
4598 { "dscliq",  ZRC(63,66,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4599 { "dscliq.", ZRC(63,66,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4600
4601 { "dquaiq",  ZRC(63,67,0), Z2_MASK,     POWER6,         { TE,  FRT, FRB, RMC } },
4602 { "dquaiq.", ZRC(63,67,1), Z2_MASK,     POWER6,         { FRT, FRA, FRB, RMC } },
4603
4604 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
4605 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
4606
4607 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
4608 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
4609
4610 { "dscriq",  ZRC(63,98,0), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4611 { "dscriq.", ZRC(63,98,1), Z_MASK,      POWER6,         { FRT, FRA, SH16 } },
4612
4613 { "drintxq", ZRC(63,99,0), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4614 { "drintxq.",ZRC(63,99,1), Z2_MASK,     POWER6,         { R, FRT, FRB, RMC } },
4615
4616 { "dcmpoq",  X(63,130),    X_MASK,      POWER6,         { BF,  FRA, FRB } },
4617
4618 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4619 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4620
4621 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
4622 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
4623
4624 { "dtstexq", X(63,162),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4625 { "dtstdcq", Z(63,194),     Z_MASK,     POWER6,         { BF,  FRA, DCM } },
4626 { "dtstdgq", Z(63,226),     Z_MASK,     POWER6,         { BF,  FRA, DGM } },
4627
4628 { "drintnq", ZRC(63,227,0), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4629 { "drintnq.",ZRC(63,227,1), Z2_MASK,    POWER6,         { R, FRT, FRB, RMC } },
4630
4631 { "dctqpq",  XRC(63,258,0), X_MASK,     POWER6,         { FRT, FRB } },
4632 { "dctqpq.", XRC(63,258,1), X_MASK,     POWER6,         { FRT, FRB } },
4633
4634 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
4635 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
4636
4637 { "dctfixq", XRC(63,290,0), X_MASK,     POWER6,         { FRT, FRB } },
4638 { "dctfixq.",XRC(63,290,1), X_MASK,     POWER6,         { FRT, FRB } },
4639
4640 { "ddedpdq", XRC(63,322,0), X_MASK,     POWER6,         { SP, FRT, FRB } },
4641 { "ddedpdq.",XRC(63,322,1), X_MASK,     POWER6,         { SP, FRT, FRB } },
4642
4643 { "dxexq",   XRC(63,354,0), X_MASK,     POWER6,         { FRT, FRB } },
4644 { "dxexq.",  XRC(63,354,1), X_MASK,     POWER6,         { FRT, FRB } },
4645
4646 { "frin",    XRC(63,392,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4647 { "frin.",   XRC(63,392,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4648 { "friz",    XRC(63,424,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4649 { "friz.",   XRC(63,424,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4650 { "frip",    XRC(63,456,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4651 { "frip.",   XRC(63,456,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4652 { "frim",    XRC(63,488,0), XRA_MASK,   POWER5,         { FRT, FRB } },
4653 { "frim.",   XRC(63,488,1), XRA_MASK,   POWER5,         { FRT, FRB } },
4654
4655 { "dsubq",   XRC(63,514,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4656 { "dsubq.",  XRC(63,514,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4657
4658 { "ddivq",   XRC(63,546,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4659 { "ddivq.",  XRC(63,546,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4660
4661 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
4662 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
4663
4664 { "dcmpuq",  X(63,642),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4665
4666 { "dtstsfq", X(63,674),     X_MASK,     POWER6,         { BF,  FRA, FRB } },
4667
4668 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
4669 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
4670
4671 { "drdpq",   XRC(63,770,0), X_MASK,     POWER6,         { FRT, FRB } },
4672 { "drdpq.",  XRC(63,770,1), X_MASK,     POWER6,         { FRT, FRB } },
4673
4674 { "dcffixq", XRC(63,802,0), X_MASK,     POWER6,         { FRT, FRB } },
4675 { "dcffixq.",XRC(63,802,1), X_MASK,     POWER6,         { FRT, FRB } },
4676
4677 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4678 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4679
4680 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4681 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4682
4683 { "denbcdq", XRC(63,834,0), X_MASK,     POWER6,         { S, FRT, FRB } },
4684 { "denbcdq.",XRC(63,834,1), X_MASK,     POWER6,         { S, FRT, FRB } },
4685
4686 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
4687 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
4688
4689 { "diexq",   XRC(63,866,0), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4690 { "diexq.",  XRC(63,866,1), X_MASK,     POWER6,         { FRT, FRA, FRB } },
4691
4692 };
4693
4694 const int powerpc_num_opcodes =
4695   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4696 \f
4697 /* The macro table.  This is only used by the assembler.  */
4698
4699 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4700    when x=0; 32-x when x is between 1 and 31; are negative if x is
4701    negative; and are 32 or more otherwise.  This is what you want
4702    when, for instance, you are emulating a right shift by a
4703    rotate-left-and-mask, because the underlying instructions support
4704    shifts of size 0 but not shifts of size 32.  By comparison, when
4705    extracting x bits from some word you want to use just 32-x, because
4706    the underlying instructions don't support extracting 0 bits but do
4707    support extracting the whole word (32 bits in this case).  */
4708
4709 const struct powerpc_macro powerpc_macros[] = {
4710 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
4711 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
4712 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4713 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4714 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
4715 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4716 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4717 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4718 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
4719 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
4720 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4721 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4722 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
4723 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
4724 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
4725 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
4726
4727 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
4728 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
4729 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4730 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4731 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4732 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4733 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4734 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4735 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4736 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4737 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
4738 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
4739 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
4740 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
4741 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4742 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4743 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4744 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4745 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
4746 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
4747 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4748 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4749 };
4750
4751 const int powerpc_num_macros =
4752   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);